1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * NXP NETC switch driver 4 * Copyright 2025-2026 NXP 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/etherdevice.h> 9 #include <linux/fsl/enetc_mdio.h> 10 #include <linux/if_bridge.h> 11 #include <linux/if_vlan.h> 12 #include <linux/of_mdio.h> 13 14 #include "netc_switch.h" 15 16 static struct netc_fdb_entry * 17 netc_lookup_fdb_entry(struct netc_switch *priv, 18 const unsigned char *addr, 19 u16 vid) 20 { 21 struct netc_fdb_entry *entry; 22 23 hlist_for_each_entry(entry, &priv->fdb_list, node) 24 if (ether_addr_equal(entry->keye.mac_addr, addr) && 25 le16_to_cpu(entry->keye.fid) == vid) 26 return entry; 27 28 return NULL; 29 } 30 31 static void netc_destroy_fdb_list(struct netc_switch *priv) 32 { 33 struct netc_fdb_entry *entry; 34 struct hlist_node *tmp; 35 36 hlist_for_each_entry_safe(entry, tmp, &priv->fdb_list, node) 37 netc_del_fdb_entry(entry); 38 } 39 40 static enum dsa_tag_protocol 41 netc_get_tag_protocol(struct dsa_switch *ds, int port, 42 enum dsa_tag_protocol mprot) 43 { 44 return DSA_TAG_PROTO_NETC; 45 } 46 47 static void netc_port_rmw(struct netc_port *np, u32 reg, 48 u32 mask, u32 val) 49 { 50 u32 old, new; 51 52 WARN_ON((mask | val) != mask); 53 54 old = netc_port_rd(np, reg); 55 new = (old & ~mask) | val; 56 if (new == old) 57 return; 58 59 netc_port_wr(np, reg, new); 60 } 61 62 static void netc_mac_port_wr(struct netc_port *np, u32 reg, u32 val) 63 { 64 if (is_netc_pseudo_port(np)) 65 return; 66 67 netc_port_wr(np, reg, val); 68 if (np->caps.pmac) 69 netc_port_wr(np, reg + NETC_PMAC_OFFSET, val); 70 } 71 72 /* netc_mac_port_rmw() is used to synchronize the configurations of eMAC 73 * and pMAC to maintain consistency. This function should not be used if 74 * differentiated settings are required. 75 */ 76 static void netc_mac_port_rmw(struct netc_port *np, u32 reg, 77 u32 mask, u32 val) 78 { 79 u32 old, new; 80 81 if (is_netc_pseudo_port(np)) 82 return; 83 84 WARN_ON((mask | val) != mask); 85 86 old = netc_port_rd(np, reg); 87 new = (old & ~mask) | val; 88 if (new == old) 89 return; 90 91 netc_port_wr(np, reg, new); 92 if (np->caps.pmac) 93 netc_port_wr(np, reg + NETC_PMAC_OFFSET, new); 94 } 95 96 static void netc_port_get_capability(struct netc_port *np) 97 { 98 u32 val; 99 100 val = netc_port_rd(np, NETC_PMCAPR); 101 if (val & PMCAPR_HD) 102 np->caps.half_duplex = true; 103 104 if (FIELD_GET(PMCAPR_FP, val) == FP_SUPPORT) 105 np->caps.pmac = true; 106 107 val = netc_port_rd(np, NETC_PCAPR); 108 if (val & PCAPR_LINK_TYPE) 109 np->caps.pseudo_link = true; 110 } 111 112 static int netc_port_get_info_from_dt(struct netc_port *np, 113 struct device_node *node, 114 struct device *dev) 115 { 116 if (of_find_property(node, "clock-names", NULL)) { 117 np->ref_clk = devm_get_clk_from_child(dev, node, "ref"); 118 if (IS_ERR(np->ref_clk)) { 119 dev_err(dev, "Port %d cannot get reference clock\n", 120 np->dp->index); 121 return PTR_ERR(np->ref_clk); 122 } 123 } 124 125 return 0; 126 } 127 128 static int netc_port_create_emdio_bus(struct netc_port *np, 129 struct device_node *node) 130 { 131 struct netc_switch *priv = np->switch_priv; 132 struct enetc_mdio_priv *mdio_priv; 133 struct device *dev = priv->dev; 134 struct enetc_hw *hw; 135 struct mii_bus *bus; 136 int err; 137 138 hw = enetc_hw_alloc(dev, np->iobase); 139 if (IS_ERR(hw)) 140 return dev_err_probe(dev, PTR_ERR(hw), 141 "Failed to allocate enetc_hw\n"); 142 143 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 144 if (!bus) 145 return -ENOMEM; 146 147 bus->name = "NXP NETC switch external MDIO Bus"; 148 bus->read = enetc_mdio_read_c22; 149 bus->write = enetc_mdio_write_c22; 150 bus->read_c45 = enetc_mdio_read_c45; 151 bus->write_c45 = enetc_mdio_write_c45; 152 bus->parent = dev; 153 mdio_priv = bus->priv; 154 mdio_priv->hw = hw; 155 mdio_priv->mdio_base = NETC_EMDIO_BASE; 156 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-p%d-emdio", 157 dev_name(dev), np->dp->index); 158 159 err = devm_of_mdiobus_register(dev, bus, node); 160 if (err) 161 return dev_err_probe(dev, err, 162 "Cannot register EMDIO bus\n"); 163 164 np->emdio = bus; 165 166 return 0; 167 } 168 169 static int netc_port_create_mdio_bus(struct netc_port *np, 170 struct device_node *node) 171 { 172 struct device_node *mdio_node; 173 int err; 174 175 mdio_node = of_get_child_by_name(node, "mdio"); 176 if (mdio_node) { 177 err = netc_port_create_emdio_bus(np, mdio_node); 178 of_node_put(mdio_node); 179 if (err) 180 return err; 181 } 182 183 return 0; 184 } 185 186 static int netc_init_switch_id(struct netc_switch *priv) 187 { 188 struct netc_switch_regs *regs = &priv->regs; 189 struct dsa_switch *ds = priv->ds; 190 191 /* The value of 0 is reserved for the VEPA switch and cannot 192 * be used. So 'dsa,member' is a required property for NETC 193 * switch, the member is used to specify the switch ID, which 194 * cannot be zero. This way, the hardware switch ID and the 195 * software switch ID are consistent. 196 */ 197 if (ds->index > FIELD_MAX(SWCR_SWID) || !ds->index) { 198 dev_err(priv->dev, "Switch index %d out of range\n", 199 ds->index); 200 return -ERANGE; 201 } 202 203 netc_base_wr(regs, NETC_SWCR, ds->index); 204 205 return 0; 206 } 207 208 static void netc_get_switch_capabilities(struct netc_switch *priv) 209 { 210 struct netc_switch_regs *regs = &priv->regs; 211 u32 val; 212 213 val = netc_base_rd(regs, NETC_HTMCAPR); 214 priv->htmcapr_num_words = FIELD_GET(HTMCAPR_NUM_WORDS, val); 215 216 val = netc_base_rd(regs, NETC_BPCAPR); 217 priv->num_bp = FIELD_GET(BPCAPR_NUM_BP, val); 218 } 219 220 static int netc_init_all_ports(struct netc_switch *priv) 221 { 222 struct device *dev = priv->dev; 223 struct netc_port *np; 224 struct dsa_port *dp; 225 int err; 226 227 priv->ports = devm_kcalloc(dev, priv->info->num_ports, 228 sizeof(struct netc_port *), 229 GFP_KERNEL); 230 if (!priv->ports) 231 return -ENOMEM; 232 233 /* Some DSA interfaces may set the port even it is disabled, such 234 * as .port_disable(), .port_stp_state_set() and so on. To avoid 235 * crash caused by accessing NULL port pointer, each port is 236 * allocated its own memory. Otherwise, we need to check whether 237 * the port pointer is NULL in these interfaces. The latter is 238 * difficult for us to cover. 239 */ 240 for (int i = 0; i < priv->info->num_ports; i++) { 241 np = devm_kzalloc(dev, sizeof(*np), GFP_KERNEL); 242 if (!np) 243 return -ENOMEM; 244 245 np->switch_priv = priv; 246 np->iobase = priv->regs.port + PORT_IOBASE(i); 247 netc_port_get_capability(np); 248 priv->ports[i] = np; 249 } 250 251 dsa_switch_for_each_available_port(dp, priv->ds) { 252 np = priv->ports[dp->index]; 253 np->dp = dp; 254 255 err = netc_port_get_info_from_dt(np, dp->dn, dev); 256 if (err) 257 return err; 258 259 if (dsa_port_is_user(dp)) { 260 err = netc_port_create_mdio_bus(np, dp->dn); 261 if (err) { 262 dev_err(dev, "Failed to create MDIO bus\n"); 263 return err; 264 } 265 } 266 } 267 268 return 0; 269 } 270 271 static void netc_init_ntmp_tbl_versions(struct netc_switch *priv) 272 { 273 struct ntmp_user *ntmp = &priv->ntmp; 274 275 /* All tables default to version 0 */ 276 memset(&ntmp->tbl, 0, sizeof(ntmp->tbl)); 277 } 278 279 static int netc_init_all_cbdrs(struct netc_switch *priv) 280 { 281 struct netc_switch_regs *regs = &priv->regs; 282 struct ntmp_user *ntmp = &priv->ntmp; 283 int i, err; 284 285 ntmp->cbdr_num = NETC_CBDR_NUM; 286 ntmp->dev = priv->dev; 287 ntmp->ring = devm_kcalloc(ntmp->dev, ntmp->cbdr_num, 288 sizeof(struct netc_cbdr), 289 GFP_KERNEL); 290 if (!ntmp->ring) 291 return -ENOMEM; 292 293 for (i = 0; i < ntmp->cbdr_num; i++) { 294 struct netc_cbdr *cbdr = &ntmp->ring[i]; 295 struct netc_cbdr_regs cbdr_regs; 296 297 cbdr_regs.pir = regs->base + NETC_CBDRPIR(i); 298 cbdr_regs.cir = regs->base + NETC_CBDRCIR(i); 299 cbdr_regs.mr = regs->base + NETC_CBDRMR(i); 300 cbdr_regs.bar0 = regs->base + NETC_CBDRBAR0(i); 301 cbdr_regs.bar1 = regs->base + NETC_CBDRBAR1(i); 302 cbdr_regs.lenr = regs->base + NETC_CBDRLENR(i); 303 304 err = ntmp_init_cbdr(cbdr, ntmp->dev, &cbdr_regs); 305 if (err) 306 goto free_cbdrs; 307 } 308 309 return 0; 310 311 free_cbdrs: 312 for (i--; i >= 0; i--) 313 ntmp_free_cbdr(&ntmp->ring[i]); 314 315 return err; 316 } 317 318 static void netc_remove_all_cbdrs(struct netc_switch *priv) 319 { 320 struct ntmp_user *ntmp = &priv->ntmp; 321 322 for (int i = 0; i < NETC_CBDR_NUM; i++) 323 ntmp_free_cbdr(&ntmp->ring[i]); 324 } 325 326 static int netc_init_ntmp_user(struct netc_switch *priv) 327 { 328 netc_init_ntmp_tbl_versions(priv); 329 330 return netc_init_all_cbdrs(priv); 331 } 332 333 static void netc_free_ntmp_user(struct netc_switch *priv) 334 { 335 netc_remove_all_cbdrs(priv); 336 } 337 338 static void netc_switch_dos_default_config(struct netc_switch *priv) 339 { 340 struct netc_switch_regs *regs = &priv->regs; 341 u32 val; 342 343 val = DOSL2CR_SAMEADDR | DOSL2CR_MSAMCC; 344 netc_base_wr(regs, NETC_DOSL2CR, val); 345 346 val = DOSL3CR_SAMEADDR | DOSL3CR_IPSAMCC; 347 netc_base_wr(regs, NETC_DOSL3CR, val); 348 } 349 350 static void netc_switch_vfht_default_config(struct netc_switch *priv) 351 { 352 struct netc_switch_regs *regs = &priv->regs; 353 u32 val; 354 355 val = netc_base_rd(regs, NETC_VFHTDECR2); 356 357 /* If no match is found in the VLAN Filter table, then VFHTDECR2[MLO] 358 * will take effect. VFHTDECR2[MLO] is set to "Software MAC learning 359 * secure" by default. Notice BPCR[MLO] will override VFHTDECR2[MLO] 360 * if its value is not zero. 361 */ 362 val = u32_replace_bits(val, MLO_SW_SEC, VFHTDECR2_MLO); 363 val = u32_replace_bits(val, MFO_NO_MATCH_DISCARD, VFHTDECR2_MFO); 364 netc_base_wr(regs, NETC_VFHTDECR2, val); 365 } 366 367 static void netc_port_set_max_frame_size(struct netc_port *np, 368 u32 max_frame_size) 369 { 370 netc_mac_port_wr(np, NETC_PM_MAXFRM(0), 371 max_frame_size & PM_MAXFRAM); 372 } 373 374 static void netc_switch_fixed_config(struct netc_switch *priv) 375 { 376 netc_switch_dos_default_config(priv); 377 netc_switch_vfht_default_config(priv); 378 } 379 380 static void netc_port_set_tc_max_sdu(struct netc_port *np, 381 int tc, u32 max_sdu) 382 { 383 u32 val = FIELD_PREP(PTCTMSDUR_MAXSDU, max_sdu) | 384 FIELD_PREP(PTCTMSDUR_SDU_TYPE, SDU_TYPE_MPDU); 385 386 netc_port_wr(np, NETC_PTCTMSDUR(tc), val); 387 } 388 389 static void netc_port_set_all_tc_msdu(struct netc_port *np) 390 { 391 for (int tc = 0; tc < NETC_TC_NUM; tc++) 392 netc_port_set_tc_max_sdu(np, tc, NETC_MAX_FRAME_LEN); 393 } 394 395 static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo) 396 { 397 netc_port_rmw(np, NETC_BPCR, BPCR_MLO, FIELD_PREP(BPCR_MLO, mlo)); 398 } 399 400 static void netc_port_fixed_config(struct netc_port *np) 401 { 402 /* Default IPV and DR setting */ 403 netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE, 404 PQOSMR_VS | PQOSMR_VE); 405 406 /* Enable L2 and L3 DOS */ 407 netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE, 408 PCR_L2DOSE | PCR_L3DOSE); 409 410 /* Set the quanta value of TX PAUSE frame */ 411 netc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), NETC_PAUSE_QUANTA); 412 413 /* When a quanta timer counts down and reaches this value, 414 * the MAC sends a refresh PAUSE frame with the programmed 415 * full quanta value if a pause condition still exists. 416 */ 417 netc_mac_port_wr(np, NETC_PM_PAUSE_THRESH(0), NETC_PAUSE_THRESH); 418 } 419 420 static void netc_port_default_config(struct netc_port *np) 421 { 422 netc_port_fixed_config(np); 423 424 /* Default VLAN unaware */ 425 netc_port_rmw(np, NETC_BPDVR, BPDVR_RXVAM, BPDVR_RXVAM); 426 427 if (dsa_port_is_cpu(np->dp)) 428 /* For CPU port, source port pruning is disabled */ 429 netc_port_rmw(np, NETC_BPCR, BPCR_SRCPRND, BPCR_SRCPRND); 430 else 431 netc_port_set_mlo(np, MLO_DISABLE); 432 433 netc_port_set_max_frame_size(np, NETC_MAX_FRAME_LEN); 434 netc_port_set_all_tc_msdu(np); 435 } 436 437 static u32 netc_available_port_bitmap(struct netc_switch *priv) 438 { 439 struct dsa_port *dp; 440 u32 bitmap = 0; 441 442 dsa_switch_for_each_available_port(dp, priv->ds) 443 bitmap |= BIT(dp->index); 444 445 return bitmap; 446 } 447 448 static int netc_add_standalone_vlan_entry(struct netc_switch *priv) 449 { 450 u32 bitmap_stg = VFT_STG_ID(0) | netc_available_port_bitmap(priv); 451 struct vft_cfge_data *cfge; 452 u16 cfg; 453 int err; 454 455 cfge = kzalloc_obj(*cfge); 456 if (!cfge) 457 return -ENOMEM; 458 459 cfge->bitmap_stg = cpu_to_le32(bitmap_stg); 460 cfge->et_eid = cpu_to_le32(NTMP_NULL_ENTRY_ID); 461 cfge->fid = cpu_to_le16(NETC_STANDALONE_PVID); 462 463 /* For standalone ports, MAC learning needs to be disabled, so frames 464 * from other user ports will not be forwarded to the standalone ports, 465 * because there are no FDB entries on the standalone ports. Also, the 466 * frames received by the standalone ports cannot be flooded to other 467 * ports, so MAC forwarding option needs to be set to 468 * MFO_NO_MATCH_DISCARD, so the frames will be discarded rather than 469 * flooding to other ports. 470 */ 471 cfg = FIELD_PREP(VFT_MLO, MLO_DISABLE) | 472 FIELD_PREP(VFT_MFO, MFO_NO_MATCH_DISCARD); 473 cfge->cfg = cpu_to_le16(cfg); 474 475 err = ntmp_vft_add_entry(&priv->ntmp, NETC_STANDALONE_PVID, cfge); 476 if (err) 477 dev_err(priv->dev, 478 "Failed to add standalone VLAN entry\n"); 479 480 kfree(cfge); 481 482 return err; 483 } 484 485 static int netc_port_add_fdb_entry(struct netc_port *np, 486 const unsigned char *addr, u16 vid) 487 { 488 struct netc_switch *priv = np->switch_priv; 489 struct netc_fdb_entry *entry; 490 struct fdbt_keye_data *keye; 491 struct fdbt_cfge_data *cfge; 492 int port = np->dp->index; 493 u32 cfg = 0; 494 int err; 495 496 entry = kzalloc_obj(*entry); 497 if (!entry) 498 return -ENOMEM; 499 500 keye = &entry->keye; 501 cfge = &entry->cfge; 502 ether_addr_copy(keye->mac_addr, addr); 503 keye->fid = cpu_to_le16(vid); 504 505 cfge->port_bitmap = cpu_to_le32(BIT(port)); 506 cfge->cfg = cpu_to_le32(cfg); 507 cfge->et_eid = cpu_to_le32(NTMP_NULL_ENTRY_ID); 508 509 err = ntmp_fdbt_add_entry(&priv->ntmp, &entry->entry_id, keye, cfge); 510 if (err) { 511 kfree(entry); 512 513 return err; 514 } 515 516 netc_add_fdb_entry(priv, entry); 517 518 return 0; 519 } 520 521 static int netc_port_set_fdb_entry(struct netc_port *np, 522 const unsigned char *addr, u16 vid) 523 { 524 struct netc_switch *priv = np->switch_priv; 525 struct netc_fdb_entry *entry; 526 struct fdbt_cfge_data *cfge; 527 int port = np->dp->index; 528 __le32 old_port_bitmap; 529 int err = 0; 530 531 mutex_lock(&priv->fdbt_lock); 532 533 entry = netc_lookup_fdb_entry(priv, addr, vid); 534 if (!entry) { 535 err = netc_port_add_fdb_entry(np, addr, vid); 536 if (err) 537 dev_err(priv->dev, 538 "Failed to add FDB entry on port %d\n", 539 port); 540 541 goto unlock_fdbt; 542 } 543 544 cfge = &entry->cfge; 545 /* If the entry already exists on the port, return 0 directly */ 546 if (unlikely(cfge->port_bitmap & cpu_to_le32(BIT(port)))) 547 goto unlock_fdbt; 548 549 /* If the entry already exists, but not on this port, we need to 550 * update the port bitmap. In general, it should only be valid 551 * for multicast or broadcast address. 552 */ 553 old_port_bitmap = cfge->port_bitmap; 554 if (is_multicast_ether_addr(addr)) 555 cfge->port_bitmap |= cpu_to_le32(BIT(port)); 556 else 557 cfge->port_bitmap = cpu_to_le32(BIT(port)); 558 559 err = ntmp_fdbt_update_entry(&priv->ntmp, entry->entry_id, cfge); 560 if (err) { 561 cfge->port_bitmap = old_port_bitmap; 562 dev_err(priv->dev, "Failed to set FDB entry on port %d\n", 563 port); 564 } 565 566 unlock_fdbt: 567 mutex_unlock(&priv->fdbt_lock); 568 569 return err; 570 } 571 572 static int netc_port_del_fdb_entry(struct netc_port *np, 573 const unsigned char *addr, u16 vid) 574 { 575 struct netc_switch *priv = np->switch_priv; 576 struct ntmp_user *ntmp = &priv->ntmp; 577 struct netc_fdb_entry *entry; 578 struct fdbt_cfge_data *cfge; 579 int port = np->dp->index; 580 int err = 0; 581 582 mutex_lock(&priv->fdbt_lock); 583 584 entry = netc_lookup_fdb_entry(priv, addr, vid); 585 if (unlikely(!entry)) 586 /* Currently only single port mode is supported, MAC learning 587 * is disabled, so there is no dynamically learned FDB entry. 588 * We need to support deleting dynamically FDB entry when the 589 * bridge mode is supported. 590 */ 591 goto unlock_fdbt; 592 593 cfge = &entry->cfge; 594 if (unlikely(!(cfge->port_bitmap & cpu_to_le32(BIT(port))))) 595 goto unlock_fdbt; 596 597 if (cfge->port_bitmap != cpu_to_le32(BIT(port))) { 598 /* If the entry also exists on other ports, we need to 599 * update the entry in the FDB table. 600 */ 601 cfge->port_bitmap &= cpu_to_le32(~BIT(port)); 602 err = ntmp_fdbt_update_entry(ntmp, entry->entry_id, cfge); 603 if (err) { 604 cfge->port_bitmap |= cpu_to_le32(BIT(port)); 605 goto unlock_fdbt; 606 } 607 } else { 608 /* If the entry only exists on this port, just delete 609 * it from the FDB table. 610 */ 611 err = ntmp_fdbt_delete_entry(ntmp, entry->entry_id); 612 if (err) 613 goto unlock_fdbt; 614 615 netc_del_fdb_entry(entry); 616 } 617 618 unlock_fdbt: 619 mutex_unlock(&priv->fdbt_lock); 620 621 return err; 622 } 623 624 static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv) 625 { 626 const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 627 struct dsa_port *dp, *cpu_dp = NULL; 628 629 dsa_switch_for_each_cpu_port(dp, priv->ds) { 630 /* The switch has only one CPU port, so only need to find 631 * the first CPU port to break out of the loop. 632 */ 633 cpu_dp = dp; 634 break; 635 } 636 637 if (!cpu_dp) 638 return -ENODEV; 639 640 /* If the user port acts as a standalone port, then its PVID is 0, 641 * MLO is set to "disable MAC learning" and MFO is set to "discard 642 * frames if no matching entry found in FDB table". Therefore, we 643 * need to add a broadcast FDB entry on the CPU port so that the 644 * broadcast frames received on the user port can be forwarded to 645 * the CPU port. 646 */ 647 return netc_port_set_fdb_entry(NETC_PORT(priv->ds, cpu_dp->index), 648 bcast, NETC_STANDALONE_PVID); 649 } 650 651 static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping) 652 { 653 u32 pbpmcr0 = lower_32_bits(mapping); 654 u32 pbpmcr1 = upper_32_bits(mapping); 655 656 netc_port_wr(np, NETC_PBPMCR0, pbpmcr0); 657 netc_port_wr(np, NETC_PBPMCR1, pbpmcr1); 658 } 659 660 static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv) 661 { 662 int bp_per_port = priv->num_bp / priv->info->num_ports; 663 int q = NETC_IPV_NUM / bp_per_port; 664 int r = NETC_IPV_NUM % bp_per_port; 665 int num = q + r; 666 667 /* IPV-to-buffer-pool mapping per port: 668 * Each port is allocated 'bp_per_port' buffer pools and supports 8 669 * IPVs, where a higher IPV indicates a higher frame priority. Each 670 * IPV can be mapped to only one buffer pool, from hardware design 671 * perspective, bp_per_port will not be greater than 8. So 'q' will 672 * not be 0. 673 * 674 * The mapping rule is as follows: 675 * - The first 'num' IPVs share the port's first buffer pool (index 676 * 'base_id'). 677 * - After that, every 'q' IPVs share one buffer pool, with pool 678 * indices increasing sequentially. 679 */ 680 for (int i = 0; i < priv->info->num_ports; i++) { 681 u32 base_id = i * bp_per_port; 682 u32 bp_id = base_id; 683 u64 mapping = 0; 684 685 for (int ipv = 0; ipv < NETC_IPV_NUM; ipv++) { 686 /* Update the buffer pool index */ 687 if (ipv >= num) 688 bp_id = base_id + ((ipv - num) / q) + 1; 689 690 mapping |= (u64)bp_id << (ipv * 8); 691 } 692 693 netc_port_set_pbpmcr(priv->ports[i], mapping); 694 } 695 } 696 697 static int netc_switch_bpt_default_config(struct netc_switch *priv) 698 { 699 if (priv->num_bp < priv->info->num_ports) 700 return -EINVAL; 701 702 priv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp, 703 sizeof(struct bpt_cfge_data), 704 GFP_KERNEL); 705 if (!priv->bpt_list) 706 return -ENOMEM; 707 708 /* Initialize the maximum threshold of each buffer pool entry */ 709 for (int i = 0; i < priv->num_bp; i++) { 710 struct bpt_cfge_data *cfge = &priv->bpt_list[i]; 711 int err; 712 713 cfge->max_thresh = cpu_to_le16(NETC_BP_THRESH); 714 err = ntmp_bpt_update_entry(&priv->ntmp, i, cfge); 715 if (err) 716 return err; 717 } 718 719 netc_ipv_to_buffer_pool_mapping(priv); 720 721 return 0; 722 } 723 724 static int netc_setup(struct dsa_switch *ds) 725 { 726 struct netc_switch *priv = ds->priv; 727 struct dsa_port *dp; 728 int err; 729 730 err = netc_init_switch_id(priv); 731 if (err) 732 return err; 733 734 netc_get_switch_capabilities(priv); 735 736 err = netc_init_all_ports(priv); 737 if (err) 738 return err; 739 740 err = netc_init_ntmp_user(priv); 741 if (err) 742 return err; 743 744 INIT_HLIST_HEAD(&priv->fdb_list); 745 mutex_init(&priv->fdbt_lock); 746 747 netc_switch_fixed_config(priv); 748 749 /* default setting for ports */ 750 dsa_switch_for_each_available_port(dp, ds) 751 netc_port_default_config(priv->ports[dp->index]); 752 753 err = netc_switch_bpt_default_config(priv); 754 if (err) 755 goto free_lock_and_ntmp_user; 756 757 err = netc_add_standalone_vlan_entry(priv); 758 if (err) 759 goto free_lock_and_ntmp_user; 760 761 err = netc_add_standalone_fdb_bcast_entry(priv); 762 if (err) 763 goto free_lock_and_ntmp_user; 764 765 return 0; 766 767 free_lock_and_ntmp_user: 768 /* No need to clear the hardware state, netc_setup() is only called 769 * when the driver is bound, and FLR will be performed to reset the 770 * hardware state. 771 */ 772 mutex_destroy(&priv->fdbt_lock); 773 netc_free_ntmp_user(priv); 774 775 return err; 776 } 777 778 static void netc_destroy_all_lists(struct netc_switch *priv) 779 { 780 netc_destroy_fdb_list(priv); 781 mutex_destroy(&priv->fdbt_lock); 782 } 783 784 static void netc_free_host_flood_rules(struct netc_switch *priv) 785 { 786 struct dsa_port *dp; 787 788 dsa_switch_for_each_user_port(dp, priv->ds) { 789 struct netc_port *np = priv->ports[dp->index]; 790 791 /* No need to clear the hardware IPFT entry. Because PCIe 792 * FLR will be performed when the switch is re-registered, 793 * it will reset hardware state. So only need to free the 794 * memory to avoid memory leak. 795 */ 796 kfree(np->host_flood); 797 np->host_flood = NULL; 798 } 799 } 800 801 static void netc_teardown(struct dsa_switch *ds) 802 { 803 struct netc_switch *priv = ds->priv; 804 805 netc_destroy_all_lists(priv); 806 netc_free_host_flood_rules(priv); 807 netc_free_ntmp_user(priv); 808 } 809 810 static bool netc_port_is_emdio_consumer(struct device_node *node) 811 { 812 struct device_node *mdio_node; 813 814 /* If the port node has phy-handle property and it does 815 * not contain a mdio child node, then the port is the 816 * EMDIO consumer. 817 */ 818 mdio_node = of_get_child_by_name(node, "mdio"); 819 if (!mdio_node) 820 return true; 821 822 of_node_put(mdio_node); 823 824 return false; 825 } 826 827 /* Currently, phylink_of_phy_connect() is called by dsa_user_create(), 828 * so if the switch uses the external MDIO controller (like the EMDIO 829 * function) to manage the external PHYs. The MDIO bus may not be 830 * created when phylink_of_phy_connect() is called, so it will return 831 * an error and cause the switch driver to fail to probe. 832 * This workaround can be removed when DSA phylink_of_phy_connect() 833 * calls are moved from probe() to ndo_open(). 834 */ 835 static int netc_switch_check_emdio_is_ready(struct device *dev) 836 { 837 struct device_node *ports, *phy_node; 838 struct phy_device *phydev; 839 int err = 0; 840 841 ports = of_get_child_by_name(dev->of_node, "ethernet-ports"); 842 if (!ports) { 843 dev_err(dev, "Cannot find the ethernet-ports node\n"); 844 return -EINVAL; 845 } 846 847 for_each_available_child_of_node_scoped(ports, child) { 848 /* If the node does not have phy-handle property, then the 849 * port does not connect to a PHY, so the port is not the 850 * EMDIO consumer. 851 */ 852 phy_node = of_parse_phandle(child, "phy-handle", 0); 853 if (!phy_node) 854 continue; 855 856 /* Note that from the hardware perspective, the switch ports 857 * do not support sharing the MDIO bus defined under one port. 858 * Each port can only access its own external PHY through its 859 * port MDIO bus. 860 */ 861 if (!netc_port_is_emdio_consumer(child)) { 862 of_node_put(phy_node); 863 continue; 864 } 865 866 phydev = of_phy_find_device(phy_node); 867 of_node_put(phy_node); 868 if (!phydev) { 869 err = -EPROBE_DEFER; 870 goto out; 871 } 872 873 put_device(&phydev->mdio.dev); 874 } 875 876 out: 877 of_node_put(ports); 878 879 return err; 880 } 881 882 static int netc_switch_pci_init(struct pci_dev *pdev) 883 { 884 struct device *dev = &pdev->dev; 885 struct netc_switch_regs *regs; 886 struct netc_switch *priv; 887 void __iomem *base; 888 int err; 889 890 pcie_flr(pdev); 891 err = pcim_enable_device(pdev); 892 if (err) 893 return dev_err_probe(dev, err, "Failed to enable device\n"); 894 895 err = pcim_request_all_regions(pdev, KBUILD_MODNAME); 896 if (err) 897 return dev_err_probe(dev, err, "Failed to request regions\n"); 898 899 /* The command BD rings and NTMP tables need DMA. No need to check 900 * the return value, because it never returns fail when the mask is 901 * DMA_BIT_MASK(64), see dma-api-howto.rst. 902 */ 903 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 904 905 if (pci_resource_len(pdev, NETC_REGS_BAR) < NETC_REGS_SIZE) { 906 return dev_err_probe(dev, -EINVAL, 907 "Invalid register space size\n"); 908 } 909 910 base = pcim_iomap(pdev, NETC_REGS_BAR, 0); 911 if (!base) 912 return dev_err_probe(dev, -ENXIO, "pcim_iomap() failed\n"); 913 914 pci_set_master(pdev); 915 916 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 917 if (!priv) 918 return -ENOMEM; 919 920 priv->pdev = pdev; 921 priv->dev = dev; 922 923 regs = &priv->regs; 924 regs->base = base; 925 regs->port = regs->base + NETC_REGS_PORT_BASE; 926 regs->global = regs->base + NETC_REGS_GLOBAL_BASE; 927 pci_set_drvdata(pdev, priv); 928 929 return 0; 930 } 931 932 static void netc_switch_get_ip_revision(struct netc_switch *priv) 933 { 934 struct netc_switch_regs *regs = &priv->regs; 935 u32 val = netc_glb_rd(regs, NETC_IPBRR0); 936 937 priv->revision = FIELD_GET(IPBRR0_IP_REV, val); 938 } 939 940 static int netc_port_enable(struct dsa_switch *ds, int port, 941 struct phy_device *phy) 942 { 943 struct netc_port *np = NETC_PORT(ds, port); 944 int err; 945 946 if (np->enable) 947 return 0; 948 949 err = clk_prepare_enable(np->ref_clk); 950 if (err) { 951 dev_err(ds->dev, 952 "Failed to enable enet_ref_clk of port %d\n", port); 953 return err; 954 } 955 956 np->enable = true; 957 958 return 0; 959 } 960 961 static void netc_port_disable(struct dsa_switch *ds, int port) 962 { 963 struct netc_port *np = NETC_PORT(ds, port); 964 965 /* When .port_disable() is called, .port_enable() may not have been 966 * called. In this case, both the prepare_count and enable_count of 967 * clock are 0. Calling clk_disable_unprepare() at this time will 968 * cause warnings. 969 */ 970 if (!np->enable) 971 return; 972 973 clk_disable_unprepare(np->ref_clk); 974 np->enable = false; 975 } 976 977 static void netc_port_stp_state_set(struct dsa_switch *ds, 978 int port, u8 state) 979 { 980 struct netc_port *np = NETC_PORT(ds, port); 981 u32 val; 982 983 switch (state) { 984 case BR_STATE_DISABLED: 985 case BR_STATE_LISTENING: 986 case BR_STATE_BLOCKING: 987 val = NETC_STG_STATE_DISABLED; 988 break; 989 case BR_STATE_LEARNING: 990 val = NETC_STG_STATE_LEARNING; 991 break; 992 case BR_STATE_FORWARDING: 993 val = NETC_STG_STATE_FORWARDING; 994 break; 995 default: 996 return; 997 } 998 999 netc_port_wr(np, NETC_BPSTGSR, val); 1000 } 1001 1002 static int netc_port_change_mtu(struct dsa_switch *ds, 1003 int port, int mtu) 1004 { 1005 u32 max_frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 1006 1007 netc_port_set_max_frame_size(NETC_PORT(ds, port), max_frame_size); 1008 1009 return 0; 1010 } 1011 1012 static int netc_port_max_mtu(struct dsa_switch *ds, int port) 1013 { 1014 return NETC_MAX_FRAME_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; 1015 } 1016 1017 static int netc_port_fdb_add(struct dsa_switch *ds, int port, 1018 const unsigned char *addr, u16 vid, 1019 struct dsa_db db) 1020 { 1021 struct netc_port *np = NETC_PORT(ds, port); 1022 1023 /* Currently, only support standalone port mode, so only 1024 * NETC_STANDALONE_PVID (= 0) is supported here. 1025 */ 1026 if (vid != NETC_STANDALONE_PVID) 1027 return -EOPNOTSUPP; 1028 1029 return netc_port_set_fdb_entry(np, addr, vid); 1030 } 1031 1032 static int netc_port_fdb_del(struct dsa_switch *ds, int port, 1033 const unsigned char *addr, u16 vid, 1034 struct dsa_db db) 1035 { 1036 struct netc_port *np = NETC_PORT(ds, port); 1037 1038 if (vid != NETC_STANDALONE_PVID) 1039 return -EOPNOTSUPP; 1040 1041 return netc_port_del_fdb_entry(np, addr, vid); 1042 } 1043 1044 static int netc_port_fdb_dump(struct dsa_switch *ds, int port, 1045 dsa_fdb_dump_cb_t *cb, void *data) 1046 { 1047 struct netc_switch *priv = ds->priv; 1048 u32 resume_eid = NTMP_NULL_ENTRY_ID; 1049 struct fdbt_entry_data *entry; 1050 struct fdbt_keye_data *keye; 1051 struct fdbt_cfge_data *cfge; 1052 u32 cfg, cnt = 0; 1053 bool is_static; 1054 int err; 1055 u16 vid; 1056 1057 entry = kmalloc_obj(*entry); 1058 if (!entry) 1059 return -ENOMEM; 1060 1061 keye = &entry->keye; 1062 cfge = &entry->cfge; 1063 mutex_lock(&priv->fdbt_lock); 1064 1065 do { 1066 memset(entry, 0, sizeof(*entry)); 1067 err = ntmp_fdbt_search_port_entry(&priv->ntmp, port, 1068 &resume_eid, entry); 1069 if (err || entry->entry_id == NTMP_NULL_ENTRY_ID) 1070 break; 1071 1072 cfg = le32_to_cpu(cfge->cfg); 1073 is_static = (cfg & FDBT_DYNAMIC) ? false : true; 1074 vid = le16_to_cpu(keye->fid); 1075 1076 err = cb(keye->mac_addr, vid, is_static, data); 1077 if (err) 1078 break; 1079 1080 /* To prevent hardware malfunctions from causing an 1081 * infinite loop. 1082 */ 1083 if (++cnt >= priv->htmcapr_num_words) 1084 break; 1085 } while (resume_eid != NTMP_NULL_ENTRY_ID); 1086 1087 mutex_unlock(&priv->fdbt_lock); 1088 kfree(entry); 1089 1090 return err; 1091 } 1092 1093 static int netc_port_mdb_add(struct dsa_switch *ds, int port, 1094 const struct switchdev_obj_port_mdb *mdb, 1095 struct dsa_db db) 1096 { 1097 return netc_port_fdb_add(ds, port, mdb->addr, mdb->vid, db); 1098 } 1099 1100 static int netc_port_mdb_del(struct dsa_switch *ds, int port, 1101 const struct switchdev_obj_port_mdb *mdb, 1102 struct dsa_db db) 1103 { 1104 return netc_port_fdb_del(ds, port, mdb->addr, mdb->vid, db); 1105 } 1106 1107 static int netc_port_add_host_flood_rule(struct netc_port *np, 1108 bool uc, bool mc) 1109 { 1110 const u8 dmac_mask[ETH_ALEN] = {0x1, 0, 0, 0, 0, 0}; 1111 struct netc_switch *priv = np->switch_priv; 1112 struct ipft_entry_data *host_flood; 1113 struct ipft_keye_data *keye; 1114 struct ipft_cfge_data *cfge; 1115 u16 src_port; 1116 u32 cfg; 1117 int err; 1118 1119 if (!uc && !mc) { 1120 /* Disable ingress port filter table lookup */ 1121 netc_port_wr(np, NETC_PIPFCR, 0); 1122 np->uc = false; 1123 np->mc = false; 1124 1125 return 0; 1126 } 1127 1128 host_flood = kzalloc_obj(*host_flood); 1129 if (!host_flood) 1130 return -ENOMEM; 1131 1132 keye = &host_flood->keye; 1133 cfge = &host_flood->cfge; 1134 1135 src_port = FIELD_PREP(IPFT_SRC_PORT, np->dp->index); 1136 src_port |= IPFT_SRC_PORT_MASK; 1137 keye->src_port = cpu_to_le16(src_port); 1138 1139 /* If either only unicast or only multicast need to be flooded 1140 * to the host, we always set the mask that tests the first MAC 1141 * DA octet. The value should be 0 for the first bit (if unicast 1142 * has to be flooded) or 1 (if multicast). If both unicast and 1143 * multicast have to be flooded, we leave the key mask empty, so 1144 * it matches everything. 1145 */ 1146 if (uc && !mc) 1147 ether_addr_copy(keye->dmac_mask, dmac_mask); 1148 1149 if (!uc && mc) { 1150 ether_addr_copy(keye->dmac, dmac_mask); 1151 ether_addr_copy(keye->dmac_mask, dmac_mask); 1152 } 1153 1154 cfg = FIELD_PREP(IPFT_FLTFA, IPFT_FLTFA_REDIRECT); 1155 cfg |= FIELD_PREP(IPFT_HR, NETC_HR_HOST_FLOOD); 1156 cfge->cfg = cpu_to_le32(cfg); 1157 1158 err = ntmp_ipft_add_entry(&priv->ntmp, host_flood); 1159 if (err) { 1160 kfree(host_flood); 1161 return err; 1162 } 1163 1164 np->uc = uc; 1165 np->mc = mc; 1166 np->host_flood = host_flood; 1167 /* Enable ingress port filter table lookup */ 1168 netc_port_wr(np, NETC_PIPFCR, PIPFCR_EN); 1169 1170 return 0; 1171 } 1172 1173 static void netc_port_remove_host_flood(struct netc_port *np, 1174 struct ipft_entry_data *host_flood) 1175 { 1176 struct netc_switch *priv = np->switch_priv; 1177 1178 if (!host_flood) 1179 return; 1180 1181 ntmp_ipft_delete_entry(&priv->ntmp, host_flood->entry_id); 1182 kfree(host_flood); 1183 } 1184 1185 static void netc_port_set_host_flood(struct dsa_switch *ds, int port, 1186 bool uc, bool mc) 1187 { 1188 struct netc_port *np = NETC_PORT(ds, port); 1189 struct ipft_entry_data *old_host_flood; 1190 1191 if (np->uc == uc && np->mc == mc) 1192 return; 1193 1194 /* IPFT does not support in-place updates to the KEYE element, 1195 * we need to add a new entry and then delete the old one. So 1196 * save the old entry first. 1197 */ 1198 old_host_flood = np->host_flood; 1199 np->host_flood = NULL; 1200 1201 if (netc_port_add_host_flood_rule(np, uc, mc)) { 1202 np->host_flood = old_host_flood; 1203 dev_err(ds->dev, "Failed to add host flood rule on port %d\n", 1204 port); 1205 return; 1206 } 1207 1208 /* Remove the old host flood entry */ 1209 netc_port_remove_host_flood(np, old_host_flood); 1210 } 1211 1212 static void netc_phylink_get_caps(struct dsa_switch *ds, int port, 1213 struct phylink_config *config) 1214 { 1215 struct netc_switch *priv = ds->priv; 1216 1217 priv->info->phylink_get_caps(port, config); 1218 } 1219 1220 static void netc_port_set_mac_mode(struct netc_port *np, 1221 unsigned int mode, 1222 phy_interface_t phy_mode) 1223 { 1224 u32 mask = PM_IF_MODE_IFMODE | PM_IF_MODE_REVMII; 1225 u32 val = 0; 1226 1227 switch (phy_mode) { 1228 case PHY_INTERFACE_MODE_RGMII: 1229 case PHY_INTERFACE_MODE_RGMII_ID: 1230 case PHY_INTERFACE_MODE_RGMII_RXID: 1231 case PHY_INTERFACE_MODE_RGMII_TXID: 1232 val |= IFMODE_RGMII; 1233 break; 1234 case PHY_INTERFACE_MODE_RMII: 1235 val |= IFMODE_RMII; 1236 break; 1237 case PHY_INTERFACE_MODE_REVMII: 1238 val |= PM_IF_MODE_REVMII; 1239 fallthrough; 1240 case PHY_INTERFACE_MODE_MII: 1241 val |= IFMODE_MII; 1242 break; 1243 case PHY_INTERFACE_MODE_SGMII: 1244 case PHY_INTERFACE_MODE_2500BASEX: 1245 val |= IFMODE_SGMII; 1246 break; 1247 default: 1248 break; 1249 } 1250 1251 netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val); 1252 } 1253 1254 static void netc_mac_config(struct phylink_config *config, unsigned int mode, 1255 const struct phylink_link_state *state) 1256 { 1257 struct dsa_port *dp = dsa_phylink_to_port(config); 1258 1259 netc_port_set_mac_mode(NETC_PORT(dp->ds, dp->index), mode, 1260 state->interface); 1261 } 1262 1263 static void netc_port_set_speed(struct netc_port *np, int speed) 1264 { 1265 netc_port_rmw(np, NETC_PCR, PCR_PSPEED, PSPEED_SET_VAL(speed)); 1266 } 1267 1268 static void netc_port_set_rgmii_mac(struct netc_port *np, 1269 int speed, int duplex) 1270 { 1271 u32 mask, val; 1272 1273 mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10; 1274 1275 switch (speed) { 1276 default: 1277 case SPEED_1000: 1278 val = FIELD_PREP(PM_IF_MODE_SSP, SSP_1G); 1279 break; 1280 case SPEED_100: 1281 val = FIELD_PREP(PM_IF_MODE_SSP, SSP_100M); 1282 break; 1283 case SPEED_10: 1284 val = FIELD_PREP(PM_IF_MODE_SSP, SSP_10M); 1285 break; 1286 } 1287 1288 if (duplex != DUPLEX_FULL) 1289 val |= PM_IF_MODE_HD; 1290 1291 netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val); 1292 } 1293 1294 static void netc_port_set_rmii_mii_mac(struct netc_port *np, 1295 int speed, int duplex) 1296 { 1297 u32 mask, val = 0; 1298 1299 mask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10; 1300 1301 if (speed == SPEED_10) 1302 val |= PM_IF_MODE_M10; 1303 1304 if (duplex != DUPLEX_FULL) 1305 val |= PM_IF_MODE_HD; 1306 1307 netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val); 1308 } 1309 1310 static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause) 1311 { 1312 struct netc_switch *priv = np->switch_priv; 1313 int port = np->dp->index; 1314 int i, j, num_bp; 1315 1316 num_bp = priv->num_bp / priv->info->num_ports; 1317 for (i = 0, j = port * num_bp; i < num_bp; i++, j++) { 1318 struct bpt_cfge_data *cfge = &priv->bpt_list[j]; 1319 struct bpt_cfge_data old_cfge = *cfge; 1320 1321 if (tx_pause) { 1322 cfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON); 1323 cfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF); 1324 cfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG, 1325 BPT_FC_CFG_EN_BPFC); 1326 cfge->fc_ports = cpu_to_le32(BIT(port)); 1327 } else { 1328 cfge->fc_on_thresh = cpu_to_le16(0); 1329 cfge->fc_off_thresh = cpu_to_le16(0); 1330 cfge->fccfg_sbpen = 0; 1331 cfge->fc_ports = cpu_to_le32(0); 1332 } 1333 1334 if (ntmp_bpt_update_entry(&priv->ntmp, j, cfge)) { 1335 *cfge = old_cfge; 1336 dev_warn(priv->dev, 1337 "Failed to %s TX pause of buffer pool %d (swp%d)\n", 1338 tx_pause ? "enable" : "disable", j, port); 1339 } 1340 } 1341 } 1342 1343 static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause) 1344 { 1345 netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN, 1346 rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN); 1347 } 1348 1349 static void netc_port_mac_rx_enable(struct netc_port *np) 1350 { 1351 netc_port_rmw(np, NETC_POR, POR_RXDIS, 0); 1352 netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 1353 PM_CMD_CFG_RX_EN); 1354 } 1355 1356 static void netc_port_wait_rx_empty(struct netc_port *np, int mac) 1357 { 1358 u32 val; 1359 1360 /* PM_IEVENT_RX_EMPTY is a read-only bit, it is automatically set by 1361 * hardware if RX FIFO is empty and no RX packet receive in process. 1362 * And it is automatically cleared if RX FIFO is not empty or RX 1363 * packet receive in process. 1364 */ 1365 if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_RX_EMPTY, 1366 100, 10000, false, np, NETC_PM_IEVENT(mac))) 1367 dev_warn(np->switch_priv->dev, 1368 "swp%d MAC%d: RX is not idle\n", np->dp->index, mac); 1369 } 1370 1371 static void netc_port_mac_rx_graceful_stop(struct netc_port *np) 1372 { 1373 u32 val; 1374 1375 if (is_netc_pseudo_port(np)) 1376 goto rx_disable; 1377 1378 if (np->caps.pmac) { 1379 netc_port_rmw(np, NETC_PM_CMD_CFG(1), PM_CMD_CFG_RX_EN, 0); 1380 netc_port_wait_rx_empty(np, 1); 1381 } 1382 1383 netc_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 0); 1384 netc_port_wait_rx_empty(np, 0); 1385 1386 if (read_poll_timeout(netc_port_rd, val, !(val & PSR_RX_BUSY), 1387 100, 10000, false, np, NETC_PSR)) 1388 dev_warn(np->switch_priv->dev, "swp%d RX is busy\n", 1389 np->dp->index); 1390 1391 rx_disable: 1392 netc_port_rmw(np, NETC_POR, POR_RXDIS, POR_RXDIS); 1393 } 1394 1395 static void netc_port_mac_tx_enable(struct netc_port *np) 1396 { 1397 netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN, 1398 PM_CMD_CFG_TX_EN); 1399 netc_port_rmw(np, NETC_POR, POR_TXDIS, 0); 1400 } 1401 1402 static void netc_port_wait_tx_empty(struct netc_port *np, int mac) 1403 { 1404 u32 val; 1405 1406 /* PM_IEVENT_TX_EMPTY is a read-only bit, it is automatically set by 1407 * hardware if TX FIFO is empty. And it is automatically cleared if 1408 * TX FIFO is not empty. 1409 */ 1410 if (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_TX_EMPTY, 1411 100, 10000, false, np, NETC_PM_IEVENT(mac))) 1412 dev_warn(np->switch_priv->dev, 1413 "swp%d MAC%d: TX FIFO is not empty\n", 1414 np->dp->index, mac); 1415 } 1416 1417 static void netc_port_mac_tx_graceful_stop(struct netc_port *np) 1418 { 1419 netc_port_rmw(np, NETC_POR, POR_TXDIS, POR_TXDIS); 1420 1421 if (is_netc_pseudo_port(np)) 1422 return; 1423 1424 netc_port_wait_tx_empty(np, 0); 1425 if (np->caps.pmac) 1426 netc_port_wait_tx_empty(np, 1); 1427 1428 netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN, 0); 1429 } 1430 1431 static void netc_mac_link_up(struct phylink_config *config, 1432 struct phy_device *phy, unsigned int mode, 1433 phy_interface_t interface, int speed, 1434 int duplex, bool tx_pause, bool rx_pause) 1435 { 1436 struct dsa_port *dp = dsa_phylink_to_port(config); 1437 struct netc_port *np; 1438 1439 np = NETC_PORT(dp->ds, dp->index); 1440 netc_port_set_speed(np, speed); 1441 1442 if (phy_interface_mode_is_rgmii(interface)) 1443 netc_port_set_rgmii_mac(np, speed, duplex); 1444 1445 if (interface == PHY_INTERFACE_MODE_RMII || 1446 interface == PHY_INTERFACE_MODE_REVMII || 1447 interface == PHY_INTERFACE_MODE_MII) 1448 netc_port_set_rmii_mii_mac(np, speed, duplex); 1449 1450 netc_port_set_tx_pause(np, tx_pause); 1451 netc_port_set_rx_pause(np, rx_pause); 1452 netc_port_mac_tx_enable(np); 1453 netc_port_mac_rx_enable(np); 1454 } 1455 1456 static void netc_mac_link_down(struct phylink_config *config, 1457 unsigned int mode, 1458 phy_interface_t interface) 1459 { 1460 struct dsa_port *dp = dsa_phylink_to_port(config); 1461 struct netc_port *np; 1462 1463 np = NETC_PORT(dp->ds, dp->index); 1464 netc_port_mac_rx_graceful_stop(np); 1465 netc_port_mac_tx_graceful_stop(np); 1466 } 1467 1468 static const struct phylink_mac_ops netc_phylink_mac_ops = { 1469 .mac_config = netc_mac_config, 1470 .mac_link_up = netc_mac_link_up, 1471 .mac_link_down = netc_mac_link_down, 1472 }; 1473 1474 static const struct dsa_switch_ops netc_switch_ops = { 1475 .get_tag_protocol = netc_get_tag_protocol, 1476 .setup = netc_setup, 1477 .teardown = netc_teardown, 1478 .phylink_get_caps = netc_phylink_get_caps, 1479 .port_enable = netc_port_enable, 1480 .port_disable = netc_port_disable, 1481 .port_stp_state_set = netc_port_stp_state_set, 1482 .port_change_mtu = netc_port_change_mtu, 1483 .port_max_mtu = netc_port_max_mtu, 1484 .port_fdb_add = netc_port_fdb_add, 1485 .port_fdb_del = netc_port_fdb_del, 1486 .port_fdb_dump = netc_port_fdb_dump, 1487 .port_mdb_add = netc_port_mdb_add, 1488 .port_mdb_del = netc_port_mdb_del, 1489 .port_set_host_flood = netc_port_set_host_flood, 1490 .get_pause_stats = netc_port_get_pause_stats, 1491 .get_rmon_stats = netc_port_get_rmon_stats, 1492 .get_eth_ctrl_stats = netc_port_get_eth_ctrl_stats, 1493 .get_eth_mac_stats = netc_port_get_eth_mac_stats, 1494 .get_sset_count = netc_port_get_sset_count, 1495 .get_strings = netc_port_get_strings, 1496 .get_ethtool_stats = netc_port_get_ethtool_stats, 1497 }; 1498 1499 static int netc_switch_probe(struct pci_dev *pdev, 1500 const struct pci_device_id *id) 1501 { 1502 struct device_node *node = dev_of_node(&pdev->dev); 1503 struct device *dev = &pdev->dev; 1504 struct netc_switch *priv; 1505 struct dsa_switch *ds; 1506 int err; 1507 1508 if (!node) 1509 return dev_err_probe(dev, -ENODEV, 1510 "No DT bindings, skipping\n"); 1511 1512 err = netc_switch_check_emdio_is_ready(dev); 1513 if (err) 1514 return err; 1515 1516 err = netc_switch_pci_init(pdev); 1517 if (err) 1518 return err; 1519 1520 priv = pci_get_drvdata(pdev); 1521 netc_switch_get_ip_revision(priv); 1522 1523 err = netc_switch_platform_probe(priv); 1524 if (err) 1525 return err; 1526 1527 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 1528 if (!ds) 1529 return -ENOMEM; 1530 1531 ds->dev = dev; 1532 ds->num_ports = priv->info->num_ports; 1533 ds->num_tx_queues = NETC_TC_NUM; 1534 ds->ops = &netc_switch_ops; 1535 ds->phylink_mac_ops = &netc_phylink_mac_ops; 1536 ds->fdb_isolation = true; 1537 ds->priv = priv; 1538 priv->ds = ds; 1539 1540 err = dsa_register_switch(ds); 1541 if (err) 1542 return dev_err_probe(dev, err, 1543 "Failed to register DSA switch\n"); 1544 1545 return 0; 1546 } 1547 1548 static void netc_switch_remove(struct pci_dev *pdev) 1549 { 1550 struct netc_switch *priv = pci_get_drvdata(pdev); 1551 1552 if (!priv) 1553 return; 1554 1555 dsa_unregister_switch(priv->ds); 1556 } 1557 1558 static void netc_switch_shutdown(struct pci_dev *pdev) 1559 { 1560 struct netc_switch *priv = pci_get_drvdata(pdev); 1561 1562 if (!priv) 1563 return; 1564 1565 dsa_switch_shutdown(priv->ds); 1566 pci_set_drvdata(pdev, NULL); 1567 } 1568 1569 static const struct pci_device_id netc_switch_ids[] = { 1570 { PCI_DEVICE(NETC_SWITCH_VENDOR_ID, NETC_SWITCH_DEVICE_ID) }, 1571 { } 1572 }; 1573 MODULE_DEVICE_TABLE(pci, netc_switch_ids); 1574 1575 static struct pci_driver netc_switch_driver = { 1576 .name = KBUILD_MODNAME, 1577 .id_table = netc_switch_ids, 1578 .probe = netc_switch_probe, 1579 .remove = netc_switch_remove, 1580 .shutdown = netc_switch_shutdown, 1581 }; 1582 module_pci_driver(netc_switch_driver); 1583 1584 MODULE_DESCRIPTION("NXP NETC Switch driver"); 1585 MODULE_LICENSE("Dual BSD/GPL"); 1586