1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Switch PTP support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2017 National Instruments 8 * Erik Hons <erik.hons@ni.com> 9 * Brandon Streiff <brandon.streiff@ni.com> 10 * Dane Wagner <dane.wagner@ni.com> 11 */ 12 13 #ifndef _MV88E6XXX_PTP_H 14 #define _MV88E6XXX_PTP_H 15 16 #include "chip.h" 17 18 /* Offset 0x00: TAI Global Config */ 19 #define MV88E6XXX_TAI_CFG 0x00 20 #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000 21 #define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000 22 #define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000 23 #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000 24 #define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400 25 #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200 26 #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100 27 #define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080 28 #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008 29 #define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004 30 #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002 31 #define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001 32 33 /* Offset 0x01: Timestamp Clock Period (ps) */ 34 #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 35 36 /* Offset 0x02/0x03: Trigger Generation Amount */ 37 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02 38 #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03 39 40 /* Offset 0x04: Clock Compensation */ 41 #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04 42 43 /* Offset 0x05: Trigger Configuration */ 44 #define MV88E6XXX_TAI_TRIG_CFG 0x05 45 46 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ 47 #define MV88E6XXX_TAI_IRL_AMOUNT 0x06 48 49 /* Offset 0x07: Ingress Rate Limiter Compensation */ 50 #define MV88E6XXX_TAI_IRL_COMP 0x07 51 52 /* Offset 0x08: Ingress Rate Limiter Compensation */ 53 #define MV88E6XXX_TAI_IRL_COMP_PS 0x08 54 55 /* Offset 0x09: Event Status */ 56 #define MV88E6XXX_TAI_EVENT_STATUS 0x09 57 #define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200 58 #define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100 59 #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff 60 61 /* Offset 0x0A/0x0B: Event Time */ 62 #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a 63 #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b 64 65 /* Offset 0x0E/0x0F: PTP Global Time */ 66 #define MV88E6XXX_TAI_TIME_LO 0x0e 67 #define MV88E6XXX_TAI_TIME_HI 0x0f 68 69 /* Offset 0x10/0x11: Trig Generation Time */ 70 #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10 71 #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11 72 73 /* Offset 0x12: Lock Status */ 74 #define MV88E6XXX_TAI_LOCK_STATUS 0x12 75 76 /* Offset 0x00: Ether Type */ 77 #define MV88E6XXX_PTP_GC_ETYPE 0x00 78 79 /* 6165 Global Control Registers */ 80 /* Offset 0x00: Ether Type */ 81 #define MV88E6XXX_PTP_GC_ETYPE 0x00 82 83 /* Offset 0x01: Message ID */ 84 #define MV88E6XXX_PTP_GC_MESSAGE_ID 0x01 85 86 /* Offset 0x02: Time Stamp Arrive Time */ 87 #define MV88E6XXX_PTP_GC_TS_ARR_PTR 0x02 88 89 /* Offset 0x03: Port Arrival Interrupt Enable */ 90 #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN 0x03 91 92 /* Offset 0x04: Port Departure Interrupt Enable */ 93 #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN 0x04 94 95 /* Offset 0x05: Configuration */ 96 #define MV88E6XXX_PTP_GC_CONFIG 0x05 97 #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1) 98 #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0) 99 100 /* Offset 0x8: Interrupt Status */ 101 #define MV88E6XXX_PTP_GC_INT_STATUS 0x08 102 103 /* Offset 0x9/0xa: Global Time */ 104 #define MV88E6XXX_PTP_GC_TIME_LO 0x09 105 #define MV88E6XXX_PTP_GC_TIME_HI 0x0A 106 107 /* 6165 Per Port Registers */ 108 /* Offset 0: Arrival Time 0 Status */ 109 #define MV88E6165_PORT_PTP_ARR0_STS 0x00 110 111 /* Offset 0x01/0x02: PTP Arrival 0 Time */ 112 #define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01 113 #define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02 114 115 /* Offset 0x03: PTP Arrival 0 Sequence ID */ 116 #define MV88E6165_PORT_PTP_ARR0_SEQID 0x03 117 118 /* Offset 0x04: PTP Arrival 1 Status */ 119 #define MV88E6165_PORT_PTP_ARR1_STS 0x04 120 121 /* Offset 0x05/0x6E: PTP Arrival 1 Time */ 122 #define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05 123 #define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06 124 125 /* Offset 0x07: PTP Arrival 1 Sequence ID */ 126 #define MV88E6165_PORT_PTP_ARR1_SEQID 0x07 127 128 /* Offset 0x08: PTP Departure Status */ 129 #define MV88E6165_PORT_PTP_DEP_STS 0x08 130 131 /* Offset 0x09/0x0a: PTP Deperture Time */ 132 #define MV88E6165_PORT_PTP_DEP_TIME_LO 0x09 133 #define MV88E6165_PORT_PTP_DEP_TIME_HI 0x0a 134 135 /* Offset 0x0b: PTP Departure Sequence ID */ 136 #define MV88E6165_PORT_PTP_DEP_SEQID 0x0b 137 138 /* Offset 0x0d: Port Status */ 139 #define MV88E6164_PORT_STATUS 0x0d 140 141 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 142 143 long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp); 144 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); 145 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); 146 147 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \ 148 ptp_clock_info) 149 150 extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops; 151 extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops; 152 extern const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops; 153 154 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 155 156 static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp) 157 { 158 return -1; 159 } 160 161 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 162 { 163 return 0; 164 } 165 166 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 167 { 168 } 169 170 static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {}; 171 static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {}; 172 static const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops = {}; 173 174 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 175 176 #endif /* _MV88E6XXX_PTP_H */ 177