1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Switch PTP support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2017 National Instruments 8 * Erik Hons <erik.hons@ni.com> 9 * Brandon Streiff <brandon.streiff@ni.com> 10 * Dane Wagner <dane.wagner@ni.com> 11 */ 12 13 #ifndef _MV88E6XXX_PTP_H 14 #define _MV88E6XXX_PTP_H 15 16 #include "chip.h" 17 18 /* Offset 0x00: TAI Global Config */ 19 #define MV88E6352_TAI_CFG 0x00 20 #define MV88E6352_TAI_CFG_CAP_OVERWRITE 0x8000 21 #define MV88E6352_TAI_CFG_CAP_CTR_START 0x4000 22 #define MV88E6352_TAI_CFG_EVREQ_FALLING 0x2000 23 #define MV88E6352_TAI_CFG_TRIG_ACTIVE_LO 0x1000 24 #define MV88E6352_TAI_CFG_IRL_ENABLE 0x0400 25 #define MV88E6352_TAI_CFG_TRIG_IRQ_EN 0x0200 26 #define MV88E6352_TAI_CFG_EVREQ_IRQ_EN 0x0100 27 #define MV88E6352_TAI_CFG_TRIG_LOCK 0x0080 28 #define MV88E6352_TAI_CFG_BLOCK_UPDATE 0x0008 29 #define MV88E6352_TAI_CFG_MULTI_PTP 0x0004 30 #define MV88E6352_TAI_CFG_TRIG_MODE_ONESHOT 0x0002 31 #define MV88E6352_TAI_CFG_TRIG_ENABLE 0x0001 32 33 /* Offset 0x01: Timestamp Clock Period (ps) */ 34 #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 35 36 /* Offset 0x09: Event Status */ 37 #define MV88E6352_TAI_EVENT_STATUS 0x09 38 #define MV88E6352_TAI_EVENT_STATUS_ERROR 0x0200 39 #define MV88E6352_TAI_EVENT_STATUS_VALID 0x0100 40 #define MV88E6352_TAI_EVENT_STATUS_CTR_MASK 0x00ff 41 /* Offset 0x0A/0x0B: Event Time Lo/Hi. Always read with Event Status. */ 42 43 /* Offset 0x0E/0x0F: PTP Global Time */ 44 #define MV88E6352_TAI_TIME_LO 0x0e 45 #define MV88E6352_TAI_TIME_HI 0x0f 46 47 /* 6165 Global Control Registers */ 48 /* Offset 0x9/0xa: Global Time */ 49 #define MV88E6165_PTP_GC_TIME_LO 0x09 50 #define MV88E6165_PTP_GC_TIME_HI 0x0A 51 52 /* 6165 Per Port Registers. The arrival and departure registers are a 53 * common block consisting of status, two time registers and the sequence ID 54 */ 55 /* Offset 0: Arrival Time 0 Status */ 56 #define MV88E6165_PORT_PTP_ARR0_STS 0x00 57 58 /* Offset 0x04: PTP Arrival 1 Status */ 59 #define MV88E6165_PORT_PTP_ARR1_STS 0x04 60 61 /* Offset 0x08: PTP Departure Status */ 62 #define MV88E6165_PORT_PTP_DEP_STS 0x08 63 64 /* Offset 0x0d: Port Status */ 65 #define MV88E6164_PORT_STATUS 0x0d 66 67 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 68 69 int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); 70 void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); 71 72 #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \ 73 ptp_clock_info) 74 75 extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops; 76 extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops; 77 extern const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops; 78 79 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 80 81 static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) 82 { 83 return 0; 84 } 85 86 static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) 87 { 88 } 89 90 static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {}; 91 static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {}; 92 static const struct mv88e6xxx_ptp_ops mv88e6390_ptp_ops = {}; 93 94 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 95 96 #endif /* _MV88E6XXX_PTP_H */ 97