1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Port Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/if_bridge.h> 13 #include <linux/phy.h> 14 #include <linux/phylink.h> 15 16 #include "chip.h" 17 #include "global2.h" 18 #include "port.h" 19 #include "serdes.h" 20 21 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 22 u16 *val) 23 { 24 int addr = chip->info->port_base_addr + port; 25 26 return mv88e6xxx_read(chip, addr, reg, val); 27 } 28 29 int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 30 int bit, int val) 31 { 32 int addr = chip->info->port_base_addr + port; 33 34 return mv88e6xxx_wait_bit(chip, addr, reg, bit, val); 35 } 36 37 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 38 u16 val) 39 { 40 int addr = chip->info->port_base_addr + port; 41 42 return mv88e6xxx_write(chip, addr, reg, val); 43 } 44 45 /* Offset 0x00: MAC (or PCS or Physical) Status Register 46 * 47 * For most devices, this is read only. However the 6185 has the MyPause 48 * bit read/write. 49 */ 50 int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 51 int pause) 52 { 53 u16 reg; 54 int err; 55 56 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 57 if (err) 58 return err; 59 60 if (pause) 61 reg |= MV88E6XXX_PORT_STS_MY_PAUSE; 62 else 63 reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; 64 65 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 66 } 67 68 /* Offset 0x01: MAC (or PCS or Physical) Control Register 69 * 70 * Link, Duplex and Flow Control have one force bit, one value bit. 71 * 72 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. 73 * Alternative values require the 200BASE (or AltSpeed) bit 12 set. 74 * Newer chips need a ForcedSpd bit 13 set to consider the value. 75 */ 76 77 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 78 phy_interface_t mode) 79 { 80 u16 reg; 81 int err; 82 83 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 84 if (err) 85 return err; 86 87 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 88 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); 89 90 switch (mode) { 91 case PHY_INTERFACE_MODE_RGMII_RXID: 92 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; 93 break; 94 case PHY_INTERFACE_MODE_RGMII_TXID: 95 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 96 break; 97 case PHY_INTERFACE_MODE_RGMII_ID: 98 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | 99 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; 100 break; 101 case PHY_INTERFACE_MODE_RGMII: 102 break; 103 default: 104 return 0; 105 } 106 107 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 108 if (err) 109 return err; 110 111 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, 112 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", 113 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); 114 115 return 0; 116 } 117 118 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 119 phy_interface_t mode) 120 { 121 if (port < 5) 122 return -EOPNOTSUPP; 123 124 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 125 } 126 127 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 128 phy_interface_t mode) 129 { 130 if (port != 0) 131 return -EOPNOTSUPP; 132 133 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); 134 } 135 136 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) 137 { 138 u16 reg; 139 int err; 140 141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 142 if (err) 143 return err; 144 145 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 146 MV88E6XXX_PORT_MAC_CTL_LINK_UP); 147 148 switch (link) { 149 case LINK_FORCED_DOWN: 150 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; 151 break; 152 case LINK_FORCED_UP: 153 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | 154 MV88E6XXX_PORT_MAC_CTL_LINK_UP; 155 break; 156 case LINK_UNFORCED: 157 /* normal link detection */ 158 break; 159 default: 160 return -EINVAL; 161 } 162 163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 164 if (err) 165 return err; 166 167 dev_dbg(chip->dev, "p%d: %s link %s\n", port, 168 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", 169 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); 170 171 return 0; 172 } 173 174 int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 175 { 176 const struct mv88e6xxx_ops *ops = chip->info->ops; 177 int err = 0; 178 int link; 179 180 if (isup) 181 link = LINK_FORCED_UP; 182 else 183 link = LINK_FORCED_DOWN; 184 185 if (ops->port_set_link) 186 err = ops->port_set_link(chip, port, link); 187 188 return err; 189 } 190 191 int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup) 192 { 193 const struct mv88e6xxx_ops *ops = chip->info->ops; 194 int err = 0; 195 int link; 196 197 if (mode == MLO_AN_INBAND) 198 link = LINK_UNFORCED; 199 else if (isup) 200 link = LINK_FORCED_UP; 201 else 202 link = LINK_FORCED_DOWN; 203 204 if (ops->port_set_link) 205 err = ops->port_set_link(chip, port, link); 206 207 return err; 208 } 209 210 static int mv88e6xxx_port_set_speed_duplex(struct mv88e6xxx_chip *chip, 211 int port, int speed, bool alt_bit, 212 bool force_bit, int duplex) 213 { 214 u16 reg, ctrl; 215 int err; 216 217 switch (speed) { 218 case 10: 219 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 220 break; 221 case 100: 222 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 223 break; 224 case 200: 225 if (alt_bit) 226 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 227 MV88E6390_PORT_MAC_CTL_ALTSPEED; 228 else 229 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; 230 break; 231 case 1000: 232 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 233 break; 234 case 2500: 235 if (alt_bit) 236 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 237 MV88E6390_PORT_MAC_CTL_ALTSPEED; 238 else 239 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000; 240 break; 241 case 10000: 242 /* all bits set, fall through... */ 243 case SPEED_UNFORCED: 244 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 245 break; 246 default: 247 return -EOPNOTSUPP; 248 } 249 250 switch (duplex) { 251 case DUPLEX_HALF: 252 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 253 break; 254 case DUPLEX_FULL: 255 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 256 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 257 break; 258 case DUPLEX_UNFORCED: 259 /* normal duplex detection */ 260 break; 261 default: 262 return -EOPNOTSUPP; 263 } 264 265 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 266 if (err) 267 return err; 268 269 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 270 MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 271 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); 272 273 if (alt_bit) 274 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; 275 if (force_bit) { 276 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 277 if (speed != SPEED_UNFORCED) 278 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 279 } 280 reg |= ctrl; 281 282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 283 if (err) 284 return err; 285 286 if (speed != SPEED_UNFORCED) 287 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 288 else 289 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 290 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 291 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 292 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 293 294 return 0; 295 } 296 297 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ 298 int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 299 int speed, int duplex) 300 { 301 if (speed == 200 || speed > 1000) 302 return -EOPNOTSUPP; 303 304 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 305 duplex); 306 } 307 308 /* Support 10, 100 Mbps (e.g. 88E6250 family) */ 309 int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 310 int speed, int duplex) 311 { 312 if (speed > 100) 313 return -EOPNOTSUPP; 314 315 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, false, false, 316 duplex); 317 } 318 319 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6341) */ 320 int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 321 int speed, int duplex) 322 { 323 if (speed > 2500) 324 return -EOPNOTSUPP; 325 326 if (speed == 200 && port != 0) 327 return -EOPNOTSUPP; 328 329 if (speed == 2500 && port < 5) 330 return -EOPNOTSUPP; 331 332 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, !port, true, 333 duplex); 334 } 335 336 phy_interface_t mv88e6341_port_max_speed_mode(int port) 337 { 338 if (port == 5) 339 return PHY_INTERFACE_MODE_2500BASEX; 340 341 return PHY_INTERFACE_MODE_NA; 342 } 343 344 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ 345 int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 346 int speed, int duplex) 347 { 348 if (speed > 1000) 349 return -EOPNOTSUPP; 350 351 if (speed == 200 && port < 5) 352 return -EOPNOTSUPP; 353 354 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, false, 355 duplex); 356 } 357 358 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ 359 int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 360 int speed, int duplex) 361 { 362 if (speed > 2500) 363 return -EOPNOTSUPP; 364 365 if (speed == 200 && port != 0) 366 return -EOPNOTSUPP; 367 368 if (speed == 2500 && port < 9) 369 return -EOPNOTSUPP; 370 371 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 372 duplex); 373 } 374 375 phy_interface_t mv88e6390_port_max_speed_mode(int port) 376 { 377 if (port == 9 || port == 10) 378 return PHY_INTERFACE_MODE_2500BASEX; 379 380 return PHY_INTERFACE_MODE_NA; 381 } 382 383 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ 384 int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 385 int speed, int duplex) 386 { 387 if (speed == 200 && port != 0) 388 return -EOPNOTSUPP; 389 390 if (speed >= 2500 && port < 9) 391 return -EOPNOTSUPP; 392 393 return mv88e6xxx_port_set_speed_duplex(chip, port, speed, true, true, 394 duplex); 395 } 396 397 phy_interface_t mv88e6390x_port_max_speed_mode(int port) 398 { 399 if (port == 9 || port == 10) 400 return PHY_INTERFACE_MODE_XAUI; 401 402 return PHY_INTERFACE_MODE_NA; 403 } 404 405 /* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) 406 * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register 407 * values for speeds 2500 & 5000 conflict. 408 */ 409 int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 410 int speed, int duplex) 411 { 412 u16 reg, ctrl; 413 int err; 414 415 if (speed == 200 && port != 0) 416 return -EOPNOTSUPP; 417 418 if (speed >= 2500 && port > 0 && port < 9) 419 return -EOPNOTSUPP; 420 421 switch (speed) { 422 case 10: 423 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; 424 break; 425 case 100: 426 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; 427 break; 428 case 200: 429 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | 430 MV88E6390_PORT_MAC_CTL_ALTSPEED; 431 break; 432 case 1000: 433 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; 434 break; 435 case 2500: 436 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000 | 437 MV88E6390_PORT_MAC_CTL_ALTSPEED; 438 break; 439 case 5000: 440 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | 441 MV88E6390_PORT_MAC_CTL_ALTSPEED; 442 break; 443 case 10000: 444 case SPEED_UNFORCED: 445 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; 446 break; 447 default: 448 return -EOPNOTSUPP; 449 } 450 451 switch (duplex) { 452 case DUPLEX_HALF: 453 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; 454 break; 455 case DUPLEX_FULL: 456 ctrl |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | 457 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; 458 break; 459 case DUPLEX_UNFORCED: 460 /* normal duplex detection */ 461 break; 462 default: 463 return -EOPNOTSUPP; 464 } 465 466 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 467 if (err) 468 return err; 469 470 reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK | 471 MV88E6390_PORT_MAC_CTL_ALTSPEED | 472 MV88E6390_PORT_MAC_CTL_FORCE_SPEED); 473 474 if (speed != SPEED_UNFORCED) 475 reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; 476 477 reg |= ctrl; 478 479 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 480 if (err) 481 return err; 482 483 if (speed != SPEED_UNFORCED) 484 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); 485 else 486 dev_dbg(chip->dev, "p%d: Speed unforced\n", port); 487 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, 488 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", 489 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); 490 491 return 0; 492 } 493 494 phy_interface_t mv88e6393x_port_max_speed_mode(int port) 495 { 496 if (port == 0 || port == 9 || port == 10) 497 return PHY_INTERFACE_MODE_10GBASER; 498 499 return PHY_INTERFACE_MODE_NA; 500 } 501 502 static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 503 phy_interface_t mode, bool force) 504 { 505 u16 cmode; 506 int lane; 507 u16 reg; 508 int err; 509 510 /* Default to a slow mode, so freeing up SERDES interfaces for 511 * other ports which might use them for SFPs. 512 */ 513 if (mode == PHY_INTERFACE_MODE_NA) 514 mode = PHY_INTERFACE_MODE_1000BASEX; 515 516 switch (mode) { 517 case PHY_INTERFACE_MODE_RMII: 518 cmode = MV88E6XXX_PORT_STS_CMODE_RMII; 519 break; 520 case PHY_INTERFACE_MODE_1000BASEX: 521 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX; 522 break; 523 case PHY_INTERFACE_MODE_SGMII: 524 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; 525 break; 526 case PHY_INTERFACE_MODE_2500BASEX: 527 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; 528 break; 529 case PHY_INTERFACE_MODE_5GBASER: 530 cmode = MV88E6393X_PORT_STS_CMODE_5GBASER; 531 break; 532 case PHY_INTERFACE_MODE_XGMII: 533 case PHY_INTERFACE_MODE_XAUI: 534 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; 535 break; 536 case PHY_INTERFACE_MODE_RXAUI: 537 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; 538 break; 539 case PHY_INTERFACE_MODE_10GBASER: 540 cmode = MV88E6393X_PORT_STS_CMODE_10GBASER; 541 break; 542 default: 543 cmode = 0; 544 } 545 546 /* cmode doesn't change, nothing to do for us unless forced */ 547 if (cmode == chip->ports[port].cmode && !force) 548 return 0; 549 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane >= 0) { 552 if (chip->ports[port].serdes_irq) { 553 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 554 if (err) 555 return err; 556 } 557 558 err = mv88e6xxx_serdes_power_down(chip, port, lane); 559 if (err) 560 return err; 561 } 562 563 chip->ports[port].cmode = 0; 564 565 if (cmode) { 566 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 567 if (err) 568 return err; 569 570 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; 571 reg |= cmode; 572 573 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 574 if (err) 575 return err; 576 577 chip->ports[port].cmode = cmode; 578 579 lane = mv88e6xxx_serdes_get_lane(chip, port); 580 if (lane == -ENODEV) 581 return 0; 582 if (lane < 0) 583 return lane; 584 585 err = mv88e6xxx_serdes_power_up(chip, port, lane); 586 if (err) 587 return err; 588 589 if (chip->ports[port].serdes_irq) { 590 err = mv88e6xxx_serdes_irq_enable(chip, port, lane); 591 if (err) 592 return err; 593 } 594 } 595 596 return 0; 597 } 598 599 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 600 phy_interface_t mode) 601 { 602 if (port != 9 && port != 10) 603 return -EOPNOTSUPP; 604 605 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 606 } 607 608 int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 609 phy_interface_t mode) 610 { 611 if (port != 9 && port != 10) 612 return -EOPNOTSUPP; 613 614 switch (mode) { 615 case PHY_INTERFACE_MODE_NA: 616 return 0; 617 case PHY_INTERFACE_MODE_XGMII: 618 case PHY_INTERFACE_MODE_XAUI: 619 case PHY_INTERFACE_MODE_RXAUI: 620 return -EINVAL; 621 default: 622 break; 623 } 624 625 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 626 } 627 628 int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 629 phy_interface_t mode) 630 { 631 int err; 632 u16 reg; 633 634 if (port != 0 && port != 9 && port != 10) 635 return -EOPNOTSUPP; 636 637 /* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */ 638 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); 639 if (err) 640 return err; 641 642 reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE; 643 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE; 644 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); 645 if (err) 646 return err; 647 648 return mv88e6xxx_port_set_cmode(chip, port, mode, false); 649 } 650 651 static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip, 652 int port) 653 { 654 int err, addr; 655 u16 reg, bits; 656 657 if (port != 5) 658 return -EOPNOTSUPP; 659 660 addr = chip->info->port_base_addr + port; 661 662 err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); 663 if (err) 664 return err; 665 666 bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE | 667 MV88E6341_PORT_RESERVED_1A_SGMII_AN; 668 669 if ((reg & bits) == bits) 670 return 0; 671 672 reg |= bits; 673 return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); 674 } 675 676 int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 677 phy_interface_t mode) 678 { 679 int err; 680 681 if (port != 5) 682 return -EOPNOTSUPP; 683 684 switch (mode) { 685 case PHY_INTERFACE_MODE_NA: 686 return 0; 687 case PHY_INTERFACE_MODE_XGMII: 688 case PHY_INTERFACE_MODE_XAUI: 689 case PHY_INTERFACE_MODE_RXAUI: 690 return -EINVAL; 691 default: 692 break; 693 } 694 695 err = mv88e6341_port_set_cmode_writable(chip, port); 696 if (err) 697 return err; 698 699 return mv88e6xxx_port_set_cmode(chip, port, mode, true); 700 } 701 702 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 703 { 704 int err; 705 u16 reg; 706 707 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 708 if (err) 709 return err; 710 711 *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; 712 713 return 0; 714 } 715 716 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 717 { 718 int err; 719 u16 reg; 720 721 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 722 if (err) 723 return err; 724 725 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; 726 727 return 0; 728 } 729 730 /* Offset 0x02: Jamming Control 731 * 732 * Do not limit the period of time that this port can be paused for by 733 * the remote end or the period of time that this port can pause the 734 * remote end. 735 */ 736 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 737 u8 out) 738 { 739 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, 740 out << 8 | in); 741 } 742 743 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 744 u8 out) 745 { 746 int err; 747 748 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 749 MV88E6390_PORT_FLOW_CTL_UPDATE | 750 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); 751 if (err) 752 return err; 753 754 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, 755 MV88E6390_PORT_FLOW_CTL_UPDATE | 756 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); 757 } 758 759 /* Offset 0x04: Port Control Register */ 760 761 static const char * const mv88e6xxx_port_state_names[] = { 762 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", 763 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", 764 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", 765 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", 766 }; 767 768 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) 769 { 770 u16 reg; 771 int err; 772 773 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 774 if (err) 775 return err; 776 777 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; 778 779 switch (state) { 780 case BR_STATE_DISABLED: 781 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; 782 break; 783 case BR_STATE_BLOCKING: 784 case BR_STATE_LISTENING: 785 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 786 break; 787 case BR_STATE_LEARNING: 788 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 789 break; 790 case BR_STATE_FORWARDING: 791 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 792 break; 793 default: 794 return -EINVAL; 795 } 796 797 reg |= state; 798 799 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 800 if (err) 801 return err; 802 803 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, 804 mv88e6xxx_port_state_names[state]); 805 806 return 0; 807 } 808 809 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 810 enum mv88e6xxx_egress_mode mode) 811 { 812 int err; 813 u16 reg; 814 815 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 816 if (err) 817 return err; 818 819 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; 820 821 switch (mode) { 822 case MV88E6XXX_EGRESS_MODE_UNMODIFIED: 823 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; 824 break; 825 case MV88E6XXX_EGRESS_MODE_UNTAGGED: 826 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; 827 break; 828 case MV88E6XXX_EGRESS_MODE_TAGGED: 829 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; 830 break; 831 case MV88E6XXX_EGRESS_MODE_ETHERTYPE: 832 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; 833 break; 834 default: 835 return -EINVAL; 836 } 837 838 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 839 } 840 841 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 842 enum mv88e6xxx_frame_mode mode) 843 { 844 int err; 845 u16 reg; 846 847 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 848 if (err) 849 return err; 850 851 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 852 853 switch (mode) { 854 case MV88E6XXX_FRAME_MODE_NORMAL: 855 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 856 break; 857 case MV88E6XXX_FRAME_MODE_DSA: 858 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 859 break; 860 default: 861 return -EINVAL; 862 } 863 864 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 865 } 866 867 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 868 enum mv88e6xxx_frame_mode mode) 869 { 870 int err; 871 u16 reg; 872 873 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 874 if (err) 875 return err; 876 877 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; 878 879 switch (mode) { 880 case MV88E6XXX_FRAME_MODE_NORMAL: 881 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; 882 break; 883 case MV88E6XXX_FRAME_MODE_DSA: 884 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; 885 break; 886 case MV88E6XXX_FRAME_MODE_PROVIDER: 887 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; 888 break; 889 case MV88E6XXX_FRAME_MODE_ETHERTYPE: 890 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; 891 break; 892 default: 893 return -EINVAL; 894 } 895 896 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 897 } 898 899 int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 900 int port, bool unicast) 901 { 902 int err; 903 u16 reg; 904 905 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 906 if (err) 907 return err; 908 909 if (unicast) 910 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 911 else 912 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; 913 914 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 915 } 916 917 int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 918 bool unicast) 919 { 920 int err; 921 u16 reg; 922 923 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 924 if (err) 925 return err; 926 927 if (unicast) 928 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 929 else 930 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC; 931 932 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 933 } 934 935 int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 936 bool multicast) 937 { 938 int err; 939 u16 reg; 940 941 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 942 if (err) 943 return err; 944 945 if (multicast) 946 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 947 else 948 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC; 949 950 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 951 } 952 953 /* Offset 0x05: Port Control 1 */ 954 955 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 956 bool message_port) 957 { 958 u16 val; 959 int err; 960 961 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 962 if (err) 963 return err; 964 965 if (message_port) 966 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 967 else 968 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; 969 970 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 971 } 972 973 int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 974 bool trunk, u8 id) 975 { 976 u16 val; 977 int err; 978 979 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); 980 if (err) 981 return err; 982 983 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK; 984 985 if (trunk) 986 val |= MV88E6XXX_PORT_CTL1_TRUNK_PORT | 987 (id << MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT); 988 else 989 val &= ~MV88E6XXX_PORT_CTL1_TRUNK_PORT; 990 991 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); 992 } 993 994 /* Offset 0x06: Port Based VLAN Map */ 995 996 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) 997 { 998 const u16 mask = mv88e6xxx_port_mask(chip); 999 u16 reg; 1000 int err; 1001 1002 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1003 if (err) 1004 return err; 1005 1006 reg &= ~mask; 1007 reg |= map & mask; 1008 1009 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1010 if (err) 1011 return err; 1012 1013 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); 1014 1015 return 0; 1016 } 1017 1018 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) 1019 { 1020 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1021 u16 reg; 1022 int err; 1023 1024 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1025 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1026 if (err) 1027 return err; 1028 1029 *fid = (reg & 0xf000) >> 12; 1030 1031 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1032 if (upper_mask) { 1033 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1034 ®); 1035 if (err) 1036 return err; 1037 1038 *fid |= (reg & upper_mask) << 4; 1039 } 1040 1041 return 0; 1042 } 1043 1044 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) 1045 { 1046 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; 1047 u16 reg; 1048 int err; 1049 1050 if (fid >= mv88e6xxx_num_databases(chip)) 1051 return -EINVAL; 1052 1053 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ 1054 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); 1055 if (err) 1056 return err; 1057 1058 reg &= 0x0fff; 1059 reg |= (fid & 0x000f) << 12; 1060 1061 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); 1062 if (err) 1063 return err; 1064 1065 /* Port's default FID upper bits are located in reg 0x05, offset 0 */ 1066 if (upper_mask) { 1067 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, 1068 ®); 1069 if (err) 1070 return err; 1071 1072 reg &= ~upper_mask; 1073 reg |= (fid >> 4) & upper_mask; 1074 1075 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, 1076 reg); 1077 if (err) 1078 return err; 1079 } 1080 1081 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); 1082 1083 return 0; 1084 } 1085 1086 /* Offset 0x07: Default Port VLAN ID & Priority */ 1087 1088 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) 1089 { 1090 u16 reg; 1091 int err; 1092 1093 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1094 ®); 1095 if (err) 1096 return err; 1097 1098 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1099 1100 return 0; 1101 } 1102 1103 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) 1104 { 1105 u16 reg; 1106 int err; 1107 1108 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1109 ®); 1110 if (err) 1111 return err; 1112 1113 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1114 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; 1115 1116 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 1117 reg); 1118 if (err) 1119 return err; 1120 1121 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); 1122 1123 return 0; 1124 } 1125 1126 /* Offset 0x08: Port Control 2 Register */ 1127 1128 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1129 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", 1130 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", 1131 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", 1132 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", 1133 }; 1134 1135 int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 1136 int port, bool multicast) 1137 { 1138 int err; 1139 u16 reg; 1140 1141 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1142 if (err) 1143 return err; 1144 1145 if (multicast) 1146 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1147 else 1148 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; 1149 1150 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1151 } 1152 1153 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1154 int upstream_port) 1155 { 1156 int err; 1157 u16 reg; 1158 1159 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1160 if (err) 1161 return err; 1162 1163 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; 1164 reg |= upstream_port; 1165 1166 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1167 } 1168 1169 int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 1170 enum mv88e6xxx_egress_direction direction, 1171 bool mirror) 1172 { 1173 bool *mirror_port; 1174 u16 reg; 1175 u16 bit; 1176 int err; 1177 1178 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1179 if (err) 1180 return err; 1181 1182 switch (direction) { 1183 case MV88E6XXX_EGRESS_DIR_INGRESS: 1184 bit = MV88E6XXX_PORT_CTL2_INGRESS_MONITOR; 1185 mirror_port = &chip->ports[port].mirror_ingress; 1186 break; 1187 case MV88E6XXX_EGRESS_DIR_EGRESS: 1188 bit = MV88E6XXX_PORT_CTL2_EGRESS_MONITOR; 1189 mirror_port = &chip->ports[port].mirror_egress; 1190 break; 1191 default: 1192 return -EINVAL; 1193 } 1194 1195 reg &= ~bit; 1196 if (mirror) 1197 reg |= bit; 1198 1199 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1200 if (!err) 1201 *mirror_port = mirror; 1202 1203 return err; 1204 } 1205 1206 int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 1207 bool locked) 1208 { 1209 u16 reg; 1210 int err; 1211 1212 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); 1213 if (err) 1214 return err; 1215 1216 reg &= ~MV88E6XXX_PORT_CTL0_SA_FILT_MASK; 1217 if (locked) 1218 reg |= MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK; 1219 1220 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1221 if (err) 1222 return err; 1223 1224 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, ®); 1225 if (err) 1226 return err; 1227 1228 reg &= ~MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1229 if (locked) 1230 reg |= MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT; 1231 1232 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, reg); 1233 } 1234 1235 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 1236 u16 mode) 1237 { 1238 u16 reg; 1239 int err; 1240 1241 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1242 if (err) 1243 return err; 1244 1245 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1246 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; 1247 1248 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1249 if (err) 1250 return err; 1251 1252 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, 1253 mv88e6xxx_port_8021q_mode_names[mode]); 1254 1255 return 0; 1256 } 1257 1258 int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 1259 bool drop_untagged) 1260 { 1261 u16 old, new; 1262 int err; 1263 1264 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); 1265 if (err) 1266 return err; 1267 1268 if (drop_untagged) 1269 new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1270 else 1271 new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; 1272 1273 if (new == old) 1274 return 0; 1275 1276 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); 1277 } 1278 1279 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map) 1280 { 1281 u16 reg; 1282 int err; 1283 1284 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1285 if (err) 1286 return err; 1287 1288 if (map) 1289 reg |= MV88E6XXX_PORT_CTL2_MAP_DA; 1290 else 1291 reg &= ~MV88E6XXX_PORT_CTL2_MAP_DA; 1292 1293 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1294 } 1295 1296 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 1297 size_t size) 1298 { 1299 u16 reg; 1300 int err; 1301 1302 size += VLAN_ETH_HLEN + ETH_FCS_LEN; 1303 1304 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); 1305 if (err) 1306 return err; 1307 1308 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; 1309 1310 if (size <= 1522) 1311 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; 1312 else if (size <= 2048) 1313 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; 1314 else if (size <= 10240) 1315 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; 1316 else 1317 return -ERANGE; 1318 1319 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); 1320 } 1321 1322 /* Offset 0x09: Port Rate Control */ 1323 1324 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1325 { 1326 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1327 0x0000); 1328 } 1329 1330 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 1331 { 1332 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, 1333 0x0001); 1334 } 1335 1336 /* Offset 0x0B: Port Association Vector */ 1337 1338 int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 1339 u16 pav) 1340 { 1341 u16 reg, mask; 1342 int err; 1343 1344 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1345 ®); 1346 if (err) 1347 return err; 1348 1349 mask = mv88e6xxx_port_mask(chip); 1350 reg &= ~mask; 1351 reg |= pav & mask; 1352 1353 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1354 reg); 1355 } 1356 1357 /* Offset 0x0C: Port ATU Control */ 1358 1359 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) 1360 { 1361 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); 1362 } 1363 1364 /* Offset 0x0D: (Priority) Override Register */ 1365 1366 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) 1367 { 1368 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); 1369 } 1370 1371 /* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X */ 1372 1373 static int mv88e6393x_port_policy_read(struct mv88e6xxx_chip *chip, int port, 1374 u16 pointer, u8 *data) 1375 { 1376 u16 reg; 1377 int err; 1378 1379 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1380 pointer); 1381 if (err) 1382 return err; 1383 1384 err = mv88e6xxx_port_read(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1385 ®); 1386 if (err) 1387 return err; 1388 1389 *data = reg; 1390 1391 return 0; 1392 } 1393 1394 static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, int port, 1395 u16 pointer, u8 data) 1396 { 1397 u16 reg; 1398 1399 reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data; 1400 1401 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, 1402 reg); 1403 } 1404 1405 static int mv88e6393x_port_policy_write_all(struct mv88e6xxx_chip *chip, 1406 u16 pointer, u8 data) 1407 { 1408 int err, port; 1409 1410 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1411 if (dsa_is_unused_port(chip->ds, port)) 1412 continue; 1413 1414 err = mv88e6393x_port_policy_write(chip, port, pointer, data); 1415 if (err) 1416 return err; 1417 } 1418 1419 return 0; 1420 } 1421 1422 int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 1423 enum mv88e6xxx_egress_direction direction, 1424 int port) 1425 { 1426 u16 ptr; 1427 int err; 1428 1429 switch (direction) { 1430 case MV88E6XXX_EGRESS_DIR_INGRESS: 1431 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST; 1432 err = mv88e6393x_port_policy_write_all(chip, ptr, port); 1433 if (err) 1434 return err; 1435 break; 1436 case MV88E6XXX_EGRESS_DIR_EGRESS: 1437 ptr = MV88E6393X_G2_EGRESS_MONITOR_DEST; 1438 err = mv88e6xxx_g2_write(chip, ptr, port); 1439 if (err) 1440 return err; 1441 break; 1442 } 1443 1444 return 0; 1445 } 1446 1447 int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 1448 int upstream_port) 1449 { 1450 u16 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST; 1451 u8 data = MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI | 1452 upstream_port; 1453 1454 return mv88e6393x_port_policy_write(chip, port, ptr, data); 1455 } 1456 1457 int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 1458 { 1459 u16 ptr; 1460 int err; 1461 1462 /* Consider the frames with reserved multicast destination 1463 * addresses matching 01:80:c2:00:00:00 and 1464 * 01:80:c2:00:00:02 as MGMT. 1465 */ 1466 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO; 1467 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1468 if (err) 1469 return err; 1470 1471 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI; 1472 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1473 if (err) 1474 return err; 1475 1476 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO; 1477 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1478 if (err) 1479 return err; 1480 1481 ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI; 1482 err = mv88e6393x_port_policy_write_all(chip, ptr, 0xff); 1483 if (err) 1484 return err; 1485 1486 return 0; 1487 } 1488 1489 /* Offset 0x10 & 0x11: EPC */ 1490 1491 static int mv88e6393x_port_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) 1492 { 1493 int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); 1494 1495 return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); 1496 } 1497 1498 /* Port Ether type for 6393X family */ 1499 1500 int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1501 u16 etype) 1502 { 1503 u16 val; 1504 int err; 1505 1506 err = mv88e6393x_port_epc_wait_ready(chip, port); 1507 if (err) 1508 return err; 1509 1510 err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_DATA, etype); 1511 if (err) 1512 return err; 1513 1514 val = MV88E6393X_PORT_EPC_CMD_BUSY | 1515 MV88E6393X_PORT_EPC_CMD_WRITE | 1516 MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE; 1517 1518 return mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val); 1519 } 1520 1521 /* Offset 0x0f: Port Ether type */ 1522 1523 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 1524 u16 etype) 1525 { 1526 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); 1527 } 1528 1529 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] 1530 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] 1531 */ 1532 1533 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1534 { 1535 int err; 1536 1537 /* Use a direct priority mapping for all IEEE tagged frames */ 1538 err = mv88e6xxx_port_write(chip, port, 1539 MV88E6095_PORT_IEEE_PRIO_REMAP_0123, 1540 0x3210); 1541 if (err) 1542 return err; 1543 1544 return mv88e6xxx_port_write(chip, port, 1545 MV88E6095_PORT_IEEE_PRIO_REMAP_4567, 1546 0x7654); 1547 } 1548 1549 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, 1550 int port, u16 table, u8 ptr, u16 data) 1551 { 1552 u16 reg; 1553 1554 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | 1555 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | 1556 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); 1557 1558 return mv88e6xxx_port_write(chip, port, 1559 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); 1560 } 1561 1562 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) 1563 { 1564 int err, i; 1565 u16 table; 1566 1567 for (i = 0; i <= 7; i++) { 1568 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; 1569 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, 1570 (i | i << 4)); 1571 if (err) 1572 return err; 1573 1574 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; 1575 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1576 if (err) 1577 return err; 1578 1579 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; 1580 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1581 if (err) 1582 return err; 1583 1584 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; 1585 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); 1586 if (err) 1587 return err; 1588 } 1589 1590 return 0; 1591 } 1592 1593 /* Offset 0x0E: Policy Control Register */ 1594 1595 static int 1596 mv88e6xxx_port_policy_mapping_get_pos(enum mv88e6xxx_policy_mapping mapping, 1597 enum mv88e6xxx_policy_action action, 1598 u16 *mask, u16 *val, int *shift) 1599 { 1600 switch (mapping) { 1601 case MV88E6XXX_POLICY_MAPPING_DA: 1602 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_DA_MASK); 1603 *mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; 1604 break; 1605 case MV88E6XXX_POLICY_MAPPING_SA: 1606 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_SA_MASK); 1607 *mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; 1608 break; 1609 case MV88E6XXX_POLICY_MAPPING_VTU: 1610 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VTU_MASK); 1611 *mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; 1612 break; 1613 case MV88E6XXX_POLICY_MAPPING_ETYPE: 1614 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK); 1615 *mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; 1616 break; 1617 case MV88E6XXX_POLICY_MAPPING_PPPOE: 1618 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK); 1619 *mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; 1620 break; 1621 case MV88E6XXX_POLICY_MAPPING_VBAS: 1622 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK); 1623 *mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; 1624 break; 1625 case MV88E6XXX_POLICY_MAPPING_OPT82: 1626 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK); 1627 *mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; 1628 break; 1629 case MV88E6XXX_POLICY_MAPPING_UDP: 1630 *shift = __bf_shf(MV88E6XXX_PORT_POLICY_CTL_UDP_MASK); 1631 *mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; 1632 break; 1633 default: 1634 return -EOPNOTSUPP; 1635 } 1636 1637 switch (action) { 1638 case MV88E6XXX_POLICY_ACTION_NORMAL: 1639 *val = MV88E6XXX_PORT_POLICY_CTL_NORMAL; 1640 break; 1641 case MV88E6XXX_POLICY_ACTION_MIRROR: 1642 *val = MV88E6XXX_PORT_POLICY_CTL_MIRROR; 1643 break; 1644 case MV88E6XXX_POLICY_ACTION_TRAP: 1645 *val = MV88E6XXX_PORT_POLICY_CTL_TRAP; 1646 break; 1647 case MV88E6XXX_POLICY_ACTION_DISCARD: 1648 *val = MV88E6XXX_PORT_POLICY_CTL_DISCARD; 1649 break; 1650 default: 1651 return -EOPNOTSUPP; 1652 } 1653 1654 return 0; 1655 } 1656 1657 int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1658 enum mv88e6xxx_policy_mapping mapping, 1659 enum mv88e6xxx_policy_action action) 1660 { 1661 u16 reg, mask, val; 1662 int shift; 1663 int err; 1664 1665 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1666 &val, &shift); 1667 if (err) 1668 return err; 1669 1670 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); 1671 if (err) 1672 return err; 1673 1674 reg &= ~mask; 1675 reg |= (val << shift) & mask; 1676 1677 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); 1678 } 1679 1680 int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 1681 enum mv88e6xxx_policy_mapping mapping, 1682 enum mv88e6xxx_policy_action action) 1683 { 1684 u16 mask, val; 1685 int shift; 1686 int err; 1687 u16 ptr; 1688 u8 reg; 1689 1690 err = mv88e6xxx_port_policy_mapping_get_pos(mapping, action, &mask, 1691 &val, &shift); 1692 if (err) 1693 return err; 1694 1695 /* The 16-bit Port Policy CTL register from older chips is on 6393x 1696 * changed to Port Policy MGMT CTL, which can access more data, but 1697 * indirectly. The original 16-bit value is divided into two 8-bit 1698 * registers. 1699 */ 1700 ptr = shift / 8; 1701 shift %= 8; 1702 mask >>= ptr * 8; 1703 1704 err = mv88e6393x_port_policy_read(chip, port, ptr, ®); 1705 if (err) 1706 return err; 1707 1708 reg &= ~mask; 1709 reg |= (val << shift) & mask; 1710 1711 return mv88e6393x_port_policy_write(chip, port, ptr, reg); 1712 } 1713