1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Switch hardware timestamping support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2017 National Instruments 8 * Erik Hons <erik.hons@ni.com> 9 * Brandon Streiff <brandon.streiff@ni.com> 10 * Dane Wagner <dane.wagner@ni.com> 11 */ 12 13 #ifndef _MV88E6XXX_HWTSTAMP_H 14 #define _MV88E6XXX_HWTSTAMP_H 15 16 #include "chip.h" 17 18 /* Global 6352 PTP registers */ 19 /* Offset 0x00: PTP EtherType */ 20 #define MV88E6XXX_PTP_ETHERTYPE 0x00 21 22 /* Offset 0x01: Message Type Timestamp Enables */ 23 #define MV88E6XXX_PTP_MSGTYPE 0x01 24 #define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001 25 #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002 26 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004 27 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008 28 #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f 29 30 /* Offset 0x02: Timestamp Arrival Capture Pointers */ 31 #define MV88E6XXX_PTP_TS_ARRIVAL_PTR 0x02 32 33 /* Offset 0x05: PTP Global Configuration */ 34 #define MV88E6165_PTP_CFG 0x05 35 #define MV88E6165_PTP_CFG_TSPEC_MASK 0xf000 36 #define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE BIT(1) 37 #define MV88E6165_PTP_CFG_DISABLE_PTP BIT(0) 38 39 /* Offset 0x07: PTP Global Configuration */ 40 #define MV88E6341_PTP_CFG 0x07 41 #define MV88E6341_PTP_CFG_UPDATE 0x8000 42 #define MV88E6341_PTP_CFG_IDX_MASK 0x7f00 43 #define MV88E6341_PTP_CFG_DATA_MASK 0x00ff 44 #define MV88E6341_PTP_CFG_MODE_IDX 0x0 45 #define MV88E6341_PTP_CFG_MODE_TS_AT_PHY 0x00 46 #define MV88E6341_PTP_CFG_MODE_TS_AT_MAC 0x80 47 48 /* Offset 0x08: PTP Interrupt Status */ 49 #define MV88E6XXX_PTP_IRQ_STATUS 0x08 50 51 /* Per-Port 6352 PTP Registers */ 52 /* Offset 0x00: PTP Configuration 0 */ 53 #define MV88E6XXX_PORT_PTP_CFG0 0x00 54 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT 12 55 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK 0xf000 56 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 0x0000 57 #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS 0x1000 58 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH 0x0800 59 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE 0x0002 60 #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP 0x0001 61 62 /* Offset 0x01: PTP Configuration 1 */ 63 #define MV88E6XXX_PORT_PTP_CFG1 0x01 64 65 /* Offset 0x02: PTP Configuration 2 */ 66 #define MV88E6XXX_PORT_PTP_CFG2 0x02 67 #define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL 0x1000 68 #define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN 0x0002 69 #define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN 0x0001 70 71 /* Offset 0x03: PTP LED Configuration */ 72 #define MV88E6XXX_PORT_PTP_LED_CFG 0x03 73 74 /* Offset 0x08: PTP Arrival 0 Status */ 75 #define MV88E6XXX_PORT_PTP_ARR0_STS 0x08 76 77 /* Offset 0x09/0x0A: PTP Arrival 0 Time */ 78 #define MV88E6XXX_PORT_PTP_ARR0_TIME_LO 0x09 79 #define MV88E6XXX_PORT_PTP_ARR0_TIME_HI 0x0a 80 81 /* Offset 0x0B: PTP Arrival 0 Sequence ID */ 82 #define MV88E6XXX_PORT_PTP_ARR0_SEQID 0x0b 83 84 /* Offset 0x0C: PTP Arrival 1 Status */ 85 #define MV88E6XXX_PORT_PTP_ARR1_STS 0x0c 86 87 /* Offset 0x0D/0x0E: PTP Arrival 1 Time */ 88 #define MV88E6XXX_PORT_PTP_ARR1_TIME_LO 0x0d 89 #define MV88E6XXX_PORT_PTP_ARR1_TIME_HI 0x0e 90 91 /* Offset 0x0F: PTP Arrival 1 Sequence ID */ 92 #define MV88E6XXX_PORT_PTP_ARR1_SEQID 0x0f 93 94 /* Offset 0x10: PTP Departure Status */ 95 #define MV88E6XXX_PORT_PTP_DEP_STS 0x10 96 97 /* Offset 0x11/0x12: PTP Deperture Time */ 98 #define MV88E6XXX_PORT_PTP_DEP_TIME_LO 0x11 99 #define MV88E6XXX_PORT_PTP_DEP_TIME_HI 0x12 100 101 /* Offset 0x13: PTP Departure Sequence ID */ 102 #define MV88E6XXX_PORT_PTP_DEP_SEQID 0x13 103 104 /* Status fields for arrival and depature timestamp status registers */ 105 #define MV88E6XXX_PTP_TS_STATUS_MASK 0x0006 106 #define MV88E6XXX_PTP_TS_STATUS_NORMAL 0x0000 107 #define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN 0x0002 108 #define MV88E6XXX_PTP_TS_STATUS_DISCARDED 0x0004 109 #define MV88E6XXX_PTP_TS_VALID 0x0001 110 111 #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP 112 113 int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port, 114 struct ifreq *ifr); 115 int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port, 116 struct ifreq *ifr); 117 118 bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 119 struct sk_buff *clone, unsigned int type); 120 void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 121 struct sk_buff *skb); 122 123 int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 124 struct kernel_ethtool_ts_info *info); 125 126 int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip); 127 void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip); 128 int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port); 129 int mv88e6352_hwtstamp_port_disable(struct mv88e6xxx_chip *chip, int port); 130 int mv88e6165_global_enable(struct mv88e6xxx_chip *chip); 131 int mv88e6165_global_disable(struct mv88e6xxx_chip *chip); 132 133 #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ 134 135 static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, 136 int port, struct ifreq *ifr) 137 { 138 return -EOPNOTSUPP; 139 } 140 141 static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, 142 int port, struct ifreq *ifr) 143 { 144 return -EOPNOTSUPP; 145 } 146 147 static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port, 148 struct sk_buff *clone, 149 unsigned int type) 150 { 151 return false; 152 } 153 154 static inline void mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port, 155 struct sk_buff *skb) 156 { 157 } 158 159 static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port, 160 struct kernel_ethtool_ts_info *info) 161 { 162 return -EOPNOTSUPP; 163 } 164 165 static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip) 166 { 167 return 0; 168 } 169 170 static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip) 171 { 172 } 173 174 #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ 175 176 #endif /* _MV88E6XXX_HWTSTAMP_H */ 177