1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6085, 58 MV88E6095, 59 MV88E6097, 60 MV88E6123, 61 MV88E6131, 62 MV88E6141, 63 MV88E6161, 64 MV88E6165, 65 MV88E6171, 66 MV88E6172, 67 MV88E6175, 68 MV88E6176, 69 MV88E6185, 70 MV88E6190, 71 MV88E6190X, 72 MV88E6191, 73 MV88E6191X, 74 MV88E6193X, 75 MV88E6220, 76 MV88E6240, 77 MV88E6250, 78 MV88E6290, 79 MV88E6320, 80 MV88E6321, 81 MV88E6341, 82 MV88E6350, 83 MV88E6351, 84 MV88E6352, 85 MV88E6390, 86 MV88E6390X, 87 MV88E6393X, 88 }; 89 90 enum mv88e6xxx_family { 91 MV88E6XXX_FAMILY_NONE, 92 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 93 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 94 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 95 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 96 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 97 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 103 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ 104 }; 105 106 /** 107 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 108 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 109 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 110 * egressing FORWARD frames with an EDSA 111 * tag is reserved for future use, but 112 * empirical data shows that this mode 113 * is supported. 114 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 115 */ 116 enum mv88e6xxx_edsa_support { 117 MV88E6XXX_EDSA_UNSUPPORTED = 0, 118 MV88E6XXX_EDSA_UNDOCUMENTED, 119 MV88E6XXX_EDSA_SUPPORTED, 120 }; 121 122 struct mv88e6xxx_ops; 123 124 struct mv88e6xxx_info { 125 enum mv88e6xxx_family family; 126 u16 prod_num; 127 const char *name; 128 unsigned int num_databases; 129 unsigned int num_macs; 130 unsigned int num_ports; 131 unsigned int num_internal_phys; 132 unsigned int num_gpio; 133 unsigned int max_vid; 134 unsigned int max_sid; 135 unsigned int port_base_addr; 136 unsigned int phy_base_addr; 137 unsigned int global1_addr; 138 unsigned int global2_addr; 139 unsigned int age_time_coeff; 140 unsigned int g1_irqs; 141 unsigned int g2_irqs; 142 bool pvt; 143 144 /* Mark certain ports as invalid. This is required for example for the 145 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 146 * ports 2-4 are not routet to pins. 147 */ 148 unsigned int invalid_port_mask; 149 /* Multi-chip Addressing Mode. 150 * Some chips respond to only 2 registers of its own SMI device address 151 * when it is non-zero, and use indirect access to internal registers. 152 */ 153 bool multi_chip; 154 /* Dual-chip Addressing Mode 155 * Some chips respond to only half of the 32 SMI addresses, 156 * allowing two to coexist on the same SMI interface. 157 */ 158 bool dual_chip; 159 160 enum mv88e6xxx_edsa_support edsa_support; 161 162 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 163 * operation. 0 means that the ATU Move operation is not supported. 164 */ 165 u8 atu_move_port_mask; 166 const struct mv88e6xxx_ops *ops; 167 168 /* Supports PTP */ 169 bool ptp_support; 170 }; 171 172 struct mv88e6xxx_atu_entry { 173 u8 state; 174 bool trunk; 175 u16 portvec; 176 u8 mac[ETH_ALEN]; 177 }; 178 179 struct mv88e6xxx_vtu_entry { 180 u16 vid; 181 u16 fid; 182 u8 sid; 183 bool valid; 184 bool policy; 185 u8 member[DSA_MAX_PORTS]; 186 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 187 }; 188 189 struct mv88e6xxx_stu_entry { 190 u8 sid; 191 bool valid; 192 u8 state[DSA_MAX_PORTS]; 193 }; 194 195 struct mv88e6xxx_bus_ops; 196 struct mv88e6xxx_irq_ops; 197 struct mv88e6xxx_gpio_ops; 198 struct mv88e6xxx_avb_ops; 199 struct mv88e6xxx_ptp_ops; 200 201 struct mv88e6xxx_irq { 202 u16 masked; 203 struct irq_chip chip; 204 struct irq_domain *domain; 205 int nirqs; 206 }; 207 208 /* state flags for mv88e6xxx_port_hwtstamp::state */ 209 enum { 210 MV88E6XXX_HWTSTAMP_ENABLED, 211 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 212 }; 213 214 struct mv88e6xxx_port_hwtstamp { 215 /* Port index */ 216 int port_id; 217 218 /* Timestamping state */ 219 unsigned long state; 220 221 /* Resources for receive timestamping */ 222 struct sk_buff_head rx_queue; 223 struct sk_buff_head rx_queue2; 224 225 /* Resources for transmit timestamping */ 226 unsigned long tx_tstamp_start; 227 struct sk_buff *tx_skb; 228 u16 tx_seq_id; 229 230 /* Current timestamp configuration */ 231 struct hwtstamp_config tstamp_config; 232 }; 233 234 enum mv88e6xxx_policy_mapping { 235 MV88E6XXX_POLICY_MAPPING_DA, 236 MV88E6XXX_POLICY_MAPPING_SA, 237 MV88E6XXX_POLICY_MAPPING_VTU, 238 MV88E6XXX_POLICY_MAPPING_ETYPE, 239 MV88E6XXX_POLICY_MAPPING_PPPOE, 240 MV88E6XXX_POLICY_MAPPING_VBAS, 241 MV88E6XXX_POLICY_MAPPING_OPT82, 242 MV88E6XXX_POLICY_MAPPING_UDP, 243 }; 244 245 enum mv88e6xxx_policy_action { 246 MV88E6XXX_POLICY_ACTION_NORMAL, 247 MV88E6XXX_POLICY_ACTION_MIRROR, 248 MV88E6XXX_POLICY_ACTION_TRAP, 249 MV88E6XXX_POLICY_ACTION_DISCARD, 250 }; 251 252 struct mv88e6xxx_policy { 253 enum mv88e6xxx_policy_mapping mapping; 254 enum mv88e6xxx_policy_action action; 255 struct ethtool_rx_flow_spec fs; 256 u8 addr[ETH_ALEN]; 257 int port; 258 u16 vid; 259 }; 260 261 struct mv88e6xxx_vlan { 262 u16 vid; 263 bool valid; 264 }; 265 266 struct mv88e6xxx_port { 267 struct mv88e6xxx_chip *chip; 268 int port; 269 struct mv88e6xxx_vlan bridge_pvid; 270 u64 serdes_stats[2]; 271 u64 atu_member_violation; 272 u64 atu_miss_violation; 273 u64 atu_full_violation; 274 u64 vtu_member_violation; 275 u64 vtu_miss_violation; 276 phy_interface_t interface; 277 u8 cmode; 278 bool mirror_ingress; 279 bool mirror_egress; 280 unsigned int serdes_irq; 281 char serdes_irq_name[64]; 282 struct devlink_region *region; 283 }; 284 285 enum mv88e6xxx_region_id { 286 MV88E6XXX_REGION_GLOBAL1 = 0, 287 MV88E6XXX_REGION_GLOBAL2, 288 MV88E6XXX_REGION_ATU, 289 MV88E6XXX_REGION_VTU, 290 MV88E6XXX_REGION_STU, 291 MV88E6XXX_REGION_PVT, 292 293 _MV88E6XXX_REGION_MAX, 294 }; 295 296 struct mv88e6xxx_region_priv { 297 enum mv88e6xxx_region_id id; 298 }; 299 300 struct mv88e6xxx_mst { 301 struct list_head node; 302 303 refcount_t refcnt; 304 struct net_device *br; 305 u16 msti; 306 307 struct mv88e6xxx_stu_entry stu; 308 }; 309 310 struct mv88e6xxx_chip { 311 const struct mv88e6xxx_info *info; 312 313 /* Currently configured tagging protocol */ 314 enum dsa_tag_protocol tag_protocol; 315 316 /* The dsa_switch this private structure is related to */ 317 struct dsa_switch *ds; 318 319 /* The device this structure is associated to */ 320 struct device *dev; 321 322 /* This mutex protects the access to the switch registers */ 323 struct mutex reg_lock; 324 325 /* The MII bus and the address on the bus that is used to 326 * communication with the switch 327 */ 328 const struct mv88e6xxx_bus_ops *smi_ops; 329 struct mii_bus *bus; 330 int sw_addr; 331 332 /* Handles automatic disabling and re-enabling of the PHY 333 * polling unit. 334 */ 335 const struct mv88e6xxx_bus_ops *phy_ops; 336 struct mutex ppu_mutex; 337 int ppu_disabled; 338 struct work_struct ppu_work; 339 struct timer_list ppu_timer; 340 341 /* This mutex serialises access to the statistics unit. 342 * Hold this mutex over snapshot + dump sequences. 343 */ 344 struct mutex stats_mutex; 345 346 /* A switch may have a GPIO line tied to its reset pin. Parse 347 * this from the device tree, and use it before performing 348 * switch soft reset. 349 */ 350 struct gpio_desc *reset; 351 352 /* set to size of eeprom if supported by the switch */ 353 u32 eeprom_len; 354 355 /* List of mdio busses */ 356 struct list_head mdios; 357 358 /* Policy Control List IDs and rules */ 359 struct idr policies; 360 361 /* There can be two interrupt controllers, which are chained 362 * off a GPIO as interrupt source 363 */ 364 struct mv88e6xxx_irq g1_irq; 365 struct mv88e6xxx_irq g2_irq; 366 int irq; 367 char irq_name[64]; 368 int device_irq; 369 char device_irq_name[64]; 370 int watchdog_irq; 371 char watchdog_irq_name[64]; 372 373 int atu_prob_irq; 374 char atu_prob_irq_name[64]; 375 int vtu_prob_irq; 376 char vtu_prob_irq_name[64]; 377 struct kthread_worker *kworker; 378 struct kthread_delayed_work irq_poll_work; 379 380 /* GPIO resources */ 381 u8 gpio_data[2]; 382 383 /* This cyclecounter abstracts the switch PTP time. 384 * reg_lock must be held for any operation that read()s. 385 */ 386 struct cyclecounter tstamp_cc; 387 struct timecounter tstamp_tc; 388 struct delayed_work overflow_work; 389 390 struct ptp_clock *ptp_clock; 391 struct ptp_clock_info ptp_clock_info; 392 struct delayed_work tai_event_work; 393 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 394 u16 trig_config; 395 u16 evcap_config; 396 u16 enable_count; 397 398 /* Current ingress and egress monitor ports */ 399 int egress_dest_port; 400 int ingress_dest_port; 401 402 /* Per-port timestamping resources. */ 403 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 404 405 /* Array of port structures. */ 406 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 407 408 /* devlink regions */ 409 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 410 411 /* Bridge MST to SID mappings */ 412 struct list_head msts; 413 }; 414 415 struct mv88e6xxx_bus_ops { 416 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 417 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 418 int (*init)(struct mv88e6xxx_chip *chip); 419 }; 420 421 struct mv88e6xxx_mdio_bus { 422 struct mii_bus *bus; 423 struct mv88e6xxx_chip *chip; 424 struct list_head list; 425 bool external; 426 }; 427 428 struct mv88e6xxx_ops { 429 /* Switch Setup Errata, called early in the switch setup to 430 * allow any errata actions to be performed 431 */ 432 int (*setup_errata)(struct mv88e6xxx_chip *chip); 433 434 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 435 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 436 437 /* Ingress Rate Limit unit (IRL) operations */ 438 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 439 440 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 441 struct ethtool_eeprom *eeprom, u8 *data); 442 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 443 struct ethtool_eeprom *eeprom, u8 *data); 444 445 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 446 447 int (*phy_read)(struct mv88e6xxx_chip *chip, 448 struct mii_bus *bus, 449 int addr, int reg, u16 *val); 450 int (*phy_write)(struct mv88e6xxx_chip *chip, 451 struct mii_bus *bus, 452 int addr, int reg, u16 val); 453 454 /* Priority Override Table operations */ 455 int (*pot_clear)(struct mv88e6xxx_chip *chip); 456 457 /* PHY Polling Unit (PPU) operations */ 458 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 459 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 460 461 /* Switch Software Reset */ 462 int (*reset)(struct mv88e6xxx_chip *chip); 463 464 /* RGMII Receive/Transmit Timing Control 465 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 466 */ 467 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 468 phy_interface_t mode); 469 470 #define LINK_FORCED_DOWN 0 471 #define LINK_FORCED_UP 1 472 #define LINK_UNFORCED -2 473 474 /* Port's MAC link state 475 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 476 * or LINK_UNFORCED for normal link detection. 477 */ 478 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 479 480 /* Synchronise the port link state with that of the SERDES 481 */ 482 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 483 484 #define PAUSE_ON 1 485 #define PAUSE_OFF 0 486 487 /* Enable/disable sending Pause */ 488 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 489 int pause); 490 491 #define SPEED_MAX INT_MAX 492 #define SPEED_UNFORCED -2 493 #define DUPLEX_UNFORCED -2 494 495 /* Port's MAC speed (in Mbps) and MAC duplex mode 496 * 497 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 498 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 499 * 500 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 501 * or DUPLEX_UNFORCED for normal duplex detection. 502 */ 503 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 504 int speed, int duplex); 505 506 /* What interface mode should be used for maximum speed? */ 507 phy_interface_t (*port_max_speed_mode)(int port); 508 509 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 510 511 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 512 enum mv88e6xxx_policy_mapping mapping, 513 enum mv88e6xxx_policy_action action); 514 515 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 516 enum mv88e6xxx_frame_mode mode); 517 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 518 bool unicast); 519 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 520 bool multicast); 521 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 522 u16 etype); 523 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 524 size_t size); 525 526 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 527 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 528 u8 out); 529 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 530 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 531 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 532 533 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 534 * Some chips allow this to be configured on specific ports. 535 */ 536 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 537 phy_interface_t mode); 538 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 539 540 /* Some devices have a per port register indicating what is 541 * the upstream port this port should forward to. 542 */ 543 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 544 int upstream_port); 545 546 /* Snapshot the statistics for a port. The statistics can then 547 * be read back a leisure but still with a consistent view. 548 */ 549 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 550 551 /* Set the histogram mode for statistics, when the control registers 552 * are separated out of the STATS_OP register. 553 */ 554 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 555 556 /* Return the number of strings describing statistics */ 557 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 558 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 559 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 560 uint64_t *data); 561 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 562 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 563 enum mv88e6xxx_egress_direction direction, 564 int port); 565 566 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 567 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 568 569 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 570 571 const struct mv88e6xxx_irq_ops *watchdog_ops; 572 573 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 574 575 /* Power on/off a SERDES interface */ 576 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 577 bool up); 578 579 /* SERDES lane mapping */ 580 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 581 582 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 583 int lane, struct phylink_link_state *state); 584 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 585 int lane, unsigned int mode, 586 phy_interface_t interface, 587 const unsigned long *advertise); 588 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 589 int lane); 590 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 591 int lane, int speed, int duplex); 592 593 /* SERDES interrupt handling */ 594 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 595 int port); 596 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 597 bool enable); 598 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 599 int lane); 600 601 /* Statistics from the SERDES interface */ 602 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 603 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 604 uint8_t *data); 605 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 606 uint64_t *data); 607 608 /* SERDES registers for ethtool */ 609 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 610 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 611 void *_p); 612 613 /* SERDES SGMII/Fiber Output Amplitude */ 614 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 615 int val); 616 617 /* Address Translation Unit operations */ 618 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 619 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 620 621 /* VLAN Translation Unit operations */ 622 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 623 struct mv88e6xxx_vtu_entry *entry); 624 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 625 struct mv88e6xxx_vtu_entry *entry); 626 627 /* Spanning Tree Unit operations */ 628 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 629 struct mv88e6xxx_stu_entry *entry); 630 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 631 struct mv88e6xxx_stu_entry *entry); 632 633 /* GPIO operations */ 634 const struct mv88e6xxx_gpio_ops *gpio_ops; 635 636 /* Interface to the AVB/PTP registers */ 637 const struct mv88e6xxx_avb_ops *avb_ops; 638 639 /* Remote Management Unit operations */ 640 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 641 642 /* Precision Time Protocol operations */ 643 const struct mv88e6xxx_ptp_ops *ptp_ops; 644 645 /* Phylink */ 646 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 647 struct phylink_config *config); 648 649 /* Max Frame Size */ 650 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 651 }; 652 653 struct mv88e6xxx_irq_ops { 654 /* Action to be performed when the interrupt happens */ 655 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 656 /* Setup the hardware to generate the interrupt */ 657 int (*irq_setup)(struct mv88e6xxx_chip *chip); 658 /* Reset the hardware to stop generating the interrupt */ 659 void (*irq_free)(struct mv88e6xxx_chip *chip); 660 }; 661 662 struct mv88e6xxx_gpio_ops { 663 /* Get/set data on GPIO pin */ 664 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 665 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 666 int value); 667 668 /* get/set GPIO direction */ 669 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 670 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 671 bool input); 672 673 /* get/set GPIO pin control */ 674 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 675 int *func); 676 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 677 int func); 678 }; 679 680 struct mv88e6xxx_avb_ops { 681 /* Access port-scoped Precision Time Protocol registers */ 682 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 683 u16 *data, int len); 684 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 685 u16 data); 686 687 /* Access global Precision Time Protocol registers */ 688 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 689 int len); 690 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 691 692 /* Access global Time Application Interface registers */ 693 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 694 int len); 695 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 696 }; 697 698 struct mv88e6xxx_ptp_ops { 699 u64 (*clock_read)(const struct cyclecounter *cc); 700 int (*ptp_enable)(struct ptp_clock_info *ptp, 701 struct ptp_clock_request *rq, int on); 702 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 703 enum ptp_pin_function func, unsigned int chan); 704 void (*event_work)(struct work_struct *ugly); 705 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 706 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 707 int (*global_enable)(struct mv88e6xxx_chip *chip); 708 int (*global_disable)(struct mv88e6xxx_chip *chip); 709 int n_ext_ts; 710 int arr0_sts_reg; 711 int arr1_sts_reg; 712 int dep_sts_reg; 713 u32 rx_filters; 714 u32 cc_shift; 715 u32 cc_mult; 716 u32 cc_mult_num; 717 u32 cc_mult_dem; 718 }; 719 720 #define STATS_TYPE_PORT BIT(0) 721 #define STATS_TYPE_BANK0 BIT(1) 722 #define STATS_TYPE_BANK1 BIT(2) 723 724 struct mv88e6xxx_hw_stat { 725 char string[ETH_GSTRING_LEN]; 726 size_t size; 727 int reg; 728 int type; 729 }; 730 731 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 732 { 733 return chip->info->max_sid > 0 && 734 chip->info->ops->stu_loadpurge && 735 chip->info->ops->stu_getnext; 736 } 737 738 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 739 { 740 return chip->info->pvt; 741 } 742 743 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 744 { 745 return !!chip->info->global2_addr; 746 } 747 748 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 749 { 750 return chip->info->num_databases; 751 } 752 753 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 754 { 755 return chip->info->num_macs; 756 } 757 758 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 759 { 760 return chip->info->num_ports; 761 } 762 763 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 764 { 765 return chip->info->max_vid; 766 } 767 768 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 769 { 770 return chip->info->max_sid; 771 } 772 773 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 774 { 775 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 776 } 777 778 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 779 { 780 return chip->info->num_gpio; 781 } 782 783 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 784 { 785 return (chip->info->invalid_port_mask & BIT(port)) != 0; 786 } 787 788 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 789 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 790 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 791 u16 mask, u16 val); 792 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 793 int bit, int val); 794 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 795 796 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 797 { 798 mutex_lock(&chip->reg_lock); 799 } 800 801 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 802 { 803 mutex_unlock(&chip->reg_lock); 804 } 805 806 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 807 808 #endif /* _MV88E6XXX_CHIP_H */ 809