1 /* 2 * Marvell 88E6xxx Ethernet switch single-chip definition 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #ifndef _MV88E6XXX_CHIP_H 13 #define _MV88E6XXX_CHIP_H 14 15 #include <linux/if_vlan.h> 16 #include <linux/irq.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/kthread.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/timecounter.h> 22 #include <net/dsa.h> 23 24 #ifndef UINT64_MAX 25 #define UINT64_MAX (u64)(~((u64)0)) 26 #endif 27 28 #define SMI_CMD 0x00 29 #define SMI_CMD_BUSY BIT(15) 30 #define SMI_CMD_CLAUSE_22 BIT(12) 31 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 32 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 33 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 34 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 35 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 36 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 37 #define SMI_DATA 0x01 38 39 #define MV88E6XXX_N_FID 4096 40 41 /* PVT limits for 4-bit port and 5-bit switch */ 42 #define MV88E6XXX_MAX_PVT_SWITCHES 32 43 #define MV88E6XXX_MAX_PVT_PORTS 16 44 45 #define MV88E6XXX_MAX_GPIO 16 46 47 enum mv88e6xxx_egress_mode { 48 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 49 MV88E6XXX_EGRESS_MODE_UNTAGGED, 50 MV88E6XXX_EGRESS_MODE_TAGGED, 51 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 52 }; 53 54 enum mv88e6xxx_frame_mode { 55 MV88E6XXX_FRAME_MODE_NORMAL, 56 MV88E6XXX_FRAME_MODE_DSA, 57 MV88E6XXX_FRAME_MODE_PROVIDER, 58 MV88E6XXX_FRAME_MODE_ETHERTYPE, 59 }; 60 61 /* List of supported models */ 62 enum mv88e6xxx_model { 63 MV88E6085, 64 MV88E6095, 65 MV88E6097, 66 MV88E6123, 67 MV88E6131, 68 MV88E6141, 69 MV88E6161, 70 MV88E6165, 71 MV88E6171, 72 MV88E6172, 73 MV88E6175, 74 MV88E6176, 75 MV88E6185, 76 MV88E6190, 77 MV88E6190X, 78 MV88E6191, 79 MV88E6240, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6390, 88 MV88E6390X, 89 }; 90 91 enum mv88e6xxx_family { 92 MV88E6XXX_FAMILY_NONE, 93 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 94 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 95 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 96 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 97 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 103 }; 104 105 struct mv88e6xxx_ops; 106 107 struct mv88e6xxx_info { 108 enum mv88e6xxx_family family; 109 u16 prod_num; 110 const char *name; 111 unsigned int num_databases; 112 unsigned int num_ports; 113 unsigned int num_gpio; 114 unsigned int max_vid; 115 unsigned int port_base_addr; 116 unsigned int global1_addr; 117 unsigned int global2_addr; 118 unsigned int age_time_coeff; 119 unsigned int g1_irqs; 120 unsigned int g2_irqs; 121 bool pvt; 122 123 /* Multi-chip Addressing Mode. 124 * Some chips respond to only 2 registers of its own SMI device address 125 * when it is non-zero, and use indirect access to internal registers. 126 */ 127 bool multi_chip; 128 enum dsa_tag_protocol tag_protocol; 129 130 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 131 * operation. 0 means that the ATU Move operation is not supported. 132 */ 133 u8 atu_move_port_mask; 134 const struct mv88e6xxx_ops *ops; 135 136 /* Supports PTP */ 137 bool ptp_support; 138 }; 139 140 struct mv88e6xxx_atu_entry { 141 u8 state; 142 bool trunk; 143 u16 portvec; 144 u8 mac[ETH_ALEN]; 145 }; 146 147 struct mv88e6xxx_vtu_entry { 148 u16 vid; 149 u16 fid; 150 u8 sid; 151 bool valid; 152 u8 member[DSA_MAX_PORTS]; 153 u8 state[DSA_MAX_PORTS]; 154 }; 155 156 struct mv88e6xxx_bus_ops; 157 struct mv88e6xxx_irq_ops; 158 struct mv88e6xxx_gpio_ops; 159 struct mv88e6xxx_avb_ops; 160 161 struct mv88e6xxx_irq { 162 u16 masked; 163 struct irq_chip chip; 164 struct irq_domain *domain; 165 unsigned int nirqs; 166 }; 167 168 /* state flags for mv88e6xxx_port_hwtstamp::state */ 169 enum { 170 MV88E6XXX_HWTSTAMP_ENABLED, 171 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 172 }; 173 174 struct mv88e6xxx_port_hwtstamp { 175 /* Port index */ 176 int port_id; 177 178 /* Timestamping state */ 179 unsigned long state; 180 181 /* Resources for receive timestamping */ 182 struct sk_buff_head rx_queue; 183 struct sk_buff_head rx_queue2; 184 185 /* Resources for transmit timestamping */ 186 unsigned long tx_tstamp_start; 187 struct sk_buff *tx_skb; 188 u16 tx_seq_id; 189 190 /* Current timestamp configuration */ 191 struct hwtstamp_config tstamp_config; 192 }; 193 194 struct mv88e6xxx_chip { 195 const struct mv88e6xxx_info *info; 196 197 /* The dsa_switch this private structure is related to */ 198 struct dsa_switch *ds; 199 200 /* The device this structure is associated to */ 201 struct device *dev; 202 203 /* This mutex protects the access to the switch registers */ 204 struct mutex reg_lock; 205 206 /* The MII bus and the address on the bus that is used to 207 * communication with the switch 208 */ 209 const struct mv88e6xxx_bus_ops *smi_ops; 210 struct mii_bus *bus; 211 int sw_addr; 212 213 /* Handles automatic disabling and re-enabling of the PHY 214 * polling unit. 215 */ 216 const struct mv88e6xxx_bus_ops *phy_ops; 217 struct mutex ppu_mutex; 218 int ppu_disabled; 219 struct work_struct ppu_work; 220 struct timer_list ppu_timer; 221 222 /* This mutex serialises access to the statistics unit. 223 * Hold this mutex over snapshot + dump sequences. 224 */ 225 struct mutex stats_mutex; 226 227 /* A switch may have a GPIO line tied to its reset pin. Parse 228 * this from the device tree, and use it before performing 229 * switch soft reset. 230 */ 231 struct gpio_desc *reset; 232 233 /* set to size of eeprom if supported by the switch */ 234 int eeprom_len; 235 236 /* List of mdio busses */ 237 struct list_head mdios; 238 239 /* There can be two interrupt controllers, which are chained 240 * off a GPIO as interrupt source 241 */ 242 struct mv88e6xxx_irq g1_irq; 243 struct mv88e6xxx_irq g2_irq; 244 int irq; 245 int device_irq; 246 int watchdog_irq; 247 int atu_prob_irq; 248 int vtu_prob_irq; 249 struct kthread_worker *kworker; 250 struct kthread_delayed_work irq_poll_work; 251 252 /* GPIO resources */ 253 u8 gpio_data[2]; 254 255 /* This cyclecounter abstracts the switch PTP time. 256 * reg_lock must be held for any operation that read()s. 257 */ 258 struct cyclecounter tstamp_cc; 259 struct timecounter tstamp_tc; 260 struct delayed_work overflow_work; 261 262 struct ptp_clock *ptp_clock; 263 struct ptp_clock_info ptp_clock_info; 264 struct delayed_work tai_event_work; 265 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 266 u16 trig_config; 267 u16 evcap_config; 268 269 /* Per-port timestamping resources. */ 270 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 271 }; 272 273 struct mv88e6xxx_bus_ops { 274 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 275 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 276 }; 277 278 struct mv88e6xxx_mdio_bus { 279 struct mii_bus *bus; 280 struct mv88e6xxx_chip *chip; 281 struct list_head list; 282 bool external; 283 }; 284 285 struct mv88e6xxx_ops { 286 /* Ingress Rate Limit unit (IRL) operations */ 287 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 288 289 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 290 struct ethtool_eeprom *eeprom, u8 *data); 291 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 292 struct ethtool_eeprom *eeprom, u8 *data); 293 294 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 295 296 int (*phy_read)(struct mv88e6xxx_chip *chip, 297 struct mii_bus *bus, 298 int addr, int reg, u16 *val); 299 int (*phy_write)(struct mv88e6xxx_chip *chip, 300 struct mii_bus *bus, 301 int addr, int reg, u16 val); 302 303 /* Priority Override Table operations */ 304 int (*pot_clear)(struct mv88e6xxx_chip *chip); 305 306 /* PHY Polling Unit (PPU) operations */ 307 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 308 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 309 310 /* Switch Software Reset */ 311 int (*reset)(struct mv88e6xxx_chip *chip); 312 313 /* RGMII Receive/Transmit Timing Control 314 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 315 */ 316 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 317 phy_interface_t mode); 318 319 #define LINK_FORCED_DOWN 0 320 #define LINK_FORCED_UP 1 321 #define LINK_UNFORCED -2 322 323 /* Port's MAC link state 324 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 325 * or LINK_UNFORCED for normal link detection. 326 */ 327 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 328 329 #define DUPLEX_UNFORCED -2 330 331 /* Port's MAC duplex mode 332 * 333 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 334 * or DUPLEX_UNFORCED for normal duplex detection. 335 */ 336 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); 337 338 #define SPEED_MAX INT_MAX 339 #define SPEED_UNFORCED -2 340 341 /* Port's MAC speed (in Mbps) 342 * 343 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 344 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 345 */ 346 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); 347 348 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 349 350 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 351 enum mv88e6xxx_frame_mode mode); 352 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port, 353 bool unicast, bool multicast); 354 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 355 u16 etype); 356 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 357 size_t size); 358 359 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 360 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 361 u8 out); 362 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 363 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 364 365 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 366 * Some chips allow this to be configured on specific ports. 367 */ 368 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 369 phy_interface_t mode); 370 371 /* Some devices have a per port register indicating what is 372 * the upstream port this port should forward to. 373 */ 374 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 375 int upstream_port); 376 377 /* Snapshot the statistics for a port. The statistics can then 378 * be read back a leisure but still with a consistent view. 379 */ 380 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 381 382 /* Set the histogram mode for statistics, when the control registers 383 * are separated out of the STATS_OP register. 384 */ 385 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 386 387 /* Return the number of strings describing statistics */ 388 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 389 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 390 void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 391 uint64_t *data); 392 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 393 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port); 394 const struct mv88e6xxx_irq_ops *watchdog_ops; 395 396 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 397 398 /* Power on/off a SERDES interface */ 399 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on); 400 401 /* VLAN Translation Unit operations */ 402 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 403 struct mv88e6xxx_vtu_entry *entry); 404 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 405 struct mv88e6xxx_vtu_entry *entry); 406 407 /* GPIO operations */ 408 const struct mv88e6xxx_gpio_ops *gpio_ops; 409 410 /* Interface to the AVB/PTP registers */ 411 const struct mv88e6xxx_avb_ops *avb_ops; 412 }; 413 414 struct mv88e6xxx_irq_ops { 415 /* Action to be performed when the interrupt happens */ 416 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 417 /* Setup the hardware to generate the interrupt */ 418 int (*irq_setup)(struct mv88e6xxx_chip *chip); 419 /* Reset the hardware to stop generating the interrupt */ 420 void (*irq_free)(struct mv88e6xxx_chip *chip); 421 }; 422 423 struct mv88e6xxx_gpio_ops { 424 /* Get/set data on GPIO pin */ 425 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 426 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 427 int value); 428 429 /* get/set GPIO direction */ 430 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 431 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 432 bool input); 433 434 /* get/set GPIO pin control */ 435 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 436 int *func); 437 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 438 int func); 439 }; 440 441 struct mv88e6xxx_avb_ops { 442 /* Access port-scoped Precision Time Protocol registers */ 443 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 444 u16 *data, int len); 445 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 446 u16 data); 447 448 /* Access global Precision Time Protocol registers */ 449 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 450 int len); 451 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 452 453 /* Access global Time Application Interface registers */ 454 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 455 int len); 456 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 457 }; 458 459 #define STATS_TYPE_PORT BIT(0) 460 #define STATS_TYPE_BANK0 BIT(1) 461 #define STATS_TYPE_BANK1 BIT(2) 462 463 struct mv88e6xxx_hw_stat { 464 char string[ETH_GSTRING_LEN]; 465 int sizeof_stat; 466 int reg; 467 int type; 468 }; 469 470 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 471 { 472 return chip->info->pvt; 473 } 474 475 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 476 { 477 return chip->info->num_databases; 478 } 479 480 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 481 { 482 return chip->info->num_ports; 483 } 484 485 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 486 { 487 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); 488 } 489 490 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 491 { 492 return chip->info->num_gpio; 493 } 494 495 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 496 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 497 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, 498 u16 update); 499 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); 500 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 501 502 #endif /* _MV88E6XXX_CHIP_H */ 503