1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6020, 58 MV88E6071, 59 MV88E6085, 60 MV88E6095, 61 MV88E6097, 62 MV88E6123, 63 MV88E6131, 64 MV88E6141, 65 MV88E6161, 66 MV88E6165, 67 MV88E6171, 68 MV88E6172, 69 MV88E6175, 70 MV88E6176, 71 MV88E6185, 72 MV88E6190, 73 MV88E6190X, 74 MV88E6191, 75 MV88E6191X, 76 MV88E6193X, 77 MV88E6220, 78 MV88E6240, 79 MV88E6250, 80 MV88E6290, 81 MV88E6320, 82 MV88E6321, 83 MV88E6341, 84 MV88E6350, 85 MV88E6351, 86 MV88E6352, 87 MV88E6361, 88 MV88E6390, 89 MV88E6390X, 90 MV88E6393X, 91 }; 92 93 enum mv88e6xxx_family { 94 MV88E6XXX_FAMILY_NONE, 95 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 96 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 97 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 98 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 99 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 100 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 101 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 102 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 103 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 104 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 105 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 106 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 107 }; 108 109 /** 110 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 111 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 112 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 113 * egressing FORWARD frames with an EDSA 114 * tag is reserved for future use, but 115 * empirical data shows that this mode 116 * is supported. 117 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 118 */ 119 enum mv88e6xxx_edsa_support { 120 MV88E6XXX_EDSA_UNSUPPORTED = 0, 121 MV88E6XXX_EDSA_UNDOCUMENTED, 122 MV88E6XXX_EDSA_SUPPORTED, 123 }; 124 125 struct mv88e6xxx_ops; 126 127 struct mv88e6xxx_info { 128 enum mv88e6xxx_family family; 129 u16 prod_num; 130 const char *name; 131 unsigned int num_databases; 132 unsigned int num_macs; 133 unsigned int num_ports; 134 unsigned int num_internal_phys; 135 unsigned int num_gpio; 136 unsigned int max_vid; 137 unsigned int max_sid; 138 unsigned int port_base_addr; 139 unsigned int phy_base_addr; 140 unsigned int global1_addr; 141 unsigned int global2_addr; 142 unsigned int age_time_coeff; 143 unsigned int g1_irqs; 144 unsigned int g2_irqs; 145 bool pvt; 146 147 /* Mark certain ports as invalid. This is required for example for the 148 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 149 * ports 2-4 are not routet to pins. 150 */ 151 unsigned int invalid_port_mask; 152 /* Multi-chip Addressing Mode. 153 * Some chips respond to only 2 registers of its own SMI device address 154 * when it is non-zero, and use indirect access to internal registers. 155 */ 156 bool multi_chip; 157 /* Dual-chip Addressing Mode 158 * Some chips respond to only half of the 32 SMI addresses, 159 * allowing two to coexist on the same SMI interface. 160 */ 161 bool dual_chip; 162 163 enum mv88e6xxx_edsa_support edsa_support; 164 165 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 166 * operation. 0 means that the ATU Move operation is not supported. 167 */ 168 u8 atu_move_port_mask; 169 const struct mv88e6xxx_ops *ops; 170 171 /* Supports PTP */ 172 bool ptp_support; 173 174 /* Internal PHY start index. 0 means that internal PHYs range starts at 175 * port 0, 1 means internal PHYs range starts at port 1, etc 176 */ 177 unsigned int internal_phys_offset; 178 }; 179 180 struct mv88e6xxx_atu_entry { 181 u8 state; 182 bool trunk; 183 u16 portvec; 184 u8 mac[ETH_ALEN]; 185 }; 186 187 struct mv88e6xxx_vtu_entry { 188 u16 vid; 189 u16 fid; 190 u8 sid; 191 bool valid; 192 bool policy; 193 u8 member[DSA_MAX_PORTS]; 194 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 195 }; 196 197 struct mv88e6xxx_stu_entry { 198 u8 sid; 199 bool valid; 200 u8 state[DSA_MAX_PORTS]; 201 }; 202 203 struct mv88e6xxx_bus_ops; 204 struct mv88e6xxx_irq_ops; 205 struct mv88e6xxx_gpio_ops; 206 struct mv88e6xxx_avb_ops; 207 struct mv88e6xxx_ptp_ops; 208 struct mv88e6xxx_pcs_ops; 209 struct mv88e6xxx_cc_coeffs; 210 211 struct mv88e6xxx_irq { 212 u16 masked; 213 struct irq_chip chip; 214 struct irq_domain *domain; 215 int nirqs; 216 }; 217 218 /* state flags for mv88e6xxx_port_hwtstamp::state */ 219 enum { 220 MV88E6XXX_HWTSTAMP_ENABLED, 221 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 222 }; 223 224 struct mv88e6xxx_port_hwtstamp { 225 /* Port index */ 226 int port_id; 227 228 /* Timestamping state */ 229 unsigned long state; 230 231 /* Resources for receive timestamping */ 232 struct sk_buff_head rx_queue; 233 struct sk_buff_head rx_queue2; 234 235 /* Resources for transmit timestamping */ 236 unsigned long tx_tstamp_start; 237 struct sk_buff *tx_skb; 238 u16 tx_seq_id; 239 240 /* Current timestamp configuration */ 241 struct hwtstamp_config tstamp_config; 242 }; 243 244 enum mv88e6xxx_policy_mapping { 245 MV88E6XXX_POLICY_MAPPING_DA, 246 MV88E6XXX_POLICY_MAPPING_SA, 247 MV88E6XXX_POLICY_MAPPING_VTU, 248 MV88E6XXX_POLICY_MAPPING_ETYPE, 249 MV88E6XXX_POLICY_MAPPING_PPPOE, 250 MV88E6XXX_POLICY_MAPPING_VBAS, 251 MV88E6XXX_POLICY_MAPPING_OPT82, 252 MV88E6XXX_POLICY_MAPPING_UDP, 253 }; 254 255 enum mv88e6xxx_policy_action { 256 MV88E6XXX_POLICY_ACTION_NORMAL, 257 MV88E6XXX_POLICY_ACTION_MIRROR, 258 MV88E6XXX_POLICY_ACTION_TRAP, 259 MV88E6XXX_POLICY_ACTION_DISCARD, 260 }; 261 262 struct mv88e6xxx_policy { 263 enum mv88e6xxx_policy_mapping mapping; 264 enum mv88e6xxx_policy_action action; 265 struct ethtool_rx_flow_spec fs; 266 u8 addr[ETH_ALEN]; 267 int port; 268 u16 vid; 269 }; 270 271 struct mv88e6xxx_vlan { 272 u16 vid; 273 bool valid; 274 }; 275 276 struct mv88e6xxx_port { 277 struct mv88e6xxx_chip *chip; 278 int port; 279 struct mv88e6xxx_vlan bridge_pvid; 280 u64 serdes_stats[2]; 281 u64 atu_member_violation; 282 u64 atu_miss_violation; 283 u64 atu_full_violation; 284 u64 vtu_member_violation; 285 u64 vtu_miss_violation; 286 phy_interface_t interface; 287 u8 cmode; 288 bool mirror_ingress; 289 bool mirror_egress; 290 struct devlink_region *region; 291 void *pcs_private; 292 293 /* MacAuth Bypass control flag */ 294 bool mab; 295 }; 296 297 enum mv88e6xxx_region_id { 298 MV88E6XXX_REGION_GLOBAL1 = 0, 299 MV88E6XXX_REGION_GLOBAL2, 300 MV88E6XXX_REGION_ATU, 301 MV88E6XXX_REGION_VTU, 302 MV88E6XXX_REGION_STU, 303 MV88E6XXX_REGION_PVT, 304 305 _MV88E6XXX_REGION_MAX, 306 }; 307 308 struct mv88e6xxx_region_priv { 309 enum mv88e6xxx_region_id id; 310 }; 311 312 struct mv88e6xxx_mst { 313 struct list_head node; 314 315 refcount_t refcnt; 316 struct net_device *br; 317 u16 msti; 318 319 struct mv88e6xxx_stu_entry stu; 320 }; 321 322 #define STATS_TYPE_PORT BIT(0) 323 #define STATS_TYPE_BANK0 BIT(1) 324 #define STATS_TYPE_BANK1 BIT(2) 325 326 struct mv88e6xxx_hw_stat { 327 char string[ETH_GSTRING_LEN]; 328 size_t size; 329 int reg; 330 int type; 331 }; 332 333 struct mv88e6xxx_chip { 334 const struct mv88e6xxx_info *info; 335 336 /* Currently configured tagging protocol */ 337 enum dsa_tag_protocol tag_protocol; 338 339 /* The dsa_switch this private structure is related to */ 340 struct dsa_switch *ds; 341 342 /* The device this structure is associated to */ 343 struct device *dev; 344 345 /* This mutex protects the access to the switch registers */ 346 struct mutex reg_lock; 347 348 /* The MII bus and the address on the bus that is used to 349 * communication with the switch 350 */ 351 const struct mv88e6xxx_bus_ops *smi_ops; 352 struct mii_bus *bus; 353 int sw_addr; 354 355 /* Handles automatic disabling and re-enabling of the PHY 356 * polling unit. 357 */ 358 const struct mv88e6xxx_bus_ops *phy_ops; 359 struct mutex ppu_mutex; 360 int ppu_disabled; 361 struct work_struct ppu_work; 362 struct timer_list ppu_timer; 363 364 /* This mutex serialises access to the statistics unit. 365 * Hold this mutex over snapshot + dump sequences. 366 */ 367 struct mutex stats_mutex; 368 369 /* A switch may have a GPIO line tied to its reset pin. Parse 370 * this from the device tree, and use it before performing 371 * switch soft reset. 372 */ 373 struct gpio_desc *reset; 374 375 /* set to size of eeprom if supported by the switch */ 376 u32 eeprom_len; 377 378 /* List of mdio busses */ 379 struct list_head mdios; 380 381 /* Policy Control List IDs and rules */ 382 struct idr policies; 383 384 /* There can be two interrupt controllers, which are chained 385 * off a GPIO as interrupt source 386 */ 387 struct mv88e6xxx_irq g1_irq; 388 struct mv88e6xxx_irq g2_irq; 389 int irq; 390 char irq_name[64]; 391 int device_irq; 392 char device_irq_name[64]; 393 int watchdog_irq; 394 char watchdog_irq_name[64]; 395 396 int atu_prob_irq; 397 char atu_prob_irq_name[64]; 398 int vtu_prob_irq; 399 char vtu_prob_irq_name[64]; 400 struct kthread_worker *kworker; 401 struct kthread_delayed_work irq_poll_work; 402 403 /* GPIO resources */ 404 u8 gpio_data[2]; 405 406 /* This cyclecounter abstracts the switch PTP time. 407 * reg_lock must be held for any operation that read()s. 408 */ 409 struct cyclecounter tstamp_cc; 410 struct timecounter tstamp_tc; 411 struct delayed_work overflow_work; 412 const struct mv88e6xxx_cc_coeffs *cc_coeffs; 413 414 struct ptp_clock *ptp_clock; 415 struct ptp_clock_info ptp_clock_info; 416 struct delayed_work tai_event_work; 417 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 418 u16 trig_config; 419 u16 evcap_config; 420 u16 enable_count; 421 422 /* Current ingress and egress monitor ports */ 423 int egress_dest_port; 424 int ingress_dest_port; 425 426 /* Per-port timestamping resources. */ 427 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 428 429 /* Array of port structures. */ 430 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 431 432 /* devlink regions */ 433 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 434 435 /* Bridge MST to SID mappings */ 436 struct list_head msts; 437 }; 438 439 struct mv88e6xxx_bus_ops { 440 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 441 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 442 int (*init)(struct mv88e6xxx_chip *chip); 443 }; 444 445 struct mv88e6xxx_mdio_bus { 446 struct mii_bus *bus; 447 struct mv88e6xxx_chip *chip; 448 struct list_head list; 449 bool external; 450 }; 451 452 struct mv88e6xxx_ops { 453 /* Switch Setup Errata, called early in the switch setup to 454 * allow any errata actions to be performed 455 */ 456 int (*setup_errata)(struct mv88e6xxx_chip *chip); 457 458 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 459 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 460 461 /* Ingress Rate Limit unit (IRL) operations */ 462 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 463 464 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 465 struct ethtool_eeprom *eeprom, u8 *data); 466 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 467 struct ethtool_eeprom *eeprom, u8 *data); 468 469 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 470 471 int (*phy_read)(struct mv88e6xxx_chip *chip, 472 struct mii_bus *bus, 473 int addr, int reg, u16 *val); 474 int (*phy_write)(struct mv88e6xxx_chip *chip, 475 struct mii_bus *bus, 476 int addr, int reg, u16 val); 477 478 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 479 struct mii_bus *bus, 480 int addr, int devad, int reg, u16 *val); 481 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 482 struct mii_bus *bus, 483 int addr, int devad, int reg, u16 val); 484 485 /* Priority Override Table operations */ 486 int (*pot_clear)(struct mv88e6xxx_chip *chip); 487 488 /* PHY Polling Unit (PPU) operations */ 489 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 490 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 491 492 /* Additional handlers to run before and after hard reset, to make sure 493 * that the switch and EEPROM are in a good state. 494 */ 495 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip); 496 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip); 497 498 /* Switch Software Reset */ 499 int (*reset)(struct mv88e6xxx_chip *chip); 500 501 /* RGMII Receive/Transmit Timing Control 502 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 503 */ 504 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 505 phy_interface_t mode); 506 507 #define LINK_FORCED_DOWN 0 508 #define LINK_FORCED_UP 1 509 #define LINK_UNFORCED -2 510 511 /* Port's MAC link state 512 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 513 * or LINK_UNFORCED for normal link detection. 514 */ 515 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 516 517 /* Synchronise the port link state with that of the SERDES 518 */ 519 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 520 521 #define PAUSE_ON 1 522 #define PAUSE_OFF 0 523 524 /* Enable/disable sending Pause */ 525 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 526 int pause); 527 528 #define SPEED_UNFORCED -2 529 #define DUPLEX_UNFORCED -2 530 531 /* Port's MAC speed (in Mbps) and MAC duplex mode 532 * 533 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 534 * Use SPEED_UNFORCED for normal detection. 535 * 536 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 537 * or DUPLEX_UNFORCED for normal duplex detection. 538 */ 539 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 540 int speed, int duplex); 541 542 /* What interface mode should be used for maximum speed? */ 543 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 544 int port); 545 546 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 547 548 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 549 enum mv88e6xxx_policy_mapping mapping, 550 enum mv88e6xxx_policy_action action); 551 552 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 553 enum mv88e6xxx_frame_mode mode); 554 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 555 bool unicast); 556 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 557 bool multicast); 558 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 559 u16 etype); 560 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 561 size_t size); 562 563 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 564 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 565 u8 out); 566 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 567 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 568 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 569 570 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 571 * Some chips allow this to be configured on specific ports. 572 */ 573 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 574 phy_interface_t mode); 575 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 576 577 /* Some devices have a per port register indicating what is 578 * the upstream port this port should forward to. 579 */ 580 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 581 int upstream_port); 582 583 /* Snapshot the statistics for a port. The statistics can then 584 * be read back a leisure but still with a consistent view. 585 */ 586 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 587 588 /* Set the histogram mode for statistics, when the control registers 589 * are separated out of the STATS_OP register. 590 */ 591 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 592 593 /* Return the number of strings describing statistics */ 594 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 595 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 596 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port, 597 const struct mv88e6xxx_hw_stat *stat, 598 uint64_t *data); 599 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 600 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 601 enum mv88e6xxx_egress_direction direction, 602 int port); 603 604 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 605 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 606 607 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 608 609 const struct mv88e6xxx_irq_ops *watchdog_ops; 610 611 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 612 613 /* SERDES lane mapping */ 614 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 615 616 /* SERDES interrupt handling */ 617 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 618 int port); 619 620 /* Statistics from the SERDES interface */ 621 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 622 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 623 uint8_t *data); 624 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 625 uint64_t *data); 626 627 /* SERDES registers for ethtool */ 628 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 629 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 630 void *_p); 631 632 /* SERDES SGMII/Fiber Output Amplitude */ 633 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 634 int val); 635 636 /* Address Translation Unit operations */ 637 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 638 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 639 640 /* VLAN Translation Unit operations */ 641 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 642 struct mv88e6xxx_vtu_entry *entry); 643 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 644 struct mv88e6xxx_vtu_entry *entry); 645 646 /* Spanning Tree Unit operations */ 647 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 648 struct mv88e6xxx_stu_entry *entry); 649 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 650 struct mv88e6xxx_stu_entry *entry); 651 652 /* GPIO operations */ 653 const struct mv88e6xxx_gpio_ops *gpio_ops; 654 655 /* Interface to the AVB/PTP registers */ 656 const struct mv88e6xxx_avb_ops *avb_ops; 657 658 /* Remote Management Unit operations */ 659 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 660 661 /* Precision Time Protocol operations */ 662 const struct mv88e6xxx_ptp_ops *ptp_ops; 663 664 /* Phylink */ 665 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 666 struct phylink_config *config); 667 668 const struct mv88e6xxx_pcs_ops *pcs_ops; 669 670 /* Max Frame Size */ 671 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 672 }; 673 674 struct mv88e6xxx_irq_ops { 675 /* Action to be performed when the interrupt happens */ 676 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 677 /* Setup the hardware to generate the interrupt */ 678 int (*irq_setup)(struct mv88e6xxx_chip *chip); 679 /* Reset the hardware to stop generating the interrupt */ 680 void (*irq_free)(struct mv88e6xxx_chip *chip); 681 }; 682 683 struct mv88e6xxx_gpio_ops { 684 /* Get/set data on GPIO pin */ 685 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 686 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 687 int value); 688 689 /* get/set GPIO direction */ 690 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 691 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 692 bool input); 693 694 /* get/set GPIO pin control */ 695 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 696 int *func); 697 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 698 int func); 699 }; 700 701 struct mv88e6xxx_avb_ops { 702 /* Access port-scoped Precision Time Protocol registers */ 703 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 704 u16 *data, int len); 705 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 706 u16 data); 707 708 /* Access global Precision Time Protocol registers */ 709 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 710 int len); 711 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 712 713 /* Access global Time Application Interface registers */ 714 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 715 int len); 716 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 717 }; 718 719 struct mv88e6xxx_ptp_ops { 720 u64 (*clock_read)(const struct cyclecounter *cc); 721 int (*ptp_enable)(struct ptp_clock_info *ptp, 722 struct ptp_clock_request *rq, int on); 723 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 724 enum ptp_pin_function func, unsigned int chan); 725 void (*event_work)(struct work_struct *ugly); 726 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 727 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 728 int (*global_enable)(struct mv88e6xxx_chip *chip); 729 int (*global_disable)(struct mv88e6xxx_chip *chip); 730 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 731 int n_ext_ts; 732 int arr0_sts_reg; 733 int arr1_sts_reg; 734 int dep_sts_reg; 735 u32 rx_filters; 736 }; 737 738 struct mv88e6xxx_pcs_ops { 739 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port); 740 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port); 741 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port, 742 phy_interface_t mode); 743 744 }; 745 746 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 747 { 748 return chip->info->max_sid > 0 && 749 chip->info->ops->stu_loadpurge && 750 chip->info->ops->stu_getnext; 751 } 752 753 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 754 { 755 return chip->info->pvt; 756 } 757 758 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 759 { 760 return !!chip->info->global2_addr; 761 } 762 763 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 764 { 765 return chip->info->num_databases; 766 } 767 768 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 769 { 770 return chip->info->num_macs; 771 } 772 773 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 774 { 775 return chip->info->num_ports; 776 } 777 778 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 779 { 780 return chip->info->max_vid; 781 } 782 783 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 784 { 785 return chip->info->max_sid; 786 } 787 788 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 789 { 790 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 791 } 792 793 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 794 { 795 return chip->info->num_gpio; 796 } 797 798 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 799 { 800 return (chip->info->invalid_port_mask & BIT(port)) != 0; 801 } 802 803 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 804 int port, bool mab) 805 { 806 chip->ports[port].mab = mab; 807 } 808 809 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 810 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 811 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 812 u16 mask, u16 val); 813 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 814 int bit, int val); 815 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 816 817 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 818 { 819 mutex_lock(&chip->reg_lock); 820 } 821 822 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 823 { 824 mutex_unlock(&chip->reg_lock); 825 } 826 827 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 828 int (*cb)(struct mv88e6xxx_chip *chip, 829 const struct mv88e6xxx_vtu_entry *entry, 830 void *priv), 831 void *priv); 832 833 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 834 835 #endif /* _MV88E6XXX_CHIP_H */ 836