1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/leds.h> 17 #include <linux/phy.h> 18 #include <linux/property.h> 19 #include <linux/ptp_clock_kernel.h> 20 #include <linux/timecounter.h> 21 #include <net/dsa.h> 22 23 #define EDSA_HLEN 8 24 #define MV88E6XXX_N_FID 4096 25 #define MV88E6XXX_N_SID 64 26 27 #define MV88E6XXX_FID_STANDALONE 0 28 #define MV88E6XXX_FID_BRIDGED 1 29 30 /* PVT limits for 4-bit port and 5-bit switch */ 31 #define MV88E6XXX_MAX_PVT_SWITCHES 32 32 #define MV88E6XXX_MAX_PVT_PORTS 16 33 #define MV88E6XXX_MAX_PVT_ENTRIES \ 34 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 35 36 #define MV88E6XXX_MAX_GPIO 16 37 38 enum mv88e6xxx_egress_mode { 39 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 40 MV88E6XXX_EGRESS_MODE_UNTAGGED, 41 MV88E6XXX_EGRESS_MODE_TAGGED, 42 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 43 }; 44 45 enum mv88e6xxx_egress_direction { 46 MV88E6XXX_EGRESS_DIR_INGRESS, 47 MV88E6XXX_EGRESS_DIR_EGRESS, 48 }; 49 50 enum mv88e6xxx_frame_mode { 51 MV88E6XXX_FRAME_MODE_NORMAL, 52 MV88E6XXX_FRAME_MODE_DSA, 53 MV88E6XXX_FRAME_MODE_PROVIDER, 54 MV88E6XXX_FRAME_MODE_ETHERTYPE, 55 }; 56 57 /* List of supported models */ 58 enum mv88e6xxx_model { 59 MV88E6020, 60 MV88E6071, 61 MV88E6085, 62 MV88E6095, 63 MV88E6097, 64 MV88E6123, 65 MV88E6131, 66 MV88E6141, 67 MV88E6161, 68 MV88E6165, 69 MV88E6171, 70 MV88E6172, 71 MV88E6175, 72 MV88E6176, 73 MV88E6185, 74 MV88E6190, 75 MV88E6190X, 76 MV88E6191, 77 MV88E6191X, 78 MV88E6193X, 79 MV88E6220, 80 MV88E6240, 81 MV88E6250, 82 MV88E6290, 83 MV88E6320, 84 MV88E6321, 85 MV88E6341, 86 MV88E6350, 87 MV88E6351, 88 MV88E6352, 89 MV88E6361, 90 MV88E6390, 91 MV88E6390X, 92 MV88E6393X, 93 }; 94 95 enum mv88e6xxx_family { 96 MV88E6XXX_FAMILY_NONE, 97 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 98 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 99 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 100 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 101 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 102 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 103 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 104 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 105 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 106 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 107 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 108 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 109 }; 110 111 /** 112 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 113 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 114 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 115 * egressing FORWARD frames with an EDSA 116 * tag is reserved for future use, but 117 * empirical data shows that this mode 118 * is supported. 119 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 120 */ 121 enum mv88e6xxx_edsa_support { 122 MV88E6XXX_EDSA_UNSUPPORTED = 0, 123 MV88E6XXX_EDSA_UNDOCUMENTED, 124 MV88E6XXX_EDSA_SUPPORTED, 125 }; 126 127 struct mv88e6xxx_ops; 128 129 struct mv88e6xxx_info { 130 enum mv88e6xxx_family family; 131 u16 prod_num; 132 const char *name; 133 unsigned int num_databases; 134 unsigned int num_macs; 135 unsigned int num_ports; 136 unsigned int num_internal_phys; 137 unsigned int num_gpio; 138 unsigned int max_vid; 139 unsigned int max_sid; 140 unsigned int port_base_addr; 141 unsigned int phy_base_addr; 142 unsigned int global1_addr; 143 unsigned int global2_addr; 144 unsigned int age_time_coeff; 145 unsigned int g1_irqs; 146 unsigned int g2_irqs; 147 bool pvt; 148 149 /* Mark certain ports as invalid. This is required for example for the 150 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 151 * ports 2-4 are not routet to pins. 152 */ 153 unsigned int invalid_port_mask; 154 /* Multi-chip Addressing Mode. 155 * Some chips respond to only 2 registers of its own SMI device address 156 * when it is non-zero, and use indirect access to internal registers. 157 */ 158 bool multi_chip; 159 /* Dual-chip Addressing Mode 160 * Some chips respond to only half of the 32 SMI addresses, 161 * allowing two to coexist on the same SMI interface. 162 */ 163 bool dual_chip; 164 165 enum mv88e6xxx_edsa_support edsa_support; 166 167 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 168 * operation. 0 means that the ATU Move operation is not supported. 169 */ 170 u8 atu_move_port_mask; 171 const struct mv88e6xxx_ops *ops; 172 173 /* Supports PTP */ 174 bool ptp_support; 175 176 /* Internal PHY start index. 0 means that internal PHYs range starts at 177 * port 0, 1 means internal PHYs range starts at port 1, etc 178 */ 179 unsigned int internal_phys_offset; 180 }; 181 182 struct mv88e6xxx_atu_entry { 183 u8 state; 184 bool trunk; 185 u16 portvec; 186 u8 mac[ETH_ALEN]; 187 }; 188 189 struct mv88e6xxx_vtu_entry { 190 u16 vid; 191 u16 fid; 192 u8 sid; 193 bool valid; 194 bool policy; 195 u8 member[DSA_MAX_PORTS]; 196 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 197 }; 198 199 struct mv88e6xxx_stu_entry { 200 u8 sid; 201 bool valid; 202 u8 state[DSA_MAX_PORTS]; 203 }; 204 205 struct mv88e6xxx_bus_ops; 206 struct mv88e6xxx_irq_ops; 207 struct mv88e6xxx_gpio_ops; 208 struct mv88e6xxx_avb_ops; 209 struct mv88e6xxx_ptp_ops; 210 struct mv88e6xxx_pcs_ops; 211 212 struct mv88e6xxx_irq { 213 u16 masked; 214 struct irq_chip chip; 215 struct irq_domain *domain; 216 int nirqs; 217 }; 218 219 /* state flags for mv88e6xxx_port_hwtstamp::state */ 220 enum { 221 MV88E6XXX_HWTSTAMP_ENABLED, 222 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 223 }; 224 225 struct mv88e6xxx_port_hwtstamp { 226 /* Port index */ 227 int port_id; 228 229 /* Timestamping state */ 230 unsigned long state; 231 232 /* Resources for receive timestamping */ 233 struct sk_buff_head rx_queue; 234 struct sk_buff_head rx_queue2; 235 236 /* Resources for transmit timestamping */ 237 unsigned long tx_tstamp_start; 238 struct sk_buff *tx_skb; 239 u16 tx_seq_id; 240 241 /* Current timestamp configuration */ 242 struct hwtstamp_config tstamp_config; 243 }; 244 245 enum mv88e6xxx_policy_mapping { 246 MV88E6XXX_POLICY_MAPPING_DA, 247 MV88E6XXX_POLICY_MAPPING_SA, 248 MV88E6XXX_POLICY_MAPPING_VTU, 249 MV88E6XXX_POLICY_MAPPING_ETYPE, 250 MV88E6XXX_POLICY_MAPPING_PPPOE, 251 MV88E6XXX_POLICY_MAPPING_VBAS, 252 MV88E6XXX_POLICY_MAPPING_OPT82, 253 MV88E6XXX_POLICY_MAPPING_UDP, 254 }; 255 256 enum mv88e6xxx_policy_action { 257 MV88E6XXX_POLICY_ACTION_NORMAL, 258 MV88E6XXX_POLICY_ACTION_MIRROR, 259 MV88E6XXX_POLICY_ACTION_TRAP, 260 MV88E6XXX_POLICY_ACTION_DISCARD, 261 }; 262 263 struct mv88e6xxx_policy { 264 enum mv88e6xxx_policy_mapping mapping; 265 enum mv88e6xxx_policy_action action; 266 struct ethtool_rx_flow_spec fs; 267 u8 addr[ETH_ALEN]; 268 int port; 269 u16 vid; 270 }; 271 272 struct mv88e6xxx_vlan { 273 u16 vid; 274 bool valid; 275 }; 276 277 struct mv88e6xxx_port { 278 struct mv88e6xxx_chip *chip; 279 int port; 280 struct fwnode_handle *fwnode; 281 struct mv88e6xxx_vlan bridge_pvid; 282 u64 serdes_stats[2]; 283 u64 atu_member_violation; 284 u64 atu_miss_violation; 285 u64 atu_full_violation; 286 u64 vtu_member_violation; 287 u64 vtu_miss_violation; 288 phy_interface_t interface; 289 u8 cmode; 290 bool mirror_ingress; 291 bool mirror_egress; 292 struct devlink_region *region; 293 void *pcs_private; 294 295 /* LED related information */ 296 bool fiber; 297 struct led_classdev led0; 298 struct led_classdev led1; 299 300 /* MacAuth Bypass control flag */ 301 bool mab; 302 }; 303 304 enum mv88e6xxx_region_id { 305 MV88E6XXX_REGION_GLOBAL1 = 0, 306 MV88E6XXX_REGION_GLOBAL2, 307 MV88E6XXX_REGION_ATU, 308 MV88E6XXX_REGION_VTU, 309 MV88E6XXX_REGION_STU, 310 MV88E6XXX_REGION_PVT, 311 312 _MV88E6XXX_REGION_MAX, 313 }; 314 315 struct mv88e6xxx_region_priv { 316 enum mv88e6xxx_region_id id; 317 }; 318 319 struct mv88e6xxx_mst { 320 struct list_head node; 321 322 refcount_t refcnt; 323 struct net_device *br; 324 u16 msti; 325 326 struct mv88e6xxx_stu_entry stu; 327 }; 328 329 #define STATS_TYPE_PORT BIT(0) 330 #define STATS_TYPE_BANK0 BIT(1) 331 #define STATS_TYPE_BANK1 BIT(2) 332 333 struct mv88e6xxx_hw_stat { 334 char string[ETH_GSTRING_LEN]; 335 size_t size; 336 int reg; 337 int type; 338 }; 339 340 struct mv88e6xxx_chip { 341 const struct mv88e6xxx_info *info; 342 343 /* Currently configured tagging protocol */ 344 enum dsa_tag_protocol tag_protocol; 345 346 /* The dsa_switch this private structure is related to */ 347 struct dsa_switch *ds; 348 349 /* The device this structure is associated to */ 350 struct device *dev; 351 352 /* This mutex protects the access to the switch registers */ 353 struct mutex reg_lock; 354 355 /* The MII bus and the address on the bus that is used to 356 * communication with the switch 357 */ 358 const struct mv88e6xxx_bus_ops *smi_ops; 359 struct mii_bus *bus; 360 int sw_addr; 361 362 /* Handles automatic disabling and re-enabling of the PHY 363 * polling unit. 364 */ 365 const struct mv88e6xxx_bus_ops *phy_ops; 366 struct mutex ppu_mutex; 367 int ppu_disabled; 368 struct work_struct ppu_work; 369 struct timer_list ppu_timer; 370 371 /* This mutex serialises access to the statistics unit. 372 * Hold this mutex over snapshot + dump sequences. 373 */ 374 struct mutex stats_mutex; 375 376 /* A switch may have a GPIO line tied to its reset pin. Parse 377 * this from the device tree, and use it before performing 378 * switch soft reset. 379 */ 380 struct gpio_desc *reset; 381 382 /* set to size of eeprom if supported by the switch */ 383 u32 eeprom_len; 384 385 /* List of mdio busses */ 386 struct list_head mdios; 387 388 /* Policy Control List IDs and rules */ 389 struct idr policies; 390 391 /* There can be two interrupt controllers, which are chained 392 * off a GPIO as interrupt source 393 */ 394 struct mv88e6xxx_irq g1_irq; 395 struct mv88e6xxx_irq g2_irq; 396 int irq; 397 char irq_name[64]; 398 int device_irq; 399 char device_irq_name[64]; 400 int watchdog_irq; 401 char watchdog_irq_name[64]; 402 403 int atu_prob_irq; 404 char atu_prob_irq_name[64]; 405 int vtu_prob_irq; 406 char vtu_prob_irq_name[64]; 407 struct kthread_worker *kworker; 408 struct kthread_delayed_work irq_poll_work; 409 410 /* GPIO resources */ 411 u8 gpio_data[2]; 412 413 /* This cyclecounter abstracts the switch PTP time. 414 * reg_lock must be held for any operation that read()s. 415 */ 416 struct cyclecounter tstamp_cc; 417 struct timecounter tstamp_tc; 418 struct delayed_work overflow_work; 419 420 struct ptp_clock *ptp_clock; 421 struct ptp_clock_info ptp_clock_info; 422 struct delayed_work tai_event_work; 423 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 424 u16 trig_config; 425 u16 evcap_config; 426 u16 enable_count; 427 428 /* Current ingress and egress monitor ports */ 429 int egress_dest_port; 430 int ingress_dest_port; 431 432 /* Per-port timestamping resources. */ 433 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 434 435 /* Array of port structures. */ 436 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 437 438 /* devlink regions */ 439 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 440 441 /* Bridge MST to SID mappings */ 442 struct list_head msts; 443 }; 444 445 struct mv88e6xxx_bus_ops { 446 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 447 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 448 int (*init)(struct mv88e6xxx_chip *chip); 449 }; 450 451 struct mv88e6xxx_mdio_bus { 452 struct mii_bus *bus; 453 struct mv88e6xxx_chip *chip; 454 struct list_head list; 455 bool external; 456 }; 457 458 struct mv88e6xxx_ops { 459 /* Switch Setup Errata, called early in the switch setup to 460 * allow any errata actions to be performed 461 */ 462 int (*setup_errata)(struct mv88e6xxx_chip *chip); 463 464 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 465 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 466 467 /* Ingress Rate Limit unit (IRL) operations */ 468 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 469 470 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 471 struct ethtool_eeprom *eeprom, u8 *data); 472 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 473 struct ethtool_eeprom *eeprom, u8 *data); 474 475 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 476 477 int (*phy_read)(struct mv88e6xxx_chip *chip, 478 struct mii_bus *bus, 479 int addr, int reg, u16 *val); 480 int (*phy_write)(struct mv88e6xxx_chip *chip, 481 struct mii_bus *bus, 482 int addr, int reg, u16 val); 483 484 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 485 struct mii_bus *bus, 486 int addr, int devad, int reg, u16 *val); 487 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 488 struct mii_bus *bus, 489 int addr, int devad, int reg, u16 val); 490 491 /* Priority Override Table operations */ 492 int (*pot_clear)(struct mv88e6xxx_chip *chip); 493 494 /* PHY Polling Unit (PPU) operations */ 495 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 496 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 497 498 /* Additional handlers to run before and after hard reset, to make sure 499 * that the switch and EEPROM are in a good state. 500 */ 501 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip); 502 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip); 503 504 /* Switch Software Reset */ 505 int (*reset)(struct mv88e6xxx_chip *chip); 506 507 /* RGMII Receive/Transmit Timing Control 508 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 509 */ 510 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 511 phy_interface_t mode); 512 513 #define LINK_FORCED_DOWN 0 514 #define LINK_FORCED_UP 1 515 #define LINK_UNFORCED -2 516 517 /* Port's MAC link state 518 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 519 * or LINK_UNFORCED for normal link detection. 520 */ 521 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 522 523 /* Synchronise the port link state with that of the SERDES 524 */ 525 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 526 527 #define PAUSE_ON 1 528 #define PAUSE_OFF 0 529 530 /* Enable/disable sending Pause */ 531 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 532 int pause); 533 534 #define SPEED_UNFORCED -2 535 #define DUPLEX_UNFORCED -2 536 537 /* Port's MAC speed (in Mbps) and MAC duplex mode 538 * 539 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 540 * Use SPEED_UNFORCED for normal detection. 541 * 542 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 543 * or DUPLEX_UNFORCED for normal duplex detection. 544 */ 545 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 546 int speed, int duplex); 547 548 /* What interface mode should be used for maximum speed? */ 549 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 550 int port); 551 552 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 553 554 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 555 enum mv88e6xxx_policy_mapping mapping, 556 enum mv88e6xxx_policy_action action); 557 558 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 559 enum mv88e6xxx_frame_mode mode); 560 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 561 bool unicast); 562 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 563 bool multicast); 564 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 565 u16 etype); 566 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 567 size_t size); 568 569 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 570 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 571 u8 out); 572 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 573 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 574 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 575 576 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 577 * Some chips allow this to be configured on specific ports. 578 */ 579 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 580 phy_interface_t mode); 581 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 582 583 /* LED control */ 584 int (*port_setup_leds)(struct mv88e6xxx_chip *chip, int port); 585 586 /* Some devices have a per port register indicating what is 587 * the upstream port this port should forward to. 588 */ 589 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 590 int upstream_port); 591 592 /* Snapshot the statistics for a port. The statistics can then 593 * be read back a leisure but still with a consistent view. 594 */ 595 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 596 597 /* Set the histogram mode for statistics, when the control registers 598 * are separated out of the STATS_OP register. 599 */ 600 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 601 602 /* Return the number of strings describing statistics */ 603 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 604 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 605 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port, 606 const struct mv88e6xxx_hw_stat *stat, 607 uint64_t *data); 608 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 609 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 610 enum mv88e6xxx_egress_direction direction, 611 int port); 612 613 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 614 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 615 616 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 617 618 const struct mv88e6xxx_irq_ops *watchdog_ops; 619 620 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 621 622 /* SERDES lane mapping */ 623 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 624 625 /* SERDES interrupt handling */ 626 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 627 int port); 628 629 /* Statistics from the SERDES interface */ 630 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 631 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 632 uint8_t *data); 633 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 634 uint64_t *data); 635 636 /* SERDES registers for ethtool */ 637 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 638 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 639 void *_p); 640 641 /* SERDES SGMII/Fiber Output Amplitude */ 642 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 643 int val); 644 645 /* Address Translation Unit operations */ 646 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 647 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 648 649 /* VLAN Translation Unit operations */ 650 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 651 struct mv88e6xxx_vtu_entry *entry); 652 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 653 struct mv88e6xxx_vtu_entry *entry); 654 655 /* Spanning Tree Unit operations */ 656 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 657 struct mv88e6xxx_stu_entry *entry); 658 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 659 struct mv88e6xxx_stu_entry *entry); 660 661 /* GPIO operations */ 662 const struct mv88e6xxx_gpio_ops *gpio_ops; 663 664 /* Interface to the AVB/PTP registers */ 665 const struct mv88e6xxx_avb_ops *avb_ops; 666 667 /* Remote Management Unit operations */ 668 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 669 670 /* Precision Time Protocol operations */ 671 const struct mv88e6xxx_ptp_ops *ptp_ops; 672 673 /* Phylink */ 674 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 675 struct phylink_config *config); 676 677 const struct mv88e6xxx_pcs_ops *pcs_ops; 678 679 /* Max Frame Size */ 680 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 681 }; 682 683 struct mv88e6xxx_irq_ops { 684 /* Action to be performed when the interrupt happens */ 685 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 686 /* Setup the hardware to generate the interrupt */ 687 int (*irq_setup)(struct mv88e6xxx_chip *chip); 688 /* Reset the hardware to stop generating the interrupt */ 689 void (*irq_free)(struct mv88e6xxx_chip *chip); 690 }; 691 692 struct mv88e6xxx_gpio_ops { 693 /* Get/set data on GPIO pin */ 694 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 695 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 696 int value); 697 698 /* get/set GPIO direction */ 699 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 700 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 701 bool input); 702 703 /* get/set GPIO pin control */ 704 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 705 int *func); 706 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 707 int func); 708 }; 709 710 struct mv88e6xxx_avb_ops { 711 /* Access port-scoped Precision Time Protocol registers */ 712 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 713 u16 *data, int len); 714 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 715 u16 data); 716 717 /* Access global Precision Time Protocol registers */ 718 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 719 int len); 720 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 721 722 /* Access global Time Application Interface registers */ 723 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 724 int len); 725 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 726 }; 727 728 struct mv88e6xxx_ptp_ops { 729 u64 (*clock_read)(const struct cyclecounter *cc); 730 int (*ptp_enable)(struct ptp_clock_info *ptp, 731 struct ptp_clock_request *rq, int on); 732 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 733 enum ptp_pin_function func, unsigned int chan); 734 void (*event_work)(struct work_struct *ugly); 735 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 736 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 737 int (*global_enable)(struct mv88e6xxx_chip *chip); 738 int (*global_disable)(struct mv88e6xxx_chip *chip); 739 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 740 int n_ext_ts; 741 int arr0_sts_reg; 742 int arr1_sts_reg; 743 int dep_sts_reg; 744 u32 rx_filters; 745 u32 cc_shift; 746 u32 cc_mult; 747 u32 cc_mult_num; 748 u32 cc_mult_dem; 749 }; 750 751 struct mv88e6xxx_pcs_ops { 752 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port); 753 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port); 754 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port, 755 phy_interface_t mode); 756 757 }; 758 759 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 760 { 761 return chip->info->max_sid > 0 && 762 chip->info->ops->stu_loadpurge && 763 chip->info->ops->stu_getnext; 764 } 765 766 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 767 { 768 return chip->info->pvt; 769 } 770 771 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 772 { 773 return !!chip->info->global2_addr; 774 } 775 776 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 777 { 778 return chip->info->num_databases; 779 } 780 781 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 782 { 783 return chip->info->num_macs; 784 } 785 786 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 787 { 788 return chip->info->num_ports; 789 } 790 791 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 792 { 793 return chip->info->max_vid; 794 } 795 796 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 797 { 798 return chip->info->max_sid; 799 } 800 801 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 802 { 803 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 804 } 805 806 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 807 { 808 return chip->info->num_gpio; 809 } 810 811 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 812 { 813 return (chip->info->invalid_port_mask & BIT(port)) != 0; 814 } 815 816 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 817 int port, bool mab) 818 { 819 chip->ports[port].mab = mab; 820 } 821 822 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 823 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 824 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 825 u16 mask, u16 val); 826 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 827 int bit, int val); 828 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 829 830 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 831 { 832 mutex_lock(&chip->reg_lock); 833 } 834 835 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 836 { 837 mutex_unlock(&chip->reg_lock); 838 } 839 840 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 841 int (*cb)(struct mv88e6xxx_chip *chip, 842 const struct mv88e6xxx_vtu_entry *entry, 843 void *priv), 844 void *priv); 845 846 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 847 848 #endif /* _MV88E6XXX_CHIP_H */ 849