1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/leds.h> 17 #include <linux/phy.h> 18 #include <linux/property.h> 19 #include <linux/ptp_clock_kernel.h> 20 #include <linux/timecounter.h> 21 #include <net/dsa.h> 22 23 #define EDSA_HLEN 8 24 #define MV88E6XXX_N_FID 4096 25 #define MV88E6XXX_N_SID 64 26 27 #define MV88E6XXX_FID_STANDALONE 0 28 #define MV88E6XXX_FID_BRIDGED 1 29 30 /* PVT limits for 4-bit port and 5-bit switch */ 31 #define MV88E6XXX_MAX_PVT_SWITCHES 32 32 #define MV88E6XXX_MAX_PVT_PORTS 16 33 #define MV88E6XXX_MAX_PVT_ENTRIES \ 34 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 35 36 #define MV88E6XXX_MAX_GPIO 16 37 38 enum mv88e6xxx_egress_mode { 39 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 40 MV88E6XXX_EGRESS_MODE_UNTAGGED, 41 MV88E6XXX_EGRESS_MODE_TAGGED, 42 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 43 }; 44 45 enum mv88e6xxx_egress_direction { 46 MV88E6XXX_EGRESS_DIR_INGRESS, 47 MV88E6XXX_EGRESS_DIR_EGRESS, 48 }; 49 50 enum mv88e6xxx_frame_mode { 51 MV88E6XXX_FRAME_MODE_NORMAL, 52 MV88E6XXX_FRAME_MODE_DSA, 53 MV88E6XXX_FRAME_MODE_PROVIDER, 54 MV88E6XXX_FRAME_MODE_ETHERTYPE, 55 }; 56 57 /* List of supported models */ 58 enum mv88e6xxx_model { 59 MV88E6020, 60 MV88E6071, 61 MV88E6085, 62 MV88E6095, 63 MV88E6097, 64 MV88E6123, 65 MV88E6131, 66 MV88E6141, 67 MV88E6161, 68 MV88E6165, 69 MV88E6171, 70 MV88E6172, 71 MV88E6175, 72 MV88E6176, 73 MV88E6185, 74 MV88E6190, 75 MV88E6190X, 76 MV88E6191, 77 MV88E6191X, 78 MV88E6193X, 79 MV88E6220, 80 MV88E6240, 81 MV88E6250, 82 MV88E6290, 83 MV88E6320, 84 MV88E6321, 85 MV88E6341, 86 MV88E6350, 87 MV88E6351, 88 MV88E6352, 89 MV88E6361, 90 MV88E6390, 91 MV88E6390X, 92 MV88E6393X, 93 }; 94 95 enum mv88e6xxx_family { 96 MV88E6XXX_FAMILY_NONE, 97 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 98 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 99 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 100 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 101 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 102 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */ 103 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 104 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 105 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 106 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 107 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 108 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 109 }; 110 111 /** 112 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 113 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 114 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 115 * egressing FORWARD frames with an EDSA 116 * tag is reserved for future use, but 117 * empirical data shows that this mode 118 * is supported. 119 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 120 */ 121 enum mv88e6xxx_edsa_support { 122 MV88E6XXX_EDSA_UNSUPPORTED = 0, 123 MV88E6XXX_EDSA_UNDOCUMENTED, 124 MV88E6XXX_EDSA_SUPPORTED, 125 }; 126 127 struct mv88e6xxx_ops; 128 129 struct mv88e6xxx_info { 130 enum mv88e6xxx_family family; 131 u16 prod_num; 132 const char *name; 133 unsigned int num_databases; 134 unsigned int num_macs; 135 unsigned int num_ports; 136 unsigned int num_internal_phys; 137 unsigned int num_gpio; 138 unsigned int max_vid; 139 unsigned int max_sid; 140 unsigned int port_base_addr; 141 unsigned int phy_base_addr; 142 unsigned int global1_addr; 143 unsigned int global2_addr; 144 unsigned int age_time_coeff; 145 unsigned int g1_irqs; 146 unsigned int g2_irqs; 147 int stats_type; 148 bool pvt; 149 150 /* Mark certain ports as invalid. This is required for example for the 151 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 152 * ports 2-4 are not routet to pins. 153 */ 154 unsigned int invalid_port_mask; 155 /* Multi-chip Addressing Mode. 156 * Some chips respond to only 2 registers of its own SMI device address 157 * when it is non-zero, and use indirect access to internal registers. 158 */ 159 bool multi_chip; 160 /* Dual-chip Addressing Mode 161 * Some chips respond to only half of the 32 SMI addresses, 162 * allowing two to coexist on the same SMI interface. 163 */ 164 bool dual_chip; 165 166 enum mv88e6xxx_edsa_support edsa_support; 167 168 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 169 * operation. 0 means that the ATU Move operation is not supported. 170 */ 171 u8 atu_move_port_mask; 172 const struct mv88e6xxx_ops *ops; 173 174 /* Supports PTP */ 175 bool ptp_support; 176 177 /* Internal PHY start index. 0 means that internal PHYs range starts at 178 * port 0, 1 means internal PHYs range starts at port 1, etc 179 */ 180 unsigned int internal_phys_offset; 181 }; 182 183 struct mv88e6xxx_atu_entry { 184 u8 state; 185 bool trunk; 186 u16 portvec; 187 u8 mac[ETH_ALEN]; 188 }; 189 190 struct mv88e6xxx_vtu_entry { 191 u16 vid; 192 u16 fid; 193 u8 sid; 194 bool valid; 195 bool policy; 196 u8 member[DSA_MAX_PORTS]; 197 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 198 }; 199 200 struct mv88e6xxx_stu_entry { 201 u8 sid; 202 bool valid; 203 u8 state[DSA_MAX_PORTS]; 204 }; 205 206 struct mv88e6xxx_bus_ops; 207 struct mv88e6xxx_irq_ops; 208 struct mv88e6xxx_gpio_ops; 209 struct mv88e6xxx_avb_ops; 210 struct mv88e6xxx_ptp_ops; 211 struct mv88e6xxx_pcs_ops; 212 struct mv88e6xxx_cc_coeffs; 213 214 struct mv88e6xxx_irq { 215 u16 masked; 216 struct irq_chip chip; 217 struct irq_domain *domain; 218 int nirqs; 219 }; 220 221 /* state flags for mv88e6xxx_port_hwtstamp::state */ 222 enum { 223 MV88E6XXX_HWTSTAMP_ENABLED, 224 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 225 }; 226 227 struct mv88e6xxx_port_hwtstamp { 228 /* Port index */ 229 int port_id; 230 231 /* Timestamping state */ 232 unsigned long state; 233 234 /* Resources for receive timestamping */ 235 struct sk_buff_head rx_queue; 236 struct sk_buff_head rx_queue2; 237 238 /* Resources for transmit timestamping */ 239 unsigned long tx_tstamp_start; 240 struct sk_buff *tx_skb; 241 u16 tx_seq_id; 242 243 /* Current timestamp configuration */ 244 struct kernel_hwtstamp_config tstamp_config; 245 }; 246 247 enum mv88e6xxx_policy_mapping { 248 MV88E6XXX_POLICY_MAPPING_DA, 249 MV88E6XXX_POLICY_MAPPING_SA, 250 MV88E6XXX_POLICY_MAPPING_VTU, 251 MV88E6XXX_POLICY_MAPPING_ETYPE, 252 MV88E6XXX_POLICY_MAPPING_PPPOE, 253 MV88E6XXX_POLICY_MAPPING_VBAS, 254 MV88E6XXX_POLICY_MAPPING_OPT82, 255 MV88E6XXX_POLICY_MAPPING_UDP, 256 }; 257 258 enum mv88e6xxx_policy_action { 259 MV88E6XXX_POLICY_ACTION_NORMAL, 260 MV88E6XXX_POLICY_ACTION_MIRROR, 261 MV88E6XXX_POLICY_ACTION_TRAP, 262 MV88E6XXX_POLICY_ACTION_DISCARD, 263 }; 264 265 struct mv88e6xxx_policy { 266 enum mv88e6xxx_policy_mapping mapping; 267 enum mv88e6xxx_policy_action action; 268 struct ethtool_rx_flow_spec fs; 269 u8 addr[ETH_ALEN]; 270 int port; 271 u16 vid; 272 }; 273 274 struct mv88e6xxx_vlan { 275 u16 vid; 276 bool valid; 277 }; 278 279 struct mv88e6xxx_port { 280 struct mv88e6xxx_chip *chip; 281 int port; 282 struct fwnode_handle *fwnode; 283 struct mv88e6xxx_vlan bridge_pvid; 284 u64 serdes_stats[2]; 285 u64 atu_member_violation; 286 u64 atu_miss_violation; 287 u64 atu_full_violation; 288 u64 vtu_member_violation; 289 u64 vtu_miss_violation; 290 phy_interface_t interface; 291 u8 cmode; 292 bool mirror_ingress; 293 bool mirror_egress; 294 struct devlink_region *region; 295 void *pcs_private; 296 297 /* LED related information */ 298 bool fiber; 299 struct led_classdev led0; 300 struct led_classdev led1; 301 302 /* MacAuth Bypass control flag */ 303 bool mab; 304 }; 305 306 enum mv88e6xxx_region_id { 307 MV88E6XXX_REGION_GLOBAL1 = 0, 308 MV88E6XXX_REGION_GLOBAL2, 309 MV88E6XXX_REGION_ATU, 310 MV88E6XXX_REGION_VTU, 311 MV88E6XXX_REGION_STU, 312 MV88E6XXX_REGION_PVT, 313 314 _MV88E6XXX_REGION_MAX, 315 }; 316 317 struct mv88e6xxx_region_priv { 318 enum mv88e6xxx_region_id id; 319 }; 320 321 struct mv88e6xxx_mst { 322 struct list_head node; 323 324 refcount_t refcnt; 325 struct net_device *br; 326 u16 msti; 327 328 struct mv88e6xxx_stu_entry stu; 329 }; 330 331 #define STATS_TYPE_PORT BIT(0) 332 #define STATS_TYPE_BANK0 BIT(1) 333 #define STATS_TYPE_BANK1 BIT(2) 334 335 struct mv88e6xxx_hw_stat { 336 char string[ETH_GSTRING_LEN]; 337 size_t size; 338 int reg; 339 int type; 340 }; 341 342 struct mv88e6xxx_chip { 343 const struct mv88e6xxx_info *info; 344 345 /* Currently configured tagging protocol */ 346 enum dsa_tag_protocol tag_protocol; 347 348 /* The dsa_switch this private structure is related to */ 349 struct dsa_switch *ds; 350 351 /* The device this structure is associated to */ 352 struct device *dev; 353 354 /* This mutex protects the access to the switch registers */ 355 struct mutex reg_lock; 356 357 /* The MII bus and the address on the bus that is used to 358 * communication with the switch 359 */ 360 const struct mv88e6xxx_bus_ops *smi_ops; 361 struct mii_bus *bus; 362 int sw_addr; 363 364 /* Handles automatic disabling and re-enabling of the PHY 365 * polling unit. 366 */ 367 const struct mv88e6xxx_bus_ops *phy_ops; 368 struct mutex ppu_mutex; 369 int ppu_disabled; 370 struct work_struct ppu_work; 371 struct timer_list ppu_timer; 372 373 /* This mutex serialises access to the statistics unit. 374 * Hold this mutex over snapshot + dump sequences. 375 */ 376 struct mutex stats_mutex; 377 378 /* A switch may have a GPIO line tied to its reset pin. Parse 379 * this from the device tree, and use it before performing 380 * switch soft reset. 381 */ 382 struct gpio_desc *reset; 383 384 /* set to size of eeprom if supported by the switch */ 385 u32 eeprom_len; 386 387 /* List of mdio busses */ 388 struct list_head mdios; 389 390 /* Policy Control List IDs and rules */ 391 struct idr policies; 392 393 /* There can be two interrupt controllers, which are chained 394 * off a GPIO as interrupt source 395 */ 396 struct mv88e6xxx_irq g1_irq; 397 struct mv88e6xxx_irq g2_irq; 398 int irq; 399 char irq_name[64]; 400 int device_irq; 401 char device_irq_name[64]; 402 int watchdog_irq; 403 char watchdog_irq_name[64]; 404 405 int atu_prob_irq; 406 char atu_prob_irq_name[64]; 407 int vtu_prob_irq; 408 char vtu_prob_irq_name[64]; 409 struct kthread_worker *kworker; 410 struct kthread_delayed_work irq_poll_work; 411 412 /* GPIO resources */ 413 u8 gpio_data[2]; 414 415 /* This cyclecounter abstracts the switch PTP time. 416 * reg_lock must be held for any operation that read()s. 417 */ 418 struct cyclecounter tstamp_cc; 419 struct timecounter tstamp_tc; 420 struct delayed_work overflow_work; 421 const struct mv88e6xxx_cc_coeffs *cc_coeffs; 422 423 struct ptp_clock *ptp_clock; 424 struct ptp_clock_info ptp_clock_info; 425 struct delayed_work tai_event_work; 426 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 427 u16 enable_count; 428 429 /* Current ingress and egress monitor ports */ 430 int egress_dest_port; 431 int ingress_dest_port; 432 433 /* Per-port timestamping resources. */ 434 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 435 436 /* Array of port structures. */ 437 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 438 439 /* devlink regions */ 440 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 441 442 /* Bridge MST to SID mappings */ 443 struct list_head msts; 444 445 /* FID map */ 446 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 447 }; 448 449 struct mv88e6xxx_bus_ops { 450 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 451 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 452 int (*init)(struct mv88e6xxx_chip *chip); 453 }; 454 455 struct mv88e6xxx_mdio_bus { 456 struct mii_bus *bus; 457 struct mv88e6xxx_chip *chip; 458 struct list_head list; 459 bool external; 460 }; 461 462 struct mv88e6xxx_ops { 463 /* Switch Setup Errata, called early in the switch setup to 464 * allow any errata actions to be performed 465 */ 466 int (*setup_errata)(struct mv88e6xxx_chip *chip); 467 468 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 469 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 470 471 /* Ingress Rate Limit unit (IRL) operations */ 472 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 473 474 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 475 struct ethtool_eeprom *eeprom, u8 *data); 476 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 477 struct ethtool_eeprom *eeprom, u8 *data); 478 479 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 480 481 int (*phy_read)(struct mv88e6xxx_chip *chip, 482 struct mii_bus *bus, 483 int addr, int reg, u16 *val); 484 int (*phy_write)(struct mv88e6xxx_chip *chip, 485 struct mii_bus *bus, 486 int addr, int reg, u16 val); 487 488 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 489 struct mii_bus *bus, 490 int addr, int devad, int reg, u16 *val); 491 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 492 struct mii_bus *bus, 493 int addr, int devad, int reg, u16 val); 494 495 /* Priority Override Table operations */ 496 int (*pot_clear)(struct mv88e6xxx_chip *chip); 497 498 /* PHY Polling Unit (PPU) operations */ 499 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 500 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 501 502 /* Additional handlers to run before and after hard reset, to make sure 503 * that the switch and EEPROM are in a good state. 504 */ 505 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip); 506 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip); 507 508 /* Switch Software Reset */ 509 int (*reset)(struct mv88e6xxx_chip *chip); 510 511 /* RGMII Receive/Transmit Timing Control 512 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 513 */ 514 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 515 phy_interface_t mode); 516 517 #define LINK_FORCED_DOWN 0 518 #define LINK_FORCED_UP 1 519 #define LINK_UNFORCED -2 520 521 /* Port's MAC link state 522 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 523 * or LINK_UNFORCED for normal link detection. 524 */ 525 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 526 527 /* Synchronise the port link state with that of the SERDES 528 */ 529 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 530 531 #define PAUSE_ON 1 532 #define PAUSE_OFF 0 533 534 /* Enable/disable sending Pause */ 535 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 536 int pause); 537 538 #define SPEED_UNFORCED -2 539 #define DUPLEX_UNFORCED -2 540 541 /* Port's MAC speed (in Mbps) and MAC duplex mode 542 * 543 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 544 * Use SPEED_UNFORCED for normal detection. 545 * 546 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 547 * or DUPLEX_UNFORCED for normal duplex detection. 548 */ 549 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 550 int speed, int duplex); 551 552 /* What interface mode should be used for maximum speed? */ 553 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 554 int port); 555 556 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 557 558 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 559 enum mv88e6xxx_policy_mapping mapping, 560 enum mv88e6xxx_policy_action action); 561 562 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 563 enum mv88e6xxx_frame_mode mode); 564 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 565 bool unicast); 566 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 567 bool multicast); 568 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 569 u16 etype); 570 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 571 size_t size); 572 573 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 574 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 575 u8 out); 576 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 577 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 578 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 579 580 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 581 * Some chips allow this to be configured on specific ports. 582 */ 583 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 584 phy_interface_t mode); 585 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 586 587 /* LED control */ 588 int (*port_setup_leds)(struct mv88e6xxx_chip *chip, int port); 589 590 /* Some devices have a per port register indicating what is 591 * the upstream port this port should forward to. 592 */ 593 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 594 int upstream_port); 595 596 /* Snapshot the statistics for a port. The statistics can then 597 * be read back a leisure but still with a consistent view. 598 */ 599 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 600 601 /* Set the histogram mode for statistics, when the control registers 602 * are separated out of the STATS_OP register. 603 */ 604 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 605 606 /* Return the number of strings describing statistics */ 607 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 608 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t **data); 609 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port, 610 const struct mv88e6xxx_hw_stat *stat, 611 uint64_t *data); 612 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 613 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 614 enum mv88e6xxx_egress_direction direction, 615 int port); 616 617 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 618 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 619 620 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 621 622 const struct mv88e6xxx_irq_ops *watchdog_ops; 623 624 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 625 626 /* SERDES lane mapping */ 627 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 628 629 /* SERDES interrupt handling */ 630 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 631 int port); 632 633 /* Statistics from the SERDES interface */ 634 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 635 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 636 uint8_t **data); 637 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 638 uint64_t *data); 639 640 /* SERDES registers for ethtool */ 641 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 642 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 643 void *_p); 644 645 /* SERDES SGMII/Fiber Output Amplitude */ 646 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 647 int val); 648 649 /* Address Translation Unit operations */ 650 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 651 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 652 653 /* VLAN Translation Unit operations */ 654 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 655 struct mv88e6xxx_vtu_entry *entry); 656 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 657 struct mv88e6xxx_vtu_entry *entry); 658 659 /* Spanning Tree Unit operations */ 660 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 661 struct mv88e6xxx_stu_entry *entry); 662 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 663 struct mv88e6xxx_stu_entry *entry); 664 665 /* GPIO operations */ 666 const struct mv88e6xxx_gpio_ops *gpio_ops; 667 668 /* Interface to the AVB/PTP registers */ 669 const struct mv88e6xxx_avb_ops *avb_ops; 670 671 /* Remote Management Unit operations */ 672 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 673 674 /* Precision Time Protocol operations */ 675 const struct mv88e6xxx_ptp_ops *ptp_ops; 676 677 /* Phylink */ 678 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config); 680 681 const struct mv88e6xxx_pcs_ops *pcs_ops; 682 683 /* Max Frame Size */ 684 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 685 }; 686 687 struct mv88e6xxx_irq_ops { 688 /* Action to be performed when the interrupt happens */ 689 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 690 /* Setup the hardware to generate the interrupt */ 691 int (*irq_setup)(struct mv88e6xxx_chip *chip); 692 /* Reset the hardware to stop generating the interrupt */ 693 void (*irq_free)(struct mv88e6xxx_chip *chip); 694 }; 695 696 struct mv88e6xxx_gpio_ops { 697 /* Get/set data on GPIO pin */ 698 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 699 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 700 int value); 701 702 /* get/set GPIO direction */ 703 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 704 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 705 bool input); 706 707 /* get/set GPIO pin control */ 708 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 709 int *func); 710 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 711 int func); 712 }; 713 714 struct mv88e6xxx_avb_ops { 715 /* Access port-scoped Precision Time Protocol registers */ 716 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 717 u16 *data, int len); 718 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 719 u16 data); 720 721 /* Access global Precision Time Protocol registers */ 722 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 723 int len); 724 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 725 726 /* Access global Time Application Interface registers */ 727 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 728 int len); 729 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 730 }; 731 732 struct mv88e6xxx_ptp_ops { 733 u64 (*clock_read)(struct cyclecounter *cc); 734 int (*ptp_enable)(struct ptp_clock_info *ptp, 735 struct ptp_clock_request *rq, int on); 736 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 737 enum ptp_pin_function func, unsigned int chan); 738 void (*event_work)(struct work_struct *ugly); 739 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 740 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 741 int (*global_enable)(struct mv88e6xxx_chip *chip); 742 int (*global_disable)(struct mv88e6xxx_chip *chip); 743 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 744 int n_ext_ts; 745 int arr0_sts_reg; 746 int arr1_sts_reg; 747 int dep_sts_reg; 748 u32 rx_filters; 749 }; 750 751 struct mv88e6xxx_pcs_ops { 752 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port); 753 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port); 754 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port, 755 phy_interface_t mode); 756 757 }; 758 759 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 760 { 761 return chip->info->max_sid > 0 && 762 chip->info->ops->stu_loadpurge && 763 chip->info->ops->stu_getnext; 764 } 765 766 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 767 { 768 return chip->info->pvt; 769 } 770 771 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 772 { 773 return !!chip->info->global2_addr; 774 } 775 776 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 777 { 778 return chip->info->num_databases; 779 } 780 781 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 782 { 783 return chip->info->num_macs; 784 } 785 786 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 787 { 788 return chip->info->num_ports; 789 } 790 791 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 792 { 793 return chip->info->max_vid; 794 } 795 796 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 797 { 798 return chip->info->max_sid; 799 } 800 801 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 802 { 803 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 804 } 805 806 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 807 { 808 return chip->info->num_gpio; 809 } 810 811 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 812 { 813 return (chip->info->invalid_port_mask & BIT(port)) != 0; 814 } 815 816 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 817 int port, bool mab) 818 { 819 chip->ports[port].mab = mab; 820 } 821 822 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 823 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 824 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 825 u16 mask, u16 val); 826 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 827 int bit, int val); 828 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 829 830 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 831 { 832 mutex_lock(&chip->reg_lock); 833 } 834 835 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 836 { 837 mutex_unlock(&chip->reg_lock); 838 } 839 840 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 841 int (*cb)(struct mv88e6xxx_chip *chip, 842 const struct mv88e6xxx_vtu_entry *entry, 843 void *priv), 844 void *priv); 845 846 #endif /* _MV88E6XXX_CHIP_H */ 847