1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 #define MV88E6XXX_N_SID 64 24 25 #define MV88E6XXX_FID_STANDALONE 0 26 #define MV88E6XXX_FID_BRIDGED 1 27 28 /* PVT limits for 4-bit port and 5-bit switch */ 29 #define MV88E6XXX_MAX_PVT_SWITCHES 32 30 #define MV88E6XXX_MAX_PVT_PORTS 16 31 #define MV88E6XXX_MAX_PVT_ENTRIES \ 32 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 33 34 #define MV88E6XXX_MAX_GPIO 16 35 36 enum mv88e6xxx_egress_mode { 37 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 38 MV88E6XXX_EGRESS_MODE_UNTAGGED, 39 MV88E6XXX_EGRESS_MODE_TAGGED, 40 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 41 }; 42 43 enum mv88e6xxx_egress_direction { 44 MV88E6XXX_EGRESS_DIR_INGRESS, 45 MV88E6XXX_EGRESS_DIR_EGRESS, 46 }; 47 48 enum mv88e6xxx_frame_mode { 49 MV88E6XXX_FRAME_MODE_NORMAL, 50 MV88E6XXX_FRAME_MODE_DSA, 51 MV88E6XXX_FRAME_MODE_PROVIDER, 52 MV88E6XXX_FRAME_MODE_ETHERTYPE, 53 }; 54 55 /* List of supported models */ 56 enum mv88e6xxx_model { 57 MV88E6085, 58 MV88E6095, 59 MV88E6097, 60 MV88E6123, 61 MV88E6131, 62 MV88E6141, 63 MV88E6161, 64 MV88E6165, 65 MV88E6171, 66 MV88E6172, 67 MV88E6175, 68 MV88E6176, 69 MV88E6185, 70 MV88E6190, 71 MV88E6190X, 72 MV88E6191, 73 MV88E6191X, 74 MV88E6193X, 75 MV88E6220, 76 MV88E6240, 77 MV88E6250, 78 MV88E6290, 79 MV88E6320, 80 MV88E6321, 81 MV88E6341, 82 MV88E6350, 83 MV88E6351, 84 MV88E6352, 85 MV88E6361, 86 MV88E6390, 87 MV88E6390X, 88 MV88E6393X, 89 }; 90 91 enum mv88e6xxx_family { 92 MV88E6XXX_FAMILY_NONE, 93 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 94 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 95 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 96 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 97 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 98 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 99 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 100 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 101 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 102 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 103 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 104 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */ 105 }; 106 107 /** 108 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 109 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 110 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 111 * egressing FORWARD frames with an EDSA 112 * tag is reserved for future use, but 113 * empirical data shows that this mode 114 * is supported. 115 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 116 */ 117 enum mv88e6xxx_edsa_support { 118 MV88E6XXX_EDSA_UNSUPPORTED = 0, 119 MV88E6XXX_EDSA_UNDOCUMENTED, 120 MV88E6XXX_EDSA_SUPPORTED, 121 }; 122 123 struct mv88e6xxx_ops; 124 125 struct mv88e6xxx_info { 126 enum mv88e6xxx_family family; 127 u16 prod_num; 128 const char *name; 129 unsigned int num_databases; 130 unsigned int num_macs; 131 unsigned int num_ports; 132 unsigned int num_internal_phys; 133 unsigned int num_gpio; 134 unsigned int max_vid; 135 unsigned int max_sid; 136 unsigned int port_base_addr; 137 unsigned int phy_base_addr; 138 unsigned int global1_addr; 139 unsigned int global2_addr; 140 unsigned int age_time_coeff; 141 unsigned int g1_irqs; 142 unsigned int g2_irqs; 143 bool pvt; 144 145 /* Mark certain ports as invalid. This is required for example for the 146 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 147 * ports 2-4 are not routet to pins. 148 */ 149 unsigned int invalid_port_mask; 150 /* Multi-chip Addressing Mode. 151 * Some chips respond to only 2 registers of its own SMI device address 152 * when it is non-zero, and use indirect access to internal registers. 153 */ 154 bool multi_chip; 155 /* Dual-chip Addressing Mode 156 * Some chips respond to only half of the 32 SMI addresses, 157 * allowing two to coexist on the same SMI interface. 158 */ 159 bool dual_chip; 160 161 enum mv88e6xxx_edsa_support edsa_support; 162 163 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 164 * operation. 0 means that the ATU Move operation is not supported. 165 */ 166 u8 atu_move_port_mask; 167 const struct mv88e6xxx_ops *ops; 168 169 /* Supports PTP */ 170 bool ptp_support; 171 172 /* Internal PHY start index. 0 means that internal PHYs range starts at 173 * port 0, 1 means internal PHYs range starts at port 1, etc 174 */ 175 unsigned int internal_phys_offset; 176 }; 177 178 struct mv88e6xxx_atu_entry { 179 u8 state; 180 bool trunk; 181 u16 portvec; 182 u8 mac[ETH_ALEN]; 183 }; 184 185 struct mv88e6xxx_vtu_entry { 186 u16 vid; 187 u16 fid; 188 u8 sid; 189 bool valid; 190 bool policy; 191 u8 member[DSA_MAX_PORTS]; 192 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */ 193 }; 194 195 struct mv88e6xxx_stu_entry { 196 u8 sid; 197 bool valid; 198 u8 state[DSA_MAX_PORTS]; 199 }; 200 201 struct mv88e6xxx_bus_ops; 202 struct mv88e6xxx_irq_ops; 203 struct mv88e6xxx_gpio_ops; 204 struct mv88e6xxx_avb_ops; 205 struct mv88e6xxx_ptp_ops; 206 207 struct mv88e6xxx_irq { 208 u16 masked; 209 struct irq_chip chip; 210 struct irq_domain *domain; 211 int nirqs; 212 }; 213 214 /* state flags for mv88e6xxx_port_hwtstamp::state */ 215 enum { 216 MV88E6XXX_HWTSTAMP_ENABLED, 217 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 218 }; 219 220 struct mv88e6xxx_port_hwtstamp { 221 /* Port index */ 222 int port_id; 223 224 /* Timestamping state */ 225 unsigned long state; 226 227 /* Resources for receive timestamping */ 228 struct sk_buff_head rx_queue; 229 struct sk_buff_head rx_queue2; 230 231 /* Resources for transmit timestamping */ 232 unsigned long tx_tstamp_start; 233 struct sk_buff *tx_skb; 234 u16 tx_seq_id; 235 236 /* Current timestamp configuration */ 237 struct hwtstamp_config tstamp_config; 238 }; 239 240 enum mv88e6xxx_policy_mapping { 241 MV88E6XXX_POLICY_MAPPING_DA, 242 MV88E6XXX_POLICY_MAPPING_SA, 243 MV88E6XXX_POLICY_MAPPING_VTU, 244 MV88E6XXX_POLICY_MAPPING_ETYPE, 245 MV88E6XXX_POLICY_MAPPING_PPPOE, 246 MV88E6XXX_POLICY_MAPPING_VBAS, 247 MV88E6XXX_POLICY_MAPPING_OPT82, 248 MV88E6XXX_POLICY_MAPPING_UDP, 249 }; 250 251 enum mv88e6xxx_policy_action { 252 MV88E6XXX_POLICY_ACTION_NORMAL, 253 MV88E6XXX_POLICY_ACTION_MIRROR, 254 MV88E6XXX_POLICY_ACTION_TRAP, 255 MV88E6XXX_POLICY_ACTION_DISCARD, 256 }; 257 258 struct mv88e6xxx_policy { 259 enum mv88e6xxx_policy_mapping mapping; 260 enum mv88e6xxx_policy_action action; 261 struct ethtool_rx_flow_spec fs; 262 u8 addr[ETH_ALEN]; 263 int port; 264 u16 vid; 265 }; 266 267 struct mv88e6xxx_vlan { 268 u16 vid; 269 bool valid; 270 }; 271 272 struct mv88e6xxx_port { 273 struct mv88e6xxx_chip *chip; 274 int port; 275 struct mv88e6xxx_vlan bridge_pvid; 276 u64 serdes_stats[2]; 277 u64 atu_member_violation; 278 u64 atu_miss_violation; 279 u64 atu_full_violation; 280 u64 vtu_member_violation; 281 u64 vtu_miss_violation; 282 phy_interface_t interface; 283 u8 cmode; 284 bool mirror_ingress; 285 bool mirror_egress; 286 unsigned int serdes_irq; 287 char serdes_irq_name[64]; 288 struct devlink_region *region; 289 290 /* MacAuth Bypass control flag */ 291 bool mab; 292 }; 293 294 enum mv88e6xxx_region_id { 295 MV88E6XXX_REGION_GLOBAL1 = 0, 296 MV88E6XXX_REGION_GLOBAL2, 297 MV88E6XXX_REGION_ATU, 298 MV88E6XXX_REGION_VTU, 299 MV88E6XXX_REGION_STU, 300 MV88E6XXX_REGION_PVT, 301 302 _MV88E6XXX_REGION_MAX, 303 }; 304 305 struct mv88e6xxx_region_priv { 306 enum mv88e6xxx_region_id id; 307 }; 308 309 struct mv88e6xxx_mst { 310 struct list_head node; 311 312 refcount_t refcnt; 313 struct net_device *br; 314 u16 msti; 315 316 struct mv88e6xxx_stu_entry stu; 317 }; 318 319 struct mv88e6xxx_chip { 320 const struct mv88e6xxx_info *info; 321 322 /* Currently configured tagging protocol */ 323 enum dsa_tag_protocol tag_protocol; 324 325 /* The dsa_switch this private structure is related to */ 326 struct dsa_switch *ds; 327 328 /* The device this structure is associated to */ 329 struct device *dev; 330 331 /* This mutex protects the access to the switch registers */ 332 struct mutex reg_lock; 333 334 /* The MII bus and the address on the bus that is used to 335 * communication with the switch 336 */ 337 const struct mv88e6xxx_bus_ops *smi_ops; 338 struct mii_bus *bus; 339 int sw_addr; 340 341 /* Handles automatic disabling and re-enabling of the PHY 342 * polling unit. 343 */ 344 const struct mv88e6xxx_bus_ops *phy_ops; 345 struct mutex ppu_mutex; 346 int ppu_disabled; 347 struct work_struct ppu_work; 348 struct timer_list ppu_timer; 349 350 /* This mutex serialises access to the statistics unit. 351 * Hold this mutex over snapshot + dump sequences. 352 */ 353 struct mutex stats_mutex; 354 355 /* A switch may have a GPIO line tied to its reset pin. Parse 356 * this from the device tree, and use it before performing 357 * switch soft reset. 358 */ 359 struct gpio_desc *reset; 360 361 /* set to size of eeprom if supported by the switch */ 362 u32 eeprom_len; 363 364 /* List of mdio busses */ 365 struct list_head mdios; 366 367 /* Policy Control List IDs and rules */ 368 struct idr policies; 369 370 /* There can be two interrupt controllers, which are chained 371 * off a GPIO as interrupt source 372 */ 373 struct mv88e6xxx_irq g1_irq; 374 struct mv88e6xxx_irq g2_irq; 375 int irq; 376 char irq_name[64]; 377 int device_irq; 378 char device_irq_name[64]; 379 int watchdog_irq; 380 char watchdog_irq_name[64]; 381 382 int atu_prob_irq; 383 char atu_prob_irq_name[64]; 384 int vtu_prob_irq; 385 char vtu_prob_irq_name[64]; 386 struct kthread_worker *kworker; 387 struct kthread_delayed_work irq_poll_work; 388 389 /* GPIO resources */ 390 u8 gpio_data[2]; 391 392 /* This cyclecounter abstracts the switch PTP time. 393 * reg_lock must be held for any operation that read()s. 394 */ 395 struct cyclecounter tstamp_cc; 396 struct timecounter tstamp_tc; 397 struct delayed_work overflow_work; 398 399 struct ptp_clock *ptp_clock; 400 struct ptp_clock_info ptp_clock_info; 401 struct delayed_work tai_event_work; 402 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 403 u16 trig_config; 404 u16 evcap_config; 405 u16 enable_count; 406 407 /* Current ingress and egress monitor ports */ 408 int egress_dest_port; 409 int ingress_dest_port; 410 411 /* Per-port timestamping resources. */ 412 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 413 414 /* Array of port structures. */ 415 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 416 417 /* devlink regions */ 418 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 419 420 /* Bridge MST to SID mappings */ 421 struct list_head msts; 422 }; 423 424 struct mv88e6xxx_bus_ops { 425 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 426 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 427 int (*init)(struct mv88e6xxx_chip *chip); 428 }; 429 430 struct mv88e6xxx_mdio_bus { 431 struct mii_bus *bus; 432 struct mv88e6xxx_chip *chip; 433 struct list_head list; 434 bool external; 435 }; 436 437 struct mv88e6xxx_ops { 438 /* Switch Setup Errata, called early in the switch setup to 439 * allow any errata actions to be performed 440 */ 441 int (*setup_errata)(struct mv88e6xxx_chip *chip); 442 443 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 444 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 445 446 /* Ingress Rate Limit unit (IRL) operations */ 447 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 448 449 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 450 struct ethtool_eeprom *eeprom, u8 *data); 451 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 452 struct ethtool_eeprom *eeprom, u8 *data); 453 454 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 455 456 int (*phy_read)(struct mv88e6xxx_chip *chip, 457 struct mii_bus *bus, 458 int addr, int reg, u16 *val); 459 int (*phy_write)(struct mv88e6xxx_chip *chip, 460 struct mii_bus *bus, 461 int addr, int reg, u16 val); 462 463 int (*phy_read_c45)(struct mv88e6xxx_chip *chip, 464 struct mii_bus *bus, 465 int addr, int devad, int reg, u16 *val); 466 int (*phy_write_c45)(struct mv88e6xxx_chip *chip, 467 struct mii_bus *bus, 468 int addr, int devad, int reg, u16 val); 469 470 /* Priority Override Table operations */ 471 int (*pot_clear)(struct mv88e6xxx_chip *chip); 472 473 /* PHY Polling Unit (PPU) operations */ 474 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 475 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 476 477 /* Switch Software Reset */ 478 int (*reset)(struct mv88e6xxx_chip *chip); 479 480 /* RGMII Receive/Transmit Timing Control 481 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 482 */ 483 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 484 phy_interface_t mode); 485 486 #define LINK_FORCED_DOWN 0 487 #define LINK_FORCED_UP 1 488 #define LINK_UNFORCED -2 489 490 /* Port's MAC link state 491 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 492 * or LINK_UNFORCED for normal link detection. 493 */ 494 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 495 496 /* Synchronise the port link state with that of the SERDES 497 */ 498 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 499 500 #define PAUSE_ON 1 501 #define PAUSE_OFF 0 502 503 /* Enable/disable sending Pause */ 504 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 505 int pause); 506 507 #define SPEED_UNFORCED -2 508 #define DUPLEX_UNFORCED -2 509 510 /* Port's MAC speed (in Mbps) and MAC duplex mode 511 * 512 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 513 * Use SPEED_UNFORCED for normal detection. 514 * 515 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 516 * or DUPLEX_UNFORCED for normal duplex detection. 517 */ 518 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 519 int speed, int duplex); 520 521 /* What interface mode should be used for maximum speed? */ 522 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip, 523 int port); 524 525 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 526 527 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 528 enum mv88e6xxx_policy_mapping mapping, 529 enum mv88e6xxx_policy_action action); 530 531 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 532 enum mv88e6xxx_frame_mode mode); 533 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 534 bool unicast); 535 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 536 bool multicast); 537 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 538 u16 etype); 539 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 540 size_t size); 541 542 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 543 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 544 u8 out); 545 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 546 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 547 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 548 549 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 550 * Some chips allow this to be configured on specific ports. 551 */ 552 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 553 phy_interface_t mode); 554 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 555 556 /* Some devices have a per port register indicating what is 557 * the upstream port this port should forward to. 558 */ 559 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 560 int upstream_port); 561 562 /* Snapshot the statistics for a port. The statistics can then 563 * be read back a leisure but still with a consistent view. 564 */ 565 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 566 567 /* Set the histogram mode for statistics, when the control registers 568 * are separated out of the STATS_OP register. 569 */ 570 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 571 572 /* Return the number of strings describing statistics */ 573 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 574 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 575 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 576 uint64_t *data); 577 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 578 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 579 enum mv88e6xxx_egress_direction direction, 580 int port); 581 582 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 583 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 584 585 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 586 587 const struct mv88e6xxx_irq_ops *watchdog_ops; 588 589 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 590 591 /* Power on/off a SERDES interface */ 592 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 593 bool up); 594 595 /* SERDES lane mapping */ 596 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 597 598 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 599 int lane, struct phylink_link_state *state); 600 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 601 int lane, unsigned int mode, 602 phy_interface_t interface, 603 const unsigned long *advertise); 604 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 605 int lane); 606 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 607 int lane, int speed, int duplex); 608 609 /* SERDES interrupt handling */ 610 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 611 int port); 612 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 613 bool enable); 614 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 615 int lane); 616 617 /* Statistics from the SERDES interface */ 618 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 619 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 620 uint8_t *data); 621 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 622 uint64_t *data); 623 624 /* SERDES registers for ethtool */ 625 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 626 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 627 void *_p); 628 629 /* SERDES SGMII/Fiber Output Amplitude */ 630 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 631 int val); 632 633 /* Address Translation Unit operations */ 634 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 635 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 636 637 /* VLAN Translation Unit operations */ 638 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 639 struct mv88e6xxx_vtu_entry *entry); 640 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 641 struct mv88e6xxx_vtu_entry *entry); 642 643 /* Spanning Tree Unit operations */ 644 int (*stu_getnext)(struct mv88e6xxx_chip *chip, 645 struct mv88e6xxx_stu_entry *entry); 646 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip, 647 struct mv88e6xxx_stu_entry *entry); 648 649 /* GPIO operations */ 650 const struct mv88e6xxx_gpio_ops *gpio_ops; 651 652 /* Interface to the AVB/PTP registers */ 653 const struct mv88e6xxx_avb_ops *avb_ops; 654 655 /* Remote Management Unit operations */ 656 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 657 658 /* Precision Time Protocol operations */ 659 const struct mv88e6xxx_ptp_ops *ptp_ops; 660 661 /* Phylink */ 662 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 663 struct phylink_config *config); 664 665 /* Max Frame Size */ 666 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 667 }; 668 669 struct mv88e6xxx_irq_ops { 670 /* Action to be performed when the interrupt happens */ 671 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 672 /* Setup the hardware to generate the interrupt */ 673 int (*irq_setup)(struct mv88e6xxx_chip *chip); 674 /* Reset the hardware to stop generating the interrupt */ 675 void (*irq_free)(struct mv88e6xxx_chip *chip); 676 }; 677 678 struct mv88e6xxx_gpio_ops { 679 /* Get/set data on GPIO pin */ 680 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 681 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 682 int value); 683 684 /* get/set GPIO direction */ 685 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 686 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 687 bool input); 688 689 /* get/set GPIO pin control */ 690 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 691 int *func); 692 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 693 int func); 694 }; 695 696 struct mv88e6xxx_avb_ops { 697 /* Access port-scoped Precision Time Protocol registers */ 698 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 699 u16 *data, int len); 700 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 701 u16 data); 702 703 /* Access global Precision Time Protocol registers */ 704 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 705 int len); 706 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 707 708 /* Access global Time Application Interface registers */ 709 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 710 int len); 711 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 712 }; 713 714 struct mv88e6xxx_ptp_ops { 715 u64 (*clock_read)(const struct cyclecounter *cc); 716 int (*ptp_enable)(struct ptp_clock_info *ptp, 717 struct ptp_clock_request *rq, int on); 718 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 719 enum ptp_pin_function func, unsigned int chan); 720 void (*event_work)(struct work_struct *ugly); 721 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 722 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 723 int (*global_enable)(struct mv88e6xxx_chip *chip); 724 int (*global_disable)(struct mv88e6xxx_chip *chip); 725 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port); 726 int n_ext_ts; 727 int arr0_sts_reg; 728 int arr1_sts_reg; 729 int dep_sts_reg; 730 u32 rx_filters; 731 u32 cc_shift; 732 u32 cc_mult; 733 u32 cc_mult_num; 734 u32 cc_mult_dem; 735 }; 736 737 #define STATS_TYPE_PORT BIT(0) 738 #define STATS_TYPE_BANK0 BIT(1) 739 #define STATS_TYPE_BANK1 BIT(2) 740 741 struct mv88e6xxx_hw_stat { 742 char string[ETH_GSTRING_LEN]; 743 size_t size; 744 int reg; 745 int type; 746 }; 747 748 static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip) 749 { 750 return chip->info->max_sid > 0 && 751 chip->info->ops->stu_loadpurge && 752 chip->info->ops->stu_getnext; 753 } 754 755 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 756 { 757 return chip->info->pvt; 758 } 759 760 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 761 { 762 return !!chip->info->global2_addr; 763 } 764 765 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 766 { 767 return chip->info->num_databases; 768 } 769 770 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 771 { 772 return chip->info->num_macs; 773 } 774 775 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 776 { 777 return chip->info->num_ports; 778 } 779 780 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 781 { 782 return chip->info->max_vid; 783 } 784 785 static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip) 786 { 787 return chip->info->max_sid; 788 } 789 790 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 791 { 792 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 793 } 794 795 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 796 { 797 return chip->info->num_gpio; 798 } 799 800 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 801 { 802 return (chip->info->invalid_port_mask & BIT(port)) != 0; 803 } 804 805 static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip, 806 int port, bool mab) 807 { 808 chip->ports[port].mab = mab; 809 } 810 811 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 812 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 813 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 814 u16 mask, u16 val); 815 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 816 int bit, int val); 817 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 818 819 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 820 { 821 mutex_lock(&chip->reg_lock); 822 } 823 824 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 825 { 826 mutex_unlock(&chip->reg_lock); 827 } 828 829 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 830 int (*cb)(struct mv88e6xxx_chip *chip, 831 const struct mv88e6xxx_vtu_entry *entry, 832 void *priv), 833 void *priv); 834 835 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 836 837 #endif /* _MV88E6XXX_CHIP_H */ 838