1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Marvell 88E6xxx Ethernet switch single-chip definition 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 */ 7 8 #ifndef _MV88E6XXX_CHIP_H 9 #define _MV88E6XXX_CHIP_H 10 11 #include <linux/idr.h> 12 #include <linux/if_vlan.h> 13 #include <linux/irq.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/kthread.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/timecounter.h> 19 #include <net/dsa.h> 20 21 #define EDSA_HLEN 8 22 #define MV88E6XXX_N_FID 4096 23 24 #define MV88E6XXX_FID_STANDALONE 0 25 #define MV88E6XXX_FID_BRIDGED 1 26 27 /* PVT limits for 4-bit port and 5-bit switch */ 28 #define MV88E6XXX_MAX_PVT_SWITCHES 32 29 #define MV88E6XXX_MAX_PVT_PORTS 16 30 #define MV88E6XXX_MAX_PVT_ENTRIES \ 31 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS) 32 33 #define MV88E6XXX_MAX_GPIO 16 34 35 enum mv88e6xxx_egress_mode { 36 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 37 MV88E6XXX_EGRESS_MODE_UNTAGGED, 38 MV88E6XXX_EGRESS_MODE_TAGGED, 39 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 40 }; 41 42 enum mv88e6xxx_egress_direction { 43 MV88E6XXX_EGRESS_DIR_INGRESS, 44 MV88E6XXX_EGRESS_DIR_EGRESS, 45 }; 46 47 enum mv88e6xxx_frame_mode { 48 MV88E6XXX_FRAME_MODE_NORMAL, 49 MV88E6XXX_FRAME_MODE_DSA, 50 MV88E6XXX_FRAME_MODE_PROVIDER, 51 MV88E6XXX_FRAME_MODE_ETHERTYPE, 52 }; 53 54 /* List of supported models */ 55 enum mv88e6xxx_model { 56 MV88E6085, 57 MV88E6095, 58 MV88E6097, 59 MV88E6123, 60 MV88E6131, 61 MV88E6141, 62 MV88E6161, 63 MV88E6165, 64 MV88E6171, 65 MV88E6172, 66 MV88E6175, 67 MV88E6176, 68 MV88E6185, 69 MV88E6190, 70 MV88E6190X, 71 MV88E6191, 72 MV88E6191X, 73 MV88E6193X, 74 MV88E6220, 75 MV88E6240, 76 MV88E6250, 77 MV88E6290, 78 MV88E6320, 79 MV88E6321, 80 MV88E6341, 81 MV88E6350, 82 MV88E6351, 83 MV88E6352, 84 MV88E6390, 85 MV88E6390X, 86 MV88E6393X, 87 }; 88 89 enum mv88e6xxx_family { 90 MV88E6XXX_FAMILY_NONE, 91 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ 92 MV88E6XXX_FAMILY_6095, /* 6092 6095 */ 93 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ 94 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ 95 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ 96 MV88E6XXX_FAMILY_6250, /* 6220 6250 */ 97 MV88E6XXX_FAMILY_6320, /* 6320 6321 */ 98 MV88E6XXX_FAMILY_6341, /* 6141 6341 */ 99 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ 100 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ 101 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ 102 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */ 103 }; 104 105 /** 106 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level 107 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags 108 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that 109 * egressing FORWARD frames with an EDSA 110 * tag is reserved for future use, but 111 * empirical data shows that this mode 112 * is supported. 113 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported. 114 */ 115 enum mv88e6xxx_edsa_support { 116 MV88E6XXX_EDSA_UNSUPPORTED = 0, 117 MV88E6XXX_EDSA_UNDOCUMENTED, 118 MV88E6XXX_EDSA_SUPPORTED, 119 }; 120 121 struct mv88e6xxx_ops; 122 123 struct mv88e6xxx_info { 124 enum mv88e6xxx_family family; 125 u16 prod_num; 126 const char *name; 127 unsigned int num_databases; 128 unsigned int num_macs; 129 unsigned int num_ports; 130 unsigned int num_internal_phys; 131 unsigned int num_gpio; 132 unsigned int max_vid; 133 unsigned int port_base_addr; 134 unsigned int phy_base_addr; 135 unsigned int global1_addr; 136 unsigned int global2_addr; 137 unsigned int age_time_coeff; 138 unsigned int g1_irqs; 139 unsigned int g2_irqs; 140 bool pvt; 141 142 /* Mark certain ports as invalid. This is required for example for the 143 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the 144 * ports 2-4 are not routet to pins. 145 */ 146 unsigned int invalid_port_mask; 147 /* Multi-chip Addressing Mode. 148 * Some chips respond to only 2 registers of its own SMI device address 149 * when it is non-zero, and use indirect access to internal registers. 150 */ 151 bool multi_chip; 152 /* Dual-chip Addressing Mode 153 * Some chips respond to only half of the 32 SMI addresses, 154 * allowing two to coexist on the same SMI interface. 155 */ 156 bool dual_chip; 157 158 enum mv88e6xxx_edsa_support edsa_support; 159 160 /* Mask for FromPort and ToPort value of PortVec used in ATU Move 161 * operation. 0 means that the ATU Move operation is not supported. 162 */ 163 u8 atu_move_port_mask; 164 const struct mv88e6xxx_ops *ops; 165 166 /* Supports PTP */ 167 bool ptp_support; 168 }; 169 170 struct mv88e6xxx_atu_entry { 171 u8 state; 172 bool trunk; 173 u16 portvec; 174 u8 mac[ETH_ALEN]; 175 }; 176 177 struct mv88e6xxx_vtu_entry { 178 u16 vid; 179 u16 fid; 180 u8 sid; 181 bool valid; 182 bool policy; 183 u8 member[DSA_MAX_PORTS]; 184 u8 state[DSA_MAX_PORTS]; 185 }; 186 187 struct mv88e6xxx_bus_ops; 188 struct mv88e6xxx_irq_ops; 189 struct mv88e6xxx_gpio_ops; 190 struct mv88e6xxx_avb_ops; 191 struct mv88e6xxx_ptp_ops; 192 193 struct mv88e6xxx_irq { 194 u16 masked; 195 struct irq_chip chip; 196 struct irq_domain *domain; 197 int nirqs; 198 }; 199 200 /* state flags for mv88e6xxx_port_hwtstamp::state */ 201 enum { 202 MV88E6XXX_HWTSTAMP_ENABLED, 203 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS, 204 }; 205 206 struct mv88e6xxx_port_hwtstamp { 207 /* Port index */ 208 int port_id; 209 210 /* Timestamping state */ 211 unsigned long state; 212 213 /* Resources for receive timestamping */ 214 struct sk_buff_head rx_queue; 215 struct sk_buff_head rx_queue2; 216 217 /* Resources for transmit timestamping */ 218 unsigned long tx_tstamp_start; 219 struct sk_buff *tx_skb; 220 u16 tx_seq_id; 221 222 /* Current timestamp configuration */ 223 struct hwtstamp_config tstamp_config; 224 }; 225 226 enum mv88e6xxx_policy_mapping { 227 MV88E6XXX_POLICY_MAPPING_DA, 228 MV88E6XXX_POLICY_MAPPING_SA, 229 MV88E6XXX_POLICY_MAPPING_VTU, 230 MV88E6XXX_POLICY_MAPPING_ETYPE, 231 MV88E6XXX_POLICY_MAPPING_PPPOE, 232 MV88E6XXX_POLICY_MAPPING_VBAS, 233 MV88E6XXX_POLICY_MAPPING_OPT82, 234 MV88E6XXX_POLICY_MAPPING_UDP, 235 }; 236 237 enum mv88e6xxx_policy_action { 238 MV88E6XXX_POLICY_ACTION_NORMAL, 239 MV88E6XXX_POLICY_ACTION_MIRROR, 240 MV88E6XXX_POLICY_ACTION_TRAP, 241 MV88E6XXX_POLICY_ACTION_DISCARD, 242 }; 243 244 struct mv88e6xxx_policy { 245 enum mv88e6xxx_policy_mapping mapping; 246 enum mv88e6xxx_policy_action action; 247 struct ethtool_rx_flow_spec fs; 248 u8 addr[ETH_ALEN]; 249 int port; 250 u16 vid; 251 }; 252 253 struct mv88e6xxx_vlan { 254 u16 vid; 255 bool valid; 256 }; 257 258 struct mv88e6xxx_port { 259 struct mv88e6xxx_chip *chip; 260 int port; 261 struct mv88e6xxx_vlan bridge_pvid; 262 u64 serdes_stats[2]; 263 u64 atu_member_violation; 264 u64 atu_miss_violation; 265 u64 atu_full_violation; 266 u64 vtu_member_violation; 267 u64 vtu_miss_violation; 268 phy_interface_t interface; 269 u8 cmode; 270 bool mirror_ingress; 271 bool mirror_egress; 272 unsigned int serdes_irq; 273 char serdes_irq_name[64]; 274 struct devlink_region *region; 275 }; 276 277 enum mv88e6xxx_region_id { 278 MV88E6XXX_REGION_GLOBAL1 = 0, 279 MV88E6XXX_REGION_GLOBAL2, 280 MV88E6XXX_REGION_ATU, 281 MV88E6XXX_REGION_VTU, 282 MV88E6XXX_REGION_PVT, 283 284 _MV88E6XXX_REGION_MAX, 285 }; 286 287 struct mv88e6xxx_region_priv { 288 enum mv88e6xxx_region_id id; 289 }; 290 291 struct mv88e6xxx_chip { 292 const struct mv88e6xxx_info *info; 293 294 /* Currently configured tagging protocol */ 295 enum dsa_tag_protocol tag_protocol; 296 297 /* The dsa_switch this private structure is related to */ 298 struct dsa_switch *ds; 299 300 /* The device this structure is associated to */ 301 struct device *dev; 302 303 /* This mutex protects the access to the switch registers */ 304 struct mutex reg_lock; 305 306 /* The MII bus and the address on the bus that is used to 307 * communication with the switch 308 */ 309 const struct mv88e6xxx_bus_ops *smi_ops; 310 struct mii_bus *bus; 311 int sw_addr; 312 313 /* Handles automatic disabling and re-enabling of the PHY 314 * polling unit. 315 */ 316 const struct mv88e6xxx_bus_ops *phy_ops; 317 struct mutex ppu_mutex; 318 int ppu_disabled; 319 struct work_struct ppu_work; 320 struct timer_list ppu_timer; 321 322 /* This mutex serialises access to the statistics unit. 323 * Hold this mutex over snapshot + dump sequences. 324 */ 325 struct mutex stats_mutex; 326 327 /* A switch may have a GPIO line tied to its reset pin. Parse 328 * this from the device tree, and use it before performing 329 * switch soft reset. 330 */ 331 struct gpio_desc *reset; 332 333 /* set to size of eeprom if supported by the switch */ 334 u32 eeprom_len; 335 336 /* List of mdio busses */ 337 struct list_head mdios; 338 339 /* Policy Control List IDs and rules */ 340 struct idr policies; 341 342 /* There can be two interrupt controllers, which are chained 343 * off a GPIO as interrupt source 344 */ 345 struct mv88e6xxx_irq g1_irq; 346 struct mv88e6xxx_irq g2_irq; 347 int irq; 348 char irq_name[64]; 349 int device_irq; 350 char device_irq_name[64]; 351 int watchdog_irq; 352 char watchdog_irq_name[64]; 353 354 int atu_prob_irq; 355 char atu_prob_irq_name[64]; 356 int vtu_prob_irq; 357 char vtu_prob_irq_name[64]; 358 struct kthread_worker *kworker; 359 struct kthread_delayed_work irq_poll_work; 360 361 /* GPIO resources */ 362 u8 gpio_data[2]; 363 364 /* This cyclecounter abstracts the switch PTP time. 365 * reg_lock must be held for any operation that read()s. 366 */ 367 struct cyclecounter tstamp_cc; 368 struct timecounter tstamp_tc; 369 struct delayed_work overflow_work; 370 371 struct ptp_clock *ptp_clock; 372 struct ptp_clock_info ptp_clock_info; 373 struct delayed_work tai_event_work; 374 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO]; 375 u16 trig_config; 376 u16 evcap_config; 377 u16 enable_count; 378 379 /* Current ingress and egress monitor ports */ 380 int egress_dest_port; 381 int ingress_dest_port; 382 383 /* Per-port timestamping resources. */ 384 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS]; 385 386 /* Array of port structures. */ 387 struct mv88e6xxx_port ports[DSA_MAX_PORTS]; 388 389 /* devlink regions */ 390 struct devlink_region *regions[_MV88E6XXX_REGION_MAX]; 391 }; 392 393 struct mv88e6xxx_bus_ops { 394 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 395 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 396 int (*init)(struct mv88e6xxx_chip *chip); 397 }; 398 399 struct mv88e6xxx_mdio_bus { 400 struct mii_bus *bus; 401 struct mv88e6xxx_chip *chip; 402 struct list_head list; 403 bool external; 404 }; 405 406 struct mv88e6xxx_ops { 407 /* Switch Setup Errata, called early in the switch setup to 408 * allow any errata actions to be performed 409 */ 410 int (*setup_errata)(struct mv88e6xxx_chip *chip); 411 412 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip); 413 int (*ip_pri_map)(struct mv88e6xxx_chip *chip); 414 415 /* Ingress Rate Limit unit (IRL) operations */ 416 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port); 417 418 int (*get_eeprom)(struct mv88e6xxx_chip *chip, 419 struct ethtool_eeprom *eeprom, u8 *data); 420 int (*set_eeprom)(struct mv88e6xxx_chip *chip, 421 struct ethtool_eeprom *eeprom, u8 *data); 422 423 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); 424 425 int (*phy_read)(struct mv88e6xxx_chip *chip, 426 struct mii_bus *bus, 427 int addr, int reg, u16 *val); 428 int (*phy_write)(struct mv88e6xxx_chip *chip, 429 struct mii_bus *bus, 430 int addr, int reg, u16 val); 431 432 /* Priority Override Table operations */ 433 int (*pot_clear)(struct mv88e6xxx_chip *chip); 434 435 /* PHY Polling Unit (PPU) operations */ 436 int (*ppu_enable)(struct mv88e6xxx_chip *chip); 437 int (*ppu_disable)(struct mv88e6xxx_chip *chip); 438 439 /* Switch Software Reset */ 440 int (*reset)(struct mv88e6xxx_chip *chip); 441 442 /* RGMII Receive/Transmit Timing Control 443 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. 444 */ 445 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, 446 phy_interface_t mode); 447 448 #define LINK_FORCED_DOWN 0 449 #define LINK_FORCED_UP 1 450 #define LINK_UNFORCED -2 451 452 /* Port's MAC link state 453 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, 454 * or LINK_UNFORCED for normal link detection. 455 */ 456 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); 457 458 /* Synchronise the port link state with that of the SERDES 459 */ 460 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 461 462 #define PAUSE_ON 1 463 #define PAUSE_OFF 0 464 465 /* Enable/disable sending Pause */ 466 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port, 467 int pause); 468 469 #define SPEED_MAX INT_MAX 470 #define SPEED_UNFORCED -2 471 #define DUPLEX_UNFORCED -2 472 473 /* Port's MAC speed (in Mbps) and MAC duplex mode 474 * 475 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. 476 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. 477 * 478 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, 479 * or DUPLEX_UNFORCED for normal duplex detection. 480 */ 481 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port, 482 int speed, int duplex); 483 484 /* What interface mode should be used for maximum speed? */ 485 phy_interface_t (*port_max_speed_mode)(int port); 486 487 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); 488 489 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port, 490 enum mv88e6xxx_policy_mapping mapping, 491 enum mv88e6xxx_policy_action action); 492 493 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, 494 enum mv88e6xxx_frame_mode mode); 495 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port, 496 bool unicast); 497 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port, 498 bool multicast); 499 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, 500 u16 etype); 501 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, 502 size_t size); 503 504 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); 505 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, 506 u8 out); 507 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); 508 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port); 509 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port); 510 511 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. 512 * Some chips allow this to be configured on specific ports. 513 */ 514 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, 515 phy_interface_t mode); 516 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 517 518 /* Some devices have a per port register indicating what is 519 * the upstream port this port should forward to. 520 */ 521 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, 522 int upstream_port); 523 524 /* Snapshot the statistics for a port. The statistics can then 525 * be read back a leisure but still with a consistent view. 526 */ 527 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); 528 529 /* Set the histogram mode for statistics, when the control registers 530 * are separated out of the STATS_OP register. 531 */ 532 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); 533 534 /* Return the number of strings describing statistics */ 535 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); 536 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); 537 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, 538 uint64_t *data); 539 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port); 540 int (*set_egress_port)(struct mv88e6xxx_chip *chip, 541 enum mv88e6xxx_egress_direction direction, 542 int port); 543 544 #define MV88E6XXX_CASCADE_PORT_NONE 0xe 545 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf 546 547 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port); 548 549 const struct mv88e6xxx_irq_ops *watchdog_ops; 550 551 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); 552 553 /* Power on/off a SERDES interface */ 554 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane, 555 bool up); 556 557 /* SERDES lane mapping */ 558 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port); 559 560 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port, 561 int lane, struct phylink_link_state *state); 562 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port, 563 int lane, unsigned int mode, 564 phy_interface_t interface, 565 const unsigned long *advertise); 566 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port, 567 int lane); 568 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port, 569 int lane, int speed, int duplex); 570 571 /* SERDES interrupt handling */ 572 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip, 573 int port); 574 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane, 575 bool enable); 576 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port, 577 int lane); 578 579 /* Statistics from the SERDES interface */ 580 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port); 581 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port, 582 uint8_t *data); 583 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port, 584 uint64_t *data); 585 586 /* SERDES registers for ethtool */ 587 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port); 588 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port, 589 void *_p); 590 591 /* SERDES SGMII/Fiber Output Amplitude */ 592 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port, 593 int val); 594 595 /* Address Translation Unit operations */ 596 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash); 597 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash); 598 599 /* VLAN Translation Unit operations */ 600 int (*vtu_getnext)(struct mv88e6xxx_chip *chip, 601 struct mv88e6xxx_vtu_entry *entry); 602 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip, 603 struct mv88e6xxx_vtu_entry *entry); 604 605 /* GPIO operations */ 606 const struct mv88e6xxx_gpio_ops *gpio_ops; 607 608 /* Interface to the AVB/PTP registers */ 609 const struct mv88e6xxx_avb_ops *avb_ops; 610 611 /* Remote Management Unit operations */ 612 int (*rmu_disable)(struct mv88e6xxx_chip *chip); 613 614 /* Precision Time Protocol operations */ 615 const struct mv88e6xxx_ptp_ops *ptp_ops; 616 617 /* Phylink */ 618 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port, 619 struct phylink_config *config); 620 621 /* Max Frame Size */ 622 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); 623 }; 624 625 struct mv88e6xxx_irq_ops { 626 /* Action to be performed when the interrupt happens */ 627 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); 628 /* Setup the hardware to generate the interrupt */ 629 int (*irq_setup)(struct mv88e6xxx_chip *chip); 630 /* Reset the hardware to stop generating the interrupt */ 631 void (*irq_free)(struct mv88e6xxx_chip *chip); 632 }; 633 634 struct mv88e6xxx_gpio_ops { 635 /* Get/set data on GPIO pin */ 636 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin); 637 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin, 638 int value); 639 640 /* get/set GPIO direction */ 641 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin); 642 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin, 643 bool input); 644 645 /* get/set GPIO pin control */ 646 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 647 int *func); 648 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin, 649 int func); 650 }; 651 652 struct mv88e6xxx_avb_ops { 653 /* Access port-scoped Precision Time Protocol registers */ 654 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr, 655 u16 *data, int len); 656 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr, 657 u16 data); 658 659 /* Access global Precision Time Protocol registers */ 660 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 661 int len); 662 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 663 664 /* Access global Time Application Interface registers */ 665 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data, 666 int len); 667 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data); 668 }; 669 670 struct mv88e6xxx_ptp_ops { 671 u64 (*clock_read)(const struct cyclecounter *cc); 672 int (*ptp_enable)(struct ptp_clock_info *ptp, 673 struct ptp_clock_request *rq, int on); 674 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin, 675 enum ptp_pin_function func, unsigned int chan); 676 void (*event_work)(struct work_struct *ugly); 677 int (*port_enable)(struct mv88e6xxx_chip *chip, int port); 678 int (*port_disable)(struct mv88e6xxx_chip *chip, int port); 679 int (*global_enable)(struct mv88e6xxx_chip *chip); 680 int (*global_disable)(struct mv88e6xxx_chip *chip); 681 int n_ext_ts; 682 int arr0_sts_reg; 683 int arr1_sts_reg; 684 int dep_sts_reg; 685 u32 rx_filters; 686 u32 cc_shift; 687 u32 cc_mult; 688 u32 cc_mult_num; 689 u32 cc_mult_dem; 690 }; 691 692 #define STATS_TYPE_PORT BIT(0) 693 #define STATS_TYPE_BANK0 BIT(1) 694 #define STATS_TYPE_BANK1 BIT(2) 695 696 struct mv88e6xxx_hw_stat { 697 char string[ETH_GSTRING_LEN]; 698 size_t size; 699 int reg; 700 int type; 701 }; 702 703 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip) 704 { 705 return chip->info->pvt; 706 } 707 708 static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip) 709 { 710 return !!chip->info->global2_addr; 711 } 712 713 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) 714 { 715 return chip->info->num_databases; 716 } 717 718 static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip) 719 { 720 return chip->info->num_macs; 721 } 722 723 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) 724 { 725 return chip->info->num_ports; 726 } 727 728 static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip) 729 { 730 return chip->info->max_vid; 731 } 732 733 static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) 734 { 735 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0); 736 } 737 738 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip) 739 { 740 return chip->info->num_gpio; 741 } 742 743 static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port) 744 { 745 return (chip->info->invalid_port_mask & BIT(port)) != 0; 746 } 747 748 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); 749 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); 750 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 751 u16 mask, u16 val); 752 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 753 int bit, int val); 754 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip); 755 756 static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip) 757 { 758 mutex_lock(&chip->reg_lock); 759 } 760 761 static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip) 762 { 763 mutex_unlock(&chip->reg_lock); 764 } 765 766 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap); 767 768 #endif /* _MV88E6XXX_CHIP_H */ 769