1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_add_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t **data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i; 1161 1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) 1165 ethtool_puts(data, stat->string); 1166 } 1167 } 1168 1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t **data) 1171 { 1172 mv88e6xxx_stats_get_strings(chip, data, 1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1174 } 1175 1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1177 uint8_t **data) 1178 { 1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1180 } 1181 1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1183 uint8_t **data) 1184 { 1185 mv88e6xxx_stats_get_strings(chip, data, 1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1187 } 1188 1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1190 "atu_member_violation", 1191 "atu_miss_violation", 1192 "atu_full_violation", 1193 "vtu_member_violation", 1194 "vtu_miss_violation", 1195 }; 1196 1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1203 } 1204 1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1206 u32 stringset, uint8_t *data) 1207 { 1208 struct mv88e6xxx_chip *chip = ds->priv; 1209 1210 if (stringset != ETH_SS_STATS) 1211 return; 1212 1213 mv88e6xxx_reg_lock(chip); 1214 1215 if (chip->info->ops->stats_get_strings) 1216 chip->info->ops->stats_get_strings(chip, &data); 1217 1218 if (chip->info->ops->serdes_get_strings) 1219 chip->info->ops->serdes_get_strings(chip, port, &data); 1220 1221 mv88e6xxx_atu_vtu_get_strings(&data); 1222 1223 mv88e6xxx_reg_unlock(chip); 1224 } 1225 1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1227 int types) 1228 { 1229 const struct mv88e6xxx_hw_stat *stat; 1230 int i, j; 1231 1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1233 stat = &mv88e6xxx_hw_stats[i]; 1234 if (stat->type & types) 1235 j++; 1236 } 1237 return j; 1238 } 1239 1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1241 { 1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1243 STATS_TYPE_PORT); 1244 } 1245 1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1247 { 1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1249 } 1250 1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_BANK1); 1255 } 1256 1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1258 { 1259 struct mv88e6xxx_chip *chip = ds->priv; 1260 int serdes_count = 0; 1261 int count = 0; 1262 1263 if (sset != ETH_SS_STATS) 1264 return 0; 1265 1266 mv88e6xxx_reg_lock(chip); 1267 if (chip->info->ops->stats_get_sset_count) 1268 count = chip->info->ops->stats_get_sset_count(chip); 1269 if (count < 0) 1270 goto out; 1271 1272 if (chip->info->ops->serdes_get_sset_count) 1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1274 port); 1275 if (serdes_count < 0) { 1276 count = serdes_count; 1277 goto out; 1278 } 1279 count += serdes_count; 1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1281 1282 out: 1283 mv88e6xxx_reg_unlock(chip); 1284 1285 return count; 1286 } 1287 1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1289 const struct mv88e6xxx_hw_stat *stat, 1290 uint64_t *data) 1291 { 1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1293 MV88E6XXX_G1_STATS_OP_HIST_RX); 1294 return 1; 1295 } 1296 1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1298 const struct mv88e6xxx_hw_stat *stat, 1299 uint64_t *data) 1300 { 1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1302 MV88E6XXX_G1_STATS_OP_HIST_RX); 1303 return 1; 1304 } 1305 1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1307 const struct mv88e6xxx_hw_stat *stat, 1308 uint64_t *data) 1309 { 1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1312 MV88E6XXX_G1_STATS_OP_HIST_RX); 1313 return 1; 1314 } 1315 1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1317 const struct mv88e6xxx_hw_stat *stat, 1318 uint64_t *data) 1319 { 1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1322 0); 1323 return 1; 1324 } 1325 1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1327 const struct mv88e6xxx_hw_stat *stat, 1328 uint64_t *data) 1329 { 1330 int ret = 0; 1331 1332 if (!(stat->type & chip->info->stats_type)) 1333 return 0; 1334 1335 if (chip->info->ops->stats_get_stat) { 1336 mv88e6xxx_reg_lock(chip); 1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 return ret; 1342 } 1343 1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1345 uint64_t *data) 1346 { 1347 const struct mv88e6xxx_hw_stat *stat; 1348 size_t i, j; 1349 1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1351 stat = &mv88e6xxx_hw_stats[i]; 1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1353 } 1354 return j; 1355 } 1356 1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1358 uint64_t *data) 1359 { 1360 *data++ = chip->ports[port].atu_member_violation; 1361 *data++ = chip->ports[port].atu_miss_violation; 1362 *data++ = chip->ports[port].atu_full_violation; 1363 *data++ = chip->ports[port].vtu_member_violation; 1364 *data++ = chip->ports[port].vtu_miss_violation; 1365 } 1366 1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1368 uint64_t *data) 1369 { 1370 size_t count; 1371 1372 count = mv88e6xxx_stats_get_stats(chip, port, data); 1373 1374 mv88e6xxx_reg_lock(chip); 1375 if (chip->info->ops->serdes_get_stats) { 1376 data += count; 1377 count = chip->info->ops->serdes_get_stats(chip, port, data); 1378 } 1379 data += count; 1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1381 mv88e6xxx_reg_unlock(chip); 1382 } 1383 1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1385 uint64_t *data) 1386 { 1387 struct mv88e6xxx_chip *chip = ds->priv; 1388 int ret; 1389 1390 ret = mv88e6xxx_stats_snapshot(chip, port); 1391 if (ret < 0) 1392 return; 1393 1394 mv88e6xxx_get_stats(chip, port, data); 1395 } 1396 1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1398 struct ethtool_eth_mac_stats *mac_stats) 1399 { 1400 struct mv88e6xxx_chip *chip = ds->priv; 1401 int ret; 1402 1403 ret = mv88e6xxx_stats_snapshot(chip, port); 1404 if (ret < 0) 1405 return; 1406 1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1408 mv88e6xxx_stats_get_stat(chip, port, \ 1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1410 &mac_stats->stats._member) 1411 1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1426 1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1428 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1433 } 1434 1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1436 struct ethtool_rmon_stats *rmon_stats, 1437 const struct ethtool_rmon_hist_range **ranges) 1438 { 1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1440 { 64, 64 }, 1441 { 65, 127 }, 1442 { 128, 255 }, 1443 { 256, 511 }, 1444 { 512, 1023 }, 1445 { 1024, 65535 }, 1446 {} 1447 }; 1448 struct mv88e6xxx_chip *chip = ds->priv; 1449 int ret; 1450 1451 ret = mv88e6xxx_stats_snapshot(chip, port); 1452 if (ret < 0) 1453 return; 1454 1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1456 mv88e6xxx_stats_get_stat(chip, port, \ 1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1458 &rmon_stats->stats._member) 1459 1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1470 1471 #undef MV88E6XXX_RMON_STAT_MAP 1472 1473 *ranges = rmon_ranges; 1474 } 1475 1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int len; 1480 1481 len = 32 * sizeof(u16); 1482 if (chip->info->ops->serdes_get_regs_len) 1483 len += chip->info->ops->serdes_get_regs_len(chip, port); 1484 1485 return len; 1486 } 1487 1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1489 struct ethtool_regs *regs, void *_p) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 int err; 1493 u16 reg; 1494 u16 *p = _p; 1495 int i; 1496 1497 regs->version = chip->info->prod_num; 1498 1499 memset(p, 0xff, 32 * sizeof(u16)); 1500 1501 mv88e6xxx_reg_lock(chip); 1502 1503 for (i = 0; i < 32; i++) { 1504 1505 err = mv88e6xxx_port_read(chip, port, i, ®); 1506 if (!err) 1507 p[i] = reg; 1508 } 1509 1510 if (chip->info->ops->serdes_get_regs) 1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1512 1513 mv88e6xxx_reg_unlock(chip); 1514 } 1515 1516 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1517 struct ethtool_keee *e) 1518 { 1519 /* Nothing to do on the port's MAC */ 1520 return 0; 1521 } 1522 1523 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1524 struct ethtool_keee *e) 1525 { 1526 /* Nothing to do on the port's MAC */ 1527 return 0; 1528 } 1529 1530 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1531 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1532 { 1533 struct dsa_switch *ds = chip->ds; 1534 struct dsa_switch_tree *dst = ds->dst; 1535 struct dsa_port *dp, *other_dp; 1536 bool found = false; 1537 u16 pvlan; 1538 1539 /* dev is a physical switch */ 1540 if (dev <= dst->last_switch) { 1541 list_for_each_entry(dp, &dst->ports, list) { 1542 if (dp->ds->index == dev && dp->index == port) { 1543 /* dp might be a DSA link or a user port, so it 1544 * might or might not have a bridge. 1545 * Use the "found" variable for both cases. 1546 */ 1547 found = true; 1548 break; 1549 } 1550 } 1551 /* dev is a virtual bridge */ 1552 } else { 1553 list_for_each_entry(dp, &dst->ports, list) { 1554 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1555 1556 if (!bridge_num) 1557 continue; 1558 1559 if (bridge_num + dst->last_switch != dev) 1560 continue; 1561 1562 found = true; 1563 break; 1564 } 1565 } 1566 1567 /* Prevent frames from unknown switch or virtual bridge */ 1568 if (!found) 1569 return 0; 1570 1571 /* Frames from DSA links and CPU ports can egress any local port */ 1572 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1573 return mv88e6xxx_port_mask(chip); 1574 1575 pvlan = 0; 1576 1577 /* Frames from standalone user ports can only egress on the 1578 * upstream port. 1579 */ 1580 if (!dsa_port_bridge_dev_get(dp)) 1581 return BIT(dsa_switch_upstream_port(ds)); 1582 1583 /* Frames from bridged user ports can egress any local DSA 1584 * links and CPU ports, as well as any local member of their 1585 * bridge group. 1586 */ 1587 dsa_switch_for_each_port(other_dp, ds) 1588 if (other_dp->type == DSA_PORT_TYPE_CPU || 1589 other_dp->type == DSA_PORT_TYPE_DSA || 1590 dsa_port_bridge_same(dp, other_dp)) 1591 pvlan |= BIT(other_dp->index); 1592 1593 return pvlan; 1594 } 1595 1596 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1597 { 1598 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1599 1600 /* prevent frames from going back out of the port they came in on */ 1601 output_ports &= ~BIT(port); 1602 1603 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1604 } 1605 1606 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1607 u8 state) 1608 { 1609 struct mv88e6xxx_chip *chip = ds->priv; 1610 int err; 1611 1612 mv88e6xxx_reg_lock(chip); 1613 err = mv88e6xxx_port_set_state(chip, port, state); 1614 mv88e6xxx_reg_unlock(chip); 1615 1616 if (err) 1617 dev_err(ds->dev, "p%d: failed to update state\n", port); 1618 } 1619 1620 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1621 { 1622 int err; 1623 1624 if (chip->info->ops->ieee_pri_map) { 1625 err = chip->info->ops->ieee_pri_map(chip); 1626 if (err) 1627 return err; 1628 } 1629 1630 if (chip->info->ops->ip_pri_map) { 1631 err = chip->info->ops->ip_pri_map(chip); 1632 if (err) 1633 return err; 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1640 { 1641 struct dsa_switch *ds = chip->ds; 1642 int target, port; 1643 int err; 1644 1645 if (!chip->info->global2_addr) 1646 return 0; 1647 1648 /* Initialize the routing port to the 32 possible target devices */ 1649 for (target = 0; target < 32; target++) { 1650 port = dsa_routing_port(ds, target); 1651 if (port == ds->num_ports) 1652 port = 0x1f; 1653 1654 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1655 if (err) 1656 return err; 1657 } 1658 1659 if (chip->info->ops->set_cascade_port) { 1660 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1661 err = chip->info->ops->set_cascade_port(chip, port); 1662 if (err) 1663 return err; 1664 } 1665 1666 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1667 if (err) 1668 return err; 1669 1670 return 0; 1671 } 1672 1673 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1674 { 1675 /* Clear all trunk masks and mapping */ 1676 if (chip->info->global2_addr) 1677 return mv88e6xxx_g2_trunk_clear(chip); 1678 1679 return 0; 1680 } 1681 1682 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1683 { 1684 if (chip->info->ops->rmu_disable) 1685 return chip->info->ops->rmu_disable(chip); 1686 1687 return 0; 1688 } 1689 1690 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1691 { 1692 if (chip->info->ops->pot_clear) 1693 return chip->info->ops->pot_clear(chip); 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1699 { 1700 if (chip->info->ops->mgmt_rsvd2cpu) 1701 return chip->info->ops->mgmt_rsvd2cpu(chip); 1702 1703 return 0; 1704 } 1705 1706 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1707 { 1708 int err; 1709 1710 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1711 if (err) 1712 return err; 1713 1714 /* The chips that have a "learn2all" bit in Global1, ATU 1715 * Control are precisely those whose port registers have a 1716 * Message Port bit in Port Control 1 and hence implement 1717 * ->port_setup_message_port. 1718 */ 1719 if (chip->info->ops->port_setup_message_port) { 1720 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1721 if (err) 1722 return err; 1723 } 1724 1725 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1726 } 1727 1728 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1729 { 1730 int port; 1731 int err; 1732 1733 if (!chip->info->ops->irl_init_all) 1734 return 0; 1735 1736 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1737 /* Disable ingress rate limiting by resetting all per port 1738 * ingress rate limit resources to their initial state. 1739 */ 1740 err = chip->info->ops->irl_init_all(chip, port); 1741 if (err) 1742 return err; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1749 { 1750 if (chip->info->ops->set_switch_mac) { 1751 u8 addr[ETH_ALEN]; 1752 1753 eth_random_addr(addr); 1754 1755 return chip->info->ops->set_switch_mac(chip, addr); 1756 } 1757 1758 return 0; 1759 } 1760 1761 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1762 { 1763 struct dsa_switch_tree *dst = chip->ds->dst; 1764 struct dsa_switch *ds; 1765 struct dsa_port *dp; 1766 u16 pvlan = 0; 1767 1768 if (!mv88e6xxx_has_pvt(chip)) 1769 return 0; 1770 1771 /* Skip the local source device, which uses in-chip port VLAN */ 1772 if (dev != chip->ds->index) { 1773 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1774 1775 ds = dsa_switch_find(dst->index, dev); 1776 dp = ds ? dsa_to_port(ds, port) : NULL; 1777 if (dp && dp->lag) { 1778 /* As the PVT is used to limit flooding of 1779 * FORWARD frames, which use the LAG ID as the 1780 * source port, we must translate dev/port to 1781 * the special "LAG device" in the PVT, using 1782 * the LAG ID (one-based) as the port number 1783 * (zero-based). 1784 */ 1785 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1786 port = dsa_port_lag_id_get(dp) - 1; 1787 } 1788 } 1789 1790 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1791 } 1792 1793 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1794 { 1795 int dev, port; 1796 int err; 1797 1798 if (!mv88e6xxx_has_pvt(chip)) 1799 return 0; 1800 1801 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1802 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1803 */ 1804 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1805 if (err) 1806 return err; 1807 1808 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1809 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1810 err = mv88e6xxx_pvt_map(chip, dev, port); 1811 if (err) 1812 return err; 1813 } 1814 } 1815 1816 return 0; 1817 } 1818 1819 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1820 u16 fid) 1821 { 1822 if (dsa_to_port(chip->ds, port)->lag) 1823 /* Hardware is incapable of fast-aging a LAG through a 1824 * regular ATU move operation. Until we have something 1825 * more fancy in place this is a no-op. 1826 */ 1827 return -EOPNOTSUPP; 1828 1829 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1830 } 1831 1832 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1833 { 1834 struct mv88e6xxx_chip *chip = ds->priv; 1835 int err; 1836 1837 mv88e6xxx_reg_lock(chip); 1838 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1839 mv88e6xxx_reg_unlock(chip); 1840 1841 if (err) 1842 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1843 port, err); 1844 } 1845 1846 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1847 { 1848 if (!mv88e6xxx_max_vid(chip)) 1849 return 0; 1850 1851 return mv88e6xxx_g1_vtu_flush(chip); 1852 } 1853 1854 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1855 struct mv88e6xxx_vtu_entry *entry) 1856 { 1857 int err; 1858 1859 if (!chip->info->ops->vtu_getnext) 1860 return -EOPNOTSUPP; 1861 1862 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1863 entry->valid = false; 1864 1865 err = chip->info->ops->vtu_getnext(chip, entry); 1866 1867 if (entry->vid != vid) 1868 entry->valid = false; 1869 1870 return err; 1871 } 1872 1873 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1874 int (*cb)(struct mv88e6xxx_chip *chip, 1875 const struct mv88e6xxx_vtu_entry *entry, 1876 void *priv), 1877 void *priv) 1878 { 1879 struct mv88e6xxx_vtu_entry entry = { 1880 .vid = mv88e6xxx_max_vid(chip), 1881 .valid = false, 1882 }; 1883 int err; 1884 1885 if (!chip->info->ops->vtu_getnext) 1886 return -EOPNOTSUPP; 1887 1888 do { 1889 err = chip->info->ops->vtu_getnext(chip, &entry); 1890 if (err) 1891 return err; 1892 1893 if (!entry.valid) 1894 break; 1895 1896 err = cb(chip, &entry, priv); 1897 if (err) 1898 return err; 1899 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1900 1901 return 0; 1902 } 1903 1904 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1905 struct mv88e6xxx_vtu_entry *entry) 1906 { 1907 if (!chip->info->ops->vtu_loadpurge) 1908 return -EOPNOTSUPP; 1909 1910 return chip->info->ops->vtu_loadpurge(chip, entry); 1911 } 1912 1913 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1914 { 1915 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1916 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1917 return -ENOSPC; 1918 1919 /* Clear the database */ 1920 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1921 } 1922 1923 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1924 struct mv88e6xxx_stu_entry *entry) 1925 { 1926 if (!chip->info->ops->stu_loadpurge) 1927 return -EOPNOTSUPP; 1928 1929 return chip->info->ops->stu_loadpurge(chip, entry); 1930 } 1931 1932 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1933 { 1934 struct mv88e6xxx_stu_entry stu = { 1935 .valid = true, 1936 .sid = 0 1937 }; 1938 1939 if (!mv88e6xxx_has_stu(chip)) 1940 return 0; 1941 1942 /* Make sure that SID 0 is always valid. This is used by VTU 1943 * entries that do not make use of the STU, e.g. when creating 1944 * a VLAN upper on a port that is also part of a VLAN 1945 * filtering bridge. 1946 */ 1947 return mv88e6xxx_stu_loadpurge(chip, &stu); 1948 } 1949 1950 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1951 { 1952 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1953 struct mv88e6xxx_mst *mst; 1954 1955 __set_bit(0, busy); 1956 1957 list_for_each_entry(mst, &chip->msts, node) 1958 __set_bit(mst->stu.sid, busy); 1959 1960 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1961 1962 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1963 } 1964 1965 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1966 { 1967 struct mv88e6xxx_mst *mst, *tmp; 1968 int err; 1969 1970 if (!sid) 1971 return 0; 1972 1973 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1974 if (mst->stu.sid != sid) 1975 continue; 1976 1977 if (!refcount_dec_and_test(&mst->refcnt)) 1978 return 0; 1979 1980 mst->stu.valid = false; 1981 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1982 if (err) { 1983 refcount_set(&mst->refcnt, 1); 1984 return err; 1985 } 1986 1987 list_del(&mst->node); 1988 kfree(mst); 1989 return 0; 1990 } 1991 1992 return -ENOENT; 1993 } 1994 1995 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1996 u16 msti, u8 *sid) 1997 { 1998 struct mv88e6xxx_mst *mst; 1999 int err, i; 2000 2001 if (!mv88e6xxx_has_stu(chip)) { 2002 err = -EOPNOTSUPP; 2003 goto err; 2004 } 2005 2006 if (!msti) { 2007 *sid = 0; 2008 return 0; 2009 } 2010 2011 list_for_each_entry(mst, &chip->msts, node) { 2012 if (mst->br == br && mst->msti == msti) { 2013 refcount_inc(&mst->refcnt); 2014 *sid = mst->stu.sid; 2015 return 0; 2016 } 2017 } 2018 2019 err = mv88e6xxx_sid_get(chip, sid); 2020 if (err) 2021 goto err; 2022 2023 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2024 if (!mst) { 2025 err = -ENOMEM; 2026 goto err; 2027 } 2028 2029 INIT_LIST_HEAD(&mst->node); 2030 refcount_set(&mst->refcnt, 1); 2031 mst->br = br; 2032 mst->msti = msti; 2033 mst->stu.valid = true; 2034 mst->stu.sid = *sid; 2035 2036 /* The bridge starts out all ports in the disabled state. But 2037 * a STU state of disabled means to go by the port-global 2038 * state. So we set all user port's initial state to blocking, 2039 * to match the bridge's behavior. 2040 */ 2041 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2042 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2043 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2044 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2045 2046 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2047 if (err) 2048 goto err_free; 2049 2050 list_add_tail(&mst->node, &chip->msts); 2051 return 0; 2052 2053 err_free: 2054 kfree(mst); 2055 err: 2056 return err; 2057 } 2058 2059 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2060 const struct switchdev_mst_state *st) 2061 { 2062 struct dsa_port *dp = dsa_to_port(ds, port); 2063 struct mv88e6xxx_chip *chip = ds->priv; 2064 struct mv88e6xxx_mst *mst; 2065 u8 state; 2066 int err; 2067 2068 if (!mv88e6xxx_has_stu(chip)) 2069 return -EOPNOTSUPP; 2070 2071 switch (st->state) { 2072 case BR_STATE_DISABLED: 2073 case BR_STATE_BLOCKING: 2074 case BR_STATE_LISTENING: 2075 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2076 break; 2077 case BR_STATE_LEARNING: 2078 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2079 break; 2080 case BR_STATE_FORWARDING: 2081 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2082 break; 2083 default: 2084 return -EINVAL; 2085 } 2086 2087 list_for_each_entry(mst, &chip->msts, node) { 2088 if (mst->br == dsa_port_bridge_dev_get(dp) && 2089 mst->msti == st->msti) { 2090 if (mst->stu.state[port] == state) 2091 return 0; 2092 2093 mst->stu.state[port] = state; 2094 mv88e6xxx_reg_lock(chip); 2095 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2096 mv88e6xxx_reg_unlock(chip); 2097 return err; 2098 } 2099 } 2100 2101 return -ENOENT; 2102 } 2103 2104 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2105 u16 vid) 2106 { 2107 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2108 struct mv88e6xxx_chip *chip = ds->priv; 2109 struct mv88e6xxx_vtu_entry vlan; 2110 int err; 2111 2112 /* DSA and CPU ports have to be members of multiple vlans */ 2113 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2114 return 0; 2115 2116 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2117 if (err) 2118 return err; 2119 2120 if (!vlan.valid) 2121 return 0; 2122 2123 dsa_switch_for_each_user_port(other_dp, ds) { 2124 struct net_device *other_br; 2125 2126 if (vlan.member[other_dp->index] == 2127 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2128 continue; 2129 2130 if (dsa_port_bridge_same(dp, other_dp)) 2131 break; /* same bridge, check next VLAN */ 2132 2133 other_br = dsa_port_bridge_dev_get(other_dp); 2134 if (!other_br) 2135 continue; 2136 2137 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2138 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2139 return -EOPNOTSUPP; 2140 } 2141 2142 return 0; 2143 } 2144 2145 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2146 { 2147 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2148 struct net_device *br = dsa_port_bridge_dev_get(dp); 2149 struct mv88e6xxx_port *p = &chip->ports[port]; 2150 u16 pvid = MV88E6XXX_VID_STANDALONE; 2151 bool drop_untagged = false; 2152 int err; 2153 2154 if (br) { 2155 if (br_vlan_enabled(br)) { 2156 pvid = p->bridge_pvid.vid; 2157 drop_untagged = !p->bridge_pvid.valid; 2158 } else { 2159 pvid = MV88E6XXX_VID_BRIDGED; 2160 } 2161 } 2162 2163 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2164 if (err) 2165 return err; 2166 2167 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2168 } 2169 2170 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2171 bool vlan_filtering, 2172 struct netlink_ext_ack *extack) 2173 { 2174 struct mv88e6xxx_chip *chip = ds->priv; 2175 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2176 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2177 int err; 2178 2179 if (!mv88e6xxx_max_vid(chip)) 2180 return -EOPNOTSUPP; 2181 2182 mv88e6xxx_reg_lock(chip); 2183 2184 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2185 if (err) 2186 goto unlock; 2187 2188 err = mv88e6xxx_port_commit_pvid(chip, port); 2189 if (err) 2190 goto unlock; 2191 2192 unlock: 2193 mv88e6xxx_reg_unlock(chip); 2194 2195 return err; 2196 } 2197 2198 static int 2199 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2200 const struct switchdev_obj_port_vlan *vlan) 2201 { 2202 struct mv88e6xxx_chip *chip = ds->priv; 2203 int err; 2204 2205 if (!mv88e6xxx_max_vid(chip)) 2206 return -EOPNOTSUPP; 2207 2208 /* If the requested port doesn't belong to the same bridge as the VLAN 2209 * members, do not support it (yet) and fallback to software VLAN. 2210 */ 2211 mv88e6xxx_reg_lock(chip); 2212 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2213 mv88e6xxx_reg_unlock(chip); 2214 2215 return err; 2216 } 2217 2218 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2219 const unsigned char *addr, u16 vid, 2220 u8 state) 2221 { 2222 struct mv88e6xxx_atu_entry entry; 2223 struct mv88e6xxx_vtu_entry vlan; 2224 u16 fid; 2225 int err; 2226 2227 /* Ports have two private address databases: one for when the port is 2228 * standalone and one for when the port is under a bridge and the 2229 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2230 * address database to remain 100% empty, so we never load an ATU entry 2231 * into a standalone port's database. Therefore, translate the null 2232 * VLAN ID into the port's database used for VLAN-unaware bridging. 2233 */ 2234 if (vid == 0) { 2235 fid = MV88E6XXX_FID_BRIDGED; 2236 } else { 2237 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2238 if (err) 2239 return err; 2240 2241 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2242 if (!vlan.valid) 2243 return -EOPNOTSUPP; 2244 2245 fid = vlan.fid; 2246 } 2247 2248 entry.state = 0; 2249 ether_addr_copy(entry.mac, addr); 2250 eth_addr_dec(entry.mac); 2251 2252 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2253 if (err) 2254 return err; 2255 2256 /* Initialize a fresh ATU entry if it isn't found */ 2257 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2258 memset(&entry, 0, sizeof(entry)); 2259 ether_addr_copy(entry.mac, addr); 2260 } 2261 2262 /* Purge the ATU entry only if no port is using it anymore */ 2263 if (!state) { 2264 entry.portvec &= ~BIT(port); 2265 if (!entry.portvec) 2266 entry.state = 0; 2267 } else { 2268 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2269 entry.portvec = BIT(port); 2270 else 2271 entry.portvec |= BIT(port); 2272 2273 entry.state = state; 2274 } 2275 2276 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2277 } 2278 2279 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2280 const struct mv88e6xxx_policy *policy) 2281 { 2282 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2283 enum mv88e6xxx_policy_action action = policy->action; 2284 const u8 *addr = policy->addr; 2285 u16 vid = policy->vid; 2286 u8 state; 2287 int err; 2288 int id; 2289 2290 if (!chip->info->ops->port_set_policy) 2291 return -EOPNOTSUPP; 2292 2293 switch (mapping) { 2294 case MV88E6XXX_POLICY_MAPPING_DA: 2295 case MV88E6XXX_POLICY_MAPPING_SA: 2296 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2297 state = 0; /* Dissociate the port and address */ 2298 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2299 is_multicast_ether_addr(addr)) 2300 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2301 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2302 is_unicast_ether_addr(addr)) 2303 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2304 else 2305 return -EOPNOTSUPP; 2306 2307 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2308 state); 2309 if (err) 2310 return err; 2311 break; 2312 default: 2313 return -EOPNOTSUPP; 2314 } 2315 2316 /* Skip the port's policy clearing if the mapping is still in use */ 2317 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2318 idr_for_each_entry(&chip->policies, policy, id) 2319 if (policy->port == port && 2320 policy->mapping == mapping && 2321 policy->action != action) 2322 return 0; 2323 2324 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2325 } 2326 2327 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2328 struct ethtool_rx_flow_spec *fs) 2329 { 2330 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2331 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2332 enum mv88e6xxx_policy_mapping mapping; 2333 enum mv88e6xxx_policy_action action; 2334 struct mv88e6xxx_policy *policy; 2335 u16 vid = 0; 2336 u8 *addr; 2337 int err; 2338 int id; 2339 2340 if (fs->location != RX_CLS_LOC_ANY) 2341 return -EINVAL; 2342 2343 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2344 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2345 else 2346 return -EOPNOTSUPP; 2347 2348 switch (fs->flow_type & ~FLOW_EXT) { 2349 case ETHER_FLOW: 2350 if (!is_zero_ether_addr(mac_mask->h_dest) && 2351 is_zero_ether_addr(mac_mask->h_source)) { 2352 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2353 addr = mac_entry->h_dest; 2354 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2355 !is_zero_ether_addr(mac_mask->h_source)) { 2356 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2357 addr = mac_entry->h_source; 2358 } else { 2359 /* Cannot support DA and SA mapping in the same rule */ 2360 return -EOPNOTSUPP; 2361 } 2362 break; 2363 default: 2364 return -EOPNOTSUPP; 2365 } 2366 2367 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2368 if (fs->m_ext.vlan_tci != htons(0xffff)) 2369 return -EOPNOTSUPP; 2370 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2371 } 2372 2373 idr_for_each_entry(&chip->policies, policy, id) { 2374 if (policy->port == port && policy->mapping == mapping && 2375 policy->action == action && policy->vid == vid && 2376 ether_addr_equal(policy->addr, addr)) 2377 return -EEXIST; 2378 } 2379 2380 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2381 if (!policy) 2382 return -ENOMEM; 2383 2384 fs->location = 0; 2385 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2386 GFP_KERNEL); 2387 if (err) { 2388 devm_kfree(chip->dev, policy); 2389 return err; 2390 } 2391 2392 memcpy(&policy->fs, fs, sizeof(*fs)); 2393 ether_addr_copy(policy->addr, addr); 2394 policy->mapping = mapping; 2395 policy->action = action; 2396 policy->port = port; 2397 policy->vid = vid; 2398 2399 err = mv88e6xxx_policy_apply(chip, port, policy); 2400 if (err) { 2401 idr_remove(&chip->policies, fs->location); 2402 devm_kfree(chip->dev, policy); 2403 return err; 2404 } 2405 2406 return 0; 2407 } 2408 2409 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2410 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2411 { 2412 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2413 struct mv88e6xxx_chip *chip = ds->priv; 2414 struct mv88e6xxx_policy *policy; 2415 int err; 2416 int id; 2417 2418 mv88e6xxx_reg_lock(chip); 2419 2420 switch (rxnfc->cmd) { 2421 case ETHTOOL_GRXCLSRLCNT: 2422 rxnfc->data = 0; 2423 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2424 rxnfc->rule_cnt = 0; 2425 idr_for_each_entry(&chip->policies, policy, id) 2426 if (policy->port == port) 2427 rxnfc->rule_cnt++; 2428 err = 0; 2429 break; 2430 case ETHTOOL_GRXCLSRULE: 2431 err = -ENOENT; 2432 policy = idr_find(&chip->policies, fs->location); 2433 if (policy) { 2434 memcpy(fs, &policy->fs, sizeof(*fs)); 2435 err = 0; 2436 } 2437 break; 2438 case ETHTOOL_GRXCLSRLALL: 2439 rxnfc->data = 0; 2440 rxnfc->rule_cnt = 0; 2441 idr_for_each_entry(&chip->policies, policy, id) 2442 if (policy->port == port) 2443 rule_locs[rxnfc->rule_cnt++] = id; 2444 err = 0; 2445 break; 2446 default: 2447 err = -EOPNOTSUPP; 2448 break; 2449 } 2450 2451 mv88e6xxx_reg_unlock(chip); 2452 2453 return err; 2454 } 2455 2456 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2457 struct ethtool_rxnfc *rxnfc) 2458 { 2459 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2460 struct mv88e6xxx_chip *chip = ds->priv; 2461 struct mv88e6xxx_policy *policy; 2462 int err; 2463 2464 mv88e6xxx_reg_lock(chip); 2465 2466 switch (rxnfc->cmd) { 2467 case ETHTOOL_SRXCLSRLINS: 2468 err = mv88e6xxx_policy_insert(chip, port, fs); 2469 break; 2470 case ETHTOOL_SRXCLSRLDEL: 2471 err = -ENOENT; 2472 policy = idr_remove(&chip->policies, fs->location); 2473 if (policy) { 2474 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2475 err = mv88e6xxx_policy_apply(chip, port, policy); 2476 devm_kfree(chip->dev, policy); 2477 } 2478 break; 2479 default: 2480 err = -EOPNOTSUPP; 2481 break; 2482 } 2483 2484 mv88e6xxx_reg_unlock(chip); 2485 2486 return err; 2487 } 2488 2489 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2490 u16 vid) 2491 { 2492 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2493 u8 broadcast[ETH_ALEN]; 2494 2495 eth_broadcast_addr(broadcast); 2496 2497 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2498 } 2499 2500 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2501 { 2502 int port; 2503 int err; 2504 2505 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2506 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2507 struct net_device *brport; 2508 2509 if (dsa_is_unused_port(chip->ds, port)) 2510 continue; 2511 2512 brport = dsa_port_to_bridge_port(dp); 2513 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2514 /* Skip bridged user ports where broadcast 2515 * flooding is disabled. 2516 */ 2517 continue; 2518 2519 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2520 if (err) 2521 return err; 2522 } 2523 2524 return 0; 2525 } 2526 2527 struct mv88e6xxx_port_broadcast_sync_ctx { 2528 int port; 2529 bool flood; 2530 }; 2531 2532 static int 2533 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2534 const struct mv88e6xxx_vtu_entry *vlan, 2535 void *_ctx) 2536 { 2537 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2538 u8 broadcast[ETH_ALEN]; 2539 u8 state; 2540 2541 if (ctx->flood) 2542 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2543 else 2544 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2545 2546 eth_broadcast_addr(broadcast); 2547 2548 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2549 vlan->vid, state); 2550 } 2551 2552 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2553 bool flood) 2554 { 2555 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2556 .port = port, 2557 .flood = flood, 2558 }; 2559 struct mv88e6xxx_vtu_entry vid0 = { 2560 .vid = 0, 2561 }; 2562 int err; 2563 2564 /* Update the port's private database... */ 2565 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2566 if (err) 2567 return err; 2568 2569 /* ...and the database for all VLANs. */ 2570 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2571 &ctx); 2572 } 2573 2574 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2575 u16 vid, u8 member, bool warn) 2576 { 2577 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2578 struct mv88e6xxx_vtu_entry vlan; 2579 int i, err; 2580 2581 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2582 if (err) 2583 return err; 2584 2585 if (!vlan.valid) { 2586 memset(&vlan, 0, sizeof(vlan)); 2587 2588 if (vid == MV88E6XXX_VID_STANDALONE) 2589 vlan.policy = true; 2590 2591 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2592 if (err) 2593 return err; 2594 2595 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2596 if (i == port) 2597 vlan.member[i] = member; 2598 else 2599 vlan.member[i] = non_member; 2600 2601 vlan.vid = vid; 2602 vlan.valid = true; 2603 2604 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2605 if (err) 2606 return err; 2607 2608 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2609 if (err) 2610 return err; 2611 } else if (vlan.member[port] != member) { 2612 vlan.member[port] = member; 2613 2614 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2615 if (err) 2616 return err; 2617 } else if (warn) { 2618 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2619 port, vid); 2620 } 2621 2622 /* Record FID used in SW FID map */ 2623 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2624 2625 return 0; 2626 } 2627 2628 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2629 const struct switchdev_obj_port_vlan *vlan, 2630 struct netlink_ext_ack *extack) 2631 { 2632 struct mv88e6xxx_chip *chip = ds->priv; 2633 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2634 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2635 struct mv88e6xxx_port *p = &chip->ports[port]; 2636 bool warn; 2637 u8 member; 2638 int err; 2639 2640 if (!vlan->vid) 2641 return 0; 2642 2643 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2644 if (err) 2645 return err; 2646 2647 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2648 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2649 else if (untagged) 2650 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2651 else 2652 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2653 2654 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2655 * and then the CPU port. Do not warn for duplicates for the CPU port. 2656 */ 2657 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2658 2659 mv88e6xxx_reg_lock(chip); 2660 2661 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2662 if (err) { 2663 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2664 vlan->vid, untagged ? 'u' : 't'); 2665 goto out; 2666 } 2667 2668 if (pvid) { 2669 p->bridge_pvid.vid = vlan->vid; 2670 p->bridge_pvid.valid = true; 2671 2672 err = mv88e6xxx_port_commit_pvid(chip, port); 2673 if (err) 2674 goto out; 2675 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2676 /* The old pvid was reinstalled as a non-pvid VLAN */ 2677 p->bridge_pvid.valid = false; 2678 2679 err = mv88e6xxx_port_commit_pvid(chip, port); 2680 if (err) 2681 goto out; 2682 } 2683 2684 out: 2685 mv88e6xxx_reg_unlock(chip); 2686 2687 return err; 2688 } 2689 2690 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2691 int port, u16 vid) 2692 { 2693 struct mv88e6xxx_vtu_entry vlan; 2694 int i, err; 2695 2696 if (!vid) 2697 return 0; 2698 2699 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2700 if (err) 2701 return err; 2702 2703 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2704 * tell switchdev that this VLAN is likely handled in software. 2705 */ 2706 if (!vlan.valid || 2707 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2708 return -EOPNOTSUPP; 2709 2710 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2711 2712 /* keep the VLAN unless all ports are excluded */ 2713 vlan.valid = false; 2714 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2715 if (vlan.member[i] != 2716 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2717 vlan.valid = true; 2718 break; 2719 } 2720 } 2721 2722 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2723 if (err) 2724 return err; 2725 2726 if (!vlan.valid) { 2727 err = mv88e6xxx_mst_put(chip, vlan.sid); 2728 if (err) 2729 return err; 2730 2731 /* Record FID freed in SW FID map */ 2732 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2733 } 2734 2735 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2736 } 2737 2738 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2739 const struct switchdev_obj_port_vlan *vlan) 2740 { 2741 struct mv88e6xxx_chip *chip = ds->priv; 2742 struct mv88e6xxx_port *p = &chip->ports[port]; 2743 int err = 0; 2744 u16 pvid; 2745 2746 if (!mv88e6xxx_max_vid(chip)) 2747 return -EOPNOTSUPP; 2748 2749 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2750 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2751 * switchdev workqueue to ensure that all FDB entries are deleted 2752 * before we remove the VLAN. 2753 */ 2754 dsa_flush_workqueue(); 2755 2756 mv88e6xxx_reg_lock(chip); 2757 2758 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2759 if (err) 2760 goto unlock; 2761 2762 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2763 if (err) 2764 goto unlock; 2765 2766 if (vlan->vid == pvid) { 2767 p->bridge_pvid.valid = false; 2768 2769 err = mv88e6xxx_port_commit_pvid(chip, port); 2770 if (err) 2771 goto unlock; 2772 } 2773 2774 unlock: 2775 mv88e6xxx_reg_unlock(chip); 2776 2777 return err; 2778 } 2779 2780 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2781 { 2782 struct mv88e6xxx_chip *chip = ds->priv; 2783 struct mv88e6xxx_vtu_entry vlan; 2784 int err; 2785 2786 mv88e6xxx_reg_lock(chip); 2787 2788 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2789 if (err) 2790 goto unlock; 2791 2792 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2793 2794 unlock: 2795 mv88e6xxx_reg_unlock(chip); 2796 2797 return err; 2798 } 2799 2800 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2801 struct dsa_bridge bridge, 2802 const struct switchdev_vlan_msti *msti) 2803 { 2804 struct mv88e6xxx_chip *chip = ds->priv; 2805 struct mv88e6xxx_vtu_entry vlan; 2806 u8 old_sid, new_sid; 2807 int err; 2808 2809 if (!mv88e6xxx_has_stu(chip)) 2810 return -EOPNOTSUPP; 2811 2812 mv88e6xxx_reg_lock(chip); 2813 2814 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2815 if (err) 2816 goto unlock; 2817 2818 if (!vlan.valid) { 2819 err = -EINVAL; 2820 goto unlock; 2821 } 2822 2823 old_sid = vlan.sid; 2824 2825 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2826 if (err) 2827 goto unlock; 2828 2829 if (new_sid != old_sid) { 2830 vlan.sid = new_sid; 2831 2832 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2833 if (err) { 2834 mv88e6xxx_mst_put(chip, new_sid); 2835 goto unlock; 2836 } 2837 } 2838 2839 err = mv88e6xxx_mst_put(chip, old_sid); 2840 2841 unlock: 2842 mv88e6xxx_reg_unlock(chip); 2843 return err; 2844 } 2845 2846 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2847 const unsigned char *addr, u16 vid, 2848 struct dsa_db db) 2849 { 2850 struct mv88e6xxx_chip *chip = ds->priv; 2851 int err; 2852 2853 mv88e6xxx_reg_lock(chip); 2854 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2855 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2856 mv88e6xxx_reg_unlock(chip); 2857 2858 return err; 2859 } 2860 2861 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2862 const unsigned char *addr, u16 vid, 2863 struct dsa_db db) 2864 { 2865 struct mv88e6xxx_chip *chip = ds->priv; 2866 int err; 2867 2868 mv88e6xxx_reg_lock(chip); 2869 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2870 mv88e6xxx_reg_unlock(chip); 2871 2872 return err; 2873 } 2874 2875 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2876 u16 fid, u16 vid, int port, 2877 dsa_fdb_dump_cb_t *cb, void *data) 2878 { 2879 struct mv88e6xxx_atu_entry addr; 2880 bool is_static; 2881 int err; 2882 2883 addr.state = 0; 2884 eth_broadcast_addr(addr.mac); 2885 2886 do { 2887 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2888 if (err) 2889 return err; 2890 2891 if (!addr.state) 2892 break; 2893 2894 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2895 continue; 2896 2897 if (!is_unicast_ether_addr(addr.mac)) 2898 continue; 2899 2900 is_static = (addr.state == 2901 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2902 err = cb(addr.mac, vid, is_static, data); 2903 if (err) 2904 return err; 2905 } while (!is_broadcast_ether_addr(addr.mac)); 2906 2907 return err; 2908 } 2909 2910 struct mv88e6xxx_port_db_dump_vlan_ctx { 2911 int port; 2912 dsa_fdb_dump_cb_t *cb; 2913 void *data; 2914 }; 2915 2916 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2917 const struct mv88e6xxx_vtu_entry *entry, 2918 void *_data) 2919 { 2920 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2921 2922 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2923 ctx->port, ctx->cb, ctx->data); 2924 } 2925 2926 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2927 dsa_fdb_dump_cb_t *cb, void *data) 2928 { 2929 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2930 .port = port, 2931 .cb = cb, 2932 .data = data, 2933 }; 2934 u16 fid; 2935 int err; 2936 2937 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2938 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2939 if (err) 2940 return err; 2941 2942 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2943 if (err) 2944 return err; 2945 2946 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2947 } 2948 2949 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2950 dsa_fdb_dump_cb_t *cb, void *data) 2951 { 2952 struct mv88e6xxx_chip *chip = ds->priv; 2953 int err; 2954 2955 mv88e6xxx_reg_lock(chip); 2956 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2957 mv88e6xxx_reg_unlock(chip); 2958 2959 return err; 2960 } 2961 2962 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2963 struct dsa_bridge bridge) 2964 { 2965 struct dsa_switch *ds = chip->ds; 2966 struct dsa_switch_tree *dst = ds->dst; 2967 struct dsa_port *dp; 2968 int err; 2969 2970 list_for_each_entry(dp, &dst->ports, list) { 2971 if (dsa_port_offloads_bridge(dp, &bridge)) { 2972 if (dp->ds == ds) { 2973 /* This is a local bridge group member, 2974 * remap its Port VLAN Map. 2975 */ 2976 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2977 if (err) 2978 return err; 2979 } else { 2980 /* This is an external bridge group member, 2981 * remap its cross-chip Port VLAN Table entry. 2982 */ 2983 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2984 dp->index); 2985 if (err) 2986 return err; 2987 } 2988 } 2989 } 2990 2991 return 0; 2992 } 2993 2994 /* Treat the software bridge as a virtual single-port switch behind the 2995 * CPU and map in the PVT. First dst->last_switch elements are taken by 2996 * physical switches, so start from beyond that range. 2997 */ 2998 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2999 unsigned int bridge_num) 3000 { 3001 u8 dev = bridge_num + ds->dst->last_switch; 3002 struct mv88e6xxx_chip *chip = ds->priv; 3003 3004 return mv88e6xxx_pvt_map(chip, dev, 0); 3005 } 3006 3007 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3008 struct dsa_bridge bridge, 3009 bool *tx_fwd_offload, 3010 struct netlink_ext_ack *extack) 3011 { 3012 struct mv88e6xxx_chip *chip = ds->priv; 3013 int err; 3014 3015 mv88e6xxx_reg_lock(chip); 3016 3017 err = mv88e6xxx_bridge_map(chip, bridge); 3018 if (err) 3019 goto unlock; 3020 3021 err = mv88e6xxx_port_set_map_da(chip, port, true); 3022 if (err) 3023 goto unlock; 3024 3025 err = mv88e6xxx_port_commit_pvid(chip, port); 3026 if (err) 3027 goto unlock; 3028 3029 if (mv88e6xxx_has_pvt(chip)) { 3030 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3031 if (err) 3032 goto unlock; 3033 3034 *tx_fwd_offload = true; 3035 } 3036 3037 unlock: 3038 mv88e6xxx_reg_unlock(chip); 3039 3040 return err; 3041 } 3042 3043 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3044 struct dsa_bridge bridge) 3045 { 3046 struct mv88e6xxx_chip *chip = ds->priv; 3047 int err; 3048 3049 mv88e6xxx_reg_lock(chip); 3050 3051 if (bridge.tx_fwd_offload && 3052 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3053 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3054 3055 if (mv88e6xxx_bridge_map(chip, bridge) || 3056 mv88e6xxx_port_vlan_map(chip, port)) 3057 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3058 3059 err = mv88e6xxx_port_set_map_da(chip, port, false); 3060 if (err) 3061 dev_err(ds->dev, 3062 "port %d failed to restore map-DA: %pe\n", 3063 port, ERR_PTR(err)); 3064 3065 err = mv88e6xxx_port_commit_pvid(chip, port); 3066 if (err) 3067 dev_err(ds->dev, 3068 "port %d failed to restore standalone pvid: %pe\n", 3069 port, ERR_PTR(err)); 3070 3071 mv88e6xxx_reg_unlock(chip); 3072 } 3073 3074 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3075 int tree_index, int sw_index, 3076 int port, struct dsa_bridge bridge, 3077 struct netlink_ext_ack *extack) 3078 { 3079 struct mv88e6xxx_chip *chip = ds->priv; 3080 int err; 3081 3082 if (tree_index != ds->dst->index) 3083 return 0; 3084 3085 mv88e6xxx_reg_lock(chip); 3086 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3087 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3088 mv88e6xxx_reg_unlock(chip); 3089 3090 return err; 3091 } 3092 3093 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3094 int tree_index, int sw_index, 3095 int port, struct dsa_bridge bridge) 3096 { 3097 struct mv88e6xxx_chip *chip = ds->priv; 3098 3099 if (tree_index != ds->dst->index) 3100 return; 3101 3102 mv88e6xxx_reg_lock(chip); 3103 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3104 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3105 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3106 mv88e6xxx_reg_unlock(chip); 3107 } 3108 3109 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3110 { 3111 if (chip->info->ops->reset) 3112 return chip->info->ops->reset(chip); 3113 3114 return 0; 3115 } 3116 3117 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3118 { 3119 struct gpio_desc *gpiod = chip->reset; 3120 int err; 3121 3122 /* If there is a GPIO connected to the reset pin, toggle it */ 3123 if (gpiod) { 3124 /* If the switch has just been reset and not yet completed 3125 * loading EEPROM, the reset may interrupt the I2C transaction 3126 * mid-byte, causing the first EEPROM read after the reset 3127 * from the wrong location resulting in the switch booting 3128 * to wrong mode and inoperable. 3129 * For this reason, switch families with EEPROM support 3130 * generally wait for EEPROM loads to complete as their pre- 3131 * and post-reset handlers. 3132 */ 3133 if (chip->info->ops->hardware_reset_pre) { 3134 err = chip->info->ops->hardware_reset_pre(chip); 3135 if (err) 3136 dev_err(chip->dev, "pre-reset error: %d\n", err); 3137 } 3138 3139 gpiod_set_value_cansleep(gpiod, 1); 3140 usleep_range(10000, 20000); 3141 gpiod_set_value_cansleep(gpiod, 0); 3142 usleep_range(10000, 20000); 3143 3144 if (chip->info->ops->hardware_reset_post) { 3145 err = chip->info->ops->hardware_reset_post(chip); 3146 if (err) 3147 dev_err(chip->dev, "post-reset error: %d\n", err); 3148 } 3149 } 3150 } 3151 3152 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3153 { 3154 int i, err; 3155 3156 /* Set all ports to the Disabled state */ 3157 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3158 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3159 if (err) 3160 return err; 3161 } 3162 3163 /* Wait for transmit queues to drain, 3164 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3165 */ 3166 usleep_range(2000, 4000); 3167 3168 return 0; 3169 } 3170 3171 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3172 { 3173 int err; 3174 3175 err = mv88e6xxx_disable_ports(chip); 3176 if (err) 3177 return err; 3178 3179 mv88e6xxx_hardware_reset(chip); 3180 3181 return mv88e6xxx_software_reset(chip); 3182 } 3183 3184 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3185 enum mv88e6xxx_frame_mode frame, 3186 enum mv88e6xxx_egress_mode egress, u16 etype) 3187 { 3188 int err; 3189 3190 if (!chip->info->ops->port_set_frame_mode) 3191 return -EOPNOTSUPP; 3192 3193 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3194 if (err) 3195 return err; 3196 3197 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3198 if (err) 3199 return err; 3200 3201 if (chip->info->ops->port_set_ether_type) 3202 return chip->info->ops->port_set_ether_type(chip, port, etype); 3203 3204 return 0; 3205 } 3206 3207 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3208 { 3209 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3210 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3211 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3212 } 3213 3214 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3215 { 3216 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3217 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3218 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3219 } 3220 3221 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3222 { 3223 return mv88e6xxx_set_port_mode(chip, port, 3224 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3225 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3226 ETH_P_EDSA); 3227 } 3228 3229 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3230 { 3231 if (dsa_is_dsa_port(chip->ds, port)) 3232 return mv88e6xxx_set_port_mode_dsa(chip, port); 3233 3234 if (dsa_is_user_port(chip->ds, port)) 3235 return mv88e6xxx_set_port_mode_normal(chip, port); 3236 3237 /* Setup CPU port mode depending on its supported tag format */ 3238 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3239 return mv88e6xxx_set_port_mode_dsa(chip, port); 3240 3241 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3242 return mv88e6xxx_set_port_mode_edsa(chip, port); 3243 3244 return -EINVAL; 3245 } 3246 3247 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3248 { 3249 bool message = dsa_is_dsa_port(chip->ds, port); 3250 3251 return mv88e6xxx_port_set_message_port(chip, port, message); 3252 } 3253 3254 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3255 { 3256 int err; 3257 3258 if (chip->info->ops->port_set_ucast_flood) { 3259 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3260 if (err) 3261 return err; 3262 } 3263 if (chip->info->ops->port_set_mcast_flood) { 3264 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3265 if (err) 3266 return err; 3267 } 3268 3269 return 0; 3270 } 3271 3272 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3273 enum mv88e6xxx_egress_direction direction, 3274 int port) 3275 { 3276 int err; 3277 3278 if (!chip->info->ops->set_egress_port) 3279 return -EOPNOTSUPP; 3280 3281 err = chip->info->ops->set_egress_port(chip, direction, port); 3282 if (err) 3283 return err; 3284 3285 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3286 chip->ingress_dest_port = port; 3287 else 3288 chip->egress_dest_port = port; 3289 3290 return 0; 3291 } 3292 3293 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3294 { 3295 struct dsa_switch *ds = chip->ds; 3296 int upstream_port; 3297 int err; 3298 3299 upstream_port = dsa_upstream_port(ds, port); 3300 if (chip->info->ops->port_set_upstream_port) { 3301 err = chip->info->ops->port_set_upstream_port(chip, port, 3302 upstream_port); 3303 if (err) 3304 return err; 3305 } 3306 3307 if (port == upstream_port) { 3308 if (chip->info->ops->set_cpu_port) { 3309 err = chip->info->ops->set_cpu_port(chip, 3310 upstream_port); 3311 if (err) 3312 return err; 3313 } 3314 3315 err = mv88e6xxx_set_egress_port(chip, 3316 MV88E6XXX_EGRESS_DIR_INGRESS, 3317 upstream_port); 3318 if (err && err != -EOPNOTSUPP) 3319 return err; 3320 3321 err = mv88e6xxx_set_egress_port(chip, 3322 MV88E6XXX_EGRESS_DIR_EGRESS, 3323 upstream_port); 3324 if (err && err != -EOPNOTSUPP) 3325 return err; 3326 } 3327 3328 return 0; 3329 } 3330 3331 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3332 { 3333 struct device_node *phy_handle = NULL; 3334 struct fwnode_handle *ports_fwnode; 3335 struct fwnode_handle *port_fwnode; 3336 struct dsa_switch *ds = chip->ds; 3337 struct mv88e6xxx_port *p; 3338 struct dsa_port *dp; 3339 int tx_amp; 3340 int err; 3341 u16 reg; 3342 u32 val; 3343 3344 p = &chip->ports[port]; 3345 p->chip = chip; 3346 p->port = port; 3347 3348 /* Look up corresponding fwnode if any */ 3349 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3350 if (!ports_fwnode) 3351 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3352 if (ports_fwnode) { 3353 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3354 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3355 continue; 3356 if (val == port) { 3357 p->fwnode = port_fwnode; 3358 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3359 break; 3360 } 3361 } 3362 fwnode_handle_put(ports_fwnode); 3363 } else { 3364 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3365 } 3366 3367 if (chip->info->ops->port_setup_leds) { 3368 err = chip->info->ops->port_setup_leds(chip, port); 3369 if (err && err != -EOPNOTSUPP) 3370 return err; 3371 } 3372 3373 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3374 SPEED_UNFORCED, DUPLEX_UNFORCED, 3375 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3376 if (err) 3377 return err; 3378 3379 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3380 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3381 * tunneling, determine priority by looking at 802.1p and IP 3382 * priority fields (IP prio has precedence), and set STP state 3383 * to Forwarding. 3384 * 3385 * If this is the CPU link, use DSA or EDSA tagging depending 3386 * on which tagging mode was configured. 3387 * 3388 * If this is a link to another switch, use DSA tagging mode. 3389 * 3390 * If this is the upstream port for this switch, enable 3391 * forwarding of unknown unicasts and multicasts. 3392 */ 3393 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3394 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3395 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3396 * by a USER port to the CPU port to allow snooping. 3397 */ 3398 if (dsa_is_user_port(ds, port)) 3399 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3400 3401 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3402 if (err) 3403 return err; 3404 3405 err = mv88e6xxx_setup_port_mode(chip, port); 3406 if (err) 3407 return err; 3408 3409 err = mv88e6xxx_setup_egress_floods(chip, port); 3410 if (err) 3411 return err; 3412 3413 /* Port Control 2: don't force a good FCS, set the MTU size to 3414 * 10222 bytes, disable 802.1q tags checking, don't discard 3415 * tagged or untagged frames on this port, skip destination 3416 * address lookup on user ports, disable ARP mirroring and don't 3417 * send a copy of all transmitted/received frames on this port 3418 * to the CPU. 3419 */ 3420 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3421 if (err) 3422 return err; 3423 3424 err = mv88e6xxx_setup_upstream_port(chip, port); 3425 if (err) 3426 return err; 3427 3428 /* On chips that support it, set all downstream DSA ports' 3429 * VLAN policy to TRAP. In combination with loading 3430 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3431 * provides a better isolation barrier between standalone 3432 * ports, as the ATU is bypassed on any intermediate switches 3433 * between the incoming port and the CPU. 3434 */ 3435 if (dsa_is_downstream_port(ds, port) && 3436 chip->info->ops->port_set_policy) { 3437 err = chip->info->ops->port_set_policy(chip, port, 3438 MV88E6XXX_POLICY_MAPPING_VTU, 3439 MV88E6XXX_POLICY_ACTION_TRAP); 3440 if (err) 3441 return err; 3442 } 3443 3444 /* User ports start out in standalone mode and 802.1Q is 3445 * therefore disabled. On DSA ports, all valid VIDs are always 3446 * loaded in the VTU - therefore, enable 802.1Q in order to take 3447 * advantage of VLAN policy on chips that supports it. 3448 */ 3449 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3450 dsa_is_user_port(ds, port) ? 3451 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3452 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3453 if (err) 3454 return err; 3455 3456 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3457 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3458 * the first free FID. This will be used as the private PVID for 3459 * unbridged ports. Shared (DSA and CPU) ports must also be 3460 * members of this VID, in order to trap all frames assigned to 3461 * it to the CPU. 3462 */ 3463 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3464 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3465 false); 3466 if (err) 3467 return err; 3468 3469 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3470 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3471 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3472 * as the private PVID on ports under a VLAN-unaware bridge. 3473 * Shared (DSA and CPU) ports must also be members of it, to translate 3474 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3475 * relying on their port default FID. 3476 */ 3477 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3478 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3479 false); 3480 if (err) 3481 return err; 3482 3483 if (chip->info->ops->port_set_jumbo_size) { 3484 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3485 if (err) 3486 return err; 3487 } 3488 3489 /* Port Association Vector: disable automatic address learning 3490 * on all user ports since they start out in standalone 3491 * mode. When joining a bridge, learning will be configured to 3492 * match the bridge port settings. Enable learning on all 3493 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3494 * learning process. 3495 * 3496 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3497 * and RefreshLocked. I.e. setup standard automatic learning. 3498 */ 3499 if (dsa_is_user_port(ds, port)) 3500 reg = 0; 3501 else 3502 reg = 1 << port; 3503 3504 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3505 reg); 3506 if (err) 3507 return err; 3508 3509 /* Egress rate control 2: disable egress rate control. */ 3510 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3511 0x0000); 3512 if (err) 3513 return err; 3514 3515 if (chip->info->ops->port_pause_limit) { 3516 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3517 if (err) 3518 return err; 3519 } 3520 3521 if (chip->info->ops->port_disable_learn_limit) { 3522 err = chip->info->ops->port_disable_learn_limit(chip, port); 3523 if (err) 3524 return err; 3525 } 3526 3527 if (chip->info->ops->port_disable_pri_override) { 3528 err = chip->info->ops->port_disable_pri_override(chip, port); 3529 if (err) 3530 return err; 3531 } 3532 3533 if (chip->info->ops->port_tag_remap) { 3534 err = chip->info->ops->port_tag_remap(chip, port); 3535 if (err) 3536 return err; 3537 } 3538 3539 if (chip->info->ops->port_egress_rate_limiting) { 3540 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3541 if (err) 3542 return err; 3543 } 3544 3545 if (chip->info->ops->port_setup_message_port) { 3546 err = chip->info->ops->port_setup_message_port(chip, port); 3547 if (err) 3548 return err; 3549 } 3550 3551 if (chip->info->ops->serdes_set_tx_amplitude) { 3552 dp = dsa_to_port(ds, port); 3553 if (dp) 3554 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3555 3556 if (phy_handle && !of_property_read_u32(phy_handle, 3557 "tx-p2p-microvolt", 3558 &tx_amp)) 3559 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3560 port, tx_amp); 3561 if (phy_handle) { 3562 of_node_put(phy_handle); 3563 if (err) 3564 return err; 3565 } 3566 } 3567 3568 /* Port based VLAN map: give each port the same default address 3569 * database, and allow bidirectional communication between the 3570 * CPU and DSA port(s), and the other ports. 3571 */ 3572 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3573 if (err) 3574 return err; 3575 3576 err = mv88e6xxx_port_vlan_map(chip, port); 3577 if (err) 3578 return err; 3579 3580 /* Default VLAN ID and priority: don't set a default VLAN 3581 * ID, and set the default packet priority to zero. 3582 */ 3583 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3584 } 3585 3586 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3587 { 3588 struct mv88e6xxx_chip *chip = ds->priv; 3589 3590 if (chip->info->ops->port_set_jumbo_size) 3591 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3592 else if (chip->info->ops->set_max_frame_size) 3593 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3594 return ETH_DATA_LEN; 3595 } 3596 3597 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3598 { 3599 struct mv88e6xxx_chip *chip = ds->priv; 3600 int ret = 0; 3601 3602 /* For families where we don't know how to alter the MTU, 3603 * just accept any value up to ETH_DATA_LEN 3604 */ 3605 if (!chip->info->ops->port_set_jumbo_size && 3606 !chip->info->ops->set_max_frame_size) { 3607 if (new_mtu > ETH_DATA_LEN) 3608 return -EINVAL; 3609 3610 return 0; 3611 } 3612 3613 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3614 new_mtu += EDSA_HLEN; 3615 3616 mv88e6xxx_reg_lock(chip); 3617 if (chip->info->ops->port_set_jumbo_size) 3618 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3619 else if (chip->info->ops->set_max_frame_size && 3620 dsa_is_cpu_port(ds, port)) 3621 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3622 mv88e6xxx_reg_unlock(chip); 3623 3624 return ret; 3625 } 3626 3627 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3628 unsigned int ageing_time) 3629 { 3630 struct mv88e6xxx_chip *chip = ds->priv; 3631 int err; 3632 3633 mv88e6xxx_reg_lock(chip); 3634 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3635 mv88e6xxx_reg_unlock(chip); 3636 3637 return err; 3638 } 3639 3640 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3641 { 3642 int err; 3643 3644 /* Initialize the statistics unit */ 3645 if (chip->info->ops->stats_set_histogram) { 3646 err = chip->info->ops->stats_set_histogram(chip); 3647 if (err) 3648 return err; 3649 } 3650 3651 return mv88e6xxx_g1_stats_clear(chip); 3652 } 3653 3654 /* Check if the errata has already been applied. */ 3655 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3656 { 3657 int port; 3658 int err; 3659 u16 val; 3660 3661 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3662 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3663 if (err) { 3664 dev_err(chip->dev, 3665 "Error reading hidden register: %d\n", err); 3666 return false; 3667 } 3668 if (val != 0x01c0) 3669 return false; 3670 } 3671 3672 return true; 3673 } 3674 3675 /* The 6390 copper ports have an errata which require poking magic 3676 * values into undocumented hidden registers and then performing a 3677 * software reset. 3678 */ 3679 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3680 { 3681 int port; 3682 int err; 3683 3684 if (mv88e6390_setup_errata_applied(chip)) 3685 return 0; 3686 3687 /* Set the ports into blocking mode */ 3688 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3689 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3690 if (err) 3691 return err; 3692 } 3693 3694 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3695 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3696 if (err) 3697 return err; 3698 } 3699 3700 return mv88e6xxx_software_reset(chip); 3701 } 3702 3703 /* prod_id for switch families which do not have a PHY model number */ 3704 static const u16 family_prod_id_table[] = { 3705 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3706 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3707 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3708 }; 3709 3710 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3711 { 3712 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3713 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3714 u16 prod_id; 3715 u16 val; 3716 int err; 3717 3718 if (!chip->info->ops->phy_read) 3719 return -EOPNOTSUPP; 3720 3721 mv88e6xxx_reg_lock(chip); 3722 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3723 mv88e6xxx_reg_unlock(chip); 3724 3725 /* Some internal PHYs don't have a model number. */ 3726 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3727 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3728 prod_id = family_prod_id_table[chip->info->family]; 3729 if (prod_id) 3730 val |= prod_id >> 4; 3731 } 3732 3733 return err ? err : val; 3734 } 3735 3736 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3737 int reg) 3738 { 3739 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3740 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3741 u16 val; 3742 int err; 3743 3744 if (!chip->info->ops->phy_read_c45) 3745 return -ENODEV; 3746 3747 mv88e6xxx_reg_lock(chip); 3748 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3749 mv88e6xxx_reg_unlock(chip); 3750 3751 return err ? err : val; 3752 } 3753 3754 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3755 { 3756 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3757 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3758 int err; 3759 3760 if (!chip->info->ops->phy_write) 3761 return -EOPNOTSUPP; 3762 3763 mv88e6xxx_reg_lock(chip); 3764 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3765 mv88e6xxx_reg_unlock(chip); 3766 3767 return err; 3768 } 3769 3770 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3771 int reg, u16 val) 3772 { 3773 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3774 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3775 int err; 3776 3777 if (!chip->info->ops->phy_write_c45) 3778 return -EOPNOTSUPP; 3779 3780 mv88e6xxx_reg_lock(chip); 3781 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3782 mv88e6xxx_reg_unlock(chip); 3783 3784 return err; 3785 } 3786 3787 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3788 struct device_node *np, 3789 bool external) 3790 { 3791 static int index; 3792 struct mv88e6xxx_mdio_bus *mdio_bus; 3793 struct mii_bus *bus; 3794 int err; 3795 3796 if (external) { 3797 mv88e6xxx_reg_lock(chip); 3798 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3799 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3800 else 3801 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3802 mv88e6xxx_reg_unlock(chip); 3803 3804 if (err) 3805 return err; 3806 } 3807 3808 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3809 if (!bus) 3810 return -ENOMEM; 3811 3812 mdio_bus = bus->priv; 3813 mdio_bus->bus = bus; 3814 mdio_bus->chip = chip; 3815 INIT_LIST_HEAD(&mdio_bus->list); 3816 mdio_bus->external = external; 3817 3818 if (np) { 3819 bus->name = np->full_name; 3820 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3821 } else { 3822 bus->name = "mv88e6xxx SMI"; 3823 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3824 } 3825 3826 bus->read = mv88e6xxx_mdio_read; 3827 bus->write = mv88e6xxx_mdio_write; 3828 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3829 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3830 bus->parent = chip->dev; 3831 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3832 mv88e6xxx_num_ports(chip) - 1, 3833 chip->info->phy_base_addr); 3834 3835 if (!external) { 3836 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3837 if (err) 3838 goto out; 3839 } 3840 3841 err = of_mdiobus_register(bus, np); 3842 if (err) { 3843 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3844 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3845 goto out; 3846 } 3847 3848 if (external) 3849 list_add_tail(&mdio_bus->list, &chip->mdios); 3850 else 3851 list_add(&mdio_bus->list, &chip->mdios); 3852 3853 return 0; 3854 3855 out: 3856 mdiobus_free(bus); 3857 return err; 3858 } 3859 3860 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3861 3862 { 3863 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3864 struct mii_bus *bus; 3865 3866 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3867 bus = mdio_bus->bus; 3868 3869 if (!mdio_bus->external) 3870 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3871 3872 mdiobus_unregister(bus); 3873 mdiobus_free(bus); 3874 } 3875 } 3876 3877 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3878 { 3879 struct device_node *np = chip->dev->of_node; 3880 struct device_node *child; 3881 int err; 3882 3883 /* Always register one mdio bus for the internal/default mdio 3884 * bus. This maybe represented in the device tree, but is 3885 * optional. 3886 */ 3887 child = of_get_child_by_name(np, "mdio"); 3888 err = mv88e6xxx_mdio_register(chip, child, false); 3889 of_node_put(child); 3890 if (err) 3891 return err; 3892 3893 /* Walk the device tree, and see if there are any other nodes 3894 * which say they are compatible with the external mdio 3895 * bus. 3896 */ 3897 for_each_available_child_of_node(np, child) { 3898 if (of_device_is_compatible( 3899 child, "marvell,mv88e6xxx-mdio-external")) { 3900 err = mv88e6xxx_mdio_register(chip, child, true); 3901 if (err) { 3902 mv88e6xxx_mdios_unregister(chip); 3903 of_node_put(child); 3904 return err; 3905 } 3906 } 3907 } 3908 3909 return 0; 3910 } 3911 3912 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3913 { 3914 struct mv88e6xxx_chip *chip = ds->priv; 3915 3916 mv88e6xxx_teardown_devlink_params(ds); 3917 dsa_devlink_resources_unregister(ds); 3918 mv88e6xxx_teardown_devlink_regions_global(ds); 3919 mv88e6xxx_mdios_unregister(chip); 3920 } 3921 3922 static int mv88e6xxx_setup(struct dsa_switch *ds) 3923 { 3924 struct mv88e6xxx_chip *chip = ds->priv; 3925 u8 cmode; 3926 int err; 3927 int i; 3928 3929 err = mv88e6xxx_mdios_register(chip); 3930 if (err) 3931 return err; 3932 3933 chip->ds = ds; 3934 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3935 3936 /* Since virtual bridges are mapped in the PVT, the number we support 3937 * depends on the physical switch topology. We need to let DSA figure 3938 * that out and therefore we cannot set this at dsa_register_switch() 3939 * time. 3940 */ 3941 if (mv88e6xxx_has_pvt(chip)) 3942 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3943 ds->dst->last_switch - 1; 3944 3945 mv88e6xxx_reg_lock(chip); 3946 3947 if (chip->info->ops->setup_errata) { 3948 err = chip->info->ops->setup_errata(chip); 3949 if (err) 3950 goto unlock; 3951 } 3952 3953 /* Cache the cmode of each port. */ 3954 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3955 if (chip->info->ops->port_get_cmode) { 3956 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3957 if (err) 3958 goto unlock; 3959 3960 chip->ports[i].cmode = cmode; 3961 } 3962 } 3963 3964 err = mv88e6xxx_vtu_setup(chip); 3965 if (err) 3966 goto unlock; 3967 3968 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3969 * VTU, thereby also flushing the STU). 3970 */ 3971 err = mv88e6xxx_stu_setup(chip); 3972 if (err) 3973 goto unlock; 3974 3975 /* Setup Switch Port Registers */ 3976 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3977 if (dsa_is_unused_port(ds, i)) 3978 continue; 3979 3980 /* Prevent the use of an invalid port. */ 3981 if (mv88e6xxx_is_invalid_port(chip, i)) { 3982 dev_err(chip->dev, "port %d is invalid\n", i); 3983 err = -EINVAL; 3984 goto unlock; 3985 } 3986 3987 err = mv88e6xxx_setup_port(chip, i); 3988 if (err) 3989 goto unlock; 3990 } 3991 3992 err = mv88e6xxx_irl_setup(chip); 3993 if (err) 3994 goto unlock; 3995 3996 err = mv88e6xxx_mac_setup(chip); 3997 if (err) 3998 goto unlock; 3999 4000 err = mv88e6xxx_phy_setup(chip); 4001 if (err) 4002 goto unlock; 4003 4004 err = mv88e6xxx_pvt_setup(chip); 4005 if (err) 4006 goto unlock; 4007 4008 err = mv88e6xxx_atu_setup(chip); 4009 if (err) 4010 goto unlock; 4011 4012 err = mv88e6xxx_broadcast_setup(chip, 0); 4013 if (err) 4014 goto unlock; 4015 4016 err = mv88e6xxx_pot_setup(chip); 4017 if (err) 4018 goto unlock; 4019 4020 err = mv88e6xxx_rmu_setup(chip); 4021 if (err) 4022 goto unlock; 4023 4024 err = mv88e6xxx_rsvd2cpu_setup(chip); 4025 if (err) 4026 goto unlock; 4027 4028 err = mv88e6xxx_trunk_setup(chip); 4029 if (err) 4030 goto unlock; 4031 4032 err = mv88e6xxx_devmap_setup(chip); 4033 if (err) 4034 goto unlock; 4035 4036 err = mv88e6xxx_pri_setup(chip); 4037 if (err) 4038 goto unlock; 4039 4040 /* Setup PTP Hardware Clock and timestamping */ 4041 if (chip->info->ptp_support) { 4042 err = mv88e6xxx_ptp_setup(chip); 4043 if (err) 4044 goto unlock; 4045 4046 err = mv88e6xxx_hwtstamp_setup(chip); 4047 if (err) 4048 goto unlock; 4049 } 4050 4051 err = mv88e6xxx_stats_setup(chip); 4052 if (err) 4053 goto unlock; 4054 4055 unlock: 4056 mv88e6xxx_reg_unlock(chip); 4057 4058 if (err) 4059 goto out_mdios; 4060 4061 /* Have to be called without holding the register lock, since 4062 * they take the devlink lock, and we later take the locks in 4063 * the reverse order when getting/setting parameters or 4064 * resource occupancy. 4065 */ 4066 err = mv88e6xxx_setup_devlink_resources(ds); 4067 if (err) 4068 goto out_mdios; 4069 4070 err = mv88e6xxx_setup_devlink_params(ds); 4071 if (err) 4072 goto out_resources; 4073 4074 err = mv88e6xxx_setup_devlink_regions_global(ds); 4075 if (err) 4076 goto out_params; 4077 4078 return 0; 4079 4080 out_params: 4081 mv88e6xxx_teardown_devlink_params(ds); 4082 out_resources: 4083 dsa_devlink_resources_unregister(ds); 4084 out_mdios: 4085 mv88e6xxx_mdios_unregister(chip); 4086 4087 return err; 4088 } 4089 4090 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4091 { 4092 struct mv88e6xxx_chip *chip = ds->priv; 4093 int err; 4094 4095 if (chip->info->ops->pcs_ops && 4096 chip->info->ops->pcs_ops->pcs_init) { 4097 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4098 if (err) 4099 return err; 4100 } 4101 4102 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4103 } 4104 4105 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4106 { 4107 struct mv88e6xxx_chip *chip = ds->priv; 4108 4109 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4110 4111 if (chip->info->ops->pcs_ops && 4112 chip->info->ops->pcs_ops->pcs_teardown) 4113 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4114 } 4115 4116 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4117 { 4118 struct mv88e6xxx_chip *chip = ds->priv; 4119 4120 return chip->eeprom_len; 4121 } 4122 4123 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4124 struct ethtool_eeprom *eeprom, u8 *data) 4125 { 4126 struct mv88e6xxx_chip *chip = ds->priv; 4127 int err; 4128 4129 if (!chip->info->ops->get_eeprom) 4130 return -EOPNOTSUPP; 4131 4132 mv88e6xxx_reg_lock(chip); 4133 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4134 mv88e6xxx_reg_unlock(chip); 4135 4136 if (err) 4137 return err; 4138 4139 eeprom->magic = 0xc3ec4951; 4140 4141 return 0; 4142 } 4143 4144 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4145 struct ethtool_eeprom *eeprom, u8 *data) 4146 { 4147 struct mv88e6xxx_chip *chip = ds->priv; 4148 int err; 4149 4150 if (!chip->info->ops->set_eeprom) 4151 return -EOPNOTSUPP; 4152 4153 if (eeprom->magic != 0xc3ec4951) 4154 return -EINVAL; 4155 4156 mv88e6xxx_reg_lock(chip); 4157 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4158 mv88e6xxx_reg_unlock(chip); 4159 4160 return err; 4161 } 4162 4163 static const struct mv88e6xxx_ops mv88e6085_ops = { 4164 /* MV88E6XXX_FAMILY_6097 */ 4165 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4166 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4167 .irl_init_all = mv88e6352_g2_irl_init_all, 4168 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4169 .phy_read = mv88e6185_phy_ppu_read, 4170 .phy_write = mv88e6185_phy_ppu_write, 4171 .port_set_link = mv88e6xxx_port_set_link, 4172 .port_sync_link = mv88e6xxx_port_sync_link, 4173 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4174 .port_tag_remap = mv88e6095_port_tag_remap, 4175 .port_set_policy = mv88e6352_port_set_policy, 4176 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4177 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4178 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4179 .port_set_ether_type = mv88e6351_port_set_ether_type, 4180 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4181 .port_pause_limit = mv88e6097_port_pause_limit, 4182 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4183 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4184 .port_get_cmode = mv88e6185_port_get_cmode, 4185 .port_setup_message_port = mv88e6xxx_setup_message_port, 4186 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4187 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4188 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4189 .stats_get_strings = mv88e6095_stats_get_strings, 4190 .stats_get_stat = mv88e6095_stats_get_stat, 4191 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4192 .set_egress_port = mv88e6095_g1_set_egress_port, 4193 .watchdog_ops = &mv88e6097_watchdog_ops, 4194 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4195 .pot_clear = mv88e6xxx_g2_pot_clear, 4196 .ppu_enable = mv88e6185_g1_ppu_enable, 4197 .ppu_disable = mv88e6185_g1_ppu_disable, 4198 .reset = mv88e6185_g1_reset, 4199 .rmu_disable = mv88e6085_g1_rmu_disable, 4200 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4201 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4202 .stu_getnext = mv88e6352_g1_stu_getnext, 4203 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4204 .phylink_get_caps = mv88e6185_phylink_get_caps, 4205 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4206 }; 4207 4208 static const struct mv88e6xxx_ops mv88e6095_ops = { 4209 /* MV88E6XXX_FAMILY_6095 */ 4210 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4211 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4212 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4213 .phy_read = mv88e6185_phy_ppu_read, 4214 .phy_write = mv88e6185_phy_ppu_write, 4215 .port_set_link = mv88e6xxx_port_set_link, 4216 .port_sync_link = mv88e6185_port_sync_link, 4217 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4218 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4219 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4220 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4221 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4222 .port_get_cmode = mv88e6185_port_get_cmode, 4223 .port_setup_message_port = mv88e6xxx_setup_message_port, 4224 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4225 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4226 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4227 .stats_get_strings = mv88e6095_stats_get_strings, 4228 .stats_get_stat = mv88e6095_stats_get_stat, 4229 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4230 .ppu_enable = mv88e6185_g1_ppu_enable, 4231 .ppu_disable = mv88e6185_g1_ppu_disable, 4232 .reset = mv88e6185_g1_reset, 4233 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4234 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4235 .phylink_get_caps = mv88e6095_phylink_get_caps, 4236 .pcs_ops = &mv88e6185_pcs_ops, 4237 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4238 }; 4239 4240 static const struct mv88e6xxx_ops mv88e6097_ops = { 4241 /* MV88E6XXX_FAMILY_6097 */ 4242 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4243 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4244 .irl_init_all = mv88e6352_g2_irl_init_all, 4245 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4246 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4247 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4248 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4249 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4250 .port_set_link = mv88e6xxx_port_set_link, 4251 .port_sync_link = mv88e6185_port_sync_link, 4252 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4253 .port_tag_remap = mv88e6095_port_tag_remap, 4254 .port_set_policy = mv88e6352_port_set_policy, 4255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4256 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4257 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4258 .port_set_ether_type = mv88e6351_port_set_ether_type, 4259 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4260 .port_pause_limit = mv88e6097_port_pause_limit, 4261 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4262 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4263 .port_get_cmode = mv88e6185_port_get_cmode, 4264 .port_setup_message_port = mv88e6xxx_setup_message_port, 4265 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4266 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4267 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4268 .stats_get_strings = mv88e6095_stats_get_strings, 4269 .stats_get_stat = mv88e6095_stats_get_stat, 4270 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4271 .set_egress_port = mv88e6095_g1_set_egress_port, 4272 .watchdog_ops = &mv88e6097_watchdog_ops, 4273 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4274 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4275 .pot_clear = mv88e6xxx_g2_pot_clear, 4276 .reset = mv88e6352_g1_reset, 4277 .rmu_disable = mv88e6085_g1_rmu_disable, 4278 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4279 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4280 .phylink_get_caps = mv88e6095_phylink_get_caps, 4281 .pcs_ops = &mv88e6185_pcs_ops, 4282 .stu_getnext = mv88e6352_g1_stu_getnext, 4283 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4284 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4285 }; 4286 4287 static const struct mv88e6xxx_ops mv88e6123_ops = { 4288 /* MV88E6XXX_FAMILY_6165 */ 4289 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4290 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4291 .irl_init_all = mv88e6352_g2_irl_init_all, 4292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4293 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4294 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4295 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4296 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4297 .port_set_link = mv88e6xxx_port_set_link, 4298 .port_sync_link = mv88e6xxx_port_sync_link, 4299 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4300 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4301 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4302 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4305 .port_get_cmode = mv88e6185_port_get_cmode, 4306 .port_setup_message_port = mv88e6xxx_setup_message_port, 4307 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4308 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4309 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4310 .stats_get_strings = mv88e6095_stats_get_strings, 4311 .stats_get_stat = mv88e6095_stats_get_stat, 4312 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4313 .set_egress_port = mv88e6095_g1_set_egress_port, 4314 .watchdog_ops = &mv88e6097_watchdog_ops, 4315 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4316 .pot_clear = mv88e6xxx_g2_pot_clear, 4317 .reset = mv88e6352_g1_reset, 4318 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4319 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4320 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4321 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4322 .stu_getnext = mv88e6352_g1_stu_getnext, 4323 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4324 .phylink_get_caps = mv88e6185_phylink_get_caps, 4325 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4326 }; 4327 4328 static const struct mv88e6xxx_ops mv88e6131_ops = { 4329 /* MV88E6XXX_FAMILY_6185 */ 4330 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4331 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4332 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4333 .phy_read = mv88e6185_phy_ppu_read, 4334 .phy_write = mv88e6185_phy_ppu_write, 4335 .port_set_link = mv88e6xxx_port_set_link, 4336 .port_sync_link = mv88e6xxx_port_sync_link, 4337 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4338 .port_tag_remap = mv88e6095_port_tag_remap, 4339 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4340 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4341 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4342 .port_set_ether_type = mv88e6351_port_set_ether_type, 4343 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4344 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4345 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4346 .port_pause_limit = mv88e6097_port_pause_limit, 4347 .port_set_pause = mv88e6185_port_set_pause, 4348 .port_get_cmode = mv88e6185_port_get_cmode, 4349 .port_setup_message_port = mv88e6xxx_setup_message_port, 4350 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4351 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4352 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4353 .stats_get_strings = mv88e6095_stats_get_strings, 4354 .stats_get_stat = mv88e6095_stats_get_stat, 4355 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4356 .set_egress_port = mv88e6095_g1_set_egress_port, 4357 .watchdog_ops = &mv88e6097_watchdog_ops, 4358 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4359 .ppu_enable = mv88e6185_g1_ppu_enable, 4360 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4361 .ppu_disable = mv88e6185_g1_ppu_disable, 4362 .reset = mv88e6185_g1_reset, 4363 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4364 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4365 .phylink_get_caps = mv88e6185_phylink_get_caps, 4366 }; 4367 4368 static const struct mv88e6xxx_ops mv88e6141_ops = { 4369 /* MV88E6XXX_FAMILY_6341 */ 4370 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4371 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4372 .irl_init_all = mv88e6352_g2_irl_init_all, 4373 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4374 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4376 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4377 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4378 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4379 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4380 .port_set_link = mv88e6xxx_port_set_link, 4381 .port_sync_link = mv88e6xxx_port_sync_link, 4382 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4383 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4384 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4385 .port_tag_remap = mv88e6095_port_tag_remap, 4386 .port_set_policy = mv88e6352_port_set_policy, 4387 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4388 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4389 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4390 .port_set_ether_type = mv88e6351_port_set_ether_type, 4391 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4392 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4393 .port_pause_limit = mv88e6097_port_pause_limit, 4394 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4395 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4396 .port_get_cmode = mv88e6352_port_get_cmode, 4397 .port_set_cmode = mv88e6341_port_set_cmode, 4398 .port_setup_message_port = mv88e6xxx_setup_message_port, 4399 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4400 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4401 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4402 .stats_get_strings = mv88e6320_stats_get_strings, 4403 .stats_get_stat = mv88e6390_stats_get_stat, 4404 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4405 .set_egress_port = mv88e6390_g1_set_egress_port, 4406 .watchdog_ops = &mv88e6390_watchdog_ops, 4407 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4408 .pot_clear = mv88e6xxx_g2_pot_clear, 4409 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4410 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4411 .reset = mv88e6352_g1_reset, 4412 .rmu_disable = mv88e6390_g1_rmu_disable, 4413 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4414 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4415 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4416 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4417 .stu_getnext = mv88e6352_g1_stu_getnext, 4418 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4419 .serdes_get_lane = mv88e6341_serdes_get_lane, 4420 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4421 .gpio_ops = &mv88e6352_gpio_ops, 4422 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4423 .serdes_get_strings = mv88e6390_serdes_get_strings, 4424 .serdes_get_stats = mv88e6390_serdes_get_stats, 4425 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4426 .serdes_get_regs = mv88e6390_serdes_get_regs, 4427 .phylink_get_caps = mv88e6341_phylink_get_caps, 4428 .pcs_ops = &mv88e6390_pcs_ops, 4429 }; 4430 4431 static const struct mv88e6xxx_ops mv88e6161_ops = { 4432 /* MV88E6XXX_FAMILY_6165 */ 4433 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4434 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4435 .irl_init_all = mv88e6352_g2_irl_init_all, 4436 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4437 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4438 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4439 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4440 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4441 .port_set_link = mv88e6xxx_port_set_link, 4442 .port_sync_link = mv88e6xxx_port_sync_link, 4443 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4444 .port_tag_remap = mv88e6095_port_tag_remap, 4445 .port_set_policy = mv88e6352_port_set_policy, 4446 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4447 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4448 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4449 .port_set_ether_type = mv88e6351_port_set_ether_type, 4450 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4451 .port_pause_limit = mv88e6097_port_pause_limit, 4452 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4453 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4454 .port_get_cmode = mv88e6185_port_get_cmode, 4455 .port_setup_message_port = mv88e6xxx_setup_message_port, 4456 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4457 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4458 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4459 .stats_get_strings = mv88e6095_stats_get_strings, 4460 .stats_get_stat = mv88e6095_stats_get_stat, 4461 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4462 .set_egress_port = mv88e6095_g1_set_egress_port, 4463 .watchdog_ops = &mv88e6097_watchdog_ops, 4464 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4465 .pot_clear = mv88e6xxx_g2_pot_clear, 4466 .reset = mv88e6352_g1_reset, 4467 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4468 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4469 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4470 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4471 .stu_getnext = mv88e6352_g1_stu_getnext, 4472 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4473 .avb_ops = &mv88e6165_avb_ops, 4474 .ptp_ops = &mv88e6165_ptp_ops, 4475 .phylink_get_caps = mv88e6185_phylink_get_caps, 4476 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4477 }; 4478 4479 static const struct mv88e6xxx_ops mv88e6165_ops = { 4480 /* MV88E6XXX_FAMILY_6165 */ 4481 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4482 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4483 .irl_init_all = mv88e6352_g2_irl_init_all, 4484 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4485 .phy_read = mv88e6165_phy_read, 4486 .phy_write = mv88e6165_phy_write, 4487 .port_set_link = mv88e6xxx_port_set_link, 4488 .port_sync_link = mv88e6xxx_port_sync_link, 4489 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4492 .port_get_cmode = mv88e6185_port_get_cmode, 4493 .port_setup_message_port = mv88e6xxx_setup_message_port, 4494 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4497 .stats_get_strings = mv88e6095_stats_get_strings, 4498 .stats_get_stat = mv88e6095_stats_get_stat, 4499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4500 .set_egress_port = mv88e6095_g1_set_egress_port, 4501 .watchdog_ops = &mv88e6097_watchdog_ops, 4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4503 .pot_clear = mv88e6xxx_g2_pot_clear, 4504 .reset = mv88e6352_g1_reset, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .stu_getnext = mv88e6352_g1_stu_getnext, 4510 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4511 .avb_ops = &mv88e6165_avb_ops, 4512 .ptp_ops = &mv88e6165_ptp_ops, 4513 .phylink_get_caps = mv88e6185_phylink_get_caps, 4514 }; 4515 4516 static const struct mv88e6xxx_ops mv88e6171_ops = { 4517 /* MV88E6XXX_FAMILY_6351 */ 4518 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4519 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4520 .irl_init_all = mv88e6352_g2_irl_init_all, 4521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4522 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4523 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4524 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4525 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4526 .port_set_link = mv88e6xxx_port_set_link, 4527 .port_sync_link = mv88e6xxx_port_sync_link, 4528 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4529 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4530 .port_tag_remap = mv88e6095_port_tag_remap, 4531 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4532 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4533 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4534 .port_set_ether_type = mv88e6351_port_set_ether_type, 4535 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4537 .port_pause_limit = mv88e6097_port_pause_limit, 4538 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4539 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4540 .port_get_cmode = mv88e6352_port_get_cmode, 4541 .port_setup_message_port = mv88e6xxx_setup_message_port, 4542 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4543 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4544 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4545 .stats_get_strings = mv88e6095_stats_get_strings, 4546 .stats_get_stat = mv88e6095_stats_get_stat, 4547 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4548 .set_egress_port = mv88e6095_g1_set_egress_port, 4549 .watchdog_ops = &mv88e6097_watchdog_ops, 4550 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4551 .pot_clear = mv88e6xxx_g2_pot_clear, 4552 .reset = mv88e6352_g1_reset, 4553 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4554 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4555 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4556 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4557 .stu_getnext = mv88e6352_g1_stu_getnext, 4558 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4559 .phylink_get_caps = mv88e6351_phylink_get_caps, 4560 }; 4561 4562 static const struct mv88e6xxx_ops mv88e6172_ops = { 4563 /* MV88E6XXX_FAMILY_6352 */ 4564 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4565 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4566 .irl_init_all = mv88e6352_g2_irl_init_all, 4567 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4568 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4569 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4570 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4571 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4572 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4573 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4574 .port_set_link = mv88e6xxx_port_set_link, 4575 .port_sync_link = mv88e6xxx_port_sync_link, 4576 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4577 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4578 .port_tag_remap = mv88e6095_port_tag_remap, 4579 .port_set_policy = mv88e6352_port_set_policy, 4580 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4581 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4582 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4583 .port_set_ether_type = mv88e6351_port_set_ether_type, 4584 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4585 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4586 .port_pause_limit = mv88e6097_port_pause_limit, 4587 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4588 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4589 .port_get_cmode = mv88e6352_port_get_cmode, 4590 .port_setup_leds = mv88e6xxx_port_setup_leds, 4591 .port_setup_message_port = mv88e6xxx_setup_message_port, 4592 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4593 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4594 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4595 .stats_get_strings = mv88e6095_stats_get_strings, 4596 .stats_get_stat = mv88e6095_stats_get_stat, 4597 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4598 .set_egress_port = mv88e6095_g1_set_egress_port, 4599 .watchdog_ops = &mv88e6097_watchdog_ops, 4600 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4601 .pot_clear = mv88e6xxx_g2_pot_clear, 4602 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4603 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4604 .reset = mv88e6352_g1_reset, 4605 .rmu_disable = mv88e6352_g1_rmu_disable, 4606 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4607 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4608 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4609 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4610 .stu_getnext = mv88e6352_g1_stu_getnext, 4611 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4612 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4613 .serdes_get_regs = mv88e6352_serdes_get_regs, 4614 .gpio_ops = &mv88e6352_gpio_ops, 4615 .phylink_get_caps = mv88e6352_phylink_get_caps, 4616 .pcs_ops = &mv88e6352_pcs_ops, 4617 }; 4618 4619 static const struct mv88e6xxx_ops mv88e6175_ops = { 4620 /* MV88E6XXX_FAMILY_6351 */ 4621 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4622 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4623 .irl_init_all = mv88e6352_g2_irl_init_all, 4624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4625 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4626 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4627 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4628 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4629 .port_set_link = mv88e6xxx_port_set_link, 4630 .port_sync_link = mv88e6xxx_port_sync_link, 4631 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4632 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4633 .port_tag_remap = mv88e6095_port_tag_remap, 4634 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4635 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4636 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4637 .port_set_ether_type = mv88e6351_port_set_ether_type, 4638 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4639 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4640 .port_pause_limit = mv88e6097_port_pause_limit, 4641 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4642 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4643 .port_get_cmode = mv88e6352_port_get_cmode, 4644 .port_setup_message_port = mv88e6xxx_setup_message_port, 4645 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4646 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4647 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4648 .stats_get_strings = mv88e6095_stats_get_strings, 4649 .stats_get_stat = mv88e6095_stats_get_stat, 4650 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4651 .set_egress_port = mv88e6095_g1_set_egress_port, 4652 .watchdog_ops = &mv88e6097_watchdog_ops, 4653 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4654 .pot_clear = mv88e6xxx_g2_pot_clear, 4655 .reset = mv88e6352_g1_reset, 4656 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4657 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4658 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4660 .stu_getnext = mv88e6352_g1_stu_getnext, 4661 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4662 .phylink_get_caps = mv88e6351_phylink_get_caps, 4663 }; 4664 4665 static const struct mv88e6xxx_ops mv88e6176_ops = { 4666 /* MV88E6XXX_FAMILY_6352 */ 4667 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4668 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4669 .irl_init_all = mv88e6352_g2_irl_init_all, 4670 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4671 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4672 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4673 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4674 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4675 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4676 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4677 .port_set_link = mv88e6xxx_port_set_link, 4678 .port_sync_link = mv88e6xxx_port_sync_link, 4679 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4680 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4681 .port_tag_remap = mv88e6095_port_tag_remap, 4682 .port_set_policy = mv88e6352_port_set_policy, 4683 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4684 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4685 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4686 .port_set_ether_type = mv88e6351_port_set_ether_type, 4687 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4688 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4689 .port_pause_limit = mv88e6097_port_pause_limit, 4690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4692 .port_get_cmode = mv88e6352_port_get_cmode, 4693 .port_setup_leds = mv88e6xxx_port_setup_leds, 4694 .port_setup_message_port = mv88e6xxx_setup_message_port, 4695 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4696 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4697 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4698 .stats_get_strings = mv88e6095_stats_get_strings, 4699 .stats_get_stat = mv88e6095_stats_get_stat, 4700 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4701 .set_egress_port = mv88e6095_g1_set_egress_port, 4702 .watchdog_ops = &mv88e6097_watchdog_ops, 4703 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4704 .pot_clear = mv88e6xxx_g2_pot_clear, 4705 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4706 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4707 .reset = mv88e6352_g1_reset, 4708 .rmu_disable = mv88e6352_g1_rmu_disable, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4713 .stu_getnext = mv88e6352_g1_stu_getnext, 4714 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4715 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4716 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4717 .serdes_get_regs = mv88e6352_serdes_get_regs, 4718 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4719 .gpio_ops = &mv88e6352_gpio_ops, 4720 .phylink_get_caps = mv88e6352_phylink_get_caps, 4721 .pcs_ops = &mv88e6352_pcs_ops, 4722 }; 4723 4724 static const struct mv88e6xxx_ops mv88e6185_ops = { 4725 /* MV88E6XXX_FAMILY_6185 */ 4726 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4727 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4728 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4729 .phy_read = mv88e6185_phy_ppu_read, 4730 .phy_write = mv88e6185_phy_ppu_write, 4731 .port_set_link = mv88e6xxx_port_set_link, 4732 .port_sync_link = mv88e6185_port_sync_link, 4733 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4734 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4735 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4736 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4737 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4738 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4739 .port_set_pause = mv88e6185_port_set_pause, 4740 .port_get_cmode = mv88e6185_port_get_cmode, 4741 .port_setup_message_port = mv88e6xxx_setup_message_port, 4742 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4743 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4744 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4745 .stats_get_strings = mv88e6095_stats_get_strings, 4746 .stats_get_stat = mv88e6095_stats_get_stat, 4747 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4748 .set_egress_port = mv88e6095_g1_set_egress_port, 4749 .watchdog_ops = &mv88e6097_watchdog_ops, 4750 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4751 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4752 .ppu_enable = mv88e6185_g1_ppu_enable, 4753 .ppu_disable = mv88e6185_g1_ppu_disable, 4754 .reset = mv88e6185_g1_reset, 4755 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4756 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4757 .phylink_get_caps = mv88e6185_phylink_get_caps, 4758 .pcs_ops = &mv88e6185_pcs_ops, 4759 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4760 }; 4761 4762 static const struct mv88e6xxx_ops mv88e6190_ops = { 4763 /* MV88E6XXX_FAMILY_6390 */ 4764 .setup_errata = mv88e6390_setup_errata, 4765 .irl_init_all = mv88e6390_g2_irl_init_all, 4766 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4767 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4768 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4769 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4770 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4771 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4772 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4773 .port_set_link = mv88e6xxx_port_set_link, 4774 .port_sync_link = mv88e6xxx_port_sync_link, 4775 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4776 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4777 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4778 .port_tag_remap = mv88e6390_port_tag_remap, 4779 .port_set_policy = mv88e6352_port_set_policy, 4780 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4781 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4782 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4783 .port_set_ether_type = mv88e6351_port_set_ether_type, 4784 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4785 .port_pause_limit = mv88e6390_port_pause_limit, 4786 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4787 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4788 .port_get_cmode = mv88e6352_port_get_cmode, 4789 .port_set_cmode = mv88e6390_port_set_cmode, 4790 .port_setup_message_port = mv88e6xxx_setup_message_port, 4791 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4792 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4793 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4794 .stats_get_strings = mv88e6320_stats_get_strings, 4795 .stats_get_stat = mv88e6390_stats_get_stat, 4796 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4797 .set_egress_port = mv88e6390_g1_set_egress_port, 4798 .watchdog_ops = &mv88e6390_watchdog_ops, 4799 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4800 .pot_clear = mv88e6xxx_g2_pot_clear, 4801 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4802 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4803 .reset = mv88e6352_g1_reset, 4804 .rmu_disable = mv88e6390_g1_rmu_disable, 4805 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4806 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4807 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4808 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4809 .stu_getnext = mv88e6390_g1_stu_getnext, 4810 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4811 .serdes_get_lane = mv88e6390_serdes_get_lane, 4812 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4813 .serdes_get_strings = mv88e6390_serdes_get_strings, 4814 .serdes_get_stats = mv88e6390_serdes_get_stats, 4815 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4816 .serdes_get_regs = mv88e6390_serdes_get_regs, 4817 .gpio_ops = &mv88e6352_gpio_ops, 4818 .phylink_get_caps = mv88e6390_phylink_get_caps, 4819 .pcs_ops = &mv88e6390_pcs_ops, 4820 }; 4821 4822 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4823 /* MV88E6XXX_FAMILY_6390 */ 4824 .setup_errata = mv88e6390_setup_errata, 4825 .irl_init_all = mv88e6390_g2_irl_init_all, 4826 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4827 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4828 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4829 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4830 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4831 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4832 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4833 .port_set_link = mv88e6xxx_port_set_link, 4834 .port_sync_link = mv88e6xxx_port_sync_link, 4835 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4836 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4837 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4838 .port_tag_remap = mv88e6390_port_tag_remap, 4839 .port_set_policy = mv88e6352_port_set_policy, 4840 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4841 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4842 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4843 .port_set_ether_type = mv88e6351_port_set_ether_type, 4844 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4845 .port_pause_limit = mv88e6390_port_pause_limit, 4846 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4847 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4848 .port_get_cmode = mv88e6352_port_get_cmode, 4849 .port_set_cmode = mv88e6390x_port_set_cmode, 4850 .port_setup_message_port = mv88e6xxx_setup_message_port, 4851 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4852 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4853 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4854 .stats_get_strings = mv88e6320_stats_get_strings, 4855 .stats_get_stat = mv88e6390_stats_get_stat, 4856 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4857 .set_egress_port = mv88e6390_g1_set_egress_port, 4858 .watchdog_ops = &mv88e6390_watchdog_ops, 4859 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4860 .pot_clear = mv88e6xxx_g2_pot_clear, 4861 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4862 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4863 .reset = mv88e6352_g1_reset, 4864 .rmu_disable = mv88e6390_g1_rmu_disable, 4865 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4866 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4867 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4868 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4869 .stu_getnext = mv88e6390_g1_stu_getnext, 4870 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4871 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4872 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4873 .serdes_get_strings = mv88e6390_serdes_get_strings, 4874 .serdes_get_stats = mv88e6390_serdes_get_stats, 4875 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4876 .serdes_get_regs = mv88e6390_serdes_get_regs, 4877 .gpio_ops = &mv88e6352_gpio_ops, 4878 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4879 .pcs_ops = &mv88e6390_pcs_ops, 4880 }; 4881 4882 static const struct mv88e6xxx_ops mv88e6191_ops = { 4883 /* MV88E6XXX_FAMILY_6390 */ 4884 .setup_errata = mv88e6390_setup_errata, 4885 .irl_init_all = mv88e6390_g2_irl_init_all, 4886 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4887 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4888 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4889 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4890 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4891 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4892 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4893 .port_set_link = mv88e6xxx_port_set_link, 4894 .port_sync_link = mv88e6xxx_port_sync_link, 4895 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4896 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4897 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4898 .port_tag_remap = mv88e6390_port_tag_remap, 4899 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4900 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4901 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4902 .port_set_ether_type = mv88e6351_port_set_ether_type, 4903 .port_pause_limit = mv88e6390_port_pause_limit, 4904 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4905 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4906 .port_get_cmode = mv88e6352_port_get_cmode, 4907 .port_set_cmode = mv88e6390_port_set_cmode, 4908 .port_setup_message_port = mv88e6xxx_setup_message_port, 4909 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4910 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4911 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4912 .stats_get_strings = mv88e6320_stats_get_strings, 4913 .stats_get_stat = mv88e6390_stats_get_stat, 4914 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4915 .set_egress_port = mv88e6390_g1_set_egress_port, 4916 .watchdog_ops = &mv88e6390_watchdog_ops, 4917 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4918 .pot_clear = mv88e6xxx_g2_pot_clear, 4919 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4920 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4921 .reset = mv88e6352_g1_reset, 4922 .rmu_disable = mv88e6390_g1_rmu_disable, 4923 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4924 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4925 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4926 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4927 .stu_getnext = mv88e6390_g1_stu_getnext, 4928 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4929 .serdes_get_lane = mv88e6390_serdes_get_lane, 4930 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4931 .serdes_get_strings = mv88e6390_serdes_get_strings, 4932 .serdes_get_stats = mv88e6390_serdes_get_stats, 4933 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4934 .serdes_get_regs = mv88e6390_serdes_get_regs, 4935 .avb_ops = &mv88e6390_avb_ops, 4936 .ptp_ops = &mv88e6352_ptp_ops, 4937 .phylink_get_caps = mv88e6390_phylink_get_caps, 4938 .pcs_ops = &mv88e6390_pcs_ops, 4939 }; 4940 4941 static const struct mv88e6xxx_ops mv88e6240_ops = { 4942 /* MV88E6XXX_FAMILY_6352 */ 4943 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4944 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4945 .irl_init_all = mv88e6352_g2_irl_init_all, 4946 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4947 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4949 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4950 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4951 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4952 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4953 .port_set_link = mv88e6xxx_port_set_link, 4954 .port_sync_link = mv88e6xxx_port_sync_link, 4955 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4956 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4957 .port_tag_remap = mv88e6095_port_tag_remap, 4958 .port_set_policy = mv88e6352_port_set_policy, 4959 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4960 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4961 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4962 .port_set_ether_type = mv88e6351_port_set_ether_type, 4963 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4964 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4965 .port_pause_limit = mv88e6097_port_pause_limit, 4966 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4967 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4968 .port_get_cmode = mv88e6352_port_get_cmode, 4969 .port_setup_leds = mv88e6xxx_port_setup_leds, 4970 .port_setup_message_port = mv88e6xxx_setup_message_port, 4971 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4972 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4973 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4974 .stats_get_strings = mv88e6095_stats_get_strings, 4975 .stats_get_stat = mv88e6095_stats_get_stat, 4976 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4977 .set_egress_port = mv88e6095_g1_set_egress_port, 4978 .watchdog_ops = &mv88e6097_watchdog_ops, 4979 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4980 .pot_clear = mv88e6xxx_g2_pot_clear, 4981 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4982 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4983 .reset = mv88e6352_g1_reset, 4984 .rmu_disable = mv88e6352_g1_rmu_disable, 4985 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4986 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4987 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4988 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4989 .stu_getnext = mv88e6352_g1_stu_getnext, 4990 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4991 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4992 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4993 .serdes_get_regs = mv88e6352_serdes_get_regs, 4994 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4995 .gpio_ops = &mv88e6352_gpio_ops, 4996 .avb_ops = &mv88e6352_avb_ops, 4997 .ptp_ops = &mv88e6352_ptp_ops, 4998 .phylink_get_caps = mv88e6352_phylink_get_caps, 4999 .pcs_ops = &mv88e6352_pcs_ops, 5000 }; 5001 5002 static const struct mv88e6xxx_ops mv88e6250_ops = { 5003 /* MV88E6XXX_FAMILY_6250 */ 5004 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5005 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5006 .irl_init_all = mv88e6352_g2_irl_init_all, 5007 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5008 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5009 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5010 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5011 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5012 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5013 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5014 .port_set_link = mv88e6xxx_port_set_link, 5015 .port_sync_link = mv88e6xxx_port_sync_link, 5016 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5017 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5018 .port_tag_remap = mv88e6095_port_tag_remap, 5019 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5020 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5021 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5022 .port_set_ether_type = mv88e6351_port_set_ether_type, 5023 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5024 .port_pause_limit = mv88e6097_port_pause_limit, 5025 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5026 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5027 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5028 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5029 .stats_get_strings = mv88e6250_stats_get_strings, 5030 .stats_get_stat = mv88e6250_stats_get_stat, 5031 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5032 .set_egress_port = mv88e6095_g1_set_egress_port, 5033 .watchdog_ops = &mv88e6250_watchdog_ops, 5034 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5035 .pot_clear = mv88e6xxx_g2_pot_clear, 5036 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5037 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5038 .reset = mv88e6250_g1_reset, 5039 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5040 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5041 .avb_ops = &mv88e6352_avb_ops, 5042 .ptp_ops = &mv88e6250_ptp_ops, 5043 .phylink_get_caps = mv88e6250_phylink_get_caps, 5044 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5045 }; 5046 5047 static const struct mv88e6xxx_ops mv88e6290_ops = { 5048 /* MV88E6XXX_FAMILY_6390 */ 5049 .setup_errata = mv88e6390_setup_errata, 5050 .irl_init_all = mv88e6390_g2_irl_init_all, 5051 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5052 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5053 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5054 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5055 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5056 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5057 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5058 .port_set_link = mv88e6xxx_port_set_link, 5059 .port_sync_link = mv88e6xxx_port_sync_link, 5060 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5061 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5062 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5063 .port_tag_remap = mv88e6390_port_tag_remap, 5064 .port_set_policy = mv88e6352_port_set_policy, 5065 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5066 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5067 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5068 .port_set_ether_type = mv88e6351_port_set_ether_type, 5069 .port_pause_limit = mv88e6390_port_pause_limit, 5070 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5071 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5072 .port_get_cmode = mv88e6352_port_get_cmode, 5073 .port_set_cmode = mv88e6390_port_set_cmode, 5074 .port_setup_message_port = mv88e6xxx_setup_message_port, 5075 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5076 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5077 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5078 .stats_get_strings = mv88e6320_stats_get_strings, 5079 .stats_get_stat = mv88e6390_stats_get_stat, 5080 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5081 .set_egress_port = mv88e6390_g1_set_egress_port, 5082 .watchdog_ops = &mv88e6390_watchdog_ops, 5083 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5084 .pot_clear = mv88e6xxx_g2_pot_clear, 5085 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5086 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5087 .reset = mv88e6352_g1_reset, 5088 .rmu_disable = mv88e6390_g1_rmu_disable, 5089 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5090 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5091 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5092 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5093 .stu_getnext = mv88e6390_g1_stu_getnext, 5094 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5095 .serdes_get_lane = mv88e6390_serdes_get_lane, 5096 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5097 .serdes_get_strings = mv88e6390_serdes_get_strings, 5098 .serdes_get_stats = mv88e6390_serdes_get_stats, 5099 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5100 .serdes_get_regs = mv88e6390_serdes_get_regs, 5101 .gpio_ops = &mv88e6352_gpio_ops, 5102 .avb_ops = &mv88e6390_avb_ops, 5103 .ptp_ops = &mv88e6390_ptp_ops, 5104 .phylink_get_caps = mv88e6390_phylink_get_caps, 5105 .pcs_ops = &mv88e6390_pcs_ops, 5106 }; 5107 5108 static const struct mv88e6xxx_ops mv88e6320_ops = { 5109 /* MV88E6XXX_FAMILY_6320 */ 5110 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5111 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5112 .irl_init_all = mv88e6352_g2_irl_init_all, 5113 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5114 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5115 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5116 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5117 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5118 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5119 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5120 .port_set_link = mv88e6xxx_port_set_link, 5121 .port_sync_link = mv88e6xxx_port_sync_link, 5122 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5123 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5124 .port_tag_remap = mv88e6095_port_tag_remap, 5125 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5126 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5127 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5128 .port_set_ether_type = mv88e6351_port_set_ether_type, 5129 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5130 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5131 .port_pause_limit = mv88e6097_port_pause_limit, 5132 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5133 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5134 .port_get_cmode = mv88e6352_port_get_cmode, 5135 .port_setup_message_port = mv88e6xxx_setup_message_port, 5136 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5137 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5138 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5139 .stats_get_strings = mv88e6320_stats_get_strings, 5140 .stats_get_stat = mv88e6320_stats_get_stat, 5141 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5142 .set_egress_port = mv88e6095_g1_set_egress_port, 5143 .watchdog_ops = &mv88e6390_watchdog_ops, 5144 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5145 .pot_clear = mv88e6xxx_g2_pot_clear, 5146 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5147 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5148 .reset = mv88e6352_g1_reset, 5149 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5150 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5151 .gpio_ops = &mv88e6352_gpio_ops, 5152 .avb_ops = &mv88e6352_avb_ops, 5153 .ptp_ops = &mv88e6352_ptp_ops, 5154 .phylink_get_caps = mv88e632x_phylink_get_caps, 5155 }; 5156 5157 static const struct mv88e6xxx_ops mv88e6321_ops = { 5158 /* MV88E6XXX_FAMILY_6320 */ 5159 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5160 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5161 .irl_init_all = mv88e6352_g2_irl_init_all, 5162 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5163 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5164 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5165 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5166 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5167 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5168 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5169 .port_set_link = mv88e6xxx_port_set_link, 5170 .port_sync_link = mv88e6xxx_port_sync_link, 5171 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5172 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5173 .port_tag_remap = mv88e6095_port_tag_remap, 5174 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5175 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5176 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5177 .port_set_ether_type = mv88e6351_port_set_ether_type, 5178 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5179 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5180 .port_pause_limit = mv88e6097_port_pause_limit, 5181 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5182 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5183 .port_get_cmode = mv88e6352_port_get_cmode, 5184 .port_setup_message_port = mv88e6xxx_setup_message_port, 5185 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5186 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5187 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5188 .stats_get_strings = mv88e6320_stats_get_strings, 5189 .stats_get_stat = mv88e6320_stats_get_stat, 5190 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5191 .set_egress_port = mv88e6095_g1_set_egress_port, 5192 .watchdog_ops = &mv88e6390_watchdog_ops, 5193 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5194 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5195 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5196 .reset = mv88e6352_g1_reset, 5197 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5198 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5199 .gpio_ops = &mv88e6352_gpio_ops, 5200 .avb_ops = &mv88e6352_avb_ops, 5201 .ptp_ops = &mv88e6352_ptp_ops, 5202 .phylink_get_caps = mv88e632x_phylink_get_caps, 5203 }; 5204 5205 static const struct mv88e6xxx_ops mv88e6341_ops = { 5206 /* MV88E6XXX_FAMILY_6341 */ 5207 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5208 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5209 .irl_init_all = mv88e6352_g2_irl_init_all, 5210 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5211 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5212 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5213 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5214 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5215 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5216 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5217 .port_set_link = mv88e6xxx_port_set_link, 5218 .port_sync_link = mv88e6xxx_port_sync_link, 5219 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5220 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5221 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5222 .port_tag_remap = mv88e6095_port_tag_remap, 5223 .port_set_policy = mv88e6352_port_set_policy, 5224 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5225 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5226 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5227 .port_set_ether_type = mv88e6351_port_set_ether_type, 5228 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5229 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5230 .port_pause_limit = mv88e6097_port_pause_limit, 5231 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5232 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5233 .port_get_cmode = mv88e6352_port_get_cmode, 5234 .port_set_cmode = mv88e6341_port_set_cmode, 5235 .port_setup_message_port = mv88e6xxx_setup_message_port, 5236 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5237 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5238 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5239 .stats_get_strings = mv88e6320_stats_get_strings, 5240 .stats_get_stat = mv88e6390_stats_get_stat, 5241 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5242 .set_egress_port = mv88e6390_g1_set_egress_port, 5243 .watchdog_ops = &mv88e6390_watchdog_ops, 5244 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5245 .pot_clear = mv88e6xxx_g2_pot_clear, 5246 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5247 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5248 .reset = mv88e6352_g1_reset, 5249 .rmu_disable = mv88e6390_g1_rmu_disable, 5250 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5251 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5252 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5253 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5254 .stu_getnext = mv88e6352_g1_stu_getnext, 5255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5256 .serdes_get_lane = mv88e6341_serdes_get_lane, 5257 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5258 .gpio_ops = &mv88e6352_gpio_ops, 5259 .avb_ops = &mv88e6390_avb_ops, 5260 .ptp_ops = &mv88e6352_ptp_ops, 5261 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5262 .serdes_get_strings = mv88e6390_serdes_get_strings, 5263 .serdes_get_stats = mv88e6390_serdes_get_stats, 5264 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5265 .serdes_get_regs = mv88e6390_serdes_get_regs, 5266 .phylink_get_caps = mv88e6341_phylink_get_caps, 5267 .pcs_ops = &mv88e6390_pcs_ops, 5268 }; 5269 5270 static const struct mv88e6xxx_ops mv88e6350_ops = { 5271 /* MV88E6XXX_FAMILY_6351 */ 5272 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5273 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5274 .irl_init_all = mv88e6352_g2_irl_init_all, 5275 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5276 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5277 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5278 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5279 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5280 .port_set_link = mv88e6xxx_port_set_link, 5281 .port_sync_link = mv88e6xxx_port_sync_link, 5282 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5283 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5284 .port_tag_remap = mv88e6095_port_tag_remap, 5285 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5286 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5287 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5288 .port_set_ether_type = mv88e6351_port_set_ether_type, 5289 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5290 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5291 .port_pause_limit = mv88e6097_port_pause_limit, 5292 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5293 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5294 .port_get_cmode = mv88e6352_port_get_cmode, 5295 .port_setup_message_port = mv88e6xxx_setup_message_port, 5296 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5297 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5298 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5299 .stats_get_strings = mv88e6095_stats_get_strings, 5300 .stats_get_stat = mv88e6095_stats_get_stat, 5301 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5302 .set_egress_port = mv88e6095_g1_set_egress_port, 5303 .watchdog_ops = &mv88e6097_watchdog_ops, 5304 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5305 .pot_clear = mv88e6xxx_g2_pot_clear, 5306 .reset = mv88e6352_g1_reset, 5307 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5308 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5309 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5310 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5311 .stu_getnext = mv88e6352_g1_stu_getnext, 5312 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5313 .phylink_get_caps = mv88e6351_phylink_get_caps, 5314 }; 5315 5316 static const struct mv88e6xxx_ops mv88e6351_ops = { 5317 /* MV88E6XXX_FAMILY_6351 */ 5318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5319 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5320 .irl_init_all = mv88e6352_g2_irl_init_all, 5321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5322 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5323 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5324 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5325 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5326 .port_set_link = mv88e6xxx_port_set_link, 5327 .port_sync_link = mv88e6xxx_port_sync_link, 5328 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5329 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5330 .port_tag_remap = mv88e6095_port_tag_remap, 5331 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5332 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5333 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5334 .port_set_ether_type = mv88e6351_port_set_ether_type, 5335 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5336 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5337 .port_pause_limit = mv88e6097_port_pause_limit, 5338 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5339 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5340 .port_get_cmode = mv88e6352_port_get_cmode, 5341 .port_setup_message_port = mv88e6xxx_setup_message_port, 5342 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5343 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5344 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5345 .stats_get_strings = mv88e6095_stats_get_strings, 5346 .stats_get_stat = mv88e6095_stats_get_stat, 5347 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5348 .set_egress_port = mv88e6095_g1_set_egress_port, 5349 .watchdog_ops = &mv88e6097_watchdog_ops, 5350 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5351 .pot_clear = mv88e6xxx_g2_pot_clear, 5352 .reset = mv88e6352_g1_reset, 5353 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5354 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5355 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5357 .stu_getnext = mv88e6352_g1_stu_getnext, 5358 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5359 .avb_ops = &mv88e6352_avb_ops, 5360 .ptp_ops = &mv88e6352_ptp_ops, 5361 .phylink_get_caps = mv88e6351_phylink_get_caps, 5362 }; 5363 5364 static const struct mv88e6xxx_ops mv88e6352_ops = { 5365 /* MV88E6XXX_FAMILY_6352 */ 5366 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5367 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5368 .irl_init_all = mv88e6352_g2_irl_init_all, 5369 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5370 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5371 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5372 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5373 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5374 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5375 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5376 .port_set_link = mv88e6xxx_port_set_link, 5377 .port_sync_link = mv88e6xxx_port_sync_link, 5378 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5379 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5380 .port_tag_remap = mv88e6095_port_tag_remap, 5381 .port_set_policy = mv88e6352_port_set_policy, 5382 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5383 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5384 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5385 .port_set_ether_type = mv88e6351_port_set_ether_type, 5386 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5388 .port_pause_limit = mv88e6097_port_pause_limit, 5389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5391 .port_get_cmode = mv88e6352_port_get_cmode, 5392 .port_setup_leds = mv88e6xxx_port_setup_leds, 5393 .port_setup_message_port = mv88e6xxx_setup_message_port, 5394 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5395 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5396 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5397 .stats_get_strings = mv88e6095_stats_get_strings, 5398 .stats_get_stat = mv88e6095_stats_get_stat, 5399 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5400 .set_egress_port = mv88e6095_g1_set_egress_port, 5401 .watchdog_ops = &mv88e6097_watchdog_ops, 5402 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5403 .pot_clear = mv88e6xxx_g2_pot_clear, 5404 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5405 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5406 .reset = mv88e6352_g1_reset, 5407 .rmu_disable = mv88e6352_g1_rmu_disable, 5408 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5409 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5410 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5411 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5412 .stu_getnext = mv88e6352_g1_stu_getnext, 5413 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5414 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5415 .gpio_ops = &mv88e6352_gpio_ops, 5416 .avb_ops = &mv88e6352_avb_ops, 5417 .ptp_ops = &mv88e6352_ptp_ops, 5418 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5419 .serdes_get_strings = mv88e6352_serdes_get_strings, 5420 .serdes_get_stats = mv88e6352_serdes_get_stats, 5421 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5422 .serdes_get_regs = mv88e6352_serdes_get_regs, 5423 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5424 .phylink_get_caps = mv88e6352_phylink_get_caps, 5425 .pcs_ops = &mv88e6352_pcs_ops, 5426 }; 5427 5428 static const struct mv88e6xxx_ops mv88e6390_ops = { 5429 /* MV88E6XXX_FAMILY_6390 */ 5430 .setup_errata = mv88e6390_setup_errata, 5431 .irl_init_all = mv88e6390_g2_irl_init_all, 5432 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5433 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5434 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5435 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5436 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5437 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5438 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5439 .port_set_link = mv88e6xxx_port_set_link, 5440 .port_sync_link = mv88e6xxx_port_sync_link, 5441 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5442 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5443 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5444 .port_tag_remap = mv88e6390_port_tag_remap, 5445 .port_set_policy = mv88e6352_port_set_policy, 5446 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5447 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5448 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5449 .port_set_ether_type = mv88e6351_port_set_ether_type, 5450 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5451 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5452 .port_pause_limit = mv88e6390_port_pause_limit, 5453 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5454 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5455 .port_get_cmode = mv88e6352_port_get_cmode, 5456 .port_set_cmode = mv88e6390_port_set_cmode, 5457 .port_setup_message_port = mv88e6xxx_setup_message_port, 5458 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5459 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5460 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5461 .stats_get_strings = mv88e6320_stats_get_strings, 5462 .stats_get_stat = mv88e6390_stats_get_stat, 5463 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5464 .set_egress_port = mv88e6390_g1_set_egress_port, 5465 .watchdog_ops = &mv88e6390_watchdog_ops, 5466 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5467 .pot_clear = mv88e6xxx_g2_pot_clear, 5468 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5469 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5470 .reset = mv88e6352_g1_reset, 5471 .rmu_disable = mv88e6390_g1_rmu_disable, 5472 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5473 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5474 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5475 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5476 .stu_getnext = mv88e6390_g1_stu_getnext, 5477 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5478 .serdes_get_lane = mv88e6390_serdes_get_lane, 5479 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5480 .gpio_ops = &mv88e6352_gpio_ops, 5481 .avb_ops = &mv88e6390_avb_ops, 5482 .ptp_ops = &mv88e6390_ptp_ops, 5483 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5484 .serdes_get_strings = mv88e6390_serdes_get_strings, 5485 .serdes_get_stats = mv88e6390_serdes_get_stats, 5486 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5487 .serdes_get_regs = mv88e6390_serdes_get_regs, 5488 .phylink_get_caps = mv88e6390_phylink_get_caps, 5489 .pcs_ops = &mv88e6390_pcs_ops, 5490 }; 5491 5492 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5493 /* MV88E6XXX_FAMILY_6390 */ 5494 .setup_errata = mv88e6390_setup_errata, 5495 .irl_init_all = mv88e6390_g2_irl_init_all, 5496 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5497 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5499 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5500 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5501 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5502 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5503 .port_set_link = mv88e6xxx_port_set_link, 5504 .port_sync_link = mv88e6xxx_port_sync_link, 5505 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5506 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5507 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5508 .port_tag_remap = mv88e6390_port_tag_remap, 5509 .port_set_policy = mv88e6352_port_set_policy, 5510 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5511 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5512 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5513 .port_set_ether_type = mv88e6351_port_set_ether_type, 5514 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5515 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5516 .port_pause_limit = mv88e6390_port_pause_limit, 5517 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5518 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5519 .port_get_cmode = mv88e6352_port_get_cmode, 5520 .port_set_cmode = mv88e6390x_port_set_cmode, 5521 .port_setup_message_port = mv88e6xxx_setup_message_port, 5522 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5523 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5524 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5525 .stats_get_strings = mv88e6320_stats_get_strings, 5526 .stats_get_stat = mv88e6390_stats_get_stat, 5527 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5528 .set_egress_port = mv88e6390_g1_set_egress_port, 5529 .watchdog_ops = &mv88e6390_watchdog_ops, 5530 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5531 .pot_clear = mv88e6xxx_g2_pot_clear, 5532 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5533 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5534 .reset = mv88e6352_g1_reset, 5535 .rmu_disable = mv88e6390_g1_rmu_disable, 5536 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5537 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5538 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5539 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5540 .stu_getnext = mv88e6390_g1_stu_getnext, 5541 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5542 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5543 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5544 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5545 .serdes_get_strings = mv88e6390_serdes_get_strings, 5546 .serdes_get_stats = mv88e6390_serdes_get_stats, 5547 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5548 .serdes_get_regs = mv88e6390_serdes_get_regs, 5549 .gpio_ops = &mv88e6352_gpio_ops, 5550 .avb_ops = &mv88e6390_avb_ops, 5551 .ptp_ops = &mv88e6390_ptp_ops, 5552 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5553 .pcs_ops = &mv88e6390_pcs_ops, 5554 }; 5555 5556 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5557 /* MV88E6XXX_FAMILY_6393 */ 5558 .irl_init_all = mv88e6390_g2_irl_init_all, 5559 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5560 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5561 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5562 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5563 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5564 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5565 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5566 .port_set_link = mv88e6xxx_port_set_link, 5567 .port_sync_link = mv88e6xxx_port_sync_link, 5568 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5569 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5570 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5571 .port_tag_remap = mv88e6390_port_tag_remap, 5572 .port_set_policy = mv88e6393x_port_set_policy, 5573 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5574 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5575 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5576 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5577 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5578 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5579 .port_pause_limit = mv88e6390_port_pause_limit, 5580 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5581 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5582 .port_get_cmode = mv88e6352_port_get_cmode, 5583 .port_set_cmode = mv88e6393x_port_set_cmode, 5584 .port_setup_message_port = mv88e6xxx_setup_message_port, 5585 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5586 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5587 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5588 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5589 .stats_get_strings = mv88e6320_stats_get_strings, 5590 .stats_get_stat = mv88e6390_stats_get_stat, 5591 /* .set_cpu_port is missing because this family does not support a global 5592 * CPU port, only per port CPU port which is set via 5593 * .port_set_upstream_port method. 5594 */ 5595 .set_egress_port = mv88e6393x_set_egress_port, 5596 .watchdog_ops = &mv88e6393x_watchdog_ops, 5597 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5598 .pot_clear = mv88e6xxx_g2_pot_clear, 5599 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5600 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5601 .reset = mv88e6352_g1_reset, 5602 .rmu_disable = mv88e6390_g1_rmu_disable, 5603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5605 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5606 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5607 .stu_getnext = mv88e6390_g1_stu_getnext, 5608 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5609 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5610 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5611 /* TODO: serdes stats */ 5612 .gpio_ops = &mv88e6352_gpio_ops, 5613 .avb_ops = &mv88e6390_avb_ops, 5614 .ptp_ops = &mv88e6352_ptp_ops, 5615 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5616 .pcs_ops = &mv88e6393x_pcs_ops, 5617 }; 5618 5619 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5620 [MV88E6020] = { 5621 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5622 .family = MV88E6XXX_FAMILY_6250, 5623 .name = "Marvell 88E6020", 5624 .num_databases = 64, 5625 /* Ports 2-4 are not routed to pins 5626 * => usable ports 0, 1, 5, 6 5627 */ 5628 .num_ports = 7, 5629 .num_internal_phys = 2, 5630 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5631 .max_vid = 4095, 5632 .port_base_addr = 0x8, 5633 .phy_base_addr = 0x0, 5634 .global1_addr = 0xf, 5635 .global2_addr = 0x7, 5636 .age_time_coeff = 15000, 5637 .g1_irqs = 9, 5638 .g2_irqs = 5, 5639 .stats_type = STATS_TYPE_BANK0, 5640 .atu_move_port_mask = 0xf, 5641 .dual_chip = true, 5642 .ops = &mv88e6250_ops, 5643 }, 5644 5645 [MV88E6071] = { 5646 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5647 .family = MV88E6XXX_FAMILY_6250, 5648 .name = "Marvell 88E6071", 5649 .num_databases = 64, 5650 .num_ports = 7, 5651 .num_internal_phys = 5, 5652 .max_vid = 4095, 5653 .port_base_addr = 0x08, 5654 .phy_base_addr = 0x00, 5655 .global1_addr = 0x0f, 5656 .global2_addr = 0x07, 5657 .age_time_coeff = 15000, 5658 .g1_irqs = 9, 5659 .g2_irqs = 5, 5660 .stats_type = STATS_TYPE_BANK0, 5661 .atu_move_port_mask = 0xf, 5662 .dual_chip = true, 5663 .ops = &mv88e6250_ops, 5664 }, 5665 5666 [MV88E6085] = { 5667 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5668 .family = MV88E6XXX_FAMILY_6097, 5669 .name = "Marvell 88E6085", 5670 .num_databases = 4096, 5671 .num_macs = 8192, 5672 .num_ports = 10, 5673 .num_internal_phys = 5, 5674 .max_vid = 4095, 5675 .max_sid = 63, 5676 .port_base_addr = 0x10, 5677 .phy_base_addr = 0x0, 5678 .global1_addr = 0x1b, 5679 .global2_addr = 0x1c, 5680 .age_time_coeff = 15000, 5681 .g1_irqs = 8, 5682 .g2_irqs = 10, 5683 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5684 .atu_move_port_mask = 0xf, 5685 .pvt = true, 5686 .multi_chip = true, 5687 .ops = &mv88e6085_ops, 5688 }, 5689 5690 [MV88E6095] = { 5691 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5692 .family = MV88E6XXX_FAMILY_6095, 5693 .name = "Marvell 88E6095/88E6095F", 5694 .num_databases = 256, 5695 .num_macs = 8192, 5696 .num_ports = 11, 5697 .num_internal_phys = 0, 5698 .max_vid = 4095, 5699 .port_base_addr = 0x10, 5700 .phy_base_addr = 0x0, 5701 .global1_addr = 0x1b, 5702 .global2_addr = 0x1c, 5703 .age_time_coeff = 15000, 5704 .g1_irqs = 8, 5705 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5706 .atu_move_port_mask = 0xf, 5707 .multi_chip = true, 5708 .ops = &mv88e6095_ops, 5709 }, 5710 5711 [MV88E6097] = { 5712 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5713 .family = MV88E6XXX_FAMILY_6097, 5714 .name = "Marvell 88E6097/88E6097F", 5715 .num_databases = 4096, 5716 .num_macs = 8192, 5717 .num_ports = 11, 5718 .num_internal_phys = 8, 5719 .max_vid = 4095, 5720 .max_sid = 63, 5721 .port_base_addr = 0x10, 5722 .phy_base_addr = 0x0, 5723 .global1_addr = 0x1b, 5724 .global2_addr = 0x1c, 5725 .age_time_coeff = 15000, 5726 .g1_irqs = 8, 5727 .g2_irqs = 10, 5728 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5729 .atu_move_port_mask = 0xf, 5730 .pvt = true, 5731 .multi_chip = true, 5732 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5733 .ops = &mv88e6097_ops, 5734 }, 5735 5736 [MV88E6123] = { 5737 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5738 .family = MV88E6XXX_FAMILY_6165, 5739 .name = "Marvell 88E6123", 5740 .num_databases = 4096, 5741 .num_macs = 1024, 5742 .num_ports = 3, 5743 .num_internal_phys = 5, 5744 .max_vid = 4095, 5745 .max_sid = 63, 5746 .port_base_addr = 0x10, 5747 .phy_base_addr = 0x0, 5748 .global1_addr = 0x1b, 5749 .global2_addr = 0x1c, 5750 .age_time_coeff = 15000, 5751 .g1_irqs = 9, 5752 .g2_irqs = 10, 5753 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5754 .atu_move_port_mask = 0xf, 5755 .pvt = true, 5756 .multi_chip = true, 5757 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5758 .ops = &mv88e6123_ops, 5759 }, 5760 5761 [MV88E6131] = { 5762 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5763 .family = MV88E6XXX_FAMILY_6185, 5764 .name = "Marvell 88E6131", 5765 .num_databases = 256, 5766 .num_macs = 8192, 5767 .num_ports = 8, 5768 .num_internal_phys = 0, 5769 .max_vid = 4095, 5770 .port_base_addr = 0x10, 5771 .phy_base_addr = 0x0, 5772 .global1_addr = 0x1b, 5773 .global2_addr = 0x1c, 5774 .age_time_coeff = 15000, 5775 .g1_irqs = 9, 5776 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5777 .atu_move_port_mask = 0xf, 5778 .multi_chip = true, 5779 .ops = &mv88e6131_ops, 5780 }, 5781 5782 [MV88E6141] = { 5783 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5784 .family = MV88E6XXX_FAMILY_6341, 5785 .name = "Marvell 88E6141", 5786 .num_databases = 256, 5787 .num_macs = 2048, 5788 .num_ports = 6, 5789 .num_internal_phys = 5, 5790 .num_gpio = 11, 5791 .max_vid = 4095, 5792 .max_sid = 63, 5793 .port_base_addr = 0x10, 5794 .phy_base_addr = 0x10, 5795 .global1_addr = 0x1b, 5796 .global2_addr = 0x1c, 5797 .age_time_coeff = 3750, 5798 .atu_move_port_mask = 0x1f, 5799 .g1_irqs = 9, 5800 .g2_irqs = 10, 5801 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5802 .pvt = true, 5803 .multi_chip = true, 5804 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5805 .ops = &mv88e6141_ops, 5806 }, 5807 5808 [MV88E6161] = { 5809 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5810 .family = MV88E6XXX_FAMILY_6165, 5811 .name = "Marvell 88E6161", 5812 .num_databases = 4096, 5813 .num_macs = 1024, 5814 .num_ports = 6, 5815 .num_internal_phys = 5, 5816 .max_vid = 4095, 5817 .max_sid = 63, 5818 .port_base_addr = 0x10, 5819 .phy_base_addr = 0x0, 5820 .global1_addr = 0x1b, 5821 .global2_addr = 0x1c, 5822 .age_time_coeff = 15000, 5823 .g1_irqs = 9, 5824 .g2_irqs = 10, 5825 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5826 .atu_move_port_mask = 0xf, 5827 .pvt = true, 5828 .multi_chip = true, 5829 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5830 .ptp_support = true, 5831 .ops = &mv88e6161_ops, 5832 }, 5833 5834 [MV88E6165] = { 5835 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5836 .family = MV88E6XXX_FAMILY_6165, 5837 .name = "Marvell 88E6165", 5838 .num_databases = 4096, 5839 .num_macs = 8192, 5840 .num_ports = 6, 5841 .num_internal_phys = 0, 5842 .max_vid = 4095, 5843 .max_sid = 63, 5844 .port_base_addr = 0x10, 5845 .phy_base_addr = 0x0, 5846 .global1_addr = 0x1b, 5847 .global2_addr = 0x1c, 5848 .age_time_coeff = 15000, 5849 .g1_irqs = 9, 5850 .g2_irqs = 10, 5851 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5852 .atu_move_port_mask = 0xf, 5853 .pvt = true, 5854 .multi_chip = true, 5855 .ptp_support = true, 5856 .ops = &mv88e6165_ops, 5857 }, 5858 5859 [MV88E6171] = { 5860 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5861 .family = MV88E6XXX_FAMILY_6351, 5862 .name = "Marvell 88E6171", 5863 .num_databases = 4096, 5864 .num_macs = 8192, 5865 .num_ports = 7, 5866 .num_internal_phys = 5, 5867 .max_vid = 4095, 5868 .max_sid = 63, 5869 .port_base_addr = 0x10, 5870 .phy_base_addr = 0x0, 5871 .global1_addr = 0x1b, 5872 .global2_addr = 0x1c, 5873 .age_time_coeff = 15000, 5874 .g1_irqs = 9, 5875 .g2_irqs = 10, 5876 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5877 .atu_move_port_mask = 0xf, 5878 .pvt = true, 5879 .multi_chip = true, 5880 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5881 .ops = &mv88e6171_ops, 5882 }, 5883 5884 [MV88E6172] = { 5885 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5886 .family = MV88E6XXX_FAMILY_6352, 5887 .name = "Marvell 88E6172", 5888 .num_databases = 4096, 5889 .num_macs = 8192, 5890 .num_ports = 7, 5891 .num_internal_phys = 5, 5892 .num_gpio = 15, 5893 .max_vid = 4095, 5894 .max_sid = 63, 5895 .port_base_addr = 0x10, 5896 .phy_base_addr = 0x0, 5897 .global1_addr = 0x1b, 5898 .global2_addr = 0x1c, 5899 .age_time_coeff = 15000, 5900 .g1_irqs = 9, 5901 .g2_irqs = 10, 5902 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5903 .atu_move_port_mask = 0xf, 5904 .pvt = true, 5905 .multi_chip = true, 5906 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5907 .ops = &mv88e6172_ops, 5908 }, 5909 5910 [MV88E6175] = { 5911 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5912 .family = MV88E6XXX_FAMILY_6351, 5913 .name = "Marvell 88E6175", 5914 .num_databases = 4096, 5915 .num_macs = 8192, 5916 .num_ports = 7, 5917 .num_internal_phys = 5, 5918 .max_vid = 4095, 5919 .max_sid = 63, 5920 .port_base_addr = 0x10, 5921 .phy_base_addr = 0x0, 5922 .global1_addr = 0x1b, 5923 .global2_addr = 0x1c, 5924 .age_time_coeff = 15000, 5925 .g1_irqs = 9, 5926 .g2_irqs = 10, 5927 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5928 .atu_move_port_mask = 0xf, 5929 .pvt = true, 5930 .multi_chip = true, 5931 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5932 .ops = &mv88e6175_ops, 5933 }, 5934 5935 [MV88E6176] = { 5936 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5937 .family = MV88E6XXX_FAMILY_6352, 5938 .name = "Marvell 88E6176", 5939 .num_databases = 4096, 5940 .num_macs = 8192, 5941 .num_ports = 7, 5942 .num_internal_phys = 5, 5943 .num_gpio = 15, 5944 .max_vid = 4095, 5945 .max_sid = 63, 5946 .port_base_addr = 0x10, 5947 .phy_base_addr = 0x0, 5948 .global1_addr = 0x1b, 5949 .global2_addr = 0x1c, 5950 .age_time_coeff = 15000, 5951 .g1_irqs = 9, 5952 .g2_irqs = 10, 5953 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5954 .atu_move_port_mask = 0xf, 5955 .pvt = true, 5956 .multi_chip = true, 5957 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5958 .ops = &mv88e6176_ops, 5959 }, 5960 5961 [MV88E6185] = { 5962 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5963 .family = MV88E6XXX_FAMILY_6185, 5964 .name = "Marvell 88E6185", 5965 .num_databases = 256, 5966 .num_macs = 8192, 5967 .num_ports = 10, 5968 .num_internal_phys = 0, 5969 .max_vid = 4095, 5970 .port_base_addr = 0x10, 5971 .phy_base_addr = 0x0, 5972 .global1_addr = 0x1b, 5973 .global2_addr = 0x1c, 5974 .age_time_coeff = 15000, 5975 .g1_irqs = 8, 5976 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5977 .atu_move_port_mask = 0xf, 5978 .multi_chip = true, 5979 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5980 .ops = &mv88e6185_ops, 5981 }, 5982 5983 [MV88E6190] = { 5984 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5985 .family = MV88E6XXX_FAMILY_6390, 5986 .name = "Marvell 88E6190", 5987 .num_databases = 4096, 5988 .num_macs = 16384, 5989 .num_ports = 11, /* 10 + Z80 */ 5990 .num_internal_phys = 9, 5991 .num_gpio = 16, 5992 .max_vid = 8191, 5993 .max_sid = 63, 5994 .port_base_addr = 0x0, 5995 .phy_base_addr = 0x0, 5996 .global1_addr = 0x1b, 5997 .global2_addr = 0x1c, 5998 .age_time_coeff = 3750, 5999 .g1_irqs = 9, 6000 .g2_irqs = 14, 6001 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6002 .pvt = true, 6003 .multi_chip = true, 6004 .atu_move_port_mask = 0x1f, 6005 .ops = &mv88e6190_ops, 6006 }, 6007 6008 [MV88E6190X] = { 6009 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6010 .family = MV88E6XXX_FAMILY_6390, 6011 .name = "Marvell 88E6190X", 6012 .num_databases = 4096, 6013 .num_macs = 16384, 6014 .num_ports = 11, /* 10 + Z80 */ 6015 .num_internal_phys = 9, 6016 .num_gpio = 16, 6017 .max_vid = 8191, 6018 .max_sid = 63, 6019 .port_base_addr = 0x0, 6020 .phy_base_addr = 0x0, 6021 .global1_addr = 0x1b, 6022 .global2_addr = 0x1c, 6023 .age_time_coeff = 3750, 6024 .g1_irqs = 9, 6025 .g2_irqs = 14, 6026 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6027 .atu_move_port_mask = 0x1f, 6028 .pvt = true, 6029 .multi_chip = true, 6030 .ops = &mv88e6190x_ops, 6031 }, 6032 6033 [MV88E6191] = { 6034 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6035 .family = MV88E6XXX_FAMILY_6390, 6036 .name = "Marvell 88E6191", 6037 .num_databases = 4096, 6038 .num_macs = 16384, 6039 .num_ports = 11, /* 10 + Z80 */ 6040 .num_internal_phys = 9, 6041 .max_vid = 8191, 6042 .max_sid = 63, 6043 .port_base_addr = 0x0, 6044 .phy_base_addr = 0x0, 6045 .global1_addr = 0x1b, 6046 .global2_addr = 0x1c, 6047 .age_time_coeff = 3750, 6048 .g1_irqs = 9, 6049 .g2_irqs = 14, 6050 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6051 .atu_move_port_mask = 0x1f, 6052 .pvt = true, 6053 .multi_chip = true, 6054 .ptp_support = true, 6055 .ops = &mv88e6191_ops, 6056 }, 6057 6058 [MV88E6191X] = { 6059 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6060 .family = MV88E6XXX_FAMILY_6393, 6061 .name = "Marvell 88E6191X", 6062 .num_databases = 4096, 6063 .num_ports = 11, /* 10 + Z80 */ 6064 .num_internal_phys = 8, 6065 .internal_phys_offset = 1, 6066 .max_vid = 8191, 6067 .max_sid = 63, 6068 .port_base_addr = 0x0, 6069 .phy_base_addr = 0x0, 6070 .global1_addr = 0x1b, 6071 .global2_addr = 0x1c, 6072 .age_time_coeff = 3750, 6073 .g1_irqs = 10, 6074 .g2_irqs = 14, 6075 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6076 .atu_move_port_mask = 0x1f, 6077 .pvt = true, 6078 .multi_chip = true, 6079 .ptp_support = true, 6080 .ops = &mv88e6393x_ops, 6081 }, 6082 6083 [MV88E6193X] = { 6084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6085 .family = MV88E6XXX_FAMILY_6393, 6086 .name = "Marvell 88E6193X", 6087 .num_databases = 4096, 6088 .num_ports = 11, /* 10 + Z80 */ 6089 .num_internal_phys = 8, 6090 .internal_phys_offset = 1, 6091 .max_vid = 8191, 6092 .max_sid = 63, 6093 .port_base_addr = 0x0, 6094 .phy_base_addr = 0x0, 6095 .global1_addr = 0x1b, 6096 .global2_addr = 0x1c, 6097 .age_time_coeff = 3750, 6098 .g1_irqs = 10, 6099 .g2_irqs = 14, 6100 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6101 .atu_move_port_mask = 0x1f, 6102 .pvt = true, 6103 .multi_chip = true, 6104 .ptp_support = true, 6105 .ops = &mv88e6393x_ops, 6106 }, 6107 6108 [MV88E6220] = { 6109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6110 .family = MV88E6XXX_FAMILY_6250, 6111 .name = "Marvell 88E6220", 6112 .num_databases = 64, 6113 6114 /* Ports 2-4 are not routed to pins 6115 * => usable ports 0, 1, 5, 6 6116 */ 6117 .num_ports = 7, 6118 .num_internal_phys = 2, 6119 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6120 .max_vid = 4095, 6121 .port_base_addr = 0x08, 6122 .phy_base_addr = 0x00, 6123 .global1_addr = 0x0f, 6124 .global2_addr = 0x07, 6125 .age_time_coeff = 15000, 6126 .g1_irqs = 9, 6127 .g2_irqs = 10, 6128 .stats_type = STATS_TYPE_BANK0, 6129 .atu_move_port_mask = 0xf, 6130 .dual_chip = true, 6131 .ptp_support = true, 6132 .ops = &mv88e6250_ops, 6133 }, 6134 6135 [MV88E6240] = { 6136 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6137 .family = MV88E6XXX_FAMILY_6352, 6138 .name = "Marvell 88E6240", 6139 .num_databases = 4096, 6140 .num_macs = 8192, 6141 .num_ports = 7, 6142 .num_internal_phys = 5, 6143 .num_gpio = 15, 6144 .max_vid = 4095, 6145 .max_sid = 63, 6146 .port_base_addr = 0x10, 6147 .phy_base_addr = 0x0, 6148 .global1_addr = 0x1b, 6149 .global2_addr = 0x1c, 6150 .age_time_coeff = 15000, 6151 .g1_irqs = 9, 6152 .g2_irqs = 10, 6153 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6154 .atu_move_port_mask = 0xf, 6155 .pvt = true, 6156 .multi_chip = true, 6157 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6158 .ptp_support = true, 6159 .ops = &mv88e6240_ops, 6160 }, 6161 6162 [MV88E6250] = { 6163 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6164 .family = MV88E6XXX_FAMILY_6250, 6165 .name = "Marvell 88E6250", 6166 .num_databases = 64, 6167 .num_ports = 7, 6168 .num_internal_phys = 5, 6169 .max_vid = 4095, 6170 .port_base_addr = 0x08, 6171 .phy_base_addr = 0x00, 6172 .global1_addr = 0x0f, 6173 .global2_addr = 0x07, 6174 .age_time_coeff = 15000, 6175 .g1_irqs = 9, 6176 .g2_irqs = 10, 6177 .stats_type = STATS_TYPE_BANK0, 6178 .atu_move_port_mask = 0xf, 6179 .dual_chip = true, 6180 .ptp_support = true, 6181 .ops = &mv88e6250_ops, 6182 }, 6183 6184 [MV88E6290] = { 6185 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6186 .family = MV88E6XXX_FAMILY_6390, 6187 .name = "Marvell 88E6290", 6188 .num_databases = 4096, 6189 .num_ports = 11, /* 10 + Z80 */ 6190 .num_internal_phys = 9, 6191 .num_gpio = 16, 6192 .max_vid = 8191, 6193 .max_sid = 63, 6194 .port_base_addr = 0x0, 6195 .phy_base_addr = 0x0, 6196 .global1_addr = 0x1b, 6197 .global2_addr = 0x1c, 6198 .age_time_coeff = 3750, 6199 .g1_irqs = 9, 6200 .g2_irqs = 14, 6201 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6202 .atu_move_port_mask = 0x1f, 6203 .pvt = true, 6204 .multi_chip = true, 6205 .ptp_support = true, 6206 .ops = &mv88e6290_ops, 6207 }, 6208 6209 [MV88E6320] = { 6210 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6211 .family = MV88E6XXX_FAMILY_6320, 6212 .name = "Marvell 88E6320", 6213 .num_databases = 4096, 6214 .num_macs = 8192, 6215 .num_ports = 7, 6216 .num_internal_phys = 5, 6217 .num_gpio = 15, 6218 .max_vid = 4095, 6219 .port_base_addr = 0x10, 6220 .phy_base_addr = 0x0, 6221 .global1_addr = 0x1b, 6222 .global2_addr = 0x1c, 6223 .age_time_coeff = 15000, 6224 .g1_irqs = 8, 6225 .g2_irqs = 10, 6226 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6227 .atu_move_port_mask = 0xf, 6228 .pvt = true, 6229 .multi_chip = true, 6230 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6231 .ptp_support = true, 6232 .ops = &mv88e6320_ops, 6233 }, 6234 6235 [MV88E6321] = { 6236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6237 .family = MV88E6XXX_FAMILY_6320, 6238 .name = "Marvell 88E6321", 6239 .num_databases = 4096, 6240 .num_macs = 8192, 6241 .num_ports = 7, 6242 .num_internal_phys = 5, 6243 .num_gpio = 15, 6244 .max_vid = 4095, 6245 .port_base_addr = 0x10, 6246 .phy_base_addr = 0x0, 6247 .global1_addr = 0x1b, 6248 .global2_addr = 0x1c, 6249 .age_time_coeff = 15000, 6250 .g1_irqs = 8, 6251 .g2_irqs = 10, 6252 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6253 .atu_move_port_mask = 0xf, 6254 .multi_chip = true, 6255 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6256 .ptp_support = true, 6257 .ops = &mv88e6321_ops, 6258 }, 6259 6260 [MV88E6341] = { 6261 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6262 .family = MV88E6XXX_FAMILY_6341, 6263 .name = "Marvell 88E6341", 6264 .num_databases = 256, 6265 .num_macs = 2048, 6266 .num_internal_phys = 5, 6267 .num_ports = 6, 6268 .num_gpio = 11, 6269 .max_vid = 4095, 6270 .max_sid = 63, 6271 .port_base_addr = 0x10, 6272 .phy_base_addr = 0x10, 6273 .global1_addr = 0x1b, 6274 .global2_addr = 0x1c, 6275 .age_time_coeff = 3750, 6276 .atu_move_port_mask = 0x1f, 6277 .g1_irqs = 9, 6278 .g2_irqs = 10, 6279 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6280 .pvt = true, 6281 .multi_chip = true, 6282 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6283 .ptp_support = true, 6284 .ops = &mv88e6341_ops, 6285 }, 6286 6287 [MV88E6350] = { 6288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6289 .family = MV88E6XXX_FAMILY_6351, 6290 .name = "Marvell 88E6350", 6291 .num_databases = 4096, 6292 .num_macs = 8192, 6293 .num_ports = 7, 6294 .num_internal_phys = 5, 6295 .max_vid = 4095, 6296 .max_sid = 63, 6297 .port_base_addr = 0x10, 6298 .phy_base_addr = 0x0, 6299 .global1_addr = 0x1b, 6300 .global2_addr = 0x1c, 6301 .age_time_coeff = 15000, 6302 .g1_irqs = 9, 6303 .g2_irqs = 10, 6304 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6305 .atu_move_port_mask = 0xf, 6306 .pvt = true, 6307 .multi_chip = true, 6308 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6309 .ops = &mv88e6350_ops, 6310 }, 6311 6312 [MV88E6351] = { 6313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6314 .family = MV88E6XXX_FAMILY_6351, 6315 .name = "Marvell 88E6351", 6316 .num_databases = 4096, 6317 .num_macs = 8192, 6318 .num_ports = 7, 6319 .num_internal_phys = 5, 6320 .max_vid = 4095, 6321 .max_sid = 63, 6322 .port_base_addr = 0x10, 6323 .phy_base_addr = 0x0, 6324 .global1_addr = 0x1b, 6325 .global2_addr = 0x1c, 6326 .age_time_coeff = 15000, 6327 .g1_irqs = 9, 6328 .g2_irqs = 10, 6329 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6330 .atu_move_port_mask = 0xf, 6331 .pvt = true, 6332 .multi_chip = true, 6333 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6334 .ops = &mv88e6351_ops, 6335 }, 6336 6337 [MV88E6352] = { 6338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6339 .family = MV88E6XXX_FAMILY_6352, 6340 .name = "Marvell 88E6352", 6341 .num_databases = 4096, 6342 .num_macs = 8192, 6343 .num_ports = 7, 6344 .num_internal_phys = 5, 6345 .num_gpio = 15, 6346 .max_vid = 4095, 6347 .max_sid = 63, 6348 .port_base_addr = 0x10, 6349 .phy_base_addr = 0x0, 6350 .global1_addr = 0x1b, 6351 .global2_addr = 0x1c, 6352 .age_time_coeff = 15000, 6353 .g1_irqs = 9, 6354 .g2_irqs = 10, 6355 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6356 .atu_move_port_mask = 0xf, 6357 .pvt = true, 6358 .multi_chip = true, 6359 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6360 .ptp_support = true, 6361 .ops = &mv88e6352_ops, 6362 }, 6363 [MV88E6361] = { 6364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6365 .family = MV88E6XXX_FAMILY_6393, 6366 .name = "Marvell 88E6361", 6367 .num_databases = 4096, 6368 .num_macs = 16384, 6369 .num_ports = 11, 6370 /* Ports 1, 2 and 8 are not routed */ 6371 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6372 .num_internal_phys = 5, 6373 .internal_phys_offset = 3, 6374 .max_vid = 8191, 6375 .max_sid = 63, 6376 .port_base_addr = 0x0, 6377 .phy_base_addr = 0x0, 6378 .global1_addr = 0x1b, 6379 .global2_addr = 0x1c, 6380 .age_time_coeff = 3750, 6381 .g1_irqs = 10, 6382 .g2_irqs = 14, 6383 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6384 .atu_move_port_mask = 0x1f, 6385 .pvt = true, 6386 .multi_chip = true, 6387 .ptp_support = true, 6388 .ops = &mv88e6393x_ops, 6389 }, 6390 [MV88E6390] = { 6391 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6392 .family = MV88E6XXX_FAMILY_6390, 6393 .name = "Marvell 88E6390", 6394 .num_databases = 4096, 6395 .num_macs = 16384, 6396 .num_ports = 11, /* 10 + Z80 */ 6397 .num_internal_phys = 9, 6398 .num_gpio = 16, 6399 .max_vid = 8191, 6400 .max_sid = 63, 6401 .port_base_addr = 0x0, 6402 .phy_base_addr = 0x0, 6403 .global1_addr = 0x1b, 6404 .global2_addr = 0x1c, 6405 .age_time_coeff = 3750, 6406 .g1_irqs = 9, 6407 .g2_irqs = 14, 6408 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6409 .atu_move_port_mask = 0x1f, 6410 .pvt = true, 6411 .multi_chip = true, 6412 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6413 .ptp_support = true, 6414 .ops = &mv88e6390_ops, 6415 }, 6416 [MV88E6390X] = { 6417 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6418 .family = MV88E6XXX_FAMILY_6390, 6419 .name = "Marvell 88E6390X", 6420 .num_databases = 4096, 6421 .num_macs = 16384, 6422 .num_ports = 11, /* 10 + Z80 */ 6423 .num_internal_phys = 9, 6424 .num_gpio = 16, 6425 .max_vid = 8191, 6426 .max_sid = 63, 6427 .port_base_addr = 0x0, 6428 .phy_base_addr = 0x0, 6429 .global1_addr = 0x1b, 6430 .global2_addr = 0x1c, 6431 .age_time_coeff = 3750, 6432 .g1_irqs = 9, 6433 .g2_irqs = 14, 6434 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6435 .atu_move_port_mask = 0x1f, 6436 .pvt = true, 6437 .multi_chip = true, 6438 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6439 .ptp_support = true, 6440 .ops = &mv88e6390x_ops, 6441 }, 6442 6443 [MV88E6393X] = { 6444 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6445 .family = MV88E6XXX_FAMILY_6393, 6446 .name = "Marvell 88E6393X", 6447 .num_databases = 4096, 6448 .num_ports = 11, /* 10 + Z80 */ 6449 .num_internal_phys = 8, 6450 .internal_phys_offset = 1, 6451 .max_vid = 8191, 6452 .max_sid = 63, 6453 .port_base_addr = 0x0, 6454 .phy_base_addr = 0x0, 6455 .global1_addr = 0x1b, 6456 .global2_addr = 0x1c, 6457 .age_time_coeff = 3750, 6458 .g1_irqs = 10, 6459 .g2_irqs = 14, 6460 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6461 .atu_move_port_mask = 0x1f, 6462 .pvt = true, 6463 .multi_chip = true, 6464 .ptp_support = true, 6465 .ops = &mv88e6393x_ops, 6466 }, 6467 }; 6468 6469 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6470 { 6471 int i; 6472 6473 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6474 if (mv88e6xxx_table[i].prod_num == prod_num) 6475 return &mv88e6xxx_table[i]; 6476 6477 return NULL; 6478 } 6479 6480 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6481 { 6482 const struct mv88e6xxx_info *info; 6483 unsigned int prod_num, rev; 6484 u16 id; 6485 int err; 6486 6487 mv88e6xxx_reg_lock(chip); 6488 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6489 mv88e6xxx_reg_unlock(chip); 6490 if (err) 6491 return err; 6492 6493 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6494 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6495 6496 info = mv88e6xxx_lookup_info(prod_num); 6497 if (!info) 6498 return -ENODEV; 6499 6500 /* Update the compatible info with the probed one */ 6501 chip->info = info; 6502 6503 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6504 chip->info->prod_num, chip->info->name, rev); 6505 6506 return 0; 6507 } 6508 6509 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6510 struct mdio_device *mdiodev) 6511 { 6512 int err; 6513 6514 /* dual_chip takes precedence over single/multi-chip modes */ 6515 if (chip->info->dual_chip) 6516 return -EINVAL; 6517 6518 /* If the mdio addr is 16 indicating the first port address of a switch 6519 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6520 * configured in single chip addressing mode. Setup the smi access as 6521 * single chip addressing mode and attempt to detect the model of the 6522 * switch, if this fails the device is not configured in single chip 6523 * addressing mode. 6524 */ 6525 if (mdiodev->addr != 16) 6526 return -EINVAL; 6527 6528 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6529 if (err) 6530 return err; 6531 6532 return mv88e6xxx_detect(chip); 6533 } 6534 6535 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6536 { 6537 struct mv88e6xxx_chip *chip; 6538 6539 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6540 if (!chip) 6541 return NULL; 6542 6543 chip->dev = dev; 6544 6545 mutex_init(&chip->reg_lock); 6546 INIT_LIST_HEAD(&chip->mdios); 6547 idr_init(&chip->policies); 6548 INIT_LIST_HEAD(&chip->msts); 6549 6550 return chip; 6551 } 6552 6553 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6554 int port, 6555 enum dsa_tag_protocol m) 6556 { 6557 struct mv88e6xxx_chip *chip = ds->priv; 6558 6559 return chip->tag_protocol; 6560 } 6561 6562 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6563 enum dsa_tag_protocol proto) 6564 { 6565 struct mv88e6xxx_chip *chip = ds->priv; 6566 enum dsa_tag_protocol old_protocol; 6567 struct dsa_port *cpu_dp; 6568 int err; 6569 6570 switch (proto) { 6571 case DSA_TAG_PROTO_EDSA: 6572 switch (chip->info->edsa_support) { 6573 case MV88E6XXX_EDSA_UNSUPPORTED: 6574 return -EPROTONOSUPPORT; 6575 case MV88E6XXX_EDSA_UNDOCUMENTED: 6576 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6577 fallthrough; 6578 case MV88E6XXX_EDSA_SUPPORTED: 6579 break; 6580 } 6581 break; 6582 case DSA_TAG_PROTO_DSA: 6583 break; 6584 default: 6585 return -EPROTONOSUPPORT; 6586 } 6587 6588 old_protocol = chip->tag_protocol; 6589 chip->tag_protocol = proto; 6590 6591 mv88e6xxx_reg_lock(chip); 6592 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6593 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6594 if (err) { 6595 mv88e6xxx_reg_unlock(chip); 6596 goto unwind; 6597 } 6598 } 6599 mv88e6xxx_reg_unlock(chip); 6600 6601 return 0; 6602 6603 unwind: 6604 chip->tag_protocol = old_protocol; 6605 6606 mv88e6xxx_reg_lock(chip); 6607 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6608 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6609 mv88e6xxx_reg_unlock(chip); 6610 6611 return err; 6612 } 6613 6614 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6615 const struct switchdev_obj_port_mdb *mdb, 6616 struct dsa_db db) 6617 { 6618 struct mv88e6xxx_chip *chip = ds->priv; 6619 int err; 6620 6621 mv88e6xxx_reg_lock(chip); 6622 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6623 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6624 mv88e6xxx_reg_unlock(chip); 6625 6626 return err; 6627 } 6628 6629 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6630 const struct switchdev_obj_port_mdb *mdb, 6631 struct dsa_db db) 6632 { 6633 struct mv88e6xxx_chip *chip = ds->priv; 6634 int err; 6635 6636 mv88e6xxx_reg_lock(chip); 6637 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6638 mv88e6xxx_reg_unlock(chip); 6639 6640 return err; 6641 } 6642 6643 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6644 struct dsa_mall_mirror_tc_entry *mirror, 6645 bool ingress, 6646 struct netlink_ext_ack *extack) 6647 { 6648 enum mv88e6xxx_egress_direction direction = ingress ? 6649 MV88E6XXX_EGRESS_DIR_INGRESS : 6650 MV88E6XXX_EGRESS_DIR_EGRESS; 6651 struct mv88e6xxx_chip *chip = ds->priv; 6652 bool other_mirrors = false; 6653 int i; 6654 int err; 6655 6656 mutex_lock(&chip->reg_lock); 6657 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6658 mirror->to_local_port) { 6659 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6660 other_mirrors |= ingress ? 6661 chip->ports[i].mirror_ingress : 6662 chip->ports[i].mirror_egress; 6663 6664 /* Can't change egress port when other mirror is active */ 6665 if (other_mirrors) { 6666 err = -EBUSY; 6667 goto out; 6668 } 6669 6670 err = mv88e6xxx_set_egress_port(chip, direction, 6671 mirror->to_local_port); 6672 if (err) 6673 goto out; 6674 } 6675 6676 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6677 out: 6678 mutex_unlock(&chip->reg_lock); 6679 6680 return err; 6681 } 6682 6683 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6684 struct dsa_mall_mirror_tc_entry *mirror) 6685 { 6686 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6687 MV88E6XXX_EGRESS_DIR_INGRESS : 6688 MV88E6XXX_EGRESS_DIR_EGRESS; 6689 struct mv88e6xxx_chip *chip = ds->priv; 6690 bool other_mirrors = false; 6691 int i; 6692 6693 mutex_lock(&chip->reg_lock); 6694 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6695 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6696 6697 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6698 other_mirrors |= mirror->ingress ? 6699 chip->ports[i].mirror_ingress : 6700 chip->ports[i].mirror_egress; 6701 6702 /* Reset egress port when no other mirror is active */ 6703 if (!other_mirrors) { 6704 if (mv88e6xxx_set_egress_port(chip, direction, 6705 dsa_upstream_port(ds, port))) 6706 dev_err(ds->dev, "failed to set egress port\n"); 6707 } 6708 6709 mutex_unlock(&chip->reg_lock); 6710 } 6711 6712 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6713 struct switchdev_brport_flags flags, 6714 struct netlink_ext_ack *extack) 6715 { 6716 struct mv88e6xxx_chip *chip = ds->priv; 6717 const struct mv88e6xxx_ops *ops; 6718 6719 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6720 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6721 return -EINVAL; 6722 6723 ops = chip->info->ops; 6724 6725 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6726 return -EINVAL; 6727 6728 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6729 return -EINVAL; 6730 6731 return 0; 6732 } 6733 6734 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6735 struct switchdev_brport_flags flags, 6736 struct netlink_ext_ack *extack) 6737 { 6738 struct mv88e6xxx_chip *chip = ds->priv; 6739 int err = 0; 6740 6741 mv88e6xxx_reg_lock(chip); 6742 6743 if (flags.mask & BR_LEARNING) { 6744 bool learning = !!(flags.val & BR_LEARNING); 6745 u16 pav = learning ? (1 << port) : 0; 6746 6747 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6748 if (err) 6749 goto out; 6750 } 6751 6752 if (flags.mask & BR_FLOOD) { 6753 bool unicast = !!(flags.val & BR_FLOOD); 6754 6755 err = chip->info->ops->port_set_ucast_flood(chip, port, 6756 unicast); 6757 if (err) 6758 goto out; 6759 } 6760 6761 if (flags.mask & BR_MCAST_FLOOD) { 6762 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6763 6764 err = chip->info->ops->port_set_mcast_flood(chip, port, 6765 multicast); 6766 if (err) 6767 goto out; 6768 } 6769 6770 if (flags.mask & BR_BCAST_FLOOD) { 6771 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6772 6773 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6774 if (err) 6775 goto out; 6776 } 6777 6778 if (flags.mask & BR_PORT_MAB) { 6779 bool mab = !!(flags.val & BR_PORT_MAB); 6780 6781 mv88e6xxx_port_set_mab(chip, port, mab); 6782 } 6783 6784 if (flags.mask & BR_PORT_LOCKED) { 6785 bool locked = !!(flags.val & BR_PORT_LOCKED); 6786 6787 err = mv88e6xxx_port_set_lock(chip, port, locked); 6788 if (err) 6789 goto out; 6790 } 6791 out: 6792 mv88e6xxx_reg_unlock(chip); 6793 6794 return err; 6795 } 6796 6797 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6798 struct dsa_lag lag, 6799 struct netdev_lag_upper_info *info, 6800 struct netlink_ext_ack *extack) 6801 { 6802 struct mv88e6xxx_chip *chip = ds->priv; 6803 struct dsa_port *dp; 6804 int members = 0; 6805 6806 if (!mv88e6xxx_has_lag(chip)) { 6807 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6808 return false; 6809 } 6810 6811 if (!lag.id) 6812 return false; 6813 6814 dsa_lag_foreach_port(dp, ds->dst, &lag) 6815 /* Includes the port joining the LAG */ 6816 members++; 6817 6818 if (members > 8) { 6819 NL_SET_ERR_MSG_MOD(extack, 6820 "Cannot offload more than 8 LAG ports"); 6821 return false; 6822 } 6823 6824 /* We could potentially relax this to include active 6825 * backup in the future. 6826 */ 6827 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6828 NL_SET_ERR_MSG_MOD(extack, 6829 "Can only offload LAG using hash TX type"); 6830 return false; 6831 } 6832 6833 /* Ideally we would also validate that the hash type matches 6834 * the hardware. Alas, this is always set to unknown on team 6835 * interfaces. 6836 */ 6837 return true; 6838 } 6839 6840 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6841 { 6842 struct mv88e6xxx_chip *chip = ds->priv; 6843 struct dsa_port *dp; 6844 u16 map = 0; 6845 int id; 6846 6847 /* DSA LAG IDs are one-based, hardware is zero-based */ 6848 id = lag.id - 1; 6849 6850 /* Build the map of all ports to distribute flows destined for 6851 * this LAG. This can be either a local user port, or a DSA 6852 * port if the LAG port is on a remote chip. 6853 */ 6854 dsa_lag_foreach_port(dp, ds->dst, &lag) 6855 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6856 6857 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6858 } 6859 6860 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6861 /* Row number corresponds to the number of active members in a 6862 * LAG. Each column states which of the eight hash buckets are 6863 * mapped to the column:th port in the LAG. 6864 * 6865 * Example: In a LAG with three active ports, the second port 6866 * ([2][1]) would be selected for traffic mapped to buckets 6867 * 3,4,5 (0x38). 6868 */ 6869 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6870 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6871 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6872 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6873 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6874 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6875 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6876 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6877 }; 6878 6879 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6880 int num_tx, int nth) 6881 { 6882 u8 active = 0; 6883 int i; 6884 6885 num_tx = num_tx <= 8 ? num_tx : 8; 6886 if (nth < num_tx) 6887 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6888 6889 for (i = 0; i < 8; i++) { 6890 if (BIT(i) & active) 6891 mask[i] |= BIT(port); 6892 } 6893 } 6894 6895 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6896 { 6897 struct mv88e6xxx_chip *chip = ds->priv; 6898 unsigned int id, num_tx; 6899 struct dsa_port *dp; 6900 struct dsa_lag *lag; 6901 int i, err, nth; 6902 u16 mask[8]; 6903 u16 ivec; 6904 6905 /* Assume no port is a member of any LAG. */ 6906 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6907 6908 /* Disable all masks for ports that _are_ members of a LAG. */ 6909 dsa_switch_for_each_port(dp, ds) { 6910 if (!dp->lag) 6911 continue; 6912 6913 ivec &= ~BIT(dp->index); 6914 } 6915 6916 for (i = 0; i < 8; i++) 6917 mask[i] = ivec; 6918 6919 /* Enable the correct subset of masks for all LAG ports that 6920 * are in the Tx set. 6921 */ 6922 dsa_lags_foreach_id(id, ds->dst) { 6923 lag = dsa_lag_by_id(ds->dst, id); 6924 if (!lag) 6925 continue; 6926 6927 num_tx = 0; 6928 dsa_lag_foreach_port(dp, ds->dst, lag) { 6929 if (dp->lag_tx_enabled) 6930 num_tx++; 6931 } 6932 6933 if (!num_tx) 6934 continue; 6935 6936 nth = 0; 6937 dsa_lag_foreach_port(dp, ds->dst, lag) { 6938 if (!dp->lag_tx_enabled) 6939 continue; 6940 6941 if (dp->ds == ds) 6942 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6943 num_tx, nth); 6944 6945 nth++; 6946 } 6947 } 6948 6949 for (i = 0; i < 8; i++) { 6950 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6951 if (err) 6952 return err; 6953 } 6954 6955 return 0; 6956 } 6957 6958 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6959 struct dsa_lag lag) 6960 { 6961 int err; 6962 6963 err = mv88e6xxx_lag_sync_masks(ds); 6964 6965 if (!err) 6966 err = mv88e6xxx_lag_sync_map(ds, lag); 6967 6968 return err; 6969 } 6970 6971 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6972 { 6973 struct mv88e6xxx_chip *chip = ds->priv; 6974 int err; 6975 6976 mv88e6xxx_reg_lock(chip); 6977 err = mv88e6xxx_lag_sync_masks(ds); 6978 mv88e6xxx_reg_unlock(chip); 6979 return err; 6980 } 6981 6982 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6983 struct dsa_lag lag, 6984 struct netdev_lag_upper_info *info, 6985 struct netlink_ext_ack *extack) 6986 { 6987 struct mv88e6xxx_chip *chip = ds->priv; 6988 int err, id; 6989 6990 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6991 return -EOPNOTSUPP; 6992 6993 /* DSA LAG IDs are one-based */ 6994 id = lag.id - 1; 6995 6996 mv88e6xxx_reg_lock(chip); 6997 6998 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6999 if (err) 7000 goto err_unlock; 7001 7002 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7003 if (err) 7004 goto err_clear_trunk; 7005 7006 mv88e6xxx_reg_unlock(chip); 7007 return 0; 7008 7009 err_clear_trunk: 7010 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7011 err_unlock: 7012 mv88e6xxx_reg_unlock(chip); 7013 return err; 7014 } 7015 7016 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7017 struct dsa_lag lag) 7018 { 7019 struct mv88e6xxx_chip *chip = ds->priv; 7020 int err_sync, err_trunk; 7021 7022 mv88e6xxx_reg_lock(chip); 7023 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7024 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7025 mv88e6xxx_reg_unlock(chip); 7026 return err_sync ? : err_trunk; 7027 } 7028 7029 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7030 int port) 7031 { 7032 struct mv88e6xxx_chip *chip = ds->priv; 7033 int err; 7034 7035 mv88e6xxx_reg_lock(chip); 7036 err = mv88e6xxx_lag_sync_masks(ds); 7037 mv88e6xxx_reg_unlock(chip); 7038 return err; 7039 } 7040 7041 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7042 int port, struct dsa_lag lag, 7043 struct netdev_lag_upper_info *info, 7044 struct netlink_ext_ack *extack) 7045 { 7046 struct mv88e6xxx_chip *chip = ds->priv; 7047 int err; 7048 7049 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7050 return -EOPNOTSUPP; 7051 7052 mv88e6xxx_reg_lock(chip); 7053 7054 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7055 if (err) 7056 goto unlock; 7057 7058 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7059 7060 unlock: 7061 mv88e6xxx_reg_unlock(chip); 7062 return err; 7063 } 7064 7065 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7066 int port, struct dsa_lag lag) 7067 { 7068 struct mv88e6xxx_chip *chip = ds->priv; 7069 int err_sync, err_pvt; 7070 7071 mv88e6xxx_reg_lock(chip); 7072 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7073 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7074 mv88e6xxx_reg_unlock(chip); 7075 return err_sync ? : err_pvt; 7076 } 7077 7078 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7079 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7080 .mac_prepare = mv88e6xxx_mac_prepare, 7081 .mac_config = mv88e6xxx_mac_config, 7082 .mac_finish = mv88e6xxx_mac_finish, 7083 .mac_link_down = mv88e6xxx_mac_link_down, 7084 .mac_link_up = mv88e6xxx_mac_link_up, 7085 }; 7086 7087 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7088 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7089 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7090 .setup = mv88e6xxx_setup, 7091 .teardown = mv88e6xxx_teardown, 7092 .port_setup = mv88e6xxx_port_setup, 7093 .port_teardown = mv88e6xxx_port_teardown, 7094 .phylink_get_caps = mv88e6xxx_get_caps, 7095 .get_strings = mv88e6xxx_get_strings, 7096 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7097 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7098 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7099 .get_sset_count = mv88e6xxx_get_sset_count, 7100 .port_max_mtu = mv88e6xxx_get_max_mtu, 7101 .port_change_mtu = mv88e6xxx_change_mtu, 7102 .support_eee = dsa_supports_eee, 7103 .get_mac_eee = mv88e6xxx_get_mac_eee, 7104 .set_mac_eee = mv88e6xxx_set_mac_eee, 7105 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7106 .get_eeprom = mv88e6xxx_get_eeprom, 7107 .set_eeprom = mv88e6xxx_set_eeprom, 7108 .get_regs_len = mv88e6xxx_get_regs_len, 7109 .get_regs = mv88e6xxx_get_regs, 7110 .get_rxnfc = mv88e6xxx_get_rxnfc, 7111 .set_rxnfc = mv88e6xxx_set_rxnfc, 7112 .set_ageing_time = mv88e6xxx_set_ageing_time, 7113 .port_bridge_join = mv88e6xxx_port_bridge_join, 7114 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7115 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7116 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7117 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7118 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7119 .port_fast_age = mv88e6xxx_port_fast_age, 7120 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7121 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7122 .port_vlan_add = mv88e6xxx_port_vlan_add, 7123 .port_vlan_del = mv88e6xxx_port_vlan_del, 7124 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7125 .port_fdb_add = mv88e6xxx_port_fdb_add, 7126 .port_fdb_del = mv88e6xxx_port_fdb_del, 7127 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7128 .port_mdb_add = mv88e6xxx_port_mdb_add, 7129 .port_mdb_del = mv88e6xxx_port_mdb_del, 7130 .port_mirror_add = mv88e6xxx_port_mirror_add, 7131 .port_mirror_del = mv88e6xxx_port_mirror_del, 7132 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7133 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7134 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7135 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7136 .port_txtstamp = mv88e6xxx_port_txtstamp, 7137 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7138 .get_ts_info = mv88e6xxx_get_ts_info, 7139 .devlink_param_get = mv88e6xxx_devlink_param_get, 7140 .devlink_param_set = mv88e6xxx_devlink_param_set, 7141 .devlink_info_get = mv88e6xxx_devlink_info_get, 7142 .port_lag_change = mv88e6xxx_port_lag_change, 7143 .port_lag_join = mv88e6xxx_port_lag_join, 7144 .port_lag_leave = mv88e6xxx_port_lag_leave, 7145 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7146 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7147 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7148 }; 7149 7150 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7151 { 7152 struct device *dev = chip->dev; 7153 struct dsa_switch *ds; 7154 7155 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7156 if (!ds) 7157 return -ENOMEM; 7158 7159 ds->dev = dev; 7160 ds->num_ports = mv88e6xxx_num_ports(chip); 7161 ds->priv = chip; 7162 ds->dev = dev; 7163 ds->ops = &mv88e6xxx_switch_ops; 7164 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7165 ds->ageing_time_min = chip->info->age_time_coeff; 7166 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7167 7168 /* Some chips support up to 32, but that requires enabling the 7169 * 5-bit port mode, which we do not support. 640k^W16 ought to 7170 * be enough for anyone. 7171 */ 7172 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7173 7174 dev_set_drvdata(dev, ds); 7175 7176 return dsa_register_switch(ds); 7177 } 7178 7179 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7180 { 7181 dsa_unregister_switch(chip->ds); 7182 } 7183 7184 static const void *pdata_device_get_match_data(struct device *dev) 7185 { 7186 const struct of_device_id *matches = dev->driver->of_match_table; 7187 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7188 7189 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7190 matches++) { 7191 if (!strcmp(pdata->compatible, matches->compatible)) 7192 return matches->data; 7193 } 7194 return NULL; 7195 } 7196 7197 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7198 * would be lost after a power cycle so prevent it to be suspended. 7199 */ 7200 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7201 { 7202 return -EOPNOTSUPP; 7203 } 7204 7205 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7206 { 7207 return 0; 7208 } 7209 7210 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7211 7212 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7213 { 7214 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7215 const struct mv88e6xxx_info *compat_info = NULL; 7216 struct device *dev = &mdiodev->dev; 7217 struct device_node *np = dev->of_node; 7218 struct mv88e6xxx_chip *chip; 7219 int port; 7220 int err; 7221 7222 if (!np && !pdata) 7223 return -EINVAL; 7224 7225 if (np) 7226 compat_info = of_device_get_match_data(dev); 7227 7228 if (pdata) { 7229 compat_info = pdata_device_get_match_data(dev); 7230 7231 if (!pdata->netdev) 7232 return -EINVAL; 7233 7234 for (port = 0; port < DSA_MAX_PORTS; port++) { 7235 if (!(pdata->enabled_ports & (1 << port))) 7236 continue; 7237 if (strcmp(pdata->cd.port_names[port], "cpu")) 7238 continue; 7239 pdata->cd.netdev[port] = &pdata->netdev->dev; 7240 break; 7241 } 7242 } 7243 7244 if (!compat_info) 7245 return -EINVAL; 7246 7247 chip = mv88e6xxx_alloc_chip(dev); 7248 if (!chip) { 7249 err = -ENOMEM; 7250 goto out; 7251 } 7252 7253 chip->info = compat_info; 7254 7255 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7256 if (IS_ERR(chip->reset)) { 7257 err = PTR_ERR(chip->reset); 7258 goto out; 7259 } 7260 if (chip->reset) 7261 usleep_range(10000, 20000); 7262 7263 /* Detect if the device is configured in single chip addressing mode, 7264 * otherwise continue with address specific smi init/detection. 7265 */ 7266 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7267 if (err) { 7268 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7269 if (err) 7270 goto out; 7271 7272 err = mv88e6xxx_detect(chip); 7273 if (err) 7274 goto out; 7275 } 7276 7277 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7278 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7279 else 7280 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7281 7282 mv88e6xxx_phy_init(chip); 7283 7284 if (chip->info->ops->get_eeprom) { 7285 if (np) 7286 of_property_read_u32(np, "eeprom-length", 7287 &chip->eeprom_len); 7288 else 7289 chip->eeprom_len = pdata->eeprom_len; 7290 } 7291 7292 mv88e6xxx_reg_lock(chip); 7293 err = mv88e6xxx_switch_reset(chip); 7294 mv88e6xxx_reg_unlock(chip); 7295 if (err) 7296 goto out; 7297 7298 if (np) { 7299 chip->irq = of_irq_get(np, 0); 7300 if (chip->irq == -EPROBE_DEFER) { 7301 err = chip->irq; 7302 goto out; 7303 } 7304 } 7305 7306 if (pdata) 7307 chip->irq = pdata->irq; 7308 7309 /* Has to be performed before the MDIO bus is created, because 7310 * the PHYs will link their interrupts to these interrupt 7311 * controllers 7312 */ 7313 mv88e6xxx_reg_lock(chip); 7314 if (chip->irq > 0) 7315 err = mv88e6xxx_g1_irq_setup(chip); 7316 else 7317 err = mv88e6xxx_irq_poll_setup(chip); 7318 mv88e6xxx_reg_unlock(chip); 7319 7320 if (err) 7321 goto out; 7322 7323 if (chip->info->g2_irqs > 0) { 7324 err = mv88e6xxx_g2_irq_setup(chip); 7325 if (err) 7326 goto out_g1_irq; 7327 } 7328 7329 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7330 if (err) 7331 goto out_g2_irq; 7332 7333 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7334 if (err) 7335 goto out_g1_atu_prob_irq; 7336 7337 err = mv88e6xxx_register_switch(chip); 7338 if (err) 7339 goto out_g1_vtu_prob_irq; 7340 7341 return 0; 7342 7343 out_g1_vtu_prob_irq: 7344 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7345 out_g1_atu_prob_irq: 7346 mv88e6xxx_g1_atu_prob_irq_free(chip); 7347 out_g2_irq: 7348 if (chip->info->g2_irqs > 0) 7349 mv88e6xxx_g2_irq_free(chip); 7350 out_g1_irq: 7351 if (chip->irq > 0) 7352 mv88e6xxx_g1_irq_free(chip); 7353 else 7354 mv88e6xxx_irq_poll_free(chip); 7355 out: 7356 if (pdata) 7357 dev_put(pdata->netdev); 7358 7359 return err; 7360 } 7361 7362 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7363 { 7364 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7365 struct mv88e6xxx_chip *chip; 7366 7367 if (!ds) 7368 return; 7369 7370 chip = ds->priv; 7371 7372 if (chip->info->ptp_support) { 7373 mv88e6xxx_hwtstamp_free(chip); 7374 mv88e6xxx_ptp_free(chip); 7375 } 7376 7377 mv88e6xxx_phy_destroy(chip); 7378 mv88e6xxx_unregister_switch(chip); 7379 7380 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7381 mv88e6xxx_g1_atu_prob_irq_free(chip); 7382 7383 if (chip->info->g2_irqs > 0) 7384 mv88e6xxx_g2_irq_free(chip); 7385 7386 if (chip->irq > 0) 7387 mv88e6xxx_g1_irq_free(chip); 7388 else 7389 mv88e6xxx_irq_poll_free(chip); 7390 } 7391 7392 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7393 { 7394 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7395 7396 if (!ds) 7397 return; 7398 7399 dsa_switch_shutdown(ds); 7400 7401 dev_set_drvdata(&mdiodev->dev, NULL); 7402 } 7403 7404 static const struct of_device_id mv88e6xxx_of_match[] = { 7405 { 7406 .compatible = "marvell,mv88e6085", 7407 .data = &mv88e6xxx_table[MV88E6085], 7408 }, 7409 { 7410 .compatible = "marvell,mv88e6190", 7411 .data = &mv88e6xxx_table[MV88E6190], 7412 }, 7413 { 7414 .compatible = "marvell,mv88e6250", 7415 .data = &mv88e6xxx_table[MV88E6250], 7416 }, 7417 { /* sentinel */ }, 7418 }; 7419 7420 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7421 7422 static struct mdio_driver mv88e6xxx_driver = { 7423 .probe = mv88e6xxx_probe, 7424 .remove = mv88e6xxx_remove, 7425 .shutdown = mv88e6xxx_shutdown, 7426 .mdiodrv.driver = { 7427 .name = "mv88e6085", 7428 .of_match_table = mv88e6xxx_of_match, 7429 .pm = &mv88e6xxx_pm_ops, 7430 }, 7431 }; 7432 7433 mdio_module_driver(mv88e6xxx_driver); 7434 7435 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7436 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7437 MODULE_LICENSE("GPL"); 7438