xref: /linux/drivers/net/dsa/mv88e6xxx/chip.c (revision f858cc9eed5b05cbe38d7ffd2787c21e3718eb7d)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88e6xxx Ethernet switch single-chip support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8  *
9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11  */
12 
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/property.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phylink.h>
34 #include <net/dsa.h>
35 
36 #include "chip.h"
37 #include "devlink.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "hwtstamp.h"
41 #include "phy.h"
42 #include "port.h"
43 #include "ptp.h"
44 #include "serdes.h"
45 #include "smi.h"
46 
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48 {
49 	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 		dev_err(chip->dev, "Switch registers lock not held!\n");
51 		dump_stack();
52 	}
53 }
54 
55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
56 {
57 	int err;
58 
59 	assert_reg_lock(chip);
60 
61 	err = mv88e6xxx_smi_read(chip, addr, reg, val);
62 	if (err)
63 		return err;
64 
65 	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
66 		addr, reg, *val);
67 
68 	return 0;
69 }
70 
71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
72 {
73 	int err;
74 
75 	assert_reg_lock(chip);
76 
77 	err = mv88e6xxx_smi_write(chip, addr, reg, val);
78 	if (err)
79 		return err;
80 
81 	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
82 		addr, reg, val);
83 
84 	return 0;
85 }
86 
87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
88 			u16 mask, u16 val)
89 {
90 	const unsigned long timeout = jiffies + msecs_to_jiffies(50);
91 	u16 data;
92 	int err;
93 	int i;
94 
95 	/* There's no bus specific operation to wait for a mask. Even
96 	 * if the initial poll takes longer than 50ms, always do at
97 	 * least one more attempt.
98 	 */
99 	for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
100 		err = mv88e6xxx_read(chip, addr, reg, &data);
101 		if (err)
102 			return err;
103 
104 		if ((data & mask) == val)
105 			return 0;
106 
107 		if (i < 2)
108 			cpu_relax();
109 		else
110 			usleep_range(1000, 2000);
111 	}
112 
113 	err = mv88e6xxx_read(chip, addr, reg, &data);
114 	if (err)
115 		return err;
116 
117 	if ((data & mask) == val)
118 		return 0;
119 
120 	dev_err(chip->dev, "Timeout while waiting for switch\n");
121 	return -ETIMEDOUT;
122 }
123 
124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
125 		       int bit, int val)
126 {
127 	return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
128 				   val ? BIT(bit) : 0x0000);
129 }
130 
131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
132 {
133 	struct mv88e6xxx_mdio_bus *mdio_bus;
134 
135 	mdio_bus = list_first_entry_or_null(&chip->mdios,
136 					    struct mv88e6xxx_mdio_bus, list);
137 	if (!mdio_bus)
138 		return NULL;
139 
140 	return mdio_bus->bus;
141 }
142 
143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
144 {
145 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 	unsigned int n = d->hwirq;
147 
148 	chip->g1_irq.masked |= (1 << n);
149 }
150 
151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
152 {
153 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
154 	unsigned int n = d->hwirq;
155 
156 	chip->g1_irq.masked &= ~(1 << n);
157 }
158 
159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
160 {
161 	unsigned int nhandled = 0;
162 	unsigned int sub_irq;
163 	unsigned int n;
164 	u16 reg;
165 	u16 ctl1;
166 	int err;
167 
168 	mv88e6xxx_reg_lock(chip);
169 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
170 	mv88e6xxx_reg_unlock(chip);
171 
172 	if (err)
173 		goto out;
174 
175 	do {
176 		for (n = 0; n < chip->g1_irq.nirqs; ++n) {
177 			if (reg & (1 << n)) {
178 				sub_irq = irq_find_mapping(chip->g1_irq.domain,
179 							   n);
180 				handle_nested_irq(sub_irq);
181 				++nhandled;
182 			}
183 		}
184 
185 		mv88e6xxx_reg_lock(chip);
186 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
187 		if (err)
188 			goto unlock;
189 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
190 unlock:
191 		mv88e6xxx_reg_unlock(chip);
192 		if (err)
193 			goto out;
194 		ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
195 	} while (reg & ctl1);
196 
197 out:
198 	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
199 }
200 
201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
202 {
203 	struct mv88e6xxx_chip *chip = dev_id;
204 
205 	return mv88e6xxx_g1_irq_thread_work(chip);
206 }
207 
208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
209 {
210 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
211 
212 	mv88e6xxx_reg_lock(chip);
213 }
214 
215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
216 {
217 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
218 	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
219 	u16 reg;
220 	int err;
221 
222 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
223 	if (err)
224 		goto out;
225 
226 	reg &= ~mask;
227 	reg |= (~chip->g1_irq.masked & mask);
228 
229 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
230 	if (err)
231 		goto out;
232 
233 out:
234 	mv88e6xxx_reg_unlock(chip);
235 }
236 
237 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
238 	.name			= "mv88e6xxx-g1",
239 	.irq_mask		= mv88e6xxx_g1_irq_mask,
240 	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
241 	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
242 	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
243 };
244 
245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
246 				       unsigned int irq,
247 				       irq_hw_number_t hwirq)
248 {
249 	struct mv88e6xxx_chip *chip = d->host_data;
250 
251 	irq_set_chip_data(irq, d->host_data);
252 	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
253 	irq_set_noprobe(irq);
254 
255 	return 0;
256 }
257 
258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
259 	.map	= mv88e6xxx_g1_irq_domain_map,
260 	.xlate	= irq_domain_xlate_twocell,
261 };
262 
263 /* To be called with reg_lock held */
264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
265 {
266 	int irq, virq;
267 	u16 mask;
268 
269 	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
270 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
272 
273 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
274 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
275 		irq_dispose_mapping(virq);
276 	}
277 
278 	irq_domain_remove(chip->g1_irq.domain);
279 }
280 
281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
282 {
283 	/*
284 	 * free_irq must be called without reg_lock taken because the irq
285 	 * handler takes this lock, too.
286 	 */
287 	free_irq(chip->irq, chip);
288 
289 	mv88e6xxx_reg_lock(chip);
290 	mv88e6xxx_g1_irq_free_common(chip);
291 	mv88e6xxx_reg_unlock(chip);
292 }
293 
294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
295 {
296 	int err, irq, virq;
297 	u16 reg, mask;
298 
299 	chip->g1_irq.nirqs = chip->info->g1_irqs;
300 	chip->g1_irq.domain = irq_domain_add_simple(
301 		NULL, chip->g1_irq.nirqs, 0,
302 		&mv88e6xxx_g1_irq_domain_ops, chip);
303 	if (!chip->g1_irq.domain)
304 		return -ENOMEM;
305 
306 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
307 		irq_create_mapping(chip->g1_irq.domain, irq);
308 
309 	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
310 	chip->g1_irq.masked = ~0;
311 
312 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
313 	if (err)
314 		goto out_mapping;
315 
316 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
317 
318 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
319 	if (err)
320 		goto out_disable;
321 
322 	/* Reading the interrupt status clears (most of) them */
323 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
324 	if (err)
325 		goto out_disable;
326 
327 	return 0;
328 
329 out_disable:
330 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
331 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
332 
333 out_mapping:
334 	for (irq = 0; irq < 16; irq++) {
335 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
336 		irq_dispose_mapping(virq);
337 	}
338 
339 	irq_domain_remove(chip->g1_irq.domain);
340 
341 	return err;
342 }
343 
344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
345 {
346 	static struct lock_class_key lock_key;
347 	static struct lock_class_key request_key;
348 	int err;
349 
350 	err = mv88e6xxx_g1_irq_setup_common(chip);
351 	if (err)
352 		return err;
353 
354 	/* These lock classes tells lockdep that global 1 irqs are in
355 	 * a different category than their parent GPIO, so it won't
356 	 * report false recursion.
357 	 */
358 	irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
359 
360 	snprintf(chip->irq_name, sizeof(chip->irq_name),
361 		 "mv88e6xxx-%s", dev_name(chip->dev));
362 
363 	mv88e6xxx_reg_unlock(chip);
364 	err = request_threaded_irq(chip->irq, NULL,
365 				   mv88e6xxx_g1_irq_thread_fn,
366 				   IRQF_ONESHOT | IRQF_SHARED,
367 				   chip->irq_name, chip);
368 	mv88e6xxx_reg_lock(chip);
369 	if (err)
370 		mv88e6xxx_g1_irq_free_common(chip);
371 
372 	return err;
373 }
374 
375 static void mv88e6xxx_irq_poll(struct kthread_work *work)
376 {
377 	struct mv88e6xxx_chip *chip = container_of(work,
378 						   struct mv88e6xxx_chip,
379 						   irq_poll_work.work);
380 	mv88e6xxx_g1_irq_thread_work(chip);
381 
382 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
383 				   msecs_to_jiffies(100));
384 }
385 
386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
387 {
388 	int err;
389 
390 	err = mv88e6xxx_g1_irq_setup_common(chip);
391 	if (err)
392 		return err;
393 
394 	kthread_init_delayed_work(&chip->irq_poll_work,
395 				  mv88e6xxx_irq_poll);
396 
397 	chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
398 	if (IS_ERR(chip->kworker))
399 		return PTR_ERR(chip->kworker);
400 
401 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
402 				   msecs_to_jiffies(100));
403 
404 	return 0;
405 }
406 
407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
408 {
409 	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
410 	kthread_destroy_worker(chip->kworker);
411 
412 	mv88e6xxx_reg_lock(chip);
413 	mv88e6xxx_g1_irq_free_common(chip);
414 	mv88e6xxx_reg_unlock(chip);
415 }
416 
417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
418 					   int port, phy_interface_t interface)
419 {
420 	int err;
421 
422 	if (chip->info->ops->port_set_rgmii_delay) {
423 		err = chip->info->ops->port_set_rgmii_delay(chip, port,
424 							    interface);
425 		if (err && err != -EOPNOTSUPP)
426 			return err;
427 	}
428 
429 	if (chip->info->ops->port_set_cmode) {
430 		err = chip->info->ops->port_set_cmode(chip, port,
431 						      interface);
432 		if (err && err != -EOPNOTSUPP)
433 			return err;
434 	}
435 
436 	return 0;
437 }
438 
439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
440 				    int link, int speed, int duplex, int pause,
441 				    phy_interface_t mode)
442 {
443 	int err;
444 
445 	if (!chip->info->ops->port_set_link)
446 		return 0;
447 
448 	/* Port's MAC control must not be changed unless the link is down */
449 	err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
450 	if (err)
451 		return err;
452 
453 	if (chip->info->ops->port_set_speed_duplex) {
454 		err = chip->info->ops->port_set_speed_duplex(chip, port,
455 							     speed, duplex);
456 		if (err && err != -EOPNOTSUPP)
457 			goto restore_link;
458 	}
459 
460 	if (chip->info->ops->port_set_pause) {
461 		err = chip->info->ops->port_set_pause(chip, port, pause);
462 		if (err)
463 			goto restore_link;
464 	}
465 
466 	err = mv88e6xxx_port_config_interface(chip, port, mode);
467 restore_link:
468 	if (chip->info->ops->port_set_link(chip, port, link))
469 		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
470 
471 	return err;
472 }
473 
474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
475 {
476 	return port >= chip->info->internal_phys_offset &&
477 		port < chip->info->num_internal_phys +
478 			chip->info->internal_phys_offset;
479 }
480 
481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
482 {
483 	u16 reg;
484 	int err;
485 
486 	/* The 88e6250 family does not have the PHY detect bit. Instead,
487 	 * report whether the port is internal.
488 	 */
489 	if (chip->info->family == MV88E6XXX_FAMILY_6250)
490 		return mv88e6xxx_phy_is_internal(chip, port);
491 
492 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
493 	if (err) {
494 		dev_err(chip->dev,
495 			"p%d: %s: failed to read port status\n",
496 			port, __func__);
497 		return err;
498 	}
499 
500 	return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
501 }
502 
503 static const u8 mv88e6185_phy_interface_modes[] = {
504 	[MV88E6185_PORT_STS_CMODE_GMII_FD]	 = PHY_INTERFACE_MODE_GMII,
505 	[MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
506 	[MV88E6185_PORT_STS_CMODE_MII_100]	 = PHY_INTERFACE_MODE_MII,
507 	[MV88E6185_PORT_STS_CMODE_MII_10]	 = PHY_INTERFACE_MODE_MII,
508 	[MV88E6185_PORT_STS_CMODE_SERDES]	 = PHY_INTERFACE_MODE_1000BASEX,
509 	[MV88E6185_PORT_STS_CMODE_1000BASE_X]	 = PHY_INTERFACE_MODE_1000BASEX,
510 	[MV88E6185_PORT_STS_CMODE_PHY]		 = PHY_INTERFACE_MODE_SGMII,
511 };
512 
513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
514 				       struct phylink_config *config)
515 {
516 	u8 cmode = chip->ports[port].cmode;
517 
518 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
519 
520 	if (mv88e6xxx_phy_is_internal(chip, port)) {
521 		__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
522 	} else {
523 		if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
524 		    mv88e6185_phy_interface_modes[cmode])
525 			__set_bit(mv88e6185_phy_interface_modes[cmode],
526 				  config->supported_interfaces);
527 
528 		config->mac_capabilities |= MAC_1000FD;
529 	}
530 }
531 
532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
533 				       struct phylink_config *config)
534 {
535 	u8 cmode = chip->ports[port].cmode;
536 
537 	if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
538 	    mv88e6185_phy_interface_modes[cmode])
539 		__set_bit(mv88e6185_phy_interface_modes[cmode],
540 			  config->supported_interfaces);
541 
542 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
543 				   MAC_1000FD;
544 }
545 
546 static const u8 mv88e6xxx_phy_interface_modes[] = {
547 	[MV88E6XXX_PORT_STS_CMODE_MII_PHY]	= PHY_INTERFACE_MODE_REVMII,
548 	[MV88E6XXX_PORT_STS_CMODE_MII]		= PHY_INTERFACE_MODE_MII,
549 	[MV88E6XXX_PORT_STS_CMODE_GMII]		= PHY_INTERFACE_MODE_GMII,
550 	[MV88E6XXX_PORT_STS_CMODE_RMII_PHY]	= PHY_INTERFACE_MODE_REVRMII,
551 	[MV88E6XXX_PORT_STS_CMODE_RMII]		= PHY_INTERFACE_MODE_RMII,
552 	[MV88E6XXX_PORT_STS_CMODE_100BASEX]	= PHY_INTERFACE_MODE_100BASEX,
553 	[MV88E6XXX_PORT_STS_CMODE_1000BASEX]	= PHY_INTERFACE_MODE_1000BASEX,
554 	[MV88E6XXX_PORT_STS_CMODE_SGMII]	= PHY_INTERFACE_MODE_SGMII,
555 	/* higher interface modes are not needed here, since ports supporting
556 	 * them are writable, and so the supported interfaces are filled in the
557 	 * corresponding .phylink_set_interfaces() implementation below
558 	 */
559 };
560 
561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
562 {
563 	if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
564 	    mv88e6xxx_phy_interface_modes[cmode])
565 		__set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
566 	else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
567 		phy_interface_set_rgmii(supported);
568 }
569 
570 static void
571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
572 				     struct phylink_config *config)
573 {
574 	unsigned long *supported = config->supported_interfaces;
575 	int err;
576 	u16 reg;
577 
578 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
579 	if (err) {
580 		dev_err(chip->dev, "p%d: failed to read port status\n", port);
581 		return;
582 	}
583 
584 	switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
585 	case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
586 	case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
587 	case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
588 	case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
589 		__set_bit(PHY_INTERFACE_MODE_REVMII, supported);
590 		break;
591 
592 	case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
593 	case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
594 		__set_bit(PHY_INTERFACE_MODE_MII, supported);
595 		break;
596 
597 	case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
598 	case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
599 	case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
600 	case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
601 		__set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
602 		break;
603 
604 	case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
605 	case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
606 		__set_bit(PHY_INTERFACE_MODE_RMII, supported);
607 		break;
608 
609 	case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
610 		__set_bit(PHY_INTERFACE_MODE_RGMII, supported);
611 		break;
612 
613 	default:
614 		dev_err(chip->dev,
615 			"p%d: invalid port mode in status register: %04x\n",
616 			port, reg);
617 	}
618 }
619 
620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
621 				       struct phylink_config *config)
622 {
623 	if (!mv88e6xxx_phy_is_internal(chip, port))
624 		mv88e6250_setup_supported_interfaces(chip, port, config);
625 
626 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
627 }
628 
629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
630 				       struct phylink_config *config)
631 {
632 	unsigned long *supported = config->supported_interfaces;
633 
634 	/* Translate the default cmode */
635 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
636 
637 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
638 				   MAC_1000FD;
639 }
640 
641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
642 {
643 	u16 reg, val;
644 	int err;
645 
646 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
647 	if (err)
648 		return err;
649 
650 	/* If PHY_DETECT is zero, then we are not in auto-media mode */
651 	if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
652 		return 0xf;
653 
654 	val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
655 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
656 	if (err)
657 		return err;
658 
659 	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
660 	if (err)
661 		return err;
662 
663 	/* Restore PHY_DETECT value */
664 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
665 	if (err)
666 		return err;
667 
668 	return val & MV88E6XXX_PORT_STS_CMODE_MASK;
669 }
670 
671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
672 				       struct phylink_config *config)
673 {
674 	unsigned long *supported = config->supported_interfaces;
675 	int err, cmode;
676 
677 	/* Translate the default cmode */
678 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
679 
680 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
681 				   MAC_1000FD;
682 
683 	/* Port 4 supports automedia if the serdes is associated with it. */
684 	if (port == 4) {
685 		err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
686 		if (err < 0)
687 			dev_err(chip->dev, "p%d: failed to read scratch\n",
688 				port);
689 		if (err <= 0)
690 			return;
691 
692 		cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
693 		if (cmode < 0)
694 			dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
695 				port);
696 		else
697 			mv88e6xxx_translate_cmode(cmode, supported);
698 	}
699 }
700 
701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
702 				       struct phylink_config *config)
703 {
704 	unsigned long *supported = config->supported_interfaces;
705 	int cmode;
706 
707 	/* Translate the default cmode */
708 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
709 
710 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
711 				   MAC_1000FD;
712 
713 	/* Port 0/1 are serdes only ports */
714 	if (port == 0 || port == 1) {
715 		cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
716 		if (cmode < 0)
717 			dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
718 				port);
719 		else
720 			mv88e6xxx_translate_cmode(cmode, supported);
721 	}
722 }
723 
724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
725 				       struct phylink_config *config)
726 {
727 	unsigned long *supported = config->supported_interfaces;
728 
729 	/* Translate the default cmode */
730 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
731 
732 	/* No ethtool bits for 200Mbps */
733 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
734 				   MAC_1000FD;
735 
736 	/* The C_Mode field is programmable on port 5 */
737 	if (port == 5) {
738 		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
739 		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
740 		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
741 
742 		config->mac_capabilities |= MAC_2500FD;
743 	}
744 }
745 
746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
747 				       struct phylink_config *config)
748 {
749 	unsigned long *supported = config->supported_interfaces;
750 
751 	/* Translate the default cmode */
752 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
753 
754 	/* No ethtool bits for 200Mbps */
755 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
756 				   MAC_1000FD;
757 
758 	/* The C_Mode field is programmable on ports 9 and 10 */
759 	if (port == 9 || port == 10) {
760 		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
761 		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
762 		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
763 
764 		config->mac_capabilities |= MAC_2500FD;
765 	}
766 }
767 
768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
769 					struct phylink_config *config)
770 {
771 	unsigned long *supported = config->supported_interfaces;
772 
773 	mv88e6390_phylink_get_caps(chip, port, config);
774 
775 	/* For the 6x90X, ports 2-7 can be in automedia mode.
776 	 * (Note that 6x90 doesn't support RXAUI nor XAUI).
777 	 *
778 	 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
779 	 * configured for 1000BASE-X, SGMII or 2500BASE-X.
780 	 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
781 	 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
782 	 *
783 	 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
784 	 * configured for 1000BASE-X, SGMII or 2500BASE-X.
785 	 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
786 	 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
787 	 *
788 	 * For now, be permissive (as the old code was) and allow 1000BASE-X
789 	 * on ports 2..7.
790 	 */
791 	if (port >= 2 && port <= 7)
792 		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
793 
794 	/* The C_Mode field can also be programmed for 10G speeds */
795 	if (port == 9 || port == 10) {
796 		__set_bit(PHY_INTERFACE_MODE_XAUI, supported);
797 		__set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
798 
799 		config->mac_capabilities |= MAC_10000FD;
800 	}
801 }
802 
803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
804 					struct phylink_config *config)
805 {
806 	unsigned long *supported = config->supported_interfaces;
807 	bool is_6191x =
808 		chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
809 	bool is_6361 =
810 		chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
811 
812 	mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
813 
814 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
815 				   MAC_1000FD;
816 
817 	/* The C_Mode field can be programmed for ports 0, 9 and 10 */
818 	if (port == 0 || port == 9 || port == 10) {
819 		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
820 		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
821 
822 		/* 6191X supports >1G modes only on port 10 */
823 		if (!is_6191x || port == 10) {
824 			__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
825 			config->mac_capabilities |= MAC_2500FD;
826 
827 			/* 6361 only supports up to 2500BaseX */
828 			if (!is_6361) {
829 				__set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
830 				__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
831 				__set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
832 				config->mac_capabilities |= MAC_5000FD |
833 					MAC_10000FD;
834 			}
835 		}
836 	}
837 
838 	if (port == 0) {
839 		__set_bit(PHY_INTERFACE_MODE_RMII, supported);
840 		__set_bit(PHY_INTERFACE_MODE_RGMII, supported);
841 		__set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
842 		__set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
843 		__set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
844 	}
845 }
846 
847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
848 			       struct phylink_config *config)
849 {
850 	struct mv88e6xxx_chip *chip = ds->priv;
851 
852 	mv88e6xxx_reg_lock(chip);
853 	chip->info->ops->phylink_get_caps(chip, port, config);
854 	mv88e6xxx_reg_unlock(chip);
855 
856 	if (mv88e6xxx_phy_is_internal(chip, port)) {
857 		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
858 			  config->supported_interfaces);
859 		/* Internal ports with no phy-mode need GMII for PHYLIB */
860 		__set_bit(PHY_INTERFACE_MODE_GMII,
861 			  config->supported_interfaces);
862 	}
863 }
864 
865 static struct phylink_pcs *
866 mv88e6xxx_mac_select_pcs(struct phylink_config *config,
867 			 phy_interface_t interface)
868 {
869 	struct dsa_port *dp = dsa_phylink_to_port(config);
870 	struct mv88e6xxx_chip *chip = dp->ds->priv;
871 	struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
872 
873 	if (chip->info->ops->pcs_ops)
874 		pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
875 							   interface);
876 
877 	return pcs;
878 }
879 
880 static int mv88e6xxx_mac_prepare(struct phylink_config *config,
881 				 unsigned int mode, phy_interface_t interface)
882 {
883 	struct dsa_port *dp = dsa_phylink_to_port(config);
884 	struct mv88e6xxx_chip *chip = dp->ds->priv;
885 	int port = dp->index;
886 	int err = 0;
887 
888 	/* In inband mode, the link may come up at any time while the link
889 	 * is not forced down. Force the link down while we reconfigure the
890 	 * interface mode.
891 	 */
892 	if (mode == MLO_AN_INBAND &&
893 	    chip->ports[port].interface != interface &&
894 	    chip->info->ops->port_set_link) {
895 		mv88e6xxx_reg_lock(chip);
896 		err = chip->info->ops->port_set_link(chip, port,
897 						     LINK_FORCED_DOWN);
898 		mv88e6xxx_reg_unlock(chip);
899 	}
900 
901 	return err;
902 }
903 
904 static void mv88e6xxx_mac_config(struct phylink_config *config,
905 				 unsigned int mode,
906 				 const struct phylink_link_state *state)
907 {
908 	struct dsa_port *dp = dsa_phylink_to_port(config);
909 	struct mv88e6xxx_chip *chip = dp->ds->priv;
910 	int port = dp->index;
911 	int err = 0;
912 
913 	mv88e6xxx_reg_lock(chip);
914 
915 	if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
916 		err = mv88e6xxx_port_config_interface(chip, port,
917 						      state->interface);
918 		if (err && err != -EOPNOTSUPP)
919 			goto err_unlock;
920 	}
921 
922 err_unlock:
923 	mv88e6xxx_reg_unlock(chip);
924 
925 	if (err && err != -EOPNOTSUPP)
926 		dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
927 }
928 
929 static int mv88e6xxx_mac_finish(struct phylink_config *config,
930 				unsigned int mode, phy_interface_t interface)
931 {
932 	struct dsa_port *dp = dsa_phylink_to_port(config);
933 	struct mv88e6xxx_chip *chip = dp->ds->priv;
934 	int port = dp->index;
935 	int err = 0;
936 
937 	/* Undo the forced down state above after completing configuration
938 	 * irrespective of its state on entry, which allows the link to come
939 	 * up in the in-band case where there is no separate SERDES. Also
940 	 * ensure that the link can come up if the PPU is in use and we are
941 	 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
942 	 */
943 	mv88e6xxx_reg_lock(chip);
944 
945 	if (chip->info->ops->port_set_link &&
946 	    ((mode == MLO_AN_INBAND &&
947 	      chip->ports[port].interface != interface) ||
948 	     (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
949 		err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
950 
951 	mv88e6xxx_reg_unlock(chip);
952 
953 	chip->ports[port].interface = interface;
954 
955 	return err;
956 }
957 
958 static void mv88e6xxx_mac_link_down(struct phylink_config *config,
959 				    unsigned int mode,
960 				    phy_interface_t interface)
961 {
962 	struct dsa_port *dp = dsa_phylink_to_port(config);
963 	struct mv88e6xxx_chip *chip = dp->ds->priv;
964 	const struct mv88e6xxx_ops *ops;
965 	int port = dp->index;
966 	int err = 0;
967 
968 	ops = chip->info->ops;
969 
970 	mv88e6xxx_reg_lock(chip);
971 	/* Force the link down if we know the port may not be automatically
972 	 * updated by the switch or if we are using fixed-link mode.
973 	 */
974 	if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
975 	     mode == MLO_AN_FIXED) && ops->port_sync_link)
976 		err = ops->port_sync_link(chip, port, mode, false);
977 
978 	if (!err && ops->port_set_speed_duplex)
979 		err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
980 						 DUPLEX_UNFORCED);
981 	mv88e6xxx_reg_unlock(chip);
982 
983 	if (err)
984 		dev_err(chip->dev,
985 			"p%d: failed to force MAC link down\n", port);
986 }
987 
988 static void mv88e6xxx_mac_link_up(struct phylink_config *config,
989 				  struct phy_device *phydev,
990 				  unsigned int mode, phy_interface_t interface,
991 				  int speed, int duplex,
992 				  bool tx_pause, bool rx_pause)
993 {
994 	struct dsa_port *dp = dsa_phylink_to_port(config);
995 	struct mv88e6xxx_chip *chip = dp->ds->priv;
996 	const struct mv88e6xxx_ops *ops;
997 	int port = dp->index;
998 	int err = 0;
999 
1000 	ops = chip->info->ops;
1001 
1002 	mv88e6xxx_reg_lock(chip);
1003 	/* Configure and force the link up if we know that the port may not
1004 	 * automatically updated by the switch or if we are using fixed-link
1005 	 * mode.
1006 	 */
1007 	if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1008 	    mode == MLO_AN_FIXED) {
1009 		if (ops->port_set_speed_duplex) {
1010 			err = ops->port_set_speed_duplex(chip, port,
1011 							 speed, duplex);
1012 			if (err && err != -EOPNOTSUPP)
1013 				goto error;
1014 		}
1015 
1016 		if (ops->port_sync_link)
1017 			err = ops->port_sync_link(chip, port, mode, true);
1018 	}
1019 error:
1020 	mv88e6xxx_reg_unlock(chip);
1021 
1022 	if (err && err != -EOPNOTSUPP)
1023 		dev_err(chip->dev,
1024 			"p%d: failed to configure MAC link up\n", port);
1025 }
1026 
1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1028 {
1029 	int err;
1030 
1031 	if (!chip->info->ops->stats_snapshot)
1032 		return -EOPNOTSUPP;
1033 
1034 	mv88e6xxx_reg_lock(chip);
1035 	err = chip->info->ops->stats_snapshot(chip, port);
1036 	mv88e6xxx_reg_unlock(chip);
1037 
1038 	return err;
1039 }
1040 
1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn)				    \
1042 	_fn(in_good_octets,		8, 0x00, STATS_TYPE_BANK0), \
1043 	_fn(in_bad_octets,		4, 0x02, STATS_TYPE_BANK0), \
1044 	_fn(in_unicast,			4, 0x04, STATS_TYPE_BANK0), \
1045 	_fn(in_broadcasts,		4, 0x06, STATS_TYPE_BANK0), \
1046 	_fn(in_multicasts,		4, 0x07, STATS_TYPE_BANK0), \
1047 	_fn(in_pause,			4, 0x16, STATS_TYPE_BANK0), \
1048 	_fn(in_undersize,		4, 0x18, STATS_TYPE_BANK0), \
1049 	_fn(in_fragments,		4, 0x19, STATS_TYPE_BANK0), \
1050 	_fn(in_oversize,		4, 0x1a, STATS_TYPE_BANK0), \
1051 	_fn(in_jabber,			4, 0x1b, STATS_TYPE_BANK0), \
1052 	_fn(in_rx_error,		4, 0x1c, STATS_TYPE_BANK0), \
1053 	_fn(in_fcs_error,		4, 0x1d, STATS_TYPE_BANK0), \
1054 	_fn(out_octets,			8, 0x0e, STATS_TYPE_BANK0), \
1055 	_fn(out_unicast,		4, 0x10, STATS_TYPE_BANK0), \
1056 	_fn(out_broadcasts,		4, 0x13, STATS_TYPE_BANK0), \
1057 	_fn(out_multicasts,		4, 0x12, STATS_TYPE_BANK0), \
1058 	_fn(out_pause,			4, 0x15, STATS_TYPE_BANK0), \
1059 	_fn(excessive,			4, 0x11, STATS_TYPE_BANK0), \
1060 	_fn(collisions,			4, 0x1e, STATS_TYPE_BANK0), \
1061 	_fn(deferred,			4, 0x05, STATS_TYPE_BANK0), \
1062 	_fn(single,			4, 0x14, STATS_TYPE_BANK0), \
1063 	_fn(multiple,			4, 0x17, STATS_TYPE_BANK0), \
1064 	_fn(out_fcs_error,		4, 0x03, STATS_TYPE_BANK0), \
1065 	_fn(late,			4, 0x1f, STATS_TYPE_BANK0), \
1066 	_fn(hist_64bytes,		4, 0x08, STATS_TYPE_BANK0), \
1067 	_fn(hist_65_127bytes,		4, 0x09, STATS_TYPE_BANK0), \
1068 	_fn(hist_128_255bytes,		4, 0x0a, STATS_TYPE_BANK0), \
1069 	_fn(hist_256_511bytes,		4, 0x0b, STATS_TYPE_BANK0), \
1070 	_fn(hist_512_1023bytes,		4, 0x0c, STATS_TYPE_BANK0), \
1071 	_fn(hist_1024_max_bytes,	4, 0x0d, STATS_TYPE_BANK0), \
1072 	_fn(sw_in_discards,		4, 0x10, STATS_TYPE_PORT), \
1073 	_fn(sw_in_filtered,		2, 0x12, STATS_TYPE_PORT), \
1074 	_fn(sw_out_filtered,		2, 0x13, STATS_TYPE_PORT), \
1075 	_fn(in_discards,		4, 0x00, STATS_TYPE_BANK1), \
1076 	_fn(in_filtered,		4, 0x01, STATS_TYPE_BANK1), \
1077 	_fn(in_accepted,		4, 0x02, STATS_TYPE_BANK1), \
1078 	_fn(in_bad_accepted,		4, 0x03, STATS_TYPE_BANK1), \
1079 	_fn(in_good_avb_class_a,	4, 0x04, STATS_TYPE_BANK1), \
1080 	_fn(in_good_avb_class_b,	4, 0x05, STATS_TYPE_BANK1), \
1081 	_fn(in_bad_avb_class_a,		4, 0x06, STATS_TYPE_BANK1), \
1082 	_fn(in_bad_avb_class_b,		4, 0x07, STATS_TYPE_BANK1), \
1083 	_fn(tcam_counter_0,		4, 0x08, STATS_TYPE_BANK1), \
1084 	_fn(tcam_counter_1,		4, 0x09, STATS_TYPE_BANK1), \
1085 	_fn(tcam_counter_2,		4, 0x0a, STATS_TYPE_BANK1), \
1086 	_fn(tcam_counter_3,		4, 0x0b, STATS_TYPE_BANK1), \
1087 	_fn(in_da_unknown,		4, 0x0e, STATS_TYPE_BANK1), \
1088 	_fn(in_management,		4, 0x0f, STATS_TYPE_BANK1), \
1089 	_fn(out_queue_0,		4, 0x10, STATS_TYPE_BANK1), \
1090 	_fn(out_queue_1,		4, 0x11, STATS_TYPE_BANK1), \
1091 	_fn(out_queue_2,		4, 0x12, STATS_TYPE_BANK1), \
1092 	_fn(out_queue_3,		4, 0x13, STATS_TYPE_BANK1), \
1093 	_fn(out_queue_4,		4, 0x14, STATS_TYPE_BANK1), \
1094 	_fn(out_queue_5,		4, 0x15, STATS_TYPE_BANK1), \
1095 	_fn(out_queue_6,		4, 0x16, STATS_TYPE_BANK1), \
1096 	_fn(out_queue_7,		4, 0x17, STATS_TYPE_BANK1), \
1097 	_fn(out_cut_through,		4, 0x18, STATS_TYPE_BANK1), \
1098 	_fn(out_octets_a,		4, 0x1a, STATS_TYPE_BANK1), \
1099 	_fn(out_octets_b,		4, 0x1b, STATS_TYPE_BANK1), \
1100 	_fn(out_management,		4, 0x1f, STATS_TYPE_BANK1), \
1101 	/*  */
1102 
1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1104 	{ #_string, _size, _reg, _type }
1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1106 	MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1107 };
1108 
1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1110 	MV88E6XXX_HW_STAT_ID_ ## _string
1111 enum mv88e6xxx_hw_stat_id {
1112 	MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1113 };
1114 
1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1116 					    const struct mv88e6xxx_hw_stat *s,
1117 					    int port, u16 bank1_select,
1118 					    u16 histogram)
1119 {
1120 	u32 low;
1121 	u32 high = 0;
1122 	u16 reg = 0;
1123 	int err;
1124 	u64 value;
1125 
1126 	switch (s->type) {
1127 	case STATS_TYPE_PORT:
1128 		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1129 		if (err)
1130 			return U64_MAX;
1131 
1132 		low = reg;
1133 		if (s->size == 4) {
1134 			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1135 			if (err)
1136 				return U64_MAX;
1137 			low |= ((u32)reg) << 16;
1138 		}
1139 		break;
1140 	case STATS_TYPE_BANK1:
1141 		reg = bank1_select;
1142 		fallthrough;
1143 	case STATS_TYPE_BANK0:
1144 		reg |= s->reg | histogram;
1145 		mv88e6xxx_g1_stats_read(chip, reg, &low);
1146 		if (s->size == 8)
1147 			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1148 		break;
1149 	default:
1150 		return U64_MAX;
1151 	}
1152 	value = (((u64)high) << 32) | low;
1153 	return value;
1154 }
1155 
1156 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1157 				       uint8_t *data, int types)
1158 {
1159 	const struct mv88e6xxx_hw_stat *stat;
1160 	int i, j;
1161 
1162 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1163 		stat = &mv88e6xxx_hw_stats[i];
1164 		if (stat->type & types) {
1165 			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1166 			       ETH_GSTRING_LEN);
1167 			j++;
1168 		}
1169 	}
1170 
1171 	return j;
1172 }
1173 
1174 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1175 				       uint8_t *data)
1176 {
1177 	return mv88e6xxx_stats_get_strings(chip, data,
1178 					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1179 }
1180 
1181 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1182 				       uint8_t *data)
1183 {
1184 	return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1185 }
1186 
1187 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1188 				       uint8_t *data)
1189 {
1190 	return mv88e6xxx_stats_get_strings(chip, data,
1191 					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1192 }
1193 
1194 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1195 	"atu_member_violation",
1196 	"atu_miss_violation",
1197 	"atu_full_violation",
1198 	"vtu_member_violation",
1199 	"vtu_miss_violation",
1200 };
1201 
1202 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1203 {
1204 	unsigned int i;
1205 
1206 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1207 		strscpy(data + i * ETH_GSTRING_LEN,
1208 			mv88e6xxx_atu_vtu_stats_strings[i],
1209 			ETH_GSTRING_LEN);
1210 }
1211 
1212 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1213 				  u32 stringset, uint8_t *data)
1214 {
1215 	struct mv88e6xxx_chip *chip = ds->priv;
1216 	int count = 0;
1217 
1218 	if (stringset != ETH_SS_STATS)
1219 		return;
1220 
1221 	mv88e6xxx_reg_lock(chip);
1222 
1223 	if (chip->info->ops->stats_get_strings)
1224 		count = chip->info->ops->stats_get_strings(chip, data);
1225 
1226 	if (chip->info->ops->serdes_get_strings) {
1227 		data += count * ETH_GSTRING_LEN;
1228 		count = chip->info->ops->serdes_get_strings(chip, port, data);
1229 	}
1230 
1231 	data += count * ETH_GSTRING_LEN;
1232 	mv88e6xxx_atu_vtu_get_strings(data);
1233 
1234 	mv88e6xxx_reg_unlock(chip);
1235 }
1236 
1237 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1238 					  int types)
1239 {
1240 	const struct mv88e6xxx_hw_stat *stat;
1241 	int i, j;
1242 
1243 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1244 		stat = &mv88e6xxx_hw_stats[i];
1245 		if (stat->type & types)
1246 			j++;
1247 	}
1248 	return j;
1249 }
1250 
1251 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1252 {
1253 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1254 					      STATS_TYPE_PORT);
1255 }
1256 
1257 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1258 {
1259 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1260 }
1261 
1262 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1263 {
1264 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1265 					      STATS_TYPE_BANK1);
1266 }
1267 
1268 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1269 {
1270 	struct mv88e6xxx_chip *chip = ds->priv;
1271 	int serdes_count = 0;
1272 	int count = 0;
1273 
1274 	if (sset != ETH_SS_STATS)
1275 		return 0;
1276 
1277 	mv88e6xxx_reg_lock(chip);
1278 	if (chip->info->ops->stats_get_sset_count)
1279 		count = chip->info->ops->stats_get_sset_count(chip);
1280 	if (count < 0)
1281 		goto out;
1282 
1283 	if (chip->info->ops->serdes_get_sset_count)
1284 		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1285 								      port);
1286 	if (serdes_count < 0) {
1287 		count = serdes_count;
1288 		goto out;
1289 	}
1290 	count += serdes_count;
1291 	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1292 
1293 out:
1294 	mv88e6xxx_reg_unlock(chip);
1295 
1296 	return count;
1297 }
1298 
1299 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1300 				       const struct mv88e6xxx_hw_stat *stat,
1301 				       uint64_t *data)
1302 {
1303 	if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1304 		return 0;
1305 
1306 	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1307 					    MV88E6XXX_G1_STATS_OP_HIST_RX);
1308 	return 1;
1309 }
1310 
1311 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1312 				       const struct mv88e6xxx_hw_stat *stat,
1313 				       uint64_t *data)
1314 {
1315 	if (!(stat->type & STATS_TYPE_BANK0))
1316 		return 0;
1317 
1318 	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1319 					    MV88E6XXX_G1_STATS_OP_HIST_RX);
1320 	return 1;
1321 }
1322 
1323 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1324 				       const struct mv88e6xxx_hw_stat *stat,
1325 				       uint64_t *data)
1326 {
1327 	if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1328 		return 0;
1329 
1330 	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1331 					    MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1332 					    MV88E6XXX_G1_STATS_OP_HIST_RX);
1333 	return 1;
1334 }
1335 
1336 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1337 				       const struct mv88e6xxx_hw_stat *stat,
1338 				       uint64_t *data)
1339 {
1340 	if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1341 		return 0;
1342 
1343 	*data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1344 					    MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1345 					    0);
1346 	return 1;
1347 }
1348 
1349 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1350 				       const struct mv88e6xxx_hw_stat *stat,
1351 				       uint64_t *data)
1352 {
1353 	int ret = 0;
1354 
1355 	if (chip->info->ops->stats_get_stat) {
1356 		mv88e6xxx_reg_lock(chip);
1357 		ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1358 		mv88e6xxx_reg_unlock(chip);
1359 	}
1360 
1361 	return ret;
1362 }
1363 
1364 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1365 					uint64_t *data)
1366 {
1367 	const struct mv88e6xxx_hw_stat *stat;
1368 	size_t i, j;
1369 
1370 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1371 		stat = &mv88e6xxx_hw_stats[i];
1372 		j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1373 	}
1374 	return j;
1375 }
1376 
1377 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1378 					uint64_t *data)
1379 {
1380 	*data++ = chip->ports[port].atu_member_violation;
1381 	*data++ = chip->ports[port].atu_miss_violation;
1382 	*data++ = chip->ports[port].atu_full_violation;
1383 	*data++ = chip->ports[port].vtu_member_violation;
1384 	*data++ = chip->ports[port].vtu_miss_violation;
1385 }
1386 
1387 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1388 				uint64_t *data)
1389 {
1390 	size_t count;
1391 
1392 	count = mv88e6xxx_stats_get_stats(chip, port, data);
1393 
1394 	mv88e6xxx_reg_lock(chip);
1395 	if (chip->info->ops->serdes_get_stats) {
1396 		data += count;
1397 		count = chip->info->ops->serdes_get_stats(chip, port, data);
1398 	}
1399 	data += count;
1400 	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1401 	mv88e6xxx_reg_unlock(chip);
1402 }
1403 
1404 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1405 					uint64_t *data)
1406 {
1407 	struct mv88e6xxx_chip *chip = ds->priv;
1408 	int ret;
1409 
1410 	ret = mv88e6xxx_stats_snapshot(chip, port);
1411 	if (ret < 0)
1412 		return;
1413 
1414 	mv88e6xxx_get_stats(chip, port, data);
1415 }
1416 
1417 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1418 					struct ethtool_eth_mac_stats *mac_stats)
1419 {
1420 	struct mv88e6xxx_chip *chip = ds->priv;
1421 	int ret;
1422 
1423 	ret = mv88e6xxx_stats_snapshot(chip, port);
1424 	if (ret < 0)
1425 		return;
1426 
1427 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member)			\
1428 	mv88e6xxx_stats_get_stat(chip, port,				\
1429 				 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1430 				 &mac_stats->stats._member)
1431 
1432 	MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1433 	MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1434 	MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1435 	MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1436 	MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1437 	MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1438 	MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1439 	MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1440 	MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1441 	MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1442 	MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1443 	MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1444 	MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1445 	MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1446 
1447 #undef MV88E6XXX_ETH_MAC_STAT_MAP
1448 
1449 	mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1450 	mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1451 	mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1452 	mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1453 }
1454 
1455 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1456 				     struct ethtool_rmon_stats *rmon_stats,
1457 				     const struct ethtool_rmon_hist_range **ranges)
1458 {
1459 	static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1460 		{   64,    64 },
1461 		{   65,   127 },
1462 		{  128,   255 },
1463 		{  256,   511 },
1464 		{  512,  1023 },
1465 		{ 1024, 65535 },
1466 		{}
1467 	};
1468 	struct mv88e6xxx_chip *chip = ds->priv;
1469 	int ret;
1470 
1471 	ret = mv88e6xxx_stats_snapshot(chip, port);
1472 	if (ret < 0)
1473 		return;
1474 
1475 #define MV88E6XXX_RMON_STAT_MAP(_id, _member)				\
1476 	mv88e6xxx_stats_get_stat(chip, port,				\
1477 				 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1478 				 &rmon_stats->stats._member)
1479 
1480 	MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1481 	MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1482 	MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1483 	MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1484 	MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1485 	MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1486 	MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1487 	MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1488 	MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1489 	MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1490 
1491 #undef MV88E6XXX_RMON_STAT_MAP
1492 
1493 	*ranges = rmon_ranges;
1494 }
1495 
1496 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1497 {
1498 	struct mv88e6xxx_chip *chip = ds->priv;
1499 	int len;
1500 
1501 	len = 32 * sizeof(u16);
1502 	if (chip->info->ops->serdes_get_regs_len)
1503 		len += chip->info->ops->serdes_get_regs_len(chip, port);
1504 
1505 	return len;
1506 }
1507 
1508 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1509 			       struct ethtool_regs *regs, void *_p)
1510 {
1511 	struct mv88e6xxx_chip *chip = ds->priv;
1512 	int err;
1513 	u16 reg;
1514 	u16 *p = _p;
1515 	int i;
1516 
1517 	regs->version = chip->info->prod_num;
1518 
1519 	memset(p, 0xff, 32 * sizeof(u16));
1520 
1521 	mv88e6xxx_reg_lock(chip);
1522 
1523 	for (i = 0; i < 32; i++) {
1524 
1525 		err = mv88e6xxx_port_read(chip, port, i, &reg);
1526 		if (!err)
1527 			p[i] = reg;
1528 	}
1529 
1530 	if (chip->info->ops->serdes_get_regs)
1531 		chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1532 
1533 	mv88e6xxx_reg_unlock(chip);
1534 }
1535 
1536 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1537 				 struct ethtool_keee *e)
1538 {
1539 	/* Nothing to do on the port's MAC */
1540 	return 0;
1541 }
1542 
1543 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1544 				 struct ethtool_keee *e)
1545 {
1546 	/* Nothing to do on the port's MAC */
1547 	return 0;
1548 }
1549 
1550 /* Mask of the local ports allowed to receive frames from a given fabric port */
1551 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1552 {
1553 	struct dsa_switch *ds = chip->ds;
1554 	struct dsa_switch_tree *dst = ds->dst;
1555 	struct dsa_port *dp, *other_dp;
1556 	bool found = false;
1557 	u16 pvlan;
1558 
1559 	/* dev is a physical switch */
1560 	if (dev <= dst->last_switch) {
1561 		list_for_each_entry(dp, &dst->ports, list) {
1562 			if (dp->ds->index == dev && dp->index == port) {
1563 				/* dp might be a DSA link or a user port, so it
1564 				 * might or might not have a bridge.
1565 				 * Use the "found" variable for both cases.
1566 				 */
1567 				found = true;
1568 				break;
1569 			}
1570 		}
1571 	/* dev is a virtual bridge */
1572 	} else {
1573 		list_for_each_entry(dp, &dst->ports, list) {
1574 			unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1575 
1576 			if (!bridge_num)
1577 				continue;
1578 
1579 			if (bridge_num + dst->last_switch != dev)
1580 				continue;
1581 
1582 			found = true;
1583 			break;
1584 		}
1585 	}
1586 
1587 	/* Prevent frames from unknown switch or virtual bridge */
1588 	if (!found)
1589 		return 0;
1590 
1591 	/* Frames from DSA links and CPU ports can egress any local port */
1592 	if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1593 		return mv88e6xxx_port_mask(chip);
1594 
1595 	pvlan = 0;
1596 
1597 	/* Frames from standalone user ports can only egress on the
1598 	 * upstream port.
1599 	 */
1600 	if (!dsa_port_bridge_dev_get(dp))
1601 		return BIT(dsa_switch_upstream_port(ds));
1602 
1603 	/* Frames from bridged user ports can egress any local DSA
1604 	 * links and CPU ports, as well as any local member of their
1605 	 * bridge group.
1606 	 */
1607 	dsa_switch_for_each_port(other_dp, ds)
1608 		if (other_dp->type == DSA_PORT_TYPE_CPU ||
1609 		    other_dp->type == DSA_PORT_TYPE_DSA ||
1610 		    dsa_port_bridge_same(dp, other_dp))
1611 			pvlan |= BIT(other_dp->index);
1612 
1613 	return pvlan;
1614 }
1615 
1616 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1617 {
1618 	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1619 
1620 	/* prevent frames from going back out of the port they came in on */
1621 	output_ports &= ~BIT(port);
1622 
1623 	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1624 }
1625 
1626 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1627 					 u8 state)
1628 {
1629 	struct mv88e6xxx_chip *chip = ds->priv;
1630 	int err;
1631 
1632 	mv88e6xxx_reg_lock(chip);
1633 	err = mv88e6xxx_port_set_state(chip, port, state);
1634 	mv88e6xxx_reg_unlock(chip);
1635 
1636 	if (err)
1637 		dev_err(ds->dev, "p%d: failed to update state\n", port);
1638 }
1639 
1640 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1641 {
1642 	int err;
1643 
1644 	if (chip->info->ops->ieee_pri_map) {
1645 		err = chip->info->ops->ieee_pri_map(chip);
1646 		if (err)
1647 			return err;
1648 	}
1649 
1650 	if (chip->info->ops->ip_pri_map) {
1651 		err = chip->info->ops->ip_pri_map(chip);
1652 		if (err)
1653 			return err;
1654 	}
1655 
1656 	return 0;
1657 }
1658 
1659 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1660 {
1661 	struct dsa_switch *ds = chip->ds;
1662 	int target, port;
1663 	int err;
1664 
1665 	if (!chip->info->global2_addr)
1666 		return 0;
1667 
1668 	/* Initialize the routing port to the 32 possible target devices */
1669 	for (target = 0; target < 32; target++) {
1670 		port = dsa_routing_port(ds, target);
1671 		if (port == ds->num_ports)
1672 			port = 0x1f;
1673 
1674 		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1675 		if (err)
1676 			return err;
1677 	}
1678 
1679 	if (chip->info->ops->set_cascade_port) {
1680 		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1681 		err = chip->info->ops->set_cascade_port(chip, port);
1682 		if (err)
1683 			return err;
1684 	}
1685 
1686 	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1687 	if (err)
1688 		return err;
1689 
1690 	return 0;
1691 }
1692 
1693 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1694 {
1695 	/* Clear all trunk masks and mapping */
1696 	if (chip->info->global2_addr)
1697 		return mv88e6xxx_g2_trunk_clear(chip);
1698 
1699 	return 0;
1700 }
1701 
1702 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1703 {
1704 	if (chip->info->ops->rmu_disable)
1705 		return chip->info->ops->rmu_disable(chip);
1706 
1707 	return 0;
1708 }
1709 
1710 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1711 {
1712 	if (chip->info->ops->pot_clear)
1713 		return chip->info->ops->pot_clear(chip);
1714 
1715 	return 0;
1716 }
1717 
1718 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1719 {
1720 	if (chip->info->ops->mgmt_rsvd2cpu)
1721 		return chip->info->ops->mgmt_rsvd2cpu(chip);
1722 
1723 	return 0;
1724 }
1725 
1726 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1727 {
1728 	int err;
1729 
1730 	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1731 	if (err)
1732 		return err;
1733 
1734 	/* The chips that have a "learn2all" bit in Global1, ATU
1735 	 * Control are precisely those whose port registers have a
1736 	 * Message Port bit in Port Control 1 and hence implement
1737 	 * ->port_setup_message_port.
1738 	 */
1739 	if (chip->info->ops->port_setup_message_port) {
1740 		err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1741 		if (err)
1742 			return err;
1743 	}
1744 
1745 	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1746 }
1747 
1748 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1749 {
1750 	int port;
1751 	int err;
1752 
1753 	if (!chip->info->ops->irl_init_all)
1754 		return 0;
1755 
1756 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1757 		/* Disable ingress rate limiting by resetting all per port
1758 		 * ingress rate limit resources to their initial state.
1759 		 */
1760 		err = chip->info->ops->irl_init_all(chip, port);
1761 		if (err)
1762 			return err;
1763 	}
1764 
1765 	return 0;
1766 }
1767 
1768 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1769 {
1770 	if (chip->info->ops->set_switch_mac) {
1771 		u8 addr[ETH_ALEN];
1772 
1773 		eth_random_addr(addr);
1774 
1775 		return chip->info->ops->set_switch_mac(chip, addr);
1776 	}
1777 
1778 	return 0;
1779 }
1780 
1781 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1782 {
1783 	struct dsa_switch_tree *dst = chip->ds->dst;
1784 	struct dsa_switch *ds;
1785 	struct dsa_port *dp;
1786 	u16 pvlan = 0;
1787 
1788 	if (!mv88e6xxx_has_pvt(chip))
1789 		return 0;
1790 
1791 	/* Skip the local source device, which uses in-chip port VLAN */
1792 	if (dev != chip->ds->index) {
1793 		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1794 
1795 		ds = dsa_switch_find(dst->index, dev);
1796 		dp = ds ? dsa_to_port(ds, port) : NULL;
1797 		if (dp && dp->lag) {
1798 			/* As the PVT is used to limit flooding of
1799 			 * FORWARD frames, which use the LAG ID as the
1800 			 * source port, we must translate dev/port to
1801 			 * the special "LAG device" in the PVT, using
1802 			 * the LAG ID (one-based) as the port number
1803 			 * (zero-based).
1804 			 */
1805 			dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1806 			port = dsa_port_lag_id_get(dp) - 1;
1807 		}
1808 	}
1809 
1810 	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1811 }
1812 
1813 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1814 {
1815 	int dev, port;
1816 	int err;
1817 
1818 	if (!mv88e6xxx_has_pvt(chip))
1819 		return 0;
1820 
1821 	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
1822 	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1823 	 */
1824 	err = mv88e6xxx_g2_misc_4_bit_port(chip);
1825 	if (err)
1826 		return err;
1827 
1828 	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1829 		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1830 			err = mv88e6xxx_pvt_map(chip, dev, port);
1831 			if (err)
1832 				return err;
1833 		}
1834 	}
1835 
1836 	return 0;
1837 }
1838 
1839 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1840 				       u16 fid)
1841 {
1842 	if (dsa_to_port(chip->ds, port)->lag)
1843 		/* Hardware is incapable of fast-aging a LAG through a
1844 		 * regular ATU move operation. Until we have something
1845 		 * more fancy in place this is a no-op.
1846 		 */
1847 		return -EOPNOTSUPP;
1848 
1849 	return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1850 }
1851 
1852 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1853 {
1854 	struct mv88e6xxx_chip *chip = ds->priv;
1855 	int err;
1856 
1857 	mv88e6xxx_reg_lock(chip);
1858 	err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1859 	mv88e6xxx_reg_unlock(chip);
1860 
1861 	if (err)
1862 		dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1863 			port, err);
1864 }
1865 
1866 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1867 {
1868 	if (!mv88e6xxx_max_vid(chip))
1869 		return 0;
1870 
1871 	return mv88e6xxx_g1_vtu_flush(chip);
1872 }
1873 
1874 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1875 			     struct mv88e6xxx_vtu_entry *entry)
1876 {
1877 	int err;
1878 
1879 	if (!chip->info->ops->vtu_getnext)
1880 		return -EOPNOTSUPP;
1881 
1882 	entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1883 	entry->valid = false;
1884 
1885 	err = chip->info->ops->vtu_getnext(chip, entry);
1886 
1887 	if (entry->vid != vid)
1888 		entry->valid = false;
1889 
1890 	return err;
1891 }
1892 
1893 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1894 		       int (*cb)(struct mv88e6xxx_chip *chip,
1895 				 const struct mv88e6xxx_vtu_entry *entry,
1896 				 void *priv),
1897 		       void *priv)
1898 {
1899 	struct mv88e6xxx_vtu_entry entry = {
1900 		.vid = mv88e6xxx_max_vid(chip),
1901 		.valid = false,
1902 	};
1903 	int err;
1904 
1905 	if (!chip->info->ops->vtu_getnext)
1906 		return -EOPNOTSUPP;
1907 
1908 	do {
1909 		err = chip->info->ops->vtu_getnext(chip, &entry);
1910 		if (err)
1911 			return err;
1912 
1913 		if (!entry.valid)
1914 			break;
1915 
1916 		err = cb(chip, &entry, priv);
1917 		if (err)
1918 			return err;
1919 	} while (entry.vid < mv88e6xxx_max_vid(chip));
1920 
1921 	return 0;
1922 }
1923 
1924 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1925 				   struct mv88e6xxx_vtu_entry *entry)
1926 {
1927 	if (!chip->info->ops->vtu_loadpurge)
1928 		return -EOPNOTSUPP;
1929 
1930 	return chip->info->ops->vtu_loadpurge(chip, entry);
1931 }
1932 
1933 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1934 				  const struct mv88e6xxx_vtu_entry *entry,
1935 				  void *_fid_bitmap)
1936 {
1937 	unsigned long *fid_bitmap = _fid_bitmap;
1938 
1939 	set_bit(entry->fid, fid_bitmap);
1940 	return 0;
1941 }
1942 
1943 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1944 {
1945 	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1946 
1947 	/* Every FID has an associated VID, so walking the VTU
1948 	 * will discover the full set of FIDs in use.
1949 	 */
1950 	return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1951 }
1952 
1953 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1954 {
1955 	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1956 	int err;
1957 
1958 	err = mv88e6xxx_fid_map(chip, fid_bitmap);
1959 	if (err)
1960 		return err;
1961 
1962 	*fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1963 	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1964 		return -ENOSPC;
1965 
1966 	/* Clear the database */
1967 	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1968 }
1969 
1970 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1971 				   struct mv88e6xxx_stu_entry *entry)
1972 {
1973 	if (!chip->info->ops->stu_loadpurge)
1974 		return -EOPNOTSUPP;
1975 
1976 	return chip->info->ops->stu_loadpurge(chip, entry);
1977 }
1978 
1979 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1980 {
1981 	struct mv88e6xxx_stu_entry stu = {
1982 		.valid = true,
1983 		.sid = 0
1984 	};
1985 
1986 	if (!mv88e6xxx_has_stu(chip))
1987 		return 0;
1988 
1989 	/* Make sure that SID 0 is always valid. This is used by VTU
1990 	 * entries that do not make use of the STU, e.g. when creating
1991 	 * a VLAN upper on a port that is also part of a VLAN
1992 	 * filtering bridge.
1993 	 */
1994 	return mv88e6xxx_stu_loadpurge(chip, &stu);
1995 }
1996 
1997 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1998 {
1999 	DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
2000 	struct mv88e6xxx_mst *mst;
2001 
2002 	__set_bit(0, busy);
2003 
2004 	list_for_each_entry(mst, &chip->msts, node)
2005 		__set_bit(mst->stu.sid, busy);
2006 
2007 	*sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
2008 
2009 	return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
2010 }
2011 
2012 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
2013 {
2014 	struct mv88e6xxx_mst *mst, *tmp;
2015 	int err;
2016 
2017 	if (!sid)
2018 		return 0;
2019 
2020 	list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
2021 		if (mst->stu.sid != sid)
2022 			continue;
2023 
2024 		if (!refcount_dec_and_test(&mst->refcnt))
2025 			return 0;
2026 
2027 		mst->stu.valid = false;
2028 		err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2029 		if (err) {
2030 			refcount_set(&mst->refcnt, 1);
2031 			return err;
2032 		}
2033 
2034 		list_del(&mst->node);
2035 		kfree(mst);
2036 		return 0;
2037 	}
2038 
2039 	return -ENOENT;
2040 }
2041 
2042 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2043 			     u16 msti, u8 *sid)
2044 {
2045 	struct mv88e6xxx_mst *mst;
2046 	int err, i;
2047 
2048 	if (!mv88e6xxx_has_stu(chip)) {
2049 		err = -EOPNOTSUPP;
2050 		goto err;
2051 	}
2052 
2053 	if (!msti) {
2054 		*sid = 0;
2055 		return 0;
2056 	}
2057 
2058 	list_for_each_entry(mst, &chip->msts, node) {
2059 		if (mst->br == br && mst->msti == msti) {
2060 			refcount_inc(&mst->refcnt);
2061 			*sid = mst->stu.sid;
2062 			return 0;
2063 		}
2064 	}
2065 
2066 	err = mv88e6xxx_sid_get(chip, sid);
2067 	if (err)
2068 		goto err;
2069 
2070 	mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2071 	if (!mst) {
2072 		err = -ENOMEM;
2073 		goto err;
2074 	}
2075 
2076 	INIT_LIST_HEAD(&mst->node);
2077 	refcount_set(&mst->refcnt, 1);
2078 	mst->br = br;
2079 	mst->msti = msti;
2080 	mst->stu.valid = true;
2081 	mst->stu.sid = *sid;
2082 
2083 	/* The bridge starts out all ports in the disabled state. But
2084 	 * a STU state of disabled means to go by the port-global
2085 	 * state. So we set all user port's initial state to blocking,
2086 	 * to match the bridge's behavior.
2087 	 */
2088 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2089 		mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2090 			MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2091 			MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2092 
2093 	err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2094 	if (err)
2095 		goto err_free;
2096 
2097 	list_add_tail(&mst->node, &chip->msts);
2098 	return 0;
2099 
2100 err_free:
2101 	kfree(mst);
2102 err:
2103 	return err;
2104 }
2105 
2106 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2107 					const struct switchdev_mst_state *st)
2108 {
2109 	struct dsa_port *dp = dsa_to_port(ds, port);
2110 	struct mv88e6xxx_chip *chip = ds->priv;
2111 	struct mv88e6xxx_mst *mst;
2112 	u8 state;
2113 	int err;
2114 
2115 	if (!mv88e6xxx_has_stu(chip))
2116 		return -EOPNOTSUPP;
2117 
2118 	switch (st->state) {
2119 	case BR_STATE_DISABLED:
2120 	case BR_STATE_BLOCKING:
2121 	case BR_STATE_LISTENING:
2122 		state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2123 		break;
2124 	case BR_STATE_LEARNING:
2125 		state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2126 		break;
2127 	case BR_STATE_FORWARDING:
2128 		state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2129 		break;
2130 	default:
2131 		return -EINVAL;
2132 	}
2133 
2134 	list_for_each_entry(mst, &chip->msts, node) {
2135 		if (mst->br == dsa_port_bridge_dev_get(dp) &&
2136 		    mst->msti == st->msti) {
2137 			if (mst->stu.state[port] == state)
2138 				return 0;
2139 
2140 			mst->stu.state[port] = state;
2141 			mv88e6xxx_reg_lock(chip);
2142 			err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2143 			mv88e6xxx_reg_unlock(chip);
2144 			return err;
2145 		}
2146 	}
2147 
2148 	return -ENOENT;
2149 }
2150 
2151 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2152 					u16 vid)
2153 {
2154 	struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2155 	struct mv88e6xxx_chip *chip = ds->priv;
2156 	struct mv88e6xxx_vtu_entry vlan;
2157 	int err;
2158 
2159 	/* DSA and CPU ports have to be members of multiple vlans */
2160 	if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2161 		return 0;
2162 
2163 	err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2164 	if (err)
2165 		return err;
2166 
2167 	if (!vlan.valid)
2168 		return 0;
2169 
2170 	dsa_switch_for_each_user_port(other_dp, ds) {
2171 		struct net_device *other_br;
2172 
2173 		if (vlan.member[other_dp->index] ==
2174 		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2175 			continue;
2176 
2177 		if (dsa_port_bridge_same(dp, other_dp))
2178 			break; /* same bridge, check next VLAN */
2179 
2180 		other_br = dsa_port_bridge_dev_get(other_dp);
2181 		if (!other_br)
2182 			continue;
2183 
2184 		dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2185 			port, vlan.vid, other_dp->index, netdev_name(other_br));
2186 		return -EOPNOTSUPP;
2187 	}
2188 
2189 	return 0;
2190 }
2191 
2192 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2193 {
2194 	struct dsa_port *dp = dsa_to_port(chip->ds, port);
2195 	struct net_device *br = dsa_port_bridge_dev_get(dp);
2196 	struct mv88e6xxx_port *p = &chip->ports[port];
2197 	u16 pvid = MV88E6XXX_VID_STANDALONE;
2198 	bool drop_untagged = false;
2199 	int err;
2200 
2201 	if (br) {
2202 		if (br_vlan_enabled(br)) {
2203 			pvid = p->bridge_pvid.vid;
2204 			drop_untagged = !p->bridge_pvid.valid;
2205 		} else {
2206 			pvid = MV88E6XXX_VID_BRIDGED;
2207 		}
2208 	}
2209 
2210 	err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2211 	if (err)
2212 		return err;
2213 
2214 	return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2215 }
2216 
2217 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2218 					 bool vlan_filtering,
2219 					 struct netlink_ext_ack *extack)
2220 {
2221 	struct mv88e6xxx_chip *chip = ds->priv;
2222 	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2223 		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2224 	int err;
2225 
2226 	if (!mv88e6xxx_max_vid(chip))
2227 		return -EOPNOTSUPP;
2228 
2229 	mv88e6xxx_reg_lock(chip);
2230 
2231 	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2232 	if (err)
2233 		goto unlock;
2234 
2235 	err = mv88e6xxx_port_commit_pvid(chip, port);
2236 	if (err)
2237 		goto unlock;
2238 
2239 unlock:
2240 	mv88e6xxx_reg_unlock(chip);
2241 
2242 	return err;
2243 }
2244 
2245 static int
2246 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2247 			    const struct switchdev_obj_port_vlan *vlan)
2248 {
2249 	struct mv88e6xxx_chip *chip = ds->priv;
2250 	int err;
2251 
2252 	if (!mv88e6xxx_max_vid(chip))
2253 		return -EOPNOTSUPP;
2254 
2255 	/* If the requested port doesn't belong to the same bridge as the VLAN
2256 	 * members, do not support it (yet) and fallback to software VLAN.
2257 	 */
2258 	mv88e6xxx_reg_lock(chip);
2259 	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2260 	mv88e6xxx_reg_unlock(chip);
2261 
2262 	return err;
2263 }
2264 
2265 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2266 					const unsigned char *addr, u16 vid,
2267 					u8 state)
2268 {
2269 	struct mv88e6xxx_atu_entry entry;
2270 	struct mv88e6xxx_vtu_entry vlan;
2271 	u16 fid;
2272 	int err;
2273 
2274 	/* Ports have two private address databases: one for when the port is
2275 	 * standalone and one for when the port is under a bridge and the
2276 	 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2277 	 * address database to remain 100% empty, so we never load an ATU entry
2278 	 * into a standalone port's database. Therefore, translate the null
2279 	 * VLAN ID into the port's database used for VLAN-unaware bridging.
2280 	 */
2281 	if (vid == 0) {
2282 		fid = MV88E6XXX_FID_BRIDGED;
2283 	} else {
2284 		err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2285 		if (err)
2286 			return err;
2287 
2288 		/* switchdev expects -EOPNOTSUPP to honor software VLANs */
2289 		if (!vlan.valid)
2290 			return -EOPNOTSUPP;
2291 
2292 		fid = vlan.fid;
2293 	}
2294 
2295 	entry.state = 0;
2296 	ether_addr_copy(entry.mac, addr);
2297 	eth_addr_dec(entry.mac);
2298 
2299 	err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2300 	if (err)
2301 		return err;
2302 
2303 	/* Initialize a fresh ATU entry if it isn't found */
2304 	if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2305 		memset(&entry, 0, sizeof(entry));
2306 		ether_addr_copy(entry.mac, addr);
2307 	}
2308 
2309 	/* Purge the ATU entry only if no port is using it anymore */
2310 	if (!state) {
2311 		entry.portvec &= ~BIT(port);
2312 		if (!entry.portvec)
2313 			entry.state = 0;
2314 	} else {
2315 		if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2316 			entry.portvec = BIT(port);
2317 		else
2318 			entry.portvec |= BIT(port);
2319 
2320 		entry.state = state;
2321 	}
2322 
2323 	return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2324 }
2325 
2326 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2327 				  const struct mv88e6xxx_policy *policy)
2328 {
2329 	enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2330 	enum mv88e6xxx_policy_action action = policy->action;
2331 	const u8 *addr = policy->addr;
2332 	u16 vid = policy->vid;
2333 	u8 state;
2334 	int err;
2335 	int id;
2336 
2337 	if (!chip->info->ops->port_set_policy)
2338 		return -EOPNOTSUPP;
2339 
2340 	switch (mapping) {
2341 	case MV88E6XXX_POLICY_MAPPING_DA:
2342 	case MV88E6XXX_POLICY_MAPPING_SA:
2343 		if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2344 			state = 0; /* Dissociate the port and address */
2345 		else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2346 			 is_multicast_ether_addr(addr))
2347 			state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2348 		else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2349 			 is_unicast_ether_addr(addr))
2350 			state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2351 		else
2352 			return -EOPNOTSUPP;
2353 
2354 		err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2355 						   state);
2356 		if (err)
2357 			return err;
2358 		break;
2359 	default:
2360 		return -EOPNOTSUPP;
2361 	}
2362 
2363 	/* Skip the port's policy clearing if the mapping is still in use */
2364 	if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2365 		idr_for_each_entry(&chip->policies, policy, id)
2366 			if (policy->port == port &&
2367 			    policy->mapping == mapping &&
2368 			    policy->action != action)
2369 				return 0;
2370 
2371 	return chip->info->ops->port_set_policy(chip, port, mapping, action);
2372 }
2373 
2374 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2375 				   struct ethtool_rx_flow_spec *fs)
2376 {
2377 	struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2378 	struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2379 	enum mv88e6xxx_policy_mapping mapping;
2380 	enum mv88e6xxx_policy_action action;
2381 	struct mv88e6xxx_policy *policy;
2382 	u16 vid = 0;
2383 	u8 *addr;
2384 	int err;
2385 	int id;
2386 
2387 	if (fs->location != RX_CLS_LOC_ANY)
2388 		return -EINVAL;
2389 
2390 	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2391 		action = MV88E6XXX_POLICY_ACTION_DISCARD;
2392 	else
2393 		return -EOPNOTSUPP;
2394 
2395 	switch (fs->flow_type & ~FLOW_EXT) {
2396 	case ETHER_FLOW:
2397 		if (!is_zero_ether_addr(mac_mask->h_dest) &&
2398 		    is_zero_ether_addr(mac_mask->h_source)) {
2399 			mapping = MV88E6XXX_POLICY_MAPPING_DA;
2400 			addr = mac_entry->h_dest;
2401 		} else if (is_zero_ether_addr(mac_mask->h_dest) &&
2402 		    !is_zero_ether_addr(mac_mask->h_source)) {
2403 			mapping = MV88E6XXX_POLICY_MAPPING_SA;
2404 			addr = mac_entry->h_source;
2405 		} else {
2406 			/* Cannot support DA and SA mapping in the same rule */
2407 			return -EOPNOTSUPP;
2408 		}
2409 		break;
2410 	default:
2411 		return -EOPNOTSUPP;
2412 	}
2413 
2414 	if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2415 		if (fs->m_ext.vlan_tci != htons(0xffff))
2416 			return -EOPNOTSUPP;
2417 		vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2418 	}
2419 
2420 	idr_for_each_entry(&chip->policies, policy, id) {
2421 		if (policy->port == port && policy->mapping == mapping &&
2422 		    policy->action == action && policy->vid == vid &&
2423 		    ether_addr_equal(policy->addr, addr))
2424 			return -EEXIST;
2425 	}
2426 
2427 	policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2428 	if (!policy)
2429 		return -ENOMEM;
2430 
2431 	fs->location = 0;
2432 	err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2433 			    GFP_KERNEL);
2434 	if (err) {
2435 		devm_kfree(chip->dev, policy);
2436 		return err;
2437 	}
2438 
2439 	memcpy(&policy->fs, fs, sizeof(*fs));
2440 	ether_addr_copy(policy->addr, addr);
2441 	policy->mapping = mapping;
2442 	policy->action = action;
2443 	policy->port = port;
2444 	policy->vid = vid;
2445 
2446 	err = mv88e6xxx_policy_apply(chip, port, policy);
2447 	if (err) {
2448 		idr_remove(&chip->policies, fs->location);
2449 		devm_kfree(chip->dev, policy);
2450 		return err;
2451 	}
2452 
2453 	return 0;
2454 }
2455 
2456 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2457 			       struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2458 {
2459 	struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2460 	struct mv88e6xxx_chip *chip = ds->priv;
2461 	struct mv88e6xxx_policy *policy;
2462 	int err;
2463 	int id;
2464 
2465 	mv88e6xxx_reg_lock(chip);
2466 
2467 	switch (rxnfc->cmd) {
2468 	case ETHTOOL_GRXCLSRLCNT:
2469 		rxnfc->data = 0;
2470 		rxnfc->data |= RX_CLS_LOC_SPECIAL;
2471 		rxnfc->rule_cnt = 0;
2472 		idr_for_each_entry(&chip->policies, policy, id)
2473 			if (policy->port == port)
2474 				rxnfc->rule_cnt++;
2475 		err = 0;
2476 		break;
2477 	case ETHTOOL_GRXCLSRULE:
2478 		err = -ENOENT;
2479 		policy = idr_find(&chip->policies, fs->location);
2480 		if (policy) {
2481 			memcpy(fs, &policy->fs, sizeof(*fs));
2482 			err = 0;
2483 		}
2484 		break;
2485 	case ETHTOOL_GRXCLSRLALL:
2486 		rxnfc->data = 0;
2487 		rxnfc->rule_cnt = 0;
2488 		idr_for_each_entry(&chip->policies, policy, id)
2489 			if (policy->port == port)
2490 				rule_locs[rxnfc->rule_cnt++] = id;
2491 		err = 0;
2492 		break;
2493 	default:
2494 		err = -EOPNOTSUPP;
2495 		break;
2496 	}
2497 
2498 	mv88e6xxx_reg_unlock(chip);
2499 
2500 	return err;
2501 }
2502 
2503 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2504 			       struct ethtool_rxnfc *rxnfc)
2505 {
2506 	struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2507 	struct mv88e6xxx_chip *chip = ds->priv;
2508 	struct mv88e6xxx_policy *policy;
2509 	int err;
2510 
2511 	mv88e6xxx_reg_lock(chip);
2512 
2513 	switch (rxnfc->cmd) {
2514 	case ETHTOOL_SRXCLSRLINS:
2515 		err = mv88e6xxx_policy_insert(chip, port, fs);
2516 		break;
2517 	case ETHTOOL_SRXCLSRLDEL:
2518 		err = -ENOENT;
2519 		policy = idr_remove(&chip->policies, fs->location);
2520 		if (policy) {
2521 			policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2522 			err = mv88e6xxx_policy_apply(chip, port, policy);
2523 			devm_kfree(chip->dev, policy);
2524 		}
2525 		break;
2526 	default:
2527 		err = -EOPNOTSUPP;
2528 		break;
2529 	}
2530 
2531 	mv88e6xxx_reg_unlock(chip);
2532 
2533 	return err;
2534 }
2535 
2536 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2537 					u16 vid)
2538 {
2539 	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2540 	u8 broadcast[ETH_ALEN];
2541 
2542 	eth_broadcast_addr(broadcast);
2543 
2544 	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2545 }
2546 
2547 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2548 {
2549 	int port;
2550 	int err;
2551 
2552 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2553 		struct dsa_port *dp = dsa_to_port(chip->ds, port);
2554 		struct net_device *brport;
2555 
2556 		if (dsa_is_unused_port(chip->ds, port))
2557 			continue;
2558 
2559 		brport = dsa_port_to_bridge_port(dp);
2560 		if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2561 			/* Skip bridged user ports where broadcast
2562 			 * flooding is disabled.
2563 			 */
2564 			continue;
2565 
2566 		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2567 		if (err)
2568 			return err;
2569 	}
2570 
2571 	return 0;
2572 }
2573 
2574 struct mv88e6xxx_port_broadcast_sync_ctx {
2575 	int port;
2576 	bool flood;
2577 };
2578 
2579 static int
2580 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2581 				   const struct mv88e6xxx_vtu_entry *vlan,
2582 				   void *_ctx)
2583 {
2584 	struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2585 	u8 broadcast[ETH_ALEN];
2586 	u8 state;
2587 
2588 	if (ctx->flood)
2589 		state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2590 	else
2591 		state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2592 
2593 	eth_broadcast_addr(broadcast);
2594 
2595 	return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2596 					    vlan->vid, state);
2597 }
2598 
2599 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2600 					 bool flood)
2601 {
2602 	struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2603 		.port = port,
2604 		.flood = flood,
2605 	};
2606 	struct mv88e6xxx_vtu_entry vid0 = {
2607 		.vid = 0,
2608 	};
2609 	int err;
2610 
2611 	/* Update the port's private database... */
2612 	err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2613 	if (err)
2614 		return err;
2615 
2616 	/* ...and the database for all VLANs. */
2617 	return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2618 				  &ctx);
2619 }
2620 
2621 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2622 				    u16 vid, u8 member, bool warn)
2623 {
2624 	const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2625 	struct mv88e6xxx_vtu_entry vlan;
2626 	int i, err;
2627 
2628 	err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2629 	if (err)
2630 		return err;
2631 
2632 	if (!vlan.valid) {
2633 		memset(&vlan, 0, sizeof(vlan));
2634 
2635 		if (vid == MV88E6XXX_VID_STANDALONE)
2636 			vlan.policy = true;
2637 
2638 		err = mv88e6xxx_atu_new(chip, &vlan.fid);
2639 		if (err)
2640 			return err;
2641 
2642 		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2643 			if (i == port)
2644 				vlan.member[i] = member;
2645 			else
2646 				vlan.member[i] = non_member;
2647 
2648 		vlan.vid = vid;
2649 		vlan.valid = true;
2650 
2651 		err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2652 		if (err)
2653 			return err;
2654 
2655 		err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2656 		if (err)
2657 			return err;
2658 	} else if (vlan.member[port] != member) {
2659 		vlan.member[port] = member;
2660 
2661 		err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2662 		if (err)
2663 			return err;
2664 	} else if (warn) {
2665 		dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2666 			 port, vid);
2667 	}
2668 
2669 	return 0;
2670 }
2671 
2672 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2673 				   const struct switchdev_obj_port_vlan *vlan,
2674 				   struct netlink_ext_ack *extack)
2675 {
2676 	struct mv88e6xxx_chip *chip = ds->priv;
2677 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2678 	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2679 	struct mv88e6xxx_port *p = &chip->ports[port];
2680 	bool warn;
2681 	u8 member;
2682 	int err;
2683 
2684 	if (!vlan->vid)
2685 		return 0;
2686 
2687 	err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2688 	if (err)
2689 		return err;
2690 
2691 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2692 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2693 	else if (untagged)
2694 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2695 	else
2696 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2697 
2698 	/* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2699 	 * and then the CPU port. Do not warn for duplicates for the CPU port.
2700 	 */
2701 	warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2702 
2703 	mv88e6xxx_reg_lock(chip);
2704 
2705 	err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2706 	if (err) {
2707 		dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2708 			vlan->vid, untagged ? 'u' : 't');
2709 		goto out;
2710 	}
2711 
2712 	if (pvid) {
2713 		p->bridge_pvid.vid = vlan->vid;
2714 		p->bridge_pvid.valid = true;
2715 
2716 		err = mv88e6xxx_port_commit_pvid(chip, port);
2717 		if (err)
2718 			goto out;
2719 	} else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2720 		/* The old pvid was reinstalled as a non-pvid VLAN */
2721 		p->bridge_pvid.valid = false;
2722 
2723 		err = mv88e6xxx_port_commit_pvid(chip, port);
2724 		if (err)
2725 			goto out;
2726 	}
2727 
2728 out:
2729 	mv88e6xxx_reg_unlock(chip);
2730 
2731 	return err;
2732 }
2733 
2734 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2735 				     int port, u16 vid)
2736 {
2737 	struct mv88e6xxx_vtu_entry vlan;
2738 	int i, err;
2739 
2740 	if (!vid)
2741 		return 0;
2742 
2743 	err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2744 	if (err)
2745 		return err;
2746 
2747 	/* If the VLAN doesn't exist in hardware or the port isn't a member,
2748 	 * tell switchdev that this VLAN is likely handled in software.
2749 	 */
2750 	if (!vlan.valid ||
2751 	    vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2752 		return -EOPNOTSUPP;
2753 
2754 	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2755 
2756 	/* keep the VLAN unless all ports are excluded */
2757 	vlan.valid = false;
2758 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2759 		if (vlan.member[i] !=
2760 		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2761 			vlan.valid = true;
2762 			break;
2763 		}
2764 	}
2765 
2766 	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2767 	if (err)
2768 		return err;
2769 
2770 	if (!vlan.valid) {
2771 		err = mv88e6xxx_mst_put(chip, vlan.sid);
2772 		if (err)
2773 			return err;
2774 	}
2775 
2776 	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2777 }
2778 
2779 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2780 				   const struct switchdev_obj_port_vlan *vlan)
2781 {
2782 	struct mv88e6xxx_chip *chip = ds->priv;
2783 	struct mv88e6xxx_port *p = &chip->ports[port];
2784 	int err = 0;
2785 	u16 pvid;
2786 
2787 	if (!mv88e6xxx_max_vid(chip))
2788 		return -EOPNOTSUPP;
2789 
2790 	/* The ATU removal procedure needs the FID to be mapped in the VTU,
2791 	 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2792 	 * switchdev workqueue to ensure that all FDB entries are deleted
2793 	 * before we remove the VLAN.
2794 	 */
2795 	dsa_flush_workqueue();
2796 
2797 	mv88e6xxx_reg_lock(chip);
2798 
2799 	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2800 	if (err)
2801 		goto unlock;
2802 
2803 	err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2804 	if (err)
2805 		goto unlock;
2806 
2807 	if (vlan->vid == pvid) {
2808 		p->bridge_pvid.valid = false;
2809 
2810 		err = mv88e6xxx_port_commit_pvid(chip, port);
2811 		if (err)
2812 			goto unlock;
2813 	}
2814 
2815 unlock:
2816 	mv88e6xxx_reg_unlock(chip);
2817 
2818 	return err;
2819 }
2820 
2821 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2822 {
2823 	struct mv88e6xxx_chip *chip = ds->priv;
2824 	struct mv88e6xxx_vtu_entry vlan;
2825 	int err;
2826 
2827 	mv88e6xxx_reg_lock(chip);
2828 
2829 	err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2830 	if (err)
2831 		goto unlock;
2832 
2833 	err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2834 
2835 unlock:
2836 	mv88e6xxx_reg_unlock(chip);
2837 
2838 	return err;
2839 }
2840 
2841 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2842 				   struct dsa_bridge bridge,
2843 				   const struct switchdev_vlan_msti *msti)
2844 {
2845 	struct mv88e6xxx_chip *chip = ds->priv;
2846 	struct mv88e6xxx_vtu_entry vlan;
2847 	u8 old_sid, new_sid;
2848 	int err;
2849 
2850 	if (!mv88e6xxx_has_stu(chip))
2851 		return -EOPNOTSUPP;
2852 
2853 	mv88e6xxx_reg_lock(chip);
2854 
2855 	err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2856 	if (err)
2857 		goto unlock;
2858 
2859 	if (!vlan.valid) {
2860 		err = -EINVAL;
2861 		goto unlock;
2862 	}
2863 
2864 	old_sid = vlan.sid;
2865 
2866 	err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2867 	if (err)
2868 		goto unlock;
2869 
2870 	if (new_sid != old_sid) {
2871 		vlan.sid = new_sid;
2872 
2873 		err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2874 		if (err) {
2875 			mv88e6xxx_mst_put(chip, new_sid);
2876 			goto unlock;
2877 		}
2878 	}
2879 
2880 	err = mv88e6xxx_mst_put(chip, old_sid);
2881 
2882 unlock:
2883 	mv88e6xxx_reg_unlock(chip);
2884 	return err;
2885 }
2886 
2887 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2888 				  const unsigned char *addr, u16 vid,
2889 				  struct dsa_db db)
2890 {
2891 	struct mv88e6xxx_chip *chip = ds->priv;
2892 	int err;
2893 
2894 	mv88e6xxx_reg_lock(chip);
2895 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2896 					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2897 	mv88e6xxx_reg_unlock(chip);
2898 
2899 	return err;
2900 }
2901 
2902 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2903 				  const unsigned char *addr, u16 vid,
2904 				  struct dsa_db db)
2905 {
2906 	struct mv88e6xxx_chip *chip = ds->priv;
2907 	int err;
2908 
2909 	mv88e6xxx_reg_lock(chip);
2910 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2911 	mv88e6xxx_reg_unlock(chip);
2912 
2913 	return err;
2914 }
2915 
2916 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2917 				      u16 fid, u16 vid, int port,
2918 				      dsa_fdb_dump_cb_t *cb, void *data)
2919 {
2920 	struct mv88e6xxx_atu_entry addr;
2921 	bool is_static;
2922 	int err;
2923 
2924 	addr.state = 0;
2925 	eth_broadcast_addr(addr.mac);
2926 
2927 	do {
2928 		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2929 		if (err)
2930 			return err;
2931 
2932 		if (!addr.state)
2933 			break;
2934 
2935 		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2936 			continue;
2937 
2938 		if (!is_unicast_ether_addr(addr.mac))
2939 			continue;
2940 
2941 		is_static = (addr.state ==
2942 			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2943 		err = cb(addr.mac, vid, is_static, data);
2944 		if (err)
2945 			return err;
2946 	} while (!is_broadcast_ether_addr(addr.mac));
2947 
2948 	return err;
2949 }
2950 
2951 struct mv88e6xxx_port_db_dump_vlan_ctx {
2952 	int port;
2953 	dsa_fdb_dump_cb_t *cb;
2954 	void *data;
2955 };
2956 
2957 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2958 				       const struct mv88e6xxx_vtu_entry *entry,
2959 				       void *_data)
2960 {
2961 	struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2962 
2963 	return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2964 					  ctx->port, ctx->cb, ctx->data);
2965 }
2966 
2967 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2968 				  dsa_fdb_dump_cb_t *cb, void *data)
2969 {
2970 	struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2971 		.port = port,
2972 		.cb = cb,
2973 		.data = data,
2974 	};
2975 	u16 fid;
2976 	int err;
2977 
2978 	/* Dump port's default Filtering Information Database (VLAN ID 0) */
2979 	err = mv88e6xxx_port_get_fid(chip, port, &fid);
2980 	if (err)
2981 		return err;
2982 
2983 	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2984 	if (err)
2985 		return err;
2986 
2987 	return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2988 }
2989 
2990 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2991 				   dsa_fdb_dump_cb_t *cb, void *data)
2992 {
2993 	struct mv88e6xxx_chip *chip = ds->priv;
2994 	int err;
2995 
2996 	mv88e6xxx_reg_lock(chip);
2997 	err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2998 	mv88e6xxx_reg_unlock(chip);
2999 
3000 	return err;
3001 }
3002 
3003 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
3004 				struct dsa_bridge bridge)
3005 {
3006 	struct dsa_switch *ds = chip->ds;
3007 	struct dsa_switch_tree *dst = ds->dst;
3008 	struct dsa_port *dp;
3009 	int err;
3010 
3011 	list_for_each_entry(dp, &dst->ports, list) {
3012 		if (dsa_port_offloads_bridge(dp, &bridge)) {
3013 			if (dp->ds == ds) {
3014 				/* This is a local bridge group member,
3015 				 * remap its Port VLAN Map.
3016 				 */
3017 				err = mv88e6xxx_port_vlan_map(chip, dp->index);
3018 				if (err)
3019 					return err;
3020 			} else {
3021 				/* This is an external bridge group member,
3022 				 * remap its cross-chip Port VLAN Table entry.
3023 				 */
3024 				err = mv88e6xxx_pvt_map(chip, dp->ds->index,
3025 							dp->index);
3026 				if (err)
3027 					return err;
3028 			}
3029 		}
3030 	}
3031 
3032 	return 0;
3033 }
3034 
3035 /* Treat the software bridge as a virtual single-port switch behind the
3036  * CPU and map in the PVT. First dst->last_switch elements are taken by
3037  * physical switches, so start from beyond that range.
3038  */
3039 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3040 					       unsigned int bridge_num)
3041 {
3042 	u8 dev = bridge_num + ds->dst->last_switch;
3043 	struct mv88e6xxx_chip *chip = ds->priv;
3044 
3045 	return mv88e6xxx_pvt_map(chip, dev, 0);
3046 }
3047 
3048 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3049 				      struct dsa_bridge bridge,
3050 				      bool *tx_fwd_offload,
3051 				      struct netlink_ext_ack *extack)
3052 {
3053 	struct mv88e6xxx_chip *chip = ds->priv;
3054 	int err;
3055 
3056 	mv88e6xxx_reg_lock(chip);
3057 
3058 	err = mv88e6xxx_bridge_map(chip, bridge);
3059 	if (err)
3060 		goto unlock;
3061 
3062 	err = mv88e6xxx_port_set_map_da(chip, port, true);
3063 	if (err)
3064 		goto unlock;
3065 
3066 	err = mv88e6xxx_port_commit_pvid(chip, port);
3067 	if (err)
3068 		goto unlock;
3069 
3070 	if (mv88e6xxx_has_pvt(chip)) {
3071 		err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3072 		if (err)
3073 			goto unlock;
3074 
3075 		*tx_fwd_offload = true;
3076 	}
3077 
3078 unlock:
3079 	mv88e6xxx_reg_unlock(chip);
3080 
3081 	return err;
3082 }
3083 
3084 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3085 					struct dsa_bridge bridge)
3086 {
3087 	struct mv88e6xxx_chip *chip = ds->priv;
3088 	int err;
3089 
3090 	mv88e6xxx_reg_lock(chip);
3091 
3092 	if (bridge.tx_fwd_offload &&
3093 	    mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3094 		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3095 
3096 	if (mv88e6xxx_bridge_map(chip, bridge) ||
3097 	    mv88e6xxx_port_vlan_map(chip, port))
3098 		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3099 
3100 	err = mv88e6xxx_port_set_map_da(chip, port, false);
3101 	if (err)
3102 		dev_err(ds->dev,
3103 			"port %d failed to restore map-DA: %pe\n",
3104 			port, ERR_PTR(err));
3105 
3106 	err = mv88e6xxx_port_commit_pvid(chip, port);
3107 	if (err)
3108 		dev_err(ds->dev,
3109 			"port %d failed to restore standalone pvid: %pe\n",
3110 			port, ERR_PTR(err));
3111 
3112 	mv88e6xxx_reg_unlock(chip);
3113 }
3114 
3115 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3116 					   int tree_index, int sw_index,
3117 					   int port, struct dsa_bridge bridge,
3118 					   struct netlink_ext_ack *extack)
3119 {
3120 	struct mv88e6xxx_chip *chip = ds->priv;
3121 	int err;
3122 
3123 	if (tree_index != ds->dst->index)
3124 		return 0;
3125 
3126 	mv88e6xxx_reg_lock(chip);
3127 	err = mv88e6xxx_pvt_map(chip, sw_index, port);
3128 	err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3129 	mv88e6xxx_reg_unlock(chip);
3130 
3131 	return err;
3132 }
3133 
3134 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3135 					     int tree_index, int sw_index,
3136 					     int port, struct dsa_bridge bridge)
3137 {
3138 	struct mv88e6xxx_chip *chip = ds->priv;
3139 
3140 	if (tree_index != ds->dst->index)
3141 		return;
3142 
3143 	mv88e6xxx_reg_lock(chip);
3144 	if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3145 	    mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3146 		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3147 	mv88e6xxx_reg_unlock(chip);
3148 }
3149 
3150 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3151 {
3152 	if (chip->info->ops->reset)
3153 		return chip->info->ops->reset(chip);
3154 
3155 	return 0;
3156 }
3157 
3158 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3159 {
3160 	struct gpio_desc *gpiod = chip->reset;
3161 	int err;
3162 
3163 	/* If there is a GPIO connected to the reset pin, toggle it */
3164 	if (gpiod) {
3165 		/* If the switch has just been reset and not yet completed
3166 		 * loading EEPROM, the reset may interrupt the I2C transaction
3167 		 * mid-byte, causing the first EEPROM read after the reset
3168 		 * from the wrong location resulting in the switch booting
3169 		 * to wrong mode and inoperable.
3170 		 * For this reason, switch families with EEPROM support
3171 		 * generally wait for EEPROM loads to complete as their pre-
3172 		 * and post-reset handlers.
3173 		 */
3174 		if (chip->info->ops->hardware_reset_pre) {
3175 			err = chip->info->ops->hardware_reset_pre(chip);
3176 			if (err)
3177 				dev_err(chip->dev, "pre-reset error: %d\n", err);
3178 		}
3179 
3180 		gpiod_set_value_cansleep(gpiod, 1);
3181 		usleep_range(10000, 20000);
3182 		gpiod_set_value_cansleep(gpiod, 0);
3183 		usleep_range(10000, 20000);
3184 
3185 		if (chip->info->ops->hardware_reset_post) {
3186 			err = chip->info->ops->hardware_reset_post(chip);
3187 			if (err)
3188 				dev_err(chip->dev, "post-reset error: %d\n", err);
3189 		}
3190 	}
3191 }
3192 
3193 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3194 {
3195 	int i, err;
3196 
3197 	/* Set all ports to the Disabled state */
3198 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3199 		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3200 		if (err)
3201 			return err;
3202 	}
3203 
3204 	/* Wait for transmit queues to drain,
3205 	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3206 	 */
3207 	usleep_range(2000, 4000);
3208 
3209 	return 0;
3210 }
3211 
3212 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3213 {
3214 	int err;
3215 
3216 	err = mv88e6xxx_disable_ports(chip);
3217 	if (err)
3218 		return err;
3219 
3220 	mv88e6xxx_hardware_reset(chip);
3221 
3222 	return mv88e6xxx_software_reset(chip);
3223 }
3224 
3225 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3226 				   enum mv88e6xxx_frame_mode frame,
3227 				   enum mv88e6xxx_egress_mode egress, u16 etype)
3228 {
3229 	int err;
3230 
3231 	if (!chip->info->ops->port_set_frame_mode)
3232 		return -EOPNOTSUPP;
3233 
3234 	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3235 	if (err)
3236 		return err;
3237 
3238 	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3239 	if (err)
3240 		return err;
3241 
3242 	if (chip->info->ops->port_set_ether_type)
3243 		return chip->info->ops->port_set_ether_type(chip, port, etype);
3244 
3245 	return 0;
3246 }
3247 
3248 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3249 {
3250 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3251 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3252 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3253 }
3254 
3255 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3256 {
3257 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3258 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3259 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3260 }
3261 
3262 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3263 {
3264 	return mv88e6xxx_set_port_mode(chip, port,
3265 				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
3266 				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3267 				       ETH_P_EDSA);
3268 }
3269 
3270 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3271 {
3272 	if (dsa_is_dsa_port(chip->ds, port))
3273 		return mv88e6xxx_set_port_mode_dsa(chip, port);
3274 
3275 	if (dsa_is_user_port(chip->ds, port))
3276 		return mv88e6xxx_set_port_mode_normal(chip, port);
3277 
3278 	/* Setup CPU port mode depending on its supported tag format */
3279 	if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3280 		return mv88e6xxx_set_port_mode_dsa(chip, port);
3281 
3282 	if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3283 		return mv88e6xxx_set_port_mode_edsa(chip, port);
3284 
3285 	return -EINVAL;
3286 }
3287 
3288 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3289 {
3290 	bool message = dsa_is_dsa_port(chip->ds, port);
3291 
3292 	return mv88e6xxx_port_set_message_port(chip, port, message);
3293 }
3294 
3295 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3296 {
3297 	int err;
3298 
3299 	if (chip->info->ops->port_set_ucast_flood) {
3300 		err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3301 		if (err)
3302 			return err;
3303 	}
3304 	if (chip->info->ops->port_set_mcast_flood) {
3305 		err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3306 		if (err)
3307 			return err;
3308 	}
3309 
3310 	return 0;
3311 }
3312 
3313 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3314 				     enum mv88e6xxx_egress_direction direction,
3315 				     int port)
3316 {
3317 	int err;
3318 
3319 	if (!chip->info->ops->set_egress_port)
3320 		return -EOPNOTSUPP;
3321 
3322 	err = chip->info->ops->set_egress_port(chip, direction, port);
3323 	if (err)
3324 		return err;
3325 
3326 	if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3327 		chip->ingress_dest_port = port;
3328 	else
3329 		chip->egress_dest_port = port;
3330 
3331 	return 0;
3332 }
3333 
3334 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3335 {
3336 	struct dsa_switch *ds = chip->ds;
3337 	int upstream_port;
3338 	int err;
3339 
3340 	upstream_port = dsa_upstream_port(ds, port);
3341 	if (chip->info->ops->port_set_upstream_port) {
3342 		err = chip->info->ops->port_set_upstream_port(chip, port,
3343 							      upstream_port);
3344 		if (err)
3345 			return err;
3346 	}
3347 
3348 	if (port == upstream_port) {
3349 		if (chip->info->ops->set_cpu_port) {
3350 			err = chip->info->ops->set_cpu_port(chip,
3351 							    upstream_port);
3352 			if (err)
3353 				return err;
3354 		}
3355 
3356 		err = mv88e6xxx_set_egress_port(chip,
3357 						MV88E6XXX_EGRESS_DIR_INGRESS,
3358 						upstream_port);
3359 		if (err && err != -EOPNOTSUPP)
3360 			return err;
3361 
3362 		err = mv88e6xxx_set_egress_port(chip,
3363 						MV88E6XXX_EGRESS_DIR_EGRESS,
3364 						upstream_port);
3365 		if (err && err != -EOPNOTSUPP)
3366 			return err;
3367 	}
3368 
3369 	return 0;
3370 }
3371 
3372 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3373 {
3374 	struct device_node *phy_handle = NULL;
3375 	struct fwnode_handle *ports_fwnode;
3376 	struct fwnode_handle *port_fwnode;
3377 	struct dsa_switch *ds = chip->ds;
3378 	struct mv88e6xxx_port *p;
3379 	struct dsa_port *dp;
3380 	int tx_amp;
3381 	int err;
3382 	u16 reg;
3383 	u32 val;
3384 
3385 	p = &chip->ports[port];
3386 	p->chip = chip;
3387 	p->port = port;
3388 
3389 	/* Look up corresponding fwnode if any */
3390 	ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports");
3391 	if (!ports_fwnode)
3392 		ports_fwnode = device_get_named_child_node(chip->dev, "ports");
3393 	if (ports_fwnode) {
3394 		fwnode_for_each_child_node(ports_fwnode, port_fwnode) {
3395 			if (fwnode_property_read_u32(port_fwnode, "reg", &val))
3396 				continue;
3397 			if (val == port) {
3398 				p->fwnode = port_fwnode;
3399 				p->fiber = fwnode_property_present(port_fwnode, "sfp");
3400 				break;
3401 			}
3402 		}
3403 	} else {
3404 		dev_dbg(chip->dev, "no ethernet ports node defined for the device\n");
3405 	}
3406 
3407 	if (chip->info->ops->port_setup_leds) {
3408 		err = chip->info->ops->port_setup_leds(chip, port);
3409 		if (err && err != -EOPNOTSUPP)
3410 			return err;
3411 	}
3412 
3413 	err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3414 				       SPEED_UNFORCED, DUPLEX_UNFORCED,
3415 				       PAUSE_ON, PHY_INTERFACE_MODE_NA);
3416 	if (err)
3417 		return err;
3418 
3419 	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3420 	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3421 	 * tunneling, determine priority by looking at 802.1p and IP
3422 	 * priority fields (IP prio has precedence), and set STP state
3423 	 * to Forwarding.
3424 	 *
3425 	 * If this is the CPU link, use DSA or EDSA tagging depending
3426 	 * on which tagging mode was configured.
3427 	 *
3428 	 * If this is a link to another switch, use DSA tagging mode.
3429 	 *
3430 	 * If this is the upstream port for this switch, enable
3431 	 * forwarding of unknown unicasts and multicasts.
3432 	 */
3433 	reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3434 		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3435 	/* Forward any IPv4 IGMP or IPv6 MLD frames received
3436 	 * by a USER port to the CPU port to allow snooping.
3437 	 */
3438 	if (dsa_is_user_port(ds, port))
3439 		reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3440 
3441 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3442 	if (err)
3443 		return err;
3444 
3445 	err = mv88e6xxx_setup_port_mode(chip, port);
3446 	if (err)
3447 		return err;
3448 
3449 	err = mv88e6xxx_setup_egress_floods(chip, port);
3450 	if (err)
3451 		return err;
3452 
3453 	/* Port Control 2: don't force a good FCS, set the MTU size to
3454 	 * 10222 bytes, disable 802.1q tags checking, don't discard
3455 	 * tagged or untagged frames on this port, skip destination
3456 	 * address lookup on user ports, disable ARP mirroring and don't
3457 	 * send a copy of all transmitted/received frames on this port
3458 	 * to the CPU.
3459 	 */
3460 	err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3461 	if (err)
3462 		return err;
3463 
3464 	err = mv88e6xxx_setup_upstream_port(chip, port);
3465 	if (err)
3466 		return err;
3467 
3468 	/* On chips that support it, set all downstream DSA ports'
3469 	 * VLAN policy to TRAP. In combination with loading
3470 	 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3471 	 * provides a better isolation barrier between standalone
3472 	 * ports, as the ATU is bypassed on any intermediate switches
3473 	 * between the incoming port and the CPU.
3474 	 */
3475 	if (dsa_is_downstream_port(ds, port) &&
3476 	    chip->info->ops->port_set_policy) {
3477 		err = chip->info->ops->port_set_policy(chip, port,
3478 						MV88E6XXX_POLICY_MAPPING_VTU,
3479 						MV88E6XXX_POLICY_ACTION_TRAP);
3480 		if (err)
3481 			return err;
3482 	}
3483 
3484 	/* User ports start out in standalone mode and 802.1Q is
3485 	 * therefore disabled. On DSA ports, all valid VIDs are always
3486 	 * loaded in the VTU - therefore, enable 802.1Q in order to take
3487 	 * advantage of VLAN policy on chips that supports it.
3488 	 */
3489 	err = mv88e6xxx_port_set_8021q_mode(chip, port,
3490 				dsa_is_user_port(ds, port) ?
3491 				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3492 				MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3493 	if (err)
3494 		return err;
3495 
3496 	/* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3497 	 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3498 	 * the first free FID. This will be used as the private PVID for
3499 	 * unbridged ports. Shared (DSA and CPU) ports must also be
3500 	 * members of this VID, in order to trap all frames assigned to
3501 	 * it to the CPU.
3502 	 */
3503 	err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3504 				       MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3505 				       false);
3506 	if (err)
3507 		return err;
3508 
3509 	/* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3510 	 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3511 	 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3512 	 * as the private PVID on ports under a VLAN-unaware bridge.
3513 	 * Shared (DSA and CPU) ports must also be members of it, to translate
3514 	 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3515 	 * relying on their port default FID.
3516 	 */
3517 	err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3518 				       MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3519 				       false);
3520 	if (err)
3521 		return err;
3522 
3523 	if (chip->info->ops->port_set_jumbo_size) {
3524 		err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3525 		if (err)
3526 			return err;
3527 	}
3528 
3529 	/* Port Association Vector: disable automatic address learning
3530 	 * on all user ports since they start out in standalone
3531 	 * mode. When joining a bridge, learning will be configured to
3532 	 * match the bridge port settings. Enable learning on all
3533 	 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3534 	 * learning process.
3535 	 *
3536 	 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3537 	 * and RefreshLocked. I.e. setup standard automatic learning.
3538 	 */
3539 	if (dsa_is_user_port(ds, port))
3540 		reg = 0;
3541 	else
3542 		reg = 1 << port;
3543 
3544 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3545 				   reg);
3546 	if (err)
3547 		return err;
3548 
3549 	/* Egress rate control 2: disable egress rate control. */
3550 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3551 				   0x0000);
3552 	if (err)
3553 		return err;
3554 
3555 	if (chip->info->ops->port_pause_limit) {
3556 		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3557 		if (err)
3558 			return err;
3559 	}
3560 
3561 	if (chip->info->ops->port_disable_learn_limit) {
3562 		err = chip->info->ops->port_disable_learn_limit(chip, port);
3563 		if (err)
3564 			return err;
3565 	}
3566 
3567 	if (chip->info->ops->port_disable_pri_override) {
3568 		err = chip->info->ops->port_disable_pri_override(chip, port);
3569 		if (err)
3570 			return err;
3571 	}
3572 
3573 	if (chip->info->ops->port_tag_remap) {
3574 		err = chip->info->ops->port_tag_remap(chip, port);
3575 		if (err)
3576 			return err;
3577 	}
3578 
3579 	if (chip->info->ops->port_egress_rate_limiting) {
3580 		err = chip->info->ops->port_egress_rate_limiting(chip, port);
3581 		if (err)
3582 			return err;
3583 	}
3584 
3585 	if (chip->info->ops->port_setup_message_port) {
3586 		err = chip->info->ops->port_setup_message_port(chip, port);
3587 		if (err)
3588 			return err;
3589 	}
3590 
3591 	if (chip->info->ops->serdes_set_tx_amplitude) {
3592 		dp = dsa_to_port(ds, port);
3593 		if (dp)
3594 			phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3595 
3596 		if (phy_handle && !of_property_read_u32(phy_handle,
3597 							"tx-p2p-microvolt",
3598 							&tx_amp))
3599 			err = chip->info->ops->serdes_set_tx_amplitude(chip,
3600 								port, tx_amp);
3601 		if (phy_handle) {
3602 			of_node_put(phy_handle);
3603 			if (err)
3604 				return err;
3605 		}
3606 	}
3607 
3608 	/* Port based VLAN map: give each port the same default address
3609 	 * database, and allow bidirectional communication between the
3610 	 * CPU and DSA port(s), and the other ports.
3611 	 */
3612 	err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3613 	if (err)
3614 		return err;
3615 
3616 	err = mv88e6xxx_port_vlan_map(chip, port);
3617 	if (err)
3618 		return err;
3619 
3620 	/* Default VLAN ID and priority: don't set a default VLAN
3621 	 * ID, and set the default packet priority to zero.
3622 	 */
3623 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3624 }
3625 
3626 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3627 {
3628 	struct mv88e6xxx_chip *chip = ds->priv;
3629 
3630 	if (chip->info->ops->port_set_jumbo_size)
3631 		return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3632 	else if (chip->info->ops->set_max_frame_size)
3633 		return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3634 	return ETH_DATA_LEN;
3635 }
3636 
3637 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3638 {
3639 	struct mv88e6xxx_chip *chip = ds->priv;
3640 	int ret = 0;
3641 
3642 	/* For families where we don't know how to alter the MTU,
3643 	 * just accept any value up to ETH_DATA_LEN
3644 	 */
3645 	if (!chip->info->ops->port_set_jumbo_size &&
3646 	    !chip->info->ops->set_max_frame_size) {
3647 		if (new_mtu > ETH_DATA_LEN)
3648 			return -EINVAL;
3649 
3650 		return 0;
3651 	}
3652 
3653 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3654 		new_mtu += EDSA_HLEN;
3655 
3656 	mv88e6xxx_reg_lock(chip);
3657 	if (chip->info->ops->port_set_jumbo_size)
3658 		ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3659 	else if (chip->info->ops->set_max_frame_size &&
3660 		 dsa_is_cpu_port(ds, port))
3661 		ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3662 	mv88e6xxx_reg_unlock(chip);
3663 
3664 	return ret;
3665 }
3666 
3667 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3668 				     unsigned int ageing_time)
3669 {
3670 	struct mv88e6xxx_chip *chip = ds->priv;
3671 	int err;
3672 
3673 	mv88e6xxx_reg_lock(chip);
3674 	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3675 	mv88e6xxx_reg_unlock(chip);
3676 
3677 	return err;
3678 }
3679 
3680 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3681 {
3682 	int err;
3683 
3684 	/* Initialize the statistics unit */
3685 	if (chip->info->ops->stats_set_histogram) {
3686 		err = chip->info->ops->stats_set_histogram(chip);
3687 		if (err)
3688 			return err;
3689 	}
3690 
3691 	return mv88e6xxx_g1_stats_clear(chip);
3692 }
3693 
3694 /* Check if the errata has already been applied. */
3695 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3696 {
3697 	int port;
3698 	int err;
3699 	u16 val;
3700 
3701 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3702 		err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3703 		if (err) {
3704 			dev_err(chip->dev,
3705 				"Error reading hidden register: %d\n", err);
3706 			return false;
3707 		}
3708 		if (val != 0x01c0)
3709 			return false;
3710 	}
3711 
3712 	return true;
3713 }
3714 
3715 /* The 6390 copper ports have an errata which require poking magic
3716  * values into undocumented hidden registers and then performing a
3717  * software reset.
3718  */
3719 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3720 {
3721 	int port;
3722 	int err;
3723 
3724 	if (mv88e6390_setup_errata_applied(chip))
3725 		return 0;
3726 
3727 	/* Set the ports into blocking mode */
3728 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3729 		err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3730 		if (err)
3731 			return err;
3732 	}
3733 
3734 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3735 		err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3736 		if (err)
3737 			return err;
3738 	}
3739 
3740 	return mv88e6xxx_software_reset(chip);
3741 }
3742 
3743 /* prod_id for switch families which do not have a PHY model number */
3744 static const u16 family_prod_id_table[] = {
3745 	[MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3746 	[MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3747 	[MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3748 };
3749 
3750 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3751 {
3752 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3753 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3754 	u16 prod_id;
3755 	u16 val;
3756 	int err;
3757 
3758 	if (!chip->info->ops->phy_read)
3759 		return -EOPNOTSUPP;
3760 
3761 	mv88e6xxx_reg_lock(chip);
3762 	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3763 	mv88e6xxx_reg_unlock(chip);
3764 
3765 	/* Some internal PHYs don't have a model number. */
3766 	if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3767 	    chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3768 		prod_id = family_prod_id_table[chip->info->family];
3769 		if (prod_id)
3770 			val |= prod_id >> 4;
3771 	}
3772 
3773 	return err ? err : val;
3774 }
3775 
3776 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3777 				   int reg)
3778 {
3779 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3780 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3781 	u16 val;
3782 	int err;
3783 
3784 	if (!chip->info->ops->phy_read_c45)
3785 		return -ENODEV;
3786 
3787 	mv88e6xxx_reg_lock(chip);
3788 	err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3789 	mv88e6xxx_reg_unlock(chip);
3790 
3791 	return err ? err : val;
3792 }
3793 
3794 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3795 {
3796 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3797 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3798 	int err;
3799 
3800 	if (!chip->info->ops->phy_write)
3801 		return -EOPNOTSUPP;
3802 
3803 	mv88e6xxx_reg_lock(chip);
3804 	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3805 	mv88e6xxx_reg_unlock(chip);
3806 
3807 	return err;
3808 }
3809 
3810 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3811 				    int reg, u16 val)
3812 {
3813 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3814 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
3815 	int err;
3816 
3817 	if (!chip->info->ops->phy_write_c45)
3818 		return -EOPNOTSUPP;
3819 
3820 	mv88e6xxx_reg_lock(chip);
3821 	err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3822 	mv88e6xxx_reg_unlock(chip);
3823 
3824 	return err;
3825 }
3826 
3827 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3828 				   struct device_node *np,
3829 				   bool external)
3830 {
3831 	static int index;
3832 	struct mv88e6xxx_mdio_bus *mdio_bus;
3833 	struct mii_bus *bus;
3834 	int err;
3835 
3836 	if (external) {
3837 		mv88e6xxx_reg_lock(chip);
3838 		if (chip->info->family == MV88E6XXX_FAMILY_6393)
3839 			err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3840 		else
3841 			err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3842 		mv88e6xxx_reg_unlock(chip);
3843 
3844 		if (err)
3845 			return err;
3846 	}
3847 
3848 	bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3849 	if (!bus)
3850 		return -ENOMEM;
3851 
3852 	mdio_bus = bus->priv;
3853 	mdio_bus->bus = bus;
3854 	mdio_bus->chip = chip;
3855 	INIT_LIST_HEAD(&mdio_bus->list);
3856 	mdio_bus->external = external;
3857 
3858 	if (np) {
3859 		bus->name = np->full_name;
3860 		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3861 	} else {
3862 		bus->name = "mv88e6xxx SMI";
3863 		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3864 	}
3865 
3866 	bus->read = mv88e6xxx_mdio_read;
3867 	bus->write = mv88e6xxx_mdio_write;
3868 	bus->read_c45 = mv88e6xxx_mdio_read_c45;
3869 	bus->write_c45 = mv88e6xxx_mdio_write_c45;
3870 	bus->parent = chip->dev;
3871 	bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3872 				 mv88e6xxx_num_ports(chip) - 1,
3873 				 chip->info->phy_base_addr);
3874 
3875 	if (!external) {
3876 		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3877 		if (err)
3878 			goto out;
3879 	}
3880 
3881 	err = of_mdiobus_register(bus, np);
3882 	if (err) {
3883 		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3884 		mv88e6xxx_g2_irq_mdio_free(chip, bus);
3885 		goto out;
3886 	}
3887 
3888 	if (external)
3889 		list_add_tail(&mdio_bus->list, &chip->mdios);
3890 	else
3891 		list_add(&mdio_bus->list, &chip->mdios);
3892 
3893 	return 0;
3894 
3895 out:
3896 	mdiobus_free(bus);
3897 	return err;
3898 }
3899 
3900 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3901 
3902 {
3903 	struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3904 	struct mii_bus *bus;
3905 
3906 	list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3907 		bus = mdio_bus->bus;
3908 
3909 		if (!mdio_bus->external)
3910 			mv88e6xxx_g2_irq_mdio_free(chip, bus);
3911 
3912 		mdiobus_unregister(bus);
3913 		mdiobus_free(bus);
3914 	}
3915 }
3916 
3917 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3918 {
3919 	struct device_node *np = chip->dev->of_node;
3920 	struct device_node *child;
3921 	int err;
3922 
3923 	/* Always register one mdio bus for the internal/default mdio
3924 	 * bus. This maybe represented in the device tree, but is
3925 	 * optional.
3926 	 */
3927 	child = of_get_child_by_name(np, "mdio");
3928 	err = mv88e6xxx_mdio_register(chip, child, false);
3929 	of_node_put(child);
3930 	if (err)
3931 		return err;
3932 
3933 	/* Walk the device tree, and see if there are any other nodes
3934 	 * which say they are compatible with the external mdio
3935 	 * bus.
3936 	 */
3937 	for_each_available_child_of_node(np, child) {
3938 		if (of_device_is_compatible(
3939 			    child, "marvell,mv88e6xxx-mdio-external")) {
3940 			err = mv88e6xxx_mdio_register(chip, child, true);
3941 			if (err) {
3942 				mv88e6xxx_mdios_unregister(chip);
3943 				of_node_put(child);
3944 				return err;
3945 			}
3946 		}
3947 	}
3948 
3949 	return 0;
3950 }
3951 
3952 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3953 {
3954 	struct mv88e6xxx_chip *chip = ds->priv;
3955 
3956 	mv88e6xxx_teardown_devlink_params(ds);
3957 	dsa_devlink_resources_unregister(ds);
3958 	mv88e6xxx_teardown_devlink_regions_global(ds);
3959 	mv88e6xxx_mdios_unregister(chip);
3960 }
3961 
3962 static int mv88e6xxx_setup(struct dsa_switch *ds)
3963 {
3964 	struct mv88e6xxx_chip *chip = ds->priv;
3965 	u8 cmode;
3966 	int err;
3967 	int i;
3968 
3969 	err = mv88e6xxx_mdios_register(chip);
3970 	if (err)
3971 		return err;
3972 
3973 	chip->ds = ds;
3974 	ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3975 
3976 	/* Since virtual bridges are mapped in the PVT, the number we support
3977 	 * depends on the physical switch topology. We need to let DSA figure
3978 	 * that out and therefore we cannot set this at dsa_register_switch()
3979 	 * time.
3980 	 */
3981 	if (mv88e6xxx_has_pvt(chip))
3982 		ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3983 				      ds->dst->last_switch - 1;
3984 
3985 	mv88e6xxx_reg_lock(chip);
3986 
3987 	if (chip->info->ops->setup_errata) {
3988 		err = chip->info->ops->setup_errata(chip);
3989 		if (err)
3990 			goto unlock;
3991 	}
3992 
3993 	/* Cache the cmode of each port. */
3994 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3995 		if (chip->info->ops->port_get_cmode) {
3996 			err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3997 			if (err)
3998 				goto unlock;
3999 
4000 			chip->ports[i].cmode = cmode;
4001 		}
4002 	}
4003 
4004 	err = mv88e6xxx_vtu_setup(chip);
4005 	if (err)
4006 		goto unlock;
4007 
4008 	/* Must be called after mv88e6xxx_vtu_setup (which flushes the
4009 	 * VTU, thereby also flushing the STU).
4010 	 */
4011 	err = mv88e6xxx_stu_setup(chip);
4012 	if (err)
4013 		goto unlock;
4014 
4015 	/* Setup Switch Port Registers */
4016 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
4017 		if (dsa_is_unused_port(ds, i))
4018 			continue;
4019 
4020 		/* Prevent the use of an invalid port. */
4021 		if (mv88e6xxx_is_invalid_port(chip, i)) {
4022 			dev_err(chip->dev, "port %d is invalid\n", i);
4023 			err = -EINVAL;
4024 			goto unlock;
4025 		}
4026 
4027 		err = mv88e6xxx_setup_port(chip, i);
4028 		if (err)
4029 			goto unlock;
4030 	}
4031 
4032 	err = mv88e6xxx_irl_setup(chip);
4033 	if (err)
4034 		goto unlock;
4035 
4036 	err = mv88e6xxx_mac_setup(chip);
4037 	if (err)
4038 		goto unlock;
4039 
4040 	err = mv88e6xxx_phy_setup(chip);
4041 	if (err)
4042 		goto unlock;
4043 
4044 	err = mv88e6xxx_pvt_setup(chip);
4045 	if (err)
4046 		goto unlock;
4047 
4048 	err = mv88e6xxx_atu_setup(chip);
4049 	if (err)
4050 		goto unlock;
4051 
4052 	err = mv88e6xxx_broadcast_setup(chip, 0);
4053 	if (err)
4054 		goto unlock;
4055 
4056 	err = mv88e6xxx_pot_setup(chip);
4057 	if (err)
4058 		goto unlock;
4059 
4060 	err = mv88e6xxx_rmu_setup(chip);
4061 	if (err)
4062 		goto unlock;
4063 
4064 	err = mv88e6xxx_rsvd2cpu_setup(chip);
4065 	if (err)
4066 		goto unlock;
4067 
4068 	err = mv88e6xxx_trunk_setup(chip);
4069 	if (err)
4070 		goto unlock;
4071 
4072 	err = mv88e6xxx_devmap_setup(chip);
4073 	if (err)
4074 		goto unlock;
4075 
4076 	err = mv88e6xxx_pri_setup(chip);
4077 	if (err)
4078 		goto unlock;
4079 
4080 	/* Setup PTP Hardware Clock and timestamping */
4081 	if (chip->info->ptp_support) {
4082 		err = mv88e6xxx_ptp_setup(chip);
4083 		if (err)
4084 			goto unlock;
4085 
4086 		err = mv88e6xxx_hwtstamp_setup(chip);
4087 		if (err)
4088 			goto unlock;
4089 	}
4090 
4091 	err = mv88e6xxx_stats_setup(chip);
4092 	if (err)
4093 		goto unlock;
4094 
4095 unlock:
4096 	mv88e6xxx_reg_unlock(chip);
4097 
4098 	if (err)
4099 		goto out_mdios;
4100 
4101 	/* Have to be called without holding the register lock, since
4102 	 * they take the devlink lock, and we later take the locks in
4103 	 * the reverse order when getting/setting parameters or
4104 	 * resource occupancy.
4105 	 */
4106 	err = mv88e6xxx_setup_devlink_resources(ds);
4107 	if (err)
4108 		goto out_mdios;
4109 
4110 	err = mv88e6xxx_setup_devlink_params(ds);
4111 	if (err)
4112 		goto out_resources;
4113 
4114 	err = mv88e6xxx_setup_devlink_regions_global(ds);
4115 	if (err)
4116 		goto out_params;
4117 
4118 	return 0;
4119 
4120 out_params:
4121 	mv88e6xxx_teardown_devlink_params(ds);
4122 out_resources:
4123 	dsa_devlink_resources_unregister(ds);
4124 out_mdios:
4125 	mv88e6xxx_mdios_unregister(chip);
4126 
4127 	return err;
4128 }
4129 
4130 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4131 {
4132 	struct mv88e6xxx_chip *chip = ds->priv;
4133 	int err;
4134 
4135 	if (chip->info->ops->pcs_ops &&
4136 	    chip->info->ops->pcs_ops->pcs_init) {
4137 		err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4138 		if (err)
4139 			return err;
4140 	}
4141 
4142 	return mv88e6xxx_setup_devlink_regions_port(ds, port);
4143 }
4144 
4145 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4146 {
4147 	struct mv88e6xxx_chip *chip = ds->priv;
4148 
4149 	mv88e6xxx_teardown_devlink_regions_port(ds, port);
4150 
4151 	if (chip->info->ops->pcs_ops &&
4152 	    chip->info->ops->pcs_ops->pcs_teardown)
4153 		chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4154 }
4155 
4156 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4157 {
4158 	struct mv88e6xxx_chip *chip = ds->priv;
4159 
4160 	return chip->eeprom_len;
4161 }
4162 
4163 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4164 				struct ethtool_eeprom *eeprom, u8 *data)
4165 {
4166 	struct mv88e6xxx_chip *chip = ds->priv;
4167 	int err;
4168 
4169 	if (!chip->info->ops->get_eeprom)
4170 		return -EOPNOTSUPP;
4171 
4172 	mv88e6xxx_reg_lock(chip);
4173 	err = chip->info->ops->get_eeprom(chip, eeprom, data);
4174 	mv88e6xxx_reg_unlock(chip);
4175 
4176 	if (err)
4177 		return err;
4178 
4179 	eeprom->magic = 0xc3ec4951;
4180 
4181 	return 0;
4182 }
4183 
4184 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4185 				struct ethtool_eeprom *eeprom, u8 *data)
4186 {
4187 	struct mv88e6xxx_chip *chip = ds->priv;
4188 	int err;
4189 
4190 	if (!chip->info->ops->set_eeprom)
4191 		return -EOPNOTSUPP;
4192 
4193 	if (eeprom->magic != 0xc3ec4951)
4194 		return -EINVAL;
4195 
4196 	mv88e6xxx_reg_lock(chip);
4197 	err = chip->info->ops->set_eeprom(chip, eeprom, data);
4198 	mv88e6xxx_reg_unlock(chip);
4199 
4200 	return err;
4201 }
4202 
4203 static const struct mv88e6xxx_ops mv88e6085_ops = {
4204 	/* MV88E6XXX_FAMILY_6097 */
4205 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4206 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4207 	.irl_init_all = mv88e6352_g2_irl_init_all,
4208 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4209 	.phy_read = mv88e6185_phy_ppu_read,
4210 	.phy_write = mv88e6185_phy_ppu_write,
4211 	.port_set_link = mv88e6xxx_port_set_link,
4212 	.port_sync_link = mv88e6xxx_port_sync_link,
4213 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4214 	.port_tag_remap = mv88e6095_port_tag_remap,
4215 	.port_set_policy = mv88e6352_port_set_policy,
4216 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4217 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4218 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4219 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4220 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4221 	.port_pause_limit = mv88e6097_port_pause_limit,
4222 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4223 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4224 	.port_get_cmode = mv88e6185_port_get_cmode,
4225 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4226 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4227 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4228 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4229 	.stats_get_strings = mv88e6095_stats_get_strings,
4230 	.stats_get_stat = mv88e6095_stats_get_stat,
4231 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4232 	.set_egress_port = mv88e6095_g1_set_egress_port,
4233 	.watchdog_ops = &mv88e6097_watchdog_ops,
4234 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4235 	.pot_clear = mv88e6xxx_g2_pot_clear,
4236 	.ppu_enable = mv88e6185_g1_ppu_enable,
4237 	.ppu_disable = mv88e6185_g1_ppu_disable,
4238 	.reset = mv88e6185_g1_reset,
4239 	.rmu_disable = mv88e6085_g1_rmu_disable,
4240 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4241 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4242 	.stu_getnext = mv88e6352_g1_stu_getnext,
4243 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4244 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4245 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4246 };
4247 
4248 static const struct mv88e6xxx_ops mv88e6095_ops = {
4249 	/* MV88E6XXX_FAMILY_6095 */
4250 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4251 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4252 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4253 	.phy_read = mv88e6185_phy_ppu_read,
4254 	.phy_write = mv88e6185_phy_ppu_write,
4255 	.port_set_link = mv88e6xxx_port_set_link,
4256 	.port_sync_link = mv88e6185_port_sync_link,
4257 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4258 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
4259 	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4260 	.port_set_mcast_flood = mv88e6185_port_set_default_forward,
4261 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
4262 	.port_get_cmode = mv88e6185_port_get_cmode,
4263 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4264 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4265 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4266 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4267 	.stats_get_strings = mv88e6095_stats_get_strings,
4268 	.stats_get_stat = mv88e6095_stats_get_stat,
4269 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4270 	.ppu_enable = mv88e6185_g1_ppu_enable,
4271 	.ppu_disable = mv88e6185_g1_ppu_disable,
4272 	.reset = mv88e6185_g1_reset,
4273 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
4274 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4275 	.phylink_get_caps = mv88e6095_phylink_get_caps,
4276 	.pcs_ops = &mv88e6185_pcs_ops,
4277 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4278 };
4279 
4280 static const struct mv88e6xxx_ops mv88e6097_ops = {
4281 	/* MV88E6XXX_FAMILY_6097 */
4282 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4283 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4284 	.irl_init_all = mv88e6352_g2_irl_init_all,
4285 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4286 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4287 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4288 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4289 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4290 	.port_set_link = mv88e6xxx_port_set_link,
4291 	.port_sync_link = mv88e6185_port_sync_link,
4292 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4293 	.port_tag_remap = mv88e6095_port_tag_remap,
4294 	.port_set_policy = mv88e6352_port_set_policy,
4295 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4296 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4297 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4298 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4299 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4300 	.port_pause_limit = mv88e6097_port_pause_limit,
4301 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4302 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4303 	.port_get_cmode = mv88e6185_port_get_cmode,
4304 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4305 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4306 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4307 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4308 	.stats_get_strings = mv88e6095_stats_get_strings,
4309 	.stats_get_stat = mv88e6095_stats_get_stat,
4310 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4311 	.set_egress_port = mv88e6095_g1_set_egress_port,
4312 	.watchdog_ops = &mv88e6097_watchdog_ops,
4313 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4314 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4315 	.pot_clear = mv88e6xxx_g2_pot_clear,
4316 	.reset = mv88e6352_g1_reset,
4317 	.rmu_disable = mv88e6085_g1_rmu_disable,
4318 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4319 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4320 	.phylink_get_caps = mv88e6095_phylink_get_caps,
4321 	.pcs_ops = &mv88e6185_pcs_ops,
4322 	.stu_getnext = mv88e6352_g1_stu_getnext,
4323 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4324 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4325 };
4326 
4327 static const struct mv88e6xxx_ops mv88e6123_ops = {
4328 	/* MV88E6XXX_FAMILY_6165 */
4329 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4330 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4331 	.irl_init_all = mv88e6352_g2_irl_init_all,
4332 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4333 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4334 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4335 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4336 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4337 	.port_set_link = mv88e6xxx_port_set_link,
4338 	.port_sync_link = mv88e6xxx_port_sync_link,
4339 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4340 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
4341 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4342 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4343 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4344 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4345 	.port_get_cmode = mv88e6185_port_get_cmode,
4346 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4347 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4348 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4349 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4350 	.stats_get_strings = mv88e6095_stats_get_strings,
4351 	.stats_get_stat = mv88e6095_stats_get_stat,
4352 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4353 	.set_egress_port = mv88e6095_g1_set_egress_port,
4354 	.watchdog_ops = &mv88e6097_watchdog_ops,
4355 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4356 	.pot_clear = mv88e6xxx_g2_pot_clear,
4357 	.reset = mv88e6352_g1_reset,
4358 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4359 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4360 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4361 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4362 	.stu_getnext = mv88e6352_g1_stu_getnext,
4363 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4364 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4365 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4366 };
4367 
4368 static const struct mv88e6xxx_ops mv88e6131_ops = {
4369 	/* MV88E6XXX_FAMILY_6185 */
4370 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4371 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4372 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4373 	.phy_read = mv88e6185_phy_ppu_read,
4374 	.phy_write = mv88e6185_phy_ppu_write,
4375 	.port_set_link = mv88e6xxx_port_set_link,
4376 	.port_sync_link = mv88e6xxx_port_sync_link,
4377 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4378 	.port_tag_remap = mv88e6095_port_tag_remap,
4379 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4380 	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4381 	.port_set_mcast_flood = mv88e6185_port_set_default_forward,
4382 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4383 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
4384 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4385 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4386 	.port_pause_limit = mv88e6097_port_pause_limit,
4387 	.port_set_pause = mv88e6185_port_set_pause,
4388 	.port_get_cmode = mv88e6185_port_get_cmode,
4389 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4390 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4391 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4392 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4393 	.stats_get_strings = mv88e6095_stats_get_strings,
4394 	.stats_get_stat = mv88e6095_stats_get_stat,
4395 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4396 	.set_egress_port = mv88e6095_g1_set_egress_port,
4397 	.watchdog_ops = &mv88e6097_watchdog_ops,
4398 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4399 	.ppu_enable = mv88e6185_g1_ppu_enable,
4400 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
4401 	.ppu_disable = mv88e6185_g1_ppu_disable,
4402 	.reset = mv88e6185_g1_reset,
4403 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
4404 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4405 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4406 };
4407 
4408 static const struct mv88e6xxx_ops mv88e6141_ops = {
4409 	/* MV88E6XXX_FAMILY_6341 */
4410 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4411 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4412 	.irl_init_all = mv88e6352_g2_irl_init_all,
4413 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4414 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4415 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4416 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4417 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4418 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4419 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4420 	.port_set_link = mv88e6xxx_port_set_link,
4421 	.port_sync_link = mv88e6xxx_port_sync_link,
4422 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4423 	.port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4424 	.port_max_speed_mode = mv88e6341_port_max_speed_mode,
4425 	.port_tag_remap = mv88e6095_port_tag_remap,
4426 	.port_set_policy = mv88e6352_port_set_policy,
4427 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4428 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4429 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4430 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4431 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4432 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4433 	.port_pause_limit = mv88e6097_port_pause_limit,
4434 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4435 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4436 	.port_get_cmode = mv88e6352_port_get_cmode,
4437 	.port_set_cmode = mv88e6341_port_set_cmode,
4438 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4439 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4440 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4441 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4442 	.stats_get_strings = mv88e6320_stats_get_strings,
4443 	.stats_get_stat = mv88e6390_stats_get_stat,
4444 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4445 	.set_egress_port = mv88e6390_g1_set_egress_port,
4446 	.watchdog_ops = &mv88e6390_watchdog_ops,
4447 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4448 	.pot_clear = mv88e6xxx_g2_pot_clear,
4449 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4450 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4451 	.reset = mv88e6352_g1_reset,
4452 	.rmu_disable = mv88e6390_g1_rmu_disable,
4453 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4454 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4455 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4456 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4457 	.stu_getnext = mv88e6352_g1_stu_getnext,
4458 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4459 	.serdes_get_lane = mv88e6341_serdes_get_lane,
4460 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4461 	.gpio_ops = &mv88e6352_gpio_ops,
4462 	.serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4463 	.serdes_get_strings = mv88e6390_serdes_get_strings,
4464 	.serdes_get_stats = mv88e6390_serdes_get_stats,
4465 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4466 	.serdes_get_regs = mv88e6390_serdes_get_regs,
4467 	.phylink_get_caps = mv88e6341_phylink_get_caps,
4468 	.pcs_ops = &mv88e6390_pcs_ops,
4469 };
4470 
4471 static const struct mv88e6xxx_ops mv88e6161_ops = {
4472 	/* MV88E6XXX_FAMILY_6165 */
4473 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4474 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4475 	.irl_init_all = mv88e6352_g2_irl_init_all,
4476 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4477 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4478 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4479 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4480 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4481 	.port_set_link = mv88e6xxx_port_set_link,
4482 	.port_sync_link = mv88e6xxx_port_sync_link,
4483 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4484 	.port_tag_remap = mv88e6095_port_tag_remap,
4485 	.port_set_policy = mv88e6352_port_set_policy,
4486 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4487 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4488 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4489 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4490 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4491 	.port_pause_limit = mv88e6097_port_pause_limit,
4492 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4493 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4494 	.port_get_cmode = mv88e6185_port_get_cmode,
4495 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4496 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4497 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4498 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4499 	.stats_get_strings = mv88e6095_stats_get_strings,
4500 	.stats_get_stat = mv88e6095_stats_get_stat,
4501 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4502 	.set_egress_port = mv88e6095_g1_set_egress_port,
4503 	.watchdog_ops = &mv88e6097_watchdog_ops,
4504 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4505 	.pot_clear = mv88e6xxx_g2_pot_clear,
4506 	.reset = mv88e6352_g1_reset,
4507 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4508 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4509 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4510 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4511 	.stu_getnext = mv88e6352_g1_stu_getnext,
4512 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4513 	.avb_ops = &mv88e6165_avb_ops,
4514 	.ptp_ops = &mv88e6165_ptp_ops,
4515 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4516 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4517 };
4518 
4519 static const struct mv88e6xxx_ops mv88e6165_ops = {
4520 	/* MV88E6XXX_FAMILY_6165 */
4521 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4522 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4523 	.irl_init_all = mv88e6352_g2_irl_init_all,
4524 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4525 	.phy_read = mv88e6165_phy_read,
4526 	.phy_write = mv88e6165_phy_write,
4527 	.port_set_link = mv88e6xxx_port_set_link,
4528 	.port_sync_link = mv88e6xxx_port_sync_link,
4529 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4530 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4531 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4532 	.port_get_cmode = mv88e6185_port_get_cmode,
4533 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4534 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4535 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4536 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4537 	.stats_get_strings = mv88e6095_stats_get_strings,
4538 	.stats_get_stat = mv88e6095_stats_get_stat,
4539 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4540 	.set_egress_port = mv88e6095_g1_set_egress_port,
4541 	.watchdog_ops = &mv88e6097_watchdog_ops,
4542 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4543 	.pot_clear = mv88e6xxx_g2_pot_clear,
4544 	.reset = mv88e6352_g1_reset,
4545 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4546 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4547 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4548 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4549 	.stu_getnext = mv88e6352_g1_stu_getnext,
4550 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4551 	.avb_ops = &mv88e6165_avb_ops,
4552 	.ptp_ops = &mv88e6165_ptp_ops,
4553 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4554 };
4555 
4556 static const struct mv88e6xxx_ops mv88e6171_ops = {
4557 	/* MV88E6XXX_FAMILY_6351 */
4558 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4559 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4560 	.irl_init_all = mv88e6352_g2_irl_init_all,
4561 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4562 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4563 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4564 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4565 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4566 	.port_set_link = mv88e6xxx_port_set_link,
4567 	.port_sync_link = mv88e6xxx_port_sync_link,
4568 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4569 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4570 	.port_tag_remap = mv88e6095_port_tag_remap,
4571 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4572 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4573 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4574 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4575 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4576 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4577 	.port_pause_limit = mv88e6097_port_pause_limit,
4578 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4579 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4580 	.port_get_cmode = mv88e6352_port_get_cmode,
4581 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4582 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4583 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4584 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4585 	.stats_get_strings = mv88e6095_stats_get_strings,
4586 	.stats_get_stat = mv88e6095_stats_get_stat,
4587 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4588 	.set_egress_port = mv88e6095_g1_set_egress_port,
4589 	.watchdog_ops = &mv88e6097_watchdog_ops,
4590 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4591 	.pot_clear = mv88e6xxx_g2_pot_clear,
4592 	.reset = mv88e6352_g1_reset,
4593 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4594 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4595 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4596 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4597 	.stu_getnext = mv88e6352_g1_stu_getnext,
4598 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4599 	.phylink_get_caps = mv88e6351_phylink_get_caps,
4600 };
4601 
4602 static const struct mv88e6xxx_ops mv88e6172_ops = {
4603 	/* MV88E6XXX_FAMILY_6352 */
4604 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4605 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4606 	.irl_init_all = mv88e6352_g2_irl_init_all,
4607 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4608 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4609 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4610 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4611 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4612 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4613 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4614 	.port_set_link = mv88e6xxx_port_set_link,
4615 	.port_sync_link = mv88e6xxx_port_sync_link,
4616 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4617 	.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4618 	.port_tag_remap = mv88e6095_port_tag_remap,
4619 	.port_set_policy = mv88e6352_port_set_policy,
4620 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4621 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4622 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4623 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4624 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4625 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4626 	.port_pause_limit = mv88e6097_port_pause_limit,
4627 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4628 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4629 	.port_get_cmode = mv88e6352_port_get_cmode,
4630 	.port_setup_leds = mv88e6xxx_port_setup_leds,
4631 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4632 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4633 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4634 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4635 	.stats_get_strings = mv88e6095_stats_get_strings,
4636 	.stats_get_stat = mv88e6095_stats_get_stat,
4637 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4638 	.set_egress_port = mv88e6095_g1_set_egress_port,
4639 	.watchdog_ops = &mv88e6097_watchdog_ops,
4640 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4641 	.pot_clear = mv88e6xxx_g2_pot_clear,
4642 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4643 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4644 	.reset = mv88e6352_g1_reset,
4645 	.rmu_disable = mv88e6352_g1_rmu_disable,
4646 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4647 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4648 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4649 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4650 	.stu_getnext = mv88e6352_g1_stu_getnext,
4651 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4652 	.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4653 	.serdes_get_regs = mv88e6352_serdes_get_regs,
4654 	.gpio_ops = &mv88e6352_gpio_ops,
4655 	.phylink_get_caps = mv88e6352_phylink_get_caps,
4656 	.pcs_ops = &mv88e6352_pcs_ops,
4657 };
4658 
4659 static const struct mv88e6xxx_ops mv88e6175_ops = {
4660 	/* MV88E6XXX_FAMILY_6351 */
4661 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4662 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4663 	.irl_init_all = mv88e6352_g2_irl_init_all,
4664 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4665 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4666 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4667 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4668 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4669 	.port_set_link = mv88e6xxx_port_set_link,
4670 	.port_sync_link = mv88e6xxx_port_sync_link,
4671 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4672 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4673 	.port_tag_remap = mv88e6095_port_tag_remap,
4674 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4675 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4676 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4677 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4678 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4679 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4680 	.port_pause_limit = mv88e6097_port_pause_limit,
4681 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4682 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4683 	.port_get_cmode = mv88e6352_port_get_cmode,
4684 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4685 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4686 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4687 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4688 	.stats_get_strings = mv88e6095_stats_get_strings,
4689 	.stats_get_stat = mv88e6095_stats_get_stat,
4690 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4691 	.set_egress_port = mv88e6095_g1_set_egress_port,
4692 	.watchdog_ops = &mv88e6097_watchdog_ops,
4693 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4694 	.pot_clear = mv88e6xxx_g2_pot_clear,
4695 	.reset = mv88e6352_g1_reset,
4696 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4697 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4698 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4699 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4700 	.stu_getnext = mv88e6352_g1_stu_getnext,
4701 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4702 	.phylink_get_caps = mv88e6351_phylink_get_caps,
4703 };
4704 
4705 static const struct mv88e6xxx_ops mv88e6176_ops = {
4706 	/* MV88E6XXX_FAMILY_6352 */
4707 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4708 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4709 	.irl_init_all = mv88e6352_g2_irl_init_all,
4710 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4711 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4712 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4713 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4714 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4715 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4716 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4717 	.port_set_link = mv88e6xxx_port_set_link,
4718 	.port_sync_link = mv88e6xxx_port_sync_link,
4719 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4720 	.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4721 	.port_tag_remap = mv88e6095_port_tag_remap,
4722 	.port_set_policy = mv88e6352_port_set_policy,
4723 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4724 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4725 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4726 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4727 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4728 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4729 	.port_pause_limit = mv88e6097_port_pause_limit,
4730 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4731 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4732 	.port_get_cmode = mv88e6352_port_get_cmode,
4733 	.port_setup_leds = mv88e6xxx_port_setup_leds,
4734 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4735 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
4736 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4737 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4738 	.stats_get_strings = mv88e6095_stats_get_strings,
4739 	.stats_get_stat = mv88e6095_stats_get_stat,
4740 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4741 	.set_egress_port = mv88e6095_g1_set_egress_port,
4742 	.watchdog_ops = &mv88e6097_watchdog_ops,
4743 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4744 	.pot_clear = mv88e6xxx_g2_pot_clear,
4745 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4746 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4747 	.reset = mv88e6352_g1_reset,
4748 	.rmu_disable = mv88e6352_g1_rmu_disable,
4749 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4750 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4751 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
4752 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4753 	.stu_getnext = mv88e6352_g1_stu_getnext,
4754 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4755 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4756 	.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4757 	.serdes_get_regs = mv88e6352_serdes_get_regs,
4758 	.serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4759 	.gpio_ops = &mv88e6352_gpio_ops,
4760 	.phylink_get_caps = mv88e6352_phylink_get_caps,
4761 	.pcs_ops = &mv88e6352_pcs_ops,
4762 };
4763 
4764 static const struct mv88e6xxx_ops mv88e6185_ops = {
4765 	/* MV88E6XXX_FAMILY_6185 */
4766 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4767 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4768 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4769 	.phy_read = mv88e6185_phy_ppu_read,
4770 	.phy_write = mv88e6185_phy_ppu_write,
4771 	.port_set_link = mv88e6xxx_port_set_link,
4772 	.port_sync_link = mv88e6185_port_sync_link,
4773 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4774 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
4775 	.port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4776 	.port_set_mcast_flood = mv88e6185_port_set_default_forward,
4777 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4778 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
4779 	.port_set_pause = mv88e6185_port_set_pause,
4780 	.port_get_cmode = mv88e6185_port_get_cmode,
4781 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4782 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4783 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4784 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
4785 	.stats_get_strings = mv88e6095_stats_get_strings,
4786 	.stats_get_stat = mv88e6095_stats_get_stat,
4787 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
4788 	.set_egress_port = mv88e6095_g1_set_egress_port,
4789 	.watchdog_ops = &mv88e6097_watchdog_ops,
4790 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4791 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
4792 	.ppu_enable = mv88e6185_g1_ppu_enable,
4793 	.ppu_disable = mv88e6185_g1_ppu_disable,
4794 	.reset = mv88e6185_g1_reset,
4795 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
4796 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4797 	.phylink_get_caps = mv88e6185_phylink_get_caps,
4798 	.pcs_ops = &mv88e6185_pcs_ops,
4799 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4800 };
4801 
4802 static const struct mv88e6xxx_ops mv88e6190_ops = {
4803 	/* MV88E6XXX_FAMILY_6390 */
4804 	.setup_errata = mv88e6390_setup_errata,
4805 	.irl_init_all = mv88e6390_g2_irl_init_all,
4806 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4807 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4808 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4809 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4810 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4811 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4812 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4813 	.port_set_link = mv88e6xxx_port_set_link,
4814 	.port_sync_link = mv88e6xxx_port_sync_link,
4815 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4816 	.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4817 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
4818 	.port_tag_remap = mv88e6390_port_tag_remap,
4819 	.port_set_policy = mv88e6352_port_set_policy,
4820 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4821 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4822 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4823 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4824 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4825 	.port_pause_limit = mv88e6390_port_pause_limit,
4826 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4827 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4828 	.port_get_cmode = mv88e6352_port_get_cmode,
4829 	.port_set_cmode = mv88e6390_port_set_cmode,
4830 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4831 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4832 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4833 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4834 	.stats_get_strings = mv88e6320_stats_get_strings,
4835 	.stats_get_stat = mv88e6390_stats_get_stat,
4836 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4837 	.set_egress_port = mv88e6390_g1_set_egress_port,
4838 	.watchdog_ops = &mv88e6390_watchdog_ops,
4839 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4840 	.pot_clear = mv88e6xxx_g2_pot_clear,
4841 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4842 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4843 	.reset = mv88e6352_g1_reset,
4844 	.rmu_disable = mv88e6390_g1_rmu_disable,
4845 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4846 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4847 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4848 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4849 	.stu_getnext = mv88e6390_g1_stu_getnext,
4850 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4851 	.serdes_get_lane = mv88e6390_serdes_get_lane,
4852 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4853 	.serdes_get_strings = mv88e6390_serdes_get_strings,
4854 	.serdes_get_stats = mv88e6390_serdes_get_stats,
4855 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4856 	.serdes_get_regs = mv88e6390_serdes_get_regs,
4857 	.gpio_ops = &mv88e6352_gpio_ops,
4858 	.phylink_get_caps = mv88e6390_phylink_get_caps,
4859 	.pcs_ops = &mv88e6390_pcs_ops,
4860 };
4861 
4862 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4863 	/* MV88E6XXX_FAMILY_6390 */
4864 	.setup_errata = mv88e6390_setup_errata,
4865 	.irl_init_all = mv88e6390_g2_irl_init_all,
4866 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4867 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4868 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4869 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4870 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4871 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4872 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4873 	.port_set_link = mv88e6xxx_port_set_link,
4874 	.port_sync_link = mv88e6xxx_port_sync_link,
4875 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4876 	.port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4877 	.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4878 	.port_tag_remap = mv88e6390_port_tag_remap,
4879 	.port_set_policy = mv88e6352_port_set_policy,
4880 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4881 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4882 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4883 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4884 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4885 	.port_pause_limit = mv88e6390_port_pause_limit,
4886 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4887 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4888 	.port_get_cmode = mv88e6352_port_get_cmode,
4889 	.port_set_cmode = mv88e6390x_port_set_cmode,
4890 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4891 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4892 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4893 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4894 	.stats_get_strings = mv88e6320_stats_get_strings,
4895 	.stats_get_stat = mv88e6390_stats_get_stat,
4896 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4897 	.set_egress_port = mv88e6390_g1_set_egress_port,
4898 	.watchdog_ops = &mv88e6390_watchdog_ops,
4899 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4900 	.pot_clear = mv88e6xxx_g2_pot_clear,
4901 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4902 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4903 	.reset = mv88e6352_g1_reset,
4904 	.rmu_disable = mv88e6390_g1_rmu_disable,
4905 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4906 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4907 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4908 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4909 	.stu_getnext = mv88e6390_g1_stu_getnext,
4910 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4911 	.serdes_get_lane = mv88e6390x_serdes_get_lane,
4912 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4913 	.serdes_get_strings = mv88e6390_serdes_get_strings,
4914 	.serdes_get_stats = mv88e6390_serdes_get_stats,
4915 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4916 	.serdes_get_regs = mv88e6390_serdes_get_regs,
4917 	.gpio_ops = &mv88e6352_gpio_ops,
4918 	.phylink_get_caps = mv88e6390x_phylink_get_caps,
4919 	.pcs_ops = &mv88e6390_pcs_ops,
4920 };
4921 
4922 static const struct mv88e6xxx_ops mv88e6191_ops = {
4923 	/* MV88E6XXX_FAMILY_6390 */
4924 	.setup_errata = mv88e6390_setup_errata,
4925 	.irl_init_all = mv88e6390_g2_irl_init_all,
4926 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
4927 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
4928 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4929 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4930 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4931 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4932 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4933 	.port_set_link = mv88e6xxx_port_set_link,
4934 	.port_sync_link = mv88e6xxx_port_sync_link,
4935 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4936 	.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4937 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
4938 	.port_tag_remap = mv88e6390_port_tag_remap,
4939 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
4940 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4941 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4942 	.port_set_ether_type = mv88e6351_port_set_ether_type,
4943 	.port_pause_limit = mv88e6390_port_pause_limit,
4944 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4945 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4946 	.port_get_cmode = mv88e6352_port_get_cmode,
4947 	.port_set_cmode = mv88e6390_port_set_cmode,
4948 	.port_setup_message_port = mv88e6xxx_setup_message_port,
4949 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
4950 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4951 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
4952 	.stats_get_strings = mv88e6320_stats_get_strings,
4953 	.stats_get_stat = mv88e6390_stats_get_stat,
4954 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
4955 	.set_egress_port = mv88e6390_g1_set_egress_port,
4956 	.watchdog_ops = &mv88e6390_watchdog_ops,
4957 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4958 	.pot_clear = mv88e6xxx_g2_pot_clear,
4959 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4960 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4961 	.reset = mv88e6352_g1_reset,
4962 	.rmu_disable = mv88e6390_g1_rmu_disable,
4963 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
4964 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
4965 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
4966 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4967 	.stu_getnext = mv88e6390_g1_stu_getnext,
4968 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4969 	.serdes_get_lane = mv88e6390_serdes_get_lane,
4970 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4971 	.serdes_get_strings = mv88e6390_serdes_get_strings,
4972 	.serdes_get_stats = mv88e6390_serdes_get_stats,
4973 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4974 	.serdes_get_regs = mv88e6390_serdes_get_regs,
4975 	.avb_ops = &mv88e6390_avb_ops,
4976 	.ptp_ops = &mv88e6352_ptp_ops,
4977 	.phylink_get_caps = mv88e6390_phylink_get_caps,
4978 	.pcs_ops = &mv88e6390_pcs_ops,
4979 };
4980 
4981 static const struct mv88e6xxx_ops mv88e6240_ops = {
4982 	/* MV88E6XXX_FAMILY_6352 */
4983 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4984 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
4985 	.irl_init_all = mv88e6352_g2_irl_init_all,
4986 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
4987 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
4988 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4989 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4990 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4991 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4992 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4993 	.port_set_link = mv88e6xxx_port_set_link,
4994 	.port_sync_link = mv88e6xxx_port_sync_link,
4995 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4996 	.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4997 	.port_tag_remap = mv88e6095_port_tag_remap,
4998 	.port_set_policy = mv88e6352_port_set_policy,
4999 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5000 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5001 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5002 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5003 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5004 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5005 	.port_pause_limit = mv88e6097_port_pause_limit,
5006 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5007 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5008 	.port_get_cmode = mv88e6352_port_get_cmode,
5009 	.port_setup_leds = mv88e6xxx_port_setup_leds,
5010 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5011 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5012 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5013 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
5014 	.stats_get_strings = mv88e6095_stats_get_strings,
5015 	.stats_get_stat = mv88e6095_stats_get_stat,
5016 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5017 	.set_egress_port = mv88e6095_g1_set_egress_port,
5018 	.watchdog_ops = &mv88e6097_watchdog_ops,
5019 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5020 	.pot_clear = mv88e6xxx_g2_pot_clear,
5021 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5022 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5023 	.reset = mv88e6352_g1_reset,
5024 	.rmu_disable = mv88e6352_g1_rmu_disable,
5025 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5026 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5027 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
5028 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5029 	.stu_getnext = mv88e6352_g1_stu_getnext,
5030 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5031 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5032 	.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5033 	.serdes_get_regs = mv88e6352_serdes_get_regs,
5034 	.serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5035 	.gpio_ops = &mv88e6352_gpio_ops,
5036 	.avb_ops = &mv88e6352_avb_ops,
5037 	.ptp_ops = &mv88e6352_ptp_ops,
5038 	.phylink_get_caps = mv88e6352_phylink_get_caps,
5039 	.pcs_ops = &mv88e6352_pcs_ops,
5040 };
5041 
5042 static const struct mv88e6xxx_ops mv88e6250_ops = {
5043 	/* MV88E6XXX_FAMILY_6250 */
5044 	.ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5045 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5046 	.irl_init_all = mv88e6352_g2_irl_init_all,
5047 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
5048 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
5049 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5050 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5051 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5052 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5053 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5054 	.port_set_link = mv88e6xxx_port_set_link,
5055 	.port_sync_link = mv88e6xxx_port_sync_link,
5056 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5057 	.port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5058 	.port_tag_remap = mv88e6095_port_tag_remap,
5059 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5060 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5061 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5062 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5063 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5064 	.port_pause_limit = mv88e6097_port_pause_limit,
5065 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5066 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5067 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5068 	.stats_get_sset_count = mv88e6250_stats_get_sset_count,
5069 	.stats_get_strings = mv88e6250_stats_get_strings,
5070 	.stats_get_stat = mv88e6250_stats_get_stat,
5071 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5072 	.set_egress_port = mv88e6095_g1_set_egress_port,
5073 	.watchdog_ops = &mv88e6250_watchdog_ops,
5074 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5075 	.pot_clear = mv88e6xxx_g2_pot_clear,
5076 	.hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
5077 	.hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
5078 	.reset = mv88e6250_g1_reset,
5079 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
5080 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5081 	.avb_ops = &mv88e6352_avb_ops,
5082 	.ptp_ops = &mv88e6250_ptp_ops,
5083 	.phylink_get_caps = mv88e6250_phylink_get_caps,
5084 	.set_max_frame_size = mv88e6185_g1_set_max_frame_size,
5085 };
5086 
5087 static const struct mv88e6xxx_ops mv88e6290_ops = {
5088 	/* MV88E6XXX_FAMILY_6390 */
5089 	.setup_errata = mv88e6390_setup_errata,
5090 	.irl_init_all = mv88e6390_g2_irl_init_all,
5091 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
5092 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
5093 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5094 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5095 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5096 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5097 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5098 	.port_set_link = mv88e6xxx_port_set_link,
5099 	.port_sync_link = mv88e6xxx_port_sync_link,
5100 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5101 	.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5102 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
5103 	.port_tag_remap = mv88e6390_port_tag_remap,
5104 	.port_set_policy = mv88e6352_port_set_policy,
5105 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5106 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5107 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5108 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5109 	.port_pause_limit = mv88e6390_port_pause_limit,
5110 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5111 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5112 	.port_get_cmode = mv88e6352_port_get_cmode,
5113 	.port_set_cmode = mv88e6390_port_set_cmode,
5114 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5115 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
5116 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5117 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5118 	.stats_get_strings = mv88e6320_stats_get_strings,
5119 	.stats_get_stat = mv88e6390_stats_get_stat,
5120 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
5121 	.set_egress_port = mv88e6390_g1_set_egress_port,
5122 	.watchdog_ops = &mv88e6390_watchdog_ops,
5123 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5124 	.pot_clear = mv88e6xxx_g2_pot_clear,
5125 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5126 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5127 	.reset = mv88e6352_g1_reset,
5128 	.rmu_disable = mv88e6390_g1_rmu_disable,
5129 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5130 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5131 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
5132 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5133 	.stu_getnext = mv88e6390_g1_stu_getnext,
5134 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5135 	.serdes_get_lane = mv88e6390_serdes_get_lane,
5136 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5137 	.serdes_get_strings = mv88e6390_serdes_get_strings,
5138 	.serdes_get_stats = mv88e6390_serdes_get_stats,
5139 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5140 	.serdes_get_regs = mv88e6390_serdes_get_regs,
5141 	.gpio_ops = &mv88e6352_gpio_ops,
5142 	.avb_ops = &mv88e6390_avb_ops,
5143 	.ptp_ops = &mv88e6390_ptp_ops,
5144 	.phylink_get_caps = mv88e6390_phylink_get_caps,
5145 	.pcs_ops = &mv88e6390_pcs_ops,
5146 };
5147 
5148 static const struct mv88e6xxx_ops mv88e6320_ops = {
5149 	/* MV88E6XXX_FAMILY_6320 */
5150 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5151 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5152 	.irl_init_all = mv88e6352_g2_irl_init_all,
5153 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
5154 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
5155 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5156 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5157 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5158 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5159 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5160 	.port_set_link = mv88e6xxx_port_set_link,
5161 	.port_sync_link = mv88e6xxx_port_sync_link,
5162 	.port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5163 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5164 	.port_tag_remap = mv88e6095_port_tag_remap,
5165 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5166 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5167 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5168 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5169 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5170 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5171 	.port_pause_limit = mv88e6097_port_pause_limit,
5172 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5173 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5174 	.port_get_cmode = mv88e6352_port_get_cmode,
5175 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5176 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5177 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5178 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5179 	.stats_get_strings = mv88e6320_stats_get_strings,
5180 	.stats_get_stat = mv88e6320_stats_get_stat,
5181 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5182 	.set_egress_port = mv88e6095_g1_set_egress_port,
5183 	.watchdog_ops = &mv88e6390_watchdog_ops,
5184 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5185 	.pot_clear = mv88e6xxx_g2_pot_clear,
5186 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5187 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5188 	.reset = mv88e6352_g1_reset,
5189 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
5190 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5191 	.gpio_ops = &mv88e6352_gpio_ops,
5192 	.avb_ops = &mv88e6352_avb_ops,
5193 	.ptp_ops = &mv88e6352_ptp_ops,
5194 	.phylink_get_caps = mv88e632x_phylink_get_caps,
5195 };
5196 
5197 static const struct mv88e6xxx_ops mv88e6321_ops = {
5198 	/* MV88E6XXX_FAMILY_6320 */
5199 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5200 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5201 	.irl_init_all = mv88e6352_g2_irl_init_all,
5202 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
5203 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
5204 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5205 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5206 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5207 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5208 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5209 	.port_set_link = mv88e6xxx_port_set_link,
5210 	.port_sync_link = mv88e6xxx_port_sync_link,
5211 	.port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5212 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5213 	.port_tag_remap = mv88e6095_port_tag_remap,
5214 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5215 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5216 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5217 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5218 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5219 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5220 	.port_pause_limit = mv88e6097_port_pause_limit,
5221 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5222 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5223 	.port_get_cmode = mv88e6352_port_get_cmode,
5224 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5225 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5226 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5227 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5228 	.stats_get_strings = mv88e6320_stats_get_strings,
5229 	.stats_get_stat = mv88e6320_stats_get_stat,
5230 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5231 	.set_egress_port = mv88e6095_g1_set_egress_port,
5232 	.watchdog_ops = &mv88e6390_watchdog_ops,
5233 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5234 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5235 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5236 	.reset = mv88e6352_g1_reset,
5237 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
5238 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5239 	.gpio_ops = &mv88e6352_gpio_ops,
5240 	.avb_ops = &mv88e6352_avb_ops,
5241 	.ptp_ops = &mv88e6352_ptp_ops,
5242 	.phylink_get_caps = mv88e632x_phylink_get_caps,
5243 };
5244 
5245 static const struct mv88e6xxx_ops mv88e6341_ops = {
5246 	/* MV88E6XXX_FAMILY_6341 */
5247 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5248 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5249 	.irl_init_all = mv88e6352_g2_irl_init_all,
5250 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
5251 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
5252 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5253 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5254 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5255 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5256 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5257 	.port_set_link = mv88e6xxx_port_set_link,
5258 	.port_sync_link = mv88e6xxx_port_sync_link,
5259 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5260 	.port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5261 	.port_max_speed_mode = mv88e6341_port_max_speed_mode,
5262 	.port_tag_remap = mv88e6095_port_tag_remap,
5263 	.port_set_policy = mv88e6352_port_set_policy,
5264 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5265 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5266 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5267 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5268 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5269 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5270 	.port_pause_limit = mv88e6097_port_pause_limit,
5271 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5272 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5273 	.port_get_cmode = mv88e6352_port_get_cmode,
5274 	.port_set_cmode = mv88e6341_port_set_cmode,
5275 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5276 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
5277 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5278 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5279 	.stats_get_strings = mv88e6320_stats_get_strings,
5280 	.stats_get_stat = mv88e6390_stats_get_stat,
5281 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
5282 	.set_egress_port = mv88e6390_g1_set_egress_port,
5283 	.watchdog_ops = &mv88e6390_watchdog_ops,
5284 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5285 	.pot_clear = mv88e6xxx_g2_pot_clear,
5286 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5287 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5288 	.reset = mv88e6352_g1_reset,
5289 	.rmu_disable = mv88e6390_g1_rmu_disable,
5290 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5291 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5292 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
5293 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5294 	.stu_getnext = mv88e6352_g1_stu_getnext,
5295 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5296 	.serdes_get_lane = mv88e6341_serdes_get_lane,
5297 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5298 	.gpio_ops = &mv88e6352_gpio_ops,
5299 	.avb_ops = &mv88e6390_avb_ops,
5300 	.ptp_ops = &mv88e6352_ptp_ops,
5301 	.serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5302 	.serdes_get_strings = mv88e6390_serdes_get_strings,
5303 	.serdes_get_stats = mv88e6390_serdes_get_stats,
5304 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5305 	.serdes_get_regs = mv88e6390_serdes_get_regs,
5306 	.phylink_get_caps = mv88e6341_phylink_get_caps,
5307 	.pcs_ops = &mv88e6390_pcs_ops,
5308 };
5309 
5310 static const struct mv88e6xxx_ops mv88e6350_ops = {
5311 	/* MV88E6XXX_FAMILY_6351 */
5312 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5313 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5314 	.irl_init_all = mv88e6352_g2_irl_init_all,
5315 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5316 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5317 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5318 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5319 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5320 	.port_set_link = mv88e6xxx_port_set_link,
5321 	.port_sync_link = mv88e6xxx_port_sync_link,
5322 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5323 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5324 	.port_tag_remap = mv88e6095_port_tag_remap,
5325 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5326 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5327 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5328 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5329 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5330 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5331 	.port_pause_limit = mv88e6097_port_pause_limit,
5332 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5333 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5334 	.port_get_cmode = mv88e6352_port_get_cmode,
5335 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5336 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5337 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5338 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
5339 	.stats_get_strings = mv88e6095_stats_get_strings,
5340 	.stats_get_stat = mv88e6095_stats_get_stat,
5341 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5342 	.set_egress_port = mv88e6095_g1_set_egress_port,
5343 	.watchdog_ops = &mv88e6097_watchdog_ops,
5344 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5345 	.pot_clear = mv88e6xxx_g2_pot_clear,
5346 	.reset = mv88e6352_g1_reset,
5347 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5348 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5349 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
5350 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5351 	.stu_getnext = mv88e6352_g1_stu_getnext,
5352 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5353 	.phylink_get_caps = mv88e6351_phylink_get_caps,
5354 };
5355 
5356 static const struct mv88e6xxx_ops mv88e6351_ops = {
5357 	/* MV88E6XXX_FAMILY_6351 */
5358 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5359 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5360 	.irl_init_all = mv88e6352_g2_irl_init_all,
5361 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5362 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5363 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5364 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5365 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5366 	.port_set_link = mv88e6xxx_port_set_link,
5367 	.port_sync_link = mv88e6xxx_port_sync_link,
5368 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5369 	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5370 	.port_tag_remap = mv88e6095_port_tag_remap,
5371 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5372 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5373 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5374 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5375 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5376 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5377 	.port_pause_limit = mv88e6097_port_pause_limit,
5378 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5379 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5380 	.port_get_cmode = mv88e6352_port_get_cmode,
5381 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5382 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5383 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5384 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
5385 	.stats_get_strings = mv88e6095_stats_get_strings,
5386 	.stats_get_stat = mv88e6095_stats_get_stat,
5387 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5388 	.set_egress_port = mv88e6095_g1_set_egress_port,
5389 	.watchdog_ops = &mv88e6097_watchdog_ops,
5390 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5391 	.pot_clear = mv88e6xxx_g2_pot_clear,
5392 	.reset = mv88e6352_g1_reset,
5393 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5394 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5395 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
5396 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5397 	.stu_getnext = mv88e6352_g1_stu_getnext,
5398 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5399 	.avb_ops = &mv88e6352_avb_ops,
5400 	.ptp_ops = &mv88e6352_ptp_ops,
5401 	.phylink_get_caps = mv88e6351_phylink_get_caps,
5402 };
5403 
5404 static const struct mv88e6xxx_ops mv88e6352_ops = {
5405 	/* MV88E6XXX_FAMILY_6352 */
5406 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5407 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
5408 	.irl_init_all = mv88e6352_g2_irl_init_all,
5409 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
5410 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
5411 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5412 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5413 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5414 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5415 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5416 	.port_set_link = mv88e6xxx_port_set_link,
5417 	.port_sync_link = mv88e6xxx_port_sync_link,
5418 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5419 	.port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5420 	.port_tag_remap = mv88e6095_port_tag_remap,
5421 	.port_set_policy = mv88e6352_port_set_policy,
5422 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5423 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5424 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5425 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5426 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5427 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5428 	.port_pause_limit = mv88e6097_port_pause_limit,
5429 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5430 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5431 	.port_get_cmode = mv88e6352_port_get_cmode,
5432 	.port_setup_leds = mv88e6xxx_port_setup_leds,
5433 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5434 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
5435 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5436 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
5437 	.stats_get_strings = mv88e6095_stats_get_strings,
5438 	.stats_get_stat = mv88e6095_stats_get_stat,
5439 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
5440 	.set_egress_port = mv88e6095_g1_set_egress_port,
5441 	.watchdog_ops = &mv88e6097_watchdog_ops,
5442 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5443 	.pot_clear = mv88e6xxx_g2_pot_clear,
5444 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5445 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5446 	.reset = mv88e6352_g1_reset,
5447 	.rmu_disable = mv88e6352_g1_rmu_disable,
5448 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5449 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5450 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
5451 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5452 	.stu_getnext = mv88e6352_g1_stu_getnext,
5453 	.stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5454 	.serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5455 	.gpio_ops = &mv88e6352_gpio_ops,
5456 	.avb_ops = &mv88e6352_avb_ops,
5457 	.ptp_ops = &mv88e6352_ptp_ops,
5458 	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5459 	.serdes_get_strings = mv88e6352_serdes_get_strings,
5460 	.serdes_get_stats = mv88e6352_serdes_get_stats,
5461 	.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5462 	.serdes_get_regs = mv88e6352_serdes_get_regs,
5463 	.serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5464 	.phylink_get_caps = mv88e6352_phylink_get_caps,
5465 	.pcs_ops = &mv88e6352_pcs_ops,
5466 };
5467 
5468 static const struct mv88e6xxx_ops mv88e6390_ops = {
5469 	/* MV88E6XXX_FAMILY_6390 */
5470 	.setup_errata = mv88e6390_setup_errata,
5471 	.irl_init_all = mv88e6390_g2_irl_init_all,
5472 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
5473 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
5474 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5475 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5476 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5477 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5478 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5479 	.port_set_link = mv88e6xxx_port_set_link,
5480 	.port_sync_link = mv88e6xxx_port_sync_link,
5481 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5482 	.port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5483 	.port_max_speed_mode = mv88e6390_port_max_speed_mode,
5484 	.port_tag_remap = mv88e6390_port_tag_remap,
5485 	.port_set_policy = mv88e6352_port_set_policy,
5486 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5487 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5488 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5489 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5490 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5491 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5492 	.port_pause_limit = mv88e6390_port_pause_limit,
5493 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5494 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5495 	.port_get_cmode = mv88e6352_port_get_cmode,
5496 	.port_set_cmode = mv88e6390_port_set_cmode,
5497 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5498 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
5499 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5500 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5501 	.stats_get_strings = mv88e6320_stats_get_strings,
5502 	.stats_get_stat = mv88e6390_stats_get_stat,
5503 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
5504 	.set_egress_port = mv88e6390_g1_set_egress_port,
5505 	.watchdog_ops = &mv88e6390_watchdog_ops,
5506 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5507 	.pot_clear = mv88e6xxx_g2_pot_clear,
5508 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5509 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5510 	.reset = mv88e6352_g1_reset,
5511 	.rmu_disable = mv88e6390_g1_rmu_disable,
5512 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5513 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5514 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
5515 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5516 	.stu_getnext = mv88e6390_g1_stu_getnext,
5517 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5518 	.serdes_get_lane = mv88e6390_serdes_get_lane,
5519 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5520 	.gpio_ops = &mv88e6352_gpio_ops,
5521 	.avb_ops = &mv88e6390_avb_ops,
5522 	.ptp_ops = &mv88e6390_ptp_ops,
5523 	.serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5524 	.serdes_get_strings = mv88e6390_serdes_get_strings,
5525 	.serdes_get_stats = mv88e6390_serdes_get_stats,
5526 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5527 	.serdes_get_regs = mv88e6390_serdes_get_regs,
5528 	.phylink_get_caps = mv88e6390_phylink_get_caps,
5529 	.pcs_ops = &mv88e6390_pcs_ops,
5530 };
5531 
5532 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5533 	/* MV88E6XXX_FAMILY_6390 */
5534 	.setup_errata = mv88e6390_setup_errata,
5535 	.irl_init_all = mv88e6390_g2_irl_init_all,
5536 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
5537 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
5538 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5539 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5540 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5541 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5542 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5543 	.port_set_link = mv88e6xxx_port_set_link,
5544 	.port_sync_link = mv88e6xxx_port_sync_link,
5545 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5546 	.port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5547 	.port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5548 	.port_tag_remap = mv88e6390_port_tag_remap,
5549 	.port_set_policy = mv88e6352_port_set_policy,
5550 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5551 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5552 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5553 	.port_set_ether_type = mv88e6351_port_set_ether_type,
5554 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5555 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5556 	.port_pause_limit = mv88e6390_port_pause_limit,
5557 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5558 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5559 	.port_get_cmode = mv88e6352_port_get_cmode,
5560 	.port_set_cmode = mv88e6390x_port_set_cmode,
5561 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5562 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
5563 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5564 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5565 	.stats_get_strings = mv88e6320_stats_get_strings,
5566 	.stats_get_stat = mv88e6390_stats_get_stat,
5567 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
5568 	.set_egress_port = mv88e6390_g1_set_egress_port,
5569 	.watchdog_ops = &mv88e6390_watchdog_ops,
5570 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5571 	.pot_clear = mv88e6xxx_g2_pot_clear,
5572 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5573 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5574 	.reset = mv88e6352_g1_reset,
5575 	.rmu_disable = mv88e6390_g1_rmu_disable,
5576 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5577 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5578 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
5579 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5580 	.stu_getnext = mv88e6390_g1_stu_getnext,
5581 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5582 	.serdes_get_lane = mv88e6390x_serdes_get_lane,
5583 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5584 	.serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5585 	.serdes_get_strings = mv88e6390_serdes_get_strings,
5586 	.serdes_get_stats = mv88e6390_serdes_get_stats,
5587 	.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5588 	.serdes_get_regs = mv88e6390_serdes_get_regs,
5589 	.gpio_ops = &mv88e6352_gpio_ops,
5590 	.avb_ops = &mv88e6390_avb_ops,
5591 	.ptp_ops = &mv88e6390_ptp_ops,
5592 	.phylink_get_caps = mv88e6390x_phylink_get_caps,
5593 	.pcs_ops = &mv88e6390_pcs_ops,
5594 };
5595 
5596 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5597 	/* MV88E6XXX_FAMILY_6393 */
5598 	.irl_init_all = mv88e6390_g2_irl_init_all,
5599 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
5600 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
5601 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5602 	.phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5603 	.phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5604 	.phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5605 	.phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5606 	.port_set_link = mv88e6xxx_port_set_link,
5607 	.port_sync_link = mv88e6xxx_port_sync_link,
5608 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5609 	.port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5610 	.port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5611 	.port_tag_remap = mv88e6390_port_tag_remap,
5612 	.port_set_policy = mv88e6393x_port_set_policy,
5613 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
5614 	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5615 	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5616 	.port_set_ether_type = mv88e6393x_port_set_ether_type,
5617 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5618 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5619 	.port_pause_limit = mv88e6390_port_pause_limit,
5620 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5621 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5622 	.port_get_cmode = mv88e6352_port_get_cmode,
5623 	.port_set_cmode = mv88e6393x_port_set_cmode,
5624 	.port_setup_message_port = mv88e6xxx_setup_message_port,
5625 	.port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5626 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
5627 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5628 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
5629 	.stats_get_strings = mv88e6320_stats_get_strings,
5630 	.stats_get_stat = mv88e6390_stats_get_stat,
5631 	/* .set_cpu_port is missing because this family does not support a global
5632 	 * CPU port, only per port CPU port which is set via
5633 	 * .port_set_upstream_port method.
5634 	 */
5635 	.set_egress_port = mv88e6393x_set_egress_port,
5636 	.watchdog_ops = &mv88e6393x_watchdog_ops,
5637 	.mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5638 	.pot_clear = mv88e6xxx_g2_pot_clear,
5639 	.hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5640 	.hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5641 	.reset = mv88e6352_g1_reset,
5642 	.rmu_disable = mv88e6390_g1_rmu_disable,
5643 	.atu_get_hash = mv88e6165_g1_atu_get_hash,
5644 	.atu_set_hash = mv88e6165_g1_atu_set_hash,
5645 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
5646 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5647 	.stu_getnext = mv88e6390_g1_stu_getnext,
5648 	.stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5649 	.serdes_get_lane = mv88e6393x_serdes_get_lane,
5650 	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5651 	/* TODO: serdes stats */
5652 	.gpio_ops = &mv88e6352_gpio_ops,
5653 	.avb_ops = &mv88e6390_avb_ops,
5654 	.ptp_ops = &mv88e6352_ptp_ops,
5655 	.phylink_get_caps = mv88e6393x_phylink_get_caps,
5656 	.pcs_ops = &mv88e6393x_pcs_ops,
5657 };
5658 
5659 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5660 	[MV88E6020] = {
5661 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5662 		.family = MV88E6XXX_FAMILY_6250,
5663 		.name = "Marvell 88E6020",
5664 		.num_databases = 64,
5665 		/* Ports 2-4 are not routed to pins
5666 		 * => usable ports 0, 1, 5, 6
5667 		 */
5668 		.num_ports = 7,
5669 		.num_internal_phys = 2,
5670 		.invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5671 		.max_vid = 4095,
5672 		.port_base_addr = 0x8,
5673 		.phy_base_addr = 0x0,
5674 		.global1_addr = 0xf,
5675 		.global2_addr = 0x7,
5676 		.age_time_coeff = 15000,
5677 		.g1_irqs = 9,
5678 		.g2_irqs = 5,
5679 		.atu_move_port_mask = 0xf,
5680 		.dual_chip = true,
5681 		.ops = &mv88e6250_ops,
5682 	},
5683 
5684 	[MV88E6071] = {
5685 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5686 		.family = MV88E6XXX_FAMILY_6250,
5687 		.name = "Marvell 88E6071",
5688 		.num_databases = 64,
5689 		.num_ports = 7,
5690 		.num_internal_phys = 5,
5691 		.max_vid = 4095,
5692 		.port_base_addr = 0x08,
5693 		.phy_base_addr = 0x00,
5694 		.global1_addr = 0x0f,
5695 		.global2_addr = 0x07,
5696 		.age_time_coeff = 15000,
5697 		.g1_irqs = 9,
5698 		.g2_irqs = 5,
5699 		.atu_move_port_mask = 0xf,
5700 		.dual_chip = true,
5701 		.ops = &mv88e6250_ops,
5702 	},
5703 
5704 	[MV88E6085] = {
5705 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5706 		.family = MV88E6XXX_FAMILY_6097,
5707 		.name = "Marvell 88E6085",
5708 		.num_databases = 4096,
5709 		.num_macs = 8192,
5710 		.num_ports = 10,
5711 		.num_internal_phys = 5,
5712 		.max_vid = 4095,
5713 		.max_sid = 63,
5714 		.port_base_addr = 0x10,
5715 		.phy_base_addr = 0x0,
5716 		.global1_addr = 0x1b,
5717 		.global2_addr = 0x1c,
5718 		.age_time_coeff = 15000,
5719 		.g1_irqs = 8,
5720 		.g2_irqs = 10,
5721 		.atu_move_port_mask = 0xf,
5722 		.pvt = true,
5723 		.multi_chip = true,
5724 		.ops = &mv88e6085_ops,
5725 	},
5726 
5727 	[MV88E6095] = {
5728 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5729 		.family = MV88E6XXX_FAMILY_6095,
5730 		.name = "Marvell 88E6095/88E6095F",
5731 		.num_databases = 256,
5732 		.num_macs = 8192,
5733 		.num_ports = 11,
5734 		.num_internal_phys = 0,
5735 		.max_vid = 4095,
5736 		.port_base_addr = 0x10,
5737 		.phy_base_addr = 0x0,
5738 		.global1_addr = 0x1b,
5739 		.global2_addr = 0x1c,
5740 		.age_time_coeff = 15000,
5741 		.g1_irqs = 8,
5742 		.atu_move_port_mask = 0xf,
5743 		.multi_chip = true,
5744 		.ops = &mv88e6095_ops,
5745 	},
5746 
5747 	[MV88E6097] = {
5748 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5749 		.family = MV88E6XXX_FAMILY_6097,
5750 		.name = "Marvell 88E6097/88E6097F",
5751 		.num_databases = 4096,
5752 		.num_macs = 8192,
5753 		.num_ports = 11,
5754 		.num_internal_phys = 8,
5755 		.max_vid = 4095,
5756 		.max_sid = 63,
5757 		.port_base_addr = 0x10,
5758 		.phy_base_addr = 0x0,
5759 		.global1_addr = 0x1b,
5760 		.global2_addr = 0x1c,
5761 		.age_time_coeff = 15000,
5762 		.g1_irqs = 8,
5763 		.g2_irqs = 10,
5764 		.atu_move_port_mask = 0xf,
5765 		.pvt = true,
5766 		.multi_chip = true,
5767 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5768 		.ops = &mv88e6097_ops,
5769 	},
5770 
5771 	[MV88E6123] = {
5772 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5773 		.family = MV88E6XXX_FAMILY_6165,
5774 		.name = "Marvell 88E6123",
5775 		.num_databases = 4096,
5776 		.num_macs = 1024,
5777 		.num_ports = 3,
5778 		.num_internal_phys = 5,
5779 		.max_vid = 4095,
5780 		.max_sid = 63,
5781 		.port_base_addr = 0x10,
5782 		.phy_base_addr = 0x0,
5783 		.global1_addr = 0x1b,
5784 		.global2_addr = 0x1c,
5785 		.age_time_coeff = 15000,
5786 		.g1_irqs = 9,
5787 		.g2_irqs = 10,
5788 		.atu_move_port_mask = 0xf,
5789 		.pvt = true,
5790 		.multi_chip = true,
5791 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5792 		.ops = &mv88e6123_ops,
5793 	},
5794 
5795 	[MV88E6131] = {
5796 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5797 		.family = MV88E6XXX_FAMILY_6185,
5798 		.name = "Marvell 88E6131",
5799 		.num_databases = 256,
5800 		.num_macs = 8192,
5801 		.num_ports = 8,
5802 		.num_internal_phys = 0,
5803 		.max_vid = 4095,
5804 		.port_base_addr = 0x10,
5805 		.phy_base_addr = 0x0,
5806 		.global1_addr = 0x1b,
5807 		.global2_addr = 0x1c,
5808 		.age_time_coeff = 15000,
5809 		.g1_irqs = 9,
5810 		.atu_move_port_mask = 0xf,
5811 		.multi_chip = true,
5812 		.ops = &mv88e6131_ops,
5813 	},
5814 
5815 	[MV88E6141] = {
5816 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5817 		.family = MV88E6XXX_FAMILY_6341,
5818 		.name = "Marvell 88E6141",
5819 		.num_databases = 256,
5820 		.num_macs = 2048,
5821 		.num_ports = 6,
5822 		.num_internal_phys = 5,
5823 		.num_gpio = 11,
5824 		.max_vid = 4095,
5825 		.max_sid = 63,
5826 		.port_base_addr = 0x10,
5827 		.phy_base_addr = 0x10,
5828 		.global1_addr = 0x1b,
5829 		.global2_addr = 0x1c,
5830 		.age_time_coeff = 3750,
5831 		.atu_move_port_mask = 0x1f,
5832 		.g1_irqs = 9,
5833 		.g2_irqs = 10,
5834 		.pvt = true,
5835 		.multi_chip = true,
5836 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5837 		.ops = &mv88e6141_ops,
5838 	},
5839 
5840 	[MV88E6161] = {
5841 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5842 		.family = MV88E6XXX_FAMILY_6165,
5843 		.name = "Marvell 88E6161",
5844 		.num_databases = 4096,
5845 		.num_macs = 1024,
5846 		.num_ports = 6,
5847 		.num_internal_phys = 5,
5848 		.max_vid = 4095,
5849 		.max_sid = 63,
5850 		.port_base_addr = 0x10,
5851 		.phy_base_addr = 0x0,
5852 		.global1_addr = 0x1b,
5853 		.global2_addr = 0x1c,
5854 		.age_time_coeff = 15000,
5855 		.g1_irqs = 9,
5856 		.g2_irqs = 10,
5857 		.atu_move_port_mask = 0xf,
5858 		.pvt = true,
5859 		.multi_chip = true,
5860 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5861 		.ptp_support = true,
5862 		.ops = &mv88e6161_ops,
5863 	},
5864 
5865 	[MV88E6165] = {
5866 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5867 		.family = MV88E6XXX_FAMILY_6165,
5868 		.name = "Marvell 88E6165",
5869 		.num_databases = 4096,
5870 		.num_macs = 8192,
5871 		.num_ports = 6,
5872 		.num_internal_phys = 0,
5873 		.max_vid = 4095,
5874 		.max_sid = 63,
5875 		.port_base_addr = 0x10,
5876 		.phy_base_addr = 0x0,
5877 		.global1_addr = 0x1b,
5878 		.global2_addr = 0x1c,
5879 		.age_time_coeff = 15000,
5880 		.g1_irqs = 9,
5881 		.g2_irqs = 10,
5882 		.atu_move_port_mask = 0xf,
5883 		.pvt = true,
5884 		.multi_chip = true,
5885 		.ptp_support = true,
5886 		.ops = &mv88e6165_ops,
5887 	},
5888 
5889 	[MV88E6171] = {
5890 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5891 		.family = MV88E6XXX_FAMILY_6351,
5892 		.name = "Marvell 88E6171",
5893 		.num_databases = 4096,
5894 		.num_macs = 8192,
5895 		.num_ports = 7,
5896 		.num_internal_phys = 5,
5897 		.max_vid = 4095,
5898 		.max_sid = 63,
5899 		.port_base_addr = 0x10,
5900 		.phy_base_addr = 0x0,
5901 		.global1_addr = 0x1b,
5902 		.global2_addr = 0x1c,
5903 		.age_time_coeff = 15000,
5904 		.g1_irqs = 9,
5905 		.g2_irqs = 10,
5906 		.atu_move_port_mask = 0xf,
5907 		.pvt = true,
5908 		.multi_chip = true,
5909 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5910 		.ops = &mv88e6171_ops,
5911 	},
5912 
5913 	[MV88E6172] = {
5914 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5915 		.family = MV88E6XXX_FAMILY_6352,
5916 		.name = "Marvell 88E6172",
5917 		.num_databases = 4096,
5918 		.num_macs = 8192,
5919 		.num_ports = 7,
5920 		.num_internal_phys = 5,
5921 		.num_gpio = 15,
5922 		.max_vid = 4095,
5923 		.max_sid = 63,
5924 		.port_base_addr = 0x10,
5925 		.phy_base_addr = 0x0,
5926 		.global1_addr = 0x1b,
5927 		.global2_addr = 0x1c,
5928 		.age_time_coeff = 15000,
5929 		.g1_irqs = 9,
5930 		.g2_irqs = 10,
5931 		.atu_move_port_mask = 0xf,
5932 		.pvt = true,
5933 		.multi_chip = true,
5934 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5935 		.ops = &mv88e6172_ops,
5936 	},
5937 
5938 	[MV88E6175] = {
5939 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5940 		.family = MV88E6XXX_FAMILY_6351,
5941 		.name = "Marvell 88E6175",
5942 		.num_databases = 4096,
5943 		.num_macs = 8192,
5944 		.num_ports = 7,
5945 		.num_internal_phys = 5,
5946 		.max_vid = 4095,
5947 		.max_sid = 63,
5948 		.port_base_addr = 0x10,
5949 		.phy_base_addr = 0x0,
5950 		.global1_addr = 0x1b,
5951 		.global2_addr = 0x1c,
5952 		.age_time_coeff = 15000,
5953 		.g1_irqs = 9,
5954 		.g2_irqs = 10,
5955 		.atu_move_port_mask = 0xf,
5956 		.pvt = true,
5957 		.multi_chip = true,
5958 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5959 		.ops = &mv88e6175_ops,
5960 	},
5961 
5962 	[MV88E6176] = {
5963 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5964 		.family = MV88E6XXX_FAMILY_6352,
5965 		.name = "Marvell 88E6176",
5966 		.num_databases = 4096,
5967 		.num_macs = 8192,
5968 		.num_ports = 7,
5969 		.num_internal_phys = 5,
5970 		.num_gpio = 15,
5971 		.max_vid = 4095,
5972 		.max_sid = 63,
5973 		.port_base_addr = 0x10,
5974 		.phy_base_addr = 0x0,
5975 		.global1_addr = 0x1b,
5976 		.global2_addr = 0x1c,
5977 		.age_time_coeff = 15000,
5978 		.g1_irqs = 9,
5979 		.g2_irqs = 10,
5980 		.atu_move_port_mask = 0xf,
5981 		.pvt = true,
5982 		.multi_chip = true,
5983 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5984 		.ops = &mv88e6176_ops,
5985 	},
5986 
5987 	[MV88E6185] = {
5988 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5989 		.family = MV88E6XXX_FAMILY_6185,
5990 		.name = "Marvell 88E6185",
5991 		.num_databases = 256,
5992 		.num_macs = 8192,
5993 		.num_ports = 10,
5994 		.num_internal_phys = 0,
5995 		.max_vid = 4095,
5996 		.port_base_addr = 0x10,
5997 		.phy_base_addr = 0x0,
5998 		.global1_addr = 0x1b,
5999 		.global2_addr = 0x1c,
6000 		.age_time_coeff = 15000,
6001 		.g1_irqs = 8,
6002 		.atu_move_port_mask = 0xf,
6003 		.multi_chip = true,
6004 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6005 		.ops = &mv88e6185_ops,
6006 	},
6007 
6008 	[MV88E6190] = {
6009 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
6010 		.family = MV88E6XXX_FAMILY_6390,
6011 		.name = "Marvell 88E6190",
6012 		.num_databases = 4096,
6013 		.num_macs = 16384,
6014 		.num_ports = 11,	/* 10 + Z80 */
6015 		.num_internal_phys = 9,
6016 		.num_gpio = 16,
6017 		.max_vid = 8191,
6018 		.max_sid = 63,
6019 		.port_base_addr = 0x0,
6020 		.phy_base_addr = 0x0,
6021 		.global1_addr = 0x1b,
6022 		.global2_addr = 0x1c,
6023 		.age_time_coeff = 3750,
6024 		.g1_irqs = 9,
6025 		.g2_irqs = 14,
6026 		.pvt = true,
6027 		.multi_chip = true,
6028 		.atu_move_port_mask = 0x1f,
6029 		.ops = &mv88e6190_ops,
6030 	},
6031 
6032 	[MV88E6190X] = {
6033 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
6034 		.family = MV88E6XXX_FAMILY_6390,
6035 		.name = "Marvell 88E6190X",
6036 		.num_databases = 4096,
6037 		.num_macs = 16384,
6038 		.num_ports = 11,	/* 10 + Z80 */
6039 		.num_internal_phys = 9,
6040 		.num_gpio = 16,
6041 		.max_vid = 8191,
6042 		.max_sid = 63,
6043 		.port_base_addr = 0x0,
6044 		.phy_base_addr = 0x0,
6045 		.global1_addr = 0x1b,
6046 		.global2_addr = 0x1c,
6047 		.age_time_coeff = 3750,
6048 		.g1_irqs = 9,
6049 		.g2_irqs = 14,
6050 		.atu_move_port_mask = 0x1f,
6051 		.pvt = true,
6052 		.multi_chip = true,
6053 		.ops = &mv88e6190x_ops,
6054 	},
6055 
6056 	[MV88E6191] = {
6057 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
6058 		.family = MV88E6XXX_FAMILY_6390,
6059 		.name = "Marvell 88E6191",
6060 		.num_databases = 4096,
6061 		.num_macs = 16384,
6062 		.num_ports = 11,	/* 10 + Z80 */
6063 		.num_internal_phys = 9,
6064 		.max_vid = 8191,
6065 		.max_sid = 63,
6066 		.port_base_addr = 0x0,
6067 		.phy_base_addr = 0x0,
6068 		.global1_addr = 0x1b,
6069 		.global2_addr = 0x1c,
6070 		.age_time_coeff = 3750,
6071 		.g1_irqs = 9,
6072 		.g2_irqs = 14,
6073 		.atu_move_port_mask = 0x1f,
6074 		.pvt = true,
6075 		.multi_chip = true,
6076 		.ptp_support = true,
6077 		.ops = &mv88e6191_ops,
6078 	},
6079 
6080 	[MV88E6191X] = {
6081 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6082 		.family = MV88E6XXX_FAMILY_6393,
6083 		.name = "Marvell 88E6191X",
6084 		.num_databases = 4096,
6085 		.num_ports = 11,	/* 10 + Z80 */
6086 		.num_internal_phys = 8,
6087 		.internal_phys_offset = 1,
6088 		.max_vid = 8191,
6089 		.max_sid = 63,
6090 		.port_base_addr = 0x0,
6091 		.phy_base_addr = 0x0,
6092 		.global1_addr = 0x1b,
6093 		.global2_addr = 0x1c,
6094 		.age_time_coeff = 3750,
6095 		.g1_irqs = 10,
6096 		.g2_irqs = 14,
6097 		.atu_move_port_mask = 0x1f,
6098 		.pvt = true,
6099 		.multi_chip = true,
6100 		.ptp_support = true,
6101 		.ops = &mv88e6393x_ops,
6102 	},
6103 
6104 	[MV88E6193X] = {
6105 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6106 		.family = MV88E6XXX_FAMILY_6393,
6107 		.name = "Marvell 88E6193X",
6108 		.num_databases = 4096,
6109 		.num_ports = 11,	/* 10 + Z80 */
6110 		.num_internal_phys = 8,
6111 		.internal_phys_offset = 1,
6112 		.max_vid = 8191,
6113 		.max_sid = 63,
6114 		.port_base_addr = 0x0,
6115 		.phy_base_addr = 0x0,
6116 		.global1_addr = 0x1b,
6117 		.global2_addr = 0x1c,
6118 		.age_time_coeff = 3750,
6119 		.g1_irqs = 10,
6120 		.g2_irqs = 14,
6121 		.atu_move_port_mask = 0x1f,
6122 		.pvt = true,
6123 		.multi_chip = true,
6124 		.ptp_support = true,
6125 		.ops = &mv88e6393x_ops,
6126 	},
6127 
6128 	[MV88E6220] = {
6129 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6130 		.family = MV88E6XXX_FAMILY_6250,
6131 		.name = "Marvell 88E6220",
6132 		.num_databases = 64,
6133 
6134 		/* Ports 2-4 are not routed to pins
6135 		 * => usable ports 0, 1, 5, 6
6136 		 */
6137 		.num_ports = 7,
6138 		.num_internal_phys = 2,
6139 		.invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6140 		.max_vid = 4095,
6141 		.port_base_addr = 0x08,
6142 		.phy_base_addr = 0x00,
6143 		.global1_addr = 0x0f,
6144 		.global2_addr = 0x07,
6145 		.age_time_coeff = 15000,
6146 		.g1_irqs = 9,
6147 		.g2_irqs = 10,
6148 		.atu_move_port_mask = 0xf,
6149 		.dual_chip = true,
6150 		.ptp_support = true,
6151 		.ops = &mv88e6250_ops,
6152 	},
6153 
6154 	[MV88E6240] = {
6155 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6156 		.family = MV88E6XXX_FAMILY_6352,
6157 		.name = "Marvell 88E6240",
6158 		.num_databases = 4096,
6159 		.num_macs = 8192,
6160 		.num_ports = 7,
6161 		.num_internal_phys = 5,
6162 		.num_gpio = 15,
6163 		.max_vid = 4095,
6164 		.max_sid = 63,
6165 		.port_base_addr = 0x10,
6166 		.phy_base_addr = 0x0,
6167 		.global1_addr = 0x1b,
6168 		.global2_addr = 0x1c,
6169 		.age_time_coeff = 15000,
6170 		.g1_irqs = 9,
6171 		.g2_irqs = 10,
6172 		.atu_move_port_mask = 0xf,
6173 		.pvt = true,
6174 		.multi_chip = true,
6175 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6176 		.ptp_support = true,
6177 		.ops = &mv88e6240_ops,
6178 	},
6179 
6180 	[MV88E6250] = {
6181 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6182 		.family = MV88E6XXX_FAMILY_6250,
6183 		.name = "Marvell 88E6250",
6184 		.num_databases = 64,
6185 		.num_ports = 7,
6186 		.num_internal_phys = 5,
6187 		.max_vid = 4095,
6188 		.port_base_addr = 0x08,
6189 		.phy_base_addr = 0x00,
6190 		.global1_addr = 0x0f,
6191 		.global2_addr = 0x07,
6192 		.age_time_coeff = 15000,
6193 		.g1_irqs = 9,
6194 		.g2_irqs = 10,
6195 		.atu_move_port_mask = 0xf,
6196 		.dual_chip = true,
6197 		.ptp_support = true,
6198 		.ops = &mv88e6250_ops,
6199 	},
6200 
6201 	[MV88E6290] = {
6202 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6203 		.family = MV88E6XXX_FAMILY_6390,
6204 		.name = "Marvell 88E6290",
6205 		.num_databases = 4096,
6206 		.num_ports = 11,	/* 10 + Z80 */
6207 		.num_internal_phys = 9,
6208 		.num_gpio = 16,
6209 		.max_vid = 8191,
6210 		.max_sid = 63,
6211 		.port_base_addr = 0x0,
6212 		.phy_base_addr = 0x0,
6213 		.global1_addr = 0x1b,
6214 		.global2_addr = 0x1c,
6215 		.age_time_coeff = 3750,
6216 		.g1_irqs = 9,
6217 		.g2_irqs = 14,
6218 		.atu_move_port_mask = 0x1f,
6219 		.pvt = true,
6220 		.multi_chip = true,
6221 		.ptp_support = true,
6222 		.ops = &mv88e6290_ops,
6223 	},
6224 
6225 	[MV88E6320] = {
6226 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6227 		.family = MV88E6XXX_FAMILY_6320,
6228 		.name = "Marvell 88E6320",
6229 		.num_databases = 4096,
6230 		.num_macs = 8192,
6231 		.num_ports = 7,
6232 		.num_internal_phys = 5,
6233 		.num_gpio = 15,
6234 		.max_vid = 4095,
6235 		.port_base_addr = 0x10,
6236 		.phy_base_addr = 0x0,
6237 		.global1_addr = 0x1b,
6238 		.global2_addr = 0x1c,
6239 		.age_time_coeff = 15000,
6240 		.g1_irqs = 8,
6241 		.g2_irqs = 10,
6242 		.atu_move_port_mask = 0xf,
6243 		.pvt = true,
6244 		.multi_chip = true,
6245 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6246 		.ptp_support = true,
6247 		.ops = &mv88e6320_ops,
6248 	},
6249 
6250 	[MV88E6321] = {
6251 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6252 		.family = MV88E6XXX_FAMILY_6320,
6253 		.name = "Marvell 88E6321",
6254 		.num_databases = 4096,
6255 		.num_macs = 8192,
6256 		.num_ports = 7,
6257 		.num_internal_phys = 5,
6258 		.num_gpio = 15,
6259 		.max_vid = 4095,
6260 		.port_base_addr = 0x10,
6261 		.phy_base_addr = 0x0,
6262 		.global1_addr = 0x1b,
6263 		.global2_addr = 0x1c,
6264 		.age_time_coeff = 15000,
6265 		.g1_irqs = 8,
6266 		.g2_irqs = 10,
6267 		.atu_move_port_mask = 0xf,
6268 		.multi_chip = true,
6269 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6270 		.ptp_support = true,
6271 		.ops = &mv88e6321_ops,
6272 	},
6273 
6274 	[MV88E6341] = {
6275 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6276 		.family = MV88E6XXX_FAMILY_6341,
6277 		.name = "Marvell 88E6341",
6278 		.num_databases = 256,
6279 		.num_macs = 2048,
6280 		.num_internal_phys = 5,
6281 		.num_ports = 6,
6282 		.num_gpio = 11,
6283 		.max_vid = 4095,
6284 		.max_sid = 63,
6285 		.port_base_addr = 0x10,
6286 		.phy_base_addr = 0x10,
6287 		.global1_addr = 0x1b,
6288 		.global2_addr = 0x1c,
6289 		.age_time_coeff = 3750,
6290 		.atu_move_port_mask = 0x1f,
6291 		.g1_irqs = 9,
6292 		.g2_irqs = 10,
6293 		.pvt = true,
6294 		.multi_chip = true,
6295 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6296 		.ptp_support = true,
6297 		.ops = &mv88e6341_ops,
6298 	},
6299 
6300 	[MV88E6350] = {
6301 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6302 		.family = MV88E6XXX_FAMILY_6351,
6303 		.name = "Marvell 88E6350",
6304 		.num_databases = 4096,
6305 		.num_macs = 8192,
6306 		.num_ports = 7,
6307 		.num_internal_phys = 5,
6308 		.max_vid = 4095,
6309 		.max_sid = 63,
6310 		.port_base_addr = 0x10,
6311 		.phy_base_addr = 0x0,
6312 		.global1_addr = 0x1b,
6313 		.global2_addr = 0x1c,
6314 		.age_time_coeff = 15000,
6315 		.g1_irqs = 9,
6316 		.g2_irqs = 10,
6317 		.atu_move_port_mask = 0xf,
6318 		.pvt = true,
6319 		.multi_chip = true,
6320 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6321 		.ops = &mv88e6350_ops,
6322 	},
6323 
6324 	[MV88E6351] = {
6325 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6326 		.family = MV88E6XXX_FAMILY_6351,
6327 		.name = "Marvell 88E6351",
6328 		.num_databases = 4096,
6329 		.num_macs = 8192,
6330 		.num_ports = 7,
6331 		.num_internal_phys = 5,
6332 		.max_vid = 4095,
6333 		.max_sid = 63,
6334 		.port_base_addr = 0x10,
6335 		.phy_base_addr = 0x0,
6336 		.global1_addr = 0x1b,
6337 		.global2_addr = 0x1c,
6338 		.age_time_coeff = 15000,
6339 		.g1_irqs = 9,
6340 		.g2_irqs = 10,
6341 		.atu_move_port_mask = 0xf,
6342 		.pvt = true,
6343 		.multi_chip = true,
6344 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6345 		.ops = &mv88e6351_ops,
6346 	},
6347 
6348 	[MV88E6352] = {
6349 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6350 		.family = MV88E6XXX_FAMILY_6352,
6351 		.name = "Marvell 88E6352",
6352 		.num_databases = 4096,
6353 		.num_macs = 8192,
6354 		.num_ports = 7,
6355 		.num_internal_phys = 5,
6356 		.num_gpio = 15,
6357 		.max_vid = 4095,
6358 		.max_sid = 63,
6359 		.port_base_addr = 0x10,
6360 		.phy_base_addr = 0x0,
6361 		.global1_addr = 0x1b,
6362 		.global2_addr = 0x1c,
6363 		.age_time_coeff = 15000,
6364 		.g1_irqs = 9,
6365 		.g2_irqs = 10,
6366 		.atu_move_port_mask = 0xf,
6367 		.pvt = true,
6368 		.multi_chip = true,
6369 		.edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6370 		.ptp_support = true,
6371 		.ops = &mv88e6352_ops,
6372 	},
6373 	[MV88E6361] = {
6374 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6375 		.family = MV88E6XXX_FAMILY_6393,
6376 		.name = "Marvell 88E6361",
6377 		.num_databases = 4096,
6378 		.num_macs = 16384,
6379 		.num_ports = 11,
6380 		/* Ports 1, 2 and 8 are not routed */
6381 		.invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6382 		.num_internal_phys = 5,
6383 		.internal_phys_offset = 3,
6384 		.max_vid = 4095,
6385 		.max_sid = 63,
6386 		.port_base_addr = 0x0,
6387 		.phy_base_addr = 0x0,
6388 		.global1_addr = 0x1b,
6389 		.global2_addr = 0x1c,
6390 		.age_time_coeff = 3750,
6391 		.g1_irqs = 10,
6392 		.g2_irqs = 14,
6393 		.atu_move_port_mask = 0x1f,
6394 		.pvt = true,
6395 		.multi_chip = true,
6396 		.ptp_support = true,
6397 		.ops = &mv88e6393x_ops,
6398 	},
6399 	[MV88E6390] = {
6400 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6401 		.family = MV88E6XXX_FAMILY_6390,
6402 		.name = "Marvell 88E6390",
6403 		.num_databases = 4096,
6404 		.num_macs = 16384,
6405 		.num_ports = 11,	/* 10 + Z80 */
6406 		.num_internal_phys = 9,
6407 		.num_gpio = 16,
6408 		.max_vid = 8191,
6409 		.max_sid = 63,
6410 		.port_base_addr = 0x0,
6411 		.phy_base_addr = 0x0,
6412 		.global1_addr = 0x1b,
6413 		.global2_addr = 0x1c,
6414 		.age_time_coeff = 3750,
6415 		.g1_irqs = 9,
6416 		.g2_irqs = 14,
6417 		.atu_move_port_mask = 0x1f,
6418 		.pvt = true,
6419 		.multi_chip = true,
6420 		.edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6421 		.ptp_support = true,
6422 		.ops = &mv88e6390_ops,
6423 	},
6424 	[MV88E6390X] = {
6425 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6426 		.family = MV88E6XXX_FAMILY_6390,
6427 		.name = "Marvell 88E6390X",
6428 		.num_databases = 4096,
6429 		.num_macs = 16384,
6430 		.num_ports = 11,	/* 10 + Z80 */
6431 		.num_internal_phys = 9,
6432 		.num_gpio = 16,
6433 		.max_vid = 8191,
6434 		.max_sid = 63,
6435 		.port_base_addr = 0x0,
6436 		.phy_base_addr = 0x0,
6437 		.global1_addr = 0x1b,
6438 		.global2_addr = 0x1c,
6439 		.age_time_coeff = 3750,
6440 		.g1_irqs = 9,
6441 		.g2_irqs = 14,
6442 		.atu_move_port_mask = 0x1f,
6443 		.pvt = true,
6444 		.multi_chip = true,
6445 		.edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6446 		.ptp_support = true,
6447 		.ops = &mv88e6390x_ops,
6448 	},
6449 
6450 	[MV88E6393X] = {
6451 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6452 		.family = MV88E6XXX_FAMILY_6393,
6453 		.name = "Marvell 88E6393X",
6454 		.num_databases = 4096,
6455 		.num_ports = 11,	/* 10 + Z80 */
6456 		.num_internal_phys = 8,
6457 		.internal_phys_offset = 1,
6458 		.max_vid = 8191,
6459 		.max_sid = 63,
6460 		.port_base_addr = 0x0,
6461 		.phy_base_addr = 0x0,
6462 		.global1_addr = 0x1b,
6463 		.global2_addr = 0x1c,
6464 		.age_time_coeff = 3750,
6465 		.g1_irqs = 10,
6466 		.g2_irqs = 14,
6467 		.atu_move_port_mask = 0x1f,
6468 		.pvt = true,
6469 		.multi_chip = true,
6470 		.ptp_support = true,
6471 		.ops = &mv88e6393x_ops,
6472 	},
6473 };
6474 
6475 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6476 {
6477 	int i;
6478 
6479 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6480 		if (mv88e6xxx_table[i].prod_num == prod_num)
6481 			return &mv88e6xxx_table[i];
6482 
6483 	return NULL;
6484 }
6485 
6486 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6487 {
6488 	const struct mv88e6xxx_info *info;
6489 	unsigned int prod_num, rev;
6490 	u16 id;
6491 	int err;
6492 
6493 	mv88e6xxx_reg_lock(chip);
6494 	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6495 	mv88e6xxx_reg_unlock(chip);
6496 	if (err)
6497 		return err;
6498 
6499 	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6500 	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6501 
6502 	info = mv88e6xxx_lookup_info(prod_num);
6503 	if (!info)
6504 		return -ENODEV;
6505 
6506 	/* Update the compatible info with the probed one */
6507 	chip->info = info;
6508 
6509 	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6510 		 chip->info->prod_num, chip->info->name, rev);
6511 
6512 	return 0;
6513 }
6514 
6515 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6516 					struct mdio_device *mdiodev)
6517 {
6518 	int err;
6519 
6520 	/* dual_chip takes precedence over single/multi-chip modes */
6521 	if (chip->info->dual_chip)
6522 		return -EINVAL;
6523 
6524 	/* If the mdio addr is 16 indicating the first port address of a switch
6525 	 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6526 	 * configured in single chip addressing mode. Setup the smi access as
6527 	 * single chip addressing mode and attempt to detect the model of the
6528 	 * switch, if this fails the device is not configured in single chip
6529 	 * addressing mode.
6530 	 */
6531 	if (mdiodev->addr != 16)
6532 		return -EINVAL;
6533 
6534 	err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6535 	if (err)
6536 		return err;
6537 
6538 	return mv88e6xxx_detect(chip);
6539 }
6540 
6541 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6542 {
6543 	struct mv88e6xxx_chip *chip;
6544 
6545 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6546 	if (!chip)
6547 		return NULL;
6548 
6549 	chip->dev = dev;
6550 
6551 	mutex_init(&chip->reg_lock);
6552 	INIT_LIST_HEAD(&chip->mdios);
6553 	idr_init(&chip->policies);
6554 	INIT_LIST_HEAD(&chip->msts);
6555 
6556 	return chip;
6557 }
6558 
6559 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6560 							int port,
6561 							enum dsa_tag_protocol m)
6562 {
6563 	struct mv88e6xxx_chip *chip = ds->priv;
6564 
6565 	return chip->tag_protocol;
6566 }
6567 
6568 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6569 					 enum dsa_tag_protocol proto)
6570 {
6571 	struct mv88e6xxx_chip *chip = ds->priv;
6572 	enum dsa_tag_protocol old_protocol;
6573 	struct dsa_port *cpu_dp;
6574 	int err;
6575 
6576 	switch (proto) {
6577 	case DSA_TAG_PROTO_EDSA:
6578 		switch (chip->info->edsa_support) {
6579 		case MV88E6XXX_EDSA_UNSUPPORTED:
6580 			return -EPROTONOSUPPORT;
6581 		case MV88E6XXX_EDSA_UNDOCUMENTED:
6582 			dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6583 			fallthrough;
6584 		case MV88E6XXX_EDSA_SUPPORTED:
6585 			break;
6586 		}
6587 		break;
6588 	case DSA_TAG_PROTO_DSA:
6589 		break;
6590 	default:
6591 		return -EPROTONOSUPPORT;
6592 	}
6593 
6594 	old_protocol = chip->tag_protocol;
6595 	chip->tag_protocol = proto;
6596 
6597 	mv88e6xxx_reg_lock(chip);
6598 	dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6599 		err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6600 		if (err) {
6601 			mv88e6xxx_reg_unlock(chip);
6602 			goto unwind;
6603 		}
6604 	}
6605 	mv88e6xxx_reg_unlock(chip);
6606 
6607 	return 0;
6608 
6609 unwind:
6610 	chip->tag_protocol = old_protocol;
6611 
6612 	mv88e6xxx_reg_lock(chip);
6613 	dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6614 		mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6615 	mv88e6xxx_reg_unlock(chip);
6616 
6617 	return err;
6618 }
6619 
6620 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6621 				  const struct switchdev_obj_port_mdb *mdb,
6622 				  struct dsa_db db)
6623 {
6624 	struct mv88e6xxx_chip *chip = ds->priv;
6625 	int err;
6626 
6627 	mv88e6xxx_reg_lock(chip);
6628 	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6629 					   MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6630 	mv88e6xxx_reg_unlock(chip);
6631 
6632 	return err;
6633 }
6634 
6635 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6636 				  const struct switchdev_obj_port_mdb *mdb,
6637 				  struct dsa_db db)
6638 {
6639 	struct mv88e6xxx_chip *chip = ds->priv;
6640 	int err;
6641 
6642 	mv88e6xxx_reg_lock(chip);
6643 	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6644 	mv88e6xxx_reg_unlock(chip);
6645 
6646 	return err;
6647 }
6648 
6649 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6650 				     struct dsa_mall_mirror_tc_entry *mirror,
6651 				     bool ingress,
6652 				     struct netlink_ext_ack *extack)
6653 {
6654 	enum mv88e6xxx_egress_direction direction = ingress ?
6655 						MV88E6XXX_EGRESS_DIR_INGRESS :
6656 						MV88E6XXX_EGRESS_DIR_EGRESS;
6657 	struct mv88e6xxx_chip *chip = ds->priv;
6658 	bool other_mirrors = false;
6659 	int i;
6660 	int err;
6661 
6662 	mutex_lock(&chip->reg_lock);
6663 	if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6664 	    mirror->to_local_port) {
6665 		for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6666 			other_mirrors |= ingress ?
6667 					 chip->ports[i].mirror_ingress :
6668 					 chip->ports[i].mirror_egress;
6669 
6670 		/* Can't change egress port when other mirror is active */
6671 		if (other_mirrors) {
6672 			err = -EBUSY;
6673 			goto out;
6674 		}
6675 
6676 		err = mv88e6xxx_set_egress_port(chip, direction,
6677 						mirror->to_local_port);
6678 		if (err)
6679 			goto out;
6680 	}
6681 
6682 	err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6683 out:
6684 	mutex_unlock(&chip->reg_lock);
6685 
6686 	return err;
6687 }
6688 
6689 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6690 				      struct dsa_mall_mirror_tc_entry *mirror)
6691 {
6692 	enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6693 						MV88E6XXX_EGRESS_DIR_INGRESS :
6694 						MV88E6XXX_EGRESS_DIR_EGRESS;
6695 	struct mv88e6xxx_chip *chip = ds->priv;
6696 	bool other_mirrors = false;
6697 	int i;
6698 
6699 	mutex_lock(&chip->reg_lock);
6700 	if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6701 		dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6702 
6703 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6704 		other_mirrors |= mirror->ingress ?
6705 				 chip->ports[i].mirror_ingress :
6706 				 chip->ports[i].mirror_egress;
6707 
6708 	/* Reset egress port when no other mirror is active */
6709 	if (!other_mirrors) {
6710 		if (mv88e6xxx_set_egress_port(chip, direction,
6711 					      dsa_upstream_port(ds, port)))
6712 			dev_err(ds->dev, "failed to set egress port\n");
6713 	}
6714 
6715 	mutex_unlock(&chip->reg_lock);
6716 }
6717 
6718 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6719 					   struct switchdev_brport_flags flags,
6720 					   struct netlink_ext_ack *extack)
6721 {
6722 	struct mv88e6xxx_chip *chip = ds->priv;
6723 	const struct mv88e6xxx_ops *ops;
6724 
6725 	if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6726 			   BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6727 		return -EINVAL;
6728 
6729 	ops = chip->info->ops;
6730 
6731 	if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6732 		return -EINVAL;
6733 
6734 	if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6735 		return -EINVAL;
6736 
6737 	return 0;
6738 }
6739 
6740 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6741 				       struct switchdev_brport_flags flags,
6742 				       struct netlink_ext_ack *extack)
6743 {
6744 	struct mv88e6xxx_chip *chip = ds->priv;
6745 	int err = 0;
6746 
6747 	mv88e6xxx_reg_lock(chip);
6748 
6749 	if (flags.mask & BR_LEARNING) {
6750 		bool learning = !!(flags.val & BR_LEARNING);
6751 		u16 pav = learning ? (1 << port) : 0;
6752 
6753 		err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6754 		if (err)
6755 			goto out;
6756 	}
6757 
6758 	if (flags.mask & BR_FLOOD) {
6759 		bool unicast = !!(flags.val & BR_FLOOD);
6760 
6761 		err = chip->info->ops->port_set_ucast_flood(chip, port,
6762 							    unicast);
6763 		if (err)
6764 			goto out;
6765 	}
6766 
6767 	if (flags.mask & BR_MCAST_FLOOD) {
6768 		bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6769 
6770 		err = chip->info->ops->port_set_mcast_flood(chip, port,
6771 							    multicast);
6772 		if (err)
6773 			goto out;
6774 	}
6775 
6776 	if (flags.mask & BR_BCAST_FLOOD) {
6777 		bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6778 
6779 		err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6780 		if (err)
6781 			goto out;
6782 	}
6783 
6784 	if (flags.mask & BR_PORT_MAB) {
6785 		bool mab = !!(flags.val & BR_PORT_MAB);
6786 
6787 		mv88e6xxx_port_set_mab(chip, port, mab);
6788 	}
6789 
6790 	if (flags.mask & BR_PORT_LOCKED) {
6791 		bool locked = !!(flags.val & BR_PORT_LOCKED);
6792 
6793 		err = mv88e6xxx_port_set_lock(chip, port, locked);
6794 		if (err)
6795 			goto out;
6796 	}
6797 out:
6798 	mv88e6xxx_reg_unlock(chip);
6799 
6800 	return err;
6801 }
6802 
6803 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6804 				      struct dsa_lag lag,
6805 				      struct netdev_lag_upper_info *info,
6806 				      struct netlink_ext_ack *extack)
6807 {
6808 	struct mv88e6xxx_chip *chip = ds->priv;
6809 	struct dsa_port *dp;
6810 	int members = 0;
6811 
6812 	if (!mv88e6xxx_has_lag(chip)) {
6813 		NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6814 		return false;
6815 	}
6816 
6817 	if (!lag.id)
6818 		return false;
6819 
6820 	dsa_lag_foreach_port(dp, ds->dst, &lag)
6821 		/* Includes the port joining the LAG */
6822 		members++;
6823 
6824 	if (members > 8) {
6825 		NL_SET_ERR_MSG_MOD(extack,
6826 				   "Cannot offload more than 8 LAG ports");
6827 		return false;
6828 	}
6829 
6830 	/* We could potentially relax this to include active
6831 	 * backup in the future.
6832 	 */
6833 	if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6834 		NL_SET_ERR_MSG_MOD(extack,
6835 				   "Can only offload LAG using hash TX type");
6836 		return false;
6837 	}
6838 
6839 	/* Ideally we would also validate that the hash type matches
6840 	 * the hardware. Alas, this is always set to unknown on team
6841 	 * interfaces.
6842 	 */
6843 	return true;
6844 }
6845 
6846 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6847 {
6848 	struct mv88e6xxx_chip *chip = ds->priv;
6849 	struct dsa_port *dp;
6850 	u16 map = 0;
6851 	int id;
6852 
6853 	/* DSA LAG IDs are one-based, hardware is zero-based */
6854 	id = lag.id - 1;
6855 
6856 	/* Build the map of all ports to distribute flows destined for
6857 	 * this LAG. This can be either a local user port, or a DSA
6858 	 * port if the LAG port is on a remote chip.
6859 	 */
6860 	dsa_lag_foreach_port(dp, ds->dst, &lag)
6861 		map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6862 
6863 	return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6864 }
6865 
6866 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6867 	/* Row number corresponds to the number of active members in a
6868 	 * LAG. Each column states which of the eight hash buckets are
6869 	 * mapped to the column:th port in the LAG.
6870 	 *
6871 	 * Example: In a LAG with three active ports, the second port
6872 	 * ([2][1]) would be selected for traffic mapped to buckets
6873 	 * 3,4,5 (0x38).
6874 	 */
6875 	{ 0xff,    0,    0,    0,    0,    0,    0,    0 },
6876 	{ 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6877 	{ 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6878 	{ 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6879 	{ 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6880 	{ 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6881 	{ 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6882 	{ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6883 };
6884 
6885 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6886 					int num_tx, int nth)
6887 {
6888 	u8 active = 0;
6889 	int i;
6890 
6891 	num_tx = num_tx <= 8 ? num_tx : 8;
6892 	if (nth < num_tx)
6893 		active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6894 
6895 	for (i = 0; i < 8; i++) {
6896 		if (BIT(i) & active)
6897 			mask[i] |= BIT(port);
6898 	}
6899 }
6900 
6901 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6902 {
6903 	struct mv88e6xxx_chip *chip = ds->priv;
6904 	unsigned int id, num_tx;
6905 	struct dsa_port *dp;
6906 	struct dsa_lag *lag;
6907 	int i, err, nth;
6908 	u16 mask[8];
6909 	u16 ivec;
6910 
6911 	/* Assume no port is a member of any LAG. */
6912 	ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6913 
6914 	/* Disable all masks for ports that _are_ members of a LAG. */
6915 	dsa_switch_for_each_port(dp, ds) {
6916 		if (!dp->lag)
6917 			continue;
6918 
6919 		ivec &= ~BIT(dp->index);
6920 	}
6921 
6922 	for (i = 0; i < 8; i++)
6923 		mask[i] = ivec;
6924 
6925 	/* Enable the correct subset of masks for all LAG ports that
6926 	 * are in the Tx set.
6927 	 */
6928 	dsa_lags_foreach_id(id, ds->dst) {
6929 		lag = dsa_lag_by_id(ds->dst, id);
6930 		if (!lag)
6931 			continue;
6932 
6933 		num_tx = 0;
6934 		dsa_lag_foreach_port(dp, ds->dst, lag) {
6935 			if (dp->lag_tx_enabled)
6936 				num_tx++;
6937 		}
6938 
6939 		if (!num_tx)
6940 			continue;
6941 
6942 		nth = 0;
6943 		dsa_lag_foreach_port(dp, ds->dst, lag) {
6944 			if (!dp->lag_tx_enabled)
6945 				continue;
6946 
6947 			if (dp->ds == ds)
6948 				mv88e6xxx_lag_set_port_mask(mask, dp->index,
6949 							    num_tx, nth);
6950 
6951 			nth++;
6952 		}
6953 	}
6954 
6955 	for (i = 0; i < 8; i++) {
6956 		err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6957 		if (err)
6958 			return err;
6959 	}
6960 
6961 	return 0;
6962 }
6963 
6964 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6965 					struct dsa_lag lag)
6966 {
6967 	int err;
6968 
6969 	err = mv88e6xxx_lag_sync_masks(ds);
6970 
6971 	if (!err)
6972 		err = mv88e6xxx_lag_sync_map(ds, lag);
6973 
6974 	return err;
6975 }
6976 
6977 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6978 {
6979 	struct mv88e6xxx_chip *chip = ds->priv;
6980 	int err;
6981 
6982 	mv88e6xxx_reg_lock(chip);
6983 	err = mv88e6xxx_lag_sync_masks(ds);
6984 	mv88e6xxx_reg_unlock(chip);
6985 	return err;
6986 }
6987 
6988 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6989 				   struct dsa_lag lag,
6990 				   struct netdev_lag_upper_info *info,
6991 				   struct netlink_ext_ack *extack)
6992 {
6993 	struct mv88e6xxx_chip *chip = ds->priv;
6994 	int err, id;
6995 
6996 	if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6997 		return -EOPNOTSUPP;
6998 
6999 	/* DSA LAG IDs are one-based */
7000 	id = lag.id - 1;
7001 
7002 	mv88e6xxx_reg_lock(chip);
7003 
7004 	err = mv88e6xxx_port_set_trunk(chip, port, true, id);
7005 	if (err)
7006 		goto err_unlock;
7007 
7008 	err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7009 	if (err)
7010 		goto err_clear_trunk;
7011 
7012 	mv88e6xxx_reg_unlock(chip);
7013 	return 0;
7014 
7015 err_clear_trunk:
7016 	mv88e6xxx_port_set_trunk(chip, port, false, 0);
7017 err_unlock:
7018 	mv88e6xxx_reg_unlock(chip);
7019 	return err;
7020 }
7021 
7022 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
7023 				    struct dsa_lag lag)
7024 {
7025 	struct mv88e6xxx_chip *chip = ds->priv;
7026 	int err_sync, err_trunk;
7027 
7028 	mv88e6xxx_reg_lock(chip);
7029 	err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7030 	err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7031 	mv88e6xxx_reg_unlock(chip);
7032 	return err_sync ? : err_trunk;
7033 }
7034 
7035 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
7036 					  int port)
7037 {
7038 	struct mv88e6xxx_chip *chip = ds->priv;
7039 	int err;
7040 
7041 	mv88e6xxx_reg_lock(chip);
7042 	err = mv88e6xxx_lag_sync_masks(ds);
7043 	mv88e6xxx_reg_unlock(chip);
7044 	return err;
7045 }
7046 
7047 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
7048 					int port, struct dsa_lag lag,
7049 					struct netdev_lag_upper_info *info,
7050 					struct netlink_ext_ack *extack)
7051 {
7052 	struct mv88e6xxx_chip *chip = ds->priv;
7053 	int err;
7054 
7055 	if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7056 		return -EOPNOTSUPP;
7057 
7058 	mv88e6xxx_reg_lock(chip);
7059 
7060 	err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7061 	if (err)
7062 		goto unlock;
7063 
7064 	err = mv88e6xxx_pvt_map(chip, sw_index, port);
7065 
7066 unlock:
7067 	mv88e6xxx_reg_unlock(chip);
7068 	return err;
7069 }
7070 
7071 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
7072 					 int port, struct dsa_lag lag)
7073 {
7074 	struct mv88e6xxx_chip *chip = ds->priv;
7075 	int err_sync, err_pvt;
7076 
7077 	mv88e6xxx_reg_lock(chip);
7078 	err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7079 	err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7080 	mv88e6xxx_reg_unlock(chip);
7081 	return err_sync ? : err_pvt;
7082 }
7083 
7084 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = {
7085 	.mac_select_pcs		= mv88e6xxx_mac_select_pcs,
7086 	.mac_prepare		= mv88e6xxx_mac_prepare,
7087 	.mac_config		= mv88e6xxx_mac_config,
7088 	.mac_finish		= mv88e6xxx_mac_finish,
7089 	.mac_link_down		= mv88e6xxx_mac_link_down,
7090 	.mac_link_up		= mv88e6xxx_mac_link_up,
7091 };
7092 
7093 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7094 	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
7095 	.change_tag_protocol	= mv88e6xxx_change_tag_protocol,
7096 	.setup			= mv88e6xxx_setup,
7097 	.teardown		= mv88e6xxx_teardown,
7098 	.port_setup		= mv88e6xxx_port_setup,
7099 	.port_teardown		= mv88e6xxx_port_teardown,
7100 	.phylink_get_caps	= mv88e6xxx_get_caps,
7101 	.get_strings		= mv88e6xxx_get_strings,
7102 	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
7103 	.get_eth_mac_stats	= mv88e6xxx_get_eth_mac_stats,
7104 	.get_rmon_stats		= mv88e6xxx_get_rmon_stats,
7105 	.get_sset_count		= mv88e6xxx_get_sset_count,
7106 	.port_max_mtu		= mv88e6xxx_get_max_mtu,
7107 	.port_change_mtu	= mv88e6xxx_change_mtu,
7108 	.get_mac_eee		= mv88e6xxx_get_mac_eee,
7109 	.set_mac_eee		= mv88e6xxx_set_mac_eee,
7110 	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
7111 	.get_eeprom		= mv88e6xxx_get_eeprom,
7112 	.set_eeprom		= mv88e6xxx_set_eeprom,
7113 	.get_regs_len		= mv88e6xxx_get_regs_len,
7114 	.get_regs		= mv88e6xxx_get_regs,
7115 	.get_rxnfc		= mv88e6xxx_get_rxnfc,
7116 	.set_rxnfc		= mv88e6xxx_set_rxnfc,
7117 	.set_ageing_time	= mv88e6xxx_set_ageing_time,
7118 	.port_bridge_join	= mv88e6xxx_port_bridge_join,
7119 	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
7120 	.port_pre_bridge_flags	= mv88e6xxx_port_pre_bridge_flags,
7121 	.port_bridge_flags	= mv88e6xxx_port_bridge_flags,
7122 	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
7123 	.port_mst_state_set	= mv88e6xxx_port_mst_state_set,
7124 	.port_fast_age		= mv88e6xxx_port_fast_age,
7125 	.port_vlan_fast_age	= mv88e6xxx_port_vlan_fast_age,
7126 	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
7127 	.port_vlan_add		= mv88e6xxx_port_vlan_add,
7128 	.port_vlan_del		= mv88e6xxx_port_vlan_del,
7129 	.vlan_msti_set		= mv88e6xxx_vlan_msti_set,
7130 	.port_fdb_add		= mv88e6xxx_port_fdb_add,
7131 	.port_fdb_del		= mv88e6xxx_port_fdb_del,
7132 	.port_fdb_dump		= mv88e6xxx_port_fdb_dump,
7133 	.port_mdb_add		= mv88e6xxx_port_mdb_add,
7134 	.port_mdb_del		= mv88e6xxx_port_mdb_del,
7135 	.port_mirror_add	= mv88e6xxx_port_mirror_add,
7136 	.port_mirror_del	= mv88e6xxx_port_mirror_del,
7137 	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
7138 	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
7139 	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
7140 	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
7141 	.port_txtstamp		= mv88e6xxx_port_txtstamp,
7142 	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
7143 	.get_ts_info		= mv88e6xxx_get_ts_info,
7144 	.devlink_param_get	= mv88e6xxx_devlink_param_get,
7145 	.devlink_param_set	= mv88e6xxx_devlink_param_set,
7146 	.devlink_info_get	= mv88e6xxx_devlink_info_get,
7147 	.port_lag_change	= mv88e6xxx_port_lag_change,
7148 	.port_lag_join		= mv88e6xxx_port_lag_join,
7149 	.port_lag_leave		= mv88e6xxx_port_lag_leave,
7150 	.crosschip_lag_change	= mv88e6xxx_crosschip_lag_change,
7151 	.crosschip_lag_join	= mv88e6xxx_crosschip_lag_join,
7152 	.crosschip_lag_leave	= mv88e6xxx_crosschip_lag_leave,
7153 };
7154 
7155 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7156 {
7157 	struct device *dev = chip->dev;
7158 	struct dsa_switch *ds;
7159 
7160 	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7161 	if (!ds)
7162 		return -ENOMEM;
7163 
7164 	ds->dev = dev;
7165 	ds->num_ports = mv88e6xxx_num_ports(chip);
7166 	ds->priv = chip;
7167 	ds->dev = dev;
7168 	ds->ops = &mv88e6xxx_switch_ops;
7169 	ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops;
7170 	ds->ageing_time_min = chip->info->age_time_coeff;
7171 	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7172 
7173 	/* Some chips support up to 32, but that requires enabling the
7174 	 * 5-bit port mode, which we do not support. 640k^W16 ought to
7175 	 * be enough for anyone.
7176 	 */
7177 	ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7178 
7179 	dev_set_drvdata(dev, ds);
7180 
7181 	return dsa_register_switch(ds);
7182 }
7183 
7184 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7185 {
7186 	dsa_unregister_switch(chip->ds);
7187 }
7188 
7189 static const void *pdata_device_get_match_data(struct device *dev)
7190 {
7191 	const struct of_device_id *matches = dev->driver->of_match_table;
7192 	const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7193 
7194 	for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7195 	     matches++) {
7196 		if (!strcmp(pdata->compatible, matches->compatible))
7197 			return matches->data;
7198 	}
7199 	return NULL;
7200 }
7201 
7202 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7203  * would be lost after a power cycle so prevent it to be suspended.
7204  */
7205 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7206 {
7207 	return -EOPNOTSUPP;
7208 }
7209 
7210 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7211 {
7212 	return 0;
7213 }
7214 
7215 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7216 
7217 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7218 {
7219 	struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7220 	const struct mv88e6xxx_info *compat_info = NULL;
7221 	struct device *dev = &mdiodev->dev;
7222 	struct device_node *np = dev->of_node;
7223 	struct mv88e6xxx_chip *chip;
7224 	int port;
7225 	int err;
7226 
7227 	if (!np && !pdata)
7228 		return -EINVAL;
7229 
7230 	if (np)
7231 		compat_info = of_device_get_match_data(dev);
7232 
7233 	if (pdata) {
7234 		compat_info = pdata_device_get_match_data(dev);
7235 
7236 		if (!pdata->netdev)
7237 			return -EINVAL;
7238 
7239 		for (port = 0; port < DSA_MAX_PORTS; port++) {
7240 			if (!(pdata->enabled_ports & (1 << port)))
7241 				continue;
7242 			if (strcmp(pdata->cd.port_names[port], "cpu"))
7243 				continue;
7244 			pdata->cd.netdev[port] = &pdata->netdev->dev;
7245 			break;
7246 		}
7247 	}
7248 
7249 	if (!compat_info)
7250 		return -EINVAL;
7251 
7252 	chip = mv88e6xxx_alloc_chip(dev);
7253 	if (!chip) {
7254 		err = -ENOMEM;
7255 		goto out;
7256 	}
7257 
7258 	chip->info = compat_info;
7259 
7260 	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7261 	if (IS_ERR(chip->reset)) {
7262 		err = PTR_ERR(chip->reset);
7263 		goto out;
7264 	}
7265 	if (chip->reset)
7266 		usleep_range(10000, 20000);
7267 
7268 	/* Detect if the device is configured in single chip addressing mode,
7269 	 * otherwise continue with address specific smi init/detection.
7270 	 */
7271 	err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7272 	if (err) {
7273 		err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7274 		if (err)
7275 			goto out;
7276 
7277 		err = mv88e6xxx_detect(chip);
7278 		if (err)
7279 			goto out;
7280 	}
7281 
7282 	if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7283 		chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7284 	else
7285 		chip->tag_protocol = DSA_TAG_PROTO_DSA;
7286 
7287 	mv88e6xxx_phy_init(chip);
7288 
7289 	if (chip->info->ops->get_eeprom) {
7290 		if (np)
7291 			of_property_read_u32(np, "eeprom-length",
7292 					     &chip->eeprom_len);
7293 		else
7294 			chip->eeprom_len = pdata->eeprom_len;
7295 	}
7296 
7297 	mv88e6xxx_reg_lock(chip);
7298 	err = mv88e6xxx_switch_reset(chip);
7299 	mv88e6xxx_reg_unlock(chip);
7300 	if (err)
7301 		goto out;
7302 
7303 	if (np) {
7304 		chip->irq = of_irq_get(np, 0);
7305 		if (chip->irq == -EPROBE_DEFER) {
7306 			err = chip->irq;
7307 			goto out;
7308 		}
7309 	}
7310 
7311 	if (pdata)
7312 		chip->irq = pdata->irq;
7313 
7314 	/* Has to be performed before the MDIO bus is created, because
7315 	 * the PHYs will link their interrupts to these interrupt
7316 	 * controllers
7317 	 */
7318 	mv88e6xxx_reg_lock(chip);
7319 	if (chip->irq > 0)
7320 		err = mv88e6xxx_g1_irq_setup(chip);
7321 	else
7322 		err = mv88e6xxx_irq_poll_setup(chip);
7323 	mv88e6xxx_reg_unlock(chip);
7324 
7325 	if (err)
7326 		goto out;
7327 
7328 	if (chip->info->g2_irqs > 0) {
7329 		err = mv88e6xxx_g2_irq_setup(chip);
7330 		if (err)
7331 			goto out_g1_irq;
7332 	}
7333 
7334 	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7335 	if (err)
7336 		goto out_g2_irq;
7337 
7338 	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7339 	if (err)
7340 		goto out_g1_atu_prob_irq;
7341 
7342 	err = mv88e6xxx_register_switch(chip);
7343 	if (err)
7344 		goto out_g1_vtu_prob_irq;
7345 
7346 	return 0;
7347 
7348 out_g1_vtu_prob_irq:
7349 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
7350 out_g1_atu_prob_irq:
7351 	mv88e6xxx_g1_atu_prob_irq_free(chip);
7352 out_g2_irq:
7353 	if (chip->info->g2_irqs > 0)
7354 		mv88e6xxx_g2_irq_free(chip);
7355 out_g1_irq:
7356 	if (chip->irq > 0)
7357 		mv88e6xxx_g1_irq_free(chip);
7358 	else
7359 		mv88e6xxx_irq_poll_free(chip);
7360 out:
7361 	if (pdata)
7362 		dev_put(pdata->netdev);
7363 
7364 	return err;
7365 }
7366 
7367 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7368 {
7369 	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7370 	struct mv88e6xxx_chip *chip;
7371 
7372 	if (!ds)
7373 		return;
7374 
7375 	chip = ds->priv;
7376 
7377 	if (chip->info->ptp_support) {
7378 		mv88e6xxx_hwtstamp_free(chip);
7379 		mv88e6xxx_ptp_free(chip);
7380 	}
7381 
7382 	mv88e6xxx_phy_destroy(chip);
7383 	mv88e6xxx_unregister_switch(chip);
7384 
7385 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
7386 	mv88e6xxx_g1_atu_prob_irq_free(chip);
7387 
7388 	if (chip->info->g2_irqs > 0)
7389 		mv88e6xxx_g2_irq_free(chip);
7390 
7391 	if (chip->irq > 0)
7392 		mv88e6xxx_g1_irq_free(chip);
7393 	else
7394 		mv88e6xxx_irq_poll_free(chip);
7395 }
7396 
7397 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7398 {
7399 	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7400 
7401 	if (!ds)
7402 		return;
7403 
7404 	dsa_switch_shutdown(ds);
7405 
7406 	dev_set_drvdata(&mdiodev->dev, NULL);
7407 }
7408 
7409 static const struct of_device_id mv88e6xxx_of_match[] = {
7410 	{
7411 		.compatible = "marvell,mv88e6085",
7412 		.data = &mv88e6xxx_table[MV88E6085],
7413 	},
7414 	{
7415 		.compatible = "marvell,mv88e6190",
7416 		.data = &mv88e6xxx_table[MV88E6190],
7417 	},
7418 	{
7419 		.compatible = "marvell,mv88e6250",
7420 		.data = &mv88e6xxx_table[MV88E6250],
7421 	},
7422 	{ /* sentinel */ },
7423 };
7424 
7425 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7426 
7427 static struct mdio_driver mv88e6xxx_driver = {
7428 	.probe	= mv88e6xxx_probe,
7429 	.remove = mv88e6xxx_remove,
7430 	.shutdown = mv88e6xxx_shutdown,
7431 	.mdiodrv.driver = {
7432 		.name = "mv88e6085",
7433 		.of_match_table = mv88e6xxx_of_match,
7434 		.pm = &mv88e6xxx_pm_ops,
7435 	},
7436 };
7437 
7438 mdio_module_driver(mv88e6xxx_driver);
7439 
7440 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7441 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7442 MODULE_LICENSE("GPL");
7443