1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 u8 lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 u8 lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 u8 lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 u8 lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 639 unsigned long *supported, 640 struct phylink_link_state *state) 641 { 642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 643 struct mv88e6xxx_chip *chip = ds->priv; 644 645 /* Allow all the expected bits */ 646 phylink_set(mask, Autoneg); 647 phylink_set(mask, Pause); 648 phylink_set_port_modes(mask); 649 650 if (chip->info->ops->phylink_validate) 651 chip->info->ops->phylink_validate(chip, port, mask, state); 652 653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 654 bitmap_and(state->advertising, state->advertising, mask, 655 __ETHTOOL_LINK_MODE_MASK_NBITS); 656 657 /* We can only operate at 2500BaseX or 1000BaseX. If requested 658 * to advertise both, only report advertising at 2500BaseX. 659 */ 660 phylink_helper_basex_speed(state); 661 } 662 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 664 unsigned int mode, 665 const struct phylink_link_state *state) 666 { 667 struct mv88e6xxx_chip *chip = ds->priv; 668 struct mv88e6xxx_port *p; 669 int err; 670 671 p = &chip->ports[port]; 672 673 /* FIXME: is this the correct test? If we're in fixed mode on an 674 * internal port, why should we process this any different from 675 * PHY mode? On the other hand, the port may be automedia between 676 * an internal PHY and the serdes... 677 */ 678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 679 return; 680 681 mv88e6xxx_reg_lock(chip); 682 /* In inband mode, the link may come up at any time while the link 683 * is not forced down. Force the link down while we reconfigure the 684 * interface mode. 685 */ 686 if (mode == MLO_AN_INBAND && p->interface != state->interface && 687 chip->info->ops->port_set_link) 688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 689 690 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 691 if (err && err != -EOPNOTSUPP) 692 goto err_unlock; 693 694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 695 state->advertising); 696 /* FIXME: we should restart negotiation if something changed - which 697 * is something we get if we convert to using phylinks PCS operations. 698 */ 699 if (err > 0) 700 err = 0; 701 702 /* Undo the forced down state above after completing configuration 703 * irrespective of its state on entry, which allows the link to come up. 704 */ 705 if (mode == MLO_AN_INBAND && p->interface != state->interface && 706 chip->info->ops->port_set_link) 707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 708 709 p->interface = state->interface; 710 711 err_unlock: 712 mv88e6xxx_reg_unlock(chip); 713 714 if (err && err != -EOPNOTSUPP) 715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 716 } 717 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface) 721 { 722 struct mv88e6xxx_chip *chip = ds->priv; 723 const struct mv88e6xxx_ops *ops; 724 int err = 0; 725 726 ops = chip->info->ops; 727 728 mv88e6xxx_reg_lock(chip); 729 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 730 mode == MLO_AN_FIXED) && ops->port_set_link) 731 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 732 mv88e6xxx_reg_unlock(chip); 733 734 if (err) 735 dev_err(chip->dev, 736 "p%d: failed to force MAC link down\n", port); 737 } 738 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 740 unsigned int mode, phy_interface_t interface, 741 struct phy_device *phydev, 742 int speed, int duplex, 743 bool tx_pause, bool rx_pause) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 753 /* FIXME: for an automedia port, should we force the link 754 * down here - what if the link comes up due to "other" media 755 * while we're bringing the port up, how is the exclusivity 756 * handled in the Marvell hardware? E.g. port 2 on 88E6390 757 * shared between internal PHY and Serdes. 758 */ 759 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 760 duplex); 761 if (err) 762 goto error; 763 764 if (ops->port_set_speed_duplex) { 765 err = ops->port_set_speed_duplex(chip, port, 766 speed, duplex); 767 if (err && err != -EOPNOTSUPP) 768 goto error; 769 } 770 771 if (ops->port_set_link) 772 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 773 } 774 error: 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err && err != -EOPNOTSUPP) 778 dev_err(ds->dev, 779 "p%d: failed to configure MAC link up\n", port); 780 } 781 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 783 { 784 if (!chip->info->ops->stats_snapshot) 785 return -EOPNOTSUPP; 786 787 return chip->info->ops->stats_snapshot(chip, port); 788 } 789 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 791 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 792 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 793 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 794 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 795 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 796 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 797 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 798 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 799 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 800 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 801 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 802 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 803 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 804 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 805 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 806 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 807 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 808 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 809 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 810 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 811 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 812 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 813 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 814 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 815 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 816 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 817 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 818 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 819 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 820 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 821 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 822 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 823 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 824 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 825 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 826 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 827 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 828 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 829 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 830 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 831 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 832 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 833 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 834 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 835 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 836 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 837 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 838 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 839 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 840 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 841 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 842 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 843 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 844 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 845 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 846 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 847 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 848 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 849 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 850 }; 851 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 853 struct mv88e6xxx_hw_stat *s, 854 int port, u16 bank1_select, 855 u16 histogram) 856 { 857 u32 low; 858 u32 high = 0; 859 u16 reg = 0; 860 int err; 861 u64 value; 862 863 switch (s->type) { 864 case STATS_TYPE_PORT: 865 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 866 if (err) 867 return U64_MAX; 868 869 low = reg; 870 if (s->size == 4) { 871 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 872 if (err) 873 return U64_MAX; 874 low |= ((u32)reg) << 16; 875 } 876 break; 877 case STATS_TYPE_BANK1: 878 reg = bank1_select; 879 fallthrough; 880 case STATS_TYPE_BANK0: 881 reg |= s->reg | histogram; 882 mv88e6xxx_g1_stats_read(chip, reg, &low); 883 if (s->size == 8) 884 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 885 break; 886 default: 887 return U64_MAX; 888 } 889 value = (((u64)high) << 32) | low; 890 return value; 891 } 892 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data, int types) 895 { 896 struct mv88e6xxx_hw_stat *stat; 897 int i, j; 898 899 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 900 stat = &mv88e6xxx_hw_stats[i]; 901 if (stat->type & types) { 902 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 903 ETH_GSTRING_LEN); 904 j++; 905 } 906 } 907 908 return j; 909 } 910 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 912 uint8_t *data) 913 { 914 return mv88e6xxx_stats_get_strings(chip, data, 915 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 916 } 917 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 919 uint8_t *data) 920 { 921 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 922 } 923 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 925 uint8_t *data) 926 { 927 return mv88e6xxx_stats_get_strings(chip, data, 928 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 929 } 930 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 932 "atu_member_violation", 933 "atu_miss_violation", 934 "atu_full_violation", 935 "vtu_member_violation", 936 "vtu_miss_violation", 937 }; 938 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 940 { 941 unsigned int i; 942 943 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 944 strlcpy(data + i * ETH_GSTRING_LEN, 945 mv88e6xxx_atu_vtu_stats_strings[i], 946 ETH_GSTRING_LEN); 947 } 948 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 950 u32 stringset, uint8_t *data) 951 { 952 struct mv88e6xxx_chip *chip = ds->priv; 953 int count = 0; 954 955 if (stringset != ETH_SS_STATS) 956 return; 957 958 mv88e6xxx_reg_lock(chip); 959 960 if (chip->info->ops->stats_get_strings) 961 count = chip->info->ops->stats_get_strings(chip, data); 962 963 if (chip->info->ops->serdes_get_strings) { 964 data += count * ETH_GSTRING_LEN; 965 count = chip->info->ops->serdes_get_strings(chip, port, data); 966 } 967 968 data += count * ETH_GSTRING_LEN; 969 mv88e6xxx_atu_vtu_get_strings(data); 970 971 mv88e6xxx_reg_unlock(chip); 972 } 973 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 975 int types) 976 { 977 struct mv88e6xxx_hw_stat *stat; 978 int i, j; 979 980 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 981 stat = &mv88e6xxx_hw_stats[i]; 982 if (stat->type & types) 983 j++; 984 } 985 return j; 986 } 987 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 989 { 990 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 991 STATS_TYPE_PORT); 992 } 993 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 995 { 996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 997 } 998 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1000 { 1001 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1002 STATS_TYPE_BANK1); 1003 } 1004 1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int serdes_count = 0; 1009 int count = 0; 1010 1011 if (sset != ETH_SS_STATS) 1012 return 0; 1013 1014 mv88e6xxx_reg_lock(chip); 1015 if (chip->info->ops->stats_get_sset_count) 1016 count = chip->info->ops->stats_get_sset_count(chip); 1017 if (count < 0) 1018 goto out; 1019 1020 if (chip->info->ops->serdes_get_sset_count) 1021 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1022 port); 1023 if (serdes_count < 0) { 1024 count = serdes_count; 1025 goto out; 1026 } 1027 count += serdes_count; 1028 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1029 1030 out: 1031 mv88e6xxx_reg_unlock(chip); 1032 1033 return count; 1034 } 1035 1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1037 uint64_t *data, int types, 1038 u16 bank1_select, u16 histogram) 1039 { 1040 struct mv88e6xxx_hw_stat *stat; 1041 int i, j; 1042 1043 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1044 stat = &mv88e6xxx_hw_stats[i]; 1045 if (stat->type & types) { 1046 mv88e6xxx_reg_lock(chip); 1047 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1048 bank1_select, 1049 histogram); 1050 mv88e6xxx_reg_unlock(chip); 1051 1052 j++; 1053 } 1054 } 1055 return j; 1056 } 1057 1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1059 uint64_t *data) 1060 { 1061 return mv88e6xxx_stats_get_stats(chip, port, data, 1062 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1063 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1064 } 1065 1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1067 uint64_t *data) 1068 { 1069 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1070 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1071 } 1072 1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1074 uint64_t *data) 1075 { 1076 return mv88e6xxx_stats_get_stats(chip, port, data, 1077 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1078 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1079 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1080 } 1081 1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1083 uint64_t *data) 1084 { 1085 return mv88e6xxx_stats_get_stats(chip, port, data, 1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1088 0); 1089 } 1090 1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data) 1093 { 1094 *data++ = chip->ports[port].atu_member_violation; 1095 *data++ = chip->ports[port].atu_miss_violation; 1096 *data++ = chip->ports[port].atu_full_violation; 1097 *data++ = chip->ports[port].vtu_member_violation; 1098 *data++ = chip->ports[port].vtu_miss_violation; 1099 } 1100 1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 int count = 0; 1105 1106 if (chip->info->ops->stats_get_stats) 1107 count = chip->info->ops->stats_get_stats(chip, port, data); 1108 1109 mv88e6xxx_reg_lock(chip); 1110 if (chip->info->ops->serdes_get_stats) { 1111 data += count; 1112 count = chip->info->ops->serdes_get_stats(chip, port, data); 1113 } 1114 data += count; 1115 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1116 mv88e6xxx_reg_unlock(chip); 1117 } 1118 1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1120 uint64_t *data) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int ret; 1124 1125 mv88e6xxx_reg_lock(chip); 1126 1127 ret = mv88e6xxx_stats_snapshot(chip, port); 1128 mv88e6xxx_reg_unlock(chip); 1129 1130 if (ret < 0) 1131 return; 1132 1133 mv88e6xxx_get_stats(chip, port, data); 1134 1135 } 1136 1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1138 { 1139 struct mv88e6xxx_chip *chip = ds->priv; 1140 int len; 1141 1142 len = 32 * sizeof(u16); 1143 if (chip->info->ops->serdes_get_regs_len) 1144 len += chip->info->ops->serdes_get_regs_len(chip, port); 1145 1146 return len; 1147 } 1148 1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1150 struct ethtool_regs *regs, void *_p) 1151 { 1152 struct mv88e6xxx_chip *chip = ds->priv; 1153 int err; 1154 u16 reg; 1155 u16 *p = _p; 1156 int i; 1157 1158 regs->version = chip->info->prod_num; 1159 1160 memset(p, 0xff, 32 * sizeof(u16)); 1161 1162 mv88e6xxx_reg_lock(chip); 1163 1164 for (i = 0; i < 32; i++) { 1165 1166 err = mv88e6xxx_port_read(chip, port, i, ®); 1167 if (!err) 1168 p[i] = reg; 1169 } 1170 1171 if (chip->info->ops->serdes_get_regs) 1172 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1173 1174 mv88e6xxx_reg_unlock(chip); 1175 } 1176 1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1178 struct ethtool_eee *e) 1179 { 1180 /* Nothing to do on the port's MAC */ 1181 return 0; 1182 } 1183 1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1185 struct ethtool_eee *e) 1186 { 1187 /* Nothing to do on the port's MAC */ 1188 return 0; 1189 } 1190 1191 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1193 { 1194 struct dsa_switch *ds = chip->ds; 1195 struct dsa_switch_tree *dst = ds->dst; 1196 struct net_device *br; 1197 struct dsa_port *dp; 1198 bool found = false; 1199 u16 pvlan; 1200 1201 list_for_each_entry(dp, &dst->ports, list) { 1202 if (dp->ds->index == dev && dp->index == port) { 1203 found = true; 1204 break; 1205 } 1206 } 1207 1208 /* Prevent frames from unknown switch or port */ 1209 if (!found) 1210 return 0; 1211 1212 /* Frames from DSA links and CPU ports can egress any local port */ 1213 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1214 return mv88e6xxx_port_mask(chip); 1215 1216 br = dp->bridge_dev; 1217 pvlan = 0; 1218 1219 /* Frames from user ports can egress any local DSA links and CPU ports, 1220 * as well as any local member of their bridge group. 1221 */ 1222 list_for_each_entry(dp, &dst->ports, list) 1223 if (dp->ds == ds && 1224 (dp->type == DSA_PORT_TYPE_CPU || 1225 dp->type == DSA_PORT_TYPE_DSA || 1226 (br && dp->bridge_dev == br))) 1227 pvlan |= BIT(dp->index); 1228 1229 return pvlan; 1230 } 1231 1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1233 { 1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1235 1236 /* prevent frames from going back out of the port they came in on */ 1237 output_ports &= ~BIT(port); 1238 1239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1240 } 1241 1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1243 u8 state) 1244 { 1245 struct mv88e6xxx_chip *chip = ds->priv; 1246 int err; 1247 1248 mv88e6xxx_reg_lock(chip); 1249 err = mv88e6xxx_port_set_state(chip, port, state); 1250 mv88e6xxx_reg_unlock(chip); 1251 1252 if (err) 1253 dev_err(ds->dev, "p%d: failed to update state\n", port); 1254 } 1255 1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1257 { 1258 int err; 1259 1260 if (chip->info->ops->ieee_pri_map) { 1261 err = chip->info->ops->ieee_pri_map(chip); 1262 if (err) 1263 return err; 1264 } 1265 1266 if (chip->info->ops->ip_pri_map) { 1267 err = chip->info->ops->ip_pri_map(chip); 1268 if (err) 1269 return err; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1276 { 1277 struct dsa_switch *ds = chip->ds; 1278 int target, port; 1279 int err; 1280 1281 if (!chip->info->global2_addr) 1282 return 0; 1283 1284 /* Initialize the routing port to the 32 possible target devices */ 1285 for (target = 0; target < 32; target++) { 1286 port = dsa_routing_port(ds, target); 1287 if (port == ds->num_ports) 1288 port = 0x1f; 1289 1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1291 if (err) 1292 return err; 1293 } 1294 1295 if (chip->info->ops->set_cascade_port) { 1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1297 err = chip->info->ops->set_cascade_port(chip, port); 1298 if (err) 1299 return err; 1300 } 1301 1302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1303 if (err) 1304 return err; 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 /* Clear all trunk masks and mapping */ 1312 if (chip->info->global2_addr) 1313 return mv88e6xxx_g2_trunk_clear(chip); 1314 1315 return 0; 1316 } 1317 1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 if (chip->info->ops->rmu_disable) 1321 return chip->info->ops->rmu_disable(chip); 1322 1323 return 0; 1324 } 1325 1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1327 { 1328 if (chip->info->ops->pot_clear) 1329 return chip->info->ops->pot_clear(chip); 1330 1331 return 0; 1332 } 1333 1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1335 { 1336 if (chip->info->ops->mgmt_rsvd2cpu) 1337 return chip->info->ops->mgmt_rsvd2cpu(chip); 1338 1339 return 0; 1340 } 1341 1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1343 { 1344 int err; 1345 1346 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1347 if (err) 1348 return err; 1349 1350 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1351 if (err) 1352 return err; 1353 1354 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1355 } 1356 1357 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1358 { 1359 int port; 1360 int err; 1361 1362 if (!chip->info->ops->irl_init_all) 1363 return 0; 1364 1365 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1366 /* Disable ingress rate limiting by resetting all per port 1367 * ingress rate limit resources to their initial state. 1368 */ 1369 err = chip->info->ops->irl_init_all(chip, port); 1370 if (err) 1371 return err; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1378 { 1379 if (chip->info->ops->set_switch_mac) { 1380 u8 addr[ETH_ALEN]; 1381 1382 eth_random_addr(addr); 1383 1384 return chip->info->ops->set_switch_mac(chip, addr); 1385 } 1386 1387 return 0; 1388 } 1389 1390 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1391 { 1392 u16 pvlan = 0; 1393 1394 if (!mv88e6xxx_has_pvt(chip)) 1395 return 0; 1396 1397 /* Skip the local source device, which uses in-chip port VLAN */ 1398 if (dev != chip->ds->index) 1399 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1400 1401 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1402 } 1403 1404 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1405 { 1406 int dev, port; 1407 int err; 1408 1409 if (!mv88e6xxx_has_pvt(chip)) 1410 return 0; 1411 1412 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1413 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1414 */ 1415 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1416 if (err) 1417 return err; 1418 1419 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1420 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1421 err = mv88e6xxx_pvt_map(chip, dev, port); 1422 if (err) 1423 return err; 1424 } 1425 } 1426 1427 return 0; 1428 } 1429 1430 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1431 { 1432 struct mv88e6xxx_chip *chip = ds->priv; 1433 int err; 1434 1435 mv88e6xxx_reg_lock(chip); 1436 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1437 mv88e6xxx_reg_unlock(chip); 1438 1439 if (err) 1440 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1441 } 1442 1443 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1444 { 1445 if (!mv88e6xxx_max_vid(chip)) 1446 return 0; 1447 1448 return mv88e6xxx_g1_vtu_flush(chip); 1449 } 1450 1451 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1452 struct mv88e6xxx_vtu_entry *entry) 1453 { 1454 if (!chip->info->ops->vtu_getnext) 1455 return -EOPNOTSUPP; 1456 1457 return chip->info->ops->vtu_getnext(chip, entry); 1458 } 1459 1460 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1461 struct mv88e6xxx_vtu_entry *entry) 1462 { 1463 if (!chip->info->ops->vtu_loadpurge) 1464 return -EOPNOTSUPP; 1465 1466 return chip->info->ops->vtu_loadpurge(chip, entry); 1467 } 1468 1469 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1470 { 1471 struct mv88e6xxx_vtu_entry vlan; 1472 int i, err; 1473 u16 fid; 1474 1475 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1476 1477 /* Set every FID bit used by the (un)bridged ports */ 1478 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1479 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1480 if (err) 1481 return err; 1482 1483 set_bit(fid, fid_bitmap); 1484 } 1485 1486 /* Set every FID bit used by the VLAN entries */ 1487 vlan.vid = mv88e6xxx_max_vid(chip); 1488 vlan.valid = false; 1489 1490 do { 1491 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1492 if (err) 1493 return err; 1494 1495 if (!vlan.valid) 1496 break; 1497 1498 set_bit(vlan.fid, fid_bitmap); 1499 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 1500 1501 return 0; 1502 } 1503 1504 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1505 { 1506 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1507 int err; 1508 1509 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1510 if (err) 1511 return err; 1512 1513 /* The reset value 0x000 is used to indicate that multiple address 1514 * databases are not needed. Return the next positive available. 1515 */ 1516 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1517 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1518 return -ENOSPC; 1519 1520 /* Clear the database */ 1521 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1522 } 1523 1524 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1525 u16 vid_begin, u16 vid_end) 1526 { 1527 struct mv88e6xxx_chip *chip = ds->priv; 1528 struct mv88e6xxx_vtu_entry vlan; 1529 int i, err; 1530 1531 /* DSA and CPU ports have to be members of multiple vlans */ 1532 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1533 return 0; 1534 1535 if (!vid_begin) 1536 return -EOPNOTSUPP; 1537 1538 vlan.vid = vid_begin - 1; 1539 vlan.valid = false; 1540 1541 do { 1542 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1543 if (err) 1544 return err; 1545 1546 if (!vlan.valid) 1547 break; 1548 1549 if (vlan.vid > vid_end) 1550 break; 1551 1552 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1553 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1554 continue; 1555 1556 if (!dsa_to_port(ds, i)->slave) 1557 continue; 1558 1559 if (vlan.member[i] == 1560 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1561 continue; 1562 1563 if (dsa_to_port(ds, i)->bridge_dev == 1564 dsa_to_port(ds, port)->bridge_dev) 1565 break; /* same bridge, check next VLAN */ 1566 1567 if (!dsa_to_port(ds, i)->bridge_dev) 1568 continue; 1569 1570 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1571 port, vlan.vid, i, 1572 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1573 return -EOPNOTSUPP; 1574 } 1575 } while (vlan.vid < vid_end); 1576 1577 return 0; 1578 } 1579 1580 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1581 bool vlan_filtering, 1582 struct switchdev_trans *trans) 1583 { 1584 struct mv88e6xxx_chip *chip = ds->priv; 1585 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1586 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1587 int err; 1588 1589 if (switchdev_trans_ph_prepare(trans)) 1590 return mv88e6xxx_max_vid(chip) ? 0 : -EOPNOTSUPP; 1591 1592 mv88e6xxx_reg_lock(chip); 1593 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1594 mv88e6xxx_reg_unlock(chip); 1595 1596 return err; 1597 } 1598 1599 static int 1600 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1601 const struct switchdev_obj_port_vlan *vlan) 1602 { 1603 struct mv88e6xxx_chip *chip = ds->priv; 1604 int err; 1605 1606 if (!mv88e6xxx_max_vid(chip)) 1607 return -EOPNOTSUPP; 1608 1609 /* If the requested port doesn't belong to the same bridge as the VLAN 1610 * members, do not support it (yet) and fallback to software VLAN. 1611 */ 1612 mv88e6xxx_reg_lock(chip); 1613 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1614 vlan->vid_end); 1615 mv88e6xxx_reg_unlock(chip); 1616 1617 /* We don't need any dynamic resource from the kernel (yet), 1618 * so skip the prepare phase. 1619 */ 1620 return err; 1621 } 1622 1623 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1624 const unsigned char *addr, u16 vid, 1625 u8 state) 1626 { 1627 struct mv88e6xxx_atu_entry entry; 1628 struct mv88e6xxx_vtu_entry vlan; 1629 u16 fid; 1630 int err; 1631 1632 /* Null VLAN ID corresponds to the port private database */ 1633 if (vid == 0) { 1634 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1635 if (err) 1636 return err; 1637 } else { 1638 vlan.vid = vid - 1; 1639 vlan.valid = false; 1640 1641 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1642 if (err) 1643 return err; 1644 1645 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1646 if (vlan.vid != vid || !vlan.valid) 1647 return -EOPNOTSUPP; 1648 1649 fid = vlan.fid; 1650 } 1651 1652 entry.state = 0; 1653 ether_addr_copy(entry.mac, addr); 1654 eth_addr_dec(entry.mac); 1655 1656 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1657 if (err) 1658 return err; 1659 1660 /* Initialize a fresh ATU entry if it isn't found */ 1661 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1662 memset(&entry, 0, sizeof(entry)); 1663 ether_addr_copy(entry.mac, addr); 1664 } 1665 1666 /* Purge the ATU entry only if no port is using it anymore */ 1667 if (!state) { 1668 entry.portvec &= ~BIT(port); 1669 if (!entry.portvec) 1670 entry.state = 0; 1671 } else { 1672 entry.portvec |= BIT(port); 1673 entry.state = state; 1674 } 1675 1676 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1677 } 1678 1679 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1680 const struct mv88e6xxx_policy *policy) 1681 { 1682 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1683 enum mv88e6xxx_policy_action action = policy->action; 1684 const u8 *addr = policy->addr; 1685 u16 vid = policy->vid; 1686 u8 state; 1687 int err; 1688 int id; 1689 1690 if (!chip->info->ops->port_set_policy) 1691 return -EOPNOTSUPP; 1692 1693 switch (mapping) { 1694 case MV88E6XXX_POLICY_MAPPING_DA: 1695 case MV88E6XXX_POLICY_MAPPING_SA: 1696 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1697 state = 0; /* Dissociate the port and address */ 1698 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1699 is_multicast_ether_addr(addr)) 1700 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1701 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1702 is_unicast_ether_addr(addr)) 1703 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1704 else 1705 return -EOPNOTSUPP; 1706 1707 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1708 state); 1709 if (err) 1710 return err; 1711 break; 1712 default: 1713 return -EOPNOTSUPP; 1714 } 1715 1716 /* Skip the port's policy clearing if the mapping is still in use */ 1717 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1718 idr_for_each_entry(&chip->policies, policy, id) 1719 if (policy->port == port && 1720 policy->mapping == mapping && 1721 policy->action != action) 1722 return 0; 1723 1724 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1725 } 1726 1727 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1728 struct ethtool_rx_flow_spec *fs) 1729 { 1730 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1731 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1732 enum mv88e6xxx_policy_mapping mapping; 1733 enum mv88e6xxx_policy_action action; 1734 struct mv88e6xxx_policy *policy; 1735 u16 vid = 0; 1736 u8 *addr; 1737 int err; 1738 int id; 1739 1740 if (fs->location != RX_CLS_LOC_ANY) 1741 return -EINVAL; 1742 1743 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1744 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1745 else 1746 return -EOPNOTSUPP; 1747 1748 switch (fs->flow_type & ~FLOW_EXT) { 1749 case ETHER_FLOW: 1750 if (!is_zero_ether_addr(mac_mask->h_dest) && 1751 is_zero_ether_addr(mac_mask->h_source)) { 1752 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1753 addr = mac_entry->h_dest; 1754 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1755 !is_zero_ether_addr(mac_mask->h_source)) { 1756 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1757 addr = mac_entry->h_source; 1758 } else { 1759 /* Cannot support DA and SA mapping in the same rule */ 1760 return -EOPNOTSUPP; 1761 } 1762 break; 1763 default: 1764 return -EOPNOTSUPP; 1765 } 1766 1767 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1768 if (fs->m_ext.vlan_tci != htons(0xffff)) 1769 return -EOPNOTSUPP; 1770 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1771 } 1772 1773 idr_for_each_entry(&chip->policies, policy, id) { 1774 if (policy->port == port && policy->mapping == mapping && 1775 policy->action == action && policy->vid == vid && 1776 ether_addr_equal(policy->addr, addr)) 1777 return -EEXIST; 1778 } 1779 1780 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1781 if (!policy) 1782 return -ENOMEM; 1783 1784 fs->location = 0; 1785 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1786 GFP_KERNEL); 1787 if (err) { 1788 devm_kfree(chip->dev, policy); 1789 return err; 1790 } 1791 1792 memcpy(&policy->fs, fs, sizeof(*fs)); 1793 ether_addr_copy(policy->addr, addr); 1794 policy->mapping = mapping; 1795 policy->action = action; 1796 policy->port = port; 1797 policy->vid = vid; 1798 1799 err = mv88e6xxx_policy_apply(chip, port, policy); 1800 if (err) { 1801 idr_remove(&chip->policies, fs->location); 1802 devm_kfree(chip->dev, policy); 1803 return err; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1810 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1811 { 1812 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1813 struct mv88e6xxx_chip *chip = ds->priv; 1814 struct mv88e6xxx_policy *policy; 1815 int err; 1816 int id; 1817 1818 mv88e6xxx_reg_lock(chip); 1819 1820 switch (rxnfc->cmd) { 1821 case ETHTOOL_GRXCLSRLCNT: 1822 rxnfc->data = 0; 1823 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1824 rxnfc->rule_cnt = 0; 1825 idr_for_each_entry(&chip->policies, policy, id) 1826 if (policy->port == port) 1827 rxnfc->rule_cnt++; 1828 err = 0; 1829 break; 1830 case ETHTOOL_GRXCLSRULE: 1831 err = -ENOENT; 1832 policy = idr_find(&chip->policies, fs->location); 1833 if (policy) { 1834 memcpy(fs, &policy->fs, sizeof(*fs)); 1835 err = 0; 1836 } 1837 break; 1838 case ETHTOOL_GRXCLSRLALL: 1839 rxnfc->data = 0; 1840 rxnfc->rule_cnt = 0; 1841 idr_for_each_entry(&chip->policies, policy, id) 1842 if (policy->port == port) 1843 rule_locs[rxnfc->rule_cnt++] = id; 1844 err = 0; 1845 break; 1846 default: 1847 err = -EOPNOTSUPP; 1848 break; 1849 } 1850 1851 mv88e6xxx_reg_unlock(chip); 1852 1853 return err; 1854 } 1855 1856 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1857 struct ethtool_rxnfc *rxnfc) 1858 { 1859 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1860 struct mv88e6xxx_chip *chip = ds->priv; 1861 struct mv88e6xxx_policy *policy; 1862 int err; 1863 1864 mv88e6xxx_reg_lock(chip); 1865 1866 switch (rxnfc->cmd) { 1867 case ETHTOOL_SRXCLSRLINS: 1868 err = mv88e6xxx_policy_insert(chip, port, fs); 1869 break; 1870 case ETHTOOL_SRXCLSRLDEL: 1871 err = -ENOENT; 1872 policy = idr_remove(&chip->policies, fs->location); 1873 if (policy) { 1874 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1875 err = mv88e6xxx_policy_apply(chip, port, policy); 1876 devm_kfree(chip->dev, policy); 1877 } 1878 break; 1879 default: 1880 err = -EOPNOTSUPP; 1881 break; 1882 } 1883 1884 mv88e6xxx_reg_unlock(chip); 1885 1886 return err; 1887 } 1888 1889 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1890 u16 vid) 1891 { 1892 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1893 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1894 1895 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1896 } 1897 1898 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1899 { 1900 int port; 1901 int err; 1902 1903 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1904 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1905 if (err) 1906 return err; 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1913 u16 vid, u8 member, bool warn) 1914 { 1915 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1916 struct mv88e6xxx_vtu_entry vlan; 1917 int i, err; 1918 1919 if (!vid) 1920 return -EOPNOTSUPP; 1921 1922 vlan.vid = vid - 1; 1923 vlan.valid = false; 1924 1925 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1926 if (err) 1927 return err; 1928 1929 if (vlan.vid != vid || !vlan.valid) { 1930 memset(&vlan, 0, sizeof(vlan)); 1931 1932 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1933 if (err) 1934 return err; 1935 1936 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1937 if (i == port) 1938 vlan.member[i] = member; 1939 else 1940 vlan.member[i] = non_member; 1941 1942 vlan.vid = vid; 1943 vlan.valid = true; 1944 1945 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1946 if (err) 1947 return err; 1948 1949 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1950 if (err) 1951 return err; 1952 } else if (vlan.member[port] != member) { 1953 vlan.member[port] = member; 1954 1955 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1956 if (err) 1957 return err; 1958 } else if (warn) { 1959 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1960 port, vid); 1961 } 1962 1963 return 0; 1964 } 1965 1966 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1967 const struct switchdev_obj_port_vlan *vlan) 1968 { 1969 struct mv88e6xxx_chip *chip = ds->priv; 1970 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1971 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1972 bool warn; 1973 u8 member; 1974 u16 vid; 1975 1976 if (!mv88e6xxx_max_vid(chip)) 1977 return; 1978 1979 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1980 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1981 else if (untagged) 1982 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1983 else 1984 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1985 1986 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1987 * and then the CPU port. Do not warn for duplicates for the CPU port. 1988 */ 1989 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1990 1991 mv88e6xxx_reg_lock(chip); 1992 1993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1994 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1995 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1996 vid, untagged ? 'u' : 't'); 1997 1998 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1999 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 2000 vlan->vid_end); 2001 2002 mv88e6xxx_reg_unlock(chip); 2003 } 2004 2005 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2006 int port, u16 vid) 2007 { 2008 struct mv88e6xxx_vtu_entry vlan; 2009 int i, err; 2010 2011 if (!vid) 2012 return -EOPNOTSUPP; 2013 2014 vlan.vid = vid - 1; 2015 vlan.valid = false; 2016 2017 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2018 if (err) 2019 return err; 2020 2021 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2022 * tell switchdev that this VLAN is likely handled in software. 2023 */ 2024 if (vlan.vid != vid || !vlan.valid || 2025 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2026 return -EOPNOTSUPP; 2027 2028 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2029 2030 /* keep the VLAN unless all ports are excluded */ 2031 vlan.valid = false; 2032 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2033 if (vlan.member[i] != 2034 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2035 vlan.valid = true; 2036 break; 2037 } 2038 } 2039 2040 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2041 if (err) 2042 return err; 2043 2044 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2045 } 2046 2047 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2048 const struct switchdev_obj_port_vlan *vlan) 2049 { 2050 struct mv88e6xxx_chip *chip = ds->priv; 2051 u16 pvid, vid; 2052 int err = 0; 2053 2054 if (!mv88e6xxx_max_vid(chip)) 2055 return -EOPNOTSUPP; 2056 2057 mv88e6xxx_reg_lock(chip); 2058 2059 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2060 if (err) 2061 goto unlock; 2062 2063 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2064 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2065 if (err) 2066 goto unlock; 2067 2068 if (vid == pvid) { 2069 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2070 if (err) 2071 goto unlock; 2072 } 2073 } 2074 2075 unlock: 2076 mv88e6xxx_reg_unlock(chip); 2077 2078 return err; 2079 } 2080 2081 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2082 const unsigned char *addr, u16 vid) 2083 { 2084 struct mv88e6xxx_chip *chip = ds->priv; 2085 int err; 2086 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2089 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2090 mv88e6xxx_reg_unlock(chip); 2091 2092 return err; 2093 } 2094 2095 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2096 const unsigned char *addr, u16 vid) 2097 { 2098 struct mv88e6xxx_chip *chip = ds->priv; 2099 int err; 2100 2101 mv88e6xxx_reg_lock(chip); 2102 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2103 mv88e6xxx_reg_unlock(chip); 2104 2105 return err; 2106 } 2107 2108 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2109 u16 fid, u16 vid, int port, 2110 dsa_fdb_dump_cb_t *cb, void *data) 2111 { 2112 struct mv88e6xxx_atu_entry addr; 2113 bool is_static; 2114 int err; 2115 2116 addr.state = 0; 2117 eth_broadcast_addr(addr.mac); 2118 2119 do { 2120 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2121 if (err) 2122 return err; 2123 2124 if (!addr.state) 2125 break; 2126 2127 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2128 continue; 2129 2130 if (!is_unicast_ether_addr(addr.mac)) 2131 continue; 2132 2133 is_static = (addr.state == 2134 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2135 err = cb(addr.mac, vid, is_static, data); 2136 if (err) 2137 return err; 2138 } while (!is_broadcast_ether_addr(addr.mac)); 2139 2140 return err; 2141 } 2142 2143 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2144 dsa_fdb_dump_cb_t *cb, void *data) 2145 { 2146 struct mv88e6xxx_vtu_entry vlan; 2147 u16 fid; 2148 int err; 2149 2150 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2151 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2152 if (err) 2153 return err; 2154 2155 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2156 if (err) 2157 return err; 2158 2159 /* Dump VLANs' Filtering Information Databases */ 2160 vlan.vid = mv88e6xxx_max_vid(chip); 2161 vlan.valid = false; 2162 2163 do { 2164 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2165 if (err) 2166 return err; 2167 2168 if (!vlan.valid) 2169 break; 2170 2171 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2172 cb, data); 2173 if (err) 2174 return err; 2175 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 2176 2177 return err; 2178 } 2179 2180 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2181 dsa_fdb_dump_cb_t *cb, void *data) 2182 { 2183 struct mv88e6xxx_chip *chip = ds->priv; 2184 int err; 2185 2186 mv88e6xxx_reg_lock(chip); 2187 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2188 mv88e6xxx_reg_unlock(chip); 2189 2190 return err; 2191 } 2192 2193 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2194 struct net_device *br) 2195 { 2196 struct dsa_switch *ds = chip->ds; 2197 struct dsa_switch_tree *dst = ds->dst; 2198 struct dsa_port *dp; 2199 int err; 2200 2201 list_for_each_entry(dp, &dst->ports, list) { 2202 if (dp->bridge_dev == br) { 2203 if (dp->ds == ds) { 2204 /* This is a local bridge group member, 2205 * remap its Port VLAN Map. 2206 */ 2207 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2208 if (err) 2209 return err; 2210 } else { 2211 /* This is an external bridge group member, 2212 * remap its cross-chip Port VLAN Table entry. 2213 */ 2214 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2215 dp->index); 2216 if (err) 2217 return err; 2218 } 2219 } 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2226 struct net_device *br) 2227 { 2228 struct mv88e6xxx_chip *chip = ds->priv; 2229 int err; 2230 2231 mv88e6xxx_reg_lock(chip); 2232 err = mv88e6xxx_bridge_map(chip, br); 2233 mv88e6xxx_reg_unlock(chip); 2234 2235 return err; 2236 } 2237 2238 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2239 struct net_device *br) 2240 { 2241 struct mv88e6xxx_chip *chip = ds->priv; 2242 2243 mv88e6xxx_reg_lock(chip); 2244 if (mv88e6xxx_bridge_map(chip, br) || 2245 mv88e6xxx_port_vlan_map(chip, port)) 2246 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2247 mv88e6xxx_reg_unlock(chip); 2248 } 2249 2250 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2251 int tree_index, int sw_index, 2252 int port, struct net_device *br) 2253 { 2254 struct mv88e6xxx_chip *chip = ds->priv; 2255 int err; 2256 2257 if (tree_index != ds->dst->index) 2258 return 0; 2259 2260 mv88e6xxx_reg_lock(chip); 2261 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2262 mv88e6xxx_reg_unlock(chip); 2263 2264 return err; 2265 } 2266 2267 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2268 int tree_index, int sw_index, 2269 int port, struct net_device *br) 2270 { 2271 struct mv88e6xxx_chip *chip = ds->priv; 2272 2273 if (tree_index != ds->dst->index) 2274 return; 2275 2276 mv88e6xxx_reg_lock(chip); 2277 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2278 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2279 mv88e6xxx_reg_unlock(chip); 2280 } 2281 2282 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2283 { 2284 if (chip->info->ops->reset) 2285 return chip->info->ops->reset(chip); 2286 2287 return 0; 2288 } 2289 2290 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2291 { 2292 struct gpio_desc *gpiod = chip->reset; 2293 2294 /* If there is a GPIO connected to the reset pin, toggle it */ 2295 if (gpiod) { 2296 gpiod_set_value_cansleep(gpiod, 1); 2297 usleep_range(10000, 20000); 2298 gpiod_set_value_cansleep(gpiod, 0); 2299 usleep_range(10000, 20000); 2300 } 2301 } 2302 2303 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2304 { 2305 int i, err; 2306 2307 /* Set all ports to the Disabled state */ 2308 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2309 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2310 if (err) 2311 return err; 2312 } 2313 2314 /* Wait for transmit queues to drain, 2315 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2316 */ 2317 usleep_range(2000, 4000); 2318 2319 return 0; 2320 } 2321 2322 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2323 { 2324 int err; 2325 2326 err = mv88e6xxx_disable_ports(chip); 2327 if (err) 2328 return err; 2329 2330 mv88e6xxx_hardware_reset(chip); 2331 2332 return mv88e6xxx_software_reset(chip); 2333 } 2334 2335 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2336 enum mv88e6xxx_frame_mode frame, 2337 enum mv88e6xxx_egress_mode egress, u16 etype) 2338 { 2339 int err; 2340 2341 if (!chip->info->ops->port_set_frame_mode) 2342 return -EOPNOTSUPP; 2343 2344 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2345 if (err) 2346 return err; 2347 2348 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2349 if (err) 2350 return err; 2351 2352 if (chip->info->ops->port_set_ether_type) 2353 return chip->info->ops->port_set_ether_type(chip, port, etype); 2354 2355 return 0; 2356 } 2357 2358 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2359 { 2360 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2361 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2362 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2363 } 2364 2365 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2366 { 2367 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2368 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2369 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2370 } 2371 2372 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2373 { 2374 return mv88e6xxx_set_port_mode(chip, port, 2375 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2376 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2377 ETH_P_EDSA); 2378 } 2379 2380 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2381 { 2382 if (dsa_is_dsa_port(chip->ds, port)) 2383 return mv88e6xxx_set_port_mode_dsa(chip, port); 2384 2385 if (dsa_is_user_port(chip->ds, port)) 2386 return mv88e6xxx_set_port_mode_normal(chip, port); 2387 2388 /* Setup CPU port mode depending on its supported tag format */ 2389 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2390 return mv88e6xxx_set_port_mode_dsa(chip, port); 2391 2392 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2393 return mv88e6xxx_set_port_mode_edsa(chip, port); 2394 2395 return -EINVAL; 2396 } 2397 2398 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2399 { 2400 bool message = dsa_is_dsa_port(chip->ds, port); 2401 2402 return mv88e6xxx_port_set_message_port(chip, port, message); 2403 } 2404 2405 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2406 { 2407 struct dsa_switch *ds = chip->ds; 2408 bool flood; 2409 2410 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2411 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2412 if (chip->info->ops->port_set_egress_floods) 2413 return chip->info->ops->port_set_egress_floods(chip, port, 2414 flood, flood); 2415 2416 return 0; 2417 } 2418 2419 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2420 { 2421 struct mv88e6xxx_port *mvp = dev_id; 2422 struct mv88e6xxx_chip *chip = mvp->chip; 2423 irqreturn_t ret = IRQ_NONE; 2424 int port = mvp->port; 2425 u8 lane; 2426 2427 mv88e6xxx_reg_lock(chip); 2428 lane = mv88e6xxx_serdes_get_lane(chip, port); 2429 if (lane) 2430 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2431 mv88e6xxx_reg_unlock(chip); 2432 2433 return ret; 2434 } 2435 2436 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2437 u8 lane) 2438 { 2439 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2440 unsigned int irq; 2441 int err; 2442 2443 /* Nothing to request if this SERDES port has no IRQ */ 2444 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2445 if (!irq) 2446 return 0; 2447 2448 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2449 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2450 2451 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2452 mv88e6xxx_reg_unlock(chip); 2453 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2454 IRQF_ONESHOT, dev_id->serdes_irq_name, 2455 dev_id); 2456 mv88e6xxx_reg_lock(chip); 2457 if (err) 2458 return err; 2459 2460 dev_id->serdes_irq = irq; 2461 2462 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2463 } 2464 2465 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2466 u8 lane) 2467 { 2468 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2469 unsigned int irq = dev_id->serdes_irq; 2470 int err; 2471 2472 /* Nothing to free if no IRQ has been requested */ 2473 if (!irq) 2474 return 0; 2475 2476 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2477 2478 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2479 mv88e6xxx_reg_unlock(chip); 2480 free_irq(irq, dev_id); 2481 mv88e6xxx_reg_lock(chip); 2482 2483 dev_id->serdes_irq = 0; 2484 2485 return err; 2486 } 2487 2488 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2489 bool on) 2490 { 2491 u8 lane; 2492 int err; 2493 2494 lane = mv88e6xxx_serdes_get_lane(chip, port); 2495 if (!lane) 2496 return 0; 2497 2498 if (on) { 2499 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2500 if (err) 2501 return err; 2502 2503 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2504 } else { 2505 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2506 if (err) 2507 return err; 2508 2509 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2510 } 2511 2512 return err; 2513 } 2514 2515 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2516 { 2517 struct dsa_switch *ds = chip->ds; 2518 int upstream_port; 2519 int err; 2520 2521 upstream_port = dsa_upstream_port(ds, port); 2522 if (chip->info->ops->port_set_upstream_port) { 2523 err = chip->info->ops->port_set_upstream_port(chip, port, 2524 upstream_port); 2525 if (err) 2526 return err; 2527 } 2528 2529 if (port == upstream_port) { 2530 if (chip->info->ops->set_cpu_port) { 2531 err = chip->info->ops->set_cpu_port(chip, 2532 upstream_port); 2533 if (err) 2534 return err; 2535 } 2536 2537 if (chip->info->ops->set_egress_port) { 2538 err = chip->info->ops->set_egress_port(chip, 2539 MV88E6XXX_EGRESS_DIR_INGRESS, 2540 upstream_port); 2541 if (err) 2542 return err; 2543 2544 err = chip->info->ops->set_egress_port(chip, 2545 MV88E6XXX_EGRESS_DIR_EGRESS, 2546 upstream_port); 2547 if (err) 2548 return err; 2549 } 2550 } 2551 2552 return 0; 2553 } 2554 2555 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2556 { 2557 struct dsa_switch *ds = chip->ds; 2558 int err; 2559 u16 reg; 2560 2561 chip->ports[port].chip = chip; 2562 chip->ports[port].port = port; 2563 2564 /* MAC Forcing register: don't force link, speed, duplex or flow control 2565 * state to any particular values on physical ports, but force the CPU 2566 * port and all DSA ports to their maximum bandwidth and full duplex. 2567 */ 2568 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2569 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2570 SPEED_MAX, DUPLEX_FULL, 2571 PAUSE_OFF, 2572 PHY_INTERFACE_MODE_NA); 2573 else 2574 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2575 SPEED_UNFORCED, DUPLEX_UNFORCED, 2576 PAUSE_ON, 2577 PHY_INTERFACE_MODE_NA); 2578 if (err) 2579 return err; 2580 2581 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2582 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2583 * tunneling, determine priority by looking at 802.1p and IP 2584 * priority fields (IP prio has precedence), and set STP state 2585 * to Forwarding. 2586 * 2587 * If this is the CPU link, use DSA or EDSA tagging depending 2588 * on which tagging mode was configured. 2589 * 2590 * If this is a link to another switch, use DSA tagging mode. 2591 * 2592 * If this is the upstream port for this switch, enable 2593 * forwarding of unknown unicasts and multicasts. 2594 */ 2595 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2596 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2597 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2598 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2599 if (err) 2600 return err; 2601 2602 err = mv88e6xxx_setup_port_mode(chip, port); 2603 if (err) 2604 return err; 2605 2606 err = mv88e6xxx_setup_egress_floods(chip, port); 2607 if (err) 2608 return err; 2609 2610 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2611 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2612 * untagged frames on this port, do a destination address lookup on all 2613 * received packets as usual, disable ARP mirroring and don't send a 2614 * copy of all transmitted/received frames on this port to the CPU. 2615 */ 2616 err = mv88e6xxx_port_set_map_da(chip, port); 2617 if (err) 2618 return err; 2619 2620 err = mv88e6xxx_setup_upstream_port(chip, port); 2621 if (err) 2622 return err; 2623 2624 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2625 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2626 if (err) 2627 return err; 2628 2629 if (chip->info->ops->port_set_jumbo_size) { 2630 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2631 if (err) 2632 return err; 2633 } 2634 2635 /* Port Association Vector: when learning source addresses 2636 * of packets, add the address to the address database using 2637 * a port bitmap that has only the bit for this port set and 2638 * the other bits clear. 2639 */ 2640 reg = 1 << port; 2641 /* Disable learning for CPU port */ 2642 if (dsa_is_cpu_port(ds, port)) 2643 reg = 0; 2644 2645 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2646 reg); 2647 if (err) 2648 return err; 2649 2650 /* Egress rate control 2: disable egress rate control. */ 2651 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2652 0x0000); 2653 if (err) 2654 return err; 2655 2656 if (chip->info->ops->port_pause_limit) { 2657 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2658 if (err) 2659 return err; 2660 } 2661 2662 if (chip->info->ops->port_disable_learn_limit) { 2663 err = chip->info->ops->port_disable_learn_limit(chip, port); 2664 if (err) 2665 return err; 2666 } 2667 2668 if (chip->info->ops->port_disable_pri_override) { 2669 err = chip->info->ops->port_disable_pri_override(chip, port); 2670 if (err) 2671 return err; 2672 } 2673 2674 if (chip->info->ops->port_tag_remap) { 2675 err = chip->info->ops->port_tag_remap(chip, port); 2676 if (err) 2677 return err; 2678 } 2679 2680 if (chip->info->ops->port_egress_rate_limiting) { 2681 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2682 if (err) 2683 return err; 2684 } 2685 2686 if (chip->info->ops->port_setup_message_port) { 2687 err = chip->info->ops->port_setup_message_port(chip, port); 2688 if (err) 2689 return err; 2690 } 2691 2692 /* Port based VLAN map: give each port the same default address 2693 * database, and allow bidirectional communication between the 2694 * CPU and DSA port(s), and the other ports. 2695 */ 2696 err = mv88e6xxx_port_set_fid(chip, port, 0); 2697 if (err) 2698 return err; 2699 2700 err = mv88e6xxx_port_vlan_map(chip, port); 2701 if (err) 2702 return err; 2703 2704 /* Default VLAN ID and priority: don't set a default VLAN 2705 * ID, and set the default packet priority to zero. 2706 */ 2707 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2708 } 2709 2710 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2711 { 2712 struct mv88e6xxx_chip *chip = ds->priv; 2713 2714 if (chip->info->ops->port_set_jumbo_size) 2715 return 10240; 2716 else if (chip->info->ops->set_max_frame_size) 2717 return 1632; 2718 return 1522; 2719 } 2720 2721 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2722 { 2723 struct mv88e6xxx_chip *chip = ds->priv; 2724 int ret = 0; 2725 2726 mv88e6xxx_reg_lock(chip); 2727 if (chip->info->ops->port_set_jumbo_size) 2728 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2729 else if (chip->info->ops->set_max_frame_size) 2730 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2731 else 2732 if (new_mtu > 1522) 2733 ret = -EINVAL; 2734 mv88e6xxx_reg_unlock(chip); 2735 2736 return ret; 2737 } 2738 2739 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2740 struct phy_device *phydev) 2741 { 2742 struct mv88e6xxx_chip *chip = ds->priv; 2743 int err; 2744 2745 mv88e6xxx_reg_lock(chip); 2746 err = mv88e6xxx_serdes_power(chip, port, true); 2747 mv88e6xxx_reg_unlock(chip); 2748 2749 return err; 2750 } 2751 2752 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2753 { 2754 struct mv88e6xxx_chip *chip = ds->priv; 2755 2756 mv88e6xxx_reg_lock(chip); 2757 if (mv88e6xxx_serdes_power(chip, port, false)) 2758 dev_err(chip->dev, "failed to power off SERDES\n"); 2759 mv88e6xxx_reg_unlock(chip); 2760 } 2761 2762 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2763 unsigned int ageing_time) 2764 { 2765 struct mv88e6xxx_chip *chip = ds->priv; 2766 int err; 2767 2768 mv88e6xxx_reg_lock(chip); 2769 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2770 mv88e6xxx_reg_unlock(chip); 2771 2772 return err; 2773 } 2774 2775 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2776 { 2777 int err; 2778 2779 /* Initialize the statistics unit */ 2780 if (chip->info->ops->stats_set_histogram) { 2781 err = chip->info->ops->stats_set_histogram(chip); 2782 if (err) 2783 return err; 2784 } 2785 2786 return mv88e6xxx_g1_stats_clear(chip); 2787 } 2788 2789 /* Check if the errata has already been applied. */ 2790 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2791 { 2792 int port; 2793 int err; 2794 u16 val; 2795 2796 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2797 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2798 if (err) { 2799 dev_err(chip->dev, 2800 "Error reading hidden register: %d\n", err); 2801 return false; 2802 } 2803 if (val != 0x01c0) 2804 return false; 2805 } 2806 2807 return true; 2808 } 2809 2810 /* The 6390 copper ports have an errata which require poking magic 2811 * values into undocumented hidden registers and then performing a 2812 * software reset. 2813 */ 2814 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2815 { 2816 int port; 2817 int err; 2818 2819 if (mv88e6390_setup_errata_applied(chip)) 2820 return 0; 2821 2822 /* Set the ports into blocking mode */ 2823 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2824 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2825 if (err) 2826 return err; 2827 } 2828 2829 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2830 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2831 if (err) 2832 return err; 2833 } 2834 2835 return mv88e6xxx_software_reset(chip); 2836 } 2837 2838 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2839 { 2840 mv88e6xxx_teardown_devlink_params(ds); 2841 dsa_devlink_resources_unregister(ds); 2842 mv88e6xxx_teardown_devlink_regions(ds); 2843 } 2844 2845 static int mv88e6xxx_setup(struct dsa_switch *ds) 2846 { 2847 struct mv88e6xxx_chip *chip = ds->priv; 2848 u8 cmode; 2849 int err; 2850 int i; 2851 2852 chip->ds = ds; 2853 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2854 ds->configure_vlan_while_not_filtering = true; 2855 2856 mv88e6xxx_reg_lock(chip); 2857 2858 if (chip->info->ops->setup_errata) { 2859 err = chip->info->ops->setup_errata(chip); 2860 if (err) 2861 goto unlock; 2862 } 2863 2864 /* Cache the cmode of each port. */ 2865 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2866 if (chip->info->ops->port_get_cmode) { 2867 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2868 if (err) 2869 goto unlock; 2870 2871 chip->ports[i].cmode = cmode; 2872 } 2873 } 2874 2875 /* Setup Switch Port Registers */ 2876 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2877 if (dsa_is_unused_port(ds, i)) 2878 continue; 2879 2880 /* Prevent the use of an invalid port. */ 2881 if (mv88e6xxx_is_invalid_port(chip, i)) { 2882 dev_err(chip->dev, "port %d is invalid\n", i); 2883 err = -EINVAL; 2884 goto unlock; 2885 } 2886 2887 err = mv88e6xxx_setup_port(chip, i); 2888 if (err) 2889 goto unlock; 2890 } 2891 2892 err = mv88e6xxx_irl_setup(chip); 2893 if (err) 2894 goto unlock; 2895 2896 err = mv88e6xxx_mac_setup(chip); 2897 if (err) 2898 goto unlock; 2899 2900 err = mv88e6xxx_phy_setup(chip); 2901 if (err) 2902 goto unlock; 2903 2904 err = mv88e6xxx_vtu_setup(chip); 2905 if (err) 2906 goto unlock; 2907 2908 err = mv88e6xxx_pvt_setup(chip); 2909 if (err) 2910 goto unlock; 2911 2912 err = mv88e6xxx_atu_setup(chip); 2913 if (err) 2914 goto unlock; 2915 2916 err = mv88e6xxx_broadcast_setup(chip, 0); 2917 if (err) 2918 goto unlock; 2919 2920 err = mv88e6xxx_pot_setup(chip); 2921 if (err) 2922 goto unlock; 2923 2924 err = mv88e6xxx_rmu_setup(chip); 2925 if (err) 2926 goto unlock; 2927 2928 err = mv88e6xxx_rsvd2cpu_setup(chip); 2929 if (err) 2930 goto unlock; 2931 2932 err = mv88e6xxx_trunk_setup(chip); 2933 if (err) 2934 goto unlock; 2935 2936 err = mv88e6xxx_devmap_setup(chip); 2937 if (err) 2938 goto unlock; 2939 2940 err = mv88e6xxx_pri_setup(chip); 2941 if (err) 2942 goto unlock; 2943 2944 /* Setup PTP Hardware Clock and timestamping */ 2945 if (chip->info->ptp_support) { 2946 err = mv88e6xxx_ptp_setup(chip); 2947 if (err) 2948 goto unlock; 2949 2950 err = mv88e6xxx_hwtstamp_setup(chip); 2951 if (err) 2952 goto unlock; 2953 } 2954 2955 err = mv88e6xxx_stats_setup(chip); 2956 if (err) 2957 goto unlock; 2958 2959 unlock: 2960 mv88e6xxx_reg_unlock(chip); 2961 2962 if (err) 2963 return err; 2964 2965 /* Have to be called without holding the register lock, since 2966 * they take the devlink lock, and we later take the locks in 2967 * the reverse order when getting/setting parameters or 2968 * resource occupancy. 2969 */ 2970 err = mv88e6xxx_setup_devlink_resources(ds); 2971 if (err) 2972 return err; 2973 2974 err = mv88e6xxx_setup_devlink_params(ds); 2975 if (err) 2976 goto out_resources; 2977 2978 err = mv88e6xxx_setup_devlink_regions(ds); 2979 if (err) 2980 goto out_params; 2981 2982 return 0; 2983 2984 out_params: 2985 mv88e6xxx_teardown_devlink_params(ds); 2986 out_resources: 2987 dsa_devlink_resources_unregister(ds); 2988 2989 return err; 2990 } 2991 2992 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2993 { 2994 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2995 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2996 u16 val; 2997 int err; 2998 2999 if (!chip->info->ops->phy_read) 3000 return -EOPNOTSUPP; 3001 3002 mv88e6xxx_reg_lock(chip); 3003 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3004 mv88e6xxx_reg_unlock(chip); 3005 3006 if (reg == MII_PHYSID2) { 3007 /* Some internal PHYs don't have a model number. */ 3008 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3009 /* Then there is the 6165 family. It gets is 3010 * PHYs correct. But it can also have two 3011 * SERDES interfaces in the PHY address 3012 * space. And these don't have a model 3013 * number. But they are not PHYs, so we don't 3014 * want to give them something a PHY driver 3015 * will recognise. 3016 * 3017 * Use the mv88e6390 family model number 3018 * instead, for anything which really could be 3019 * a PHY, 3020 */ 3021 if (!(val & 0x3f0)) 3022 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3023 } 3024 3025 return err ? err : val; 3026 } 3027 3028 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3029 { 3030 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3031 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3032 int err; 3033 3034 if (!chip->info->ops->phy_write) 3035 return -EOPNOTSUPP; 3036 3037 mv88e6xxx_reg_lock(chip); 3038 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3039 mv88e6xxx_reg_unlock(chip); 3040 3041 return err; 3042 } 3043 3044 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3045 struct device_node *np, 3046 bool external) 3047 { 3048 static int index; 3049 struct mv88e6xxx_mdio_bus *mdio_bus; 3050 struct mii_bus *bus; 3051 int err; 3052 3053 if (external) { 3054 mv88e6xxx_reg_lock(chip); 3055 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3056 mv88e6xxx_reg_unlock(chip); 3057 3058 if (err) 3059 return err; 3060 } 3061 3062 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3063 if (!bus) 3064 return -ENOMEM; 3065 3066 mdio_bus = bus->priv; 3067 mdio_bus->bus = bus; 3068 mdio_bus->chip = chip; 3069 INIT_LIST_HEAD(&mdio_bus->list); 3070 mdio_bus->external = external; 3071 3072 if (np) { 3073 bus->name = np->full_name; 3074 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3075 } else { 3076 bus->name = "mv88e6xxx SMI"; 3077 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3078 } 3079 3080 bus->read = mv88e6xxx_mdio_read; 3081 bus->write = mv88e6xxx_mdio_write; 3082 bus->parent = chip->dev; 3083 3084 if (!external) { 3085 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3086 if (err) 3087 return err; 3088 } 3089 3090 err = of_mdiobus_register(bus, np); 3091 if (err) { 3092 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3093 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3094 return err; 3095 } 3096 3097 if (external) 3098 list_add_tail(&mdio_bus->list, &chip->mdios); 3099 else 3100 list_add(&mdio_bus->list, &chip->mdios); 3101 3102 return 0; 3103 } 3104 3105 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3106 3107 { 3108 struct mv88e6xxx_mdio_bus *mdio_bus; 3109 struct mii_bus *bus; 3110 3111 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3112 bus = mdio_bus->bus; 3113 3114 if (!mdio_bus->external) 3115 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3116 3117 mdiobus_unregister(bus); 3118 } 3119 } 3120 3121 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3122 struct device_node *np) 3123 { 3124 struct device_node *child; 3125 int err; 3126 3127 /* Always register one mdio bus for the internal/default mdio 3128 * bus. This maybe represented in the device tree, but is 3129 * optional. 3130 */ 3131 child = of_get_child_by_name(np, "mdio"); 3132 err = mv88e6xxx_mdio_register(chip, child, false); 3133 if (err) 3134 return err; 3135 3136 /* Walk the device tree, and see if there are any other nodes 3137 * which say they are compatible with the external mdio 3138 * bus. 3139 */ 3140 for_each_available_child_of_node(np, child) { 3141 if (of_device_is_compatible( 3142 child, "marvell,mv88e6xxx-mdio-external")) { 3143 err = mv88e6xxx_mdio_register(chip, child, true); 3144 if (err) { 3145 mv88e6xxx_mdios_unregister(chip); 3146 of_node_put(child); 3147 return err; 3148 } 3149 } 3150 } 3151 3152 return 0; 3153 } 3154 3155 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3156 { 3157 struct mv88e6xxx_chip *chip = ds->priv; 3158 3159 return chip->eeprom_len; 3160 } 3161 3162 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3163 struct ethtool_eeprom *eeprom, u8 *data) 3164 { 3165 struct mv88e6xxx_chip *chip = ds->priv; 3166 int err; 3167 3168 if (!chip->info->ops->get_eeprom) 3169 return -EOPNOTSUPP; 3170 3171 mv88e6xxx_reg_lock(chip); 3172 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3173 mv88e6xxx_reg_unlock(chip); 3174 3175 if (err) 3176 return err; 3177 3178 eeprom->magic = 0xc3ec4951; 3179 3180 return 0; 3181 } 3182 3183 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3184 struct ethtool_eeprom *eeprom, u8 *data) 3185 { 3186 struct mv88e6xxx_chip *chip = ds->priv; 3187 int err; 3188 3189 if (!chip->info->ops->set_eeprom) 3190 return -EOPNOTSUPP; 3191 3192 if (eeprom->magic != 0xc3ec4951) 3193 return -EINVAL; 3194 3195 mv88e6xxx_reg_lock(chip); 3196 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3197 mv88e6xxx_reg_unlock(chip); 3198 3199 return err; 3200 } 3201 3202 static const struct mv88e6xxx_ops mv88e6085_ops = { 3203 /* MV88E6XXX_FAMILY_6097 */ 3204 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3205 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3206 .irl_init_all = mv88e6352_g2_irl_init_all, 3207 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3208 .phy_read = mv88e6185_phy_ppu_read, 3209 .phy_write = mv88e6185_phy_ppu_write, 3210 .port_set_link = mv88e6xxx_port_set_link, 3211 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3212 .port_tag_remap = mv88e6095_port_tag_remap, 3213 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3214 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3215 .port_set_ether_type = mv88e6351_port_set_ether_type, 3216 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3217 .port_pause_limit = mv88e6097_port_pause_limit, 3218 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3219 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3220 .port_get_cmode = mv88e6185_port_get_cmode, 3221 .port_setup_message_port = mv88e6xxx_setup_message_port, 3222 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3223 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3224 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3225 .stats_get_strings = mv88e6095_stats_get_strings, 3226 .stats_get_stats = mv88e6095_stats_get_stats, 3227 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3228 .set_egress_port = mv88e6095_g1_set_egress_port, 3229 .watchdog_ops = &mv88e6097_watchdog_ops, 3230 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3231 .pot_clear = mv88e6xxx_g2_pot_clear, 3232 .ppu_enable = mv88e6185_g1_ppu_enable, 3233 .ppu_disable = mv88e6185_g1_ppu_disable, 3234 .reset = mv88e6185_g1_reset, 3235 .rmu_disable = mv88e6085_g1_rmu_disable, 3236 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3237 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3238 .phylink_validate = mv88e6185_phylink_validate, 3239 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3240 }; 3241 3242 static const struct mv88e6xxx_ops mv88e6095_ops = { 3243 /* MV88E6XXX_FAMILY_6095 */ 3244 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3245 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3246 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3247 .phy_read = mv88e6185_phy_ppu_read, 3248 .phy_write = mv88e6185_phy_ppu_write, 3249 .port_set_link = mv88e6xxx_port_set_link, 3250 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3251 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3252 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3253 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3254 .port_get_cmode = mv88e6185_port_get_cmode, 3255 .port_setup_message_port = mv88e6xxx_setup_message_port, 3256 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3257 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3258 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3259 .stats_get_strings = mv88e6095_stats_get_strings, 3260 .stats_get_stats = mv88e6095_stats_get_stats, 3261 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3262 .ppu_enable = mv88e6185_g1_ppu_enable, 3263 .ppu_disable = mv88e6185_g1_ppu_disable, 3264 .reset = mv88e6185_g1_reset, 3265 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3266 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3267 .phylink_validate = mv88e6185_phylink_validate, 3268 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3269 }; 3270 3271 static const struct mv88e6xxx_ops mv88e6097_ops = { 3272 /* MV88E6XXX_FAMILY_6097 */ 3273 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3274 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3275 .irl_init_all = mv88e6352_g2_irl_init_all, 3276 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3277 .phy_read = mv88e6xxx_g2_smi_phy_read, 3278 .phy_write = mv88e6xxx_g2_smi_phy_write, 3279 .port_set_link = mv88e6xxx_port_set_link, 3280 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3281 .port_tag_remap = mv88e6095_port_tag_remap, 3282 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3283 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3284 .port_set_ether_type = mv88e6351_port_set_ether_type, 3285 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3286 .port_pause_limit = mv88e6097_port_pause_limit, 3287 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3288 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3289 .port_get_cmode = mv88e6185_port_get_cmode, 3290 .port_setup_message_port = mv88e6xxx_setup_message_port, 3291 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3292 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3293 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3294 .stats_get_strings = mv88e6095_stats_get_strings, 3295 .stats_get_stats = mv88e6095_stats_get_stats, 3296 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3297 .set_egress_port = mv88e6095_g1_set_egress_port, 3298 .watchdog_ops = &mv88e6097_watchdog_ops, 3299 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3300 .pot_clear = mv88e6xxx_g2_pot_clear, 3301 .reset = mv88e6352_g1_reset, 3302 .rmu_disable = mv88e6085_g1_rmu_disable, 3303 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3304 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3305 .phylink_validate = mv88e6185_phylink_validate, 3306 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3307 }; 3308 3309 static const struct mv88e6xxx_ops mv88e6123_ops = { 3310 /* MV88E6XXX_FAMILY_6165 */ 3311 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3312 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3313 .irl_init_all = mv88e6352_g2_irl_init_all, 3314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3315 .phy_read = mv88e6xxx_g2_smi_phy_read, 3316 .phy_write = mv88e6xxx_g2_smi_phy_write, 3317 .port_set_link = mv88e6xxx_port_set_link, 3318 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3319 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3320 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3323 .port_get_cmode = mv88e6185_port_get_cmode, 3324 .port_setup_message_port = mv88e6xxx_setup_message_port, 3325 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3326 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3327 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3328 .stats_get_strings = mv88e6095_stats_get_strings, 3329 .stats_get_stats = mv88e6095_stats_get_stats, 3330 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3331 .set_egress_port = mv88e6095_g1_set_egress_port, 3332 .watchdog_ops = &mv88e6097_watchdog_ops, 3333 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3334 .pot_clear = mv88e6xxx_g2_pot_clear, 3335 .reset = mv88e6352_g1_reset, 3336 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3337 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3338 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3339 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3340 .phylink_validate = mv88e6185_phylink_validate, 3341 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3342 }; 3343 3344 static const struct mv88e6xxx_ops mv88e6131_ops = { 3345 /* MV88E6XXX_FAMILY_6185 */ 3346 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3347 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3348 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3349 .phy_read = mv88e6185_phy_ppu_read, 3350 .phy_write = mv88e6185_phy_ppu_write, 3351 .port_set_link = mv88e6xxx_port_set_link, 3352 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3353 .port_tag_remap = mv88e6095_port_tag_remap, 3354 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3355 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3356 .port_set_ether_type = mv88e6351_port_set_ether_type, 3357 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3358 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3360 .port_pause_limit = mv88e6097_port_pause_limit, 3361 .port_set_pause = mv88e6185_port_set_pause, 3362 .port_get_cmode = mv88e6185_port_get_cmode, 3363 .port_setup_message_port = mv88e6xxx_setup_message_port, 3364 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3365 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3366 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3367 .stats_get_strings = mv88e6095_stats_get_strings, 3368 .stats_get_stats = mv88e6095_stats_get_stats, 3369 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3370 .set_egress_port = mv88e6095_g1_set_egress_port, 3371 .watchdog_ops = &mv88e6097_watchdog_ops, 3372 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3373 .ppu_enable = mv88e6185_g1_ppu_enable, 3374 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3375 .ppu_disable = mv88e6185_g1_ppu_disable, 3376 .reset = mv88e6185_g1_reset, 3377 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3378 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3379 .phylink_validate = mv88e6185_phylink_validate, 3380 }; 3381 3382 static const struct mv88e6xxx_ops mv88e6141_ops = { 3383 /* MV88E6XXX_FAMILY_6341 */ 3384 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3385 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3386 .irl_init_all = mv88e6352_g2_irl_init_all, 3387 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3388 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3389 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3390 .phy_read = mv88e6xxx_g2_smi_phy_read, 3391 .phy_write = mv88e6xxx_g2_smi_phy_write, 3392 .port_set_link = mv88e6xxx_port_set_link, 3393 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3394 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3395 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3396 .port_tag_remap = mv88e6095_port_tag_remap, 3397 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3398 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3399 .port_set_ether_type = mv88e6351_port_set_ether_type, 3400 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3401 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3402 .port_pause_limit = mv88e6097_port_pause_limit, 3403 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3404 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3405 .port_get_cmode = mv88e6352_port_get_cmode, 3406 .port_set_cmode = mv88e6341_port_set_cmode, 3407 .port_setup_message_port = mv88e6xxx_setup_message_port, 3408 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3409 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3410 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3411 .stats_get_strings = mv88e6320_stats_get_strings, 3412 .stats_get_stats = mv88e6390_stats_get_stats, 3413 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3414 .set_egress_port = mv88e6390_g1_set_egress_port, 3415 .watchdog_ops = &mv88e6390_watchdog_ops, 3416 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3417 .pot_clear = mv88e6xxx_g2_pot_clear, 3418 .reset = mv88e6352_g1_reset, 3419 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3421 .serdes_power = mv88e6390_serdes_power, 3422 .serdes_get_lane = mv88e6341_serdes_get_lane, 3423 /* Check status register pause & lpa register */ 3424 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3425 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3426 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3427 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3428 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3429 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3430 .serdes_irq_status = mv88e6390_serdes_irq_status, 3431 .gpio_ops = &mv88e6352_gpio_ops, 3432 .phylink_validate = mv88e6341_phylink_validate, 3433 }; 3434 3435 static const struct mv88e6xxx_ops mv88e6161_ops = { 3436 /* MV88E6XXX_FAMILY_6165 */ 3437 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3438 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3439 .irl_init_all = mv88e6352_g2_irl_init_all, 3440 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3441 .phy_read = mv88e6xxx_g2_smi_phy_read, 3442 .phy_write = mv88e6xxx_g2_smi_phy_write, 3443 .port_set_link = mv88e6xxx_port_set_link, 3444 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3445 .port_tag_remap = mv88e6095_port_tag_remap, 3446 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3447 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3448 .port_set_ether_type = mv88e6351_port_set_ether_type, 3449 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3450 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3451 .port_pause_limit = mv88e6097_port_pause_limit, 3452 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3453 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3454 .port_get_cmode = mv88e6185_port_get_cmode, 3455 .port_setup_message_port = mv88e6xxx_setup_message_port, 3456 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3457 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3458 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3459 .stats_get_strings = mv88e6095_stats_get_strings, 3460 .stats_get_stats = mv88e6095_stats_get_stats, 3461 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3462 .set_egress_port = mv88e6095_g1_set_egress_port, 3463 .watchdog_ops = &mv88e6097_watchdog_ops, 3464 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3465 .pot_clear = mv88e6xxx_g2_pot_clear, 3466 .reset = mv88e6352_g1_reset, 3467 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3468 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3469 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3470 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3471 .avb_ops = &mv88e6165_avb_ops, 3472 .ptp_ops = &mv88e6165_ptp_ops, 3473 .phylink_validate = mv88e6185_phylink_validate, 3474 }; 3475 3476 static const struct mv88e6xxx_ops mv88e6165_ops = { 3477 /* MV88E6XXX_FAMILY_6165 */ 3478 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3479 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3480 .irl_init_all = mv88e6352_g2_irl_init_all, 3481 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3482 .phy_read = mv88e6165_phy_read, 3483 .phy_write = mv88e6165_phy_write, 3484 .port_set_link = mv88e6xxx_port_set_link, 3485 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3486 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3487 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3488 .port_get_cmode = mv88e6185_port_get_cmode, 3489 .port_setup_message_port = mv88e6xxx_setup_message_port, 3490 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3491 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3492 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3493 .stats_get_strings = mv88e6095_stats_get_strings, 3494 .stats_get_stats = mv88e6095_stats_get_stats, 3495 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3496 .set_egress_port = mv88e6095_g1_set_egress_port, 3497 .watchdog_ops = &mv88e6097_watchdog_ops, 3498 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3499 .pot_clear = mv88e6xxx_g2_pot_clear, 3500 .reset = mv88e6352_g1_reset, 3501 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3502 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3503 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3504 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3505 .avb_ops = &mv88e6165_avb_ops, 3506 .ptp_ops = &mv88e6165_ptp_ops, 3507 .phylink_validate = mv88e6185_phylink_validate, 3508 }; 3509 3510 static const struct mv88e6xxx_ops mv88e6171_ops = { 3511 /* MV88E6XXX_FAMILY_6351 */ 3512 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3513 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3514 .irl_init_all = mv88e6352_g2_irl_init_all, 3515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3516 .phy_read = mv88e6xxx_g2_smi_phy_read, 3517 .phy_write = mv88e6xxx_g2_smi_phy_write, 3518 .port_set_link = mv88e6xxx_port_set_link, 3519 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3520 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3521 .port_tag_remap = mv88e6095_port_tag_remap, 3522 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3523 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3524 .port_set_ether_type = mv88e6351_port_set_ether_type, 3525 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3526 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3527 .port_pause_limit = mv88e6097_port_pause_limit, 3528 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3529 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3530 .port_get_cmode = mv88e6352_port_get_cmode, 3531 .port_setup_message_port = mv88e6xxx_setup_message_port, 3532 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3533 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3534 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3535 .stats_get_strings = mv88e6095_stats_get_strings, 3536 .stats_get_stats = mv88e6095_stats_get_stats, 3537 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3538 .set_egress_port = mv88e6095_g1_set_egress_port, 3539 .watchdog_ops = &mv88e6097_watchdog_ops, 3540 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3541 .pot_clear = mv88e6xxx_g2_pot_clear, 3542 .reset = mv88e6352_g1_reset, 3543 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3544 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3545 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3546 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3547 .phylink_validate = mv88e6185_phylink_validate, 3548 }; 3549 3550 static const struct mv88e6xxx_ops mv88e6172_ops = { 3551 /* MV88E6XXX_FAMILY_6352 */ 3552 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3553 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3554 .irl_init_all = mv88e6352_g2_irl_init_all, 3555 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3556 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3558 .phy_read = mv88e6xxx_g2_smi_phy_read, 3559 .phy_write = mv88e6xxx_g2_smi_phy_write, 3560 .port_set_link = mv88e6xxx_port_set_link, 3561 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3562 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3563 .port_tag_remap = mv88e6095_port_tag_remap, 3564 .port_set_policy = mv88e6352_port_set_policy, 3565 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3566 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3567 .port_set_ether_type = mv88e6351_port_set_ether_type, 3568 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3569 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3570 .port_pause_limit = mv88e6097_port_pause_limit, 3571 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3572 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3573 .port_get_cmode = mv88e6352_port_get_cmode, 3574 .port_setup_message_port = mv88e6xxx_setup_message_port, 3575 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3576 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3577 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3578 .stats_get_strings = mv88e6095_stats_get_strings, 3579 .stats_get_stats = mv88e6095_stats_get_stats, 3580 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3581 .set_egress_port = mv88e6095_g1_set_egress_port, 3582 .watchdog_ops = &mv88e6097_watchdog_ops, 3583 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3584 .pot_clear = mv88e6xxx_g2_pot_clear, 3585 .reset = mv88e6352_g1_reset, 3586 .rmu_disable = mv88e6352_g1_rmu_disable, 3587 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3588 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3589 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3591 .serdes_get_lane = mv88e6352_serdes_get_lane, 3592 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3593 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3594 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3595 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3596 .serdes_power = mv88e6352_serdes_power, 3597 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3598 .serdes_get_regs = mv88e6352_serdes_get_regs, 3599 .gpio_ops = &mv88e6352_gpio_ops, 3600 .phylink_validate = mv88e6352_phylink_validate, 3601 }; 3602 3603 static const struct mv88e6xxx_ops mv88e6175_ops = { 3604 /* MV88E6XXX_FAMILY_6351 */ 3605 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3606 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3607 .irl_init_all = mv88e6352_g2_irl_init_all, 3608 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3609 .phy_read = mv88e6xxx_g2_smi_phy_read, 3610 .phy_write = mv88e6xxx_g2_smi_phy_write, 3611 .port_set_link = mv88e6xxx_port_set_link, 3612 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3613 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3614 .port_tag_remap = mv88e6095_port_tag_remap, 3615 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3616 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3617 .port_set_ether_type = mv88e6351_port_set_ether_type, 3618 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3619 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3620 .port_pause_limit = mv88e6097_port_pause_limit, 3621 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3622 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3623 .port_get_cmode = mv88e6352_port_get_cmode, 3624 .port_setup_message_port = mv88e6xxx_setup_message_port, 3625 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3626 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3627 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3628 .stats_get_strings = mv88e6095_stats_get_strings, 3629 .stats_get_stats = mv88e6095_stats_get_stats, 3630 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3631 .set_egress_port = mv88e6095_g1_set_egress_port, 3632 .watchdog_ops = &mv88e6097_watchdog_ops, 3633 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3634 .pot_clear = mv88e6xxx_g2_pot_clear, 3635 .reset = mv88e6352_g1_reset, 3636 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3637 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3638 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3639 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3640 .phylink_validate = mv88e6185_phylink_validate, 3641 }; 3642 3643 static const struct mv88e6xxx_ops mv88e6176_ops = { 3644 /* MV88E6XXX_FAMILY_6352 */ 3645 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3646 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3647 .irl_init_all = mv88e6352_g2_irl_init_all, 3648 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3649 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3650 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3651 .phy_read = mv88e6xxx_g2_smi_phy_read, 3652 .phy_write = mv88e6xxx_g2_smi_phy_write, 3653 .port_set_link = mv88e6xxx_port_set_link, 3654 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3655 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3656 .port_tag_remap = mv88e6095_port_tag_remap, 3657 .port_set_policy = mv88e6352_port_set_policy, 3658 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3659 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3660 .port_set_ether_type = mv88e6351_port_set_ether_type, 3661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3663 .port_pause_limit = mv88e6097_port_pause_limit, 3664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3666 .port_get_cmode = mv88e6352_port_get_cmode, 3667 .port_setup_message_port = mv88e6xxx_setup_message_port, 3668 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3669 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3670 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3671 .stats_get_strings = mv88e6095_stats_get_strings, 3672 .stats_get_stats = mv88e6095_stats_get_stats, 3673 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3674 .set_egress_port = mv88e6095_g1_set_egress_port, 3675 .watchdog_ops = &mv88e6097_watchdog_ops, 3676 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3677 .pot_clear = mv88e6xxx_g2_pot_clear, 3678 .reset = mv88e6352_g1_reset, 3679 .rmu_disable = mv88e6352_g1_rmu_disable, 3680 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3681 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3682 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3683 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3684 .serdes_get_lane = mv88e6352_serdes_get_lane, 3685 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3686 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3687 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3688 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3689 .serdes_power = mv88e6352_serdes_power, 3690 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3691 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3692 .serdes_irq_status = mv88e6352_serdes_irq_status, 3693 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3694 .serdes_get_regs = mv88e6352_serdes_get_regs, 3695 .gpio_ops = &mv88e6352_gpio_ops, 3696 .phylink_validate = mv88e6352_phylink_validate, 3697 }; 3698 3699 static const struct mv88e6xxx_ops mv88e6185_ops = { 3700 /* MV88E6XXX_FAMILY_6185 */ 3701 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3702 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3703 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3704 .phy_read = mv88e6185_phy_ppu_read, 3705 .phy_write = mv88e6185_phy_ppu_write, 3706 .port_set_link = mv88e6xxx_port_set_link, 3707 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3708 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3709 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3710 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3711 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3712 .port_set_pause = mv88e6185_port_set_pause, 3713 .port_get_cmode = mv88e6185_port_get_cmode, 3714 .port_setup_message_port = mv88e6xxx_setup_message_port, 3715 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3716 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3717 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3718 .stats_get_strings = mv88e6095_stats_get_strings, 3719 .stats_get_stats = mv88e6095_stats_get_stats, 3720 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3721 .set_egress_port = mv88e6095_g1_set_egress_port, 3722 .watchdog_ops = &mv88e6097_watchdog_ops, 3723 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3724 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3725 .ppu_enable = mv88e6185_g1_ppu_enable, 3726 .ppu_disable = mv88e6185_g1_ppu_disable, 3727 .reset = mv88e6185_g1_reset, 3728 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3729 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3730 .phylink_validate = mv88e6185_phylink_validate, 3731 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3732 }; 3733 3734 static const struct mv88e6xxx_ops mv88e6190_ops = { 3735 /* MV88E6XXX_FAMILY_6390 */ 3736 .setup_errata = mv88e6390_setup_errata, 3737 .irl_init_all = mv88e6390_g2_irl_init_all, 3738 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3739 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3740 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3741 .phy_read = mv88e6xxx_g2_smi_phy_read, 3742 .phy_write = mv88e6xxx_g2_smi_phy_write, 3743 .port_set_link = mv88e6xxx_port_set_link, 3744 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3745 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3746 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3747 .port_tag_remap = mv88e6390_port_tag_remap, 3748 .port_set_policy = mv88e6352_port_set_policy, 3749 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3750 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3751 .port_set_ether_type = mv88e6351_port_set_ether_type, 3752 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3753 .port_pause_limit = mv88e6390_port_pause_limit, 3754 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3755 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3756 .port_get_cmode = mv88e6352_port_get_cmode, 3757 .port_set_cmode = mv88e6390_port_set_cmode, 3758 .port_setup_message_port = mv88e6xxx_setup_message_port, 3759 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3760 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3761 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3762 .stats_get_strings = mv88e6320_stats_get_strings, 3763 .stats_get_stats = mv88e6390_stats_get_stats, 3764 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3765 .set_egress_port = mv88e6390_g1_set_egress_port, 3766 .watchdog_ops = &mv88e6390_watchdog_ops, 3767 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3768 .pot_clear = mv88e6xxx_g2_pot_clear, 3769 .reset = mv88e6352_g1_reset, 3770 .rmu_disable = mv88e6390_g1_rmu_disable, 3771 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3772 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3773 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3774 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3775 .serdes_power = mv88e6390_serdes_power, 3776 .serdes_get_lane = mv88e6390_serdes_get_lane, 3777 /* Check status register pause & lpa register */ 3778 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3779 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3780 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3781 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3782 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3783 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3784 .serdes_irq_status = mv88e6390_serdes_irq_status, 3785 .serdes_get_strings = mv88e6390_serdes_get_strings, 3786 .serdes_get_stats = mv88e6390_serdes_get_stats, 3787 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3788 .serdes_get_regs = mv88e6390_serdes_get_regs, 3789 .gpio_ops = &mv88e6352_gpio_ops, 3790 .phylink_validate = mv88e6390_phylink_validate, 3791 }; 3792 3793 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3794 /* MV88E6XXX_FAMILY_6390 */ 3795 .setup_errata = mv88e6390_setup_errata, 3796 .irl_init_all = mv88e6390_g2_irl_init_all, 3797 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3798 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3799 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3800 .phy_read = mv88e6xxx_g2_smi_phy_read, 3801 .phy_write = mv88e6xxx_g2_smi_phy_write, 3802 .port_set_link = mv88e6xxx_port_set_link, 3803 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3804 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3805 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3806 .port_tag_remap = mv88e6390_port_tag_remap, 3807 .port_set_policy = mv88e6352_port_set_policy, 3808 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3809 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3810 .port_set_ether_type = mv88e6351_port_set_ether_type, 3811 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3812 .port_pause_limit = mv88e6390_port_pause_limit, 3813 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3814 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3815 .port_get_cmode = mv88e6352_port_get_cmode, 3816 .port_set_cmode = mv88e6390x_port_set_cmode, 3817 .port_setup_message_port = mv88e6xxx_setup_message_port, 3818 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3819 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3820 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3821 .stats_get_strings = mv88e6320_stats_get_strings, 3822 .stats_get_stats = mv88e6390_stats_get_stats, 3823 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3824 .set_egress_port = mv88e6390_g1_set_egress_port, 3825 .watchdog_ops = &mv88e6390_watchdog_ops, 3826 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3827 .pot_clear = mv88e6xxx_g2_pot_clear, 3828 .reset = mv88e6352_g1_reset, 3829 .rmu_disable = mv88e6390_g1_rmu_disable, 3830 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3831 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3832 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3833 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3834 .serdes_power = mv88e6390_serdes_power, 3835 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3836 /* Check status register pause & lpa register */ 3837 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3838 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3839 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3840 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3841 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3842 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3843 .serdes_irq_status = mv88e6390_serdes_irq_status, 3844 .serdes_get_strings = mv88e6390_serdes_get_strings, 3845 .serdes_get_stats = mv88e6390_serdes_get_stats, 3846 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3847 .serdes_get_regs = mv88e6390_serdes_get_regs, 3848 .gpio_ops = &mv88e6352_gpio_ops, 3849 .phylink_validate = mv88e6390x_phylink_validate, 3850 }; 3851 3852 static const struct mv88e6xxx_ops mv88e6191_ops = { 3853 /* MV88E6XXX_FAMILY_6390 */ 3854 .setup_errata = mv88e6390_setup_errata, 3855 .irl_init_all = mv88e6390_g2_irl_init_all, 3856 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3857 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3858 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3859 .phy_read = mv88e6xxx_g2_smi_phy_read, 3860 .phy_write = mv88e6xxx_g2_smi_phy_write, 3861 .port_set_link = mv88e6xxx_port_set_link, 3862 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3863 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3864 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3865 .port_tag_remap = mv88e6390_port_tag_remap, 3866 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3867 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3868 .port_set_ether_type = mv88e6351_port_set_ether_type, 3869 .port_pause_limit = mv88e6390_port_pause_limit, 3870 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3871 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3872 .port_get_cmode = mv88e6352_port_get_cmode, 3873 .port_set_cmode = mv88e6390_port_set_cmode, 3874 .port_setup_message_port = mv88e6xxx_setup_message_port, 3875 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3876 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3877 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3878 .stats_get_strings = mv88e6320_stats_get_strings, 3879 .stats_get_stats = mv88e6390_stats_get_stats, 3880 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3881 .set_egress_port = mv88e6390_g1_set_egress_port, 3882 .watchdog_ops = &mv88e6390_watchdog_ops, 3883 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3884 .pot_clear = mv88e6xxx_g2_pot_clear, 3885 .reset = mv88e6352_g1_reset, 3886 .rmu_disable = mv88e6390_g1_rmu_disable, 3887 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3888 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3889 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3890 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3891 .serdes_power = mv88e6390_serdes_power, 3892 .serdes_get_lane = mv88e6390_serdes_get_lane, 3893 /* Check status register pause & lpa register */ 3894 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3895 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3896 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3897 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3898 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3899 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3900 .serdes_irq_status = mv88e6390_serdes_irq_status, 3901 .serdes_get_strings = mv88e6390_serdes_get_strings, 3902 .serdes_get_stats = mv88e6390_serdes_get_stats, 3903 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3904 .serdes_get_regs = mv88e6390_serdes_get_regs, 3905 .avb_ops = &mv88e6390_avb_ops, 3906 .ptp_ops = &mv88e6352_ptp_ops, 3907 .phylink_validate = mv88e6390_phylink_validate, 3908 }; 3909 3910 static const struct mv88e6xxx_ops mv88e6240_ops = { 3911 /* MV88E6XXX_FAMILY_6352 */ 3912 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3913 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3914 .irl_init_all = mv88e6352_g2_irl_init_all, 3915 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3916 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3917 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3918 .phy_read = mv88e6xxx_g2_smi_phy_read, 3919 .phy_write = mv88e6xxx_g2_smi_phy_write, 3920 .port_set_link = mv88e6xxx_port_set_link, 3921 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3922 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3923 .port_tag_remap = mv88e6095_port_tag_remap, 3924 .port_set_policy = mv88e6352_port_set_policy, 3925 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3926 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3927 .port_set_ether_type = mv88e6351_port_set_ether_type, 3928 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3929 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3930 .port_pause_limit = mv88e6097_port_pause_limit, 3931 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3932 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3933 .port_get_cmode = mv88e6352_port_get_cmode, 3934 .port_setup_message_port = mv88e6xxx_setup_message_port, 3935 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3936 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3937 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3938 .stats_get_strings = mv88e6095_stats_get_strings, 3939 .stats_get_stats = mv88e6095_stats_get_stats, 3940 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3941 .set_egress_port = mv88e6095_g1_set_egress_port, 3942 .watchdog_ops = &mv88e6097_watchdog_ops, 3943 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3944 .pot_clear = mv88e6xxx_g2_pot_clear, 3945 .reset = mv88e6352_g1_reset, 3946 .rmu_disable = mv88e6352_g1_rmu_disable, 3947 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3948 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3949 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3950 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3951 .serdes_get_lane = mv88e6352_serdes_get_lane, 3952 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3953 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3954 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3955 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3956 .serdes_power = mv88e6352_serdes_power, 3957 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3958 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3959 .serdes_irq_status = mv88e6352_serdes_irq_status, 3960 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3961 .serdes_get_regs = mv88e6352_serdes_get_regs, 3962 .gpio_ops = &mv88e6352_gpio_ops, 3963 .avb_ops = &mv88e6352_avb_ops, 3964 .ptp_ops = &mv88e6352_ptp_ops, 3965 .phylink_validate = mv88e6352_phylink_validate, 3966 }; 3967 3968 static const struct mv88e6xxx_ops mv88e6250_ops = { 3969 /* MV88E6XXX_FAMILY_6250 */ 3970 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 3971 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3972 .irl_init_all = mv88e6352_g2_irl_init_all, 3973 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3974 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3975 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3976 .phy_read = mv88e6xxx_g2_smi_phy_read, 3977 .phy_write = mv88e6xxx_g2_smi_phy_write, 3978 .port_set_link = mv88e6xxx_port_set_link, 3979 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3980 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 3981 .port_tag_remap = mv88e6095_port_tag_remap, 3982 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3983 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3984 .port_set_ether_type = mv88e6351_port_set_ether_type, 3985 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3986 .port_pause_limit = mv88e6097_port_pause_limit, 3987 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3988 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3989 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3990 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 3991 .stats_get_strings = mv88e6250_stats_get_strings, 3992 .stats_get_stats = mv88e6250_stats_get_stats, 3993 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3994 .set_egress_port = mv88e6095_g1_set_egress_port, 3995 .watchdog_ops = &mv88e6250_watchdog_ops, 3996 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3997 .pot_clear = mv88e6xxx_g2_pot_clear, 3998 .reset = mv88e6250_g1_reset, 3999 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4000 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4001 .avb_ops = &mv88e6352_avb_ops, 4002 .ptp_ops = &mv88e6250_ptp_ops, 4003 .phylink_validate = mv88e6065_phylink_validate, 4004 }; 4005 4006 static const struct mv88e6xxx_ops mv88e6290_ops = { 4007 /* MV88E6XXX_FAMILY_6390 */ 4008 .setup_errata = mv88e6390_setup_errata, 4009 .irl_init_all = mv88e6390_g2_irl_init_all, 4010 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4011 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4012 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4013 .phy_read = mv88e6xxx_g2_smi_phy_read, 4014 .phy_write = mv88e6xxx_g2_smi_phy_write, 4015 .port_set_link = mv88e6xxx_port_set_link, 4016 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4017 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4018 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4019 .port_tag_remap = mv88e6390_port_tag_remap, 4020 .port_set_policy = mv88e6352_port_set_policy, 4021 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4022 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4023 .port_set_ether_type = mv88e6351_port_set_ether_type, 4024 .port_pause_limit = mv88e6390_port_pause_limit, 4025 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4027 .port_get_cmode = mv88e6352_port_get_cmode, 4028 .port_set_cmode = mv88e6390_port_set_cmode, 4029 .port_setup_message_port = mv88e6xxx_setup_message_port, 4030 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4031 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4032 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4033 .stats_get_strings = mv88e6320_stats_get_strings, 4034 .stats_get_stats = mv88e6390_stats_get_stats, 4035 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4036 .set_egress_port = mv88e6390_g1_set_egress_port, 4037 .watchdog_ops = &mv88e6390_watchdog_ops, 4038 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4039 .pot_clear = mv88e6xxx_g2_pot_clear, 4040 .reset = mv88e6352_g1_reset, 4041 .rmu_disable = mv88e6390_g1_rmu_disable, 4042 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4043 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4044 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4045 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4046 .serdes_power = mv88e6390_serdes_power, 4047 .serdes_get_lane = mv88e6390_serdes_get_lane, 4048 /* Check status register pause & lpa register */ 4049 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4050 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4051 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4052 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4053 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4054 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4055 .serdes_irq_status = mv88e6390_serdes_irq_status, 4056 .serdes_get_strings = mv88e6390_serdes_get_strings, 4057 .serdes_get_stats = mv88e6390_serdes_get_stats, 4058 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4059 .serdes_get_regs = mv88e6390_serdes_get_regs, 4060 .gpio_ops = &mv88e6352_gpio_ops, 4061 .avb_ops = &mv88e6390_avb_ops, 4062 .ptp_ops = &mv88e6352_ptp_ops, 4063 .phylink_validate = mv88e6390_phylink_validate, 4064 }; 4065 4066 static const struct mv88e6xxx_ops mv88e6320_ops = { 4067 /* MV88E6XXX_FAMILY_6320 */ 4068 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4069 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4070 .irl_init_all = mv88e6352_g2_irl_init_all, 4071 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4072 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4073 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4074 .phy_read = mv88e6xxx_g2_smi_phy_read, 4075 .phy_write = mv88e6xxx_g2_smi_phy_write, 4076 .port_set_link = mv88e6xxx_port_set_link, 4077 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4078 .port_tag_remap = mv88e6095_port_tag_remap, 4079 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4080 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4081 .port_set_ether_type = mv88e6351_port_set_ether_type, 4082 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4083 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4084 .port_pause_limit = mv88e6097_port_pause_limit, 4085 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4086 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4087 .port_get_cmode = mv88e6352_port_get_cmode, 4088 .port_setup_message_port = mv88e6xxx_setup_message_port, 4089 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4090 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4091 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4092 .stats_get_strings = mv88e6320_stats_get_strings, 4093 .stats_get_stats = mv88e6320_stats_get_stats, 4094 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4095 .set_egress_port = mv88e6095_g1_set_egress_port, 4096 .watchdog_ops = &mv88e6390_watchdog_ops, 4097 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4098 .pot_clear = mv88e6xxx_g2_pot_clear, 4099 .reset = mv88e6352_g1_reset, 4100 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4101 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4102 .gpio_ops = &mv88e6352_gpio_ops, 4103 .avb_ops = &mv88e6352_avb_ops, 4104 .ptp_ops = &mv88e6352_ptp_ops, 4105 .phylink_validate = mv88e6185_phylink_validate, 4106 }; 4107 4108 static const struct mv88e6xxx_ops mv88e6321_ops = { 4109 /* MV88E6XXX_FAMILY_6320 */ 4110 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4111 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4112 .irl_init_all = mv88e6352_g2_irl_init_all, 4113 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4114 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4115 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4116 .phy_read = mv88e6xxx_g2_smi_phy_read, 4117 .phy_write = mv88e6xxx_g2_smi_phy_write, 4118 .port_set_link = mv88e6xxx_port_set_link, 4119 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4120 .port_tag_remap = mv88e6095_port_tag_remap, 4121 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4122 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4123 .port_set_ether_type = mv88e6351_port_set_ether_type, 4124 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4125 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4126 .port_pause_limit = mv88e6097_port_pause_limit, 4127 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4128 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4129 .port_get_cmode = mv88e6352_port_get_cmode, 4130 .port_setup_message_port = mv88e6xxx_setup_message_port, 4131 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4132 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4133 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4134 .stats_get_strings = mv88e6320_stats_get_strings, 4135 .stats_get_stats = mv88e6320_stats_get_stats, 4136 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4137 .set_egress_port = mv88e6095_g1_set_egress_port, 4138 .watchdog_ops = &mv88e6390_watchdog_ops, 4139 .reset = mv88e6352_g1_reset, 4140 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4141 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4142 .gpio_ops = &mv88e6352_gpio_ops, 4143 .avb_ops = &mv88e6352_avb_ops, 4144 .ptp_ops = &mv88e6352_ptp_ops, 4145 .phylink_validate = mv88e6185_phylink_validate, 4146 }; 4147 4148 static const struct mv88e6xxx_ops mv88e6341_ops = { 4149 /* MV88E6XXX_FAMILY_6341 */ 4150 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4151 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4152 .irl_init_all = mv88e6352_g2_irl_init_all, 4153 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4154 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4155 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4156 .phy_read = mv88e6xxx_g2_smi_phy_read, 4157 .phy_write = mv88e6xxx_g2_smi_phy_write, 4158 .port_set_link = mv88e6xxx_port_set_link, 4159 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4160 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4161 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4162 .port_tag_remap = mv88e6095_port_tag_remap, 4163 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4164 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4165 .port_set_ether_type = mv88e6351_port_set_ether_type, 4166 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4167 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4168 .port_pause_limit = mv88e6097_port_pause_limit, 4169 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4170 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4171 .port_get_cmode = mv88e6352_port_get_cmode, 4172 .port_set_cmode = mv88e6341_port_set_cmode, 4173 .port_setup_message_port = mv88e6xxx_setup_message_port, 4174 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4175 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4176 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4177 .stats_get_strings = mv88e6320_stats_get_strings, 4178 .stats_get_stats = mv88e6390_stats_get_stats, 4179 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4180 .set_egress_port = mv88e6390_g1_set_egress_port, 4181 .watchdog_ops = &mv88e6390_watchdog_ops, 4182 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4183 .pot_clear = mv88e6xxx_g2_pot_clear, 4184 .reset = mv88e6352_g1_reset, 4185 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4186 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4187 .serdes_power = mv88e6390_serdes_power, 4188 .serdes_get_lane = mv88e6341_serdes_get_lane, 4189 /* Check status register pause & lpa register */ 4190 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4191 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4192 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4193 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4194 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4195 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4196 .serdes_irq_status = mv88e6390_serdes_irq_status, 4197 .gpio_ops = &mv88e6352_gpio_ops, 4198 .avb_ops = &mv88e6390_avb_ops, 4199 .ptp_ops = &mv88e6352_ptp_ops, 4200 .phylink_validate = mv88e6341_phylink_validate, 4201 }; 4202 4203 static const struct mv88e6xxx_ops mv88e6350_ops = { 4204 /* MV88E6XXX_FAMILY_6351 */ 4205 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4206 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4207 .irl_init_all = mv88e6352_g2_irl_init_all, 4208 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4209 .phy_read = mv88e6xxx_g2_smi_phy_read, 4210 .phy_write = mv88e6xxx_g2_smi_phy_write, 4211 .port_set_link = mv88e6xxx_port_set_link, 4212 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4213 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4214 .port_tag_remap = mv88e6095_port_tag_remap, 4215 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4216 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4217 .port_set_ether_type = mv88e6351_port_set_ether_type, 4218 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4219 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4220 .port_pause_limit = mv88e6097_port_pause_limit, 4221 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4222 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4223 .port_get_cmode = mv88e6352_port_get_cmode, 4224 .port_setup_message_port = mv88e6xxx_setup_message_port, 4225 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4226 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4227 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4228 .stats_get_strings = mv88e6095_stats_get_strings, 4229 .stats_get_stats = mv88e6095_stats_get_stats, 4230 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4231 .set_egress_port = mv88e6095_g1_set_egress_port, 4232 .watchdog_ops = &mv88e6097_watchdog_ops, 4233 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4234 .pot_clear = mv88e6xxx_g2_pot_clear, 4235 .reset = mv88e6352_g1_reset, 4236 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4237 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4238 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4239 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4240 .phylink_validate = mv88e6185_phylink_validate, 4241 }; 4242 4243 static const struct mv88e6xxx_ops mv88e6351_ops = { 4244 /* MV88E6XXX_FAMILY_6351 */ 4245 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4246 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4247 .irl_init_all = mv88e6352_g2_irl_init_all, 4248 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4249 .phy_read = mv88e6xxx_g2_smi_phy_read, 4250 .phy_write = mv88e6xxx_g2_smi_phy_write, 4251 .port_set_link = mv88e6xxx_port_set_link, 4252 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4253 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4254 .port_tag_remap = mv88e6095_port_tag_remap, 4255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4256 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4257 .port_set_ether_type = mv88e6351_port_set_ether_type, 4258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4260 .port_pause_limit = mv88e6097_port_pause_limit, 4261 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4262 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4263 .port_get_cmode = mv88e6352_port_get_cmode, 4264 .port_setup_message_port = mv88e6xxx_setup_message_port, 4265 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4266 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4267 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4268 .stats_get_strings = mv88e6095_stats_get_strings, 4269 .stats_get_stats = mv88e6095_stats_get_stats, 4270 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4271 .set_egress_port = mv88e6095_g1_set_egress_port, 4272 .watchdog_ops = &mv88e6097_watchdog_ops, 4273 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4274 .pot_clear = mv88e6xxx_g2_pot_clear, 4275 .reset = mv88e6352_g1_reset, 4276 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4277 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4278 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4279 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4280 .avb_ops = &mv88e6352_avb_ops, 4281 .ptp_ops = &mv88e6352_ptp_ops, 4282 .phylink_validate = mv88e6185_phylink_validate, 4283 }; 4284 4285 static const struct mv88e6xxx_ops mv88e6352_ops = { 4286 /* MV88E6XXX_FAMILY_6352 */ 4287 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4288 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4289 .irl_init_all = mv88e6352_g2_irl_init_all, 4290 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4291 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4293 .phy_read = mv88e6xxx_g2_smi_phy_read, 4294 .phy_write = mv88e6xxx_g2_smi_phy_write, 4295 .port_set_link = mv88e6xxx_port_set_link, 4296 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4297 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4298 .port_tag_remap = mv88e6095_port_tag_remap, 4299 .port_set_policy = mv88e6352_port_set_policy, 4300 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4301 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4302 .port_set_ether_type = mv88e6351_port_set_ether_type, 4303 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4304 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4305 .port_pause_limit = mv88e6097_port_pause_limit, 4306 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4307 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4308 .port_get_cmode = mv88e6352_port_get_cmode, 4309 .port_setup_message_port = mv88e6xxx_setup_message_port, 4310 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4311 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4312 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4313 .stats_get_strings = mv88e6095_stats_get_strings, 4314 .stats_get_stats = mv88e6095_stats_get_stats, 4315 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4316 .set_egress_port = mv88e6095_g1_set_egress_port, 4317 .watchdog_ops = &mv88e6097_watchdog_ops, 4318 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4319 .pot_clear = mv88e6xxx_g2_pot_clear, 4320 .reset = mv88e6352_g1_reset, 4321 .rmu_disable = mv88e6352_g1_rmu_disable, 4322 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4323 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4324 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4325 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4326 .serdes_get_lane = mv88e6352_serdes_get_lane, 4327 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4328 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4329 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4330 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4331 .serdes_power = mv88e6352_serdes_power, 4332 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4333 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4334 .serdes_irq_status = mv88e6352_serdes_irq_status, 4335 .gpio_ops = &mv88e6352_gpio_ops, 4336 .avb_ops = &mv88e6352_avb_ops, 4337 .ptp_ops = &mv88e6352_ptp_ops, 4338 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4339 .serdes_get_strings = mv88e6352_serdes_get_strings, 4340 .serdes_get_stats = mv88e6352_serdes_get_stats, 4341 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4342 .serdes_get_regs = mv88e6352_serdes_get_regs, 4343 .phylink_validate = mv88e6352_phylink_validate, 4344 }; 4345 4346 static const struct mv88e6xxx_ops mv88e6390_ops = { 4347 /* MV88E6XXX_FAMILY_6390 */ 4348 .setup_errata = mv88e6390_setup_errata, 4349 .irl_init_all = mv88e6390_g2_irl_init_all, 4350 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4351 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4352 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4353 .phy_read = mv88e6xxx_g2_smi_phy_read, 4354 .phy_write = mv88e6xxx_g2_smi_phy_write, 4355 .port_set_link = mv88e6xxx_port_set_link, 4356 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4357 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4358 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4359 .port_tag_remap = mv88e6390_port_tag_remap, 4360 .port_set_policy = mv88e6352_port_set_policy, 4361 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4362 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4363 .port_set_ether_type = mv88e6351_port_set_ether_type, 4364 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4365 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4366 .port_pause_limit = mv88e6390_port_pause_limit, 4367 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4368 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4369 .port_get_cmode = mv88e6352_port_get_cmode, 4370 .port_set_cmode = mv88e6390_port_set_cmode, 4371 .port_setup_message_port = mv88e6xxx_setup_message_port, 4372 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4373 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4374 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4375 .stats_get_strings = mv88e6320_stats_get_strings, 4376 .stats_get_stats = mv88e6390_stats_get_stats, 4377 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4378 .set_egress_port = mv88e6390_g1_set_egress_port, 4379 .watchdog_ops = &mv88e6390_watchdog_ops, 4380 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4381 .pot_clear = mv88e6xxx_g2_pot_clear, 4382 .reset = mv88e6352_g1_reset, 4383 .rmu_disable = mv88e6390_g1_rmu_disable, 4384 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4385 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4386 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4387 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4388 .serdes_power = mv88e6390_serdes_power, 4389 .serdes_get_lane = mv88e6390_serdes_get_lane, 4390 /* Check status register pause & lpa register */ 4391 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4392 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4393 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4394 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4395 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4396 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4397 .serdes_irq_status = mv88e6390_serdes_irq_status, 4398 .gpio_ops = &mv88e6352_gpio_ops, 4399 .avb_ops = &mv88e6390_avb_ops, 4400 .ptp_ops = &mv88e6352_ptp_ops, 4401 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4402 .serdes_get_strings = mv88e6390_serdes_get_strings, 4403 .serdes_get_stats = mv88e6390_serdes_get_stats, 4404 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4405 .serdes_get_regs = mv88e6390_serdes_get_regs, 4406 .phylink_validate = mv88e6390_phylink_validate, 4407 }; 4408 4409 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4410 /* MV88E6XXX_FAMILY_6390 */ 4411 .setup_errata = mv88e6390_setup_errata, 4412 .irl_init_all = mv88e6390_g2_irl_init_all, 4413 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4414 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4415 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4416 .phy_read = mv88e6xxx_g2_smi_phy_read, 4417 .phy_write = mv88e6xxx_g2_smi_phy_write, 4418 .port_set_link = mv88e6xxx_port_set_link, 4419 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4420 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4421 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4422 .port_tag_remap = mv88e6390_port_tag_remap, 4423 .port_set_policy = mv88e6352_port_set_policy, 4424 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4425 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4426 .port_set_ether_type = mv88e6351_port_set_ether_type, 4427 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4428 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4429 .port_pause_limit = mv88e6390_port_pause_limit, 4430 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4431 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4432 .port_get_cmode = mv88e6352_port_get_cmode, 4433 .port_set_cmode = mv88e6390x_port_set_cmode, 4434 .port_setup_message_port = mv88e6xxx_setup_message_port, 4435 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4436 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4437 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4438 .stats_get_strings = mv88e6320_stats_get_strings, 4439 .stats_get_stats = mv88e6390_stats_get_stats, 4440 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4441 .set_egress_port = mv88e6390_g1_set_egress_port, 4442 .watchdog_ops = &mv88e6390_watchdog_ops, 4443 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4444 .pot_clear = mv88e6xxx_g2_pot_clear, 4445 .reset = mv88e6352_g1_reset, 4446 .rmu_disable = mv88e6390_g1_rmu_disable, 4447 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4448 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4449 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4450 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4451 .serdes_power = mv88e6390_serdes_power, 4452 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4453 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4454 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4455 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4456 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4457 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4458 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4459 .serdes_irq_status = mv88e6390_serdes_irq_status, 4460 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4461 .serdes_get_strings = mv88e6390_serdes_get_strings, 4462 .serdes_get_stats = mv88e6390_serdes_get_stats, 4463 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4464 .serdes_get_regs = mv88e6390_serdes_get_regs, 4465 .gpio_ops = &mv88e6352_gpio_ops, 4466 .avb_ops = &mv88e6390_avb_ops, 4467 .ptp_ops = &mv88e6352_ptp_ops, 4468 .phylink_validate = mv88e6390x_phylink_validate, 4469 }; 4470 4471 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4472 [MV88E6085] = { 4473 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4474 .family = MV88E6XXX_FAMILY_6097, 4475 .name = "Marvell 88E6085", 4476 .num_databases = 4096, 4477 .num_macs = 8192, 4478 .num_ports = 10, 4479 .num_internal_phys = 5, 4480 .max_vid = 4095, 4481 .port_base_addr = 0x10, 4482 .phy_base_addr = 0x0, 4483 .global1_addr = 0x1b, 4484 .global2_addr = 0x1c, 4485 .age_time_coeff = 15000, 4486 .g1_irqs = 8, 4487 .g2_irqs = 10, 4488 .atu_move_port_mask = 0xf, 4489 .pvt = true, 4490 .multi_chip = true, 4491 .tag_protocol = DSA_TAG_PROTO_DSA, 4492 .ops = &mv88e6085_ops, 4493 }, 4494 4495 [MV88E6095] = { 4496 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4497 .family = MV88E6XXX_FAMILY_6095, 4498 .name = "Marvell 88E6095/88E6095F", 4499 .num_databases = 256, 4500 .num_macs = 8192, 4501 .num_ports = 11, 4502 .num_internal_phys = 0, 4503 .max_vid = 4095, 4504 .port_base_addr = 0x10, 4505 .phy_base_addr = 0x0, 4506 .global1_addr = 0x1b, 4507 .global2_addr = 0x1c, 4508 .age_time_coeff = 15000, 4509 .g1_irqs = 8, 4510 .atu_move_port_mask = 0xf, 4511 .multi_chip = true, 4512 .tag_protocol = DSA_TAG_PROTO_DSA, 4513 .ops = &mv88e6095_ops, 4514 }, 4515 4516 [MV88E6097] = { 4517 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4518 .family = MV88E6XXX_FAMILY_6097, 4519 .name = "Marvell 88E6097/88E6097F", 4520 .num_databases = 4096, 4521 .num_macs = 8192, 4522 .num_ports = 11, 4523 .num_internal_phys = 8, 4524 .max_vid = 4095, 4525 .port_base_addr = 0x10, 4526 .phy_base_addr = 0x0, 4527 .global1_addr = 0x1b, 4528 .global2_addr = 0x1c, 4529 .age_time_coeff = 15000, 4530 .g1_irqs = 8, 4531 .g2_irqs = 10, 4532 .atu_move_port_mask = 0xf, 4533 .pvt = true, 4534 .multi_chip = true, 4535 .tag_protocol = DSA_TAG_PROTO_EDSA, 4536 .ops = &mv88e6097_ops, 4537 }, 4538 4539 [MV88E6123] = { 4540 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4541 .family = MV88E6XXX_FAMILY_6165, 4542 .name = "Marvell 88E6123", 4543 .num_databases = 4096, 4544 .num_macs = 1024, 4545 .num_ports = 3, 4546 .num_internal_phys = 5, 4547 .max_vid = 4095, 4548 .port_base_addr = 0x10, 4549 .phy_base_addr = 0x0, 4550 .global1_addr = 0x1b, 4551 .global2_addr = 0x1c, 4552 .age_time_coeff = 15000, 4553 .g1_irqs = 9, 4554 .g2_irqs = 10, 4555 .atu_move_port_mask = 0xf, 4556 .pvt = true, 4557 .multi_chip = true, 4558 .tag_protocol = DSA_TAG_PROTO_EDSA, 4559 .ops = &mv88e6123_ops, 4560 }, 4561 4562 [MV88E6131] = { 4563 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4564 .family = MV88E6XXX_FAMILY_6185, 4565 .name = "Marvell 88E6131", 4566 .num_databases = 256, 4567 .num_macs = 8192, 4568 .num_ports = 8, 4569 .num_internal_phys = 0, 4570 .max_vid = 4095, 4571 .port_base_addr = 0x10, 4572 .phy_base_addr = 0x0, 4573 .global1_addr = 0x1b, 4574 .global2_addr = 0x1c, 4575 .age_time_coeff = 15000, 4576 .g1_irqs = 9, 4577 .atu_move_port_mask = 0xf, 4578 .multi_chip = true, 4579 .tag_protocol = DSA_TAG_PROTO_DSA, 4580 .ops = &mv88e6131_ops, 4581 }, 4582 4583 [MV88E6141] = { 4584 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4585 .family = MV88E6XXX_FAMILY_6341, 4586 .name = "Marvell 88E6141", 4587 .num_databases = 4096, 4588 .num_macs = 2048, 4589 .num_ports = 6, 4590 .num_internal_phys = 5, 4591 .num_gpio = 11, 4592 .max_vid = 4095, 4593 .port_base_addr = 0x10, 4594 .phy_base_addr = 0x10, 4595 .global1_addr = 0x1b, 4596 .global2_addr = 0x1c, 4597 .age_time_coeff = 3750, 4598 .atu_move_port_mask = 0x1f, 4599 .g1_irqs = 9, 4600 .g2_irqs = 10, 4601 .pvt = true, 4602 .multi_chip = true, 4603 .tag_protocol = DSA_TAG_PROTO_EDSA, 4604 .ops = &mv88e6141_ops, 4605 }, 4606 4607 [MV88E6161] = { 4608 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4609 .family = MV88E6XXX_FAMILY_6165, 4610 .name = "Marvell 88E6161", 4611 .num_databases = 4096, 4612 .num_macs = 1024, 4613 .num_ports = 6, 4614 .num_internal_phys = 5, 4615 .max_vid = 4095, 4616 .port_base_addr = 0x10, 4617 .phy_base_addr = 0x0, 4618 .global1_addr = 0x1b, 4619 .global2_addr = 0x1c, 4620 .age_time_coeff = 15000, 4621 .g1_irqs = 9, 4622 .g2_irqs = 10, 4623 .atu_move_port_mask = 0xf, 4624 .pvt = true, 4625 .multi_chip = true, 4626 .tag_protocol = DSA_TAG_PROTO_EDSA, 4627 .ptp_support = true, 4628 .ops = &mv88e6161_ops, 4629 }, 4630 4631 [MV88E6165] = { 4632 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4633 .family = MV88E6XXX_FAMILY_6165, 4634 .name = "Marvell 88E6165", 4635 .num_databases = 4096, 4636 .num_macs = 8192, 4637 .num_ports = 6, 4638 .num_internal_phys = 0, 4639 .max_vid = 4095, 4640 .port_base_addr = 0x10, 4641 .phy_base_addr = 0x0, 4642 .global1_addr = 0x1b, 4643 .global2_addr = 0x1c, 4644 .age_time_coeff = 15000, 4645 .g1_irqs = 9, 4646 .g2_irqs = 10, 4647 .atu_move_port_mask = 0xf, 4648 .pvt = true, 4649 .multi_chip = true, 4650 .tag_protocol = DSA_TAG_PROTO_DSA, 4651 .ptp_support = true, 4652 .ops = &mv88e6165_ops, 4653 }, 4654 4655 [MV88E6171] = { 4656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4657 .family = MV88E6XXX_FAMILY_6351, 4658 .name = "Marvell 88E6171", 4659 .num_databases = 4096, 4660 .num_macs = 8192, 4661 .num_ports = 7, 4662 .num_internal_phys = 5, 4663 .max_vid = 4095, 4664 .port_base_addr = 0x10, 4665 .phy_base_addr = 0x0, 4666 .global1_addr = 0x1b, 4667 .global2_addr = 0x1c, 4668 .age_time_coeff = 15000, 4669 .g1_irqs = 9, 4670 .g2_irqs = 10, 4671 .atu_move_port_mask = 0xf, 4672 .pvt = true, 4673 .multi_chip = true, 4674 .tag_protocol = DSA_TAG_PROTO_EDSA, 4675 .ops = &mv88e6171_ops, 4676 }, 4677 4678 [MV88E6172] = { 4679 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4680 .family = MV88E6XXX_FAMILY_6352, 4681 .name = "Marvell 88E6172", 4682 .num_databases = 4096, 4683 .num_macs = 8192, 4684 .num_ports = 7, 4685 .num_internal_phys = 5, 4686 .num_gpio = 15, 4687 .max_vid = 4095, 4688 .port_base_addr = 0x10, 4689 .phy_base_addr = 0x0, 4690 .global1_addr = 0x1b, 4691 .global2_addr = 0x1c, 4692 .age_time_coeff = 15000, 4693 .g1_irqs = 9, 4694 .g2_irqs = 10, 4695 .atu_move_port_mask = 0xf, 4696 .pvt = true, 4697 .multi_chip = true, 4698 .tag_protocol = DSA_TAG_PROTO_EDSA, 4699 .ops = &mv88e6172_ops, 4700 }, 4701 4702 [MV88E6175] = { 4703 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4704 .family = MV88E6XXX_FAMILY_6351, 4705 .name = "Marvell 88E6175", 4706 .num_databases = 4096, 4707 .num_macs = 8192, 4708 .num_ports = 7, 4709 .num_internal_phys = 5, 4710 .max_vid = 4095, 4711 .port_base_addr = 0x10, 4712 .phy_base_addr = 0x0, 4713 .global1_addr = 0x1b, 4714 .global2_addr = 0x1c, 4715 .age_time_coeff = 15000, 4716 .g1_irqs = 9, 4717 .g2_irqs = 10, 4718 .atu_move_port_mask = 0xf, 4719 .pvt = true, 4720 .multi_chip = true, 4721 .tag_protocol = DSA_TAG_PROTO_EDSA, 4722 .ops = &mv88e6175_ops, 4723 }, 4724 4725 [MV88E6176] = { 4726 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4727 .family = MV88E6XXX_FAMILY_6352, 4728 .name = "Marvell 88E6176", 4729 .num_databases = 4096, 4730 .num_macs = 8192, 4731 .num_ports = 7, 4732 .num_internal_phys = 5, 4733 .num_gpio = 15, 4734 .max_vid = 4095, 4735 .port_base_addr = 0x10, 4736 .phy_base_addr = 0x0, 4737 .global1_addr = 0x1b, 4738 .global2_addr = 0x1c, 4739 .age_time_coeff = 15000, 4740 .g1_irqs = 9, 4741 .g2_irqs = 10, 4742 .atu_move_port_mask = 0xf, 4743 .pvt = true, 4744 .multi_chip = true, 4745 .tag_protocol = DSA_TAG_PROTO_EDSA, 4746 .ops = &mv88e6176_ops, 4747 }, 4748 4749 [MV88E6185] = { 4750 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4751 .family = MV88E6XXX_FAMILY_6185, 4752 .name = "Marvell 88E6185", 4753 .num_databases = 256, 4754 .num_macs = 8192, 4755 .num_ports = 10, 4756 .num_internal_phys = 0, 4757 .max_vid = 4095, 4758 .port_base_addr = 0x10, 4759 .phy_base_addr = 0x0, 4760 .global1_addr = 0x1b, 4761 .global2_addr = 0x1c, 4762 .age_time_coeff = 15000, 4763 .g1_irqs = 8, 4764 .atu_move_port_mask = 0xf, 4765 .multi_chip = true, 4766 .tag_protocol = DSA_TAG_PROTO_EDSA, 4767 .ops = &mv88e6185_ops, 4768 }, 4769 4770 [MV88E6190] = { 4771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4772 .family = MV88E6XXX_FAMILY_6390, 4773 .name = "Marvell 88E6190", 4774 .num_databases = 4096, 4775 .num_macs = 16384, 4776 .num_ports = 11, /* 10 + Z80 */ 4777 .num_internal_phys = 9, 4778 .num_gpio = 16, 4779 .max_vid = 8191, 4780 .port_base_addr = 0x0, 4781 .phy_base_addr = 0x0, 4782 .global1_addr = 0x1b, 4783 .global2_addr = 0x1c, 4784 .tag_protocol = DSA_TAG_PROTO_DSA, 4785 .age_time_coeff = 3750, 4786 .g1_irqs = 9, 4787 .g2_irqs = 14, 4788 .pvt = true, 4789 .multi_chip = true, 4790 .atu_move_port_mask = 0x1f, 4791 .ops = &mv88e6190_ops, 4792 }, 4793 4794 [MV88E6190X] = { 4795 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4796 .family = MV88E6XXX_FAMILY_6390, 4797 .name = "Marvell 88E6190X", 4798 .num_databases = 4096, 4799 .num_macs = 16384, 4800 .num_ports = 11, /* 10 + Z80 */ 4801 .num_internal_phys = 9, 4802 .num_gpio = 16, 4803 .max_vid = 8191, 4804 .port_base_addr = 0x0, 4805 .phy_base_addr = 0x0, 4806 .global1_addr = 0x1b, 4807 .global2_addr = 0x1c, 4808 .age_time_coeff = 3750, 4809 .g1_irqs = 9, 4810 .g2_irqs = 14, 4811 .atu_move_port_mask = 0x1f, 4812 .pvt = true, 4813 .multi_chip = true, 4814 .tag_protocol = DSA_TAG_PROTO_DSA, 4815 .ops = &mv88e6190x_ops, 4816 }, 4817 4818 [MV88E6191] = { 4819 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4820 .family = MV88E6XXX_FAMILY_6390, 4821 .name = "Marvell 88E6191", 4822 .num_databases = 4096, 4823 .num_macs = 16384, 4824 .num_ports = 11, /* 10 + Z80 */ 4825 .num_internal_phys = 9, 4826 .max_vid = 8191, 4827 .port_base_addr = 0x0, 4828 .phy_base_addr = 0x0, 4829 .global1_addr = 0x1b, 4830 .global2_addr = 0x1c, 4831 .age_time_coeff = 3750, 4832 .g1_irqs = 9, 4833 .g2_irqs = 14, 4834 .atu_move_port_mask = 0x1f, 4835 .pvt = true, 4836 .multi_chip = true, 4837 .tag_protocol = DSA_TAG_PROTO_DSA, 4838 .ptp_support = true, 4839 .ops = &mv88e6191_ops, 4840 }, 4841 4842 [MV88E6220] = { 4843 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4844 .family = MV88E6XXX_FAMILY_6250, 4845 .name = "Marvell 88E6220", 4846 .num_databases = 64, 4847 4848 /* Ports 2-4 are not routed to pins 4849 * => usable ports 0, 1, 5, 6 4850 */ 4851 .num_ports = 7, 4852 .num_internal_phys = 2, 4853 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4854 .max_vid = 4095, 4855 .port_base_addr = 0x08, 4856 .phy_base_addr = 0x00, 4857 .global1_addr = 0x0f, 4858 .global2_addr = 0x07, 4859 .age_time_coeff = 15000, 4860 .g1_irqs = 9, 4861 .g2_irqs = 10, 4862 .atu_move_port_mask = 0xf, 4863 .dual_chip = true, 4864 .tag_protocol = DSA_TAG_PROTO_DSA, 4865 .ptp_support = true, 4866 .ops = &mv88e6250_ops, 4867 }, 4868 4869 [MV88E6240] = { 4870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4871 .family = MV88E6XXX_FAMILY_6352, 4872 .name = "Marvell 88E6240", 4873 .num_databases = 4096, 4874 .num_macs = 8192, 4875 .num_ports = 7, 4876 .num_internal_phys = 5, 4877 .num_gpio = 15, 4878 .max_vid = 4095, 4879 .port_base_addr = 0x10, 4880 .phy_base_addr = 0x0, 4881 .global1_addr = 0x1b, 4882 .global2_addr = 0x1c, 4883 .age_time_coeff = 15000, 4884 .g1_irqs = 9, 4885 .g2_irqs = 10, 4886 .atu_move_port_mask = 0xf, 4887 .pvt = true, 4888 .multi_chip = true, 4889 .tag_protocol = DSA_TAG_PROTO_EDSA, 4890 .ptp_support = true, 4891 .ops = &mv88e6240_ops, 4892 }, 4893 4894 [MV88E6250] = { 4895 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4896 .family = MV88E6XXX_FAMILY_6250, 4897 .name = "Marvell 88E6250", 4898 .num_databases = 64, 4899 .num_ports = 7, 4900 .num_internal_phys = 5, 4901 .max_vid = 4095, 4902 .port_base_addr = 0x08, 4903 .phy_base_addr = 0x00, 4904 .global1_addr = 0x0f, 4905 .global2_addr = 0x07, 4906 .age_time_coeff = 15000, 4907 .g1_irqs = 9, 4908 .g2_irqs = 10, 4909 .atu_move_port_mask = 0xf, 4910 .dual_chip = true, 4911 .tag_protocol = DSA_TAG_PROTO_DSA, 4912 .ptp_support = true, 4913 .ops = &mv88e6250_ops, 4914 }, 4915 4916 [MV88E6290] = { 4917 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4918 .family = MV88E6XXX_FAMILY_6390, 4919 .name = "Marvell 88E6290", 4920 .num_databases = 4096, 4921 .num_ports = 11, /* 10 + Z80 */ 4922 .num_internal_phys = 9, 4923 .num_gpio = 16, 4924 .max_vid = 8191, 4925 .port_base_addr = 0x0, 4926 .phy_base_addr = 0x0, 4927 .global1_addr = 0x1b, 4928 .global2_addr = 0x1c, 4929 .age_time_coeff = 3750, 4930 .g1_irqs = 9, 4931 .g2_irqs = 14, 4932 .atu_move_port_mask = 0x1f, 4933 .pvt = true, 4934 .multi_chip = true, 4935 .tag_protocol = DSA_TAG_PROTO_DSA, 4936 .ptp_support = true, 4937 .ops = &mv88e6290_ops, 4938 }, 4939 4940 [MV88E6320] = { 4941 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4942 .family = MV88E6XXX_FAMILY_6320, 4943 .name = "Marvell 88E6320", 4944 .num_databases = 4096, 4945 .num_macs = 8192, 4946 .num_ports = 7, 4947 .num_internal_phys = 5, 4948 .num_gpio = 15, 4949 .max_vid = 4095, 4950 .port_base_addr = 0x10, 4951 .phy_base_addr = 0x0, 4952 .global1_addr = 0x1b, 4953 .global2_addr = 0x1c, 4954 .age_time_coeff = 15000, 4955 .g1_irqs = 8, 4956 .g2_irqs = 10, 4957 .atu_move_port_mask = 0xf, 4958 .pvt = true, 4959 .multi_chip = true, 4960 .tag_protocol = DSA_TAG_PROTO_EDSA, 4961 .ptp_support = true, 4962 .ops = &mv88e6320_ops, 4963 }, 4964 4965 [MV88E6321] = { 4966 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4967 .family = MV88E6XXX_FAMILY_6320, 4968 .name = "Marvell 88E6321", 4969 .num_databases = 4096, 4970 .num_macs = 8192, 4971 .num_ports = 7, 4972 .num_internal_phys = 5, 4973 .num_gpio = 15, 4974 .max_vid = 4095, 4975 .port_base_addr = 0x10, 4976 .phy_base_addr = 0x0, 4977 .global1_addr = 0x1b, 4978 .global2_addr = 0x1c, 4979 .age_time_coeff = 15000, 4980 .g1_irqs = 8, 4981 .g2_irqs = 10, 4982 .atu_move_port_mask = 0xf, 4983 .multi_chip = true, 4984 .tag_protocol = DSA_TAG_PROTO_EDSA, 4985 .ptp_support = true, 4986 .ops = &mv88e6321_ops, 4987 }, 4988 4989 [MV88E6341] = { 4990 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4991 .family = MV88E6XXX_FAMILY_6341, 4992 .name = "Marvell 88E6341", 4993 .num_databases = 4096, 4994 .num_macs = 2048, 4995 .num_internal_phys = 5, 4996 .num_ports = 6, 4997 .num_gpio = 11, 4998 .max_vid = 4095, 4999 .port_base_addr = 0x10, 5000 .phy_base_addr = 0x10, 5001 .global1_addr = 0x1b, 5002 .global2_addr = 0x1c, 5003 .age_time_coeff = 3750, 5004 .atu_move_port_mask = 0x1f, 5005 .g1_irqs = 9, 5006 .g2_irqs = 10, 5007 .pvt = true, 5008 .multi_chip = true, 5009 .tag_protocol = DSA_TAG_PROTO_EDSA, 5010 .ptp_support = true, 5011 .ops = &mv88e6341_ops, 5012 }, 5013 5014 [MV88E6350] = { 5015 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5016 .family = MV88E6XXX_FAMILY_6351, 5017 .name = "Marvell 88E6350", 5018 .num_databases = 4096, 5019 .num_macs = 8192, 5020 .num_ports = 7, 5021 .num_internal_phys = 5, 5022 .max_vid = 4095, 5023 .port_base_addr = 0x10, 5024 .phy_base_addr = 0x0, 5025 .global1_addr = 0x1b, 5026 .global2_addr = 0x1c, 5027 .age_time_coeff = 15000, 5028 .g1_irqs = 9, 5029 .g2_irqs = 10, 5030 .atu_move_port_mask = 0xf, 5031 .pvt = true, 5032 .multi_chip = true, 5033 .tag_protocol = DSA_TAG_PROTO_EDSA, 5034 .ops = &mv88e6350_ops, 5035 }, 5036 5037 [MV88E6351] = { 5038 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5039 .family = MV88E6XXX_FAMILY_6351, 5040 .name = "Marvell 88E6351", 5041 .num_databases = 4096, 5042 .num_macs = 8192, 5043 .num_ports = 7, 5044 .num_internal_phys = 5, 5045 .max_vid = 4095, 5046 .port_base_addr = 0x10, 5047 .phy_base_addr = 0x0, 5048 .global1_addr = 0x1b, 5049 .global2_addr = 0x1c, 5050 .age_time_coeff = 15000, 5051 .g1_irqs = 9, 5052 .g2_irqs = 10, 5053 .atu_move_port_mask = 0xf, 5054 .pvt = true, 5055 .multi_chip = true, 5056 .tag_protocol = DSA_TAG_PROTO_EDSA, 5057 .ops = &mv88e6351_ops, 5058 }, 5059 5060 [MV88E6352] = { 5061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5062 .family = MV88E6XXX_FAMILY_6352, 5063 .name = "Marvell 88E6352", 5064 .num_databases = 4096, 5065 .num_macs = 8192, 5066 .num_ports = 7, 5067 .num_internal_phys = 5, 5068 .num_gpio = 15, 5069 .max_vid = 4095, 5070 .port_base_addr = 0x10, 5071 .phy_base_addr = 0x0, 5072 .global1_addr = 0x1b, 5073 .global2_addr = 0x1c, 5074 .age_time_coeff = 15000, 5075 .g1_irqs = 9, 5076 .g2_irqs = 10, 5077 .atu_move_port_mask = 0xf, 5078 .pvt = true, 5079 .multi_chip = true, 5080 .tag_protocol = DSA_TAG_PROTO_EDSA, 5081 .ptp_support = true, 5082 .ops = &mv88e6352_ops, 5083 }, 5084 [MV88E6390] = { 5085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5086 .family = MV88E6XXX_FAMILY_6390, 5087 .name = "Marvell 88E6390", 5088 .num_databases = 4096, 5089 .num_macs = 16384, 5090 .num_ports = 11, /* 10 + Z80 */ 5091 .num_internal_phys = 9, 5092 .num_gpio = 16, 5093 .max_vid = 8191, 5094 .port_base_addr = 0x0, 5095 .phy_base_addr = 0x0, 5096 .global1_addr = 0x1b, 5097 .global2_addr = 0x1c, 5098 .age_time_coeff = 3750, 5099 .g1_irqs = 9, 5100 .g2_irqs = 14, 5101 .atu_move_port_mask = 0x1f, 5102 .pvt = true, 5103 .multi_chip = true, 5104 .tag_protocol = DSA_TAG_PROTO_DSA, 5105 .ptp_support = true, 5106 .ops = &mv88e6390_ops, 5107 }, 5108 [MV88E6390X] = { 5109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5110 .family = MV88E6XXX_FAMILY_6390, 5111 .name = "Marvell 88E6390X", 5112 .num_databases = 4096, 5113 .num_macs = 16384, 5114 .num_ports = 11, /* 10 + Z80 */ 5115 .num_internal_phys = 9, 5116 .num_gpio = 16, 5117 .max_vid = 8191, 5118 .port_base_addr = 0x0, 5119 .phy_base_addr = 0x0, 5120 .global1_addr = 0x1b, 5121 .global2_addr = 0x1c, 5122 .age_time_coeff = 3750, 5123 .g1_irqs = 9, 5124 .g2_irqs = 14, 5125 .atu_move_port_mask = 0x1f, 5126 .pvt = true, 5127 .multi_chip = true, 5128 .tag_protocol = DSA_TAG_PROTO_DSA, 5129 .ptp_support = true, 5130 .ops = &mv88e6390x_ops, 5131 }, 5132 }; 5133 5134 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5135 { 5136 int i; 5137 5138 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5139 if (mv88e6xxx_table[i].prod_num == prod_num) 5140 return &mv88e6xxx_table[i]; 5141 5142 return NULL; 5143 } 5144 5145 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5146 { 5147 const struct mv88e6xxx_info *info; 5148 unsigned int prod_num, rev; 5149 u16 id; 5150 int err; 5151 5152 mv88e6xxx_reg_lock(chip); 5153 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5154 mv88e6xxx_reg_unlock(chip); 5155 if (err) 5156 return err; 5157 5158 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5159 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5160 5161 info = mv88e6xxx_lookup_info(prod_num); 5162 if (!info) 5163 return -ENODEV; 5164 5165 /* Update the compatible info with the probed one */ 5166 chip->info = info; 5167 5168 err = mv88e6xxx_g2_require(chip); 5169 if (err) 5170 return err; 5171 5172 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5173 chip->info->prod_num, chip->info->name, rev); 5174 5175 return 0; 5176 } 5177 5178 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5179 { 5180 struct mv88e6xxx_chip *chip; 5181 5182 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5183 if (!chip) 5184 return NULL; 5185 5186 chip->dev = dev; 5187 5188 mutex_init(&chip->reg_lock); 5189 INIT_LIST_HEAD(&chip->mdios); 5190 idr_init(&chip->policies); 5191 5192 return chip; 5193 } 5194 5195 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5196 int port, 5197 enum dsa_tag_protocol m) 5198 { 5199 struct mv88e6xxx_chip *chip = ds->priv; 5200 5201 return chip->info->tag_protocol; 5202 } 5203 5204 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5205 const struct switchdev_obj_port_mdb *mdb) 5206 { 5207 /* We don't need any dynamic resource from the kernel (yet), 5208 * so skip the prepare phase. 5209 */ 5210 5211 return 0; 5212 } 5213 5214 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5215 const struct switchdev_obj_port_mdb *mdb) 5216 { 5217 struct mv88e6xxx_chip *chip = ds->priv; 5218 5219 mv88e6xxx_reg_lock(chip); 5220 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5221 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5222 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5223 port); 5224 mv88e6xxx_reg_unlock(chip); 5225 } 5226 5227 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5228 const struct switchdev_obj_port_mdb *mdb) 5229 { 5230 struct mv88e6xxx_chip *chip = ds->priv; 5231 int err; 5232 5233 mv88e6xxx_reg_lock(chip); 5234 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5235 mv88e6xxx_reg_unlock(chip); 5236 5237 return err; 5238 } 5239 5240 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5241 struct dsa_mall_mirror_tc_entry *mirror, 5242 bool ingress) 5243 { 5244 enum mv88e6xxx_egress_direction direction = ingress ? 5245 MV88E6XXX_EGRESS_DIR_INGRESS : 5246 MV88E6XXX_EGRESS_DIR_EGRESS; 5247 struct mv88e6xxx_chip *chip = ds->priv; 5248 bool other_mirrors = false; 5249 int i; 5250 int err; 5251 5252 if (!chip->info->ops->set_egress_port) 5253 return -EOPNOTSUPP; 5254 5255 mutex_lock(&chip->reg_lock); 5256 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5257 mirror->to_local_port) { 5258 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5259 other_mirrors |= ingress ? 5260 chip->ports[i].mirror_ingress : 5261 chip->ports[i].mirror_egress; 5262 5263 /* Can't change egress port when other mirror is active */ 5264 if (other_mirrors) { 5265 err = -EBUSY; 5266 goto out; 5267 } 5268 5269 err = chip->info->ops->set_egress_port(chip, 5270 direction, 5271 mirror->to_local_port); 5272 if (err) 5273 goto out; 5274 } 5275 5276 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5277 out: 5278 mutex_unlock(&chip->reg_lock); 5279 5280 return err; 5281 } 5282 5283 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5284 struct dsa_mall_mirror_tc_entry *mirror) 5285 { 5286 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5287 MV88E6XXX_EGRESS_DIR_INGRESS : 5288 MV88E6XXX_EGRESS_DIR_EGRESS; 5289 struct mv88e6xxx_chip *chip = ds->priv; 5290 bool other_mirrors = false; 5291 int i; 5292 5293 mutex_lock(&chip->reg_lock); 5294 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5295 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5296 5297 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5298 other_mirrors |= mirror->ingress ? 5299 chip->ports[i].mirror_ingress : 5300 chip->ports[i].mirror_egress; 5301 5302 /* Reset egress port when no other mirror is active */ 5303 if (!other_mirrors) { 5304 if (chip->info->ops->set_egress_port(chip, 5305 direction, 5306 dsa_upstream_port(ds, 5307 port))) 5308 dev_err(ds->dev, "failed to set egress port\n"); 5309 } 5310 5311 mutex_unlock(&chip->reg_lock); 5312 } 5313 5314 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5315 bool unicast, bool multicast) 5316 { 5317 struct mv88e6xxx_chip *chip = ds->priv; 5318 int err = -EOPNOTSUPP; 5319 5320 mv88e6xxx_reg_lock(chip); 5321 if (chip->info->ops->port_set_egress_floods) 5322 err = chip->info->ops->port_set_egress_floods(chip, port, 5323 unicast, 5324 multicast); 5325 mv88e6xxx_reg_unlock(chip); 5326 5327 return err; 5328 } 5329 5330 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5331 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5332 .setup = mv88e6xxx_setup, 5333 .teardown = mv88e6xxx_teardown, 5334 .phylink_validate = mv88e6xxx_validate, 5335 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5336 .phylink_mac_config = mv88e6xxx_mac_config, 5337 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5338 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5339 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5340 .get_strings = mv88e6xxx_get_strings, 5341 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5342 .get_sset_count = mv88e6xxx_get_sset_count, 5343 .port_enable = mv88e6xxx_port_enable, 5344 .port_disable = mv88e6xxx_port_disable, 5345 .port_max_mtu = mv88e6xxx_get_max_mtu, 5346 .port_change_mtu = mv88e6xxx_change_mtu, 5347 .get_mac_eee = mv88e6xxx_get_mac_eee, 5348 .set_mac_eee = mv88e6xxx_set_mac_eee, 5349 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5350 .get_eeprom = mv88e6xxx_get_eeprom, 5351 .set_eeprom = mv88e6xxx_set_eeprom, 5352 .get_regs_len = mv88e6xxx_get_regs_len, 5353 .get_regs = mv88e6xxx_get_regs, 5354 .get_rxnfc = mv88e6xxx_get_rxnfc, 5355 .set_rxnfc = mv88e6xxx_set_rxnfc, 5356 .set_ageing_time = mv88e6xxx_set_ageing_time, 5357 .port_bridge_join = mv88e6xxx_port_bridge_join, 5358 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5359 .port_egress_floods = mv88e6xxx_port_egress_floods, 5360 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5361 .port_fast_age = mv88e6xxx_port_fast_age, 5362 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5363 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5364 .port_vlan_add = mv88e6xxx_port_vlan_add, 5365 .port_vlan_del = mv88e6xxx_port_vlan_del, 5366 .port_fdb_add = mv88e6xxx_port_fdb_add, 5367 .port_fdb_del = mv88e6xxx_port_fdb_del, 5368 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5369 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5370 .port_mdb_add = mv88e6xxx_port_mdb_add, 5371 .port_mdb_del = mv88e6xxx_port_mdb_del, 5372 .port_mirror_add = mv88e6xxx_port_mirror_add, 5373 .port_mirror_del = mv88e6xxx_port_mirror_del, 5374 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5375 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5376 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5377 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5378 .port_txtstamp = mv88e6xxx_port_txtstamp, 5379 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5380 .get_ts_info = mv88e6xxx_get_ts_info, 5381 .devlink_param_get = mv88e6xxx_devlink_param_get, 5382 .devlink_param_set = mv88e6xxx_devlink_param_set, 5383 .devlink_info_get = mv88e6xxx_devlink_info_get, 5384 }; 5385 5386 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5387 { 5388 struct device *dev = chip->dev; 5389 struct dsa_switch *ds; 5390 5391 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5392 if (!ds) 5393 return -ENOMEM; 5394 5395 ds->dev = dev; 5396 ds->num_ports = mv88e6xxx_num_ports(chip); 5397 ds->priv = chip; 5398 ds->dev = dev; 5399 ds->ops = &mv88e6xxx_switch_ops; 5400 ds->ageing_time_min = chip->info->age_time_coeff; 5401 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5402 5403 dev_set_drvdata(dev, ds); 5404 5405 return dsa_register_switch(ds); 5406 } 5407 5408 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5409 { 5410 dsa_unregister_switch(chip->ds); 5411 } 5412 5413 static const void *pdata_device_get_match_data(struct device *dev) 5414 { 5415 const struct of_device_id *matches = dev->driver->of_match_table; 5416 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5417 5418 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5419 matches++) { 5420 if (!strcmp(pdata->compatible, matches->compatible)) 5421 return matches->data; 5422 } 5423 return NULL; 5424 } 5425 5426 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5427 * would be lost after a power cycle so prevent it to be suspended. 5428 */ 5429 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5430 { 5431 return -EOPNOTSUPP; 5432 } 5433 5434 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5435 { 5436 return 0; 5437 } 5438 5439 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5440 5441 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5442 { 5443 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5444 const struct mv88e6xxx_info *compat_info = NULL; 5445 struct device *dev = &mdiodev->dev; 5446 struct device_node *np = dev->of_node; 5447 struct mv88e6xxx_chip *chip; 5448 int port; 5449 int err; 5450 5451 if (!np && !pdata) 5452 return -EINVAL; 5453 5454 if (np) 5455 compat_info = of_device_get_match_data(dev); 5456 5457 if (pdata) { 5458 compat_info = pdata_device_get_match_data(dev); 5459 5460 if (!pdata->netdev) 5461 return -EINVAL; 5462 5463 for (port = 0; port < DSA_MAX_PORTS; port++) { 5464 if (!(pdata->enabled_ports & (1 << port))) 5465 continue; 5466 if (strcmp(pdata->cd.port_names[port], "cpu")) 5467 continue; 5468 pdata->cd.netdev[port] = &pdata->netdev->dev; 5469 break; 5470 } 5471 } 5472 5473 if (!compat_info) 5474 return -EINVAL; 5475 5476 chip = mv88e6xxx_alloc_chip(dev); 5477 if (!chip) { 5478 err = -ENOMEM; 5479 goto out; 5480 } 5481 5482 chip->info = compat_info; 5483 5484 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5485 if (err) 5486 goto out; 5487 5488 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5489 if (IS_ERR(chip->reset)) { 5490 err = PTR_ERR(chip->reset); 5491 goto out; 5492 } 5493 if (chip->reset) 5494 usleep_range(1000, 2000); 5495 5496 err = mv88e6xxx_detect(chip); 5497 if (err) 5498 goto out; 5499 5500 mv88e6xxx_phy_init(chip); 5501 5502 if (chip->info->ops->get_eeprom) { 5503 if (np) 5504 of_property_read_u32(np, "eeprom-length", 5505 &chip->eeprom_len); 5506 else 5507 chip->eeprom_len = pdata->eeprom_len; 5508 } 5509 5510 mv88e6xxx_reg_lock(chip); 5511 err = mv88e6xxx_switch_reset(chip); 5512 mv88e6xxx_reg_unlock(chip); 5513 if (err) 5514 goto out; 5515 5516 if (np) { 5517 chip->irq = of_irq_get(np, 0); 5518 if (chip->irq == -EPROBE_DEFER) { 5519 err = chip->irq; 5520 goto out; 5521 } 5522 } 5523 5524 if (pdata) 5525 chip->irq = pdata->irq; 5526 5527 /* Has to be performed before the MDIO bus is created, because 5528 * the PHYs will link their interrupts to these interrupt 5529 * controllers 5530 */ 5531 mv88e6xxx_reg_lock(chip); 5532 if (chip->irq > 0) 5533 err = mv88e6xxx_g1_irq_setup(chip); 5534 else 5535 err = mv88e6xxx_irq_poll_setup(chip); 5536 mv88e6xxx_reg_unlock(chip); 5537 5538 if (err) 5539 goto out; 5540 5541 if (chip->info->g2_irqs > 0) { 5542 err = mv88e6xxx_g2_irq_setup(chip); 5543 if (err) 5544 goto out_g1_irq; 5545 } 5546 5547 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5548 if (err) 5549 goto out_g2_irq; 5550 5551 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5552 if (err) 5553 goto out_g1_atu_prob_irq; 5554 5555 err = mv88e6xxx_mdios_register(chip, np); 5556 if (err) 5557 goto out_g1_vtu_prob_irq; 5558 5559 err = mv88e6xxx_register_switch(chip); 5560 if (err) 5561 goto out_mdio; 5562 5563 return 0; 5564 5565 out_mdio: 5566 mv88e6xxx_mdios_unregister(chip); 5567 out_g1_vtu_prob_irq: 5568 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5569 out_g1_atu_prob_irq: 5570 mv88e6xxx_g1_atu_prob_irq_free(chip); 5571 out_g2_irq: 5572 if (chip->info->g2_irqs > 0) 5573 mv88e6xxx_g2_irq_free(chip); 5574 out_g1_irq: 5575 if (chip->irq > 0) 5576 mv88e6xxx_g1_irq_free(chip); 5577 else 5578 mv88e6xxx_irq_poll_free(chip); 5579 out: 5580 if (pdata) 5581 dev_put(pdata->netdev); 5582 5583 return err; 5584 } 5585 5586 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5587 { 5588 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5589 struct mv88e6xxx_chip *chip = ds->priv; 5590 5591 if (chip->info->ptp_support) { 5592 mv88e6xxx_hwtstamp_free(chip); 5593 mv88e6xxx_ptp_free(chip); 5594 } 5595 5596 mv88e6xxx_phy_destroy(chip); 5597 mv88e6xxx_unregister_switch(chip); 5598 mv88e6xxx_mdios_unregister(chip); 5599 5600 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5601 mv88e6xxx_g1_atu_prob_irq_free(chip); 5602 5603 if (chip->info->g2_irqs > 0) 5604 mv88e6xxx_g2_irq_free(chip); 5605 5606 if (chip->irq > 0) 5607 mv88e6xxx_g1_irq_free(chip); 5608 else 5609 mv88e6xxx_irq_poll_free(chip); 5610 } 5611 5612 static const struct of_device_id mv88e6xxx_of_match[] = { 5613 { 5614 .compatible = "marvell,mv88e6085", 5615 .data = &mv88e6xxx_table[MV88E6085], 5616 }, 5617 { 5618 .compatible = "marvell,mv88e6190", 5619 .data = &mv88e6xxx_table[MV88E6190], 5620 }, 5621 { 5622 .compatible = "marvell,mv88e6250", 5623 .data = &mv88e6xxx_table[MV88E6250], 5624 }, 5625 { /* sentinel */ }, 5626 }; 5627 5628 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5629 5630 static struct mdio_driver mv88e6xxx_driver = { 5631 .probe = mv88e6xxx_probe, 5632 .remove = mv88e6xxx_remove, 5633 .mdiodrv.driver = { 5634 .name = "mv88e6085", 5635 .of_match_table = mv88e6xxx_of_match, 5636 .pm = &mv88e6xxx_pm_ops, 5637 }, 5638 }; 5639 5640 mdio_module_driver(mv88e6xxx_driver); 5641 5642 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5643 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5644 MODULE_LICENSE("GPL"); 5645