1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void 570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 571 struct phylink_config *config) 572 { 573 unsigned long *supported = config->supported_interfaces; 574 int err; 575 u16 reg; 576 577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 578 if (err) { 579 dev_err(chip->dev, "p%d: failed to read port status\n", port); 580 return; 581 } 582 583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 589 break; 590 591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 593 __set_bit(PHY_INTERFACE_MODE_MII, supported); 594 break; 595 596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 601 break; 602 603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 605 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 606 break; 607 608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 610 break; 611 612 default: 613 dev_err(chip->dev, 614 "p%d: invalid port mode in status register: %04x\n", 615 port, reg); 616 } 617 } 618 619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 620 struct phylink_config *config) 621 { 622 if (!mv88e6xxx_phy_is_internal(chip, port)) 623 mv88e6250_setup_supported_interfaces(chip, port, config); 624 625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 626 } 627 628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 629 struct phylink_config *config) 630 { 631 unsigned long *supported = config->supported_interfaces; 632 633 /* Translate the default cmode */ 634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 635 636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 637 MAC_1000FD; 638 } 639 640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 641 { 642 u16 reg, val; 643 int err; 644 645 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 646 if (err) 647 return err; 648 649 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 651 return 0xf; 652 653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 654 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 655 if (err) 656 return err; 657 658 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 659 if (err) 660 return err; 661 662 /* Restore PHY_DETECT value */ 663 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 664 if (err) 665 return err; 666 667 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 668 } 669 670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 671 struct phylink_config *config) 672 { 673 unsigned long *supported = config->supported_interfaces; 674 int err, cmode; 675 676 /* Translate the default cmode */ 677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 678 679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 680 MAC_1000FD; 681 682 /* Port 4 supports automedia if the serdes is associated with it. */ 683 if (port == 4) { 684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 685 if (err < 0) 686 dev_err(chip->dev, "p%d: failed to read scratch\n", 687 port); 688 if (err <= 0) 689 return; 690 691 cmode = mv88e6352_get_port4_serdes_cmode(chip); 692 if (cmode < 0) 693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 694 port); 695 else 696 mv88e6xxx_translate_cmode(cmode, supported); 697 } 698 } 699 700 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 701 struct phylink_config *config) 702 { 703 unsigned long *supported = config->supported_interfaces; 704 705 /* Translate the default cmode */ 706 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 707 708 /* No ethtool bits for 200Mbps */ 709 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 710 MAC_1000FD; 711 712 /* The C_Mode field is programmable on port 5 */ 713 if (port == 5) { 714 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 715 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 716 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 717 718 config->mac_capabilities |= MAC_2500FD; 719 } 720 } 721 722 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 723 struct phylink_config *config) 724 { 725 unsigned long *supported = config->supported_interfaces; 726 727 /* Translate the default cmode */ 728 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 729 730 /* No ethtool bits for 200Mbps */ 731 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 732 MAC_1000FD; 733 734 /* The C_Mode field is programmable on ports 9 and 10 */ 735 if (port == 9 || port == 10) { 736 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 737 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 738 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 739 740 config->mac_capabilities |= MAC_2500FD; 741 } 742 } 743 744 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 745 struct phylink_config *config) 746 { 747 unsigned long *supported = config->supported_interfaces; 748 749 mv88e6390_phylink_get_caps(chip, port, config); 750 751 /* For the 6x90X, ports 2-7 can be in automedia mode. 752 * (Note that 6x90 doesn't support RXAUI nor XAUI). 753 * 754 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 755 * configured for 1000BASE-X, SGMII or 2500BASE-X. 756 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 757 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 758 * 759 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 760 * configured for 1000BASE-X, SGMII or 2500BASE-X. 761 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 762 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 763 * 764 * For now, be permissive (as the old code was) and allow 1000BASE-X 765 * on ports 2..7. 766 */ 767 if (port >= 2 && port <= 7) 768 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 769 770 /* The C_Mode field can also be programmed for 10G speeds */ 771 if (port == 9 || port == 10) { 772 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 773 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 774 775 config->mac_capabilities |= MAC_10000FD; 776 } 777 } 778 779 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 780 struct phylink_config *config) 781 { 782 unsigned long *supported = config->supported_interfaces; 783 bool is_6191x = 784 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 785 bool is_6361 = 786 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 787 788 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 789 790 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 791 MAC_1000FD; 792 793 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 794 if (port == 0 || port == 9 || port == 10) { 795 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 796 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 797 798 /* 6191X supports >1G modes only on port 10 */ 799 if (!is_6191x || port == 10) { 800 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 801 config->mac_capabilities |= MAC_2500FD; 802 803 /* 6361 only supports up to 2500BaseX */ 804 if (!is_6361) { 805 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 806 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 807 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 808 config->mac_capabilities |= MAC_5000FD | 809 MAC_10000FD; 810 } 811 } 812 } 813 814 if (port == 0) { 815 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 816 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 817 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 818 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 819 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 820 } 821 } 822 823 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 824 struct phylink_config *config) 825 { 826 struct mv88e6xxx_chip *chip = ds->priv; 827 828 mv88e6xxx_reg_lock(chip); 829 chip->info->ops->phylink_get_caps(chip, port, config); 830 mv88e6xxx_reg_unlock(chip); 831 832 if (mv88e6xxx_phy_is_internal(chip, port)) { 833 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 834 config->supported_interfaces); 835 /* Internal ports with no phy-mode need GMII for PHYLIB */ 836 __set_bit(PHY_INTERFACE_MODE_GMII, 837 config->supported_interfaces); 838 } 839 } 840 841 static struct phylink_pcs * 842 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 843 phy_interface_t interface) 844 { 845 struct dsa_port *dp = dsa_phylink_to_port(config); 846 struct mv88e6xxx_chip *chip = dp->ds->priv; 847 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 848 849 if (chip->info->ops->pcs_ops) 850 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 851 interface); 852 853 return pcs; 854 } 855 856 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 857 unsigned int mode, phy_interface_t interface) 858 { 859 struct dsa_port *dp = dsa_phylink_to_port(config); 860 struct mv88e6xxx_chip *chip = dp->ds->priv; 861 int port = dp->index; 862 int err = 0; 863 864 /* In inband mode, the link may come up at any time while the link 865 * is not forced down. Force the link down while we reconfigure the 866 * interface mode. 867 */ 868 if (mode == MLO_AN_INBAND && 869 chip->ports[port].interface != interface && 870 chip->info->ops->port_set_link) { 871 mv88e6xxx_reg_lock(chip); 872 err = chip->info->ops->port_set_link(chip, port, 873 LINK_FORCED_DOWN); 874 mv88e6xxx_reg_unlock(chip); 875 } 876 877 return err; 878 } 879 880 static void mv88e6xxx_mac_config(struct phylink_config *config, 881 unsigned int mode, 882 const struct phylink_link_state *state) 883 { 884 struct dsa_port *dp = dsa_phylink_to_port(config); 885 struct mv88e6xxx_chip *chip = dp->ds->priv; 886 int port = dp->index; 887 int err = 0; 888 889 mv88e6xxx_reg_lock(chip); 890 891 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 892 err = mv88e6xxx_port_config_interface(chip, port, 893 state->interface); 894 if (err && err != -EOPNOTSUPP) 895 goto err_unlock; 896 } 897 898 err_unlock: 899 mv88e6xxx_reg_unlock(chip); 900 901 if (err && err != -EOPNOTSUPP) 902 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 903 } 904 905 static int mv88e6xxx_mac_finish(struct phylink_config *config, 906 unsigned int mode, phy_interface_t interface) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 /* Undo the forced down state above after completing configuration 914 * irrespective of its state on entry, which allows the link to come 915 * up in the in-band case where there is no separate SERDES. Also 916 * ensure that the link can come up if the PPU is in use and we are 917 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 918 */ 919 mv88e6xxx_reg_lock(chip); 920 921 if (chip->info->ops->port_set_link && 922 ((mode == MLO_AN_INBAND && 923 chip->ports[port].interface != interface) || 924 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 925 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 926 927 mv88e6xxx_reg_unlock(chip); 928 929 chip->ports[port].interface = interface; 930 931 return err; 932 } 933 934 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 935 unsigned int mode, 936 phy_interface_t interface) 937 { 938 struct dsa_port *dp = dsa_phylink_to_port(config); 939 struct mv88e6xxx_chip *chip = dp->ds->priv; 940 const struct mv88e6xxx_ops *ops; 941 int port = dp->index; 942 int err = 0; 943 944 ops = chip->info->ops; 945 946 mv88e6xxx_reg_lock(chip); 947 /* Force the link down if we know the port may not be automatically 948 * updated by the switch or if we are using fixed-link mode. 949 */ 950 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 951 mode == MLO_AN_FIXED) && ops->port_sync_link) 952 err = ops->port_sync_link(chip, port, mode, false); 953 954 if (!err && ops->port_set_speed_duplex) 955 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 956 DUPLEX_UNFORCED); 957 mv88e6xxx_reg_unlock(chip); 958 959 if (err) 960 dev_err(chip->dev, 961 "p%d: failed to force MAC link down\n", port); 962 } 963 964 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 965 struct phy_device *phydev, 966 unsigned int mode, phy_interface_t interface, 967 int speed, int duplex, 968 bool tx_pause, bool rx_pause) 969 { 970 struct dsa_port *dp = dsa_phylink_to_port(config); 971 struct mv88e6xxx_chip *chip = dp->ds->priv; 972 const struct mv88e6xxx_ops *ops; 973 int port = dp->index; 974 int err = 0; 975 976 ops = chip->info->ops; 977 978 mv88e6xxx_reg_lock(chip); 979 /* Configure and force the link up if we know that the port may not 980 * automatically updated by the switch or if we are using fixed-link 981 * mode. 982 */ 983 if (!mv88e6xxx_port_ppu_updates(chip, port) || 984 mode == MLO_AN_FIXED) { 985 if (ops->port_set_speed_duplex) { 986 err = ops->port_set_speed_duplex(chip, port, 987 speed, duplex); 988 if (err && err != -EOPNOTSUPP) 989 goto error; 990 } 991 992 if (ops->port_sync_link) 993 err = ops->port_sync_link(chip, port, mode, true); 994 } 995 error: 996 mv88e6xxx_reg_unlock(chip); 997 998 if (err && err != -EOPNOTSUPP) 999 dev_err(chip->dev, 1000 "p%d: failed to configure MAC link up\n", port); 1001 } 1002 1003 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1004 { 1005 int err; 1006 1007 if (!chip->info->ops->stats_snapshot) 1008 return -EOPNOTSUPP; 1009 1010 mv88e6xxx_reg_lock(chip); 1011 err = chip->info->ops->stats_snapshot(chip, port); 1012 mv88e6xxx_reg_unlock(chip); 1013 1014 return err; 1015 } 1016 1017 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1018 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1019 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1020 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1021 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1022 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1023 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1024 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1025 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1026 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1027 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1028 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1029 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1030 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1031 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1032 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1033 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1034 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1035 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1036 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1037 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1038 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1039 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1040 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1041 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1042 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1043 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1044 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1045 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1046 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1047 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1048 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1049 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1050 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1051 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1052 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1053 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1054 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1055 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1056 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1057 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1058 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1059 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1060 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1061 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1062 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1063 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1064 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1065 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1066 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1067 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1068 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1069 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1070 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1071 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1072 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1073 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1074 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1075 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1076 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1077 /* */ 1078 1079 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1080 { #_string, _size, _reg, _type } 1081 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1082 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1083 }; 1084 1085 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1086 MV88E6XXX_HW_STAT_ID_ ## _string 1087 enum mv88e6xxx_hw_stat_id { 1088 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1089 }; 1090 1091 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1092 const struct mv88e6xxx_hw_stat *s, 1093 int port, u16 bank1_select, 1094 u16 histogram) 1095 { 1096 u32 low; 1097 u32 high = 0; 1098 u16 reg = 0; 1099 int err; 1100 u64 value; 1101 1102 switch (s->type) { 1103 case STATS_TYPE_PORT: 1104 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1105 if (err) 1106 return U64_MAX; 1107 1108 low = reg; 1109 if (s->size == 4) { 1110 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1111 if (err) 1112 return U64_MAX; 1113 low |= ((u32)reg) << 16; 1114 } 1115 break; 1116 case STATS_TYPE_BANK1: 1117 reg = bank1_select; 1118 fallthrough; 1119 case STATS_TYPE_BANK0: 1120 reg |= s->reg | histogram; 1121 mv88e6xxx_g1_stats_read(chip, reg, &low); 1122 if (s->size == 8) 1123 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1124 break; 1125 default: 1126 return U64_MAX; 1127 } 1128 value = (((u64)high) << 32) | low; 1129 return value; 1130 } 1131 1132 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1133 uint8_t *data, int types) 1134 { 1135 const struct mv88e6xxx_hw_stat *stat; 1136 int i, j; 1137 1138 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1139 stat = &mv88e6xxx_hw_stats[i]; 1140 if (stat->type & types) { 1141 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1142 ETH_GSTRING_LEN); 1143 j++; 1144 } 1145 } 1146 1147 return j; 1148 } 1149 1150 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1151 uint8_t *data) 1152 { 1153 return mv88e6xxx_stats_get_strings(chip, data, 1154 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1155 } 1156 1157 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1158 uint8_t *data) 1159 { 1160 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1161 } 1162 1163 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1164 uint8_t *data) 1165 { 1166 return mv88e6xxx_stats_get_strings(chip, data, 1167 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1168 } 1169 1170 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1171 "atu_member_violation", 1172 "atu_miss_violation", 1173 "atu_full_violation", 1174 "vtu_member_violation", 1175 "vtu_miss_violation", 1176 }; 1177 1178 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1179 { 1180 unsigned int i; 1181 1182 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1183 strscpy(data + i * ETH_GSTRING_LEN, 1184 mv88e6xxx_atu_vtu_stats_strings[i], 1185 ETH_GSTRING_LEN); 1186 } 1187 1188 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1189 u32 stringset, uint8_t *data) 1190 { 1191 struct mv88e6xxx_chip *chip = ds->priv; 1192 int count = 0; 1193 1194 if (stringset != ETH_SS_STATS) 1195 return; 1196 1197 mv88e6xxx_reg_lock(chip); 1198 1199 if (chip->info->ops->stats_get_strings) 1200 count = chip->info->ops->stats_get_strings(chip, data); 1201 1202 if (chip->info->ops->serdes_get_strings) { 1203 data += count * ETH_GSTRING_LEN; 1204 count = chip->info->ops->serdes_get_strings(chip, port, data); 1205 } 1206 1207 data += count * ETH_GSTRING_LEN; 1208 mv88e6xxx_atu_vtu_get_strings(data); 1209 1210 mv88e6xxx_reg_unlock(chip); 1211 } 1212 1213 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1214 int types) 1215 { 1216 const struct mv88e6xxx_hw_stat *stat; 1217 int i, j; 1218 1219 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1220 stat = &mv88e6xxx_hw_stats[i]; 1221 if (stat->type & types) 1222 j++; 1223 } 1224 return j; 1225 } 1226 1227 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1228 { 1229 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1230 STATS_TYPE_PORT); 1231 } 1232 1233 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1234 { 1235 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1236 } 1237 1238 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1239 { 1240 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1241 STATS_TYPE_BANK1); 1242 } 1243 1244 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1245 { 1246 struct mv88e6xxx_chip *chip = ds->priv; 1247 int serdes_count = 0; 1248 int count = 0; 1249 1250 if (sset != ETH_SS_STATS) 1251 return 0; 1252 1253 mv88e6xxx_reg_lock(chip); 1254 if (chip->info->ops->stats_get_sset_count) 1255 count = chip->info->ops->stats_get_sset_count(chip); 1256 if (count < 0) 1257 goto out; 1258 1259 if (chip->info->ops->serdes_get_sset_count) 1260 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1261 port); 1262 if (serdes_count < 0) { 1263 count = serdes_count; 1264 goto out; 1265 } 1266 count += serdes_count; 1267 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1268 1269 out: 1270 mv88e6xxx_reg_unlock(chip); 1271 1272 return count; 1273 } 1274 1275 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1276 const struct mv88e6xxx_hw_stat *stat, 1277 uint64_t *data) 1278 { 1279 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT))) 1280 return 0; 1281 1282 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1283 MV88E6XXX_G1_STATS_OP_HIST_RX); 1284 return 1; 1285 } 1286 1287 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1288 const struct mv88e6xxx_hw_stat *stat, 1289 uint64_t *data) 1290 { 1291 if (!(stat->type & STATS_TYPE_BANK0)) 1292 return 0; 1293 1294 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1295 MV88E6XXX_G1_STATS_OP_HIST_RX); 1296 return 1; 1297 } 1298 1299 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1300 const struct mv88e6xxx_hw_stat *stat, 1301 uint64_t *data) 1302 { 1303 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1304 return 0; 1305 1306 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1307 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1308 MV88E6XXX_G1_STATS_OP_HIST_RX); 1309 return 1; 1310 } 1311 1312 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1313 const struct mv88e6xxx_hw_stat *stat, 1314 uint64_t *data) 1315 { 1316 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1317 return 0; 1318 1319 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1320 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1321 0); 1322 return 1; 1323 } 1324 1325 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1326 const struct mv88e6xxx_hw_stat *stat, 1327 uint64_t *data) 1328 { 1329 int ret = 0; 1330 1331 if (chip->info->ops->stats_get_stat) { 1332 mv88e6xxx_reg_lock(chip); 1333 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1334 mv88e6xxx_reg_unlock(chip); 1335 } 1336 1337 return ret; 1338 } 1339 1340 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1341 uint64_t *data) 1342 { 1343 const struct mv88e6xxx_hw_stat *stat; 1344 size_t i, j; 1345 1346 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1347 stat = &mv88e6xxx_hw_stats[i]; 1348 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1349 } 1350 return j; 1351 } 1352 1353 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1354 uint64_t *data) 1355 { 1356 *data++ = chip->ports[port].atu_member_violation; 1357 *data++ = chip->ports[port].atu_miss_violation; 1358 *data++ = chip->ports[port].atu_full_violation; 1359 *data++ = chip->ports[port].vtu_member_violation; 1360 *data++ = chip->ports[port].vtu_miss_violation; 1361 } 1362 1363 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1364 uint64_t *data) 1365 { 1366 size_t count; 1367 1368 count = mv88e6xxx_stats_get_stats(chip, port, data); 1369 1370 mv88e6xxx_reg_lock(chip); 1371 if (chip->info->ops->serdes_get_stats) { 1372 data += count; 1373 count = chip->info->ops->serdes_get_stats(chip, port, data); 1374 } 1375 data += count; 1376 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1377 mv88e6xxx_reg_unlock(chip); 1378 } 1379 1380 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1381 uint64_t *data) 1382 { 1383 struct mv88e6xxx_chip *chip = ds->priv; 1384 int ret; 1385 1386 ret = mv88e6xxx_stats_snapshot(chip, port); 1387 if (ret < 0) 1388 return; 1389 1390 mv88e6xxx_get_stats(chip, port, data); 1391 } 1392 1393 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1394 struct ethtool_eth_mac_stats *mac_stats) 1395 { 1396 struct mv88e6xxx_chip *chip = ds->priv; 1397 int ret; 1398 1399 ret = mv88e6xxx_stats_snapshot(chip, port); 1400 if (ret < 0) 1401 return; 1402 1403 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1404 mv88e6xxx_stats_get_stat(chip, port, \ 1405 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1406 &mac_stats->stats._member) 1407 1408 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1409 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1410 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1411 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1412 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1422 1423 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1424 1425 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1426 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1427 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1428 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1429 } 1430 1431 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1432 struct ethtool_rmon_stats *rmon_stats, 1433 const struct ethtool_rmon_hist_range **ranges) 1434 { 1435 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1436 { 64, 64 }, 1437 { 65, 127 }, 1438 { 128, 255 }, 1439 { 256, 511 }, 1440 { 512, 1023 }, 1441 { 1024, 65535 }, 1442 {} 1443 }; 1444 struct mv88e6xxx_chip *chip = ds->priv; 1445 int ret; 1446 1447 ret = mv88e6xxx_stats_snapshot(chip, port); 1448 if (ret < 0) 1449 return; 1450 1451 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1452 mv88e6xxx_stats_get_stat(chip, port, \ 1453 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1454 &rmon_stats->stats._member) 1455 1456 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1457 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1458 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1459 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1460 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1461 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1462 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1463 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1464 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1466 1467 #undef MV88E6XXX_RMON_STAT_MAP 1468 1469 *ranges = rmon_ranges; 1470 } 1471 1472 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1473 { 1474 struct mv88e6xxx_chip *chip = ds->priv; 1475 int len; 1476 1477 len = 32 * sizeof(u16); 1478 if (chip->info->ops->serdes_get_regs_len) 1479 len += chip->info->ops->serdes_get_regs_len(chip, port); 1480 1481 return len; 1482 } 1483 1484 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1485 struct ethtool_regs *regs, void *_p) 1486 { 1487 struct mv88e6xxx_chip *chip = ds->priv; 1488 int err; 1489 u16 reg; 1490 u16 *p = _p; 1491 int i; 1492 1493 regs->version = chip->info->prod_num; 1494 1495 memset(p, 0xff, 32 * sizeof(u16)); 1496 1497 mv88e6xxx_reg_lock(chip); 1498 1499 for (i = 0; i < 32; i++) { 1500 1501 err = mv88e6xxx_port_read(chip, port, i, ®); 1502 if (!err) 1503 p[i] = reg; 1504 } 1505 1506 if (chip->info->ops->serdes_get_regs) 1507 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1508 1509 mv88e6xxx_reg_unlock(chip); 1510 } 1511 1512 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1513 struct ethtool_keee *e) 1514 { 1515 /* Nothing to do on the port's MAC */ 1516 return 0; 1517 } 1518 1519 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1520 struct ethtool_keee *e) 1521 { 1522 /* Nothing to do on the port's MAC */ 1523 return 0; 1524 } 1525 1526 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1527 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1528 { 1529 struct dsa_switch *ds = chip->ds; 1530 struct dsa_switch_tree *dst = ds->dst; 1531 struct dsa_port *dp, *other_dp; 1532 bool found = false; 1533 u16 pvlan; 1534 1535 /* dev is a physical switch */ 1536 if (dev <= dst->last_switch) { 1537 list_for_each_entry(dp, &dst->ports, list) { 1538 if (dp->ds->index == dev && dp->index == port) { 1539 /* dp might be a DSA link or a user port, so it 1540 * might or might not have a bridge. 1541 * Use the "found" variable for both cases. 1542 */ 1543 found = true; 1544 break; 1545 } 1546 } 1547 /* dev is a virtual bridge */ 1548 } else { 1549 list_for_each_entry(dp, &dst->ports, list) { 1550 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1551 1552 if (!bridge_num) 1553 continue; 1554 1555 if (bridge_num + dst->last_switch != dev) 1556 continue; 1557 1558 found = true; 1559 break; 1560 } 1561 } 1562 1563 /* Prevent frames from unknown switch or virtual bridge */ 1564 if (!found) 1565 return 0; 1566 1567 /* Frames from DSA links and CPU ports can egress any local port */ 1568 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1569 return mv88e6xxx_port_mask(chip); 1570 1571 pvlan = 0; 1572 1573 /* Frames from standalone user ports can only egress on the 1574 * upstream port. 1575 */ 1576 if (!dsa_port_bridge_dev_get(dp)) 1577 return BIT(dsa_switch_upstream_port(ds)); 1578 1579 /* Frames from bridged user ports can egress any local DSA 1580 * links and CPU ports, as well as any local member of their 1581 * bridge group. 1582 */ 1583 dsa_switch_for_each_port(other_dp, ds) 1584 if (other_dp->type == DSA_PORT_TYPE_CPU || 1585 other_dp->type == DSA_PORT_TYPE_DSA || 1586 dsa_port_bridge_same(dp, other_dp)) 1587 pvlan |= BIT(other_dp->index); 1588 1589 return pvlan; 1590 } 1591 1592 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1593 { 1594 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1595 1596 /* prevent frames from going back out of the port they came in on */ 1597 output_ports &= ~BIT(port); 1598 1599 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1600 } 1601 1602 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1603 u8 state) 1604 { 1605 struct mv88e6xxx_chip *chip = ds->priv; 1606 int err; 1607 1608 mv88e6xxx_reg_lock(chip); 1609 err = mv88e6xxx_port_set_state(chip, port, state); 1610 mv88e6xxx_reg_unlock(chip); 1611 1612 if (err) 1613 dev_err(ds->dev, "p%d: failed to update state\n", port); 1614 } 1615 1616 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1617 { 1618 int err; 1619 1620 if (chip->info->ops->ieee_pri_map) { 1621 err = chip->info->ops->ieee_pri_map(chip); 1622 if (err) 1623 return err; 1624 } 1625 1626 if (chip->info->ops->ip_pri_map) { 1627 err = chip->info->ops->ip_pri_map(chip); 1628 if (err) 1629 return err; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1636 { 1637 struct dsa_switch *ds = chip->ds; 1638 int target, port; 1639 int err; 1640 1641 if (!chip->info->global2_addr) 1642 return 0; 1643 1644 /* Initialize the routing port to the 32 possible target devices */ 1645 for (target = 0; target < 32; target++) { 1646 port = dsa_routing_port(ds, target); 1647 if (port == ds->num_ports) 1648 port = 0x1f; 1649 1650 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1651 if (err) 1652 return err; 1653 } 1654 1655 if (chip->info->ops->set_cascade_port) { 1656 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1657 err = chip->info->ops->set_cascade_port(chip, port); 1658 if (err) 1659 return err; 1660 } 1661 1662 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1663 if (err) 1664 return err; 1665 1666 return 0; 1667 } 1668 1669 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1670 { 1671 /* Clear all trunk masks and mapping */ 1672 if (chip->info->global2_addr) 1673 return mv88e6xxx_g2_trunk_clear(chip); 1674 1675 return 0; 1676 } 1677 1678 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1679 { 1680 if (chip->info->ops->rmu_disable) 1681 return chip->info->ops->rmu_disable(chip); 1682 1683 return 0; 1684 } 1685 1686 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1687 { 1688 if (chip->info->ops->pot_clear) 1689 return chip->info->ops->pot_clear(chip); 1690 1691 return 0; 1692 } 1693 1694 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1695 { 1696 if (chip->info->ops->mgmt_rsvd2cpu) 1697 return chip->info->ops->mgmt_rsvd2cpu(chip); 1698 1699 return 0; 1700 } 1701 1702 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1703 { 1704 int err; 1705 1706 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1707 if (err) 1708 return err; 1709 1710 /* The chips that have a "learn2all" bit in Global1, ATU 1711 * Control are precisely those whose port registers have a 1712 * Message Port bit in Port Control 1 and hence implement 1713 * ->port_setup_message_port. 1714 */ 1715 if (chip->info->ops->port_setup_message_port) { 1716 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1717 if (err) 1718 return err; 1719 } 1720 1721 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1722 } 1723 1724 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1725 { 1726 int port; 1727 int err; 1728 1729 if (!chip->info->ops->irl_init_all) 1730 return 0; 1731 1732 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1733 /* Disable ingress rate limiting by resetting all per port 1734 * ingress rate limit resources to their initial state. 1735 */ 1736 err = chip->info->ops->irl_init_all(chip, port); 1737 if (err) 1738 return err; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1745 { 1746 if (chip->info->ops->set_switch_mac) { 1747 u8 addr[ETH_ALEN]; 1748 1749 eth_random_addr(addr); 1750 1751 return chip->info->ops->set_switch_mac(chip, addr); 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1758 { 1759 struct dsa_switch_tree *dst = chip->ds->dst; 1760 struct dsa_switch *ds; 1761 struct dsa_port *dp; 1762 u16 pvlan = 0; 1763 1764 if (!mv88e6xxx_has_pvt(chip)) 1765 return 0; 1766 1767 /* Skip the local source device, which uses in-chip port VLAN */ 1768 if (dev != chip->ds->index) { 1769 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1770 1771 ds = dsa_switch_find(dst->index, dev); 1772 dp = ds ? dsa_to_port(ds, port) : NULL; 1773 if (dp && dp->lag) { 1774 /* As the PVT is used to limit flooding of 1775 * FORWARD frames, which use the LAG ID as the 1776 * source port, we must translate dev/port to 1777 * the special "LAG device" in the PVT, using 1778 * the LAG ID (one-based) as the port number 1779 * (zero-based). 1780 */ 1781 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1782 port = dsa_port_lag_id_get(dp) - 1; 1783 } 1784 } 1785 1786 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1787 } 1788 1789 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1790 { 1791 int dev, port; 1792 int err; 1793 1794 if (!mv88e6xxx_has_pvt(chip)) 1795 return 0; 1796 1797 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1798 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1799 */ 1800 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1801 if (err) 1802 return err; 1803 1804 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1805 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1806 err = mv88e6xxx_pvt_map(chip, dev, port); 1807 if (err) 1808 return err; 1809 } 1810 } 1811 1812 return 0; 1813 } 1814 1815 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1816 u16 fid) 1817 { 1818 if (dsa_to_port(chip->ds, port)->lag) 1819 /* Hardware is incapable of fast-aging a LAG through a 1820 * regular ATU move operation. Until we have something 1821 * more fancy in place this is a no-op. 1822 */ 1823 return -EOPNOTSUPP; 1824 1825 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1826 } 1827 1828 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1829 { 1830 struct mv88e6xxx_chip *chip = ds->priv; 1831 int err; 1832 1833 mv88e6xxx_reg_lock(chip); 1834 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1835 mv88e6xxx_reg_unlock(chip); 1836 1837 if (err) 1838 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1839 port, err); 1840 } 1841 1842 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1843 { 1844 if (!mv88e6xxx_max_vid(chip)) 1845 return 0; 1846 1847 return mv88e6xxx_g1_vtu_flush(chip); 1848 } 1849 1850 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1851 struct mv88e6xxx_vtu_entry *entry) 1852 { 1853 int err; 1854 1855 if (!chip->info->ops->vtu_getnext) 1856 return -EOPNOTSUPP; 1857 1858 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1859 entry->valid = false; 1860 1861 err = chip->info->ops->vtu_getnext(chip, entry); 1862 1863 if (entry->vid != vid) 1864 entry->valid = false; 1865 1866 return err; 1867 } 1868 1869 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1870 int (*cb)(struct mv88e6xxx_chip *chip, 1871 const struct mv88e6xxx_vtu_entry *entry, 1872 void *priv), 1873 void *priv) 1874 { 1875 struct mv88e6xxx_vtu_entry entry = { 1876 .vid = mv88e6xxx_max_vid(chip), 1877 .valid = false, 1878 }; 1879 int err; 1880 1881 if (!chip->info->ops->vtu_getnext) 1882 return -EOPNOTSUPP; 1883 1884 do { 1885 err = chip->info->ops->vtu_getnext(chip, &entry); 1886 if (err) 1887 return err; 1888 1889 if (!entry.valid) 1890 break; 1891 1892 err = cb(chip, &entry, priv); 1893 if (err) 1894 return err; 1895 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1896 1897 return 0; 1898 } 1899 1900 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1901 struct mv88e6xxx_vtu_entry *entry) 1902 { 1903 if (!chip->info->ops->vtu_loadpurge) 1904 return -EOPNOTSUPP; 1905 1906 return chip->info->ops->vtu_loadpurge(chip, entry); 1907 } 1908 1909 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1910 const struct mv88e6xxx_vtu_entry *entry, 1911 void *_fid_bitmap) 1912 { 1913 unsigned long *fid_bitmap = _fid_bitmap; 1914 1915 set_bit(entry->fid, fid_bitmap); 1916 return 0; 1917 } 1918 1919 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1920 { 1921 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1922 1923 /* Every FID has an associated VID, so walking the VTU 1924 * will discover the full set of FIDs in use. 1925 */ 1926 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1927 } 1928 1929 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1930 { 1931 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1932 int err; 1933 1934 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1935 if (err) 1936 return err; 1937 1938 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1939 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1940 return -ENOSPC; 1941 1942 /* Clear the database */ 1943 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1944 } 1945 1946 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1947 struct mv88e6xxx_stu_entry *entry) 1948 { 1949 if (!chip->info->ops->stu_loadpurge) 1950 return -EOPNOTSUPP; 1951 1952 return chip->info->ops->stu_loadpurge(chip, entry); 1953 } 1954 1955 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1956 { 1957 struct mv88e6xxx_stu_entry stu = { 1958 .valid = true, 1959 .sid = 0 1960 }; 1961 1962 if (!mv88e6xxx_has_stu(chip)) 1963 return 0; 1964 1965 /* Make sure that SID 0 is always valid. This is used by VTU 1966 * entries that do not make use of the STU, e.g. when creating 1967 * a VLAN upper on a port that is also part of a VLAN 1968 * filtering bridge. 1969 */ 1970 return mv88e6xxx_stu_loadpurge(chip, &stu); 1971 } 1972 1973 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1974 { 1975 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1976 struct mv88e6xxx_mst *mst; 1977 1978 __set_bit(0, busy); 1979 1980 list_for_each_entry(mst, &chip->msts, node) 1981 __set_bit(mst->stu.sid, busy); 1982 1983 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1984 1985 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1986 } 1987 1988 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1989 { 1990 struct mv88e6xxx_mst *mst, *tmp; 1991 int err; 1992 1993 if (!sid) 1994 return 0; 1995 1996 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1997 if (mst->stu.sid != sid) 1998 continue; 1999 2000 if (!refcount_dec_and_test(&mst->refcnt)) 2001 return 0; 2002 2003 mst->stu.valid = false; 2004 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2005 if (err) { 2006 refcount_set(&mst->refcnt, 1); 2007 return err; 2008 } 2009 2010 list_del(&mst->node); 2011 kfree(mst); 2012 return 0; 2013 } 2014 2015 return -ENOENT; 2016 } 2017 2018 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 2019 u16 msti, u8 *sid) 2020 { 2021 struct mv88e6xxx_mst *mst; 2022 int err, i; 2023 2024 if (!mv88e6xxx_has_stu(chip)) { 2025 err = -EOPNOTSUPP; 2026 goto err; 2027 } 2028 2029 if (!msti) { 2030 *sid = 0; 2031 return 0; 2032 } 2033 2034 list_for_each_entry(mst, &chip->msts, node) { 2035 if (mst->br == br && mst->msti == msti) { 2036 refcount_inc(&mst->refcnt); 2037 *sid = mst->stu.sid; 2038 return 0; 2039 } 2040 } 2041 2042 err = mv88e6xxx_sid_get(chip, sid); 2043 if (err) 2044 goto err; 2045 2046 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2047 if (!mst) { 2048 err = -ENOMEM; 2049 goto err; 2050 } 2051 2052 INIT_LIST_HEAD(&mst->node); 2053 refcount_set(&mst->refcnt, 1); 2054 mst->br = br; 2055 mst->msti = msti; 2056 mst->stu.valid = true; 2057 mst->stu.sid = *sid; 2058 2059 /* The bridge starts out all ports in the disabled state. But 2060 * a STU state of disabled means to go by the port-global 2061 * state. So we set all user port's initial state to blocking, 2062 * to match the bridge's behavior. 2063 */ 2064 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2065 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2066 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2067 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2068 2069 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2070 if (err) 2071 goto err_free; 2072 2073 list_add_tail(&mst->node, &chip->msts); 2074 return 0; 2075 2076 err_free: 2077 kfree(mst); 2078 err: 2079 return err; 2080 } 2081 2082 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2083 const struct switchdev_mst_state *st) 2084 { 2085 struct dsa_port *dp = dsa_to_port(ds, port); 2086 struct mv88e6xxx_chip *chip = ds->priv; 2087 struct mv88e6xxx_mst *mst; 2088 u8 state; 2089 int err; 2090 2091 if (!mv88e6xxx_has_stu(chip)) 2092 return -EOPNOTSUPP; 2093 2094 switch (st->state) { 2095 case BR_STATE_DISABLED: 2096 case BR_STATE_BLOCKING: 2097 case BR_STATE_LISTENING: 2098 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2099 break; 2100 case BR_STATE_LEARNING: 2101 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2102 break; 2103 case BR_STATE_FORWARDING: 2104 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2105 break; 2106 default: 2107 return -EINVAL; 2108 } 2109 2110 list_for_each_entry(mst, &chip->msts, node) { 2111 if (mst->br == dsa_port_bridge_dev_get(dp) && 2112 mst->msti == st->msti) { 2113 if (mst->stu.state[port] == state) 2114 return 0; 2115 2116 mst->stu.state[port] = state; 2117 mv88e6xxx_reg_lock(chip); 2118 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2119 mv88e6xxx_reg_unlock(chip); 2120 return err; 2121 } 2122 } 2123 2124 return -ENOENT; 2125 } 2126 2127 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2128 u16 vid) 2129 { 2130 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2131 struct mv88e6xxx_chip *chip = ds->priv; 2132 struct mv88e6xxx_vtu_entry vlan; 2133 int err; 2134 2135 /* DSA and CPU ports have to be members of multiple vlans */ 2136 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2137 return 0; 2138 2139 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2140 if (err) 2141 return err; 2142 2143 if (!vlan.valid) 2144 return 0; 2145 2146 dsa_switch_for_each_user_port(other_dp, ds) { 2147 struct net_device *other_br; 2148 2149 if (vlan.member[other_dp->index] == 2150 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2151 continue; 2152 2153 if (dsa_port_bridge_same(dp, other_dp)) 2154 break; /* same bridge, check next VLAN */ 2155 2156 other_br = dsa_port_bridge_dev_get(other_dp); 2157 if (!other_br) 2158 continue; 2159 2160 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2161 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2162 return -EOPNOTSUPP; 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2169 { 2170 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2171 struct net_device *br = dsa_port_bridge_dev_get(dp); 2172 struct mv88e6xxx_port *p = &chip->ports[port]; 2173 u16 pvid = MV88E6XXX_VID_STANDALONE; 2174 bool drop_untagged = false; 2175 int err; 2176 2177 if (br) { 2178 if (br_vlan_enabled(br)) { 2179 pvid = p->bridge_pvid.vid; 2180 drop_untagged = !p->bridge_pvid.valid; 2181 } else { 2182 pvid = MV88E6XXX_VID_BRIDGED; 2183 } 2184 } 2185 2186 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2187 if (err) 2188 return err; 2189 2190 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2191 } 2192 2193 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2194 bool vlan_filtering, 2195 struct netlink_ext_ack *extack) 2196 { 2197 struct mv88e6xxx_chip *chip = ds->priv; 2198 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2199 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2200 int err; 2201 2202 if (!mv88e6xxx_max_vid(chip)) 2203 return -EOPNOTSUPP; 2204 2205 mv88e6xxx_reg_lock(chip); 2206 2207 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2208 if (err) 2209 goto unlock; 2210 2211 err = mv88e6xxx_port_commit_pvid(chip, port); 2212 if (err) 2213 goto unlock; 2214 2215 unlock: 2216 mv88e6xxx_reg_unlock(chip); 2217 2218 return err; 2219 } 2220 2221 static int 2222 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2223 const struct switchdev_obj_port_vlan *vlan) 2224 { 2225 struct mv88e6xxx_chip *chip = ds->priv; 2226 int err; 2227 2228 if (!mv88e6xxx_max_vid(chip)) 2229 return -EOPNOTSUPP; 2230 2231 /* If the requested port doesn't belong to the same bridge as the VLAN 2232 * members, do not support it (yet) and fallback to software VLAN. 2233 */ 2234 mv88e6xxx_reg_lock(chip); 2235 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2236 mv88e6xxx_reg_unlock(chip); 2237 2238 return err; 2239 } 2240 2241 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2242 const unsigned char *addr, u16 vid, 2243 u8 state) 2244 { 2245 struct mv88e6xxx_atu_entry entry; 2246 struct mv88e6xxx_vtu_entry vlan; 2247 u16 fid; 2248 int err; 2249 2250 /* Ports have two private address databases: one for when the port is 2251 * standalone and one for when the port is under a bridge and the 2252 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2253 * address database to remain 100% empty, so we never load an ATU entry 2254 * into a standalone port's database. Therefore, translate the null 2255 * VLAN ID into the port's database used for VLAN-unaware bridging. 2256 */ 2257 if (vid == 0) { 2258 fid = MV88E6XXX_FID_BRIDGED; 2259 } else { 2260 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2261 if (err) 2262 return err; 2263 2264 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2265 if (!vlan.valid) 2266 return -EOPNOTSUPP; 2267 2268 fid = vlan.fid; 2269 } 2270 2271 entry.state = 0; 2272 ether_addr_copy(entry.mac, addr); 2273 eth_addr_dec(entry.mac); 2274 2275 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2276 if (err) 2277 return err; 2278 2279 /* Initialize a fresh ATU entry if it isn't found */ 2280 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2281 memset(&entry, 0, sizeof(entry)); 2282 ether_addr_copy(entry.mac, addr); 2283 } 2284 2285 /* Purge the ATU entry only if no port is using it anymore */ 2286 if (!state) { 2287 entry.portvec &= ~BIT(port); 2288 if (!entry.portvec) 2289 entry.state = 0; 2290 } else { 2291 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2292 entry.portvec = BIT(port); 2293 else 2294 entry.portvec |= BIT(port); 2295 2296 entry.state = state; 2297 } 2298 2299 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2300 } 2301 2302 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2303 const struct mv88e6xxx_policy *policy) 2304 { 2305 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2306 enum mv88e6xxx_policy_action action = policy->action; 2307 const u8 *addr = policy->addr; 2308 u16 vid = policy->vid; 2309 u8 state; 2310 int err; 2311 int id; 2312 2313 if (!chip->info->ops->port_set_policy) 2314 return -EOPNOTSUPP; 2315 2316 switch (mapping) { 2317 case MV88E6XXX_POLICY_MAPPING_DA: 2318 case MV88E6XXX_POLICY_MAPPING_SA: 2319 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2320 state = 0; /* Dissociate the port and address */ 2321 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2322 is_multicast_ether_addr(addr)) 2323 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2324 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2325 is_unicast_ether_addr(addr)) 2326 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2327 else 2328 return -EOPNOTSUPP; 2329 2330 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2331 state); 2332 if (err) 2333 return err; 2334 break; 2335 default: 2336 return -EOPNOTSUPP; 2337 } 2338 2339 /* Skip the port's policy clearing if the mapping is still in use */ 2340 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2341 idr_for_each_entry(&chip->policies, policy, id) 2342 if (policy->port == port && 2343 policy->mapping == mapping && 2344 policy->action != action) 2345 return 0; 2346 2347 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2348 } 2349 2350 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2351 struct ethtool_rx_flow_spec *fs) 2352 { 2353 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2354 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2355 enum mv88e6xxx_policy_mapping mapping; 2356 enum mv88e6xxx_policy_action action; 2357 struct mv88e6xxx_policy *policy; 2358 u16 vid = 0; 2359 u8 *addr; 2360 int err; 2361 int id; 2362 2363 if (fs->location != RX_CLS_LOC_ANY) 2364 return -EINVAL; 2365 2366 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2367 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2368 else 2369 return -EOPNOTSUPP; 2370 2371 switch (fs->flow_type & ~FLOW_EXT) { 2372 case ETHER_FLOW: 2373 if (!is_zero_ether_addr(mac_mask->h_dest) && 2374 is_zero_ether_addr(mac_mask->h_source)) { 2375 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2376 addr = mac_entry->h_dest; 2377 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2378 !is_zero_ether_addr(mac_mask->h_source)) { 2379 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2380 addr = mac_entry->h_source; 2381 } else { 2382 /* Cannot support DA and SA mapping in the same rule */ 2383 return -EOPNOTSUPP; 2384 } 2385 break; 2386 default: 2387 return -EOPNOTSUPP; 2388 } 2389 2390 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2391 if (fs->m_ext.vlan_tci != htons(0xffff)) 2392 return -EOPNOTSUPP; 2393 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2394 } 2395 2396 idr_for_each_entry(&chip->policies, policy, id) { 2397 if (policy->port == port && policy->mapping == mapping && 2398 policy->action == action && policy->vid == vid && 2399 ether_addr_equal(policy->addr, addr)) 2400 return -EEXIST; 2401 } 2402 2403 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2404 if (!policy) 2405 return -ENOMEM; 2406 2407 fs->location = 0; 2408 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2409 GFP_KERNEL); 2410 if (err) { 2411 devm_kfree(chip->dev, policy); 2412 return err; 2413 } 2414 2415 memcpy(&policy->fs, fs, sizeof(*fs)); 2416 ether_addr_copy(policy->addr, addr); 2417 policy->mapping = mapping; 2418 policy->action = action; 2419 policy->port = port; 2420 policy->vid = vid; 2421 2422 err = mv88e6xxx_policy_apply(chip, port, policy); 2423 if (err) { 2424 idr_remove(&chip->policies, fs->location); 2425 devm_kfree(chip->dev, policy); 2426 return err; 2427 } 2428 2429 return 0; 2430 } 2431 2432 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2433 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2434 { 2435 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2436 struct mv88e6xxx_chip *chip = ds->priv; 2437 struct mv88e6xxx_policy *policy; 2438 int err; 2439 int id; 2440 2441 mv88e6xxx_reg_lock(chip); 2442 2443 switch (rxnfc->cmd) { 2444 case ETHTOOL_GRXCLSRLCNT: 2445 rxnfc->data = 0; 2446 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2447 rxnfc->rule_cnt = 0; 2448 idr_for_each_entry(&chip->policies, policy, id) 2449 if (policy->port == port) 2450 rxnfc->rule_cnt++; 2451 err = 0; 2452 break; 2453 case ETHTOOL_GRXCLSRULE: 2454 err = -ENOENT; 2455 policy = idr_find(&chip->policies, fs->location); 2456 if (policy) { 2457 memcpy(fs, &policy->fs, sizeof(*fs)); 2458 err = 0; 2459 } 2460 break; 2461 case ETHTOOL_GRXCLSRLALL: 2462 rxnfc->data = 0; 2463 rxnfc->rule_cnt = 0; 2464 idr_for_each_entry(&chip->policies, policy, id) 2465 if (policy->port == port) 2466 rule_locs[rxnfc->rule_cnt++] = id; 2467 err = 0; 2468 break; 2469 default: 2470 err = -EOPNOTSUPP; 2471 break; 2472 } 2473 2474 mv88e6xxx_reg_unlock(chip); 2475 2476 return err; 2477 } 2478 2479 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2480 struct ethtool_rxnfc *rxnfc) 2481 { 2482 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2483 struct mv88e6xxx_chip *chip = ds->priv; 2484 struct mv88e6xxx_policy *policy; 2485 int err; 2486 2487 mv88e6xxx_reg_lock(chip); 2488 2489 switch (rxnfc->cmd) { 2490 case ETHTOOL_SRXCLSRLINS: 2491 err = mv88e6xxx_policy_insert(chip, port, fs); 2492 break; 2493 case ETHTOOL_SRXCLSRLDEL: 2494 err = -ENOENT; 2495 policy = idr_remove(&chip->policies, fs->location); 2496 if (policy) { 2497 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2498 err = mv88e6xxx_policy_apply(chip, port, policy); 2499 devm_kfree(chip->dev, policy); 2500 } 2501 break; 2502 default: 2503 err = -EOPNOTSUPP; 2504 break; 2505 } 2506 2507 mv88e6xxx_reg_unlock(chip); 2508 2509 return err; 2510 } 2511 2512 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2513 u16 vid) 2514 { 2515 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2516 u8 broadcast[ETH_ALEN]; 2517 2518 eth_broadcast_addr(broadcast); 2519 2520 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2521 } 2522 2523 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2524 { 2525 int port; 2526 int err; 2527 2528 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2529 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2530 struct net_device *brport; 2531 2532 if (dsa_is_unused_port(chip->ds, port)) 2533 continue; 2534 2535 brport = dsa_port_to_bridge_port(dp); 2536 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2537 /* Skip bridged user ports where broadcast 2538 * flooding is disabled. 2539 */ 2540 continue; 2541 2542 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2543 if (err) 2544 return err; 2545 } 2546 2547 return 0; 2548 } 2549 2550 struct mv88e6xxx_port_broadcast_sync_ctx { 2551 int port; 2552 bool flood; 2553 }; 2554 2555 static int 2556 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2557 const struct mv88e6xxx_vtu_entry *vlan, 2558 void *_ctx) 2559 { 2560 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2561 u8 broadcast[ETH_ALEN]; 2562 u8 state; 2563 2564 if (ctx->flood) 2565 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2566 else 2567 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2568 2569 eth_broadcast_addr(broadcast); 2570 2571 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2572 vlan->vid, state); 2573 } 2574 2575 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2576 bool flood) 2577 { 2578 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2579 .port = port, 2580 .flood = flood, 2581 }; 2582 struct mv88e6xxx_vtu_entry vid0 = { 2583 .vid = 0, 2584 }; 2585 int err; 2586 2587 /* Update the port's private database... */ 2588 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2589 if (err) 2590 return err; 2591 2592 /* ...and the database for all VLANs. */ 2593 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2594 &ctx); 2595 } 2596 2597 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2598 u16 vid, u8 member, bool warn) 2599 { 2600 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2601 struct mv88e6xxx_vtu_entry vlan; 2602 int i, err; 2603 2604 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2605 if (err) 2606 return err; 2607 2608 if (!vlan.valid) { 2609 memset(&vlan, 0, sizeof(vlan)); 2610 2611 if (vid == MV88E6XXX_VID_STANDALONE) 2612 vlan.policy = true; 2613 2614 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2615 if (err) 2616 return err; 2617 2618 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2619 if (i == port) 2620 vlan.member[i] = member; 2621 else 2622 vlan.member[i] = non_member; 2623 2624 vlan.vid = vid; 2625 vlan.valid = true; 2626 2627 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2628 if (err) 2629 return err; 2630 2631 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2632 if (err) 2633 return err; 2634 } else if (vlan.member[port] != member) { 2635 vlan.member[port] = member; 2636 2637 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2638 if (err) 2639 return err; 2640 } else if (warn) { 2641 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2642 port, vid); 2643 } 2644 2645 return 0; 2646 } 2647 2648 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2649 const struct switchdev_obj_port_vlan *vlan, 2650 struct netlink_ext_ack *extack) 2651 { 2652 struct mv88e6xxx_chip *chip = ds->priv; 2653 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2654 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2655 struct mv88e6xxx_port *p = &chip->ports[port]; 2656 bool warn; 2657 u8 member; 2658 int err; 2659 2660 if (!vlan->vid) 2661 return 0; 2662 2663 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2664 if (err) 2665 return err; 2666 2667 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2668 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2669 else if (untagged) 2670 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2671 else 2672 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2673 2674 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2675 * and then the CPU port. Do not warn for duplicates for the CPU port. 2676 */ 2677 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2678 2679 mv88e6xxx_reg_lock(chip); 2680 2681 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2682 if (err) { 2683 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2684 vlan->vid, untagged ? 'u' : 't'); 2685 goto out; 2686 } 2687 2688 if (pvid) { 2689 p->bridge_pvid.vid = vlan->vid; 2690 p->bridge_pvid.valid = true; 2691 2692 err = mv88e6xxx_port_commit_pvid(chip, port); 2693 if (err) 2694 goto out; 2695 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2696 /* The old pvid was reinstalled as a non-pvid VLAN */ 2697 p->bridge_pvid.valid = false; 2698 2699 err = mv88e6xxx_port_commit_pvid(chip, port); 2700 if (err) 2701 goto out; 2702 } 2703 2704 out: 2705 mv88e6xxx_reg_unlock(chip); 2706 2707 return err; 2708 } 2709 2710 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2711 int port, u16 vid) 2712 { 2713 struct mv88e6xxx_vtu_entry vlan; 2714 int i, err; 2715 2716 if (!vid) 2717 return 0; 2718 2719 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2720 if (err) 2721 return err; 2722 2723 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2724 * tell switchdev that this VLAN is likely handled in software. 2725 */ 2726 if (!vlan.valid || 2727 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2728 return -EOPNOTSUPP; 2729 2730 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2731 2732 /* keep the VLAN unless all ports are excluded */ 2733 vlan.valid = false; 2734 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2735 if (vlan.member[i] != 2736 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2737 vlan.valid = true; 2738 break; 2739 } 2740 } 2741 2742 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2743 if (err) 2744 return err; 2745 2746 if (!vlan.valid) { 2747 err = mv88e6xxx_mst_put(chip, vlan.sid); 2748 if (err) 2749 return err; 2750 } 2751 2752 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2753 } 2754 2755 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2756 const struct switchdev_obj_port_vlan *vlan) 2757 { 2758 struct mv88e6xxx_chip *chip = ds->priv; 2759 struct mv88e6xxx_port *p = &chip->ports[port]; 2760 int err = 0; 2761 u16 pvid; 2762 2763 if (!mv88e6xxx_max_vid(chip)) 2764 return -EOPNOTSUPP; 2765 2766 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2767 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2768 * switchdev workqueue to ensure that all FDB entries are deleted 2769 * before we remove the VLAN. 2770 */ 2771 dsa_flush_workqueue(); 2772 2773 mv88e6xxx_reg_lock(chip); 2774 2775 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2776 if (err) 2777 goto unlock; 2778 2779 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2780 if (err) 2781 goto unlock; 2782 2783 if (vlan->vid == pvid) { 2784 p->bridge_pvid.valid = false; 2785 2786 err = mv88e6xxx_port_commit_pvid(chip, port); 2787 if (err) 2788 goto unlock; 2789 } 2790 2791 unlock: 2792 mv88e6xxx_reg_unlock(chip); 2793 2794 return err; 2795 } 2796 2797 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2798 { 2799 struct mv88e6xxx_chip *chip = ds->priv; 2800 struct mv88e6xxx_vtu_entry vlan; 2801 int err; 2802 2803 mv88e6xxx_reg_lock(chip); 2804 2805 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2806 if (err) 2807 goto unlock; 2808 2809 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2810 2811 unlock: 2812 mv88e6xxx_reg_unlock(chip); 2813 2814 return err; 2815 } 2816 2817 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2818 struct dsa_bridge bridge, 2819 const struct switchdev_vlan_msti *msti) 2820 { 2821 struct mv88e6xxx_chip *chip = ds->priv; 2822 struct mv88e6xxx_vtu_entry vlan; 2823 u8 old_sid, new_sid; 2824 int err; 2825 2826 if (!mv88e6xxx_has_stu(chip)) 2827 return -EOPNOTSUPP; 2828 2829 mv88e6xxx_reg_lock(chip); 2830 2831 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2832 if (err) 2833 goto unlock; 2834 2835 if (!vlan.valid) { 2836 err = -EINVAL; 2837 goto unlock; 2838 } 2839 2840 old_sid = vlan.sid; 2841 2842 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2843 if (err) 2844 goto unlock; 2845 2846 if (new_sid != old_sid) { 2847 vlan.sid = new_sid; 2848 2849 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2850 if (err) { 2851 mv88e6xxx_mst_put(chip, new_sid); 2852 goto unlock; 2853 } 2854 } 2855 2856 err = mv88e6xxx_mst_put(chip, old_sid); 2857 2858 unlock: 2859 mv88e6xxx_reg_unlock(chip); 2860 return err; 2861 } 2862 2863 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2864 const unsigned char *addr, u16 vid, 2865 struct dsa_db db) 2866 { 2867 struct mv88e6xxx_chip *chip = ds->priv; 2868 int err; 2869 2870 mv88e6xxx_reg_lock(chip); 2871 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2872 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2873 mv88e6xxx_reg_unlock(chip); 2874 2875 return err; 2876 } 2877 2878 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2879 const unsigned char *addr, u16 vid, 2880 struct dsa_db db) 2881 { 2882 struct mv88e6xxx_chip *chip = ds->priv; 2883 int err; 2884 2885 mv88e6xxx_reg_lock(chip); 2886 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2887 mv88e6xxx_reg_unlock(chip); 2888 2889 return err; 2890 } 2891 2892 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2893 u16 fid, u16 vid, int port, 2894 dsa_fdb_dump_cb_t *cb, void *data) 2895 { 2896 struct mv88e6xxx_atu_entry addr; 2897 bool is_static; 2898 int err; 2899 2900 addr.state = 0; 2901 eth_broadcast_addr(addr.mac); 2902 2903 do { 2904 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2905 if (err) 2906 return err; 2907 2908 if (!addr.state) 2909 break; 2910 2911 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2912 continue; 2913 2914 if (!is_unicast_ether_addr(addr.mac)) 2915 continue; 2916 2917 is_static = (addr.state == 2918 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2919 err = cb(addr.mac, vid, is_static, data); 2920 if (err) 2921 return err; 2922 } while (!is_broadcast_ether_addr(addr.mac)); 2923 2924 return err; 2925 } 2926 2927 struct mv88e6xxx_port_db_dump_vlan_ctx { 2928 int port; 2929 dsa_fdb_dump_cb_t *cb; 2930 void *data; 2931 }; 2932 2933 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2934 const struct mv88e6xxx_vtu_entry *entry, 2935 void *_data) 2936 { 2937 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2938 2939 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2940 ctx->port, ctx->cb, ctx->data); 2941 } 2942 2943 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2944 dsa_fdb_dump_cb_t *cb, void *data) 2945 { 2946 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2947 .port = port, 2948 .cb = cb, 2949 .data = data, 2950 }; 2951 u16 fid; 2952 int err; 2953 2954 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2955 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2956 if (err) 2957 return err; 2958 2959 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2960 if (err) 2961 return err; 2962 2963 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2964 } 2965 2966 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2967 dsa_fdb_dump_cb_t *cb, void *data) 2968 { 2969 struct mv88e6xxx_chip *chip = ds->priv; 2970 int err; 2971 2972 mv88e6xxx_reg_lock(chip); 2973 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2974 mv88e6xxx_reg_unlock(chip); 2975 2976 return err; 2977 } 2978 2979 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2980 struct dsa_bridge bridge) 2981 { 2982 struct dsa_switch *ds = chip->ds; 2983 struct dsa_switch_tree *dst = ds->dst; 2984 struct dsa_port *dp; 2985 int err; 2986 2987 list_for_each_entry(dp, &dst->ports, list) { 2988 if (dsa_port_offloads_bridge(dp, &bridge)) { 2989 if (dp->ds == ds) { 2990 /* This is a local bridge group member, 2991 * remap its Port VLAN Map. 2992 */ 2993 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2994 if (err) 2995 return err; 2996 } else { 2997 /* This is an external bridge group member, 2998 * remap its cross-chip Port VLAN Table entry. 2999 */ 3000 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3001 dp->index); 3002 if (err) 3003 return err; 3004 } 3005 } 3006 } 3007 3008 return 0; 3009 } 3010 3011 /* Treat the software bridge as a virtual single-port switch behind the 3012 * CPU and map in the PVT. First dst->last_switch elements are taken by 3013 * physical switches, so start from beyond that range. 3014 */ 3015 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3016 unsigned int bridge_num) 3017 { 3018 u8 dev = bridge_num + ds->dst->last_switch; 3019 struct mv88e6xxx_chip *chip = ds->priv; 3020 3021 return mv88e6xxx_pvt_map(chip, dev, 0); 3022 } 3023 3024 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3025 struct dsa_bridge bridge, 3026 bool *tx_fwd_offload, 3027 struct netlink_ext_ack *extack) 3028 { 3029 struct mv88e6xxx_chip *chip = ds->priv; 3030 int err; 3031 3032 mv88e6xxx_reg_lock(chip); 3033 3034 err = mv88e6xxx_bridge_map(chip, bridge); 3035 if (err) 3036 goto unlock; 3037 3038 err = mv88e6xxx_port_set_map_da(chip, port, true); 3039 if (err) 3040 goto unlock; 3041 3042 err = mv88e6xxx_port_commit_pvid(chip, port); 3043 if (err) 3044 goto unlock; 3045 3046 if (mv88e6xxx_has_pvt(chip)) { 3047 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3048 if (err) 3049 goto unlock; 3050 3051 *tx_fwd_offload = true; 3052 } 3053 3054 unlock: 3055 mv88e6xxx_reg_unlock(chip); 3056 3057 return err; 3058 } 3059 3060 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3061 struct dsa_bridge bridge) 3062 { 3063 struct mv88e6xxx_chip *chip = ds->priv; 3064 int err; 3065 3066 mv88e6xxx_reg_lock(chip); 3067 3068 if (bridge.tx_fwd_offload && 3069 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3070 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3071 3072 if (mv88e6xxx_bridge_map(chip, bridge) || 3073 mv88e6xxx_port_vlan_map(chip, port)) 3074 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3075 3076 err = mv88e6xxx_port_set_map_da(chip, port, false); 3077 if (err) 3078 dev_err(ds->dev, 3079 "port %d failed to restore map-DA: %pe\n", 3080 port, ERR_PTR(err)); 3081 3082 err = mv88e6xxx_port_commit_pvid(chip, port); 3083 if (err) 3084 dev_err(ds->dev, 3085 "port %d failed to restore standalone pvid: %pe\n", 3086 port, ERR_PTR(err)); 3087 3088 mv88e6xxx_reg_unlock(chip); 3089 } 3090 3091 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3092 int tree_index, int sw_index, 3093 int port, struct dsa_bridge bridge, 3094 struct netlink_ext_ack *extack) 3095 { 3096 struct mv88e6xxx_chip *chip = ds->priv; 3097 int err; 3098 3099 if (tree_index != ds->dst->index) 3100 return 0; 3101 3102 mv88e6xxx_reg_lock(chip); 3103 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3104 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3105 mv88e6xxx_reg_unlock(chip); 3106 3107 return err; 3108 } 3109 3110 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3111 int tree_index, int sw_index, 3112 int port, struct dsa_bridge bridge) 3113 { 3114 struct mv88e6xxx_chip *chip = ds->priv; 3115 3116 if (tree_index != ds->dst->index) 3117 return; 3118 3119 mv88e6xxx_reg_lock(chip); 3120 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3121 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3122 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3123 mv88e6xxx_reg_unlock(chip); 3124 } 3125 3126 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3127 { 3128 if (chip->info->ops->reset) 3129 return chip->info->ops->reset(chip); 3130 3131 return 0; 3132 } 3133 3134 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3135 { 3136 struct gpio_desc *gpiod = chip->reset; 3137 int err; 3138 3139 /* If there is a GPIO connected to the reset pin, toggle it */ 3140 if (gpiod) { 3141 /* If the switch has just been reset and not yet completed 3142 * loading EEPROM, the reset may interrupt the I2C transaction 3143 * mid-byte, causing the first EEPROM read after the reset 3144 * from the wrong location resulting in the switch booting 3145 * to wrong mode and inoperable. 3146 * For this reason, switch families with EEPROM support 3147 * generally wait for EEPROM loads to complete as their pre- 3148 * and post-reset handlers. 3149 */ 3150 if (chip->info->ops->hardware_reset_pre) { 3151 err = chip->info->ops->hardware_reset_pre(chip); 3152 if (err) 3153 dev_err(chip->dev, "pre-reset error: %d\n", err); 3154 } 3155 3156 gpiod_set_value_cansleep(gpiod, 1); 3157 usleep_range(10000, 20000); 3158 gpiod_set_value_cansleep(gpiod, 0); 3159 usleep_range(10000, 20000); 3160 3161 if (chip->info->ops->hardware_reset_post) { 3162 err = chip->info->ops->hardware_reset_post(chip); 3163 if (err) 3164 dev_err(chip->dev, "post-reset error: %d\n", err); 3165 } 3166 } 3167 } 3168 3169 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3170 { 3171 int i, err; 3172 3173 /* Set all ports to the Disabled state */ 3174 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3175 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3176 if (err) 3177 return err; 3178 } 3179 3180 /* Wait for transmit queues to drain, 3181 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3182 */ 3183 usleep_range(2000, 4000); 3184 3185 return 0; 3186 } 3187 3188 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3189 { 3190 int err; 3191 3192 err = mv88e6xxx_disable_ports(chip); 3193 if (err) 3194 return err; 3195 3196 mv88e6xxx_hardware_reset(chip); 3197 3198 return mv88e6xxx_software_reset(chip); 3199 } 3200 3201 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3202 enum mv88e6xxx_frame_mode frame, 3203 enum mv88e6xxx_egress_mode egress, u16 etype) 3204 { 3205 int err; 3206 3207 if (!chip->info->ops->port_set_frame_mode) 3208 return -EOPNOTSUPP; 3209 3210 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3211 if (err) 3212 return err; 3213 3214 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3215 if (err) 3216 return err; 3217 3218 if (chip->info->ops->port_set_ether_type) 3219 return chip->info->ops->port_set_ether_type(chip, port, etype); 3220 3221 return 0; 3222 } 3223 3224 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3225 { 3226 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3227 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3228 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3229 } 3230 3231 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3232 { 3233 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3234 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3235 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3236 } 3237 3238 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3239 { 3240 return mv88e6xxx_set_port_mode(chip, port, 3241 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3242 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3243 ETH_P_EDSA); 3244 } 3245 3246 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3247 { 3248 if (dsa_is_dsa_port(chip->ds, port)) 3249 return mv88e6xxx_set_port_mode_dsa(chip, port); 3250 3251 if (dsa_is_user_port(chip->ds, port)) 3252 return mv88e6xxx_set_port_mode_normal(chip, port); 3253 3254 /* Setup CPU port mode depending on its supported tag format */ 3255 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3256 return mv88e6xxx_set_port_mode_dsa(chip, port); 3257 3258 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3259 return mv88e6xxx_set_port_mode_edsa(chip, port); 3260 3261 return -EINVAL; 3262 } 3263 3264 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3265 { 3266 bool message = dsa_is_dsa_port(chip->ds, port); 3267 3268 return mv88e6xxx_port_set_message_port(chip, port, message); 3269 } 3270 3271 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3272 { 3273 int err; 3274 3275 if (chip->info->ops->port_set_ucast_flood) { 3276 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3277 if (err) 3278 return err; 3279 } 3280 if (chip->info->ops->port_set_mcast_flood) { 3281 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3282 if (err) 3283 return err; 3284 } 3285 3286 return 0; 3287 } 3288 3289 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3290 enum mv88e6xxx_egress_direction direction, 3291 int port) 3292 { 3293 int err; 3294 3295 if (!chip->info->ops->set_egress_port) 3296 return -EOPNOTSUPP; 3297 3298 err = chip->info->ops->set_egress_port(chip, direction, port); 3299 if (err) 3300 return err; 3301 3302 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3303 chip->ingress_dest_port = port; 3304 else 3305 chip->egress_dest_port = port; 3306 3307 return 0; 3308 } 3309 3310 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3311 { 3312 struct dsa_switch *ds = chip->ds; 3313 int upstream_port; 3314 int err; 3315 3316 upstream_port = dsa_upstream_port(ds, port); 3317 if (chip->info->ops->port_set_upstream_port) { 3318 err = chip->info->ops->port_set_upstream_port(chip, port, 3319 upstream_port); 3320 if (err) 3321 return err; 3322 } 3323 3324 if (port == upstream_port) { 3325 if (chip->info->ops->set_cpu_port) { 3326 err = chip->info->ops->set_cpu_port(chip, 3327 upstream_port); 3328 if (err) 3329 return err; 3330 } 3331 3332 err = mv88e6xxx_set_egress_port(chip, 3333 MV88E6XXX_EGRESS_DIR_INGRESS, 3334 upstream_port); 3335 if (err && err != -EOPNOTSUPP) 3336 return err; 3337 3338 err = mv88e6xxx_set_egress_port(chip, 3339 MV88E6XXX_EGRESS_DIR_EGRESS, 3340 upstream_port); 3341 if (err && err != -EOPNOTSUPP) 3342 return err; 3343 } 3344 3345 return 0; 3346 } 3347 3348 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3349 { 3350 struct device_node *phy_handle = NULL; 3351 struct dsa_switch *ds = chip->ds; 3352 struct dsa_port *dp; 3353 int tx_amp; 3354 int err; 3355 u16 reg; 3356 3357 chip->ports[port].chip = chip; 3358 chip->ports[port].port = port; 3359 3360 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3361 SPEED_UNFORCED, DUPLEX_UNFORCED, 3362 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3363 if (err) 3364 return err; 3365 3366 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3367 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3368 * tunneling, determine priority by looking at 802.1p and IP 3369 * priority fields (IP prio has precedence), and set STP state 3370 * to Forwarding. 3371 * 3372 * If this is the CPU link, use DSA or EDSA tagging depending 3373 * on which tagging mode was configured. 3374 * 3375 * If this is a link to another switch, use DSA tagging mode. 3376 * 3377 * If this is the upstream port for this switch, enable 3378 * forwarding of unknown unicasts and multicasts. 3379 */ 3380 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3381 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3382 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3383 * by a USER port to the CPU port to allow snooping. 3384 */ 3385 if (dsa_is_user_port(ds, port)) 3386 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3387 3388 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3389 if (err) 3390 return err; 3391 3392 err = mv88e6xxx_setup_port_mode(chip, port); 3393 if (err) 3394 return err; 3395 3396 err = mv88e6xxx_setup_egress_floods(chip, port); 3397 if (err) 3398 return err; 3399 3400 /* Port Control 2: don't force a good FCS, set the MTU size to 3401 * 10222 bytes, disable 802.1q tags checking, don't discard 3402 * tagged or untagged frames on this port, skip destination 3403 * address lookup on user ports, disable ARP mirroring and don't 3404 * send a copy of all transmitted/received frames on this port 3405 * to the CPU. 3406 */ 3407 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3408 if (err) 3409 return err; 3410 3411 err = mv88e6xxx_setup_upstream_port(chip, port); 3412 if (err) 3413 return err; 3414 3415 /* On chips that support it, set all downstream DSA ports' 3416 * VLAN policy to TRAP. In combination with loading 3417 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3418 * provides a better isolation barrier between standalone 3419 * ports, as the ATU is bypassed on any intermediate switches 3420 * between the incoming port and the CPU. 3421 */ 3422 if (dsa_is_downstream_port(ds, port) && 3423 chip->info->ops->port_set_policy) { 3424 err = chip->info->ops->port_set_policy(chip, port, 3425 MV88E6XXX_POLICY_MAPPING_VTU, 3426 MV88E6XXX_POLICY_ACTION_TRAP); 3427 if (err) 3428 return err; 3429 } 3430 3431 /* User ports start out in standalone mode and 802.1Q is 3432 * therefore disabled. On DSA ports, all valid VIDs are always 3433 * loaded in the VTU - therefore, enable 802.1Q in order to take 3434 * advantage of VLAN policy on chips that supports it. 3435 */ 3436 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3437 dsa_is_user_port(ds, port) ? 3438 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3439 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3440 if (err) 3441 return err; 3442 3443 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3444 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3445 * the first free FID. This will be used as the private PVID for 3446 * unbridged ports. Shared (DSA and CPU) ports must also be 3447 * members of this VID, in order to trap all frames assigned to 3448 * it to the CPU. 3449 */ 3450 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3451 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3452 false); 3453 if (err) 3454 return err; 3455 3456 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3457 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3458 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3459 * as the private PVID on ports under a VLAN-unaware bridge. 3460 * Shared (DSA and CPU) ports must also be members of it, to translate 3461 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3462 * relying on their port default FID. 3463 */ 3464 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3465 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3466 false); 3467 if (err) 3468 return err; 3469 3470 if (chip->info->ops->port_set_jumbo_size) { 3471 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3472 if (err) 3473 return err; 3474 } 3475 3476 /* Port Association Vector: disable automatic address learning 3477 * on all user ports since they start out in standalone 3478 * mode. When joining a bridge, learning will be configured to 3479 * match the bridge port settings. Enable learning on all 3480 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3481 * learning process. 3482 * 3483 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3484 * and RefreshLocked. I.e. setup standard automatic learning. 3485 */ 3486 if (dsa_is_user_port(ds, port)) 3487 reg = 0; 3488 else 3489 reg = 1 << port; 3490 3491 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3492 reg); 3493 if (err) 3494 return err; 3495 3496 /* Egress rate control 2: disable egress rate control. */ 3497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3498 0x0000); 3499 if (err) 3500 return err; 3501 3502 if (chip->info->ops->port_pause_limit) { 3503 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3504 if (err) 3505 return err; 3506 } 3507 3508 if (chip->info->ops->port_disable_learn_limit) { 3509 err = chip->info->ops->port_disable_learn_limit(chip, port); 3510 if (err) 3511 return err; 3512 } 3513 3514 if (chip->info->ops->port_disable_pri_override) { 3515 err = chip->info->ops->port_disable_pri_override(chip, port); 3516 if (err) 3517 return err; 3518 } 3519 3520 if (chip->info->ops->port_tag_remap) { 3521 err = chip->info->ops->port_tag_remap(chip, port); 3522 if (err) 3523 return err; 3524 } 3525 3526 if (chip->info->ops->port_egress_rate_limiting) { 3527 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3528 if (err) 3529 return err; 3530 } 3531 3532 if (chip->info->ops->port_setup_message_port) { 3533 err = chip->info->ops->port_setup_message_port(chip, port); 3534 if (err) 3535 return err; 3536 } 3537 3538 if (chip->info->ops->serdes_set_tx_amplitude) { 3539 dp = dsa_to_port(ds, port); 3540 if (dp) 3541 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3542 3543 if (phy_handle && !of_property_read_u32(phy_handle, 3544 "tx-p2p-microvolt", 3545 &tx_amp)) 3546 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3547 port, tx_amp); 3548 if (phy_handle) { 3549 of_node_put(phy_handle); 3550 if (err) 3551 return err; 3552 } 3553 } 3554 3555 /* Port based VLAN map: give each port the same default address 3556 * database, and allow bidirectional communication between the 3557 * CPU and DSA port(s), and the other ports. 3558 */ 3559 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3560 if (err) 3561 return err; 3562 3563 err = mv88e6xxx_port_vlan_map(chip, port); 3564 if (err) 3565 return err; 3566 3567 /* Default VLAN ID and priority: don't set a default VLAN 3568 * ID, and set the default packet priority to zero. 3569 */ 3570 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3571 } 3572 3573 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3574 { 3575 struct mv88e6xxx_chip *chip = ds->priv; 3576 3577 if (chip->info->ops->port_set_jumbo_size) 3578 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3579 else if (chip->info->ops->set_max_frame_size) 3580 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3581 return ETH_DATA_LEN; 3582 } 3583 3584 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3585 { 3586 struct mv88e6xxx_chip *chip = ds->priv; 3587 int ret = 0; 3588 3589 /* For families where we don't know how to alter the MTU, 3590 * just accept any value up to ETH_DATA_LEN 3591 */ 3592 if (!chip->info->ops->port_set_jumbo_size && 3593 !chip->info->ops->set_max_frame_size) { 3594 if (new_mtu > ETH_DATA_LEN) 3595 return -EINVAL; 3596 3597 return 0; 3598 } 3599 3600 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3601 new_mtu += EDSA_HLEN; 3602 3603 mv88e6xxx_reg_lock(chip); 3604 if (chip->info->ops->port_set_jumbo_size) 3605 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3606 else if (chip->info->ops->set_max_frame_size) 3607 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3608 mv88e6xxx_reg_unlock(chip); 3609 3610 return ret; 3611 } 3612 3613 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3614 unsigned int ageing_time) 3615 { 3616 struct mv88e6xxx_chip *chip = ds->priv; 3617 int err; 3618 3619 mv88e6xxx_reg_lock(chip); 3620 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3621 mv88e6xxx_reg_unlock(chip); 3622 3623 return err; 3624 } 3625 3626 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3627 { 3628 int err; 3629 3630 /* Initialize the statistics unit */ 3631 if (chip->info->ops->stats_set_histogram) { 3632 err = chip->info->ops->stats_set_histogram(chip); 3633 if (err) 3634 return err; 3635 } 3636 3637 return mv88e6xxx_g1_stats_clear(chip); 3638 } 3639 3640 /* Check if the errata has already been applied. */ 3641 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3642 { 3643 int port; 3644 int err; 3645 u16 val; 3646 3647 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3648 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3649 if (err) { 3650 dev_err(chip->dev, 3651 "Error reading hidden register: %d\n", err); 3652 return false; 3653 } 3654 if (val != 0x01c0) 3655 return false; 3656 } 3657 3658 return true; 3659 } 3660 3661 /* The 6390 copper ports have an errata which require poking magic 3662 * values into undocumented hidden registers and then performing a 3663 * software reset. 3664 */ 3665 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3666 { 3667 int port; 3668 int err; 3669 3670 if (mv88e6390_setup_errata_applied(chip)) 3671 return 0; 3672 3673 /* Set the ports into blocking mode */ 3674 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3675 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3676 if (err) 3677 return err; 3678 } 3679 3680 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3681 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3682 if (err) 3683 return err; 3684 } 3685 3686 return mv88e6xxx_software_reset(chip); 3687 } 3688 3689 /* prod_id for switch families which do not have a PHY model number */ 3690 static const u16 family_prod_id_table[] = { 3691 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3692 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3693 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3694 }; 3695 3696 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3697 { 3698 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3699 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3700 u16 prod_id; 3701 u16 val; 3702 int err; 3703 3704 if (!chip->info->ops->phy_read) 3705 return -EOPNOTSUPP; 3706 3707 mv88e6xxx_reg_lock(chip); 3708 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3709 mv88e6xxx_reg_unlock(chip); 3710 3711 /* Some internal PHYs don't have a model number. */ 3712 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3713 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3714 prod_id = family_prod_id_table[chip->info->family]; 3715 if (prod_id) 3716 val |= prod_id >> 4; 3717 } 3718 3719 return err ? err : val; 3720 } 3721 3722 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3723 int reg) 3724 { 3725 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3726 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3727 u16 val; 3728 int err; 3729 3730 if (!chip->info->ops->phy_read_c45) 3731 return -ENODEV; 3732 3733 mv88e6xxx_reg_lock(chip); 3734 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3735 mv88e6xxx_reg_unlock(chip); 3736 3737 return err ? err : val; 3738 } 3739 3740 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3741 { 3742 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3743 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3744 int err; 3745 3746 if (!chip->info->ops->phy_write) 3747 return -EOPNOTSUPP; 3748 3749 mv88e6xxx_reg_lock(chip); 3750 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3751 mv88e6xxx_reg_unlock(chip); 3752 3753 return err; 3754 } 3755 3756 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3757 int reg, u16 val) 3758 { 3759 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3760 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3761 int err; 3762 3763 if (!chip->info->ops->phy_write_c45) 3764 return -EOPNOTSUPP; 3765 3766 mv88e6xxx_reg_lock(chip); 3767 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3768 mv88e6xxx_reg_unlock(chip); 3769 3770 return err; 3771 } 3772 3773 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3774 struct device_node *np, 3775 bool external) 3776 { 3777 static int index; 3778 struct mv88e6xxx_mdio_bus *mdio_bus; 3779 struct mii_bus *bus; 3780 int err; 3781 3782 if (external) { 3783 mv88e6xxx_reg_lock(chip); 3784 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3785 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3786 else 3787 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3788 mv88e6xxx_reg_unlock(chip); 3789 3790 if (err) 3791 return err; 3792 } 3793 3794 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3795 if (!bus) 3796 return -ENOMEM; 3797 3798 mdio_bus = bus->priv; 3799 mdio_bus->bus = bus; 3800 mdio_bus->chip = chip; 3801 INIT_LIST_HEAD(&mdio_bus->list); 3802 mdio_bus->external = external; 3803 3804 if (np) { 3805 bus->name = np->full_name; 3806 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3807 } else { 3808 bus->name = "mv88e6xxx SMI"; 3809 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3810 } 3811 3812 bus->read = mv88e6xxx_mdio_read; 3813 bus->write = mv88e6xxx_mdio_write; 3814 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3815 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3816 bus->parent = chip->dev; 3817 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3818 mv88e6xxx_num_ports(chip) - 1, 3819 chip->info->phy_base_addr); 3820 3821 if (!external) { 3822 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3823 if (err) 3824 goto out; 3825 } 3826 3827 err = of_mdiobus_register(bus, np); 3828 if (err) { 3829 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3830 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3831 goto out; 3832 } 3833 3834 if (external) 3835 list_add_tail(&mdio_bus->list, &chip->mdios); 3836 else 3837 list_add(&mdio_bus->list, &chip->mdios); 3838 3839 return 0; 3840 3841 out: 3842 mdiobus_free(bus); 3843 return err; 3844 } 3845 3846 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3847 3848 { 3849 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3850 struct mii_bus *bus; 3851 3852 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3853 bus = mdio_bus->bus; 3854 3855 if (!mdio_bus->external) 3856 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3857 3858 mdiobus_unregister(bus); 3859 mdiobus_free(bus); 3860 } 3861 } 3862 3863 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3864 { 3865 struct device_node *np = chip->dev->of_node; 3866 struct device_node *child; 3867 int err; 3868 3869 /* Always register one mdio bus for the internal/default mdio 3870 * bus. This maybe represented in the device tree, but is 3871 * optional. 3872 */ 3873 child = of_get_child_by_name(np, "mdio"); 3874 err = mv88e6xxx_mdio_register(chip, child, false); 3875 of_node_put(child); 3876 if (err) 3877 return err; 3878 3879 /* Walk the device tree, and see if there are any other nodes 3880 * which say they are compatible with the external mdio 3881 * bus. 3882 */ 3883 for_each_available_child_of_node(np, child) { 3884 if (of_device_is_compatible( 3885 child, "marvell,mv88e6xxx-mdio-external")) { 3886 err = mv88e6xxx_mdio_register(chip, child, true); 3887 if (err) { 3888 mv88e6xxx_mdios_unregister(chip); 3889 of_node_put(child); 3890 return err; 3891 } 3892 } 3893 } 3894 3895 return 0; 3896 } 3897 3898 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3899 { 3900 struct mv88e6xxx_chip *chip = ds->priv; 3901 3902 mv88e6xxx_teardown_devlink_params(ds); 3903 dsa_devlink_resources_unregister(ds); 3904 mv88e6xxx_teardown_devlink_regions_global(ds); 3905 mv88e6xxx_mdios_unregister(chip); 3906 } 3907 3908 static int mv88e6xxx_setup(struct dsa_switch *ds) 3909 { 3910 struct mv88e6xxx_chip *chip = ds->priv; 3911 u8 cmode; 3912 int err; 3913 int i; 3914 3915 err = mv88e6xxx_mdios_register(chip); 3916 if (err) 3917 return err; 3918 3919 chip->ds = ds; 3920 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3921 3922 /* Since virtual bridges are mapped in the PVT, the number we support 3923 * depends on the physical switch topology. We need to let DSA figure 3924 * that out and therefore we cannot set this at dsa_register_switch() 3925 * time. 3926 */ 3927 if (mv88e6xxx_has_pvt(chip)) 3928 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3929 ds->dst->last_switch - 1; 3930 3931 mv88e6xxx_reg_lock(chip); 3932 3933 if (chip->info->ops->setup_errata) { 3934 err = chip->info->ops->setup_errata(chip); 3935 if (err) 3936 goto unlock; 3937 } 3938 3939 /* Cache the cmode of each port. */ 3940 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3941 if (chip->info->ops->port_get_cmode) { 3942 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3943 if (err) 3944 goto unlock; 3945 3946 chip->ports[i].cmode = cmode; 3947 } 3948 } 3949 3950 err = mv88e6xxx_vtu_setup(chip); 3951 if (err) 3952 goto unlock; 3953 3954 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3955 * VTU, thereby also flushing the STU). 3956 */ 3957 err = mv88e6xxx_stu_setup(chip); 3958 if (err) 3959 goto unlock; 3960 3961 /* Setup Switch Port Registers */ 3962 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3963 if (dsa_is_unused_port(ds, i)) 3964 continue; 3965 3966 /* Prevent the use of an invalid port. */ 3967 if (mv88e6xxx_is_invalid_port(chip, i)) { 3968 dev_err(chip->dev, "port %d is invalid\n", i); 3969 err = -EINVAL; 3970 goto unlock; 3971 } 3972 3973 err = mv88e6xxx_setup_port(chip, i); 3974 if (err) 3975 goto unlock; 3976 } 3977 3978 err = mv88e6xxx_irl_setup(chip); 3979 if (err) 3980 goto unlock; 3981 3982 err = mv88e6xxx_mac_setup(chip); 3983 if (err) 3984 goto unlock; 3985 3986 err = mv88e6xxx_phy_setup(chip); 3987 if (err) 3988 goto unlock; 3989 3990 err = mv88e6xxx_pvt_setup(chip); 3991 if (err) 3992 goto unlock; 3993 3994 err = mv88e6xxx_atu_setup(chip); 3995 if (err) 3996 goto unlock; 3997 3998 err = mv88e6xxx_broadcast_setup(chip, 0); 3999 if (err) 4000 goto unlock; 4001 4002 err = mv88e6xxx_pot_setup(chip); 4003 if (err) 4004 goto unlock; 4005 4006 err = mv88e6xxx_rmu_setup(chip); 4007 if (err) 4008 goto unlock; 4009 4010 err = mv88e6xxx_rsvd2cpu_setup(chip); 4011 if (err) 4012 goto unlock; 4013 4014 err = mv88e6xxx_trunk_setup(chip); 4015 if (err) 4016 goto unlock; 4017 4018 err = mv88e6xxx_devmap_setup(chip); 4019 if (err) 4020 goto unlock; 4021 4022 err = mv88e6xxx_pri_setup(chip); 4023 if (err) 4024 goto unlock; 4025 4026 /* Setup PTP Hardware Clock and timestamping */ 4027 if (chip->info->ptp_support) { 4028 err = mv88e6xxx_ptp_setup(chip); 4029 if (err) 4030 goto unlock; 4031 4032 err = mv88e6xxx_hwtstamp_setup(chip); 4033 if (err) 4034 goto unlock; 4035 } 4036 4037 err = mv88e6xxx_stats_setup(chip); 4038 if (err) 4039 goto unlock; 4040 4041 unlock: 4042 mv88e6xxx_reg_unlock(chip); 4043 4044 if (err) 4045 goto out_mdios; 4046 4047 /* Have to be called without holding the register lock, since 4048 * they take the devlink lock, and we later take the locks in 4049 * the reverse order when getting/setting parameters or 4050 * resource occupancy. 4051 */ 4052 err = mv88e6xxx_setup_devlink_resources(ds); 4053 if (err) 4054 goto out_mdios; 4055 4056 err = mv88e6xxx_setup_devlink_params(ds); 4057 if (err) 4058 goto out_resources; 4059 4060 err = mv88e6xxx_setup_devlink_regions_global(ds); 4061 if (err) 4062 goto out_params; 4063 4064 return 0; 4065 4066 out_params: 4067 mv88e6xxx_teardown_devlink_params(ds); 4068 out_resources: 4069 dsa_devlink_resources_unregister(ds); 4070 out_mdios: 4071 mv88e6xxx_mdios_unregister(chip); 4072 4073 return err; 4074 } 4075 4076 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4077 { 4078 struct mv88e6xxx_chip *chip = ds->priv; 4079 int err; 4080 4081 if (chip->info->ops->pcs_ops && 4082 chip->info->ops->pcs_ops->pcs_init) { 4083 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4084 if (err) 4085 return err; 4086 } 4087 4088 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4089 } 4090 4091 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4092 { 4093 struct mv88e6xxx_chip *chip = ds->priv; 4094 4095 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4096 4097 if (chip->info->ops->pcs_ops && 4098 chip->info->ops->pcs_ops->pcs_teardown) 4099 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4100 } 4101 4102 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4103 { 4104 struct mv88e6xxx_chip *chip = ds->priv; 4105 4106 return chip->eeprom_len; 4107 } 4108 4109 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4110 struct ethtool_eeprom *eeprom, u8 *data) 4111 { 4112 struct mv88e6xxx_chip *chip = ds->priv; 4113 int err; 4114 4115 if (!chip->info->ops->get_eeprom) 4116 return -EOPNOTSUPP; 4117 4118 mv88e6xxx_reg_lock(chip); 4119 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4120 mv88e6xxx_reg_unlock(chip); 4121 4122 if (err) 4123 return err; 4124 4125 eeprom->magic = 0xc3ec4951; 4126 4127 return 0; 4128 } 4129 4130 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4131 struct ethtool_eeprom *eeprom, u8 *data) 4132 { 4133 struct mv88e6xxx_chip *chip = ds->priv; 4134 int err; 4135 4136 if (!chip->info->ops->set_eeprom) 4137 return -EOPNOTSUPP; 4138 4139 if (eeprom->magic != 0xc3ec4951) 4140 return -EINVAL; 4141 4142 mv88e6xxx_reg_lock(chip); 4143 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4144 mv88e6xxx_reg_unlock(chip); 4145 4146 return err; 4147 } 4148 4149 static const struct mv88e6xxx_ops mv88e6085_ops = { 4150 /* MV88E6XXX_FAMILY_6097 */ 4151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4153 .irl_init_all = mv88e6352_g2_irl_init_all, 4154 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4155 .phy_read = mv88e6185_phy_ppu_read, 4156 .phy_write = mv88e6185_phy_ppu_write, 4157 .port_set_link = mv88e6xxx_port_set_link, 4158 .port_sync_link = mv88e6xxx_port_sync_link, 4159 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4160 .port_tag_remap = mv88e6095_port_tag_remap, 4161 .port_set_policy = mv88e6352_port_set_policy, 4162 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4163 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4164 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4165 .port_set_ether_type = mv88e6351_port_set_ether_type, 4166 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4167 .port_pause_limit = mv88e6097_port_pause_limit, 4168 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4169 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4170 .port_get_cmode = mv88e6185_port_get_cmode, 4171 .port_setup_message_port = mv88e6xxx_setup_message_port, 4172 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4173 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4174 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4175 .stats_get_strings = mv88e6095_stats_get_strings, 4176 .stats_get_stat = mv88e6095_stats_get_stat, 4177 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4178 .set_egress_port = mv88e6095_g1_set_egress_port, 4179 .watchdog_ops = &mv88e6097_watchdog_ops, 4180 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4181 .pot_clear = mv88e6xxx_g2_pot_clear, 4182 .ppu_enable = mv88e6185_g1_ppu_enable, 4183 .ppu_disable = mv88e6185_g1_ppu_disable, 4184 .reset = mv88e6185_g1_reset, 4185 .rmu_disable = mv88e6085_g1_rmu_disable, 4186 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4187 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4188 .stu_getnext = mv88e6352_g1_stu_getnext, 4189 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4190 .phylink_get_caps = mv88e6185_phylink_get_caps, 4191 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4192 }; 4193 4194 static const struct mv88e6xxx_ops mv88e6095_ops = { 4195 /* MV88E6XXX_FAMILY_6095 */ 4196 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4197 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4198 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4199 .phy_read = mv88e6185_phy_ppu_read, 4200 .phy_write = mv88e6185_phy_ppu_write, 4201 .port_set_link = mv88e6xxx_port_set_link, 4202 .port_sync_link = mv88e6185_port_sync_link, 4203 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4204 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4205 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4206 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4207 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4208 .port_get_cmode = mv88e6185_port_get_cmode, 4209 .port_setup_message_port = mv88e6xxx_setup_message_port, 4210 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4211 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4212 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4213 .stats_get_strings = mv88e6095_stats_get_strings, 4214 .stats_get_stat = mv88e6095_stats_get_stat, 4215 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4216 .ppu_enable = mv88e6185_g1_ppu_enable, 4217 .ppu_disable = mv88e6185_g1_ppu_disable, 4218 .reset = mv88e6185_g1_reset, 4219 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4220 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4221 .phylink_get_caps = mv88e6095_phylink_get_caps, 4222 .pcs_ops = &mv88e6185_pcs_ops, 4223 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4224 }; 4225 4226 static const struct mv88e6xxx_ops mv88e6097_ops = { 4227 /* MV88E6XXX_FAMILY_6097 */ 4228 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4229 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4230 .irl_init_all = mv88e6352_g2_irl_init_all, 4231 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4232 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4233 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4234 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4235 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4236 .port_set_link = mv88e6xxx_port_set_link, 4237 .port_sync_link = mv88e6185_port_sync_link, 4238 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4239 .port_tag_remap = mv88e6095_port_tag_remap, 4240 .port_set_policy = mv88e6352_port_set_policy, 4241 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4242 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4243 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4244 .port_set_ether_type = mv88e6351_port_set_ether_type, 4245 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4246 .port_pause_limit = mv88e6097_port_pause_limit, 4247 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4248 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4249 .port_get_cmode = mv88e6185_port_get_cmode, 4250 .port_setup_message_port = mv88e6xxx_setup_message_port, 4251 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4252 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4253 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4254 .stats_get_strings = mv88e6095_stats_get_strings, 4255 .stats_get_stat = mv88e6095_stats_get_stat, 4256 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4257 .set_egress_port = mv88e6095_g1_set_egress_port, 4258 .watchdog_ops = &mv88e6097_watchdog_ops, 4259 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4260 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4261 .pot_clear = mv88e6xxx_g2_pot_clear, 4262 .reset = mv88e6352_g1_reset, 4263 .rmu_disable = mv88e6085_g1_rmu_disable, 4264 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4265 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4266 .phylink_get_caps = mv88e6095_phylink_get_caps, 4267 .pcs_ops = &mv88e6185_pcs_ops, 4268 .stu_getnext = mv88e6352_g1_stu_getnext, 4269 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4270 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4271 }; 4272 4273 static const struct mv88e6xxx_ops mv88e6123_ops = { 4274 /* MV88E6XXX_FAMILY_6165 */ 4275 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4276 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4277 .irl_init_all = mv88e6352_g2_irl_init_all, 4278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4279 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4280 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4281 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4282 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4283 .port_set_link = mv88e6xxx_port_set_link, 4284 .port_sync_link = mv88e6xxx_port_sync_link, 4285 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4286 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4287 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4288 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4289 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4290 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4291 .port_get_cmode = mv88e6185_port_get_cmode, 4292 .port_setup_message_port = mv88e6xxx_setup_message_port, 4293 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4294 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4295 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4296 .stats_get_strings = mv88e6095_stats_get_strings, 4297 .stats_get_stat = mv88e6095_stats_get_stat, 4298 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4299 .set_egress_port = mv88e6095_g1_set_egress_port, 4300 .watchdog_ops = &mv88e6097_watchdog_ops, 4301 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4302 .pot_clear = mv88e6xxx_g2_pot_clear, 4303 .reset = mv88e6352_g1_reset, 4304 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4305 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4306 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4307 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4308 .stu_getnext = mv88e6352_g1_stu_getnext, 4309 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4310 .phylink_get_caps = mv88e6185_phylink_get_caps, 4311 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4312 }; 4313 4314 static const struct mv88e6xxx_ops mv88e6131_ops = { 4315 /* MV88E6XXX_FAMILY_6185 */ 4316 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4317 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4318 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4319 .phy_read = mv88e6185_phy_ppu_read, 4320 .phy_write = mv88e6185_phy_ppu_write, 4321 .port_set_link = mv88e6xxx_port_set_link, 4322 .port_sync_link = mv88e6xxx_port_sync_link, 4323 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4324 .port_tag_remap = mv88e6095_port_tag_remap, 4325 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4326 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4327 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4328 .port_set_ether_type = mv88e6351_port_set_ether_type, 4329 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4330 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4331 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4332 .port_pause_limit = mv88e6097_port_pause_limit, 4333 .port_set_pause = mv88e6185_port_set_pause, 4334 .port_get_cmode = mv88e6185_port_get_cmode, 4335 .port_setup_message_port = mv88e6xxx_setup_message_port, 4336 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4337 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4338 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4339 .stats_get_strings = mv88e6095_stats_get_strings, 4340 .stats_get_stat = mv88e6095_stats_get_stat, 4341 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4342 .set_egress_port = mv88e6095_g1_set_egress_port, 4343 .watchdog_ops = &mv88e6097_watchdog_ops, 4344 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4345 .ppu_enable = mv88e6185_g1_ppu_enable, 4346 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4347 .ppu_disable = mv88e6185_g1_ppu_disable, 4348 .reset = mv88e6185_g1_reset, 4349 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4350 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4351 .phylink_get_caps = mv88e6185_phylink_get_caps, 4352 }; 4353 4354 static const struct mv88e6xxx_ops mv88e6141_ops = { 4355 /* MV88E6XXX_FAMILY_6341 */ 4356 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4357 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4358 .irl_init_all = mv88e6352_g2_irl_init_all, 4359 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4360 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4361 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4362 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4363 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4364 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4365 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4366 .port_set_link = mv88e6xxx_port_set_link, 4367 .port_sync_link = mv88e6xxx_port_sync_link, 4368 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4369 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4370 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4371 .port_tag_remap = mv88e6095_port_tag_remap, 4372 .port_set_policy = mv88e6352_port_set_policy, 4373 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4376 .port_set_ether_type = mv88e6351_port_set_ether_type, 4377 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4378 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4379 .port_pause_limit = mv88e6097_port_pause_limit, 4380 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4381 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4382 .port_get_cmode = mv88e6352_port_get_cmode, 4383 .port_set_cmode = mv88e6341_port_set_cmode, 4384 .port_setup_message_port = mv88e6xxx_setup_message_port, 4385 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4386 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4387 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4388 .stats_get_strings = mv88e6320_stats_get_strings, 4389 .stats_get_stat = mv88e6390_stats_get_stat, 4390 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4391 .set_egress_port = mv88e6390_g1_set_egress_port, 4392 .watchdog_ops = &mv88e6390_watchdog_ops, 4393 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4394 .pot_clear = mv88e6xxx_g2_pot_clear, 4395 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4396 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4397 .reset = mv88e6352_g1_reset, 4398 .rmu_disable = mv88e6390_g1_rmu_disable, 4399 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4400 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4401 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4402 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4403 .stu_getnext = mv88e6352_g1_stu_getnext, 4404 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4405 .serdes_get_lane = mv88e6341_serdes_get_lane, 4406 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4407 .gpio_ops = &mv88e6352_gpio_ops, 4408 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4409 .serdes_get_strings = mv88e6390_serdes_get_strings, 4410 .serdes_get_stats = mv88e6390_serdes_get_stats, 4411 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4412 .serdes_get_regs = mv88e6390_serdes_get_regs, 4413 .phylink_get_caps = mv88e6341_phylink_get_caps, 4414 .pcs_ops = &mv88e6390_pcs_ops, 4415 }; 4416 4417 static const struct mv88e6xxx_ops mv88e6161_ops = { 4418 /* MV88E6XXX_FAMILY_6165 */ 4419 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4420 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4421 .irl_init_all = mv88e6352_g2_irl_init_all, 4422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4423 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4424 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4425 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4426 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4427 .port_set_link = mv88e6xxx_port_set_link, 4428 .port_sync_link = mv88e6xxx_port_sync_link, 4429 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4430 .port_tag_remap = mv88e6095_port_tag_remap, 4431 .port_set_policy = mv88e6352_port_set_policy, 4432 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4433 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4434 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4435 .port_set_ether_type = mv88e6351_port_set_ether_type, 4436 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4437 .port_pause_limit = mv88e6097_port_pause_limit, 4438 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4439 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4440 .port_get_cmode = mv88e6185_port_get_cmode, 4441 .port_setup_message_port = mv88e6xxx_setup_message_port, 4442 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4443 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4444 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4445 .stats_get_strings = mv88e6095_stats_get_strings, 4446 .stats_get_stat = mv88e6095_stats_get_stat, 4447 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4448 .set_egress_port = mv88e6095_g1_set_egress_port, 4449 .watchdog_ops = &mv88e6097_watchdog_ops, 4450 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4451 .pot_clear = mv88e6xxx_g2_pot_clear, 4452 .reset = mv88e6352_g1_reset, 4453 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4454 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4455 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4456 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4457 .stu_getnext = mv88e6352_g1_stu_getnext, 4458 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4459 .avb_ops = &mv88e6165_avb_ops, 4460 .ptp_ops = &mv88e6165_ptp_ops, 4461 .phylink_get_caps = mv88e6185_phylink_get_caps, 4462 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4463 }; 4464 4465 static const struct mv88e6xxx_ops mv88e6165_ops = { 4466 /* MV88E6XXX_FAMILY_6165 */ 4467 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4468 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4469 .irl_init_all = mv88e6352_g2_irl_init_all, 4470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4471 .phy_read = mv88e6165_phy_read, 4472 .phy_write = mv88e6165_phy_write, 4473 .port_set_link = mv88e6xxx_port_set_link, 4474 .port_sync_link = mv88e6xxx_port_sync_link, 4475 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4476 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4477 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4478 .port_get_cmode = mv88e6185_port_get_cmode, 4479 .port_setup_message_port = mv88e6xxx_setup_message_port, 4480 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4481 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4482 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4483 .stats_get_strings = mv88e6095_stats_get_strings, 4484 .stats_get_stat = mv88e6095_stats_get_stat, 4485 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4486 .set_egress_port = mv88e6095_g1_set_egress_port, 4487 .watchdog_ops = &mv88e6097_watchdog_ops, 4488 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4489 .pot_clear = mv88e6xxx_g2_pot_clear, 4490 .reset = mv88e6352_g1_reset, 4491 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4492 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4493 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4494 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4495 .stu_getnext = mv88e6352_g1_stu_getnext, 4496 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4497 .avb_ops = &mv88e6165_avb_ops, 4498 .ptp_ops = &mv88e6165_ptp_ops, 4499 .phylink_get_caps = mv88e6185_phylink_get_caps, 4500 }; 4501 4502 static const struct mv88e6xxx_ops mv88e6171_ops = { 4503 /* MV88E6XXX_FAMILY_6351 */ 4504 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4505 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4506 .irl_init_all = mv88e6352_g2_irl_init_all, 4507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4508 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4509 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4510 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4511 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4512 .port_set_link = mv88e6xxx_port_set_link, 4513 .port_sync_link = mv88e6xxx_port_sync_link, 4514 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4515 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4516 .port_tag_remap = mv88e6095_port_tag_remap, 4517 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4518 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4519 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4520 .port_set_ether_type = mv88e6351_port_set_ether_type, 4521 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4522 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4523 .port_pause_limit = mv88e6097_port_pause_limit, 4524 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4525 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4526 .port_get_cmode = mv88e6352_port_get_cmode, 4527 .port_setup_message_port = mv88e6xxx_setup_message_port, 4528 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4529 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4530 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4531 .stats_get_strings = mv88e6095_stats_get_strings, 4532 .stats_get_stat = mv88e6095_stats_get_stat, 4533 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4534 .set_egress_port = mv88e6095_g1_set_egress_port, 4535 .watchdog_ops = &mv88e6097_watchdog_ops, 4536 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4537 .pot_clear = mv88e6xxx_g2_pot_clear, 4538 .reset = mv88e6352_g1_reset, 4539 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4540 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4541 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4542 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4543 .stu_getnext = mv88e6352_g1_stu_getnext, 4544 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4545 .phylink_get_caps = mv88e6351_phylink_get_caps, 4546 }; 4547 4548 static const struct mv88e6xxx_ops mv88e6172_ops = { 4549 /* MV88E6XXX_FAMILY_6352 */ 4550 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4551 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4552 .irl_init_all = mv88e6352_g2_irl_init_all, 4553 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4554 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4556 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4557 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4558 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4559 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4560 .port_set_link = mv88e6xxx_port_set_link, 4561 .port_sync_link = mv88e6xxx_port_sync_link, 4562 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4563 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4564 .port_tag_remap = mv88e6095_port_tag_remap, 4565 .port_set_policy = mv88e6352_port_set_policy, 4566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4567 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4568 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4569 .port_set_ether_type = mv88e6351_port_set_ether_type, 4570 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4571 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4572 .port_pause_limit = mv88e6097_port_pause_limit, 4573 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4574 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4575 .port_get_cmode = mv88e6352_port_get_cmode, 4576 .port_setup_message_port = mv88e6xxx_setup_message_port, 4577 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4578 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4579 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4580 .stats_get_strings = mv88e6095_stats_get_strings, 4581 .stats_get_stat = mv88e6095_stats_get_stat, 4582 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4583 .set_egress_port = mv88e6095_g1_set_egress_port, 4584 .watchdog_ops = &mv88e6097_watchdog_ops, 4585 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4586 .pot_clear = mv88e6xxx_g2_pot_clear, 4587 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4588 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4589 .reset = mv88e6352_g1_reset, 4590 .rmu_disable = mv88e6352_g1_rmu_disable, 4591 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4592 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4593 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4595 .stu_getnext = mv88e6352_g1_stu_getnext, 4596 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4597 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4598 .serdes_get_regs = mv88e6352_serdes_get_regs, 4599 .gpio_ops = &mv88e6352_gpio_ops, 4600 .phylink_get_caps = mv88e6352_phylink_get_caps, 4601 .pcs_ops = &mv88e6352_pcs_ops, 4602 }; 4603 4604 static const struct mv88e6xxx_ops mv88e6175_ops = { 4605 /* MV88E6XXX_FAMILY_6351 */ 4606 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4607 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4608 .irl_init_all = mv88e6352_g2_irl_init_all, 4609 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4610 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4611 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4612 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4613 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4614 .port_set_link = mv88e6xxx_port_set_link, 4615 .port_sync_link = mv88e6xxx_port_sync_link, 4616 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4617 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4618 .port_tag_remap = mv88e6095_port_tag_remap, 4619 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4620 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4621 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4622 .port_set_ether_type = mv88e6351_port_set_ether_type, 4623 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4624 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4625 .port_pause_limit = mv88e6097_port_pause_limit, 4626 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4627 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4628 .port_get_cmode = mv88e6352_port_get_cmode, 4629 .port_setup_message_port = mv88e6xxx_setup_message_port, 4630 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4631 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4632 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4633 .stats_get_strings = mv88e6095_stats_get_strings, 4634 .stats_get_stat = mv88e6095_stats_get_stat, 4635 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4636 .set_egress_port = mv88e6095_g1_set_egress_port, 4637 .watchdog_ops = &mv88e6097_watchdog_ops, 4638 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4639 .pot_clear = mv88e6xxx_g2_pot_clear, 4640 .reset = mv88e6352_g1_reset, 4641 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4642 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4643 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4644 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4645 .stu_getnext = mv88e6352_g1_stu_getnext, 4646 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4647 .phylink_get_caps = mv88e6351_phylink_get_caps, 4648 }; 4649 4650 static const struct mv88e6xxx_ops mv88e6176_ops = { 4651 /* MV88E6XXX_FAMILY_6352 */ 4652 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4653 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4654 .irl_init_all = mv88e6352_g2_irl_init_all, 4655 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4656 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4657 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4658 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4659 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4660 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4661 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4662 .port_set_link = mv88e6xxx_port_set_link, 4663 .port_sync_link = mv88e6xxx_port_sync_link, 4664 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4665 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4666 .port_tag_remap = mv88e6095_port_tag_remap, 4667 .port_set_policy = mv88e6352_port_set_policy, 4668 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4669 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4670 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4671 .port_set_ether_type = mv88e6351_port_set_ether_type, 4672 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4673 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4674 .port_pause_limit = mv88e6097_port_pause_limit, 4675 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4676 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4677 .port_get_cmode = mv88e6352_port_get_cmode, 4678 .port_setup_message_port = mv88e6xxx_setup_message_port, 4679 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4680 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4681 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4682 .stats_get_strings = mv88e6095_stats_get_strings, 4683 .stats_get_stat = mv88e6095_stats_get_stat, 4684 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4685 .set_egress_port = mv88e6095_g1_set_egress_port, 4686 .watchdog_ops = &mv88e6097_watchdog_ops, 4687 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4688 .pot_clear = mv88e6xxx_g2_pot_clear, 4689 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4690 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4691 .reset = mv88e6352_g1_reset, 4692 .rmu_disable = mv88e6352_g1_rmu_disable, 4693 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4694 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4695 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4697 .stu_getnext = mv88e6352_g1_stu_getnext, 4698 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4699 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4700 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4701 .serdes_get_regs = mv88e6352_serdes_get_regs, 4702 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4703 .gpio_ops = &mv88e6352_gpio_ops, 4704 .phylink_get_caps = mv88e6352_phylink_get_caps, 4705 .pcs_ops = &mv88e6352_pcs_ops, 4706 }; 4707 4708 static const struct mv88e6xxx_ops mv88e6185_ops = { 4709 /* MV88E6XXX_FAMILY_6185 */ 4710 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4711 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4712 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4713 .phy_read = mv88e6185_phy_ppu_read, 4714 .phy_write = mv88e6185_phy_ppu_write, 4715 .port_set_link = mv88e6xxx_port_set_link, 4716 .port_sync_link = mv88e6185_port_sync_link, 4717 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4718 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4719 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4720 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4721 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4722 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4723 .port_set_pause = mv88e6185_port_set_pause, 4724 .port_get_cmode = mv88e6185_port_get_cmode, 4725 .port_setup_message_port = mv88e6xxx_setup_message_port, 4726 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4727 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4728 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4729 .stats_get_strings = mv88e6095_stats_get_strings, 4730 .stats_get_stat = mv88e6095_stats_get_stat, 4731 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4732 .set_egress_port = mv88e6095_g1_set_egress_port, 4733 .watchdog_ops = &mv88e6097_watchdog_ops, 4734 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4735 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4736 .ppu_enable = mv88e6185_g1_ppu_enable, 4737 .ppu_disable = mv88e6185_g1_ppu_disable, 4738 .reset = mv88e6185_g1_reset, 4739 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4740 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4741 .phylink_get_caps = mv88e6185_phylink_get_caps, 4742 .pcs_ops = &mv88e6185_pcs_ops, 4743 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4744 }; 4745 4746 static const struct mv88e6xxx_ops mv88e6190_ops = { 4747 /* MV88E6XXX_FAMILY_6390 */ 4748 .setup_errata = mv88e6390_setup_errata, 4749 .irl_init_all = mv88e6390_g2_irl_init_all, 4750 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4751 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4752 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4753 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4754 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4755 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4756 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4757 .port_set_link = mv88e6xxx_port_set_link, 4758 .port_sync_link = mv88e6xxx_port_sync_link, 4759 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4760 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4761 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4762 .port_tag_remap = mv88e6390_port_tag_remap, 4763 .port_set_policy = mv88e6352_port_set_policy, 4764 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4765 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4766 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4767 .port_set_ether_type = mv88e6351_port_set_ether_type, 4768 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4769 .port_pause_limit = mv88e6390_port_pause_limit, 4770 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4771 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4772 .port_get_cmode = mv88e6352_port_get_cmode, 4773 .port_set_cmode = mv88e6390_port_set_cmode, 4774 .port_setup_message_port = mv88e6xxx_setup_message_port, 4775 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4776 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4777 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4778 .stats_get_strings = mv88e6320_stats_get_strings, 4779 .stats_get_stat = mv88e6390_stats_get_stat, 4780 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4781 .set_egress_port = mv88e6390_g1_set_egress_port, 4782 .watchdog_ops = &mv88e6390_watchdog_ops, 4783 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4784 .pot_clear = mv88e6xxx_g2_pot_clear, 4785 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4786 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4787 .reset = mv88e6352_g1_reset, 4788 .rmu_disable = mv88e6390_g1_rmu_disable, 4789 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4790 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4791 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4792 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4793 .stu_getnext = mv88e6390_g1_stu_getnext, 4794 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4795 .serdes_get_lane = mv88e6390_serdes_get_lane, 4796 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4797 .serdes_get_strings = mv88e6390_serdes_get_strings, 4798 .serdes_get_stats = mv88e6390_serdes_get_stats, 4799 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4800 .serdes_get_regs = mv88e6390_serdes_get_regs, 4801 .gpio_ops = &mv88e6352_gpio_ops, 4802 .phylink_get_caps = mv88e6390_phylink_get_caps, 4803 .pcs_ops = &mv88e6390_pcs_ops, 4804 }; 4805 4806 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4807 /* MV88E6XXX_FAMILY_6390 */ 4808 .setup_errata = mv88e6390_setup_errata, 4809 .irl_init_all = mv88e6390_g2_irl_init_all, 4810 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4811 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4812 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4813 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4814 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4815 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4816 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4817 .port_set_link = mv88e6xxx_port_set_link, 4818 .port_sync_link = mv88e6xxx_port_sync_link, 4819 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4820 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4821 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4822 .port_tag_remap = mv88e6390_port_tag_remap, 4823 .port_set_policy = mv88e6352_port_set_policy, 4824 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4825 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4826 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4827 .port_set_ether_type = mv88e6351_port_set_ether_type, 4828 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4829 .port_pause_limit = mv88e6390_port_pause_limit, 4830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4832 .port_get_cmode = mv88e6352_port_get_cmode, 4833 .port_set_cmode = mv88e6390x_port_set_cmode, 4834 .port_setup_message_port = mv88e6xxx_setup_message_port, 4835 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4836 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4837 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4838 .stats_get_strings = mv88e6320_stats_get_strings, 4839 .stats_get_stat = mv88e6390_stats_get_stat, 4840 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4841 .set_egress_port = mv88e6390_g1_set_egress_port, 4842 .watchdog_ops = &mv88e6390_watchdog_ops, 4843 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4844 .pot_clear = mv88e6xxx_g2_pot_clear, 4845 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4846 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4847 .reset = mv88e6352_g1_reset, 4848 .rmu_disable = mv88e6390_g1_rmu_disable, 4849 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4850 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4851 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4852 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4853 .stu_getnext = mv88e6390_g1_stu_getnext, 4854 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4855 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4856 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4857 .serdes_get_strings = mv88e6390_serdes_get_strings, 4858 .serdes_get_stats = mv88e6390_serdes_get_stats, 4859 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4860 .serdes_get_regs = mv88e6390_serdes_get_regs, 4861 .gpio_ops = &mv88e6352_gpio_ops, 4862 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4863 .pcs_ops = &mv88e6390_pcs_ops, 4864 }; 4865 4866 static const struct mv88e6xxx_ops mv88e6191_ops = { 4867 /* MV88E6XXX_FAMILY_6390 */ 4868 .setup_errata = mv88e6390_setup_errata, 4869 .irl_init_all = mv88e6390_g2_irl_init_all, 4870 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4871 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4872 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4873 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4874 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4875 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4876 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4877 .port_set_link = mv88e6xxx_port_set_link, 4878 .port_sync_link = mv88e6xxx_port_sync_link, 4879 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4880 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4881 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4882 .port_tag_remap = mv88e6390_port_tag_remap, 4883 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4884 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4885 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4886 .port_set_ether_type = mv88e6351_port_set_ether_type, 4887 .port_pause_limit = mv88e6390_port_pause_limit, 4888 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4889 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4890 .port_get_cmode = mv88e6352_port_get_cmode, 4891 .port_set_cmode = mv88e6390_port_set_cmode, 4892 .port_setup_message_port = mv88e6xxx_setup_message_port, 4893 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4894 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4895 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4896 .stats_get_strings = mv88e6320_stats_get_strings, 4897 .stats_get_stat = mv88e6390_stats_get_stat, 4898 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4899 .set_egress_port = mv88e6390_g1_set_egress_port, 4900 .watchdog_ops = &mv88e6390_watchdog_ops, 4901 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4902 .pot_clear = mv88e6xxx_g2_pot_clear, 4903 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4904 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4905 .reset = mv88e6352_g1_reset, 4906 .rmu_disable = mv88e6390_g1_rmu_disable, 4907 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4908 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4909 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4910 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4911 .stu_getnext = mv88e6390_g1_stu_getnext, 4912 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4913 .serdes_get_lane = mv88e6390_serdes_get_lane, 4914 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4915 .serdes_get_strings = mv88e6390_serdes_get_strings, 4916 .serdes_get_stats = mv88e6390_serdes_get_stats, 4917 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4918 .serdes_get_regs = mv88e6390_serdes_get_regs, 4919 .avb_ops = &mv88e6390_avb_ops, 4920 .ptp_ops = &mv88e6352_ptp_ops, 4921 .phylink_get_caps = mv88e6390_phylink_get_caps, 4922 .pcs_ops = &mv88e6390_pcs_ops, 4923 }; 4924 4925 static const struct mv88e6xxx_ops mv88e6240_ops = { 4926 /* MV88E6XXX_FAMILY_6352 */ 4927 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4928 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4929 .irl_init_all = mv88e6352_g2_irl_init_all, 4930 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4931 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4932 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4933 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4934 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4935 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4936 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4937 .port_set_link = mv88e6xxx_port_set_link, 4938 .port_sync_link = mv88e6xxx_port_sync_link, 4939 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4940 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4941 .port_tag_remap = mv88e6095_port_tag_remap, 4942 .port_set_policy = mv88e6352_port_set_policy, 4943 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4944 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4945 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4946 .port_set_ether_type = mv88e6351_port_set_ether_type, 4947 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4948 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4949 .port_pause_limit = mv88e6097_port_pause_limit, 4950 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4951 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4952 .port_get_cmode = mv88e6352_port_get_cmode, 4953 .port_setup_message_port = mv88e6xxx_setup_message_port, 4954 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4955 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4956 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4957 .stats_get_strings = mv88e6095_stats_get_strings, 4958 .stats_get_stat = mv88e6095_stats_get_stat, 4959 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4960 .set_egress_port = mv88e6095_g1_set_egress_port, 4961 .watchdog_ops = &mv88e6097_watchdog_ops, 4962 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4963 .pot_clear = mv88e6xxx_g2_pot_clear, 4964 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4965 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4966 .reset = mv88e6352_g1_reset, 4967 .rmu_disable = mv88e6352_g1_rmu_disable, 4968 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4969 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4970 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4971 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4972 .stu_getnext = mv88e6352_g1_stu_getnext, 4973 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4974 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4975 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4976 .serdes_get_regs = mv88e6352_serdes_get_regs, 4977 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4978 .gpio_ops = &mv88e6352_gpio_ops, 4979 .avb_ops = &mv88e6352_avb_ops, 4980 .ptp_ops = &mv88e6352_ptp_ops, 4981 .phylink_get_caps = mv88e6352_phylink_get_caps, 4982 .pcs_ops = &mv88e6352_pcs_ops, 4983 }; 4984 4985 static const struct mv88e6xxx_ops mv88e6250_ops = { 4986 /* MV88E6XXX_FAMILY_6250 */ 4987 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4988 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4989 .irl_init_all = mv88e6352_g2_irl_init_all, 4990 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4991 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4992 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4993 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4994 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4995 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4996 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4997 .port_set_link = mv88e6xxx_port_set_link, 4998 .port_sync_link = mv88e6xxx_port_sync_link, 4999 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5000 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5001 .port_tag_remap = mv88e6095_port_tag_remap, 5002 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5003 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5004 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5005 .port_set_ether_type = mv88e6351_port_set_ether_type, 5006 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5007 .port_pause_limit = mv88e6097_port_pause_limit, 5008 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5009 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5010 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5011 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5012 .stats_get_strings = mv88e6250_stats_get_strings, 5013 .stats_get_stat = mv88e6250_stats_get_stat, 5014 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5015 .set_egress_port = mv88e6095_g1_set_egress_port, 5016 .watchdog_ops = &mv88e6250_watchdog_ops, 5017 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5018 .pot_clear = mv88e6xxx_g2_pot_clear, 5019 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5020 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5021 .reset = mv88e6250_g1_reset, 5022 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5023 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5024 .avb_ops = &mv88e6352_avb_ops, 5025 .ptp_ops = &mv88e6250_ptp_ops, 5026 .phylink_get_caps = mv88e6250_phylink_get_caps, 5027 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5028 }; 5029 5030 static const struct mv88e6xxx_ops mv88e6290_ops = { 5031 /* MV88E6XXX_FAMILY_6390 */ 5032 .setup_errata = mv88e6390_setup_errata, 5033 .irl_init_all = mv88e6390_g2_irl_init_all, 5034 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5035 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5037 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5038 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5039 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5040 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5041 .port_set_link = mv88e6xxx_port_set_link, 5042 .port_sync_link = mv88e6xxx_port_sync_link, 5043 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5044 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5045 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5046 .port_tag_remap = mv88e6390_port_tag_remap, 5047 .port_set_policy = mv88e6352_port_set_policy, 5048 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5049 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5050 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5051 .port_set_ether_type = mv88e6351_port_set_ether_type, 5052 .port_pause_limit = mv88e6390_port_pause_limit, 5053 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5054 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5055 .port_get_cmode = mv88e6352_port_get_cmode, 5056 .port_set_cmode = mv88e6390_port_set_cmode, 5057 .port_setup_message_port = mv88e6xxx_setup_message_port, 5058 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5059 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5060 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5061 .stats_get_strings = mv88e6320_stats_get_strings, 5062 .stats_get_stat = mv88e6390_stats_get_stat, 5063 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5064 .set_egress_port = mv88e6390_g1_set_egress_port, 5065 .watchdog_ops = &mv88e6390_watchdog_ops, 5066 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5067 .pot_clear = mv88e6xxx_g2_pot_clear, 5068 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5069 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5070 .reset = mv88e6352_g1_reset, 5071 .rmu_disable = mv88e6390_g1_rmu_disable, 5072 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5073 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5074 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5075 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5076 .stu_getnext = mv88e6390_g1_stu_getnext, 5077 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5078 .serdes_get_lane = mv88e6390_serdes_get_lane, 5079 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5080 .serdes_get_strings = mv88e6390_serdes_get_strings, 5081 .serdes_get_stats = mv88e6390_serdes_get_stats, 5082 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5083 .serdes_get_regs = mv88e6390_serdes_get_regs, 5084 .gpio_ops = &mv88e6352_gpio_ops, 5085 .avb_ops = &mv88e6390_avb_ops, 5086 .ptp_ops = &mv88e6390_ptp_ops, 5087 .phylink_get_caps = mv88e6390_phylink_get_caps, 5088 .pcs_ops = &mv88e6390_pcs_ops, 5089 }; 5090 5091 static const struct mv88e6xxx_ops mv88e6320_ops = { 5092 /* MV88E6XXX_FAMILY_6320 */ 5093 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5094 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5095 .irl_init_all = mv88e6352_g2_irl_init_all, 5096 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5097 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5098 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5099 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5100 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5101 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5102 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5103 .port_set_link = mv88e6xxx_port_set_link, 5104 .port_sync_link = mv88e6xxx_port_sync_link, 5105 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5106 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5107 .port_tag_remap = mv88e6095_port_tag_remap, 5108 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5109 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5110 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5111 .port_set_ether_type = mv88e6351_port_set_ether_type, 5112 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5113 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5114 .port_pause_limit = mv88e6097_port_pause_limit, 5115 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5116 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5117 .port_get_cmode = mv88e6352_port_get_cmode, 5118 .port_setup_message_port = mv88e6xxx_setup_message_port, 5119 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5120 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5121 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5122 .stats_get_strings = mv88e6320_stats_get_strings, 5123 .stats_get_stat = mv88e6320_stats_get_stat, 5124 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5125 .set_egress_port = mv88e6095_g1_set_egress_port, 5126 .watchdog_ops = &mv88e6390_watchdog_ops, 5127 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5128 .pot_clear = mv88e6xxx_g2_pot_clear, 5129 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5130 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5131 .reset = mv88e6352_g1_reset, 5132 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5133 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5134 .gpio_ops = &mv88e6352_gpio_ops, 5135 .avb_ops = &mv88e6352_avb_ops, 5136 .ptp_ops = &mv88e6352_ptp_ops, 5137 .phylink_get_caps = mv88e6185_phylink_get_caps, 5138 }; 5139 5140 static const struct mv88e6xxx_ops mv88e6321_ops = { 5141 /* MV88E6XXX_FAMILY_6320 */ 5142 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5143 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5144 .irl_init_all = mv88e6352_g2_irl_init_all, 5145 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5146 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5147 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5148 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5149 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5150 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5151 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5152 .port_set_link = mv88e6xxx_port_set_link, 5153 .port_sync_link = mv88e6xxx_port_sync_link, 5154 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5155 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5156 .port_tag_remap = mv88e6095_port_tag_remap, 5157 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5158 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5159 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5160 .port_set_ether_type = mv88e6351_port_set_ether_type, 5161 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5162 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5163 .port_pause_limit = mv88e6097_port_pause_limit, 5164 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5165 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5166 .port_get_cmode = mv88e6352_port_get_cmode, 5167 .port_setup_message_port = mv88e6xxx_setup_message_port, 5168 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5169 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5170 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5171 .stats_get_strings = mv88e6320_stats_get_strings, 5172 .stats_get_stat = mv88e6320_stats_get_stat, 5173 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5174 .set_egress_port = mv88e6095_g1_set_egress_port, 5175 .watchdog_ops = &mv88e6390_watchdog_ops, 5176 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5177 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5178 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5179 .reset = mv88e6352_g1_reset, 5180 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5181 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5182 .gpio_ops = &mv88e6352_gpio_ops, 5183 .avb_ops = &mv88e6352_avb_ops, 5184 .ptp_ops = &mv88e6352_ptp_ops, 5185 .phylink_get_caps = mv88e6185_phylink_get_caps, 5186 }; 5187 5188 static const struct mv88e6xxx_ops mv88e6341_ops = { 5189 /* MV88E6XXX_FAMILY_6341 */ 5190 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5191 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5192 .irl_init_all = mv88e6352_g2_irl_init_all, 5193 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5194 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5195 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5196 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5197 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5198 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5199 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5200 .port_set_link = mv88e6xxx_port_set_link, 5201 .port_sync_link = mv88e6xxx_port_sync_link, 5202 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5203 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5204 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5205 .port_tag_remap = mv88e6095_port_tag_remap, 5206 .port_set_policy = mv88e6352_port_set_policy, 5207 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5208 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5209 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5210 .port_set_ether_type = mv88e6351_port_set_ether_type, 5211 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5212 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5213 .port_pause_limit = mv88e6097_port_pause_limit, 5214 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5215 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5216 .port_get_cmode = mv88e6352_port_get_cmode, 5217 .port_set_cmode = mv88e6341_port_set_cmode, 5218 .port_setup_message_port = mv88e6xxx_setup_message_port, 5219 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5220 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5221 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5222 .stats_get_strings = mv88e6320_stats_get_strings, 5223 .stats_get_stat = mv88e6390_stats_get_stat, 5224 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5225 .set_egress_port = mv88e6390_g1_set_egress_port, 5226 .watchdog_ops = &mv88e6390_watchdog_ops, 5227 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5228 .pot_clear = mv88e6xxx_g2_pot_clear, 5229 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5230 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5231 .reset = mv88e6352_g1_reset, 5232 .rmu_disable = mv88e6390_g1_rmu_disable, 5233 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5234 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5235 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5236 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5237 .stu_getnext = mv88e6352_g1_stu_getnext, 5238 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5239 .serdes_get_lane = mv88e6341_serdes_get_lane, 5240 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5241 .gpio_ops = &mv88e6352_gpio_ops, 5242 .avb_ops = &mv88e6390_avb_ops, 5243 .ptp_ops = &mv88e6352_ptp_ops, 5244 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5245 .serdes_get_strings = mv88e6390_serdes_get_strings, 5246 .serdes_get_stats = mv88e6390_serdes_get_stats, 5247 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5248 .serdes_get_regs = mv88e6390_serdes_get_regs, 5249 .phylink_get_caps = mv88e6341_phylink_get_caps, 5250 .pcs_ops = &mv88e6390_pcs_ops, 5251 }; 5252 5253 static const struct mv88e6xxx_ops mv88e6350_ops = { 5254 /* MV88E6XXX_FAMILY_6351 */ 5255 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5256 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5257 .irl_init_all = mv88e6352_g2_irl_init_all, 5258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5259 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5260 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5261 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5262 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5263 .port_set_link = mv88e6xxx_port_set_link, 5264 .port_sync_link = mv88e6xxx_port_sync_link, 5265 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5266 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5267 .port_tag_remap = mv88e6095_port_tag_remap, 5268 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5269 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5270 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5271 .port_set_ether_type = mv88e6351_port_set_ether_type, 5272 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5273 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5274 .port_pause_limit = mv88e6097_port_pause_limit, 5275 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5276 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5277 .port_get_cmode = mv88e6352_port_get_cmode, 5278 .port_setup_message_port = mv88e6xxx_setup_message_port, 5279 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5280 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5281 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5282 .stats_get_strings = mv88e6095_stats_get_strings, 5283 .stats_get_stat = mv88e6095_stats_get_stat, 5284 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5285 .set_egress_port = mv88e6095_g1_set_egress_port, 5286 .watchdog_ops = &mv88e6097_watchdog_ops, 5287 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5288 .pot_clear = mv88e6xxx_g2_pot_clear, 5289 .reset = mv88e6352_g1_reset, 5290 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5291 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5292 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5293 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5294 .stu_getnext = mv88e6352_g1_stu_getnext, 5295 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5296 .phylink_get_caps = mv88e6351_phylink_get_caps, 5297 }; 5298 5299 static const struct mv88e6xxx_ops mv88e6351_ops = { 5300 /* MV88E6XXX_FAMILY_6351 */ 5301 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5302 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5303 .irl_init_all = mv88e6352_g2_irl_init_all, 5304 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5305 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5306 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5307 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5308 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5309 .port_set_link = mv88e6xxx_port_set_link, 5310 .port_sync_link = mv88e6xxx_port_sync_link, 5311 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5312 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5313 .port_tag_remap = mv88e6095_port_tag_remap, 5314 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5315 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5316 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5317 .port_set_ether_type = mv88e6351_port_set_ether_type, 5318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5320 .port_pause_limit = mv88e6097_port_pause_limit, 5321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5323 .port_get_cmode = mv88e6352_port_get_cmode, 5324 .port_setup_message_port = mv88e6xxx_setup_message_port, 5325 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5326 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5327 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5328 .stats_get_strings = mv88e6095_stats_get_strings, 5329 .stats_get_stat = mv88e6095_stats_get_stat, 5330 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5331 .set_egress_port = mv88e6095_g1_set_egress_port, 5332 .watchdog_ops = &mv88e6097_watchdog_ops, 5333 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5334 .pot_clear = mv88e6xxx_g2_pot_clear, 5335 .reset = mv88e6352_g1_reset, 5336 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5337 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5338 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5339 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5340 .stu_getnext = mv88e6352_g1_stu_getnext, 5341 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5342 .avb_ops = &mv88e6352_avb_ops, 5343 .ptp_ops = &mv88e6352_ptp_ops, 5344 .phylink_get_caps = mv88e6351_phylink_get_caps, 5345 }; 5346 5347 static const struct mv88e6xxx_ops mv88e6352_ops = { 5348 /* MV88E6XXX_FAMILY_6352 */ 5349 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5350 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5351 .irl_init_all = mv88e6352_g2_irl_init_all, 5352 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5353 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5354 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5355 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5356 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5357 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5358 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5359 .port_set_link = mv88e6xxx_port_set_link, 5360 .port_sync_link = mv88e6xxx_port_sync_link, 5361 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5362 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5363 .port_tag_remap = mv88e6095_port_tag_remap, 5364 .port_set_policy = mv88e6352_port_set_policy, 5365 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5366 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5367 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5368 .port_set_ether_type = mv88e6351_port_set_ether_type, 5369 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5370 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5371 .port_pause_limit = mv88e6097_port_pause_limit, 5372 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5373 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5374 .port_get_cmode = mv88e6352_port_get_cmode, 5375 .port_setup_message_port = mv88e6xxx_setup_message_port, 5376 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5377 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5378 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5379 .stats_get_strings = mv88e6095_stats_get_strings, 5380 .stats_get_stat = mv88e6095_stats_get_stat, 5381 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5382 .set_egress_port = mv88e6095_g1_set_egress_port, 5383 .watchdog_ops = &mv88e6097_watchdog_ops, 5384 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5385 .pot_clear = mv88e6xxx_g2_pot_clear, 5386 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5387 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5388 .reset = mv88e6352_g1_reset, 5389 .rmu_disable = mv88e6352_g1_rmu_disable, 5390 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5391 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5392 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5393 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5394 .stu_getnext = mv88e6352_g1_stu_getnext, 5395 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5396 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5397 .gpio_ops = &mv88e6352_gpio_ops, 5398 .avb_ops = &mv88e6352_avb_ops, 5399 .ptp_ops = &mv88e6352_ptp_ops, 5400 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5401 .serdes_get_strings = mv88e6352_serdes_get_strings, 5402 .serdes_get_stats = mv88e6352_serdes_get_stats, 5403 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5404 .serdes_get_regs = mv88e6352_serdes_get_regs, 5405 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5406 .phylink_get_caps = mv88e6352_phylink_get_caps, 5407 .pcs_ops = &mv88e6352_pcs_ops, 5408 }; 5409 5410 static const struct mv88e6xxx_ops mv88e6390_ops = { 5411 /* MV88E6XXX_FAMILY_6390 */ 5412 .setup_errata = mv88e6390_setup_errata, 5413 .irl_init_all = mv88e6390_g2_irl_init_all, 5414 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5415 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5417 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5418 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5419 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5420 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5421 .port_set_link = mv88e6xxx_port_set_link, 5422 .port_sync_link = mv88e6xxx_port_sync_link, 5423 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5424 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5425 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5426 .port_tag_remap = mv88e6390_port_tag_remap, 5427 .port_set_policy = mv88e6352_port_set_policy, 5428 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5429 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5430 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5431 .port_set_ether_type = mv88e6351_port_set_ether_type, 5432 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5433 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5434 .port_pause_limit = mv88e6390_port_pause_limit, 5435 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5436 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5437 .port_get_cmode = mv88e6352_port_get_cmode, 5438 .port_set_cmode = mv88e6390_port_set_cmode, 5439 .port_setup_message_port = mv88e6xxx_setup_message_port, 5440 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5441 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5442 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5443 .stats_get_strings = mv88e6320_stats_get_strings, 5444 .stats_get_stat = mv88e6390_stats_get_stat, 5445 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5446 .set_egress_port = mv88e6390_g1_set_egress_port, 5447 .watchdog_ops = &mv88e6390_watchdog_ops, 5448 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5449 .pot_clear = mv88e6xxx_g2_pot_clear, 5450 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5451 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5452 .reset = mv88e6352_g1_reset, 5453 .rmu_disable = mv88e6390_g1_rmu_disable, 5454 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5455 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5456 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5457 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5458 .stu_getnext = mv88e6390_g1_stu_getnext, 5459 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5460 .serdes_get_lane = mv88e6390_serdes_get_lane, 5461 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5462 .gpio_ops = &mv88e6352_gpio_ops, 5463 .avb_ops = &mv88e6390_avb_ops, 5464 .ptp_ops = &mv88e6390_ptp_ops, 5465 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5466 .serdes_get_strings = mv88e6390_serdes_get_strings, 5467 .serdes_get_stats = mv88e6390_serdes_get_stats, 5468 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5469 .serdes_get_regs = mv88e6390_serdes_get_regs, 5470 .phylink_get_caps = mv88e6390_phylink_get_caps, 5471 .pcs_ops = &mv88e6390_pcs_ops, 5472 }; 5473 5474 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5475 /* MV88E6XXX_FAMILY_6390 */ 5476 .setup_errata = mv88e6390_setup_errata, 5477 .irl_init_all = mv88e6390_g2_irl_init_all, 5478 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5479 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5481 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5482 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5483 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5484 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5485 .port_set_link = mv88e6xxx_port_set_link, 5486 .port_sync_link = mv88e6xxx_port_sync_link, 5487 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5488 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5489 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5490 .port_tag_remap = mv88e6390_port_tag_remap, 5491 .port_set_policy = mv88e6352_port_set_policy, 5492 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5493 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5494 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5495 .port_set_ether_type = mv88e6351_port_set_ether_type, 5496 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5497 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5498 .port_pause_limit = mv88e6390_port_pause_limit, 5499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5501 .port_get_cmode = mv88e6352_port_get_cmode, 5502 .port_set_cmode = mv88e6390x_port_set_cmode, 5503 .port_setup_message_port = mv88e6xxx_setup_message_port, 5504 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5505 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5506 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5507 .stats_get_strings = mv88e6320_stats_get_strings, 5508 .stats_get_stat = mv88e6390_stats_get_stat, 5509 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5510 .set_egress_port = mv88e6390_g1_set_egress_port, 5511 .watchdog_ops = &mv88e6390_watchdog_ops, 5512 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5513 .pot_clear = mv88e6xxx_g2_pot_clear, 5514 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5515 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5516 .reset = mv88e6352_g1_reset, 5517 .rmu_disable = mv88e6390_g1_rmu_disable, 5518 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5519 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5520 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5521 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5522 .stu_getnext = mv88e6390_g1_stu_getnext, 5523 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5524 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5525 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5526 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5527 .serdes_get_strings = mv88e6390_serdes_get_strings, 5528 .serdes_get_stats = mv88e6390_serdes_get_stats, 5529 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5530 .serdes_get_regs = mv88e6390_serdes_get_regs, 5531 .gpio_ops = &mv88e6352_gpio_ops, 5532 .avb_ops = &mv88e6390_avb_ops, 5533 .ptp_ops = &mv88e6390_ptp_ops, 5534 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5535 .pcs_ops = &mv88e6390_pcs_ops, 5536 }; 5537 5538 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5539 /* MV88E6XXX_FAMILY_6393 */ 5540 .irl_init_all = mv88e6390_g2_irl_init_all, 5541 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5542 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5543 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5544 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5545 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5546 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5547 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5548 .port_set_link = mv88e6xxx_port_set_link, 5549 .port_sync_link = mv88e6xxx_port_sync_link, 5550 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5551 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5552 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5553 .port_tag_remap = mv88e6390_port_tag_remap, 5554 .port_set_policy = mv88e6393x_port_set_policy, 5555 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5556 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5557 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5558 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5559 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5560 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5561 .port_pause_limit = mv88e6390_port_pause_limit, 5562 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5563 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5564 .port_get_cmode = mv88e6352_port_get_cmode, 5565 .port_set_cmode = mv88e6393x_port_set_cmode, 5566 .port_setup_message_port = mv88e6xxx_setup_message_port, 5567 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5568 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5569 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5570 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5571 .stats_get_strings = mv88e6320_stats_get_strings, 5572 .stats_get_stat = mv88e6390_stats_get_stat, 5573 /* .set_cpu_port is missing because this family does not support a global 5574 * CPU port, only per port CPU port which is set via 5575 * .port_set_upstream_port method. 5576 */ 5577 .set_egress_port = mv88e6393x_set_egress_port, 5578 .watchdog_ops = &mv88e6393x_watchdog_ops, 5579 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5580 .pot_clear = mv88e6xxx_g2_pot_clear, 5581 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5582 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5583 .reset = mv88e6352_g1_reset, 5584 .rmu_disable = mv88e6390_g1_rmu_disable, 5585 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5586 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5587 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5588 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5589 .stu_getnext = mv88e6390_g1_stu_getnext, 5590 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5591 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5592 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5593 /* TODO: serdes stats */ 5594 .gpio_ops = &mv88e6352_gpio_ops, 5595 .avb_ops = &mv88e6390_avb_ops, 5596 .ptp_ops = &mv88e6352_ptp_ops, 5597 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5598 .pcs_ops = &mv88e6393x_pcs_ops, 5599 }; 5600 5601 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5602 [MV88E6020] = { 5603 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5604 .family = MV88E6XXX_FAMILY_6250, 5605 .name = "Marvell 88E6020", 5606 .num_databases = 64, 5607 /* Ports 2-4 are not routed to pins 5608 * => usable ports 0, 1, 5, 6 5609 */ 5610 .num_ports = 7, 5611 .num_internal_phys = 2, 5612 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5613 .max_vid = 4095, 5614 .port_base_addr = 0x8, 5615 .phy_base_addr = 0x0, 5616 .global1_addr = 0xf, 5617 .global2_addr = 0x7, 5618 .age_time_coeff = 15000, 5619 .g1_irqs = 9, 5620 .g2_irqs = 5, 5621 .atu_move_port_mask = 0xf, 5622 .dual_chip = true, 5623 .ops = &mv88e6250_ops, 5624 }, 5625 5626 [MV88E6071] = { 5627 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5628 .family = MV88E6XXX_FAMILY_6250, 5629 .name = "Marvell 88E6071", 5630 .num_databases = 64, 5631 .num_ports = 7, 5632 .num_internal_phys = 5, 5633 .max_vid = 4095, 5634 .port_base_addr = 0x08, 5635 .phy_base_addr = 0x00, 5636 .global1_addr = 0x0f, 5637 .global2_addr = 0x07, 5638 .age_time_coeff = 15000, 5639 .g1_irqs = 9, 5640 .g2_irqs = 5, 5641 .atu_move_port_mask = 0xf, 5642 .dual_chip = true, 5643 .ops = &mv88e6250_ops, 5644 }, 5645 5646 [MV88E6085] = { 5647 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5648 .family = MV88E6XXX_FAMILY_6097, 5649 .name = "Marvell 88E6085", 5650 .num_databases = 4096, 5651 .num_macs = 8192, 5652 .num_ports = 10, 5653 .num_internal_phys = 5, 5654 .max_vid = 4095, 5655 .max_sid = 63, 5656 .port_base_addr = 0x10, 5657 .phy_base_addr = 0x0, 5658 .global1_addr = 0x1b, 5659 .global2_addr = 0x1c, 5660 .age_time_coeff = 15000, 5661 .g1_irqs = 8, 5662 .g2_irqs = 10, 5663 .atu_move_port_mask = 0xf, 5664 .pvt = true, 5665 .multi_chip = true, 5666 .ops = &mv88e6085_ops, 5667 }, 5668 5669 [MV88E6095] = { 5670 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5671 .family = MV88E6XXX_FAMILY_6095, 5672 .name = "Marvell 88E6095/88E6095F", 5673 .num_databases = 256, 5674 .num_macs = 8192, 5675 .num_ports = 11, 5676 .num_internal_phys = 0, 5677 .max_vid = 4095, 5678 .port_base_addr = 0x10, 5679 .phy_base_addr = 0x0, 5680 .global1_addr = 0x1b, 5681 .global2_addr = 0x1c, 5682 .age_time_coeff = 15000, 5683 .g1_irqs = 8, 5684 .atu_move_port_mask = 0xf, 5685 .multi_chip = true, 5686 .ops = &mv88e6095_ops, 5687 }, 5688 5689 [MV88E6097] = { 5690 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5691 .family = MV88E6XXX_FAMILY_6097, 5692 .name = "Marvell 88E6097/88E6097F", 5693 .num_databases = 4096, 5694 .num_macs = 8192, 5695 .num_ports = 11, 5696 .num_internal_phys = 8, 5697 .max_vid = 4095, 5698 .max_sid = 63, 5699 .port_base_addr = 0x10, 5700 .phy_base_addr = 0x0, 5701 .global1_addr = 0x1b, 5702 .global2_addr = 0x1c, 5703 .age_time_coeff = 15000, 5704 .g1_irqs = 8, 5705 .g2_irqs = 10, 5706 .atu_move_port_mask = 0xf, 5707 .pvt = true, 5708 .multi_chip = true, 5709 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5710 .ops = &mv88e6097_ops, 5711 }, 5712 5713 [MV88E6123] = { 5714 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5715 .family = MV88E6XXX_FAMILY_6165, 5716 .name = "Marvell 88E6123", 5717 .num_databases = 4096, 5718 .num_macs = 1024, 5719 .num_ports = 3, 5720 .num_internal_phys = 5, 5721 .max_vid = 4095, 5722 .max_sid = 63, 5723 .port_base_addr = 0x10, 5724 .phy_base_addr = 0x0, 5725 .global1_addr = 0x1b, 5726 .global2_addr = 0x1c, 5727 .age_time_coeff = 15000, 5728 .g1_irqs = 9, 5729 .g2_irqs = 10, 5730 .atu_move_port_mask = 0xf, 5731 .pvt = true, 5732 .multi_chip = true, 5733 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5734 .ops = &mv88e6123_ops, 5735 }, 5736 5737 [MV88E6131] = { 5738 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5739 .family = MV88E6XXX_FAMILY_6185, 5740 .name = "Marvell 88E6131", 5741 .num_databases = 256, 5742 .num_macs = 8192, 5743 .num_ports = 8, 5744 .num_internal_phys = 0, 5745 .max_vid = 4095, 5746 .port_base_addr = 0x10, 5747 .phy_base_addr = 0x0, 5748 .global1_addr = 0x1b, 5749 .global2_addr = 0x1c, 5750 .age_time_coeff = 15000, 5751 .g1_irqs = 9, 5752 .atu_move_port_mask = 0xf, 5753 .multi_chip = true, 5754 .ops = &mv88e6131_ops, 5755 }, 5756 5757 [MV88E6141] = { 5758 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5759 .family = MV88E6XXX_FAMILY_6341, 5760 .name = "Marvell 88E6141", 5761 .num_databases = 256, 5762 .num_macs = 2048, 5763 .num_ports = 6, 5764 .num_internal_phys = 5, 5765 .num_gpio = 11, 5766 .max_vid = 4095, 5767 .max_sid = 63, 5768 .port_base_addr = 0x10, 5769 .phy_base_addr = 0x10, 5770 .global1_addr = 0x1b, 5771 .global2_addr = 0x1c, 5772 .age_time_coeff = 3750, 5773 .atu_move_port_mask = 0x1f, 5774 .g1_irqs = 9, 5775 .g2_irqs = 10, 5776 .pvt = true, 5777 .multi_chip = true, 5778 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5779 .ops = &mv88e6141_ops, 5780 }, 5781 5782 [MV88E6161] = { 5783 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5784 .family = MV88E6XXX_FAMILY_6165, 5785 .name = "Marvell 88E6161", 5786 .num_databases = 4096, 5787 .num_macs = 1024, 5788 .num_ports = 6, 5789 .num_internal_phys = 5, 5790 .max_vid = 4095, 5791 .max_sid = 63, 5792 .port_base_addr = 0x10, 5793 .phy_base_addr = 0x0, 5794 .global1_addr = 0x1b, 5795 .global2_addr = 0x1c, 5796 .age_time_coeff = 15000, 5797 .g1_irqs = 9, 5798 .g2_irqs = 10, 5799 .atu_move_port_mask = 0xf, 5800 .pvt = true, 5801 .multi_chip = true, 5802 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5803 .ptp_support = true, 5804 .ops = &mv88e6161_ops, 5805 }, 5806 5807 [MV88E6165] = { 5808 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5809 .family = MV88E6XXX_FAMILY_6165, 5810 .name = "Marvell 88E6165", 5811 .num_databases = 4096, 5812 .num_macs = 8192, 5813 .num_ports = 6, 5814 .num_internal_phys = 0, 5815 .max_vid = 4095, 5816 .max_sid = 63, 5817 .port_base_addr = 0x10, 5818 .phy_base_addr = 0x0, 5819 .global1_addr = 0x1b, 5820 .global2_addr = 0x1c, 5821 .age_time_coeff = 15000, 5822 .g1_irqs = 9, 5823 .g2_irqs = 10, 5824 .atu_move_port_mask = 0xf, 5825 .pvt = true, 5826 .multi_chip = true, 5827 .ptp_support = true, 5828 .ops = &mv88e6165_ops, 5829 }, 5830 5831 [MV88E6171] = { 5832 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5833 .family = MV88E6XXX_FAMILY_6351, 5834 .name = "Marvell 88E6171", 5835 .num_databases = 4096, 5836 .num_macs = 8192, 5837 .num_ports = 7, 5838 .num_internal_phys = 5, 5839 .max_vid = 4095, 5840 .max_sid = 63, 5841 .port_base_addr = 0x10, 5842 .phy_base_addr = 0x0, 5843 .global1_addr = 0x1b, 5844 .global2_addr = 0x1c, 5845 .age_time_coeff = 15000, 5846 .g1_irqs = 9, 5847 .g2_irqs = 10, 5848 .atu_move_port_mask = 0xf, 5849 .pvt = true, 5850 .multi_chip = true, 5851 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5852 .ops = &mv88e6171_ops, 5853 }, 5854 5855 [MV88E6172] = { 5856 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5857 .family = MV88E6XXX_FAMILY_6352, 5858 .name = "Marvell 88E6172", 5859 .num_databases = 4096, 5860 .num_macs = 8192, 5861 .num_ports = 7, 5862 .num_internal_phys = 5, 5863 .num_gpio = 15, 5864 .max_vid = 4095, 5865 .max_sid = 63, 5866 .port_base_addr = 0x10, 5867 .phy_base_addr = 0x0, 5868 .global1_addr = 0x1b, 5869 .global2_addr = 0x1c, 5870 .age_time_coeff = 15000, 5871 .g1_irqs = 9, 5872 .g2_irqs = 10, 5873 .atu_move_port_mask = 0xf, 5874 .pvt = true, 5875 .multi_chip = true, 5876 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5877 .ops = &mv88e6172_ops, 5878 }, 5879 5880 [MV88E6175] = { 5881 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5882 .family = MV88E6XXX_FAMILY_6351, 5883 .name = "Marvell 88E6175", 5884 .num_databases = 4096, 5885 .num_macs = 8192, 5886 .num_ports = 7, 5887 .num_internal_phys = 5, 5888 .max_vid = 4095, 5889 .max_sid = 63, 5890 .port_base_addr = 0x10, 5891 .phy_base_addr = 0x0, 5892 .global1_addr = 0x1b, 5893 .global2_addr = 0x1c, 5894 .age_time_coeff = 15000, 5895 .g1_irqs = 9, 5896 .g2_irqs = 10, 5897 .atu_move_port_mask = 0xf, 5898 .pvt = true, 5899 .multi_chip = true, 5900 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5901 .ops = &mv88e6175_ops, 5902 }, 5903 5904 [MV88E6176] = { 5905 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5906 .family = MV88E6XXX_FAMILY_6352, 5907 .name = "Marvell 88E6176", 5908 .num_databases = 4096, 5909 .num_macs = 8192, 5910 .num_ports = 7, 5911 .num_internal_phys = 5, 5912 .num_gpio = 15, 5913 .max_vid = 4095, 5914 .max_sid = 63, 5915 .port_base_addr = 0x10, 5916 .phy_base_addr = 0x0, 5917 .global1_addr = 0x1b, 5918 .global2_addr = 0x1c, 5919 .age_time_coeff = 15000, 5920 .g1_irqs = 9, 5921 .g2_irqs = 10, 5922 .atu_move_port_mask = 0xf, 5923 .pvt = true, 5924 .multi_chip = true, 5925 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5926 .ops = &mv88e6176_ops, 5927 }, 5928 5929 [MV88E6185] = { 5930 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5931 .family = MV88E6XXX_FAMILY_6185, 5932 .name = "Marvell 88E6185", 5933 .num_databases = 256, 5934 .num_macs = 8192, 5935 .num_ports = 10, 5936 .num_internal_phys = 0, 5937 .max_vid = 4095, 5938 .port_base_addr = 0x10, 5939 .phy_base_addr = 0x0, 5940 .global1_addr = 0x1b, 5941 .global2_addr = 0x1c, 5942 .age_time_coeff = 15000, 5943 .g1_irqs = 8, 5944 .atu_move_port_mask = 0xf, 5945 .multi_chip = true, 5946 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5947 .ops = &mv88e6185_ops, 5948 }, 5949 5950 [MV88E6190] = { 5951 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5952 .family = MV88E6XXX_FAMILY_6390, 5953 .name = "Marvell 88E6190", 5954 .num_databases = 4096, 5955 .num_macs = 16384, 5956 .num_ports = 11, /* 10 + Z80 */ 5957 .num_internal_phys = 9, 5958 .num_gpio = 16, 5959 .max_vid = 8191, 5960 .max_sid = 63, 5961 .port_base_addr = 0x0, 5962 .phy_base_addr = 0x0, 5963 .global1_addr = 0x1b, 5964 .global2_addr = 0x1c, 5965 .age_time_coeff = 3750, 5966 .g1_irqs = 9, 5967 .g2_irqs = 14, 5968 .pvt = true, 5969 .multi_chip = true, 5970 .atu_move_port_mask = 0x1f, 5971 .ops = &mv88e6190_ops, 5972 }, 5973 5974 [MV88E6190X] = { 5975 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5976 .family = MV88E6XXX_FAMILY_6390, 5977 .name = "Marvell 88E6190X", 5978 .num_databases = 4096, 5979 .num_macs = 16384, 5980 .num_ports = 11, /* 10 + Z80 */ 5981 .num_internal_phys = 9, 5982 .num_gpio = 16, 5983 .max_vid = 8191, 5984 .max_sid = 63, 5985 .port_base_addr = 0x0, 5986 .phy_base_addr = 0x0, 5987 .global1_addr = 0x1b, 5988 .global2_addr = 0x1c, 5989 .age_time_coeff = 3750, 5990 .g1_irqs = 9, 5991 .g2_irqs = 14, 5992 .atu_move_port_mask = 0x1f, 5993 .pvt = true, 5994 .multi_chip = true, 5995 .ops = &mv88e6190x_ops, 5996 }, 5997 5998 [MV88E6191] = { 5999 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6000 .family = MV88E6XXX_FAMILY_6390, 6001 .name = "Marvell 88E6191", 6002 .num_databases = 4096, 6003 .num_macs = 16384, 6004 .num_ports = 11, /* 10 + Z80 */ 6005 .num_internal_phys = 9, 6006 .max_vid = 8191, 6007 .max_sid = 63, 6008 .port_base_addr = 0x0, 6009 .phy_base_addr = 0x0, 6010 .global1_addr = 0x1b, 6011 .global2_addr = 0x1c, 6012 .age_time_coeff = 3750, 6013 .g1_irqs = 9, 6014 .g2_irqs = 14, 6015 .atu_move_port_mask = 0x1f, 6016 .pvt = true, 6017 .multi_chip = true, 6018 .ptp_support = true, 6019 .ops = &mv88e6191_ops, 6020 }, 6021 6022 [MV88E6191X] = { 6023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6024 .family = MV88E6XXX_FAMILY_6393, 6025 .name = "Marvell 88E6191X", 6026 .num_databases = 4096, 6027 .num_ports = 11, /* 10 + Z80 */ 6028 .num_internal_phys = 8, 6029 .internal_phys_offset = 1, 6030 .max_vid = 8191, 6031 .max_sid = 63, 6032 .port_base_addr = 0x0, 6033 .phy_base_addr = 0x0, 6034 .global1_addr = 0x1b, 6035 .global2_addr = 0x1c, 6036 .age_time_coeff = 3750, 6037 .g1_irqs = 10, 6038 .g2_irqs = 14, 6039 .atu_move_port_mask = 0x1f, 6040 .pvt = true, 6041 .multi_chip = true, 6042 .ptp_support = true, 6043 .ops = &mv88e6393x_ops, 6044 }, 6045 6046 [MV88E6193X] = { 6047 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6048 .family = MV88E6XXX_FAMILY_6393, 6049 .name = "Marvell 88E6193X", 6050 .num_databases = 4096, 6051 .num_ports = 11, /* 10 + Z80 */ 6052 .num_internal_phys = 8, 6053 .internal_phys_offset = 1, 6054 .max_vid = 8191, 6055 .max_sid = 63, 6056 .port_base_addr = 0x0, 6057 .phy_base_addr = 0x0, 6058 .global1_addr = 0x1b, 6059 .global2_addr = 0x1c, 6060 .age_time_coeff = 3750, 6061 .g1_irqs = 10, 6062 .g2_irqs = 14, 6063 .atu_move_port_mask = 0x1f, 6064 .pvt = true, 6065 .multi_chip = true, 6066 .ptp_support = true, 6067 .ops = &mv88e6393x_ops, 6068 }, 6069 6070 [MV88E6220] = { 6071 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6072 .family = MV88E6XXX_FAMILY_6250, 6073 .name = "Marvell 88E6220", 6074 .num_databases = 64, 6075 6076 /* Ports 2-4 are not routed to pins 6077 * => usable ports 0, 1, 5, 6 6078 */ 6079 .num_ports = 7, 6080 .num_internal_phys = 2, 6081 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6082 .max_vid = 4095, 6083 .port_base_addr = 0x08, 6084 .phy_base_addr = 0x00, 6085 .global1_addr = 0x0f, 6086 .global2_addr = 0x07, 6087 .age_time_coeff = 15000, 6088 .g1_irqs = 9, 6089 .g2_irqs = 10, 6090 .atu_move_port_mask = 0xf, 6091 .dual_chip = true, 6092 .ptp_support = true, 6093 .ops = &mv88e6250_ops, 6094 }, 6095 6096 [MV88E6240] = { 6097 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6098 .family = MV88E6XXX_FAMILY_6352, 6099 .name = "Marvell 88E6240", 6100 .num_databases = 4096, 6101 .num_macs = 8192, 6102 .num_ports = 7, 6103 .num_internal_phys = 5, 6104 .num_gpio = 15, 6105 .max_vid = 4095, 6106 .max_sid = 63, 6107 .port_base_addr = 0x10, 6108 .phy_base_addr = 0x0, 6109 .global1_addr = 0x1b, 6110 .global2_addr = 0x1c, 6111 .age_time_coeff = 15000, 6112 .g1_irqs = 9, 6113 .g2_irqs = 10, 6114 .atu_move_port_mask = 0xf, 6115 .pvt = true, 6116 .multi_chip = true, 6117 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6118 .ptp_support = true, 6119 .ops = &mv88e6240_ops, 6120 }, 6121 6122 [MV88E6250] = { 6123 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6124 .family = MV88E6XXX_FAMILY_6250, 6125 .name = "Marvell 88E6250", 6126 .num_databases = 64, 6127 .num_ports = 7, 6128 .num_internal_phys = 5, 6129 .max_vid = 4095, 6130 .port_base_addr = 0x08, 6131 .phy_base_addr = 0x00, 6132 .global1_addr = 0x0f, 6133 .global2_addr = 0x07, 6134 .age_time_coeff = 15000, 6135 .g1_irqs = 9, 6136 .g2_irqs = 10, 6137 .atu_move_port_mask = 0xf, 6138 .dual_chip = true, 6139 .ptp_support = true, 6140 .ops = &mv88e6250_ops, 6141 }, 6142 6143 [MV88E6290] = { 6144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6145 .family = MV88E6XXX_FAMILY_6390, 6146 .name = "Marvell 88E6290", 6147 .num_databases = 4096, 6148 .num_ports = 11, /* 10 + Z80 */ 6149 .num_internal_phys = 9, 6150 .num_gpio = 16, 6151 .max_vid = 8191, 6152 .max_sid = 63, 6153 .port_base_addr = 0x0, 6154 .phy_base_addr = 0x0, 6155 .global1_addr = 0x1b, 6156 .global2_addr = 0x1c, 6157 .age_time_coeff = 3750, 6158 .g1_irqs = 9, 6159 .g2_irqs = 14, 6160 .atu_move_port_mask = 0x1f, 6161 .pvt = true, 6162 .multi_chip = true, 6163 .ptp_support = true, 6164 .ops = &mv88e6290_ops, 6165 }, 6166 6167 [MV88E6320] = { 6168 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6169 .family = MV88E6XXX_FAMILY_6320, 6170 .name = "Marvell 88E6320", 6171 .num_databases = 4096, 6172 .num_macs = 8192, 6173 .num_ports = 7, 6174 .num_internal_phys = 5, 6175 .num_gpio = 15, 6176 .max_vid = 4095, 6177 .port_base_addr = 0x10, 6178 .phy_base_addr = 0x0, 6179 .global1_addr = 0x1b, 6180 .global2_addr = 0x1c, 6181 .age_time_coeff = 15000, 6182 .g1_irqs = 8, 6183 .g2_irqs = 10, 6184 .atu_move_port_mask = 0xf, 6185 .pvt = true, 6186 .multi_chip = true, 6187 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6188 .ptp_support = true, 6189 .ops = &mv88e6320_ops, 6190 }, 6191 6192 [MV88E6321] = { 6193 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6194 .family = MV88E6XXX_FAMILY_6320, 6195 .name = "Marvell 88E6321", 6196 .num_databases = 4096, 6197 .num_macs = 8192, 6198 .num_ports = 7, 6199 .num_internal_phys = 5, 6200 .num_gpio = 15, 6201 .max_vid = 4095, 6202 .port_base_addr = 0x10, 6203 .phy_base_addr = 0x0, 6204 .global1_addr = 0x1b, 6205 .global2_addr = 0x1c, 6206 .age_time_coeff = 15000, 6207 .g1_irqs = 8, 6208 .g2_irqs = 10, 6209 .atu_move_port_mask = 0xf, 6210 .multi_chip = true, 6211 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6212 .ptp_support = true, 6213 .ops = &mv88e6321_ops, 6214 }, 6215 6216 [MV88E6341] = { 6217 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6218 .family = MV88E6XXX_FAMILY_6341, 6219 .name = "Marvell 88E6341", 6220 .num_databases = 256, 6221 .num_macs = 2048, 6222 .num_internal_phys = 5, 6223 .num_ports = 6, 6224 .num_gpio = 11, 6225 .max_vid = 4095, 6226 .max_sid = 63, 6227 .port_base_addr = 0x10, 6228 .phy_base_addr = 0x10, 6229 .global1_addr = 0x1b, 6230 .global2_addr = 0x1c, 6231 .age_time_coeff = 3750, 6232 .atu_move_port_mask = 0x1f, 6233 .g1_irqs = 9, 6234 .g2_irqs = 10, 6235 .pvt = true, 6236 .multi_chip = true, 6237 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6238 .ptp_support = true, 6239 .ops = &mv88e6341_ops, 6240 }, 6241 6242 [MV88E6350] = { 6243 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6244 .family = MV88E6XXX_FAMILY_6351, 6245 .name = "Marvell 88E6350", 6246 .num_databases = 4096, 6247 .num_macs = 8192, 6248 .num_ports = 7, 6249 .num_internal_phys = 5, 6250 .max_vid = 4095, 6251 .max_sid = 63, 6252 .port_base_addr = 0x10, 6253 .phy_base_addr = 0x0, 6254 .global1_addr = 0x1b, 6255 .global2_addr = 0x1c, 6256 .age_time_coeff = 15000, 6257 .g1_irqs = 9, 6258 .g2_irqs = 10, 6259 .atu_move_port_mask = 0xf, 6260 .pvt = true, 6261 .multi_chip = true, 6262 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6263 .ops = &mv88e6350_ops, 6264 }, 6265 6266 [MV88E6351] = { 6267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6268 .family = MV88E6XXX_FAMILY_6351, 6269 .name = "Marvell 88E6351", 6270 .num_databases = 4096, 6271 .num_macs = 8192, 6272 .num_ports = 7, 6273 .num_internal_phys = 5, 6274 .max_vid = 4095, 6275 .max_sid = 63, 6276 .port_base_addr = 0x10, 6277 .phy_base_addr = 0x0, 6278 .global1_addr = 0x1b, 6279 .global2_addr = 0x1c, 6280 .age_time_coeff = 15000, 6281 .g1_irqs = 9, 6282 .g2_irqs = 10, 6283 .atu_move_port_mask = 0xf, 6284 .pvt = true, 6285 .multi_chip = true, 6286 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6287 .ops = &mv88e6351_ops, 6288 }, 6289 6290 [MV88E6352] = { 6291 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6292 .family = MV88E6XXX_FAMILY_6352, 6293 .name = "Marvell 88E6352", 6294 .num_databases = 4096, 6295 .num_macs = 8192, 6296 .num_ports = 7, 6297 .num_internal_phys = 5, 6298 .num_gpio = 15, 6299 .max_vid = 4095, 6300 .max_sid = 63, 6301 .port_base_addr = 0x10, 6302 .phy_base_addr = 0x0, 6303 .global1_addr = 0x1b, 6304 .global2_addr = 0x1c, 6305 .age_time_coeff = 15000, 6306 .g1_irqs = 9, 6307 .g2_irqs = 10, 6308 .atu_move_port_mask = 0xf, 6309 .pvt = true, 6310 .multi_chip = true, 6311 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6312 .ptp_support = true, 6313 .ops = &mv88e6352_ops, 6314 }, 6315 [MV88E6361] = { 6316 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6317 .family = MV88E6XXX_FAMILY_6393, 6318 .name = "Marvell 88E6361", 6319 .num_databases = 4096, 6320 .num_macs = 16384, 6321 .num_ports = 11, 6322 /* Ports 1, 2 and 8 are not routed */ 6323 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6324 .num_internal_phys = 5, 6325 .internal_phys_offset = 3, 6326 .max_vid = 4095, 6327 .max_sid = 63, 6328 .port_base_addr = 0x0, 6329 .phy_base_addr = 0x0, 6330 .global1_addr = 0x1b, 6331 .global2_addr = 0x1c, 6332 .age_time_coeff = 3750, 6333 .g1_irqs = 10, 6334 .g2_irqs = 14, 6335 .atu_move_port_mask = 0x1f, 6336 .pvt = true, 6337 .multi_chip = true, 6338 .ptp_support = true, 6339 .ops = &mv88e6393x_ops, 6340 }, 6341 [MV88E6390] = { 6342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6343 .family = MV88E6XXX_FAMILY_6390, 6344 .name = "Marvell 88E6390", 6345 .num_databases = 4096, 6346 .num_macs = 16384, 6347 .num_ports = 11, /* 10 + Z80 */ 6348 .num_internal_phys = 9, 6349 .num_gpio = 16, 6350 .max_vid = 8191, 6351 .max_sid = 63, 6352 .port_base_addr = 0x0, 6353 .phy_base_addr = 0x0, 6354 .global1_addr = 0x1b, 6355 .global2_addr = 0x1c, 6356 .age_time_coeff = 3750, 6357 .g1_irqs = 9, 6358 .g2_irqs = 14, 6359 .atu_move_port_mask = 0x1f, 6360 .pvt = true, 6361 .multi_chip = true, 6362 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6363 .ptp_support = true, 6364 .ops = &mv88e6390_ops, 6365 }, 6366 [MV88E6390X] = { 6367 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6368 .family = MV88E6XXX_FAMILY_6390, 6369 .name = "Marvell 88E6390X", 6370 .num_databases = 4096, 6371 .num_macs = 16384, 6372 .num_ports = 11, /* 10 + Z80 */ 6373 .num_internal_phys = 9, 6374 .num_gpio = 16, 6375 .max_vid = 8191, 6376 .max_sid = 63, 6377 .port_base_addr = 0x0, 6378 .phy_base_addr = 0x0, 6379 .global1_addr = 0x1b, 6380 .global2_addr = 0x1c, 6381 .age_time_coeff = 3750, 6382 .g1_irqs = 9, 6383 .g2_irqs = 14, 6384 .atu_move_port_mask = 0x1f, 6385 .pvt = true, 6386 .multi_chip = true, 6387 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6388 .ptp_support = true, 6389 .ops = &mv88e6390x_ops, 6390 }, 6391 6392 [MV88E6393X] = { 6393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6394 .family = MV88E6XXX_FAMILY_6393, 6395 .name = "Marvell 88E6393X", 6396 .num_databases = 4096, 6397 .num_ports = 11, /* 10 + Z80 */ 6398 .num_internal_phys = 8, 6399 .internal_phys_offset = 1, 6400 .max_vid = 8191, 6401 .max_sid = 63, 6402 .port_base_addr = 0x0, 6403 .phy_base_addr = 0x0, 6404 .global1_addr = 0x1b, 6405 .global2_addr = 0x1c, 6406 .age_time_coeff = 3750, 6407 .g1_irqs = 10, 6408 .g2_irqs = 14, 6409 .atu_move_port_mask = 0x1f, 6410 .pvt = true, 6411 .multi_chip = true, 6412 .ptp_support = true, 6413 .ops = &mv88e6393x_ops, 6414 }, 6415 }; 6416 6417 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6418 { 6419 int i; 6420 6421 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6422 if (mv88e6xxx_table[i].prod_num == prod_num) 6423 return &mv88e6xxx_table[i]; 6424 6425 return NULL; 6426 } 6427 6428 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6429 { 6430 const struct mv88e6xxx_info *info; 6431 unsigned int prod_num, rev; 6432 u16 id; 6433 int err; 6434 6435 mv88e6xxx_reg_lock(chip); 6436 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6437 mv88e6xxx_reg_unlock(chip); 6438 if (err) 6439 return err; 6440 6441 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6442 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6443 6444 info = mv88e6xxx_lookup_info(prod_num); 6445 if (!info) 6446 return -ENODEV; 6447 6448 /* Update the compatible info with the probed one */ 6449 chip->info = info; 6450 6451 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6452 chip->info->prod_num, chip->info->name, rev); 6453 6454 return 0; 6455 } 6456 6457 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6458 struct mdio_device *mdiodev) 6459 { 6460 int err; 6461 6462 /* dual_chip takes precedence over single/multi-chip modes */ 6463 if (chip->info->dual_chip) 6464 return -EINVAL; 6465 6466 /* If the mdio addr is 16 indicating the first port address of a switch 6467 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6468 * configured in single chip addressing mode. Setup the smi access as 6469 * single chip addressing mode and attempt to detect the model of the 6470 * switch, if this fails the device is not configured in single chip 6471 * addressing mode. 6472 */ 6473 if (mdiodev->addr != 16) 6474 return -EINVAL; 6475 6476 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6477 if (err) 6478 return err; 6479 6480 return mv88e6xxx_detect(chip); 6481 } 6482 6483 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6484 { 6485 struct mv88e6xxx_chip *chip; 6486 6487 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6488 if (!chip) 6489 return NULL; 6490 6491 chip->dev = dev; 6492 6493 mutex_init(&chip->reg_lock); 6494 INIT_LIST_HEAD(&chip->mdios); 6495 idr_init(&chip->policies); 6496 INIT_LIST_HEAD(&chip->msts); 6497 6498 return chip; 6499 } 6500 6501 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6502 int port, 6503 enum dsa_tag_protocol m) 6504 { 6505 struct mv88e6xxx_chip *chip = ds->priv; 6506 6507 return chip->tag_protocol; 6508 } 6509 6510 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6511 enum dsa_tag_protocol proto) 6512 { 6513 struct mv88e6xxx_chip *chip = ds->priv; 6514 enum dsa_tag_protocol old_protocol; 6515 struct dsa_port *cpu_dp; 6516 int err; 6517 6518 switch (proto) { 6519 case DSA_TAG_PROTO_EDSA: 6520 switch (chip->info->edsa_support) { 6521 case MV88E6XXX_EDSA_UNSUPPORTED: 6522 return -EPROTONOSUPPORT; 6523 case MV88E6XXX_EDSA_UNDOCUMENTED: 6524 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6525 fallthrough; 6526 case MV88E6XXX_EDSA_SUPPORTED: 6527 break; 6528 } 6529 break; 6530 case DSA_TAG_PROTO_DSA: 6531 break; 6532 default: 6533 return -EPROTONOSUPPORT; 6534 } 6535 6536 old_protocol = chip->tag_protocol; 6537 chip->tag_protocol = proto; 6538 6539 mv88e6xxx_reg_lock(chip); 6540 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6541 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6542 if (err) { 6543 mv88e6xxx_reg_unlock(chip); 6544 goto unwind; 6545 } 6546 } 6547 mv88e6xxx_reg_unlock(chip); 6548 6549 return 0; 6550 6551 unwind: 6552 chip->tag_protocol = old_protocol; 6553 6554 mv88e6xxx_reg_lock(chip); 6555 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6556 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6557 mv88e6xxx_reg_unlock(chip); 6558 6559 return err; 6560 } 6561 6562 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6563 const struct switchdev_obj_port_mdb *mdb, 6564 struct dsa_db db) 6565 { 6566 struct mv88e6xxx_chip *chip = ds->priv; 6567 int err; 6568 6569 mv88e6xxx_reg_lock(chip); 6570 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6571 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6572 mv88e6xxx_reg_unlock(chip); 6573 6574 return err; 6575 } 6576 6577 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6578 const struct switchdev_obj_port_mdb *mdb, 6579 struct dsa_db db) 6580 { 6581 struct mv88e6xxx_chip *chip = ds->priv; 6582 int err; 6583 6584 mv88e6xxx_reg_lock(chip); 6585 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6586 mv88e6xxx_reg_unlock(chip); 6587 6588 return err; 6589 } 6590 6591 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6592 struct dsa_mall_mirror_tc_entry *mirror, 6593 bool ingress, 6594 struct netlink_ext_ack *extack) 6595 { 6596 enum mv88e6xxx_egress_direction direction = ingress ? 6597 MV88E6XXX_EGRESS_DIR_INGRESS : 6598 MV88E6XXX_EGRESS_DIR_EGRESS; 6599 struct mv88e6xxx_chip *chip = ds->priv; 6600 bool other_mirrors = false; 6601 int i; 6602 int err; 6603 6604 mutex_lock(&chip->reg_lock); 6605 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6606 mirror->to_local_port) { 6607 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6608 other_mirrors |= ingress ? 6609 chip->ports[i].mirror_ingress : 6610 chip->ports[i].mirror_egress; 6611 6612 /* Can't change egress port when other mirror is active */ 6613 if (other_mirrors) { 6614 err = -EBUSY; 6615 goto out; 6616 } 6617 6618 err = mv88e6xxx_set_egress_port(chip, direction, 6619 mirror->to_local_port); 6620 if (err) 6621 goto out; 6622 } 6623 6624 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6625 out: 6626 mutex_unlock(&chip->reg_lock); 6627 6628 return err; 6629 } 6630 6631 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6632 struct dsa_mall_mirror_tc_entry *mirror) 6633 { 6634 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6635 MV88E6XXX_EGRESS_DIR_INGRESS : 6636 MV88E6XXX_EGRESS_DIR_EGRESS; 6637 struct mv88e6xxx_chip *chip = ds->priv; 6638 bool other_mirrors = false; 6639 int i; 6640 6641 mutex_lock(&chip->reg_lock); 6642 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6643 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6644 6645 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6646 other_mirrors |= mirror->ingress ? 6647 chip->ports[i].mirror_ingress : 6648 chip->ports[i].mirror_egress; 6649 6650 /* Reset egress port when no other mirror is active */ 6651 if (!other_mirrors) { 6652 if (mv88e6xxx_set_egress_port(chip, direction, 6653 dsa_upstream_port(ds, port))) 6654 dev_err(ds->dev, "failed to set egress port\n"); 6655 } 6656 6657 mutex_unlock(&chip->reg_lock); 6658 } 6659 6660 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6661 struct switchdev_brport_flags flags, 6662 struct netlink_ext_ack *extack) 6663 { 6664 struct mv88e6xxx_chip *chip = ds->priv; 6665 const struct mv88e6xxx_ops *ops; 6666 6667 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6668 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6669 return -EINVAL; 6670 6671 ops = chip->info->ops; 6672 6673 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6674 return -EINVAL; 6675 6676 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6677 return -EINVAL; 6678 6679 return 0; 6680 } 6681 6682 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6683 struct switchdev_brport_flags flags, 6684 struct netlink_ext_ack *extack) 6685 { 6686 struct mv88e6xxx_chip *chip = ds->priv; 6687 int err = 0; 6688 6689 mv88e6xxx_reg_lock(chip); 6690 6691 if (flags.mask & BR_LEARNING) { 6692 bool learning = !!(flags.val & BR_LEARNING); 6693 u16 pav = learning ? (1 << port) : 0; 6694 6695 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6696 if (err) 6697 goto out; 6698 } 6699 6700 if (flags.mask & BR_FLOOD) { 6701 bool unicast = !!(flags.val & BR_FLOOD); 6702 6703 err = chip->info->ops->port_set_ucast_flood(chip, port, 6704 unicast); 6705 if (err) 6706 goto out; 6707 } 6708 6709 if (flags.mask & BR_MCAST_FLOOD) { 6710 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6711 6712 err = chip->info->ops->port_set_mcast_flood(chip, port, 6713 multicast); 6714 if (err) 6715 goto out; 6716 } 6717 6718 if (flags.mask & BR_BCAST_FLOOD) { 6719 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6720 6721 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6722 if (err) 6723 goto out; 6724 } 6725 6726 if (flags.mask & BR_PORT_MAB) { 6727 bool mab = !!(flags.val & BR_PORT_MAB); 6728 6729 mv88e6xxx_port_set_mab(chip, port, mab); 6730 } 6731 6732 if (flags.mask & BR_PORT_LOCKED) { 6733 bool locked = !!(flags.val & BR_PORT_LOCKED); 6734 6735 err = mv88e6xxx_port_set_lock(chip, port, locked); 6736 if (err) 6737 goto out; 6738 } 6739 out: 6740 mv88e6xxx_reg_unlock(chip); 6741 6742 return err; 6743 } 6744 6745 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6746 struct dsa_lag lag, 6747 struct netdev_lag_upper_info *info, 6748 struct netlink_ext_ack *extack) 6749 { 6750 struct mv88e6xxx_chip *chip = ds->priv; 6751 struct dsa_port *dp; 6752 int members = 0; 6753 6754 if (!mv88e6xxx_has_lag(chip)) { 6755 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6756 return false; 6757 } 6758 6759 if (!lag.id) 6760 return false; 6761 6762 dsa_lag_foreach_port(dp, ds->dst, &lag) 6763 /* Includes the port joining the LAG */ 6764 members++; 6765 6766 if (members > 8) { 6767 NL_SET_ERR_MSG_MOD(extack, 6768 "Cannot offload more than 8 LAG ports"); 6769 return false; 6770 } 6771 6772 /* We could potentially relax this to include active 6773 * backup in the future. 6774 */ 6775 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6776 NL_SET_ERR_MSG_MOD(extack, 6777 "Can only offload LAG using hash TX type"); 6778 return false; 6779 } 6780 6781 /* Ideally we would also validate that the hash type matches 6782 * the hardware. Alas, this is always set to unknown on team 6783 * interfaces. 6784 */ 6785 return true; 6786 } 6787 6788 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6789 { 6790 struct mv88e6xxx_chip *chip = ds->priv; 6791 struct dsa_port *dp; 6792 u16 map = 0; 6793 int id; 6794 6795 /* DSA LAG IDs are one-based, hardware is zero-based */ 6796 id = lag.id - 1; 6797 6798 /* Build the map of all ports to distribute flows destined for 6799 * this LAG. This can be either a local user port, or a DSA 6800 * port if the LAG port is on a remote chip. 6801 */ 6802 dsa_lag_foreach_port(dp, ds->dst, &lag) 6803 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6804 6805 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6806 } 6807 6808 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6809 /* Row number corresponds to the number of active members in a 6810 * LAG. Each column states which of the eight hash buckets are 6811 * mapped to the column:th port in the LAG. 6812 * 6813 * Example: In a LAG with three active ports, the second port 6814 * ([2][1]) would be selected for traffic mapped to buckets 6815 * 3,4,5 (0x38). 6816 */ 6817 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6818 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6819 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6820 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6821 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6822 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6823 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6824 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6825 }; 6826 6827 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6828 int num_tx, int nth) 6829 { 6830 u8 active = 0; 6831 int i; 6832 6833 num_tx = num_tx <= 8 ? num_tx : 8; 6834 if (nth < num_tx) 6835 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6836 6837 for (i = 0; i < 8; i++) { 6838 if (BIT(i) & active) 6839 mask[i] |= BIT(port); 6840 } 6841 } 6842 6843 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6844 { 6845 struct mv88e6xxx_chip *chip = ds->priv; 6846 unsigned int id, num_tx; 6847 struct dsa_port *dp; 6848 struct dsa_lag *lag; 6849 int i, err, nth; 6850 u16 mask[8]; 6851 u16 ivec; 6852 6853 /* Assume no port is a member of any LAG. */ 6854 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6855 6856 /* Disable all masks for ports that _are_ members of a LAG. */ 6857 dsa_switch_for_each_port(dp, ds) { 6858 if (!dp->lag) 6859 continue; 6860 6861 ivec &= ~BIT(dp->index); 6862 } 6863 6864 for (i = 0; i < 8; i++) 6865 mask[i] = ivec; 6866 6867 /* Enable the correct subset of masks for all LAG ports that 6868 * are in the Tx set. 6869 */ 6870 dsa_lags_foreach_id(id, ds->dst) { 6871 lag = dsa_lag_by_id(ds->dst, id); 6872 if (!lag) 6873 continue; 6874 6875 num_tx = 0; 6876 dsa_lag_foreach_port(dp, ds->dst, lag) { 6877 if (dp->lag_tx_enabled) 6878 num_tx++; 6879 } 6880 6881 if (!num_tx) 6882 continue; 6883 6884 nth = 0; 6885 dsa_lag_foreach_port(dp, ds->dst, lag) { 6886 if (!dp->lag_tx_enabled) 6887 continue; 6888 6889 if (dp->ds == ds) 6890 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6891 num_tx, nth); 6892 6893 nth++; 6894 } 6895 } 6896 6897 for (i = 0; i < 8; i++) { 6898 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6899 if (err) 6900 return err; 6901 } 6902 6903 return 0; 6904 } 6905 6906 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6907 struct dsa_lag lag) 6908 { 6909 int err; 6910 6911 err = mv88e6xxx_lag_sync_masks(ds); 6912 6913 if (!err) 6914 err = mv88e6xxx_lag_sync_map(ds, lag); 6915 6916 return err; 6917 } 6918 6919 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6920 { 6921 struct mv88e6xxx_chip *chip = ds->priv; 6922 int err; 6923 6924 mv88e6xxx_reg_lock(chip); 6925 err = mv88e6xxx_lag_sync_masks(ds); 6926 mv88e6xxx_reg_unlock(chip); 6927 return err; 6928 } 6929 6930 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6931 struct dsa_lag lag, 6932 struct netdev_lag_upper_info *info, 6933 struct netlink_ext_ack *extack) 6934 { 6935 struct mv88e6xxx_chip *chip = ds->priv; 6936 int err, id; 6937 6938 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6939 return -EOPNOTSUPP; 6940 6941 /* DSA LAG IDs are one-based */ 6942 id = lag.id - 1; 6943 6944 mv88e6xxx_reg_lock(chip); 6945 6946 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6947 if (err) 6948 goto err_unlock; 6949 6950 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6951 if (err) 6952 goto err_clear_trunk; 6953 6954 mv88e6xxx_reg_unlock(chip); 6955 return 0; 6956 6957 err_clear_trunk: 6958 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6959 err_unlock: 6960 mv88e6xxx_reg_unlock(chip); 6961 return err; 6962 } 6963 6964 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6965 struct dsa_lag lag) 6966 { 6967 struct mv88e6xxx_chip *chip = ds->priv; 6968 int err_sync, err_trunk; 6969 6970 mv88e6xxx_reg_lock(chip); 6971 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6972 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6973 mv88e6xxx_reg_unlock(chip); 6974 return err_sync ? : err_trunk; 6975 } 6976 6977 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6978 int port) 6979 { 6980 struct mv88e6xxx_chip *chip = ds->priv; 6981 int err; 6982 6983 mv88e6xxx_reg_lock(chip); 6984 err = mv88e6xxx_lag_sync_masks(ds); 6985 mv88e6xxx_reg_unlock(chip); 6986 return err; 6987 } 6988 6989 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6990 int port, struct dsa_lag lag, 6991 struct netdev_lag_upper_info *info, 6992 struct netlink_ext_ack *extack) 6993 { 6994 struct mv88e6xxx_chip *chip = ds->priv; 6995 int err; 6996 6997 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6998 return -EOPNOTSUPP; 6999 7000 mv88e6xxx_reg_lock(chip); 7001 7002 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7003 if (err) 7004 goto unlock; 7005 7006 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7007 7008 unlock: 7009 mv88e6xxx_reg_unlock(chip); 7010 return err; 7011 } 7012 7013 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7014 int port, struct dsa_lag lag) 7015 { 7016 struct mv88e6xxx_chip *chip = ds->priv; 7017 int err_sync, err_pvt; 7018 7019 mv88e6xxx_reg_lock(chip); 7020 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7021 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7022 mv88e6xxx_reg_unlock(chip); 7023 return err_sync ? : err_pvt; 7024 } 7025 7026 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7027 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7028 .mac_prepare = mv88e6xxx_mac_prepare, 7029 .mac_config = mv88e6xxx_mac_config, 7030 .mac_finish = mv88e6xxx_mac_finish, 7031 .mac_link_down = mv88e6xxx_mac_link_down, 7032 .mac_link_up = mv88e6xxx_mac_link_up, 7033 }; 7034 7035 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7036 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7037 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7038 .setup = mv88e6xxx_setup, 7039 .teardown = mv88e6xxx_teardown, 7040 .port_setup = mv88e6xxx_port_setup, 7041 .port_teardown = mv88e6xxx_port_teardown, 7042 .phylink_get_caps = mv88e6xxx_get_caps, 7043 .get_strings = mv88e6xxx_get_strings, 7044 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7045 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7046 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7047 .get_sset_count = mv88e6xxx_get_sset_count, 7048 .port_max_mtu = mv88e6xxx_get_max_mtu, 7049 .port_change_mtu = mv88e6xxx_change_mtu, 7050 .get_mac_eee = mv88e6xxx_get_mac_eee, 7051 .set_mac_eee = mv88e6xxx_set_mac_eee, 7052 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7053 .get_eeprom = mv88e6xxx_get_eeprom, 7054 .set_eeprom = mv88e6xxx_set_eeprom, 7055 .get_regs_len = mv88e6xxx_get_regs_len, 7056 .get_regs = mv88e6xxx_get_regs, 7057 .get_rxnfc = mv88e6xxx_get_rxnfc, 7058 .set_rxnfc = mv88e6xxx_set_rxnfc, 7059 .set_ageing_time = mv88e6xxx_set_ageing_time, 7060 .port_bridge_join = mv88e6xxx_port_bridge_join, 7061 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7062 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7063 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7064 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7065 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7066 .port_fast_age = mv88e6xxx_port_fast_age, 7067 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7068 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7069 .port_vlan_add = mv88e6xxx_port_vlan_add, 7070 .port_vlan_del = mv88e6xxx_port_vlan_del, 7071 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7072 .port_fdb_add = mv88e6xxx_port_fdb_add, 7073 .port_fdb_del = mv88e6xxx_port_fdb_del, 7074 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7075 .port_mdb_add = mv88e6xxx_port_mdb_add, 7076 .port_mdb_del = mv88e6xxx_port_mdb_del, 7077 .port_mirror_add = mv88e6xxx_port_mirror_add, 7078 .port_mirror_del = mv88e6xxx_port_mirror_del, 7079 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7080 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7081 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7082 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7083 .port_txtstamp = mv88e6xxx_port_txtstamp, 7084 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7085 .get_ts_info = mv88e6xxx_get_ts_info, 7086 .devlink_param_get = mv88e6xxx_devlink_param_get, 7087 .devlink_param_set = mv88e6xxx_devlink_param_set, 7088 .devlink_info_get = mv88e6xxx_devlink_info_get, 7089 .port_lag_change = mv88e6xxx_port_lag_change, 7090 .port_lag_join = mv88e6xxx_port_lag_join, 7091 .port_lag_leave = mv88e6xxx_port_lag_leave, 7092 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7093 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7094 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7095 }; 7096 7097 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7098 { 7099 struct device *dev = chip->dev; 7100 struct dsa_switch *ds; 7101 7102 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7103 if (!ds) 7104 return -ENOMEM; 7105 7106 ds->dev = dev; 7107 ds->num_ports = mv88e6xxx_num_ports(chip); 7108 ds->priv = chip; 7109 ds->dev = dev; 7110 ds->ops = &mv88e6xxx_switch_ops; 7111 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7112 ds->ageing_time_min = chip->info->age_time_coeff; 7113 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7114 7115 /* Some chips support up to 32, but that requires enabling the 7116 * 5-bit port mode, which we do not support. 640k^W16 ought to 7117 * be enough for anyone. 7118 */ 7119 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7120 7121 dev_set_drvdata(dev, ds); 7122 7123 return dsa_register_switch(ds); 7124 } 7125 7126 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7127 { 7128 dsa_unregister_switch(chip->ds); 7129 } 7130 7131 static const void *pdata_device_get_match_data(struct device *dev) 7132 { 7133 const struct of_device_id *matches = dev->driver->of_match_table; 7134 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7135 7136 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7137 matches++) { 7138 if (!strcmp(pdata->compatible, matches->compatible)) 7139 return matches->data; 7140 } 7141 return NULL; 7142 } 7143 7144 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7145 * would be lost after a power cycle so prevent it to be suspended. 7146 */ 7147 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7148 { 7149 return -EOPNOTSUPP; 7150 } 7151 7152 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7153 { 7154 return 0; 7155 } 7156 7157 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7158 7159 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7160 { 7161 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7162 const struct mv88e6xxx_info *compat_info = NULL; 7163 struct device *dev = &mdiodev->dev; 7164 struct device_node *np = dev->of_node; 7165 struct mv88e6xxx_chip *chip; 7166 int port; 7167 int err; 7168 7169 if (!np && !pdata) 7170 return -EINVAL; 7171 7172 if (np) 7173 compat_info = of_device_get_match_data(dev); 7174 7175 if (pdata) { 7176 compat_info = pdata_device_get_match_data(dev); 7177 7178 if (!pdata->netdev) 7179 return -EINVAL; 7180 7181 for (port = 0; port < DSA_MAX_PORTS; port++) { 7182 if (!(pdata->enabled_ports & (1 << port))) 7183 continue; 7184 if (strcmp(pdata->cd.port_names[port], "cpu")) 7185 continue; 7186 pdata->cd.netdev[port] = &pdata->netdev->dev; 7187 break; 7188 } 7189 } 7190 7191 if (!compat_info) 7192 return -EINVAL; 7193 7194 chip = mv88e6xxx_alloc_chip(dev); 7195 if (!chip) { 7196 err = -ENOMEM; 7197 goto out; 7198 } 7199 7200 chip->info = compat_info; 7201 7202 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7203 if (IS_ERR(chip->reset)) { 7204 err = PTR_ERR(chip->reset); 7205 goto out; 7206 } 7207 if (chip->reset) 7208 usleep_range(10000, 20000); 7209 7210 /* Detect if the device is configured in single chip addressing mode, 7211 * otherwise continue with address specific smi init/detection. 7212 */ 7213 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7214 if (err) { 7215 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7216 if (err) 7217 goto out; 7218 7219 err = mv88e6xxx_detect(chip); 7220 if (err) 7221 goto out; 7222 } 7223 7224 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7225 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7226 else 7227 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7228 7229 mv88e6xxx_phy_init(chip); 7230 7231 if (chip->info->ops->get_eeprom) { 7232 if (np) 7233 of_property_read_u32(np, "eeprom-length", 7234 &chip->eeprom_len); 7235 else 7236 chip->eeprom_len = pdata->eeprom_len; 7237 } 7238 7239 mv88e6xxx_reg_lock(chip); 7240 err = mv88e6xxx_switch_reset(chip); 7241 mv88e6xxx_reg_unlock(chip); 7242 if (err) 7243 goto out; 7244 7245 if (np) { 7246 chip->irq = of_irq_get(np, 0); 7247 if (chip->irq == -EPROBE_DEFER) { 7248 err = chip->irq; 7249 goto out; 7250 } 7251 } 7252 7253 if (pdata) 7254 chip->irq = pdata->irq; 7255 7256 /* Has to be performed before the MDIO bus is created, because 7257 * the PHYs will link their interrupts to these interrupt 7258 * controllers 7259 */ 7260 mv88e6xxx_reg_lock(chip); 7261 if (chip->irq > 0) 7262 err = mv88e6xxx_g1_irq_setup(chip); 7263 else 7264 err = mv88e6xxx_irq_poll_setup(chip); 7265 mv88e6xxx_reg_unlock(chip); 7266 7267 if (err) 7268 goto out; 7269 7270 if (chip->info->g2_irqs > 0) { 7271 err = mv88e6xxx_g2_irq_setup(chip); 7272 if (err) 7273 goto out_g1_irq; 7274 } 7275 7276 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7277 if (err) 7278 goto out_g2_irq; 7279 7280 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7281 if (err) 7282 goto out_g1_atu_prob_irq; 7283 7284 err = mv88e6xxx_register_switch(chip); 7285 if (err) 7286 goto out_g1_vtu_prob_irq; 7287 7288 return 0; 7289 7290 out_g1_vtu_prob_irq: 7291 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7292 out_g1_atu_prob_irq: 7293 mv88e6xxx_g1_atu_prob_irq_free(chip); 7294 out_g2_irq: 7295 if (chip->info->g2_irqs > 0) 7296 mv88e6xxx_g2_irq_free(chip); 7297 out_g1_irq: 7298 if (chip->irq > 0) 7299 mv88e6xxx_g1_irq_free(chip); 7300 else 7301 mv88e6xxx_irq_poll_free(chip); 7302 out: 7303 if (pdata) 7304 dev_put(pdata->netdev); 7305 7306 return err; 7307 } 7308 7309 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7310 { 7311 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7312 struct mv88e6xxx_chip *chip; 7313 7314 if (!ds) 7315 return; 7316 7317 chip = ds->priv; 7318 7319 if (chip->info->ptp_support) { 7320 mv88e6xxx_hwtstamp_free(chip); 7321 mv88e6xxx_ptp_free(chip); 7322 } 7323 7324 mv88e6xxx_phy_destroy(chip); 7325 mv88e6xxx_unregister_switch(chip); 7326 7327 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7328 mv88e6xxx_g1_atu_prob_irq_free(chip); 7329 7330 if (chip->info->g2_irqs > 0) 7331 mv88e6xxx_g2_irq_free(chip); 7332 7333 if (chip->irq > 0) 7334 mv88e6xxx_g1_irq_free(chip); 7335 else 7336 mv88e6xxx_irq_poll_free(chip); 7337 } 7338 7339 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7340 { 7341 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7342 7343 if (!ds) 7344 return; 7345 7346 dsa_switch_shutdown(ds); 7347 7348 dev_set_drvdata(&mdiodev->dev, NULL); 7349 } 7350 7351 static const struct of_device_id mv88e6xxx_of_match[] = { 7352 { 7353 .compatible = "marvell,mv88e6085", 7354 .data = &mv88e6xxx_table[MV88E6085], 7355 }, 7356 { 7357 .compatible = "marvell,mv88e6190", 7358 .data = &mv88e6xxx_table[MV88E6190], 7359 }, 7360 { 7361 .compatible = "marvell,mv88e6250", 7362 .data = &mv88e6xxx_table[MV88E6250], 7363 }, 7364 { /* sentinel */ }, 7365 }; 7366 7367 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7368 7369 static struct mdio_driver mv88e6xxx_driver = { 7370 .probe = mv88e6xxx_probe, 7371 .remove = mv88e6xxx_remove, 7372 .shutdown = mv88e6xxx_shutdown, 7373 .mdiodrv.driver = { 7374 .name = "mv88e6085", 7375 .of_match_table = mv88e6xxx_of_match, 7376 .pm = &mv88e6xxx_pm_ops, 7377 }, 7378 }; 7379 7380 mdio_module_driver(mv88e6xxx_driver); 7381 7382 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7383 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7384 MODULE_LICENSE("GPL"); 7385