1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 55 * 56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 57 * is the only device connected to the SMI master. In this mode it responds to 58 * all 32 possible SMI addresses, and thus maps directly the internal devices. 59 * 60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 61 * multiple devices to share the SMI interface. In this mode it responds to only 62 * 2 registers, used to indirectly access the internal SMI devices. 63 */ 64 65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 66 int addr, int reg, u16 *val) 67 { 68 if (!chip->smi_ops) 69 return -EOPNOTSUPP; 70 71 return chip->smi_ops->read(chip, addr, reg, val); 72 } 73 74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 75 int addr, int reg, u16 val) 76 { 77 if (!chip->smi_ops) 78 return -EOPNOTSUPP; 79 80 return chip->smi_ops->write(chip, addr, reg, val); 81 } 82 83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 84 int addr, int reg, u16 *val) 85 { 86 int ret; 87 88 ret = mdiobus_read_nested(chip->bus, addr, reg); 89 if (ret < 0) 90 return ret; 91 92 *val = ret & 0xffff; 93 94 return 0; 95 } 96 97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 98 int addr, int reg, u16 val) 99 { 100 int ret; 101 102 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 103 if (ret < 0) 104 return ret; 105 106 return 0; 107 } 108 109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 110 .read = mv88e6xxx_smi_single_chip_read, 111 .write = mv88e6xxx_smi_single_chip_write, 112 }; 113 114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 115 { 116 int ret; 117 int i; 118 119 for (i = 0; i < 16; i++) { 120 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 121 if (ret < 0) 122 return ret; 123 124 if ((ret & SMI_CMD_BUSY) == 0) 125 return 0; 126 } 127 128 return -ETIMEDOUT; 129 } 130 131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 132 int addr, int reg, u16 *val) 133 { 134 int ret; 135 136 /* Wait for the bus to become free. */ 137 ret = mv88e6xxx_smi_multi_chip_wait(chip); 138 if (ret < 0) 139 return ret; 140 141 /* Transmit the read command. */ 142 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 143 SMI_CMD_OP_22_READ | (addr << 5) | reg); 144 if (ret < 0) 145 return ret; 146 147 /* Wait for the read command to complete. */ 148 ret = mv88e6xxx_smi_multi_chip_wait(chip); 149 if (ret < 0) 150 return ret; 151 152 /* Read the data. */ 153 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 154 if (ret < 0) 155 return ret; 156 157 *val = ret & 0xffff; 158 159 return 0; 160 } 161 162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 163 int addr, int reg, u16 val) 164 { 165 int ret; 166 167 /* Wait for the bus to become free. */ 168 ret = mv88e6xxx_smi_multi_chip_wait(chip); 169 if (ret < 0) 170 return ret; 171 172 /* Transmit the data to write. */ 173 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 174 if (ret < 0) 175 return ret; 176 177 /* Transmit the write command. */ 178 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 179 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 180 if (ret < 0) 181 return ret; 182 183 /* Wait for the write command to complete. */ 184 ret = mv88e6xxx_smi_multi_chip_wait(chip); 185 if (ret < 0) 186 return ret; 187 188 return 0; 189 } 190 191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 192 .read = mv88e6xxx_smi_multi_chip_read, 193 .write = mv88e6xxx_smi_multi_chip_write, 194 }; 195 196 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 197 { 198 int err; 199 200 assert_reg_lock(chip); 201 202 err = mv88e6xxx_smi_read(chip, addr, reg, val); 203 if (err) 204 return err; 205 206 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 207 addr, reg, *val); 208 209 return 0; 210 } 211 212 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 213 { 214 int err; 215 216 assert_reg_lock(chip); 217 218 err = mv88e6xxx_smi_write(chip, addr, reg, val); 219 if (err) 220 return err; 221 222 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 223 addr, reg, val); 224 225 return 0; 226 } 227 228 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 229 { 230 struct mv88e6xxx_mdio_bus *mdio_bus; 231 232 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 233 list); 234 if (!mdio_bus) 235 return NULL; 236 237 return mdio_bus->bus; 238 } 239 240 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 241 { 242 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 243 unsigned int n = d->hwirq; 244 245 chip->g1_irq.masked |= (1 << n); 246 } 247 248 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 249 { 250 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 251 unsigned int n = d->hwirq; 252 253 chip->g1_irq.masked &= ~(1 << n); 254 } 255 256 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 257 { 258 unsigned int nhandled = 0; 259 unsigned int sub_irq; 260 unsigned int n; 261 u16 reg; 262 int err; 263 264 mutex_lock(&chip->reg_lock); 265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 266 mutex_unlock(&chip->reg_lock); 267 268 if (err) 269 goto out; 270 271 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 272 if (reg & (1 << n)) { 273 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 274 handle_nested_irq(sub_irq); 275 ++nhandled; 276 } 277 } 278 out: 279 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 280 } 281 282 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 283 { 284 struct mv88e6xxx_chip *chip = dev_id; 285 286 return mv88e6xxx_g1_irq_thread_work(chip); 287 } 288 289 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 290 { 291 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 292 293 mutex_lock(&chip->reg_lock); 294 } 295 296 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 297 { 298 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 299 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 300 u16 reg; 301 int err; 302 303 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 304 if (err) 305 goto out; 306 307 reg &= ~mask; 308 reg |= (~chip->g1_irq.masked & mask); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 311 if (err) 312 goto out; 313 314 out: 315 mutex_unlock(&chip->reg_lock); 316 } 317 318 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 319 .name = "mv88e6xxx-g1", 320 .irq_mask = mv88e6xxx_g1_irq_mask, 321 .irq_unmask = mv88e6xxx_g1_irq_unmask, 322 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 323 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 324 }; 325 326 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 327 unsigned int irq, 328 irq_hw_number_t hwirq) 329 { 330 struct mv88e6xxx_chip *chip = d->host_data; 331 332 irq_set_chip_data(irq, d->host_data); 333 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 334 irq_set_noprobe(irq); 335 336 return 0; 337 } 338 339 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 340 .map = mv88e6xxx_g1_irq_domain_map, 341 .xlate = irq_domain_xlate_twocell, 342 }; 343 344 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 345 { 346 int irq, virq; 347 u16 mask; 348 349 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 350 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 351 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 352 353 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 354 virq = irq_find_mapping(chip->g1_irq.domain, irq); 355 irq_dispose_mapping(virq); 356 } 357 358 irq_domain_remove(chip->g1_irq.domain); 359 } 360 361 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 362 { 363 mv88e6xxx_g1_irq_free(chip); 364 365 free_irq(chip->irq, chip); 366 } 367 368 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 369 { 370 int err, irq, virq; 371 u16 reg, mask; 372 373 chip->g1_irq.nirqs = chip->info->g1_irqs; 374 chip->g1_irq.domain = irq_domain_add_simple( 375 NULL, chip->g1_irq.nirqs, 0, 376 &mv88e6xxx_g1_irq_domain_ops, chip); 377 if (!chip->g1_irq.domain) 378 return -ENOMEM; 379 380 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 381 irq_create_mapping(chip->g1_irq.domain, irq); 382 383 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 384 chip->g1_irq.masked = ~0; 385 386 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 387 if (err) 388 goto out_mapping; 389 390 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 391 392 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 393 if (err) 394 goto out_disable; 395 396 /* Reading the interrupt status clears (most of) them */ 397 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 398 if (err) 399 goto out_disable; 400 401 return 0; 402 403 out_disable: 404 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 405 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 406 407 out_mapping: 408 for (irq = 0; irq < 16; irq++) { 409 virq = irq_find_mapping(chip->g1_irq.domain, irq); 410 irq_dispose_mapping(virq); 411 } 412 413 irq_domain_remove(chip->g1_irq.domain); 414 415 return err; 416 } 417 418 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 419 { 420 int err; 421 422 err = mv88e6xxx_g1_irq_setup_common(chip); 423 if (err) 424 return err; 425 426 err = request_threaded_irq(chip->irq, NULL, 427 mv88e6xxx_g1_irq_thread_fn, 428 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 429 dev_name(chip->dev), chip); 430 if (err) 431 mv88e6xxx_g1_irq_free_common(chip); 432 433 return err; 434 } 435 436 static void mv88e6xxx_irq_poll(struct kthread_work *work) 437 { 438 struct mv88e6xxx_chip *chip = container_of(work, 439 struct mv88e6xxx_chip, 440 irq_poll_work.work); 441 mv88e6xxx_g1_irq_thread_work(chip); 442 443 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 444 msecs_to_jiffies(100)); 445 } 446 447 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 448 { 449 int err; 450 451 err = mv88e6xxx_g1_irq_setup_common(chip); 452 if (err) 453 return err; 454 455 kthread_init_delayed_work(&chip->irq_poll_work, 456 mv88e6xxx_irq_poll); 457 458 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 459 if (IS_ERR(chip->kworker)) 460 return PTR_ERR(chip->kworker); 461 462 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 463 msecs_to_jiffies(100)); 464 465 return 0; 466 } 467 468 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 469 { 470 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 471 kthread_destroy_worker(chip->kworker); 472 } 473 474 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 475 { 476 int i; 477 478 for (i = 0; i < 16; i++) { 479 u16 val; 480 int err; 481 482 err = mv88e6xxx_read(chip, addr, reg, &val); 483 if (err) 484 return err; 485 486 if (!(val & mask)) 487 return 0; 488 489 usleep_range(1000, 2000); 490 } 491 492 dev_err(chip->dev, "Timeout while waiting for switch\n"); 493 return -ETIMEDOUT; 494 } 495 496 /* Indirect write to single pointer-data register with an Update bit */ 497 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 498 { 499 u16 val; 500 int err; 501 502 /* Wait until the previous operation is completed */ 503 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 504 if (err) 505 return err; 506 507 /* Set the Update bit to trigger a write operation */ 508 val = BIT(15) | update; 509 510 return mv88e6xxx_write(chip, addr, reg, val); 511 } 512 513 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 514 int link, int speed, int duplex, 515 phy_interface_t mode) 516 { 517 int err; 518 519 if (!chip->info->ops->port_set_link) 520 return 0; 521 522 /* Port's MAC control must not be changed unless the link is down */ 523 err = chip->info->ops->port_set_link(chip, port, 0); 524 if (err) 525 return err; 526 527 if (chip->info->ops->port_set_speed) { 528 err = chip->info->ops->port_set_speed(chip, port, speed); 529 if (err && err != -EOPNOTSUPP) 530 goto restore_link; 531 } 532 533 if (chip->info->ops->port_set_duplex) { 534 err = chip->info->ops->port_set_duplex(chip, port, duplex); 535 if (err && err != -EOPNOTSUPP) 536 goto restore_link; 537 } 538 539 if (chip->info->ops->port_set_rgmii_delay) { 540 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 541 if (err && err != -EOPNOTSUPP) 542 goto restore_link; 543 } 544 545 if (chip->info->ops->port_set_cmode) { 546 err = chip->info->ops->port_set_cmode(chip, port, mode); 547 if (err && err != -EOPNOTSUPP) 548 goto restore_link; 549 } 550 551 err = 0; 552 restore_link: 553 if (chip->info->ops->port_set_link(chip, port, link)) 554 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 555 556 return err; 557 } 558 559 /* We expect the switch to perform auto negotiation if there is a real 560 * phy. However, in the case of a fixed link phy, we force the port 561 * settings from the fixed link settings. 562 */ 563 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 564 struct phy_device *phydev) 565 { 566 struct mv88e6xxx_chip *chip = ds->priv; 567 int err; 568 569 if (!phy_is_pseudo_fixed_link(phydev)) 570 return; 571 572 mutex_lock(&chip->reg_lock); 573 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 574 phydev->duplex, phydev->interface); 575 mutex_unlock(&chip->reg_lock); 576 577 if (err && err != -EOPNOTSUPP) 578 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 579 } 580 581 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 582 { 583 if (!chip->info->ops->stats_snapshot) 584 return -EOPNOTSUPP; 585 586 return chip->info->ops->stats_snapshot(chip, port); 587 } 588 589 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 590 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 591 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 592 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 593 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 594 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 595 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 596 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 597 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 598 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 599 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 600 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 601 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 602 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 603 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 604 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 605 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 606 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 607 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 608 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 609 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 610 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 611 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 612 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 613 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 614 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 615 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 616 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 617 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 618 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 619 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 620 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 621 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 622 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 623 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 624 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 625 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 626 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 627 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 628 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 629 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 630 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 631 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 632 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 633 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 634 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 635 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 636 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 637 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 638 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 639 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 640 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 641 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 642 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 643 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 644 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 645 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 646 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 647 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 648 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 649 }; 650 651 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 652 struct mv88e6xxx_hw_stat *s, 653 int port, u16 bank1_select, 654 u16 histogram) 655 { 656 u32 low; 657 u32 high = 0; 658 u16 reg = 0; 659 int err; 660 u64 value; 661 662 switch (s->type) { 663 case STATS_TYPE_PORT: 664 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 665 if (err) 666 return UINT64_MAX; 667 668 low = reg; 669 if (s->sizeof_stat == 4) { 670 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 671 if (err) 672 return UINT64_MAX; 673 high = reg; 674 } 675 break; 676 case STATS_TYPE_BANK1: 677 reg = bank1_select; 678 /* fall through */ 679 case STATS_TYPE_BANK0: 680 reg |= s->reg | histogram; 681 mv88e6xxx_g1_stats_read(chip, reg, &low); 682 if (s->sizeof_stat == 8) 683 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 684 break; 685 default: 686 return UINT64_MAX; 687 } 688 value = (((u64)high) << 16) | low; 689 return value; 690 } 691 692 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 693 uint8_t *data, int types) 694 { 695 struct mv88e6xxx_hw_stat *stat; 696 int i, j; 697 698 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 699 stat = &mv88e6xxx_hw_stats[i]; 700 if (stat->type & types) { 701 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 702 ETH_GSTRING_LEN); 703 j++; 704 } 705 } 706 } 707 708 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 709 uint8_t *data) 710 { 711 mv88e6xxx_stats_get_strings(chip, data, 712 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 713 } 714 715 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 716 uint8_t *data) 717 { 718 mv88e6xxx_stats_get_strings(chip, data, 719 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 720 } 721 722 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 723 uint8_t *data) 724 { 725 struct mv88e6xxx_chip *chip = ds->priv; 726 727 if (chip->info->ops->stats_get_strings) 728 chip->info->ops->stats_get_strings(chip, data); 729 } 730 731 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 732 int types) 733 { 734 struct mv88e6xxx_hw_stat *stat; 735 int i, j; 736 737 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 738 stat = &mv88e6xxx_hw_stats[i]; 739 if (stat->type & types) 740 j++; 741 } 742 return j; 743 } 744 745 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 746 { 747 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 748 STATS_TYPE_PORT); 749 } 750 751 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 752 { 753 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 754 STATS_TYPE_BANK1); 755 } 756 757 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 761 if (chip->info->ops->stats_get_sset_count) 762 return chip->info->ops->stats_get_sset_count(chip); 763 764 return 0; 765 } 766 767 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 768 uint64_t *data, int types, 769 u16 bank1_select, u16 histogram) 770 { 771 struct mv88e6xxx_hw_stat *stat; 772 int i, j; 773 774 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 775 stat = &mv88e6xxx_hw_stats[i]; 776 if (stat->type & types) { 777 mutex_lock(&chip->reg_lock); 778 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 779 bank1_select, 780 histogram); 781 mutex_unlock(&chip->reg_lock); 782 783 j++; 784 } 785 } 786 } 787 788 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 789 uint64_t *data) 790 { 791 return mv88e6xxx_stats_get_stats(chip, port, data, 792 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 793 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 794 } 795 796 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 797 uint64_t *data) 798 { 799 return mv88e6xxx_stats_get_stats(chip, port, data, 800 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 801 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 802 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 803 } 804 805 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 806 uint64_t *data) 807 { 808 return mv88e6xxx_stats_get_stats(chip, port, data, 809 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 810 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 811 0); 812 } 813 814 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 815 uint64_t *data) 816 { 817 if (chip->info->ops->stats_get_stats) 818 chip->info->ops->stats_get_stats(chip, port, data); 819 } 820 821 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 822 uint64_t *data) 823 { 824 struct mv88e6xxx_chip *chip = ds->priv; 825 int ret; 826 827 mutex_lock(&chip->reg_lock); 828 829 ret = mv88e6xxx_stats_snapshot(chip, port); 830 mutex_unlock(&chip->reg_lock); 831 832 if (ret < 0) 833 return; 834 835 mv88e6xxx_get_stats(chip, port, data); 836 837 } 838 839 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 840 { 841 if (chip->info->ops->stats_set_histogram) 842 return chip->info->ops->stats_set_histogram(chip); 843 844 return 0; 845 } 846 847 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 848 { 849 return 32 * sizeof(u16); 850 } 851 852 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 853 struct ethtool_regs *regs, void *_p) 854 { 855 struct mv88e6xxx_chip *chip = ds->priv; 856 int err; 857 u16 reg; 858 u16 *p = _p; 859 int i; 860 861 regs->version = 0; 862 863 memset(p, 0xff, 32 * sizeof(u16)); 864 865 mutex_lock(&chip->reg_lock); 866 867 for (i = 0; i < 32; i++) { 868 869 err = mv88e6xxx_port_read(chip, port, i, ®); 870 if (!err) 871 p[i] = reg; 872 } 873 874 mutex_unlock(&chip->reg_lock); 875 } 876 877 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 878 struct ethtool_eee *e) 879 { 880 /* Nothing to do on the port's MAC */ 881 return 0; 882 } 883 884 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 885 struct ethtool_eee *e) 886 { 887 /* Nothing to do on the port's MAC */ 888 return 0; 889 } 890 891 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 892 { 893 struct dsa_switch *ds = NULL; 894 struct net_device *br; 895 u16 pvlan; 896 int i; 897 898 if (dev < DSA_MAX_SWITCHES) 899 ds = chip->ds->dst->ds[dev]; 900 901 /* Prevent frames from unknown switch or port */ 902 if (!ds || port >= ds->num_ports) 903 return 0; 904 905 /* Frames from DSA links and CPU ports can egress any local port */ 906 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 907 return mv88e6xxx_port_mask(chip); 908 909 br = ds->ports[port].bridge_dev; 910 pvlan = 0; 911 912 /* Frames from user ports can egress any local DSA links and CPU ports, 913 * as well as any local member of their bridge group. 914 */ 915 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 916 if (dsa_is_cpu_port(chip->ds, i) || 917 dsa_is_dsa_port(chip->ds, i) || 918 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 919 pvlan |= BIT(i); 920 921 return pvlan; 922 } 923 924 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 925 { 926 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 927 928 /* prevent frames from going back out of the port they came in on */ 929 output_ports &= ~BIT(port); 930 931 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 932 } 933 934 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 935 u8 state) 936 { 937 struct mv88e6xxx_chip *chip = ds->priv; 938 int err; 939 940 mutex_lock(&chip->reg_lock); 941 err = mv88e6xxx_port_set_state(chip, port, state); 942 mutex_unlock(&chip->reg_lock); 943 944 if (err) 945 dev_err(ds->dev, "p%d: failed to update state\n", port); 946 } 947 948 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 949 { 950 if (chip->info->ops->pot_clear) 951 return chip->info->ops->pot_clear(chip); 952 953 return 0; 954 } 955 956 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 957 { 958 if (chip->info->ops->mgmt_rsvd2cpu) 959 return chip->info->ops->mgmt_rsvd2cpu(chip); 960 961 return 0; 962 } 963 964 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 965 { 966 int err; 967 968 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 969 if (err) 970 return err; 971 972 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 973 if (err) 974 return err; 975 976 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 977 } 978 979 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 980 { 981 int port; 982 int err; 983 984 if (!chip->info->ops->irl_init_all) 985 return 0; 986 987 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 988 /* Disable ingress rate limiting by resetting all per port 989 * ingress rate limit resources to their initial state. 990 */ 991 err = chip->info->ops->irl_init_all(chip, port); 992 if (err) 993 return err; 994 } 995 996 return 0; 997 } 998 999 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1000 { 1001 if (chip->info->ops->set_switch_mac) { 1002 u8 addr[ETH_ALEN]; 1003 1004 eth_random_addr(addr); 1005 1006 return chip->info->ops->set_switch_mac(chip, addr); 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1013 { 1014 u16 pvlan = 0; 1015 1016 if (!mv88e6xxx_has_pvt(chip)) 1017 return -EOPNOTSUPP; 1018 1019 /* Skip the local source device, which uses in-chip port VLAN */ 1020 if (dev != chip->ds->index) 1021 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1022 1023 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1024 } 1025 1026 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1027 { 1028 int dev, port; 1029 int err; 1030 1031 if (!mv88e6xxx_has_pvt(chip)) 1032 return 0; 1033 1034 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1035 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1036 */ 1037 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1038 if (err) 1039 return err; 1040 1041 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1042 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1043 err = mv88e6xxx_pvt_map(chip, dev, port); 1044 if (err) 1045 return err; 1046 } 1047 } 1048 1049 return 0; 1050 } 1051 1052 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1053 { 1054 struct mv88e6xxx_chip *chip = ds->priv; 1055 int err; 1056 1057 mutex_lock(&chip->reg_lock); 1058 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1059 mutex_unlock(&chip->reg_lock); 1060 1061 if (err) 1062 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1063 } 1064 1065 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1066 { 1067 if (!chip->info->max_vid) 1068 return 0; 1069 1070 return mv88e6xxx_g1_vtu_flush(chip); 1071 } 1072 1073 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1074 struct mv88e6xxx_vtu_entry *entry) 1075 { 1076 if (!chip->info->ops->vtu_getnext) 1077 return -EOPNOTSUPP; 1078 1079 return chip->info->ops->vtu_getnext(chip, entry); 1080 } 1081 1082 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1083 struct mv88e6xxx_vtu_entry *entry) 1084 { 1085 if (!chip->info->ops->vtu_loadpurge) 1086 return -EOPNOTSUPP; 1087 1088 return chip->info->ops->vtu_loadpurge(chip, entry); 1089 } 1090 1091 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1092 { 1093 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1094 struct mv88e6xxx_vtu_entry vlan = { 1095 .vid = chip->info->max_vid, 1096 }; 1097 int i, err; 1098 1099 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1100 1101 /* Set every FID bit used by the (un)bridged ports */ 1102 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1103 err = mv88e6xxx_port_get_fid(chip, i, fid); 1104 if (err) 1105 return err; 1106 1107 set_bit(*fid, fid_bitmap); 1108 } 1109 1110 /* Set every FID bit used by the VLAN entries */ 1111 do { 1112 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1113 if (err) 1114 return err; 1115 1116 if (!vlan.valid) 1117 break; 1118 1119 set_bit(vlan.fid, fid_bitmap); 1120 } while (vlan.vid < chip->info->max_vid); 1121 1122 /* The reset value 0x000 is used to indicate that multiple address 1123 * databases are not needed. Return the next positive available. 1124 */ 1125 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1126 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1127 return -ENOSPC; 1128 1129 /* Clear the database */ 1130 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1131 } 1132 1133 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1134 struct mv88e6xxx_vtu_entry *entry, bool new) 1135 { 1136 int err; 1137 1138 if (!vid) 1139 return -EINVAL; 1140 1141 entry->vid = vid - 1; 1142 entry->valid = false; 1143 1144 err = mv88e6xxx_vtu_getnext(chip, entry); 1145 if (err) 1146 return err; 1147 1148 if (entry->vid == vid && entry->valid) 1149 return 0; 1150 1151 if (new) { 1152 int i; 1153 1154 /* Initialize a fresh VLAN entry */ 1155 memset(entry, 0, sizeof(*entry)); 1156 entry->valid = true; 1157 entry->vid = vid; 1158 1159 /* Exclude all ports */ 1160 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1161 entry->member[i] = 1162 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1163 1164 return mv88e6xxx_atu_new(chip, &entry->fid); 1165 } 1166 1167 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1168 return -EOPNOTSUPP; 1169 } 1170 1171 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1172 u16 vid_begin, u16 vid_end) 1173 { 1174 struct mv88e6xxx_chip *chip = ds->priv; 1175 struct mv88e6xxx_vtu_entry vlan = { 1176 .vid = vid_begin - 1, 1177 }; 1178 int i, err; 1179 1180 /* DSA and CPU ports have to be members of multiple vlans */ 1181 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1182 return 0; 1183 1184 if (!vid_begin) 1185 return -EOPNOTSUPP; 1186 1187 mutex_lock(&chip->reg_lock); 1188 1189 do { 1190 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1191 if (err) 1192 goto unlock; 1193 1194 if (!vlan.valid) 1195 break; 1196 1197 if (vlan.vid > vid_end) 1198 break; 1199 1200 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1201 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1202 continue; 1203 1204 if (!ds->ports[i].slave) 1205 continue; 1206 1207 if (vlan.member[i] == 1208 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1209 continue; 1210 1211 if (dsa_to_port(ds, i)->bridge_dev == 1212 ds->ports[port].bridge_dev) 1213 break; /* same bridge, check next VLAN */ 1214 1215 if (!dsa_to_port(ds, i)->bridge_dev) 1216 continue; 1217 1218 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1219 port, vlan.vid, i, 1220 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1221 err = -EOPNOTSUPP; 1222 goto unlock; 1223 } 1224 } while (vlan.vid < vid_end); 1225 1226 unlock: 1227 mutex_unlock(&chip->reg_lock); 1228 1229 return err; 1230 } 1231 1232 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1233 bool vlan_filtering) 1234 { 1235 struct mv88e6xxx_chip *chip = ds->priv; 1236 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1237 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1238 int err; 1239 1240 if (!chip->info->max_vid) 1241 return -EOPNOTSUPP; 1242 1243 mutex_lock(&chip->reg_lock); 1244 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1245 mutex_unlock(&chip->reg_lock); 1246 1247 return err; 1248 } 1249 1250 static int 1251 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1252 const struct switchdev_obj_port_vlan *vlan) 1253 { 1254 struct mv88e6xxx_chip *chip = ds->priv; 1255 int err; 1256 1257 if (!chip->info->max_vid) 1258 return -EOPNOTSUPP; 1259 1260 /* If the requested port doesn't belong to the same bridge as the VLAN 1261 * members, do not support it (yet) and fallback to software VLAN. 1262 */ 1263 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1264 vlan->vid_end); 1265 if (err) 1266 return err; 1267 1268 /* We don't need any dynamic resource from the kernel (yet), 1269 * so skip the prepare phase. 1270 */ 1271 return 0; 1272 } 1273 1274 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1275 const unsigned char *addr, u16 vid, 1276 u8 state) 1277 { 1278 struct mv88e6xxx_vtu_entry vlan; 1279 struct mv88e6xxx_atu_entry entry; 1280 int err; 1281 1282 /* Null VLAN ID corresponds to the port private database */ 1283 if (vid == 0) 1284 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1285 else 1286 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1287 if (err) 1288 return err; 1289 1290 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1291 ether_addr_copy(entry.mac, addr); 1292 eth_addr_dec(entry.mac); 1293 1294 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1295 if (err) 1296 return err; 1297 1298 /* Initialize a fresh ATU entry if it isn't found */ 1299 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1300 !ether_addr_equal(entry.mac, addr)) { 1301 memset(&entry, 0, sizeof(entry)); 1302 ether_addr_copy(entry.mac, addr); 1303 } 1304 1305 /* Purge the ATU entry only if no port is using it anymore */ 1306 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1307 entry.portvec &= ~BIT(port); 1308 if (!entry.portvec) 1309 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1310 } else { 1311 entry.portvec |= BIT(port); 1312 entry.state = state; 1313 } 1314 1315 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1316 } 1317 1318 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1319 u16 vid) 1320 { 1321 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1322 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1323 1324 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1325 } 1326 1327 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1328 { 1329 int port; 1330 int err; 1331 1332 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1333 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1334 if (err) 1335 return err; 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1342 u16 vid, u8 member) 1343 { 1344 struct mv88e6xxx_vtu_entry vlan; 1345 int err; 1346 1347 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1348 if (err) 1349 return err; 1350 1351 vlan.member[port] = member; 1352 1353 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1354 if (err) 1355 return err; 1356 1357 return mv88e6xxx_broadcast_setup(chip, vid); 1358 } 1359 1360 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1361 const struct switchdev_obj_port_vlan *vlan) 1362 { 1363 struct mv88e6xxx_chip *chip = ds->priv; 1364 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1365 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1366 u8 member; 1367 u16 vid; 1368 1369 if (!chip->info->max_vid) 1370 return; 1371 1372 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1373 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1374 else if (untagged) 1375 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1376 else 1377 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1378 1379 mutex_lock(&chip->reg_lock); 1380 1381 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1382 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1383 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1384 vid, untagged ? 'u' : 't'); 1385 1386 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1387 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1388 vlan->vid_end); 1389 1390 mutex_unlock(&chip->reg_lock); 1391 } 1392 1393 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1394 int port, u16 vid) 1395 { 1396 struct mv88e6xxx_vtu_entry vlan; 1397 int i, err; 1398 1399 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1400 if (err) 1401 return err; 1402 1403 /* Tell switchdev if this VLAN is handled in software */ 1404 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1405 return -EOPNOTSUPP; 1406 1407 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1408 1409 /* keep the VLAN unless all ports are excluded */ 1410 vlan.valid = false; 1411 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1412 if (vlan.member[i] != 1413 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1414 vlan.valid = true; 1415 break; 1416 } 1417 } 1418 1419 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1420 if (err) 1421 return err; 1422 1423 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1424 } 1425 1426 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1427 const struct switchdev_obj_port_vlan *vlan) 1428 { 1429 struct mv88e6xxx_chip *chip = ds->priv; 1430 u16 pvid, vid; 1431 int err = 0; 1432 1433 if (!chip->info->max_vid) 1434 return -EOPNOTSUPP; 1435 1436 mutex_lock(&chip->reg_lock); 1437 1438 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1439 if (err) 1440 goto unlock; 1441 1442 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1443 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1444 if (err) 1445 goto unlock; 1446 1447 if (vid == pvid) { 1448 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1449 if (err) 1450 goto unlock; 1451 } 1452 } 1453 1454 unlock: 1455 mutex_unlock(&chip->reg_lock); 1456 1457 return err; 1458 } 1459 1460 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1461 const unsigned char *addr, u16 vid) 1462 { 1463 struct mv88e6xxx_chip *chip = ds->priv; 1464 int err; 1465 1466 mutex_lock(&chip->reg_lock); 1467 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1468 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1469 mutex_unlock(&chip->reg_lock); 1470 1471 return err; 1472 } 1473 1474 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1475 const unsigned char *addr, u16 vid) 1476 { 1477 struct mv88e6xxx_chip *chip = ds->priv; 1478 int err; 1479 1480 mutex_lock(&chip->reg_lock); 1481 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1482 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1483 mutex_unlock(&chip->reg_lock); 1484 1485 return err; 1486 } 1487 1488 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1489 u16 fid, u16 vid, int port, 1490 dsa_fdb_dump_cb_t *cb, void *data) 1491 { 1492 struct mv88e6xxx_atu_entry addr; 1493 bool is_static; 1494 int err; 1495 1496 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1497 eth_broadcast_addr(addr.mac); 1498 1499 do { 1500 mutex_lock(&chip->reg_lock); 1501 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1502 mutex_unlock(&chip->reg_lock); 1503 if (err) 1504 return err; 1505 1506 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1507 break; 1508 1509 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1510 continue; 1511 1512 if (!is_unicast_ether_addr(addr.mac)) 1513 continue; 1514 1515 is_static = (addr.state == 1516 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1517 err = cb(addr.mac, vid, is_static, data); 1518 if (err) 1519 return err; 1520 } while (!is_broadcast_ether_addr(addr.mac)); 1521 1522 return err; 1523 } 1524 1525 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1526 dsa_fdb_dump_cb_t *cb, void *data) 1527 { 1528 struct mv88e6xxx_vtu_entry vlan = { 1529 .vid = chip->info->max_vid, 1530 }; 1531 u16 fid; 1532 int err; 1533 1534 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1535 mutex_lock(&chip->reg_lock); 1536 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1537 mutex_unlock(&chip->reg_lock); 1538 1539 if (err) 1540 return err; 1541 1542 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1543 if (err) 1544 return err; 1545 1546 /* Dump VLANs' Filtering Information Databases */ 1547 do { 1548 mutex_lock(&chip->reg_lock); 1549 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1550 mutex_unlock(&chip->reg_lock); 1551 if (err) 1552 return err; 1553 1554 if (!vlan.valid) 1555 break; 1556 1557 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1558 cb, data); 1559 if (err) 1560 return err; 1561 } while (vlan.vid < chip->info->max_vid); 1562 1563 return err; 1564 } 1565 1566 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1567 dsa_fdb_dump_cb_t *cb, void *data) 1568 { 1569 struct mv88e6xxx_chip *chip = ds->priv; 1570 1571 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1572 } 1573 1574 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1575 struct net_device *br) 1576 { 1577 struct dsa_switch *ds; 1578 int port; 1579 int dev; 1580 int err; 1581 1582 /* Remap the Port VLAN of each local bridge group member */ 1583 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1584 if (chip->ds->ports[port].bridge_dev == br) { 1585 err = mv88e6xxx_port_vlan_map(chip, port); 1586 if (err) 1587 return err; 1588 } 1589 } 1590 1591 if (!mv88e6xxx_has_pvt(chip)) 1592 return 0; 1593 1594 /* Remap the Port VLAN of each cross-chip bridge group member */ 1595 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1596 ds = chip->ds->dst->ds[dev]; 1597 if (!ds) 1598 break; 1599 1600 for (port = 0; port < ds->num_ports; ++port) { 1601 if (ds->ports[port].bridge_dev == br) { 1602 err = mv88e6xxx_pvt_map(chip, dev, port); 1603 if (err) 1604 return err; 1605 } 1606 } 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1613 struct net_device *br) 1614 { 1615 struct mv88e6xxx_chip *chip = ds->priv; 1616 int err; 1617 1618 mutex_lock(&chip->reg_lock); 1619 err = mv88e6xxx_bridge_map(chip, br); 1620 mutex_unlock(&chip->reg_lock); 1621 1622 return err; 1623 } 1624 1625 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1626 struct net_device *br) 1627 { 1628 struct mv88e6xxx_chip *chip = ds->priv; 1629 1630 mutex_lock(&chip->reg_lock); 1631 if (mv88e6xxx_bridge_map(chip, br) || 1632 mv88e6xxx_port_vlan_map(chip, port)) 1633 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1634 mutex_unlock(&chip->reg_lock); 1635 } 1636 1637 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1638 int port, struct net_device *br) 1639 { 1640 struct mv88e6xxx_chip *chip = ds->priv; 1641 int err; 1642 1643 if (!mv88e6xxx_has_pvt(chip)) 1644 return 0; 1645 1646 mutex_lock(&chip->reg_lock); 1647 err = mv88e6xxx_pvt_map(chip, dev, port); 1648 mutex_unlock(&chip->reg_lock); 1649 1650 return err; 1651 } 1652 1653 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1654 int port, struct net_device *br) 1655 { 1656 struct mv88e6xxx_chip *chip = ds->priv; 1657 1658 if (!mv88e6xxx_has_pvt(chip)) 1659 return; 1660 1661 mutex_lock(&chip->reg_lock); 1662 if (mv88e6xxx_pvt_map(chip, dev, port)) 1663 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1664 mutex_unlock(&chip->reg_lock); 1665 } 1666 1667 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1668 { 1669 if (chip->info->ops->reset) 1670 return chip->info->ops->reset(chip); 1671 1672 return 0; 1673 } 1674 1675 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1676 { 1677 struct gpio_desc *gpiod = chip->reset; 1678 1679 /* If there is a GPIO connected to the reset pin, toggle it */ 1680 if (gpiod) { 1681 gpiod_set_value_cansleep(gpiod, 1); 1682 usleep_range(10000, 20000); 1683 gpiod_set_value_cansleep(gpiod, 0); 1684 usleep_range(10000, 20000); 1685 } 1686 } 1687 1688 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1689 { 1690 int i, err; 1691 1692 /* Set all ports to the Disabled state */ 1693 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1694 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1695 if (err) 1696 return err; 1697 } 1698 1699 /* Wait for transmit queues to drain, 1700 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1701 */ 1702 usleep_range(2000, 4000); 1703 1704 return 0; 1705 } 1706 1707 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1708 { 1709 int err; 1710 1711 err = mv88e6xxx_disable_ports(chip); 1712 if (err) 1713 return err; 1714 1715 mv88e6xxx_hardware_reset(chip); 1716 1717 return mv88e6xxx_software_reset(chip); 1718 } 1719 1720 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1721 enum mv88e6xxx_frame_mode frame, 1722 enum mv88e6xxx_egress_mode egress, u16 etype) 1723 { 1724 int err; 1725 1726 if (!chip->info->ops->port_set_frame_mode) 1727 return -EOPNOTSUPP; 1728 1729 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1730 if (err) 1731 return err; 1732 1733 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1734 if (err) 1735 return err; 1736 1737 if (chip->info->ops->port_set_ether_type) 1738 return chip->info->ops->port_set_ether_type(chip, port, etype); 1739 1740 return 0; 1741 } 1742 1743 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1744 { 1745 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1746 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1747 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1748 } 1749 1750 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1751 { 1752 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1753 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1754 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1755 } 1756 1757 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1758 { 1759 return mv88e6xxx_set_port_mode(chip, port, 1760 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1761 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1762 ETH_P_EDSA); 1763 } 1764 1765 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1766 { 1767 if (dsa_is_dsa_port(chip->ds, port)) 1768 return mv88e6xxx_set_port_mode_dsa(chip, port); 1769 1770 if (dsa_is_user_port(chip->ds, port)) 1771 return mv88e6xxx_set_port_mode_normal(chip, port); 1772 1773 /* Setup CPU port mode depending on its supported tag format */ 1774 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1775 return mv88e6xxx_set_port_mode_dsa(chip, port); 1776 1777 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1778 return mv88e6xxx_set_port_mode_edsa(chip, port); 1779 1780 return -EINVAL; 1781 } 1782 1783 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1784 { 1785 bool message = dsa_is_dsa_port(chip->ds, port); 1786 1787 return mv88e6xxx_port_set_message_port(chip, port, message); 1788 } 1789 1790 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1791 { 1792 struct dsa_switch *ds = chip->ds; 1793 bool flood; 1794 1795 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1796 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 1797 if (chip->info->ops->port_set_egress_floods) 1798 return chip->info->ops->port_set_egress_floods(chip, port, 1799 flood, flood); 1800 1801 return 0; 1802 } 1803 1804 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1805 bool on) 1806 { 1807 if (chip->info->ops->serdes_power) 1808 return chip->info->ops->serdes_power(chip, port, on); 1809 1810 return 0; 1811 } 1812 1813 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 1814 { 1815 struct dsa_switch *ds = chip->ds; 1816 int upstream_port; 1817 int err; 1818 1819 upstream_port = dsa_upstream_port(ds, port); 1820 if (chip->info->ops->port_set_upstream_port) { 1821 err = chip->info->ops->port_set_upstream_port(chip, port, 1822 upstream_port); 1823 if (err) 1824 return err; 1825 } 1826 1827 if (port == upstream_port) { 1828 if (chip->info->ops->set_cpu_port) { 1829 err = chip->info->ops->set_cpu_port(chip, 1830 upstream_port); 1831 if (err) 1832 return err; 1833 } 1834 1835 if (chip->info->ops->set_egress_port) { 1836 err = chip->info->ops->set_egress_port(chip, 1837 upstream_port); 1838 if (err) 1839 return err; 1840 } 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1847 { 1848 struct dsa_switch *ds = chip->ds; 1849 int err; 1850 u16 reg; 1851 1852 /* MAC Forcing register: don't force link, speed, duplex or flow control 1853 * state to any particular values on physical ports, but force the CPU 1854 * port and all DSA ports to their maximum bandwidth and full duplex. 1855 */ 1856 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1857 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1858 SPEED_MAX, DUPLEX_FULL, 1859 PHY_INTERFACE_MODE_NA); 1860 else 1861 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1862 SPEED_UNFORCED, DUPLEX_UNFORCED, 1863 PHY_INTERFACE_MODE_NA); 1864 if (err) 1865 return err; 1866 1867 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1868 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1869 * tunneling, determine priority by looking at 802.1p and IP 1870 * priority fields (IP prio has precedence), and set STP state 1871 * to Forwarding. 1872 * 1873 * If this is the CPU link, use DSA or EDSA tagging depending 1874 * on which tagging mode was configured. 1875 * 1876 * If this is a link to another switch, use DSA tagging mode. 1877 * 1878 * If this is the upstream port for this switch, enable 1879 * forwarding of unknown unicasts and multicasts. 1880 */ 1881 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1882 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1883 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1884 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1885 if (err) 1886 return err; 1887 1888 err = mv88e6xxx_setup_port_mode(chip, port); 1889 if (err) 1890 return err; 1891 1892 err = mv88e6xxx_setup_egress_floods(chip, port); 1893 if (err) 1894 return err; 1895 1896 /* Enable the SERDES interface for DSA and CPU ports. Normal 1897 * ports SERDES are enabled when the port is enabled, thus 1898 * saving a bit of power. 1899 */ 1900 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1901 err = mv88e6xxx_serdes_power(chip, port, true); 1902 if (err) 1903 return err; 1904 } 1905 1906 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1907 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1908 * untagged frames on this port, do a destination address lookup on all 1909 * received packets as usual, disable ARP mirroring and don't send a 1910 * copy of all transmitted/received frames on this port to the CPU. 1911 */ 1912 err = mv88e6xxx_port_set_map_da(chip, port); 1913 if (err) 1914 return err; 1915 1916 err = mv88e6xxx_setup_upstream_port(chip, port); 1917 if (err) 1918 return err; 1919 1920 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1921 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1922 if (err) 1923 return err; 1924 1925 if (chip->info->ops->port_set_jumbo_size) { 1926 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1927 if (err) 1928 return err; 1929 } 1930 1931 /* Port Association Vector: when learning source addresses 1932 * of packets, add the address to the address database using 1933 * a port bitmap that has only the bit for this port set and 1934 * the other bits clear. 1935 */ 1936 reg = 1 << port; 1937 /* Disable learning for CPU port */ 1938 if (dsa_is_cpu_port(ds, port)) 1939 reg = 0; 1940 1941 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1942 reg); 1943 if (err) 1944 return err; 1945 1946 /* Egress rate control 2: disable egress rate control. */ 1947 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1948 0x0000); 1949 if (err) 1950 return err; 1951 1952 if (chip->info->ops->port_pause_limit) { 1953 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1954 if (err) 1955 return err; 1956 } 1957 1958 if (chip->info->ops->port_disable_learn_limit) { 1959 err = chip->info->ops->port_disable_learn_limit(chip, port); 1960 if (err) 1961 return err; 1962 } 1963 1964 if (chip->info->ops->port_disable_pri_override) { 1965 err = chip->info->ops->port_disable_pri_override(chip, port); 1966 if (err) 1967 return err; 1968 } 1969 1970 if (chip->info->ops->port_tag_remap) { 1971 err = chip->info->ops->port_tag_remap(chip, port); 1972 if (err) 1973 return err; 1974 } 1975 1976 if (chip->info->ops->port_egress_rate_limiting) { 1977 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1978 if (err) 1979 return err; 1980 } 1981 1982 err = mv88e6xxx_setup_message_port(chip, port); 1983 if (err) 1984 return err; 1985 1986 /* Port based VLAN map: give each port the same default address 1987 * database, and allow bidirectional communication between the 1988 * CPU and DSA port(s), and the other ports. 1989 */ 1990 err = mv88e6xxx_port_set_fid(chip, port, 0); 1991 if (err) 1992 return err; 1993 1994 err = mv88e6xxx_port_vlan_map(chip, port); 1995 if (err) 1996 return err; 1997 1998 /* Default VLAN ID and priority: don't set a default VLAN 1999 * ID, and set the default packet priority to zero. 2000 */ 2001 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2002 } 2003 2004 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2005 struct phy_device *phydev) 2006 { 2007 struct mv88e6xxx_chip *chip = ds->priv; 2008 int err; 2009 2010 mutex_lock(&chip->reg_lock); 2011 err = mv88e6xxx_serdes_power(chip, port, true); 2012 mutex_unlock(&chip->reg_lock); 2013 2014 return err; 2015 } 2016 2017 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2018 struct phy_device *phydev) 2019 { 2020 struct mv88e6xxx_chip *chip = ds->priv; 2021 2022 mutex_lock(&chip->reg_lock); 2023 if (mv88e6xxx_serdes_power(chip, port, false)) 2024 dev_err(chip->dev, "failed to power off SERDES\n"); 2025 mutex_unlock(&chip->reg_lock); 2026 } 2027 2028 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2029 unsigned int ageing_time) 2030 { 2031 struct mv88e6xxx_chip *chip = ds->priv; 2032 int err; 2033 2034 mutex_lock(&chip->reg_lock); 2035 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2036 mutex_unlock(&chip->reg_lock); 2037 2038 return err; 2039 } 2040 2041 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2042 { 2043 struct dsa_switch *ds = chip->ds; 2044 int err; 2045 2046 /* Disable remote management, and set the switch's DSA device number. */ 2047 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 2048 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 2049 (ds->index & 0x1f)); 2050 if (err) 2051 return err; 2052 2053 /* Configure the IP ToS mapping registers. */ 2054 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 2055 if (err) 2056 return err; 2057 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 2058 if (err) 2059 return err; 2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 2061 if (err) 2062 return err; 2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 2064 if (err) 2065 return err; 2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 2067 if (err) 2068 return err; 2069 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 2070 if (err) 2071 return err; 2072 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 2073 if (err) 2074 return err; 2075 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 2076 if (err) 2077 return err; 2078 2079 /* Configure the IEEE 802.1p priority mapping register. */ 2080 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 2081 if (err) 2082 return err; 2083 2084 /* Initialize the statistics unit */ 2085 err = mv88e6xxx_stats_set_histogram(chip); 2086 if (err) 2087 return err; 2088 2089 return mv88e6xxx_g1_stats_clear(chip); 2090 } 2091 2092 static int mv88e6xxx_setup(struct dsa_switch *ds) 2093 { 2094 struct mv88e6xxx_chip *chip = ds->priv; 2095 int err; 2096 int i; 2097 2098 chip->ds = ds; 2099 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2100 2101 mutex_lock(&chip->reg_lock); 2102 2103 /* Setup Switch Port Registers */ 2104 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2105 if (dsa_is_unused_port(ds, i)) 2106 continue; 2107 2108 err = mv88e6xxx_setup_port(chip, i); 2109 if (err) 2110 goto unlock; 2111 } 2112 2113 /* Setup Switch Global 1 Registers */ 2114 err = mv88e6xxx_g1_setup(chip); 2115 if (err) 2116 goto unlock; 2117 2118 /* Setup Switch Global 2 Registers */ 2119 if (chip->info->global2_addr) { 2120 err = mv88e6xxx_g2_setup(chip); 2121 if (err) 2122 goto unlock; 2123 } 2124 2125 err = mv88e6xxx_irl_setup(chip); 2126 if (err) 2127 goto unlock; 2128 2129 err = mv88e6xxx_mac_setup(chip); 2130 if (err) 2131 goto unlock; 2132 2133 err = mv88e6xxx_phy_setup(chip); 2134 if (err) 2135 goto unlock; 2136 2137 err = mv88e6xxx_vtu_setup(chip); 2138 if (err) 2139 goto unlock; 2140 2141 err = mv88e6xxx_pvt_setup(chip); 2142 if (err) 2143 goto unlock; 2144 2145 err = mv88e6xxx_atu_setup(chip); 2146 if (err) 2147 goto unlock; 2148 2149 err = mv88e6xxx_broadcast_setup(chip, 0); 2150 if (err) 2151 goto unlock; 2152 2153 err = mv88e6xxx_pot_setup(chip); 2154 if (err) 2155 goto unlock; 2156 2157 err = mv88e6xxx_rsvd2cpu_setup(chip); 2158 if (err) 2159 goto unlock; 2160 2161 /* Setup PTP Hardware Clock and timestamping */ 2162 if (chip->info->ptp_support) { 2163 err = mv88e6xxx_ptp_setup(chip); 2164 if (err) 2165 goto unlock; 2166 2167 err = mv88e6xxx_hwtstamp_setup(chip); 2168 if (err) 2169 goto unlock; 2170 } 2171 2172 unlock: 2173 mutex_unlock(&chip->reg_lock); 2174 2175 return err; 2176 } 2177 2178 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2179 { 2180 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2181 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2182 u16 val; 2183 int err; 2184 2185 if (!chip->info->ops->phy_read) 2186 return -EOPNOTSUPP; 2187 2188 mutex_lock(&chip->reg_lock); 2189 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2190 mutex_unlock(&chip->reg_lock); 2191 2192 if (reg == MII_PHYSID2) { 2193 /* Some internal PHYS don't have a model number. Use 2194 * the mv88e6390 family model number instead. 2195 */ 2196 if (!(val & 0x3f0)) 2197 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2198 } 2199 2200 return err ? err : val; 2201 } 2202 2203 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2204 { 2205 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2206 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2207 int err; 2208 2209 if (!chip->info->ops->phy_write) 2210 return -EOPNOTSUPP; 2211 2212 mutex_lock(&chip->reg_lock); 2213 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2214 mutex_unlock(&chip->reg_lock); 2215 2216 return err; 2217 } 2218 2219 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2220 struct device_node *np, 2221 bool external) 2222 { 2223 static int index; 2224 struct mv88e6xxx_mdio_bus *mdio_bus; 2225 struct mii_bus *bus; 2226 int err; 2227 2228 if (external) { 2229 mutex_lock(&chip->reg_lock); 2230 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2231 mutex_unlock(&chip->reg_lock); 2232 2233 if (err) 2234 return err; 2235 } 2236 2237 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2238 if (!bus) 2239 return -ENOMEM; 2240 2241 mdio_bus = bus->priv; 2242 mdio_bus->bus = bus; 2243 mdio_bus->chip = chip; 2244 INIT_LIST_HEAD(&mdio_bus->list); 2245 mdio_bus->external = external; 2246 2247 if (np) { 2248 bus->name = np->full_name; 2249 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2250 } else { 2251 bus->name = "mv88e6xxx SMI"; 2252 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2253 } 2254 2255 bus->read = mv88e6xxx_mdio_read; 2256 bus->write = mv88e6xxx_mdio_write; 2257 bus->parent = chip->dev; 2258 2259 if (np) 2260 err = of_mdiobus_register(bus, np); 2261 else 2262 err = mdiobus_register(bus); 2263 if (err) { 2264 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2265 return err; 2266 } 2267 2268 if (external) 2269 list_add_tail(&mdio_bus->list, &chip->mdios); 2270 else 2271 list_add(&mdio_bus->list, &chip->mdios); 2272 2273 return 0; 2274 } 2275 2276 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2277 { .compatible = "marvell,mv88e6xxx-mdio-external", 2278 .data = (void *)true }, 2279 { }, 2280 }; 2281 2282 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2283 2284 { 2285 struct mv88e6xxx_mdio_bus *mdio_bus; 2286 struct mii_bus *bus; 2287 2288 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2289 bus = mdio_bus->bus; 2290 2291 mdiobus_unregister(bus); 2292 } 2293 } 2294 2295 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2296 struct device_node *np) 2297 { 2298 const struct of_device_id *match; 2299 struct device_node *child; 2300 int err; 2301 2302 /* Always register one mdio bus for the internal/default mdio 2303 * bus. This maybe represented in the device tree, but is 2304 * optional. 2305 */ 2306 child = of_get_child_by_name(np, "mdio"); 2307 err = mv88e6xxx_mdio_register(chip, child, false); 2308 if (err) 2309 return err; 2310 2311 /* Walk the device tree, and see if there are any other nodes 2312 * which say they are compatible with the external mdio 2313 * bus. 2314 */ 2315 for_each_available_child_of_node(np, child) { 2316 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2317 if (match) { 2318 err = mv88e6xxx_mdio_register(chip, child, true); 2319 if (err) { 2320 mv88e6xxx_mdios_unregister(chip); 2321 return err; 2322 } 2323 } 2324 } 2325 2326 return 0; 2327 } 2328 2329 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2330 { 2331 struct mv88e6xxx_chip *chip = ds->priv; 2332 2333 return chip->eeprom_len; 2334 } 2335 2336 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2337 struct ethtool_eeprom *eeprom, u8 *data) 2338 { 2339 struct mv88e6xxx_chip *chip = ds->priv; 2340 int err; 2341 2342 if (!chip->info->ops->get_eeprom) 2343 return -EOPNOTSUPP; 2344 2345 mutex_lock(&chip->reg_lock); 2346 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2347 mutex_unlock(&chip->reg_lock); 2348 2349 if (err) 2350 return err; 2351 2352 eeprom->magic = 0xc3ec4951; 2353 2354 return 0; 2355 } 2356 2357 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2358 struct ethtool_eeprom *eeprom, u8 *data) 2359 { 2360 struct mv88e6xxx_chip *chip = ds->priv; 2361 int err; 2362 2363 if (!chip->info->ops->set_eeprom) 2364 return -EOPNOTSUPP; 2365 2366 if (eeprom->magic != 0xc3ec4951) 2367 return -EINVAL; 2368 2369 mutex_lock(&chip->reg_lock); 2370 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2371 mutex_unlock(&chip->reg_lock); 2372 2373 return err; 2374 } 2375 2376 static const struct mv88e6xxx_ops mv88e6085_ops = { 2377 /* MV88E6XXX_FAMILY_6097 */ 2378 .irl_init_all = mv88e6352_g2_irl_init_all, 2379 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2380 .phy_read = mv88e6185_phy_ppu_read, 2381 .phy_write = mv88e6185_phy_ppu_write, 2382 .port_set_link = mv88e6xxx_port_set_link, 2383 .port_set_duplex = mv88e6xxx_port_set_duplex, 2384 .port_set_speed = mv88e6185_port_set_speed, 2385 .port_tag_remap = mv88e6095_port_tag_remap, 2386 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2387 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2388 .port_set_ether_type = mv88e6351_port_set_ether_type, 2389 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2390 .port_pause_limit = mv88e6097_port_pause_limit, 2391 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2392 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2393 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2394 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2395 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2396 .stats_get_strings = mv88e6095_stats_get_strings, 2397 .stats_get_stats = mv88e6095_stats_get_stats, 2398 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2399 .set_egress_port = mv88e6095_g1_set_egress_port, 2400 .watchdog_ops = &mv88e6097_watchdog_ops, 2401 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2402 .pot_clear = mv88e6xxx_g2_pot_clear, 2403 .ppu_enable = mv88e6185_g1_ppu_enable, 2404 .ppu_disable = mv88e6185_g1_ppu_disable, 2405 .reset = mv88e6185_g1_reset, 2406 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2407 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2408 }; 2409 2410 static const struct mv88e6xxx_ops mv88e6095_ops = { 2411 /* MV88E6XXX_FAMILY_6095 */ 2412 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2413 .phy_read = mv88e6185_phy_ppu_read, 2414 .phy_write = mv88e6185_phy_ppu_write, 2415 .port_set_link = mv88e6xxx_port_set_link, 2416 .port_set_duplex = mv88e6xxx_port_set_duplex, 2417 .port_set_speed = mv88e6185_port_set_speed, 2418 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2419 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2420 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2421 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2422 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2423 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2424 .stats_get_strings = mv88e6095_stats_get_strings, 2425 .stats_get_stats = mv88e6095_stats_get_stats, 2426 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2427 .ppu_enable = mv88e6185_g1_ppu_enable, 2428 .ppu_disable = mv88e6185_g1_ppu_disable, 2429 .reset = mv88e6185_g1_reset, 2430 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2431 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2432 }; 2433 2434 static const struct mv88e6xxx_ops mv88e6097_ops = { 2435 /* MV88E6XXX_FAMILY_6097 */ 2436 .irl_init_all = mv88e6352_g2_irl_init_all, 2437 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2438 .phy_read = mv88e6xxx_g2_smi_phy_read, 2439 .phy_write = mv88e6xxx_g2_smi_phy_write, 2440 .port_set_link = mv88e6xxx_port_set_link, 2441 .port_set_duplex = mv88e6xxx_port_set_duplex, 2442 .port_set_speed = mv88e6185_port_set_speed, 2443 .port_tag_remap = mv88e6095_port_tag_remap, 2444 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2445 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2446 .port_set_ether_type = mv88e6351_port_set_ether_type, 2447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2448 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2449 .port_pause_limit = mv88e6097_port_pause_limit, 2450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2452 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2453 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2454 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2455 .stats_get_strings = mv88e6095_stats_get_strings, 2456 .stats_get_stats = mv88e6095_stats_get_stats, 2457 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2458 .set_egress_port = mv88e6095_g1_set_egress_port, 2459 .watchdog_ops = &mv88e6097_watchdog_ops, 2460 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2461 .pot_clear = mv88e6xxx_g2_pot_clear, 2462 .reset = mv88e6352_g1_reset, 2463 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2464 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2465 }; 2466 2467 static const struct mv88e6xxx_ops mv88e6123_ops = { 2468 /* MV88E6XXX_FAMILY_6165 */ 2469 .irl_init_all = mv88e6352_g2_irl_init_all, 2470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2471 .phy_read = mv88e6xxx_g2_smi_phy_read, 2472 .phy_write = mv88e6xxx_g2_smi_phy_write, 2473 .port_set_link = mv88e6xxx_port_set_link, 2474 .port_set_duplex = mv88e6xxx_port_set_duplex, 2475 .port_set_speed = mv88e6185_port_set_speed, 2476 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2477 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2478 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2479 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2480 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2481 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2482 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2483 .stats_get_strings = mv88e6095_stats_get_strings, 2484 .stats_get_stats = mv88e6095_stats_get_stats, 2485 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2486 .set_egress_port = mv88e6095_g1_set_egress_port, 2487 .watchdog_ops = &mv88e6097_watchdog_ops, 2488 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2489 .pot_clear = mv88e6xxx_g2_pot_clear, 2490 .reset = mv88e6352_g1_reset, 2491 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2492 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2493 }; 2494 2495 static const struct mv88e6xxx_ops mv88e6131_ops = { 2496 /* MV88E6XXX_FAMILY_6185 */ 2497 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2498 .phy_read = mv88e6185_phy_ppu_read, 2499 .phy_write = mv88e6185_phy_ppu_write, 2500 .port_set_link = mv88e6xxx_port_set_link, 2501 .port_set_duplex = mv88e6xxx_port_set_duplex, 2502 .port_set_speed = mv88e6185_port_set_speed, 2503 .port_tag_remap = mv88e6095_port_tag_remap, 2504 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2505 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2506 .port_set_ether_type = mv88e6351_port_set_ether_type, 2507 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2508 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2509 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2510 .port_pause_limit = mv88e6097_port_pause_limit, 2511 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2513 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2514 .stats_get_strings = mv88e6095_stats_get_strings, 2515 .stats_get_stats = mv88e6095_stats_get_stats, 2516 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2517 .set_egress_port = mv88e6095_g1_set_egress_port, 2518 .watchdog_ops = &mv88e6097_watchdog_ops, 2519 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2520 .ppu_enable = mv88e6185_g1_ppu_enable, 2521 .ppu_disable = mv88e6185_g1_ppu_disable, 2522 .reset = mv88e6185_g1_reset, 2523 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2524 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2525 }; 2526 2527 static const struct mv88e6xxx_ops mv88e6141_ops = { 2528 /* MV88E6XXX_FAMILY_6341 */ 2529 .irl_init_all = mv88e6352_g2_irl_init_all, 2530 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2531 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2532 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2533 .phy_read = mv88e6xxx_g2_smi_phy_read, 2534 .phy_write = mv88e6xxx_g2_smi_phy_write, 2535 .port_set_link = mv88e6xxx_port_set_link, 2536 .port_set_duplex = mv88e6xxx_port_set_duplex, 2537 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2538 .port_set_speed = mv88e6390_port_set_speed, 2539 .port_tag_remap = mv88e6095_port_tag_remap, 2540 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2541 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2542 .port_set_ether_type = mv88e6351_port_set_ether_type, 2543 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2544 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2545 .port_pause_limit = mv88e6097_port_pause_limit, 2546 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2547 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2548 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2549 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2550 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2551 .stats_get_strings = mv88e6320_stats_get_strings, 2552 .stats_get_stats = mv88e6390_stats_get_stats, 2553 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2554 .set_egress_port = mv88e6390_g1_set_egress_port, 2555 .watchdog_ops = &mv88e6390_watchdog_ops, 2556 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2557 .pot_clear = mv88e6xxx_g2_pot_clear, 2558 .reset = mv88e6352_g1_reset, 2559 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2560 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2561 .gpio_ops = &mv88e6352_gpio_ops, 2562 }; 2563 2564 static const struct mv88e6xxx_ops mv88e6161_ops = { 2565 /* MV88E6XXX_FAMILY_6165 */ 2566 .irl_init_all = mv88e6352_g2_irl_init_all, 2567 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2568 .phy_read = mv88e6xxx_g2_smi_phy_read, 2569 .phy_write = mv88e6xxx_g2_smi_phy_write, 2570 .port_set_link = mv88e6xxx_port_set_link, 2571 .port_set_duplex = mv88e6xxx_port_set_duplex, 2572 .port_set_speed = mv88e6185_port_set_speed, 2573 .port_tag_remap = mv88e6095_port_tag_remap, 2574 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2575 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2576 .port_set_ether_type = mv88e6351_port_set_ether_type, 2577 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2578 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2579 .port_pause_limit = mv88e6097_port_pause_limit, 2580 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2581 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2582 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2583 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2584 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2585 .stats_get_strings = mv88e6095_stats_get_strings, 2586 .stats_get_stats = mv88e6095_stats_get_stats, 2587 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2588 .set_egress_port = mv88e6095_g1_set_egress_port, 2589 .watchdog_ops = &mv88e6097_watchdog_ops, 2590 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2591 .pot_clear = mv88e6xxx_g2_pot_clear, 2592 .reset = mv88e6352_g1_reset, 2593 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2595 }; 2596 2597 static const struct mv88e6xxx_ops mv88e6165_ops = { 2598 /* MV88E6XXX_FAMILY_6165 */ 2599 .irl_init_all = mv88e6352_g2_irl_init_all, 2600 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2601 .phy_read = mv88e6165_phy_read, 2602 .phy_write = mv88e6165_phy_write, 2603 .port_set_link = mv88e6xxx_port_set_link, 2604 .port_set_duplex = mv88e6xxx_port_set_duplex, 2605 .port_set_speed = mv88e6185_port_set_speed, 2606 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2607 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2608 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2609 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2610 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2611 .stats_get_strings = mv88e6095_stats_get_strings, 2612 .stats_get_stats = mv88e6095_stats_get_stats, 2613 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2614 .set_egress_port = mv88e6095_g1_set_egress_port, 2615 .watchdog_ops = &mv88e6097_watchdog_ops, 2616 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2617 .pot_clear = mv88e6xxx_g2_pot_clear, 2618 .reset = mv88e6352_g1_reset, 2619 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2620 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2621 }; 2622 2623 static const struct mv88e6xxx_ops mv88e6171_ops = { 2624 /* MV88E6XXX_FAMILY_6351 */ 2625 .irl_init_all = mv88e6352_g2_irl_init_all, 2626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2627 .phy_read = mv88e6xxx_g2_smi_phy_read, 2628 .phy_write = mv88e6xxx_g2_smi_phy_write, 2629 .port_set_link = mv88e6xxx_port_set_link, 2630 .port_set_duplex = mv88e6xxx_port_set_duplex, 2631 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2632 .port_set_speed = mv88e6185_port_set_speed, 2633 .port_tag_remap = mv88e6095_port_tag_remap, 2634 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2635 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2636 .port_set_ether_type = mv88e6351_port_set_ether_type, 2637 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2638 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2639 .port_pause_limit = mv88e6097_port_pause_limit, 2640 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2641 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2642 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2643 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2644 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2645 .stats_get_strings = mv88e6095_stats_get_strings, 2646 .stats_get_stats = mv88e6095_stats_get_stats, 2647 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2648 .set_egress_port = mv88e6095_g1_set_egress_port, 2649 .watchdog_ops = &mv88e6097_watchdog_ops, 2650 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2651 .pot_clear = mv88e6xxx_g2_pot_clear, 2652 .reset = mv88e6352_g1_reset, 2653 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2655 }; 2656 2657 static const struct mv88e6xxx_ops mv88e6172_ops = { 2658 /* MV88E6XXX_FAMILY_6352 */ 2659 .irl_init_all = mv88e6352_g2_irl_init_all, 2660 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2661 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2662 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2663 .phy_read = mv88e6xxx_g2_smi_phy_read, 2664 .phy_write = mv88e6xxx_g2_smi_phy_write, 2665 .port_set_link = mv88e6xxx_port_set_link, 2666 .port_set_duplex = mv88e6xxx_port_set_duplex, 2667 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2668 .port_set_speed = mv88e6352_port_set_speed, 2669 .port_tag_remap = mv88e6095_port_tag_remap, 2670 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2671 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2672 .port_set_ether_type = mv88e6351_port_set_ether_type, 2673 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2674 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2675 .port_pause_limit = mv88e6097_port_pause_limit, 2676 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2677 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2678 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2680 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2681 .stats_get_strings = mv88e6095_stats_get_strings, 2682 .stats_get_stats = mv88e6095_stats_get_stats, 2683 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2684 .set_egress_port = mv88e6095_g1_set_egress_port, 2685 .watchdog_ops = &mv88e6097_watchdog_ops, 2686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2687 .pot_clear = mv88e6xxx_g2_pot_clear, 2688 .reset = mv88e6352_g1_reset, 2689 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2690 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2691 .serdes_power = mv88e6352_serdes_power, 2692 .gpio_ops = &mv88e6352_gpio_ops, 2693 }; 2694 2695 static const struct mv88e6xxx_ops mv88e6175_ops = { 2696 /* MV88E6XXX_FAMILY_6351 */ 2697 .irl_init_all = mv88e6352_g2_irl_init_all, 2698 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2699 .phy_read = mv88e6xxx_g2_smi_phy_read, 2700 .phy_write = mv88e6xxx_g2_smi_phy_write, 2701 .port_set_link = mv88e6xxx_port_set_link, 2702 .port_set_duplex = mv88e6xxx_port_set_duplex, 2703 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2704 .port_set_speed = mv88e6185_port_set_speed, 2705 .port_tag_remap = mv88e6095_port_tag_remap, 2706 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2707 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2708 .port_set_ether_type = mv88e6351_port_set_ether_type, 2709 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2710 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2711 .port_pause_limit = mv88e6097_port_pause_limit, 2712 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2713 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2714 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2715 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2716 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2717 .stats_get_strings = mv88e6095_stats_get_strings, 2718 .stats_get_stats = mv88e6095_stats_get_stats, 2719 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2720 .set_egress_port = mv88e6095_g1_set_egress_port, 2721 .watchdog_ops = &mv88e6097_watchdog_ops, 2722 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2723 .pot_clear = mv88e6xxx_g2_pot_clear, 2724 .reset = mv88e6352_g1_reset, 2725 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2726 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2727 }; 2728 2729 static const struct mv88e6xxx_ops mv88e6176_ops = { 2730 /* MV88E6XXX_FAMILY_6352 */ 2731 .irl_init_all = mv88e6352_g2_irl_init_all, 2732 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2733 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2734 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2735 .phy_read = mv88e6xxx_g2_smi_phy_read, 2736 .phy_write = mv88e6xxx_g2_smi_phy_write, 2737 .port_set_link = mv88e6xxx_port_set_link, 2738 .port_set_duplex = mv88e6xxx_port_set_duplex, 2739 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2740 .port_set_speed = mv88e6352_port_set_speed, 2741 .port_tag_remap = mv88e6095_port_tag_remap, 2742 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2743 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2744 .port_set_ether_type = mv88e6351_port_set_ether_type, 2745 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2746 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2747 .port_pause_limit = mv88e6097_port_pause_limit, 2748 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2749 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2750 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2751 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2752 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2753 .stats_get_strings = mv88e6095_stats_get_strings, 2754 .stats_get_stats = mv88e6095_stats_get_stats, 2755 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2756 .set_egress_port = mv88e6095_g1_set_egress_port, 2757 .watchdog_ops = &mv88e6097_watchdog_ops, 2758 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2759 .pot_clear = mv88e6xxx_g2_pot_clear, 2760 .reset = mv88e6352_g1_reset, 2761 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2762 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2763 .serdes_power = mv88e6352_serdes_power, 2764 .gpio_ops = &mv88e6352_gpio_ops, 2765 }; 2766 2767 static const struct mv88e6xxx_ops mv88e6185_ops = { 2768 /* MV88E6XXX_FAMILY_6185 */ 2769 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2770 .phy_read = mv88e6185_phy_ppu_read, 2771 .phy_write = mv88e6185_phy_ppu_write, 2772 .port_set_link = mv88e6xxx_port_set_link, 2773 .port_set_duplex = mv88e6xxx_port_set_duplex, 2774 .port_set_speed = mv88e6185_port_set_speed, 2775 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2776 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2777 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2778 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2779 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2780 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2781 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2782 .stats_get_strings = mv88e6095_stats_get_strings, 2783 .stats_get_stats = mv88e6095_stats_get_stats, 2784 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2785 .set_egress_port = mv88e6095_g1_set_egress_port, 2786 .watchdog_ops = &mv88e6097_watchdog_ops, 2787 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2788 .ppu_enable = mv88e6185_g1_ppu_enable, 2789 .ppu_disable = mv88e6185_g1_ppu_disable, 2790 .reset = mv88e6185_g1_reset, 2791 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2792 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2793 }; 2794 2795 static const struct mv88e6xxx_ops mv88e6190_ops = { 2796 /* MV88E6XXX_FAMILY_6390 */ 2797 .irl_init_all = mv88e6390_g2_irl_init_all, 2798 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2799 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2800 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2801 .phy_read = mv88e6xxx_g2_smi_phy_read, 2802 .phy_write = mv88e6xxx_g2_smi_phy_write, 2803 .port_set_link = mv88e6xxx_port_set_link, 2804 .port_set_duplex = mv88e6xxx_port_set_duplex, 2805 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2806 .port_set_speed = mv88e6390_port_set_speed, 2807 .port_tag_remap = mv88e6390_port_tag_remap, 2808 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2809 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2810 .port_set_ether_type = mv88e6351_port_set_ether_type, 2811 .port_pause_limit = mv88e6390_port_pause_limit, 2812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2814 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2815 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2816 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2817 .stats_get_strings = mv88e6320_stats_get_strings, 2818 .stats_get_stats = mv88e6390_stats_get_stats, 2819 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2820 .set_egress_port = mv88e6390_g1_set_egress_port, 2821 .watchdog_ops = &mv88e6390_watchdog_ops, 2822 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2823 .pot_clear = mv88e6xxx_g2_pot_clear, 2824 .reset = mv88e6352_g1_reset, 2825 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2827 .serdes_power = mv88e6390_serdes_power, 2828 .gpio_ops = &mv88e6352_gpio_ops, 2829 }; 2830 2831 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2832 /* MV88E6XXX_FAMILY_6390 */ 2833 .irl_init_all = mv88e6390_g2_irl_init_all, 2834 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2835 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2836 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2837 .phy_read = mv88e6xxx_g2_smi_phy_read, 2838 .phy_write = mv88e6xxx_g2_smi_phy_write, 2839 .port_set_link = mv88e6xxx_port_set_link, 2840 .port_set_duplex = mv88e6xxx_port_set_duplex, 2841 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2842 .port_set_speed = mv88e6390x_port_set_speed, 2843 .port_tag_remap = mv88e6390_port_tag_remap, 2844 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2845 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2846 .port_set_ether_type = mv88e6351_port_set_ether_type, 2847 .port_pause_limit = mv88e6390_port_pause_limit, 2848 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2849 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2850 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2851 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2852 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2853 .stats_get_strings = mv88e6320_stats_get_strings, 2854 .stats_get_stats = mv88e6390_stats_get_stats, 2855 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2856 .set_egress_port = mv88e6390_g1_set_egress_port, 2857 .watchdog_ops = &mv88e6390_watchdog_ops, 2858 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2859 .pot_clear = mv88e6xxx_g2_pot_clear, 2860 .reset = mv88e6352_g1_reset, 2861 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2862 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2863 .serdes_power = mv88e6390_serdes_power, 2864 .gpio_ops = &mv88e6352_gpio_ops, 2865 }; 2866 2867 static const struct mv88e6xxx_ops mv88e6191_ops = { 2868 /* MV88E6XXX_FAMILY_6390 */ 2869 .irl_init_all = mv88e6390_g2_irl_init_all, 2870 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2871 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2872 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2873 .phy_read = mv88e6xxx_g2_smi_phy_read, 2874 .phy_write = mv88e6xxx_g2_smi_phy_write, 2875 .port_set_link = mv88e6xxx_port_set_link, 2876 .port_set_duplex = mv88e6xxx_port_set_duplex, 2877 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2878 .port_set_speed = mv88e6390_port_set_speed, 2879 .port_tag_remap = mv88e6390_port_tag_remap, 2880 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2881 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2882 .port_set_ether_type = mv88e6351_port_set_ether_type, 2883 .port_pause_limit = mv88e6390_port_pause_limit, 2884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2886 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2887 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2888 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2889 .stats_get_strings = mv88e6320_stats_get_strings, 2890 .stats_get_stats = mv88e6390_stats_get_stats, 2891 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2892 .set_egress_port = mv88e6390_g1_set_egress_port, 2893 .watchdog_ops = &mv88e6390_watchdog_ops, 2894 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2895 .pot_clear = mv88e6xxx_g2_pot_clear, 2896 .reset = mv88e6352_g1_reset, 2897 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2898 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2899 .serdes_power = mv88e6390_serdes_power, 2900 }; 2901 2902 static const struct mv88e6xxx_ops mv88e6240_ops = { 2903 /* MV88E6XXX_FAMILY_6352 */ 2904 .irl_init_all = mv88e6352_g2_irl_init_all, 2905 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2906 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2907 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2908 .phy_read = mv88e6xxx_g2_smi_phy_read, 2909 .phy_write = mv88e6xxx_g2_smi_phy_write, 2910 .port_set_link = mv88e6xxx_port_set_link, 2911 .port_set_duplex = mv88e6xxx_port_set_duplex, 2912 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2913 .port_set_speed = mv88e6352_port_set_speed, 2914 .port_tag_remap = mv88e6095_port_tag_remap, 2915 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2916 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2917 .port_set_ether_type = mv88e6351_port_set_ether_type, 2918 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2919 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2920 .port_pause_limit = mv88e6097_port_pause_limit, 2921 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2922 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2923 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2924 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2925 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2926 .stats_get_strings = mv88e6095_stats_get_strings, 2927 .stats_get_stats = mv88e6095_stats_get_stats, 2928 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2929 .set_egress_port = mv88e6095_g1_set_egress_port, 2930 .watchdog_ops = &mv88e6097_watchdog_ops, 2931 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2932 .pot_clear = mv88e6xxx_g2_pot_clear, 2933 .reset = mv88e6352_g1_reset, 2934 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2935 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2936 .serdes_power = mv88e6352_serdes_power, 2937 .gpio_ops = &mv88e6352_gpio_ops, 2938 .avb_ops = &mv88e6352_avb_ops, 2939 }; 2940 2941 static const struct mv88e6xxx_ops mv88e6290_ops = { 2942 /* MV88E6XXX_FAMILY_6390 */ 2943 .irl_init_all = mv88e6390_g2_irl_init_all, 2944 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2945 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2946 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2947 .phy_read = mv88e6xxx_g2_smi_phy_read, 2948 .phy_write = mv88e6xxx_g2_smi_phy_write, 2949 .port_set_link = mv88e6xxx_port_set_link, 2950 .port_set_duplex = mv88e6xxx_port_set_duplex, 2951 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2952 .port_set_speed = mv88e6390_port_set_speed, 2953 .port_tag_remap = mv88e6390_port_tag_remap, 2954 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2955 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2956 .port_set_ether_type = mv88e6351_port_set_ether_type, 2957 .port_pause_limit = mv88e6390_port_pause_limit, 2958 .port_set_cmode = mv88e6390x_port_set_cmode, 2959 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2960 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2961 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2962 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2963 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2964 .stats_get_strings = mv88e6320_stats_get_strings, 2965 .stats_get_stats = mv88e6390_stats_get_stats, 2966 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2967 .set_egress_port = mv88e6390_g1_set_egress_port, 2968 .watchdog_ops = &mv88e6390_watchdog_ops, 2969 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2970 .pot_clear = mv88e6xxx_g2_pot_clear, 2971 .reset = mv88e6352_g1_reset, 2972 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2973 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2974 .serdes_power = mv88e6390_serdes_power, 2975 .gpio_ops = &mv88e6352_gpio_ops, 2976 .avb_ops = &mv88e6390_avb_ops, 2977 }; 2978 2979 static const struct mv88e6xxx_ops mv88e6320_ops = { 2980 /* MV88E6XXX_FAMILY_6320 */ 2981 .irl_init_all = mv88e6352_g2_irl_init_all, 2982 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2983 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2984 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2985 .phy_read = mv88e6xxx_g2_smi_phy_read, 2986 .phy_write = mv88e6xxx_g2_smi_phy_write, 2987 .port_set_link = mv88e6xxx_port_set_link, 2988 .port_set_duplex = mv88e6xxx_port_set_duplex, 2989 .port_set_speed = mv88e6185_port_set_speed, 2990 .port_tag_remap = mv88e6095_port_tag_remap, 2991 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2992 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2993 .port_set_ether_type = mv88e6351_port_set_ether_type, 2994 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2995 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2996 .port_pause_limit = mv88e6097_port_pause_limit, 2997 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2998 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2999 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3000 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3001 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3002 .stats_get_strings = mv88e6320_stats_get_strings, 3003 .stats_get_stats = mv88e6320_stats_get_stats, 3004 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3005 .set_egress_port = mv88e6095_g1_set_egress_port, 3006 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3007 .pot_clear = mv88e6xxx_g2_pot_clear, 3008 .reset = mv88e6352_g1_reset, 3009 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3010 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3011 .gpio_ops = &mv88e6352_gpio_ops, 3012 .avb_ops = &mv88e6352_avb_ops, 3013 }; 3014 3015 static const struct mv88e6xxx_ops mv88e6321_ops = { 3016 /* MV88E6XXX_FAMILY_6320 */ 3017 .irl_init_all = mv88e6352_g2_irl_init_all, 3018 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3019 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3020 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3021 .phy_read = mv88e6xxx_g2_smi_phy_read, 3022 .phy_write = mv88e6xxx_g2_smi_phy_write, 3023 .port_set_link = mv88e6xxx_port_set_link, 3024 .port_set_duplex = mv88e6xxx_port_set_duplex, 3025 .port_set_speed = mv88e6185_port_set_speed, 3026 .port_tag_remap = mv88e6095_port_tag_remap, 3027 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3028 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3029 .port_set_ether_type = mv88e6351_port_set_ether_type, 3030 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3031 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3032 .port_pause_limit = mv88e6097_port_pause_limit, 3033 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3034 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3035 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3036 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3037 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3038 .stats_get_strings = mv88e6320_stats_get_strings, 3039 .stats_get_stats = mv88e6320_stats_get_stats, 3040 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3041 .set_egress_port = mv88e6095_g1_set_egress_port, 3042 .reset = mv88e6352_g1_reset, 3043 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3044 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3045 .gpio_ops = &mv88e6352_gpio_ops, 3046 .avb_ops = &mv88e6352_avb_ops, 3047 }; 3048 3049 static const struct mv88e6xxx_ops mv88e6341_ops = { 3050 /* MV88E6XXX_FAMILY_6341 */ 3051 .irl_init_all = mv88e6352_g2_irl_init_all, 3052 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3053 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3054 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3055 .phy_read = mv88e6xxx_g2_smi_phy_read, 3056 .phy_write = mv88e6xxx_g2_smi_phy_write, 3057 .port_set_link = mv88e6xxx_port_set_link, 3058 .port_set_duplex = mv88e6xxx_port_set_duplex, 3059 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3060 .port_set_speed = mv88e6390_port_set_speed, 3061 .port_tag_remap = mv88e6095_port_tag_remap, 3062 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3063 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3064 .port_set_ether_type = mv88e6351_port_set_ether_type, 3065 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3066 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3067 .port_pause_limit = mv88e6097_port_pause_limit, 3068 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3069 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3070 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3071 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3072 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3073 .stats_get_strings = mv88e6320_stats_get_strings, 3074 .stats_get_stats = mv88e6390_stats_get_stats, 3075 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3076 .set_egress_port = mv88e6390_g1_set_egress_port, 3077 .watchdog_ops = &mv88e6390_watchdog_ops, 3078 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3079 .pot_clear = mv88e6xxx_g2_pot_clear, 3080 .reset = mv88e6352_g1_reset, 3081 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3082 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3083 .gpio_ops = &mv88e6352_gpio_ops, 3084 .avb_ops = &mv88e6390_avb_ops, 3085 }; 3086 3087 static const struct mv88e6xxx_ops mv88e6350_ops = { 3088 /* MV88E6XXX_FAMILY_6351 */ 3089 .irl_init_all = mv88e6352_g2_irl_init_all, 3090 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3091 .phy_read = mv88e6xxx_g2_smi_phy_read, 3092 .phy_write = mv88e6xxx_g2_smi_phy_write, 3093 .port_set_link = mv88e6xxx_port_set_link, 3094 .port_set_duplex = mv88e6xxx_port_set_duplex, 3095 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3096 .port_set_speed = mv88e6185_port_set_speed, 3097 .port_tag_remap = mv88e6095_port_tag_remap, 3098 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3099 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3100 .port_set_ether_type = mv88e6351_port_set_ether_type, 3101 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3102 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3103 .port_pause_limit = mv88e6097_port_pause_limit, 3104 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3105 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3106 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3107 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3108 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3109 .stats_get_strings = mv88e6095_stats_get_strings, 3110 .stats_get_stats = mv88e6095_stats_get_stats, 3111 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3112 .set_egress_port = mv88e6095_g1_set_egress_port, 3113 .watchdog_ops = &mv88e6097_watchdog_ops, 3114 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3115 .pot_clear = mv88e6xxx_g2_pot_clear, 3116 .reset = mv88e6352_g1_reset, 3117 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3118 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3119 }; 3120 3121 static const struct mv88e6xxx_ops mv88e6351_ops = { 3122 /* MV88E6XXX_FAMILY_6351 */ 3123 .irl_init_all = mv88e6352_g2_irl_init_all, 3124 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3125 .phy_read = mv88e6xxx_g2_smi_phy_read, 3126 .phy_write = mv88e6xxx_g2_smi_phy_write, 3127 .port_set_link = mv88e6xxx_port_set_link, 3128 .port_set_duplex = mv88e6xxx_port_set_duplex, 3129 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3130 .port_set_speed = mv88e6185_port_set_speed, 3131 .port_tag_remap = mv88e6095_port_tag_remap, 3132 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3133 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3134 .port_set_ether_type = mv88e6351_port_set_ether_type, 3135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3136 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3137 .port_pause_limit = mv88e6097_port_pause_limit, 3138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3140 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3141 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3142 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3143 .stats_get_strings = mv88e6095_stats_get_strings, 3144 .stats_get_stats = mv88e6095_stats_get_stats, 3145 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3146 .set_egress_port = mv88e6095_g1_set_egress_port, 3147 .watchdog_ops = &mv88e6097_watchdog_ops, 3148 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3149 .pot_clear = mv88e6xxx_g2_pot_clear, 3150 .reset = mv88e6352_g1_reset, 3151 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3152 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3153 .avb_ops = &mv88e6352_avb_ops, 3154 }; 3155 3156 static const struct mv88e6xxx_ops mv88e6352_ops = { 3157 /* MV88E6XXX_FAMILY_6352 */ 3158 .irl_init_all = mv88e6352_g2_irl_init_all, 3159 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3160 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3161 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3162 .phy_read = mv88e6xxx_g2_smi_phy_read, 3163 .phy_write = mv88e6xxx_g2_smi_phy_write, 3164 .port_set_link = mv88e6xxx_port_set_link, 3165 .port_set_duplex = mv88e6xxx_port_set_duplex, 3166 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3167 .port_set_speed = mv88e6352_port_set_speed, 3168 .port_tag_remap = mv88e6095_port_tag_remap, 3169 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3170 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3171 .port_set_ether_type = mv88e6351_port_set_ether_type, 3172 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3173 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3174 .port_pause_limit = mv88e6097_port_pause_limit, 3175 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3176 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3177 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3178 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3179 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3180 .stats_get_strings = mv88e6095_stats_get_strings, 3181 .stats_get_stats = mv88e6095_stats_get_stats, 3182 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3183 .set_egress_port = mv88e6095_g1_set_egress_port, 3184 .watchdog_ops = &mv88e6097_watchdog_ops, 3185 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3186 .pot_clear = mv88e6xxx_g2_pot_clear, 3187 .reset = mv88e6352_g1_reset, 3188 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3189 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3190 .serdes_power = mv88e6352_serdes_power, 3191 .gpio_ops = &mv88e6352_gpio_ops, 3192 .avb_ops = &mv88e6352_avb_ops, 3193 }; 3194 3195 static const struct mv88e6xxx_ops mv88e6390_ops = { 3196 /* MV88E6XXX_FAMILY_6390 */ 3197 .irl_init_all = mv88e6390_g2_irl_init_all, 3198 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3199 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3200 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3201 .phy_read = mv88e6xxx_g2_smi_phy_read, 3202 .phy_write = mv88e6xxx_g2_smi_phy_write, 3203 .port_set_link = mv88e6xxx_port_set_link, 3204 .port_set_duplex = mv88e6xxx_port_set_duplex, 3205 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3206 .port_set_speed = mv88e6390_port_set_speed, 3207 .port_tag_remap = mv88e6390_port_tag_remap, 3208 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3209 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3210 .port_set_ether_type = mv88e6351_port_set_ether_type, 3211 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3212 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3213 .port_pause_limit = mv88e6390_port_pause_limit, 3214 .port_set_cmode = mv88e6390x_port_set_cmode, 3215 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3216 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3217 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3218 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3219 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3220 .stats_get_strings = mv88e6320_stats_get_strings, 3221 .stats_get_stats = mv88e6390_stats_get_stats, 3222 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3223 .set_egress_port = mv88e6390_g1_set_egress_port, 3224 .watchdog_ops = &mv88e6390_watchdog_ops, 3225 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3226 .pot_clear = mv88e6xxx_g2_pot_clear, 3227 .reset = mv88e6352_g1_reset, 3228 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3229 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3230 .serdes_power = mv88e6390_serdes_power, 3231 .gpio_ops = &mv88e6352_gpio_ops, 3232 .avb_ops = &mv88e6390_avb_ops, 3233 }; 3234 3235 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3236 /* MV88E6XXX_FAMILY_6390 */ 3237 .irl_init_all = mv88e6390_g2_irl_init_all, 3238 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3239 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3240 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3241 .phy_read = mv88e6xxx_g2_smi_phy_read, 3242 .phy_write = mv88e6xxx_g2_smi_phy_write, 3243 .port_set_link = mv88e6xxx_port_set_link, 3244 .port_set_duplex = mv88e6xxx_port_set_duplex, 3245 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3246 .port_set_speed = mv88e6390x_port_set_speed, 3247 .port_tag_remap = mv88e6390_port_tag_remap, 3248 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3249 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3250 .port_set_ether_type = mv88e6351_port_set_ether_type, 3251 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3252 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3253 .port_pause_limit = mv88e6390_port_pause_limit, 3254 .port_set_cmode = mv88e6390x_port_set_cmode, 3255 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3256 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3257 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3258 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3259 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3260 .stats_get_strings = mv88e6320_stats_get_strings, 3261 .stats_get_stats = mv88e6390_stats_get_stats, 3262 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3263 .set_egress_port = mv88e6390_g1_set_egress_port, 3264 .watchdog_ops = &mv88e6390_watchdog_ops, 3265 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3266 .pot_clear = mv88e6xxx_g2_pot_clear, 3267 .reset = mv88e6352_g1_reset, 3268 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3269 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3270 .serdes_power = mv88e6390_serdes_power, 3271 .gpio_ops = &mv88e6352_gpio_ops, 3272 .avb_ops = &mv88e6390_avb_ops, 3273 }; 3274 3275 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3276 [MV88E6085] = { 3277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3278 .family = MV88E6XXX_FAMILY_6097, 3279 .name = "Marvell 88E6085", 3280 .num_databases = 4096, 3281 .num_ports = 10, 3282 .max_vid = 4095, 3283 .port_base_addr = 0x10, 3284 .global1_addr = 0x1b, 3285 .global2_addr = 0x1c, 3286 .age_time_coeff = 15000, 3287 .g1_irqs = 8, 3288 .g2_irqs = 10, 3289 .atu_move_port_mask = 0xf, 3290 .pvt = true, 3291 .multi_chip = true, 3292 .tag_protocol = DSA_TAG_PROTO_DSA, 3293 .ops = &mv88e6085_ops, 3294 }, 3295 3296 [MV88E6095] = { 3297 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3298 .family = MV88E6XXX_FAMILY_6095, 3299 .name = "Marvell 88E6095/88E6095F", 3300 .num_databases = 256, 3301 .num_ports = 11, 3302 .max_vid = 4095, 3303 .port_base_addr = 0x10, 3304 .global1_addr = 0x1b, 3305 .global2_addr = 0x1c, 3306 .age_time_coeff = 15000, 3307 .g1_irqs = 8, 3308 .atu_move_port_mask = 0xf, 3309 .multi_chip = true, 3310 .tag_protocol = DSA_TAG_PROTO_DSA, 3311 .ops = &mv88e6095_ops, 3312 }, 3313 3314 [MV88E6097] = { 3315 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3316 .family = MV88E6XXX_FAMILY_6097, 3317 .name = "Marvell 88E6097/88E6097F", 3318 .num_databases = 4096, 3319 .num_ports = 11, 3320 .max_vid = 4095, 3321 .port_base_addr = 0x10, 3322 .global1_addr = 0x1b, 3323 .global2_addr = 0x1c, 3324 .age_time_coeff = 15000, 3325 .g1_irqs = 8, 3326 .g2_irqs = 10, 3327 .atu_move_port_mask = 0xf, 3328 .pvt = true, 3329 .multi_chip = true, 3330 .tag_protocol = DSA_TAG_PROTO_EDSA, 3331 .ops = &mv88e6097_ops, 3332 }, 3333 3334 [MV88E6123] = { 3335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3336 .family = MV88E6XXX_FAMILY_6165, 3337 .name = "Marvell 88E6123", 3338 .num_databases = 4096, 3339 .num_ports = 3, 3340 .max_vid = 4095, 3341 .port_base_addr = 0x10, 3342 .global1_addr = 0x1b, 3343 .global2_addr = 0x1c, 3344 .age_time_coeff = 15000, 3345 .g1_irqs = 9, 3346 .g2_irqs = 10, 3347 .atu_move_port_mask = 0xf, 3348 .pvt = true, 3349 .multi_chip = true, 3350 .tag_protocol = DSA_TAG_PROTO_EDSA, 3351 .ops = &mv88e6123_ops, 3352 }, 3353 3354 [MV88E6131] = { 3355 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3356 .family = MV88E6XXX_FAMILY_6185, 3357 .name = "Marvell 88E6131", 3358 .num_databases = 256, 3359 .num_ports = 8, 3360 .max_vid = 4095, 3361 .port_base_addr = 0x10, 3362 .global1_addr = 0x1b, 3363 .global2_addr = 0x1c, 3364 .age_time_coeff = 15000, 3365 .g1_irqs = 9, 3366 .atu_move_port_mask = 0xf, 3367 .multi_chip = true, 3368 .tag_protocol = DSA_TAG_PROTO_DSA, 3369 .ops = &mv88e6131_ops, 3370 }, 3371 3372 [MV88E6141] = { 3373 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3374 .family = MV88E6XXX_FAMILY_6341, 3375 .name = "Marvell 88E6341", 3376 .num_databases = 4096, 3377 .num_ports = 6, 3378 .num_gpio = 11, 3379 .max_vid = 4095, 3380 .port_base_addr = 0x10, 3381 .global1_addr = 0x1b, 3382 .global2_addr = 0x1c, 3383 .age_time_coeff = 3750, 3384 .atu_move_port_mask = 0x1f, 3385 .g2_irqs = 10, 3386 .pvt = true, 3387 .multi_chip = true, 3388 .tag_protocol = DSA_TAG_PROTO_EDSA, 3389 .ops = &mv88e6141_ops, 3390 }, 3391 3392 [MV88E6161] = { 3393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3394 .family = MV88E6XXX_FAMILY_6165, 3395 .name = "Marvell 88E6161", 3396 .num_databases = 4096, 3397 .num_ports = 6, 3398 .max_vid = 4095, 3399 .port_base_addr = 0x10, 3400 .global1_addr = 0x1b, 3401 .global2_addr = 0x1c, 3402 .age_time_coeff = 15000, 3403 .g1_irqs = 9, 3404 .g2_irqs = 10, 3405 .atu_move_port_mask = 0xf, 3406 .pvt = true, 3407 .multi_chip = true, 3408 .tag_protocol = DSA_TAG_PROTO_EDSA, 3409 .ops = &mv88e6161_ops, 3410 }, 3411 3412 [MV88E6165] = { 3413 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3414 .family = MV88E6XXX_FAMILY_6165, 3415 .name = "Marvell 88E6165", 3416 .num_databases = 4096, 3417 .num_ports = 6, 3418 .max_vid = 4095, 3419 .port_base_addr = 0x10, 3420 .global1_addr = 0x1b, 3421 .global2_addr = 0x1c, 3422 .age_time_coeff = 15000, 3423 .g1_irqs = 9, 3424 .g2_irqs = 10, 3425 .atu_move_port_mask = 0xf, 3426 .pvt = true, 3427 .multi_chip = true, 3428 .tag_protocol = DSA_TAG_PROTO_DSA, 3429 .ops = &mv88e6165_ops, 3430 }, 3431 3432 [MV88E6171] = { 3433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3434 .family = MV88E6XXX_FAMILY_6351, 3435 .name = "Marvell 88E6171", 3436 .num_databases = 4096, 3437 .num_ports = 7, 3438 .max_vid = 4095, 3439 .port_base_addr = 0x10, 3440 .global1_addr = 0x1b, 3441 .global2_addr = 0x1c, 3442 .age_time_coeff = 15000, 3443 .g1_irqs = 9, 3444 .g2_irqs = 10, 3445 .atu_move_port_mask = 0xf, 3446 .pvt = true, 3447 .multi_chip = true, 3448 .tag_protocol = DSA_TAG_PROTO_EDSA, 3449 .ops = &mv88e6171_ops, 3450 }, 3451 3452 [MV88E6172] = { 3453 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3454 .family = MV88E6XXX_FAMILY_6352, 3455 .name = "Marvell 88E6172", 3456 .num_databases = 4096, 3457 .num_ports = 7, 3458 .num_gpio = 15, 3459 .max_vid = 4095, 3460 .port_base_addr = 0x10, 3461 .global1_addr = 0x1b, 3462 .global2_addr = 0x1c, 3463 .age_time_coeff = 15000, 3464 .g1_irqs = 9, 3465 .g2_irqs = 10, 3466 .atu_move_port_mask = 0xf, 3467 .pvt = true, 3468 .multi_chip = true, 3469 .tag_protocol = DSA_TAG_PROTO_EDSA, 3470 .ops = &mv88e6172_ops, 3471 }, 3472 3473 [MV88E6175] = { 3474 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3475 .family = MV88E6XXX_FAMILY_6351, 3476 .name = "Marvell 88E6175", 3477 .num_databases = 4096, 3478 .num_ports = 7, 3479 .max_vid = 4095, 3480 .port_base_addr = 0x10, 3481 .global1_addr = 0x1b, 3482 .global2_addr = 0x1c, 3483 .age_time_coeff = 15000, 3484 .g1_irqs = 9, 3485 .g2_irqs = 10, 3486 .atu_move_port_mask = 0xf, 3487 .pvt = true, 3488 .multi_chip = true, 3489 .tag_protocol = DSA_TAG_PROTO_EDSA, 3490 .ops = &mv88e6175_ops, 3491 }, 3492 3493 [MV88E6176] = { 3494 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3495 .family = MV88E6XXX_FAMILY_6352, 3496 .name = "Marvell 88E6176", 3497 .num_databases = 4096, 3498 .num_ports = 7, 3499 .num_gpio = 15, 3500 .max_vid = 4095, 3501 .port_base_addr = 0x10, 3502 .global1_addr = 0x1b, 3503 .global2_addr = 0x1c, 3504 .age_time_coeff = 15000, 3505 .g1_irqs = 9, 3506 .g2_irqs = 10, 3507 .atu_move_port_mask = 0xf, 3508 .pvt = true, 3509 .multi_chip = true, 3510 .tag_protocol = DSA_TAG_PROTO_EDSA, 3511 .ops = &mv88e6176_ops, 3512 }, 3513 3514 [MV88E6185] = { 3515 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3516 .family = MV88E6XXX_FAMILY_6185, 3517 .name = "Marvell 88E6185", 3518 .num_databases = 256, 3519 .num_ports = 10, 3520 .max_vid = 4095, 3521 .port_base_addr = 0x10, 3522 .global1_addr = 0x1b, 3523 .global2_addr = 0x1c, 3524 .age_time_coeff = 15000, 3525 .g1_irqs = 8, 3526 .atu_move_port_mask = 0xf, 3527 .multi_chip = true, 3528 .tag_protocol = DSA_TAG_PROTO_EDSA, 3529 .ops = &mv88e6185_ops, 3530 }, 3531 3532 [MV88E6190] = { 3533 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3534 .family = MV88E6XXX_FAMILY_6390, 3535 .name = "Marvell 88E6190", 3536 .num_databases = 4096, 3537 .num_ports = 11, /* 10 + Z80 */ 3538 .num_gpio = 16, 3539 .max_vid = 8191, 3540 .port_base_addr = 0x0, 3541 .global1_addr = 0x1b, 3542 .global2_addr = 0x1c, 3543 .tag_protocol = DSA_TAG_PROTO_DSA, 3544 .age_time_coeff = 3750, 3545 .g1_irqs = 9, 3546 .g2_irqs = 14, 3547 .pvt = true, 3548 .multi_chip = true, 3549 .atu_move_port_mask = 0x1f, 3550 .ops = &mv88e6190_ops, 3551 }, 3552 3553 [MV88E6190X] = { 3554 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3555 .family = MV88E6XXX_FAMILY_6390, 3556 .name = "Marvell 88E6190X", 3557 .num_databases = 4096, 3558 .num_ports = 11, /* 10 + Z80 */ 3559 .num_gpio = 16, 3560 .max_vid = 8191, 3561 .port_base_addr = 0x0, 3562 .global1_addr = 0x1b, 3563 .global2_addr = 0x1c, 3564 .age_time_coeff = 3750, 3565 .g1_irqs = 9, 3566 .g2_irqs = 14, 3567 .atu_move_port_mask = 0x1f, 3568 .pvt = true, 3569 .multi_chip = true, 3570 .tag_protocol = DSA_TAG_PROTO_DSA, 3571 .ops = &mv88e6190x_ops, 3572 }, 3573 3574 [MV88E6191] = { 3575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3576 .family = MV88E6XXX_FAMILY_6390, 3577 .name = "Marvell 88E6191", 3578 .num_databases = 4096, 3579 .num_ports = 11, /* 10 + Z80 */ 3580 .max_vid = 8191, 3581 .port_base_addr = 0x0, 3582 .global1_addr = 0x1b, 3583 .global2_addr = 0x1c, 3584 .age_time_coeff = 3750, 3585 .g1_irqs = 9, 3586 .g2_irqs = 14, 3587 .atu_move_port_mask = 0x1f, 3588 .pvt = true, 3589 .multi_chip = true, 3590 .tag_protocol = DSA_TAG_PROTO_DSA, 3591 .ptp_support = true, 3592 .ops = &mv88e6191_ops, 3593 }, 3594 3595 [MV88E6240] = { 3596 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3597 .family = MV88E6XXX_FAMILY_6352, 3598 .name = "Marvell 88E6240", 3599 .num_databases = 4096, 3600 .num_ports = 7, 3601 .num_gpio = 15, 3602 .max_vid = 4095, 3603 .port_base_addr = 0x10, 3604 .global1_addr = 0x1b, 3605 .global2_addr = 0x1c, 3606 .age_time_coeff = 15000, 3607 .g1_irqs = 9, 3608 .g2_irqs = 10, 3609 .atu_move_port_mask = 0xf, 3610 .pvt = true, 3611 .multi_chip = true, 3612 .tag_protocol = DSA_TAG_PROTO_EDSA, 3613 .ptp_support = true, 3614 .ops = &mv88e6240_ops, 3615 }, 3616 3617 [MV88E6290] = { 3618 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3619 .family = MV88E6XXX_FAMILY_6390, 3620 .name = "Marvell 88E6290", 3621 .num_databases = 4096, 3622 .num_ports = 11, /* 10 + Z80 */ 3623 .num_gpio = 16, 3624 .max_vid = 8191, 3625 .port_base_addr = 0x0, 3626 .global1_addr = 0x1b, 3627 .global2_addr = 0x1c, 3628 .age_time_coeff = 3750, 3629 .g1_irqs = 9, 3630 .g2_irqs = 14, 3631 .atu_move_port_mask = 0x1f, 3632 .pvt = true, 3633 .multi_chip = true, 3634 .tag_protocol = DSA_TAG_PROTO_DSA, 3635 .ptp_support = true, 3636 .ops = &mv88e6290_ops, 3637 }, 3638 3639 [MV88E6320] = { 3640 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3641 .family = MV88E6XXX_FAMILY_6320, 3642 .name = "Marvell 88E6320", 3643 .num_databases = 4096, 3644 .num_ports = 7, 3645 .num_gpio = 15, 3646 .max_vid = 4095, 3647 .port_base_addr = 0x10, 3648 .global1_addr = 0x1b, 3649 .global2_addr = 0x1c, 3650 .age_time_coeff = 15000, 3651 .g1_irqs = 8, 3652 .atu_move_port_mask = 0xf, 3653 .pvt = true, 3654 .multi_chip = true, 3655 .tag_protocol = DSA_TAG_PROTO_EDSA, 3656 .ptp_support = true, 3657 .ops = &mv88e6320_ops, 3658 }, 3659 3660 [MV88E6321] = { 3661 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3662 .family = MV88E6XXX_FAMILY_6320, 3663 .name = "Marvell 88E6321", 3664 .num_databases = 4096, 3665 .num_ports = 7, 3666 .num_gpio = 15, 3667 .max_vid = 4095, 3668 .port_base_addr = 0x10, 3669 .global1_addr = 0x1b, 3670 .global2_addr = 0x1c, 3671 .age_time_coeff = 15000, 3672 .g1_irqs = 8, 3673 .atu_move_port_mask = 0xf, 3674 .multi_chip = true, 3675 .tag_protocol = DSA_TAG_PROTO_EDSA, 3676 .ptp_support = true, 3677 .ops = &mv88e6321_ops, 3678 }, 3679 3680 [MV88E6341] = { 3681 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3682 .family = MV88E6XXX_FAMILY_6341, 3683 .name = "Marvell 88E6341", 3684 .num_databases = 4096, 3685 .num_ports = 6, 3686 .num_gpio = 11, 3687 .max_vid = 4095, 3688 .port_base_addr = 0x10, 3689 .global1_addr = 0x1b, 3690 .global2_addr = 0x1c, 3691 .age_time_coeff = 3750, 3692 .atu_move_port_mask = 0x1f, 3693 .g2_irqs = 10, 3694 .pvt = true, 3695 .multi_chip = true, 3696 .tag_protocol = DSA_TAG_PROTO_EDSA, 3697 .ptp_support = true, 3698 .ops = &mv88e6341_ops, 3699 }, 3700 3701 [MV88E6350] = { 3702 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3703 .family = MV88E6XXX_FAMILY_6351, 3704 .name = "Marvell 88E6350", 3705 .num_databases = 4096, 3706 .num_ports = 7, 3707 .max_vid = 4095, 3708 .port_base_addr = 0x10, 3709 .global1_addr = 0x1b, 3710 .global2_addr = 0x1c, 3711 .age_time_coeff = 15000, 3712 .g1_irqs = 9, 3713 .g2_irqs = 10, 3714 .atu_move_port_mask = 0xf, 3715 .pvt = true, 3716 .multi_chip = true, 3717 .tag_protocol = DSA_TAG_PROTO_EDSA, 3718 .ops = &mv88e6350_ops, 3719 }, 3720 3721 [MV88E6351] = { 3722 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3723 .family = MV88E6XXX_FAMILY_6351, 3724 .name = "Marvell 88E6351", 3725 .num_databases = 4096, 3726 .num_ports = 7, 3727 .max_vid = 4095, 3728 .port_base_addr = 0x10, 3729 .global1_addr = 0x1b, 3730 .global2_addr = 0x1c, 3731 .age_time_coeff = 15000, 3732 .g1_irqs = 9, 3733 .g2_irqs = 10, 3734 .atu_move_port_mask = 0xf, 3735 .pvt = true, 3736 .multi_chip = true, 3737 .tag_protocol = DSA_TAG_PROTO_EDSA, 3738 .ops = &mv88e6351_ops, 3739 }, 3740 3741 [MV88E6352] = { 3742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3743 .family = MV88E6XXX_FAMILY_6352, 3744 .name = "Marvell 88E6352", 3745 .num_databases = 4096, 3746 .num_ports = 7, 3747 .num_gpio = 15, 3748 .max_vid = 4095, 3749 .port_base_addr = 0x10, 3750 .global1_addr = 0x1b, 3751 .global2_addr = 0x1c, 3752 .age_time_coeff = 15000, 3753 .g1_irqs = 9, 3754 .g2_irqs = 10, 3755 .atu_move_port_mask = 0xf, 3756 .pvt = true, 3757 .multi_chip = true, 3758 .tag_protocol = DSA_TAG_PROTO_EDSA, 3759 .ptp_support = true, 3760 .ops = &mv88e6352_ops, 3761 }, 3762 [MV88E6390] = { 3763 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3764 .family = MV88E6XXX_FAMILY_6390, 3765 .name = "Marvell 88E6390", 3766 .num_databases = 4096, 3767 .num_ports = 11, /* 10 + Z80 */ 3768 .num_gpio = 16, 3769 .max_vid = 8191, 3770 .port_base_addr = 0x0, 3771 .global1_addr = 0x1b, 3772 .global2_addr = 0x1c, 3773 .age_time_coeff = 3750, 3774 .g1_irqs = 9, 3775 .g2_irqs = 14, 3776 .atu_move_port_mask = 0x1f, 3777 .pvt = true, 3778 .multi_chip = true, 3779 .tag_protocol = DSA_TAG_PROTO_DSA, 3780 .ptp_support = true, 3781 .ops = &mv88e6390_ops, 3782 }, 3783 [MV88E6390X] = { 3784 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3785 .family = MV88E6XXX_FAMILY_6390, 3786 .name = "Marvell 88E6390X", 3787 .num_databases = 4096, 3788 .num_ports = 11, /* 10 + Z80 */ 3789 .num_gpio = 16, 3790 .max_vid = 8191, 3791 .port_base_addr = 0x0, 3792 .global1_addr = 0x1b, 3793 .global2_addr = 0x1c, 3794 .age_time_coeff = 3750, 3795 .g1_irqs = 9, 3796 .g2_irqs = 14, 3797 .atu_move_port_mask = 0x1f, 3798 .pvt = true, 3799 .multi_chip = true, 3800 .tag_protocol = DSA_TAG_PROTO_DSA, 3801 .ptp_support = true, 3802 .ops = &mv88e6390x_ops, 3803 }, 3804 }; 3805 3806 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3807 { 3808 int i; 3809 3810 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3811 if (mv88e6xxx_table[i].prod_num == prod_num) 3812 return &mv88e6xxx_table[i]; 3813 3814 return NULL; 3815 } 3816 3817 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3818 { 3819 const struct mv88e6xxx_info *info; 3820 unsigned int prod_num, rev; 3821 u16 id; 3822 int err; 3823 3824 mutex_lock(&chip->reg_lock); 3825 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3826 mutex_unlock(&chip->reg_lock); 3827 if (err) 3828 return err; 3829 3830 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3831 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3832 3833 info = mv88e6xxx_lookup_info(prod_num); 3834 if (!info) 3835 return -ENODEV; 3836 3837 /* Update the compatible info with the probed one */ 3838 chip->info = info; 3839 3840 err = mv88e6xxx_g2_require(chip); 3841 if (err) 3842 return err; 3843 3844 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3845 chip->info->prod_num, chip->info->name, rev); 3846 3847 return 0; 3848 } 3849 3850 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3851 { 3852 struct mv88e6xxx_chip *chip; 3853 3854 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3855 if (!chip) 3856 return NULL; 3857 3858 chip->dev = dev; 3859 3860 mutex_init(&chip->reg_lock); 3861 INIT_LIST_HEAD(&chip->mdios); 3862 3863 return chip; 3864 } 3865 3866 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3867 struct mii_bus *bus, int sw_addr) 3868 { 3869 if (sw_addr == 0) 3870 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3871 else if (chip->info->multi_chip) 3872 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3873 else 3874 return -EINVAL; 3875 3876 chip->bus = bus; 3877 chip->sw_addr = sw_addr; 3878 3879 return 0; 3880 } 3881 3882 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 3883 int port) 3884 { 3885 struct mv88e6xxx_chip *chip = ds->priv; 3886 3887 return chip->info->tag_protocol; 3888 } 3889 3890 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 3891 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3892 struct device *host_dev, int sw_addr, 3893 void **priv) 3894 { 3895 struct mv88e6xxx_chip *chip; 3896 struct mii_bus *bus; 3897 int err; 3898 3899 bus = dsa_host_dev_to_mii_bus(host_dev); 3900 if (!bus) 3901 return NULL; 3902 3903 chip = mv88e6xxx_alloc_chip(dsa_dev); 3904 if (!chip) 3905 return NULL; 3906 3907 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3908 chip->info = &mv88e6xxx_table[MV88E6085]; 3909 3910 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3911 if (err) 3912 goto free; 3913 3914 err = mv88e6xxx_detect(chip); 3915 if (err) 3916 goto free; 3917 3918 mutex_lock(&chip->reg_lock); 3919 err = mv88e6xxx_switch_reset(chip); 3920 mutex_unlock(&chip->reg_lock); 3921 if (err) 3922 goto free; 3923 3924 mv88e6xxx_phy_init(chip); 3925 3926 err = mv88e6xxx_mdios_register(chip, NULL); 3927 if (err) 3928 goto free; 3929 3930 *priv = chip; 3931 3932 return chip->info->name; 3933 free: 3934 devm_kfree(dsa_dev, chip); 3935 3936 return NULL; 3937 } 3938 #endif 3939 3940 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3941 const struct switchdev_obj_port_mdb *mdb) 3942 { 3943 /* We don't need any dynamic resource from the kernel (yet), 3944 * so skip the prepare phase. 3945 */ 3946 3947 return 0; 3948 } 3949 3950 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3951 const struct switchdev_obj_port_mdb *mdb) 3952 { 3953 struct mv88e6xxx_chip *chip = ds->priv; 3954 3955 mutex_lock(&chip->reg_lock); 3956 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3957 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3958 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3959 port); 3960 mutex_unlock(&chip->reg_lock); 3961 } 3962 3963 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3964 const struct switchdev_obj_port_mdb *mdb) 3965 { 3966 struct mv88e6xxx_chip *chip = ds->priv; 3967 int err; 3968 3969 mutex_lock(&chip->reg_lock); 3970 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3971 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3972 mutex_unlock(&chip->reg_lock); 3973 3974 return err; 3975 } 3976 3977 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3978 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 3979 .probe = mv88e6xxx_drv_probe, 3980 #endif 3981 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3982 .setup = mv88e6xxx_setup, 3983 .adjust_link = mv88e6xxx_adjust_link, 3984 .get_strings = mv88e6xxx_get_strings, 3985 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3986 .get_sset_count = mv88e6xxx_get_sset_count, 3987 .port_enable = mv88e6xxx_port_enable, 3988 .port_disable = mv88e6xxx_port_disable, 3989 .get_mac_eee = mv88e6xxx_get_mac_eee, 3990 .set_mac_eee = mv88e6xxx_set_mac_eee, 3991 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3992 .get_eeprom = mv88e6xxx_get_eeprom, 3993 .set_eeprom = mv88e6xxx_set_eeprom, 3994 .get_regs_len = mv88e6xxx_get_regs_len, 3995 .get_regs = mv88e6xxx_get_regs, 3996 .set_ageing_time = mv88e6xxx_set_ageing_time, 3997 .port_bridge_join = mv88e6xxx_port_bridge_join, 3998 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3999 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4000 .port_fast_age = mv88e6xxx_port_fast_age, 4001 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4002 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4003 .port_vlan_add = mv88e6xxx_port_vlan_add, 4004 .port_vlan_del = mv88e6xxx_port_vlan_del, 4005 .port_fdb_add = mv88e6xxx_port_fdb_add, 4006 .port_fdb_del = mv88e6xxx_port_fdb_del, 4007 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4008 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4009 .port_mdb_add = mv88e6xxx_port_mdb_add, 4010 .port_mdb_del = mv88e6xxx_port_mdb_del, 4011 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4012 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4013 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4014 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4015 .port_txtstamp = mv88e6xxx_port_txtstamp, 4016 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4017 .get_ts_info = mv88e6xxx_get_ts_info, 4018 }; 4019 4020 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4021 .ops = &mv88e6xxx_switch_ops, 4022 }; 4023 4024 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4025 { 4026 struct device *dev = chip->dev; 4027 struct dsa_switch *ds; 4028 4029 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4030 if (!ds) 4031 return -ENOMEM; 4032 4033 ds->priv = chip; 4034 ds->ops = &mv88e6xxx_switch_ops; 4035 ds->ageing_time_min = chip->info->age_time_coeff; 4036 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4037 4038 dev_set_drvdata(dev, ds); 4039 4040 return dsa_register_switch(ds); 4041 } 4042 4043 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4044 { 4045 dsa_unregister_switch(chip->ds); 4046 } 4047 4048 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4049 { 4050 struct device *dev = &mdiodev->dev; 4051 struct device_node *np = dev->of_node; 4052 const struct mv88e6xxx_info *compat_info; 4053 struct mv88e6xxx_chip *chip; 4054 u32 eeprom_len; 4055 int err; 4056 4057 compat_info = of_device_get_match_data(dev); 4058 if (!compat_info) 4059 return -EINVAL; 4060 4061 chip = mv88e6xxx_alloc_chip(dev); 4062 if (!chip) 4063 return -ENOMEM; 4064 4065 chip->info = compat_info; 4066 4067 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4068 if (err) 4069 return err; 4070 4071 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4072 if (IS_ERR(chip->reset)) 4073 return PTR_ERR(chip->reset); 4074 4075 err = mv88e6xxx_detect(chip); 4076 if (err) 4077 return err; 4078 4079 mv88e6xxx_phy_init(chip); 4080 4081 if (chip->info->ops->get_eeprom && 4082 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4083 chip->eeprom_len = eeprom_len; 4084 4085 mutex_lock(&chip->reg_lock); 4086 err = mv88e6xxx_switch_reset(chip); 4087 mutex_unlock(&chip->reg_lock); 4088 if (err) 4089 goto out; 4090 4091 chip->irq = of_irq_get(np, 0); 4092 if (chip->irq == -EPROBE_DEFER) { 4093 err = chip->irq; 4094 goto out; 4095 } 4096 4097 /* Has to be performed before the MDIO bus is created, because 4098 * the PHYs will link there interrupts to these interrupt 4099 * controllers 4100 */ 4101 mutex_lock(&chip->reg_lock); 4102 if (chip->irq > 0) 4103 err = mv88e6xxx_g1_irq_setup(chip); 4104 else 4105 err = mv88e6xxx_irq_poll_setup(chip); 4106 mutex_unlock(&chip->reg_lock); 4107 4108 if (err) 4109 goto out; 4110 4111 if (chip->info->g2_irqs > 0) { 4112 err = mv88e6xxx_g2_irq_setup(chip); 4113 if (err) 4114 goto out_g1_irq; 4115 } 4116 4117 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4118 if (err) 4119 goto out_g2_irq; 4120 4121 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4122 if (err) 4123 goto out_g1_atu_prob_irq; 4124 4125 err = mv88e6xxx_mdios_register(chip, np); 4126 if (err) 4127 goto out_g1_vtu_prob_irq; 4128 4129 err = mv88e6xxx_register_switch(chip); 4130 if (err) 4131 goto out_mdio; 4132 4133 return 0; 4134 4135 out_mdio: 4136 mv88e6xxx_mdios_unregister(chip); 4137 out_g1_vtu_prob_irq: 4138 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4139 out_g1_atu_prob_irq: 4140 mv88e6xxx_g1_atu_prob_irq_free(chip); 4141 out_g2_irq: 4142 if (chip->info->g2_irqs > 0) 4143 mv88e6xxx_g2_irq_free(chip); 4144 out_g1_irq: 4145 mutex_lock(&chip->reg_lock); 4146 if (chip->irq > 0) 4147 mv88e6xxx_g1_irq_free(chip); 4148 else 4149 mv88e6xxx_irq_poll_free(chip); 4150 mutex_unlock(&chip->reg_lock); 4151 out: 4152 return err; 4153 } 4154 4155 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4156 { 4157 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4158 struct mv88e6xxx_chip *chip = ds->priv; 4159 4160 if (chip->info->ptp_support) { 4161 mv88e6xxx_hwtstamp_free(chip); 4162 mv88e6xxx_ptp_free(chip); 4163 } 4164 4165 mv88e6xxx_phy_destroy(chip); 4166 mv88e6xxx_unregister_switch(chip); 4167 mv88e6xxx_mdios_unregister(chip); 4168 4169 if (chip->irq > 0) { 4170 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4171 mv88e6xxx_g1_atu_prob_irq_free(chip); 4172 if (chip->info->g2_irqs > 0) 4173 mv88e6xxx_g2_irq_free(chip); 4174 mutex_lock(&chip->reg_lock); 4175 mv88e6xxx_g1_irq_free(chip); 4176 mutex_unlock(&chip->reg_lock); 4177 } 4178 } 4179 4180 static const struct of_device_id mv88e6xxx_of_match[] = { 4181 { 4182 .compatible = "marvell,mv88e6085", 4183 .data = &mv88e6xxx_table[MV88E6085], 4184 }, 4185 { 4186 .compatible = "marvell,mv88e6190", 4187 .data = &mv88e6xxx_table[MV88E6190], 4188 }, 4189 { /* sentinel */ }, 4190 }; 4191 4192 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4193 4194 static struct mdio_driver mv88e6xxx_driver = { 4195 .probe = mv88e6xxx_probe, 4196 .remove = mv88e6xxx_remove, 4197 .mdiodrv.driver = { 4198 .name = "mv88e6085", 4199 .of_match_table = mv88e6xxx_of_match, 4200 }, 4201 }; 4202 4203 static int __init mv88e6xxx_init(void) 4204 { 4205 register_switch_driver(&mv88e6xxx_switch_drv); 4206 return mdio_driver_register(&mv88e6xxx_driver); 4207 } 4208 module_init(mv88e6xxx_init); 4209 4210 static void __exit mv88e6xxx_cleanup(void) 4211 { 4212 mdio_driver_unregister(&mv88e6xxx_driver); 4213 unregister_switch_driver(&mv88e6xxx_switch_drv); 4214 } 4215 module_exit(mv88e6xxx_cleanup); 4216 4217 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4218 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4219 MODULE_LICENSE("GPL"); 4220