1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_add_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t **data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i; 1161 1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) 1165 ethtool_puts(data, stat->string); 1166 } 1167 } 1168 1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t **data) 1171 { 1172 mv88e6xxx_stats_get_strings(chip, data, 1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1174 } 1175 1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1177 uint8_t **data) 1178 { 1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1180 } 1181 1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1183 uint8_t **data) 1184 { 1185 mv88e6xxx_stats_get_strings(chip, data, 1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1187 } 1188 1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1190 "atu_member_violation", 1191 "atu_miss_violation", 1192 "atu_full_violation", 1193 "vtu_member_violation", 1194 "vtu_miss_violation", 1195 }; 1196 1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1203 } 1204 1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1206 u32 stringset, uint8_t *data) 1207 { 1208 struct mv88e6xxx_chip *chip = ds->priv; 1209 1210 if (stringset != ETH_SS_STATS) 1211 return; 1212 1213 mv88e6xxx_reg_lock(chip); 1214 1215 if (chip->info->ops->stats_get_strings) 1216 chip->info->ops->stats_get_strings(chip, &data); 1217 1218 if (chip->info->ops->serdes_get_strings) 1219 chip->info->ops->serdes_get_strings(chip, port, &data); 1220 1221 mv88e6xxx_atu_vtu_get_strings(&data); 1222 1223 mv88e6xxx_reg_unlock(chip); 1224 } 1225 1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1227 int types) 1228 { 1229 const struct mv88e6xxx_hw_stat *stat; 1230 int i, j; 1231 1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1233 stat = &mv88e6xxx_hw_stats[i]; 1234 if (stat->type & types) 1235 j++; 1236 } 1237 return j; 1238 } 1239 1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1241 { 1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1243 STATS_TYPE_PORT); 1244 } 1245 1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1247 { 1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1249 } 1250 1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_BANK1); 1255 } 1256 1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1258 { 1259 struct mv88e6xxx_chip *chip = ds->priv; 1260 int serdes_count = 0; 1261 int count = 0; 1262 1263 if (sset != ETH_SS_STATS) 1264 return 0; 1265 1266 mv88e6xxx_reg_lock(chip); 1267 if (chip->info->ops->stats_get_sset_count) 1268 count = chip->info->ops->stats_get_sset_count(chip); 1269 if (count < 0) 1270 goto out; 1271 1272 if (chip->info->ops->serdes_get_sset_count) 1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1274 port); 1275 if (serdes_count < 0) { 1276 count = serdes_count; 1277 goto out; 1278 } 1279 count += serdes_count; 1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1281 1282 out: 1283 mv88e6xxx_reg_unlock(chip); 1284 1285 return count; 1286 } 1287 1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1289 const struct mv88e6xxx_hw_stat *stat, 1290 uint64_t *data) 1291 { 1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1293 MV88E6XXX_G1_STATS_OP_HIST_RX); 1294 return 1; 1295 } 1296 1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1298 const struct mv88e6xxx_hw_stat *stat, 1299 uint64_t *data) 1300 { 1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1302 MV88E6XXX_G1_STATS_OP_HIST_RX); 1303 return 1; 1304 } 1305 1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1307 const struct mv88e6xxx_hw_stat *stat, 1308 uint64_t *data) 1309 { 1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1312 MV88E6XXX_G1_STATS_OP_HIST_RX); 1313 return 1; 1314 } 1315 1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1317 const struct mv88e6xxx_hw_stat *stat, 1318 uint64_t *data) 1319 { 1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1322 0); 1323 return 1; 1324 } 1325 1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1327 const struct mv88e6xxx_hw_stat *stat, 1328 uint64_t *data) 1329 { 1330 int ret = 0; 1331 1332 if (!(stat->type & chip->info->stats_type)) 1333 return 0; 1334 1335 if (chip->info->ops->stats_get_stat) { 1336 mv88e6xxx_reg_lock(chip); 1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 return ret; 1342 } 1343 1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1345 uint64_t *data) 1346 { 1347 const struct mv88e6xxx_hw_stat *stat; 1348 size_t i, j; 1349 1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1351 stat = &mv88e6xxx_hw_stats[i]; 1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1353 } 1354 return j; 1355 } 1356 1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1358 uint64_t *data) 1359 { 1360 *data++ = chip->ports[port].atu_member_violation; 1361 *data++ = chip->ports[port].atu_miss_violation; 1362 *data++ = chip->ports[port].atu_full_violation; 1363 *data++ = chip->ports[port].vtu_member_violation; 1364 *data++ = chip->ports[port].vtu_miss_violation; 1365 } 1366 1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1368 uint64_t *data) 1369 { 1370 size_t count; 1371 1372 count = mv88e6xxx_stats_get_stats(chip, port, data); 1373 1374 mv88e6xxx_reg_lock(chip); 1375 if (chip->info->ops->serdes_get_stats) { 1376 data += count; 1377 count = chip->info->ops->serdes_get_stats(chip, port, data); 1378 } 1379 data += count; 1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1381 mv88e6xxx_reg_unlock(chip); 1382 } 1383 1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1385 uint64_t *data) 1386 { 1387 struct mv88e6xxx_chip *chip = ds->priv; 1388 int ret; 1389 1390 ret = mv88e6xxx_stats_snapshot(chip, port); 1391 if (ret < 0) 1392 return; 1393 1394 mv88e6xxx_get_stats(chip, port, data); 1395 } 1396 1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1398 struct ethtool_eth_mac_stats *mac_stats) 1399 { 1400 struct mv88e6xxx_chip *chip = ds->priv; 1401 int ret; 1402 1403 ret = mv88e6xxx_stats_snapshot(chip, port); 1404 if (ret < 0) 1405 return; 1406 1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1408 mv88e6xxx_stats_get_stat(chip, port, \ 1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1410 &mac_stats->stats._member) 1411 1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1426 1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1428 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1433 } 1434 1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1436 struct ethtool_rmon_stats *rmon_stats, 1437 const struct ethtool_rmon_hist_range **ranges) 1438 { 1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1440 { 64, 64 }, 1441 { 65, 127 }, 1442 { 128, 255 }, 1443 { 256, 511 }, 1444 { 512, 1023 }, 1445 { 1024, 65535 }, 1446 {} 1447 }; 1448 struct mv88e6xxx_chip *chip = ds->priv; 1449 int ret; 1450 1451 ret = mv88e6xxx_stats_snapshot(chip, port); 1452 if (ret < 0) 1453 return; 1454 1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1456 mv88e6xxx_stats_get_stat(chip, port, \ 1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1458 &rmon_stats->stats._member) 1459 1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1470 1471 #undef MV88E6XXX_RMON_STAT_MAP 1472 1473 *ranges = rmon_ranges; 1474 } 1475 1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int len; 1480 1481 len = 32 * sizeof(u16); 1482 if (chip->info->ops->serdes_get_regs_len) 1483 len += chip->info->ops->serdes_get_regs_len(chip, port); 1484 1485 return len; 1486 } 1487 1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1489 struct ethtool_regs *regs, void *_p) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 int err; 1493 u16 reg; 1494 u16 *p = _p; 1495 int i; 1496 1497 regs->version = chip->info->prod_num; 1498 1499 memset(p, 0xff, 32 * sizeof(u16)); 1500 1501 mv88e6xxx_reg_lock(chip); 1502 1503 for (i = 0; i < 32; i++) { 1504 1505 err = mv88e6xxx_port_read(chip, port, i, ®); 1506 if (!err) 1507 p[i] = reg; 1508 } 1509 1510 if (chip->info->ops->serdes_get_regs) 1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1512 1513 mv88e6xxx_reg_unlock(chip); 1514 } 1515 1516 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1517 struct ethtool_keee *e) 1518 { 1519 /* Nothing to do on the port's MAC */ 1520 return 0; 1521 } 1522 1523 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1525 { 1526 struct dsa_switch *ds = chip->ds; 1527 struct dsa_switch_tree *dst = ds->dst; 1528 struct dsa_port *dp, *other_dp; 1529 bool found = false; 1530 u16 pvlan; 1531 1532 /* dev is a physical switch */ 1533 if (dev <= dst->last_switch) { 1534 list_for_each_entry(dp, &dst->ports, list) { 1535 if (dp->ds->index == dev && dp->index == port) { 1536 /* dp might be a DSA link or a user port, so it 1537 * might or might not have a bridge. 1538 * Use the "found" variable for both cases. 1539 */ 1540 found = true; 1541 break; 1542 } 1543 } 1544 /* dev is a virtual bridge */ 1545 } else { 1546 list_for_each_entry(dp, &dst->ports, list) { 1547 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1548 1549 if (!bridge_num) 1550 continue; 1551 1552 if (bridge_num + dst->last_switch != dev) 1553 continue; 1554 1555 found = true; 1556 break; 1557 } 1558 } 1559 1560 /* Prevent frames from unknown switch or virtual bridge */ 1561 if (!found) 1562 return 0; 1563 1564 /* Frames from DSA links and CPU ports can egress any local port */ 1565 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1566 return mv88e6xxx_port_mask(chip); 1567 1568 pvlan = 0; 1569 1570 /* Frames from standalone user ports can only egress on the 1571 * upstream port. 1572 */ 1573 if (!dsa_port_bridge_dev_get(dp)) 1574 return BIT(dsa_switch_upstream_port(ds)); 1575 1576 /* Frames from bridged user ports can egress any local DSA 1577 * links and CPU ports, as well as any local member of their 1578 * bridge group. 1579 */ 1580 dsa_switch_for_each_port(other_dp, ds) 1581 if (other_dp->type == DSA_PORT_TYPE_CPU || 1582 other_dp->type == DSA_PORT_TYPE_DSA || 1583 dsa_port_bridge_same(dp, other_dp)) 1584 pvlan |= BIT(other_dp->index); 1585 1586 return pvlan; 1587 } 1588 1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1590 { 1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1592 1593 /* prevent frames from going back out of the port they came in on */ 1594 output_ports &= ~BIT(port); 1595 1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1597 } 1598 1599 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1600 u8 state) 1601 { 1602 struct mv88e6xxx_chip *chip = ds->priv; 1603 int err; 1604 1605 mv88e6xxx_reg_lock(chip); 1606 err = mv88e6xxx_port_set_state(chip, port, state); 1607 mv88e6xxx_reg_unlock(chip); 1608 1609 if (err) 1610 dev_err(ds->dev, "p%d: failed to update state\n", port); 1611 } 1612 1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1614 { 1615 int err; 1616 1617 if (chip->info->ops->ieee_pri_map) { 1618 err = chip->info->ops->ieee_pri_map(chip); 1619 if (err) 1620 return err; 1621 } 1622 1623 if (chip->info->ops->ip_pri_map) { 1624 err = chip->info->ops->ip_pri_map(chip); 1625 if (err) 1626 return err; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1633 { 1634 struct dsa_switch *ds = chip->ds; 1635 int target, port; 1636 int err; 1637 1638 if (!chip->info->global2_addr) 1639 return 0; 1640 1641 /* Initialize the routing port to the 32 possible target devices */ 1642 for (target = 0; target < 32; target++) { 1643 port = dsa_routing_port(ds, target); 1644 if (port == ds->num_ports) 1645 port = 0x1f; 1646 1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1648 if (err) 1649 return err; 1650 } 1651 1652 if (chip->info->ops->set_cascade_port) { 1653 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1654 err = chip->info->ops->set_cascade_port(chip, port); 1655 if (err) 1656 return err; 1657 } 1658 1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1660 if (err) 1661 return err; 1662 1663 return 0; 1664 } 1665 1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1667 { 1668 /* Clear all trunk masks and mapping */ 1669 if (chip->info->global2_addr) 1670 return mv88e6xxx_g2_trunk_clear(chip); 1671 1672 return 0; 1673 } 1674 1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1676 { 1677 if (chip->info->ops->rmu_disable) 1678 return chip->info->ops->rmu_disable(chip); 1679 1680 return 0; 1681 } 1682 1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1684 { 1685 if (chip->info->ops->pot_clear) 1686 return chip->info->ops->pot_clear(chip); 1687 1688 return 0; 1689 } 1690 1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1692 { 1693 if (chip->info->ops->mgmt_rsvd2cpu) 1694 return chip->info->ops->mgmt_rsvd2cpu(chip); 1695 1696 return 0; 1697 } 1698 1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1700 { 1701 int err; 1702 1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1704 if (err) 1705 return err; 1706 1707 /* The chips that have a "learn2all" bit in Global1, ATU 1708 * Control are precisely those whose port registers have a 1709 * Message Port bit in Port Control 1 and hence implement 1710 * ->port_setup_message_port. 1711 */ 1712 if (chip->info->ops->port_setup_message_port) { 1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1714 if (err) 1715 return err; 1716 } 1717 1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1719 } 1720 1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1722 { 1723 int port; 1724 int err; 1725 1726 if (!chip->info->ops->irl_init_all) 1727 return 0; 1728 1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1730 /* Disable ingress rate limiting by resetting all per port 1731 * ingress rate limit resources to their initial state. 1732 */ 1733 err = chip->info->ops->irl_init_all(chip, port); 1734 if (err) 1735 return err; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1742 { 1743 if (chip->info->ops->set_switch_mac) { 1744 u8 addr[ETH_ALEN]; 1745 1746 eth_random_addr(addr); 1747 1748 return chip->info->ops->set_switch_mac(chip, addr); 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1755 { 1756 struct dsa_switch_tree *dst = chip->ds->dst; 1757 struct dsa_switch *ds; 1758 struct dsa_port *dp; 1759 u16 pvlan = 0; 1760 1761 if (!mv88e6xxx_has_pvt(chip)) 1762 return 0; 1763 1764 /* Skip the local source device, which uses in-chip port VLAN */ 1765 if (dev != chip->ds->index) { 1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1767 1768 ds = dsa_switch_find(dst->index, dev); 1769 dp = ds ? dsa_to_port(ds, port) : NULL; 1770 if (dp && dp->lag) { 1771 /* As the PVT is used to limit flooding of 1772 * FORWARD frames, which use the LAG ID as the 1773 * source port, we must translate dev/port to 1774 * the special "LAG device" in the PVT, using 1775 * the LAG ID (one-based) as the port number 1776 * (zero-based). 1777 */ 1778 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1779 port = dsa_port_lag_id_get(dp) - 1; 1780 } 1781 } 1782 1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1784 } 1785 1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1787 { 1788 int dev, port; 1789 int err; 1790 1791 if (!mv88e6xxx_has_pvt(chip)) 1792 return 0; 1793 1794 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1795 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1796 */ 1797 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1798 if (err) 1799 return err; 1800 1801 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1802 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1803 err = mv88e6xxx_pvt_map(chip, dev, port); 1804 if (err) 1805 return err; 1806 } 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1813 u16 fid) 1814 { 1815 if (dsa_to_port(chip->ds, port)->lag) 1816 /* Hardware is incapable of fast-aging a LAG through a 1817 * regular ATU move operation. Until we have something 1818 * more fancy in place this is a no-op. 1819 */ 1820 return -EOPNOTSUPP; 1821 1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1823 } 1824 1825 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1826 { 1827 struct mv88e6xxx_chip *chip = ds->priv; 1828 int err; 1829 1830 mv88e6xxx_reg_lock(chip); 1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1832 mv88e6xxx_reg_unlock(chip); 1833 1834 if (err) 1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1836 port, err); 1837 } 1838 1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1840 { 1841 if (!mv88e6xxx_max_vid(chip)) 1842 return 0; 1843 1844 return mv88e6xxx_g1_vtu_flush(chip); 1845 } 1846 1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1848 struct mv88e6xxx_vtu_entry *entry) 1849 { 1850 int err; 1851 1852 if (!chip->info->ops->vtu_getnext) 1853 return -EOPNOTSUPP; 1854 1855 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1856 entry->valid = false; 1857 1858 err = chip->info->ops->vtu_getnext(chip, entry); 1859 1860 if (entry->vid != vid) 1861 entry->valid = false; 1862 1863 return err; 1864 } 1865 1866 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1867 int (*cb)(struct mv88e6xxx_chip *chip, 1868 const struct mv88e6xxx_vtu_entry *entry, 1869 void *priv), 1870 void *priv) 1871 { 1872 struct mv88e6xxx_vtu_entry entry = { 1873 .vid = mv88e6xxx_max_vid(chip), 1874 .valid = false, 1875 }; 1876 int err; 1877 1878 if (!chip->info->ops->vtu_getnext) 1879 return -EOPNOTSUPP; 1880 1881 do { 1882 err = chip->info->ops->vtu_getnext(chip, &entry); 1883 if (err) 1884 return err; 1885 1886 if (!entry.valid) 1887 break; 1888 1889 err = cb(chip, &entry, priv); 1890 if (err) 1891 return err; 1892 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1893 1894 return 0; 1895 } 1896 1897 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1898 struct mv88e6xxx_vtu_entry *entry) 1899 { 1900 if (!chip->info->ops->vtu_loadpurge) 1901 return -EOPNOTSUPP; 1902 1903 return chip->info->ops->vtu_loadpurge(chip, entry); 1904 } 1905 1906 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1907 { 1908 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1909 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1910 return -ENOSPC; 1911 1912 /* Clear the database */ 1913 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1914 } 1915 1916 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1917 struct mv88e6xxx_stu_entry *entry) 1918 { 1919 if (!chip->info->ops->stu_loadpurge) 1920 return -EOPNOTSUPP; 1921 1922 return chip->info->ops->stu_loadpurge(chip, entry); 1923 } 1924 1925 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1926 { 1927 struct mv88e6xxx_stu_entry stu = { 1928 .valid = true, 1929 .sid = 0 1930 }; 1931 1932 if (!mv88e6xxx_has_stu(chip)) 1933 return 0; 1934 1935 /* Make sure that SID 0 is always valid. This is used by VTU 1936 * entries that do not make use of the STU, e.g. when creating 1937 * a VLAN upper on a port that is also part of a VLAN 1938 * filtering bridge. 1939 */ 1940 return mv88e6xxx_stu_loadpurge(chip, &stu); 1941 } 1942 1943 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1944 { 1945 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1946 struct mv88e6xxx_mst *mst; 1947 1948 __set_bit(0, busy); 1949 1950 list_for_each_entry(mst, &chip->msts, node) 1951 __set_bit(mst->stu.sid, busy); 1952 1953 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1954 1955 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1956 } 1957 1958 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1959 { 1960 struct mv88e6xxx_mst *mst, *tmp; 1961 int err; 1962 1963 if (!sid) 1964 return 0; 1965 1966 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1967 if (mst->stu.sid != sid) 1968 continue; 1969 1970 if (!refcount_dec_and_test(&mst->refcnt)) 1971 return 0; 1972 1973 mst->stu.valid = false; 1974 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1975 if (err) { 1976 refcount_set(&mst->refcnt, 1); 1977 return err; 1978 } 1979 1980 list_del(&mst->node); 1981 kfree(mst); 1982 return 0; 1983 } 1984 1985 return -ENOENT; 1986 } 1987 1988 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1989 u16 msti, u8 *sid) 1990 { 1991 struct mv88e6xxx_mst *mst; 1992 int err, i; 1993 1994 if (!mv88e6xxx_has_stu(chip)) { 1995 err = -EOPNOTSUPP; 1996 goto err; 1997 } 1998 1999 if (!msti) { 2000 *sid = 0; 2001 return 0; 2002 } 2003 2004 list_for_each_entry(mst, &chip->msts, node) { 2005 if (mst->br == br && mst->msti == msti) { 2006 refcount_inc(&mst->refcnt); 2007 *sid = mst->stu.sid; 2008 return 0; 2009 } 2010 } 2011 2012 err = mv88e6xxx_sid_get(chip, sid); 2013 if (err) 2014 goto err; 2015 2016 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2017 if (!mst) { 2018 err = -ENOMEM; 2019 goto err; 2020 } 2021 2022 INIT_LIST_HEAD(&mst->node); 2023 refcount_set(&mst->refcnt, 1); 2024 mst->br = br; 2025 mst->msti = msti; 2026 mst->stu.valid = true; 2027 mst->stu.sid = *sid; 2028 2029 /* The bridge starts out all ports in the disabled state. But 2030 * a STU state of disabled means to go by the port-global 2031 * state. So we set all user port's initial state to blocking, 2032 * to match the bridge's behavior. 2033 */ 2034 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2035 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2036 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2037 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2038 2039 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2040 if (err) 2041 goto err_free; 2042 2043 list_add_tail(&mst->node, &chip->msts); 2044 return 0; 2045 2046 err_free: 2047 kfree(mst); 2048 err: 2049 return err; 2050 } 2051 2052 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2053 const struct switchdev_mst_state *st) 2054 { 2055 struct dsa_port *dp = dsa_to_port(ds, port); 2056 struct mv88e6xxx_chip *chip = ds->priv; 2057 struct mv88e6xxx_mst *mst; 2058 u8 state; 2059 int err; 2060 2061 if (!mv88e6xxx_has_stu(chip)) 2062 return -EOPNOTSUPP; 2063 2064 switch (st->state) { 2065 case BR_STATE_DISABLED: 2066 case BR_STATE_BLOCKING: 2067 case BR_STATE_LISTENING: 2068 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2069 break; 2070 case BR_STATE_LEARNING: 2071 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2072 break; 2073 case BR_STATE_FORWARDING: 2074 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2075 break; 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 list_for_each_entry(mst, &chip->msts, node) { 2081 if (mst->br == dsa_port_bridge_dev_get(dp) && 2082 mst->msti == st->msti) { 2083 if (mst->stu.state[port] == state) 2084 return 0; 2085 2086 mst->stu.state[port] = state; 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2089 mv88e6xxx_reg_unlock(chip); 2090 return err; 2091 } 2092 } 2093 2094 return -ENOENT; 2095 } 2096 2097 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2098 u16 vid) 2099 { 2100 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2101 struct mv88e6xxx_chip *chip = ds->priv; 2102 struct mv88e6xxx_vtu_entry vlan; 2103 int err; 2104 2105 /* DSA and CPU ports have to be members of multiple vlans */ 2106 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2107 return 0; 2108 2109 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2110 if (err) 2111 return err; 2112 2113 if (!vlan.valid) 2114 return 0; 2115 2116 dsa_switch_for_each_user_port(other_dp, ds) { 2117 struct net_device *other_br; 2118 2119 if (vlan.member[other_dp->index] == 2120 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2121 continue; 2122 2123 if (dsa_port_bridge_same(dp, other_dp)) 2124 break; /* same bridge, check next VLAN */ 2125 2126 other_br = dsa_port_bridge_dev_get(other_dp); 2127 if (!other_br) 2128 continue; 2129 2130 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2131 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2132 return -EOPNOTSUPP; 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2139 { 2140 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2141 struct net_device *br = dsa_port_bridge_dev_get(dp); 2142 struct mv88e6xxx_port *p = &chip->ports[port]; 2143 u16 pvid = MV88E6XXX_VID_STANDALONE; 2144 bool drop_untagged = false; 2145 int err; 2146 2147 if (br) { 2148 if (br_vlan_enabled(br)) { 2149 pvid = p->bridge_pvid.vid; 2150 drop_untagged = !p->bridge_pvid.valid; 2151 } else { 2152 pvid = MV88E6XXX_VID_BRIDGED; 2153 } 2154 } 2155 2156 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2157 if (err) 2158 return err; 2159 2160 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2161 } 2162 2163 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2164 bool vlan_filtering, 2165 struct netlink_ext_ack *extack) 2166 { 2167 struct mv88e6xxx_chip *chip = ds->priv; 2168 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2169 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2170 int err; 2171 2172 if (!mv88e6xxx_max_vid(chip)) 2173 return -EOPNOTSUPP; 2174 2175 mv88e6xxx_reg_lock(chip); 2176 2177 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2178 if (err) 2179 goto unlock; 2180 2181 err = mv88e6xxx_port_commit_pvid(chip, port); 2182 if (err) 2183 goto unlock; 2184 2185 unlock: 2186 mv88e6xxx_reg_unlock(chip); 2187 2188 return err; 2189 } 2190 2191 static int 2192 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2193 const struct switchdev_obj_port_vlan *vlan) 2194 { 2195 struct mv88e6xxx_chip *chip = ds->priv; 2196 int err; 2197 2198 if (!mv88e6xxx_max_vid(chip)) 2199 return -EOPNOTSUPP; 2200 2201 /* If the requested port doesn't belong to the same bridge as the VLAN 2202 * members, do not support it (yet) and fallback to software VLAN. 2203 */ 2204 mv88e6xxx_reg_lock(chip); 2205 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2206 mv88e6xxx_reg_unlock(chip); 2207 2208 return err; 2209 } 2210 2211 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip, 2212 const unsigned char *addr, u16 vid, 2213 u16 *fid, struct mv88e6xxx_atu_entry *entry) 2214 { 2215 struct mv88e6xxx_vtu_entry vlan; 2216 int err; 2217 2218 /* Ports have two private address databases: one for when the port is 2219 * standalone and one for when the port is under a bridge and the 2220 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2221 * address database to remain 100% empty, so we never load an ATU entry 2222 * into a standalone port's database. Therefore, translate the null 2223 * VLAN ID into the port's database used for VLAN-unaware bridging. 2224 */ 2225 if (vid == 0) { 2226 *fid = MV88E6XXX_FID_BRIDGED; 2227 } else { 2228 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2229 if (err) 2230 return err; 2231 2232 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2233 if (!vlan.valid) 2234 return -EOPNOTSUPP; 2235 2236 *fid = vlan.fid; 2237 } 2238 2239 entry->state = 0; 2240 ether_addr_copy(entry->mac, addr); 2241 eth_addr_dec(entry->mac); 2242 2243 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry); 2244 } 2245 2246 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip, 2247 const unsigned char *addr, u16 vid) 2248 { 2249 struct mv88e6xxx_atu_entry entry; 2250 u16 fid; 2251 int err; 2252 2253 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2254 if (err) 2255 return false; 2256 2257 return entry.state && ether_addr_equal(entry.mac, addr); 2258 } 2259 2260 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2261 const unsigned char *addr, u16 vid, 2262 u8 state) 2263 { 2264 struct mv88e6xxx_atu_entry entry; 2265 u16 fid; 2266 int err; 2267 2268 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2269 if (err) 2270 return err; 2271 2272 /* Initialize a fresh ATU entry if it isn't found */ 2273 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2274 memset(&entry, 0, sizeof(entry)); 2275 ether_addr_copy(entry.mac, addr); 2276 } 2277 2278 /* Purge the ATU entry only if no port is using it anymore */ 2279 if (!state) { 2280 entry.portvec &= ~BIT(port); 2281 if (!entry.portvec) 2282 entry.state = 0; 2283 } else { 2284 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2285 entry.portvec = BIT(port); 2286 else 2287 entry.portvec |= BIT(port); 2288 2289 entry.state = state; 2290 } 2291 2292 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2293 } 2294 2295 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2296 const struct mv88e6xxx_policy *policy) 2297 { 2298 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2299 enum mv88e6xxx_policy_action action = policy->action; 2300 const u8 *addr = policy->addr; 2301 u16 vid = policy->vid; 2302 u8 state; 2303 int err; 2304 int id; 2305 2306 if (!chip->info->ops->port_set_policy) 2307 return -EOPNOTSUPP; 2308 2309 switch (mapping) { 2310 case MV88E6XXX_POLICY_MAPPING_DA: 2311 case MV88E6XXX_POLICY_MAPPING_SA: 2312 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2313 state = 0; /* Dissociate the port and address */ 2314 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2315 is_multicast_ether_addr(addr)) 2316 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2317 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2318 is_unicast_ether_addr(addr)) 2319 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2320 else 2321 return -EOPNOTSUPP; 2322 2323 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2324 state); 2325 if (err) 2326 return err; 2327 break; 2328 default: 2329 return -EOPNOTSUPP; 2330 } 2331 2332 /* Skip the port's policy clearing if the mapping is still in use */ 2333 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2334 idr_for_each_entry(&chip->policies, policy, id) 2335 if (policy->port == port && 2336 policy->mapping == mapping && 2337 policy->action != action) 2338 return 0; 2339 2340 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2341 } 2342 2343 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2344 struct ethtool_rx_flow_spec *fs) 2345 { 2346 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2347 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2348 enum mv88e6xxx_policy_mapping mapping; 2349 enum mv88e6xxx_policy_action action; 2350 struct mv88e6xxx_policy *policy; 2351 u16 vid = 0; 2352 u8 *addr; 2353 int err; 2354 int id; 2355 2356 if (fs->location != RX_CLS_LOC_ANY) 2357 return -EINVAL; 2358 2359 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2360 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2361 else 2362 return -EOPNOTSUPP; 2363 2364 switch (fs->flow_type & ~FLOW_EXT) { 2365 case ETHER_FLOW: 2366 if (!is_zero_ether_addr(mac_mask->h_dest) && 2367 is_zero_ether_addr(mac_mask->h_source)) { 2368 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2369 addr = mac_entry->h_dest; 2370 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2371 !is_zero_ether_addr(mac_mask->h_source)) { 2372 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2373 addr = mac_entry->h_source; 2374 } else { 2375 /* Cannot support DA and SA mapping in the same rule */ 2376 return -EOPNOTSUPP; 2377 } 2378 break; 2379 default: 2380 return -EOPNOTSUPP; 2381 } 2382 2383 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2384 if (fs->m_ext.vlan_tci != htons(0xffff)) 2385 return -EOPNOTSUPP; 2386 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2387 } 2388 2389 idr_for_each_entry(&chip->policies, policy, id) { 2390 if (policy->port == port && policy->mapping == mapping && 2391 policy->action == action && policy->vid == vid && 2392 ether_addr_equal(policy->addr, addr)) 2393 return -EEXIST; 2394 } 2395 2396 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2397 if (!policy) 2398 return -ENOMEM; 2399 2400 fs->location = 0; 2401 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2402 GFP_KERNEL); 2403 if (err) { 2404 devm_kfree(chip->dev, policy); 2405 return err; 2406 } 2407 2408 memcpy(&policy->fs, fs, sizeof(*fs)); 2409 ether_addr_copy(policy->addr, addr); 2410 policy->mapping = mapping; 2411 policy->action = action; 2412 policy->port = port; 2413 policy->vid = vid; 2414 2415 err = mv88e6xxx_policy_apply(chip, port, policy); 2416 if (err) { 2417 idr_remove(&chip->policies, fs->location); 2418 devm_kfree(chip->dev, policy); 2419 return err; 2420 } 2421 2422 return 0; 2423 } 2424 2425 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2426 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2427 { 2428 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2429 struct mv88e6xxx_chip *chip = ds->priv; 2430 struct mv88e6xxx_policy *policy; 2431 int err; 2432 int id; 2433 2434 mv88e6xxx_reg_lock(chip); 2435 2436 switch (rxnfc->cmd) { 2437 case ETHTOOL_GRXCLSRLCNT: 2438 rxnfc->data = 0; 2439 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2440 rxnfc->rule_cnt = 0; 2441 idr_for_each_entry(&chip->policies, policy, id) 2442 if (policy->port == port) 2443 rxnfc->rule_cnt++; 2444 err = 0; 2445 break; 2446 case ETHTOOL_GRXCLSRULE: 2447 err = -ENOENT; 2448 policy = idr_find(&chip->policies, fs->location); 2449 if (policy) { 2450 memcpy(fs, &policy->fs, sizeof(*fs)); 2451 err = 0; 2452 } 2453 break; 2454 case ETHTOOL_GRXCLSRLALL: 2455 rxnfc->data = 0; 2456 rxnfc->rule_cnt = 0; 2457 idr_for_each_entry(&chip->policies, policy, id) 2458 if (policy->port == port) 2459 rule_locs[rxnfc->rule_cnt++] = id; 2460 err = 0; 2461 break; 2462 default: 2463 err = -EOPNOTSUPP; 2464 break; 2465 } 2466 2467 mv88e6xxx_reg_unlock(chip); 2468 2469 return err; 2470 } 2471 2472 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2473 struct ethtool_rxnfc *rxnfc) 2474 { 2475 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2476 struct mv88e6xxx_chip *chip = ds->priv; 2477 struct mv88e6xxx_policy *policy; 2478 int err; 2479 2480 mv88e6xxx_reg_lock(chip); 2481 2482 switch (rxnfc->cmd) { 2483 case ETHTOOL_SRXCLSRLINS: 2484 err = mv88e6xxx_policy_insert(chip, port, fs); 2485 break; 2486 case ETHTOOL_SRXCLSRLDEL: 2487 err = -ENOENT; 2488 policy = idr_remove(&chip->policies, fs->location); 2489 if (policy) { 2490 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2491 err = mv88e6xxx_policy_apply(chip, port, policy); 2492 devm_kfree(chip->dev, policy); 2493 } 2494 break; 2495 default: 2496 err = -EOPNOTSUPP; 2497 break; 2498 } 2499 2500 mv88e6xxx_reg_unlock(chip); 2501 2502 return err; 2503 } 2504 2505 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2506 u16 vid) 2507 { 2508 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2509 u8 broadcast[ETH_ALEN]; 2510 2511 eth_broadcast_addr(broadcast); 2512 2513 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2514 } 2515 2516 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2517 { 2518 int port; 2519 int err; 2520 2521 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2522 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2523 struct net_device *brport; 2524 2525 if (dsa_is_unused_port(chip->ds, port)) 2526 continue; 2527 2528 brport = dsa_port_to_bridge_port(dp); 2529 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2530 /* Skip bridged user ports where broadcast 2531 * flooding is disabled. 2532 */ 2533 continue; 2534 2535 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2536 if (err) 2537 return err; 2538 } 2539 2540 return 0; 2541 } 2542 2543 struct mv88e6xxx_port_broadcast_sync_ctx { 2544 int port; 2545 bool flood; 2546 }; 2547 2548 static int 2549 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2550 const struct mv88e6xxx_vtu_entry *vlan, 2551 void *_ctx) 2552 { 2553 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2554 u8 broadcast[ETH_ALEN]; 2555 u8 state; 2556 2557 if (ctx->flood) 2558 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2559 else 2560 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2561 2562 eth_broadcast_addr(broadcast); 2563 2564 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2565 vlan->vid, state); 2566 } 2567 2568 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2569 bool flood) 2570 { 2571 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2572 .port = port, 2573 .flood = flood, 2574 }; 2575 struct mv88e6xxx_vtu_entry vid0 = { 2576 .vid = 0, 2577 }; 2578 int err; 2579 2580 /* Update the port's private database... */ 2581 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2582 if (err) 2583 return err; 2584 2585 /* ...and the database for all VLANs. */ 2586 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2587 &ctx); 2588 } 2589 2590 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2591 u16 vid, u8 member, bool warn) 2592 { 2593 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2594 struct mv88e6xxx_vtu_entry vlan; 2595 int i, err; 2596 2597 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2598 if (err) 2599 return err; 2600 2601 if (!vlan.valid) { 2602 memset(&vlan, 0, sizeof(vlan)); 2603 2604 if (vid == MV88E6XXX_VID_STANDALONE) 2605 vlan.policy = true; 2606 2607 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2608 if (err) 2609 return err; 2610 2611 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2612 if (i == port) 2613 vlan.member[i] = member; 2614 else 2615 vlan.member[i] = non_member; 2616 2617 vlan.vid = vid; 2618 vlan.valid = true; 2619 2620 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2621 if (err) 2622 return err; 2623 2624 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2625 if (err) 2626 return err; 2627 } else if (vlan.member[port] != member) { 2628 vlan.member[port] = member; 2629 2630 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2631 if (err) 2632 return err; 2633 } else if (warn) { 2634 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2635 port, vid); 2636 } 2637 2638 /* Record FID used in SW FID map */ 2639 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2640 2641 return 0; 2642 } 2643 2644 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2645 const struct switchdev_obj_port_vlan *vlan, 2646 struct netlink_ext_ack *extack) 2647 { 2648 struct mv88e6xxx_chip *chip = ds->priv; 2649 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2650 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2651 struct mv88e6xxx_port *p = &chip->ports[port]; 2652 bool warn; 2653 u8 member; 2654 int err; 2655 2656 if (!vlan->vid) 2657 return 0; 2658 2659 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2660 if (err) 2661 return err; 2662 2663 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2664 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2665 else if (untagged) 2666 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2667 else 2668 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2669 2670 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2671 * and then the CPU port. Do not warn for duplicates for the CPU port. 2672 */ 2673 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2674 2675 mv88e6xxx_reg_lock(chip); 2676 2677 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2678 if (err) { 2679 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2680 vlan->vid, untagged ? 'u' : 't'); 2681 goto out; 2682 } 2683 2684 if (pvid) { 2685 p->bridge_pvid.vid = vlan->vid; 2686 p->bridge_pvid.valid = true; 2687 2688 err = mv88e6xxx_port_commit_pvid(chip, port); 2689 if (err) 2690 goto out; 2691 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2692 /* The old pvid was reinstalled as a non-pvid VLAN */ 2693 p->bridge_pvid.valid = false; 2694 2695 err = mv88e6xxx_port_commit_pvid(chip, port); 2696 if (err) 2697 goto out; 2698 } 2699 2700 out: 2701 mv88e6xxx_reg_unlock(chip); 2702 2703 return err; 2704 } 2705 2706 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2707 int port, u16 vid) 2708 { 2709 struct mv88e6xxx_vtu_entry vlan; 2710 int i, err; 2711 2712 if (!vid) 2713 return 0; 2714 2715 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2716 if (err) 2717 return err; 2718 2719 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2720 * tell switchdev that this VLAN is likely handled in software. 2721 */ 2722 if (!vlan.valid || 2723 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2724 return -EOPNOTSUPP; 2725 2726 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2727 2728 /* keep the VLAN unless all ports are excluded */ 2729 vlan.valid = false; 2730 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2731 if (vlan.member[i] != 2732 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2733 vlan.valid = true; 2734 break; 2735 } 2736 } 2737 2738 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2739 if (err) 2740 return err; 2741 2742 if (!vlan.valid) { 2743 err = mv88e6xxx_mst_put(chip, vlan.sid); 2744 if (err) 2745 return err; 2746 2747 /* Record FID freed in SW FID map */ 2748 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2749 } 2750 2751 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2752 } 2753 2754 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2755 const struct switchdev_obj_port_vlan *vlan) 2756 { 2757 struct mv88e6xxx_chip *chip = ds->priv; 2758 struct mv88e6xxx_port *p = &chip->ports[port]; 2759 int err = 0; 2760 u16 pvid; 2761 2762 if (!mv88e6xxx_max_vid(chip)) 2763 return -EOPNOTSUPP; 2764 2765 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2766 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2767 * switchdev workqueue to ensure that all FDB entries are deleted 2768 * before we remove the VLAN. 2769 */ 2770 dsa_flush_workqueue(); 2771 2772 mv88e6xxx_reg_lock(chip); 2773 2774 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2775 if (err) 2776 goto unlock; 2777 2778 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2779 if (err) 2780 goto unlock; 2781 2782 if (vlan->vid == pvid) { 2783 p->bridge_pvid.valid = false; 2784 2785 err = mv88e6xxx_port_commit_pvid(chip, port); 2786 if (err) 2787 goto unlock; 2788 } 2789 2790 unlock: 2791 mv88e6xxx_reg_unlock(chip); 2792 2793 return err; 2794 } 2795 2796 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2797 { 2798 struct mv88e6xxx_chip *chip = ds->priv; 2799 struct mv88e6xxx_vtu_entry vlan; 2800 int err; 2801 2802 mv88e6xxx_reg_lock(chip); 2803 2804 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2805 if (err) 2806 goto unlock; 2807 2808 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2809 2810 unlock: 2811 mv88e6xxx_reg_unlock(chip); 2812 2813 return err; 2814 } 2815 2816 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2817 struct dsa_bridge bridge, 2818 const struct switchdev_vlan_msti *msti) 2819 { 2820 struct mv88e6xxx_chip *chip = ds->priv; 2821 struct mv88e6xxx_vtu_entry vlan; 2822 u8 old_sid, new_sid; 2823 int err; 2824 2825 if (!mv88e6xxx_has_stu(chip)) 2826 return -EOPNOTSUPP; 2827 2828 mv88e6xxx_reg_lock(chip); 2829 2830 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2831 if (err) 2832 goto unlock; 2833 2834 if (!vlan.valid) { 2835 err = -EINVAL; 2836 goto unlock; 2837 } 2838 2839 old_sid = vlan.sid; 2840 2841 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2842 if (err) 2843 goto unlock; 2844 2845 if (new_sid != old_sid) { 2846 vlan.sid = new_sid; 2847 2848 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2849 if (err) { 2850 mv88e6xxx_mst_put(chip, new_sid); 2851 goto unlock; 2852 } 2853 } 2854 2855 err = mv88e6xxx_mst_put(chip, old_sid); 2856 2857 unlock: 2858 mv88e6xxx_reg_unlock(chip); 2859 return err; 2860 } 2861 2862 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2863 const unsigned char *addr, u16 vid, 2864 struct dsa_db db) 2865 { 2866 struct mv88e6xxx_chip *chip = ds->priv; 2867 int err; 2868 2869 mv88e6xxx_reg_lock(chip); 2870 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2871 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2872 if (err) 2873 goto out; 2874 2875 if (!mv88e6xxx_port_db_find(chip, addr, vid)) 2876 err = -ENOSPC; 2877 2878 out: 2879 mv88e6xxx_reg_unlock(chip); 2880 2881 return err; 2882 } 2883 2884 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2885 const unsigned char *addr, u16 vid, 2886 struct dsa_db db) 2887 { 2888 struct mv88e6xxx_chip *chip = ds->priv; 2889 int err; 2890 2891 mv88e6xxx_reg_lock(chip); 2892 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2893 mv88e6xxx_reg_unlock(chip); 2894 2895 return err; 2896 } 2897 2898 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2899 u16 fid, u16 vid, int port, 2900 dsa_fdb_dump_cb_t *cb, void *data) 2901 { 2902 struct mv88e6xxx_atu_entry addr; 2903 bool is_static; 2904 int err; 2905 2906 addr.state = 0; 2907 eth_broadcast_addr(addr.mac); 2908 2909 do { 2910 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2911 if (err) 2912 return err; 2913 2914 if (!addr.state) 2915 break; 2916 2917 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2918 continue; 2919 2920 if (!is_unicast_ether_addr(addr.mac)) 2921 continue; 2922 2923 is_static = (addr.state == 2924 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2925 err = cb(addr.mac, vid, is_static, data); 2926 if (err) 2927 return err; 2928 } while (!is_broadcast_ether_addr(addr.mac)); 2929 2930 return err; 2931 } 2932 2933 struct mv88e6xxx_port_db_dump_vlan_ctx { 2934 int port; 2935 dsa_fdb_dump_cb_t *cb; 2936 void *data; 2937 }; 2938 2939 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2940 const struct mv88e6xxx_vtu_entry *entry, 2941 void *_data) 2942 { 2943 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2944 2945 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2946 ctx->port, ctx->cb, ctx->data); 2947 } 2948 2949 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2950 dsa_fdb_dump_cb_t *cb, void *data) 2951 { 2952 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2953 .port = port, 2954 .cb = cb, 2955 .data = data, 2956 }; 2957 u16 fid; 2958 int err; 2959 2960 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2961 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2962 if (err) 2963 return err; 2964 2965 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2966 if (err) 2967 return err; 2968 2969 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2970 } 2971 2972 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2973 dsa_fdb_dump_cb_t *cb, void *data) 2974 { 2975 struct mv88e6xxx_chip *chip = ds->priv; 2976 int err; 2977 2978 mv88e6xxx_reg_lock(chip); 2979 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2980 mv88e6xxx_reg_unlock(chip); 2981 2982 return err; 2983 } 2984 2985 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2986 struct dsa_bridge bridge) 2987 { 2988 struct dsa_switch *ds = chip->ds; 2989 struct dsa_switch_tree *dst = ds->dst; 2990 struct dsa_port *dp; 2991 int err; 2992 2993 list_for_each_entry(dp, &dst->ports, list) { 2994 if (dsa_port_offloads_bridge(dp, &bridge)) { 2995 if (dp->ds == ds) { 2996 /* This is a local bridge group member, 2997 * remap its Port VLAN Map. 2998 */ 2999 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3000 if (err) 3001 return err; 3002 } else { 3003 /* This is an external bridge group member, 3004 * remap its cross-chip Port VLAN Table entry. 3005 */ 3006 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3007 dp->index); 3008 if (err) 3009 return err; 3010 } 3011 } 3012 } 3013 3014 return 0; 3015 } 3016 3017 /* Treat the software bridge as a virtual single-port switch behind the 3018 * CPU and map in the PVT. First dst->last_switch elements are taken by 3019 * physical switches, so start from beyond that range. 3020 */ 3021 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3022 unsigned int bridge_num) 3023 { 3024 u8 dev = bridge_num + ds->dst->last_switch; 3025 struct mv88e6xxx_chip *chip = ds->priv; 3026 3027 return mv88e6xxx_pvt_map(chip, dev, 0); 3028 } 3029 3030 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3031 struct dsa_bridge bridge, 3032 bool *tx_fwd_offload, 3033 struct netlink_ext_ack *extack) 3034 { 3035 struct mv88e6xxx_chip *chip = ds->priv; 3036 int err; 3037 3038 mv88e6xxx_reg_lock(chip); 3039 3040 err = mv88e6xxx_bridge_map(chip, bridge); 3041 if (err) 3042 goto unlock; 3043 3044 err = mv88e6xxx_port_set_map_da(chip, port, true); 3045 if (err) 3046 goto unlock; 3047 3048 err = mv88e6xxx_port_commit_pvid(chip, port); 3049 if (err) 3050 goto unlock; 3051 3052 if (mv88e6xxx_has_pvt(chip)) { 3053 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3054 if (err) 3055 goto unlock; 3056 3057 *tx_fwd_offload = true; 3058 } 3059 3060 unlock: 3061 mv88e6xxx_reg_unlock(chip); 3062 3063 return err; 3064 } 3065 3066 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3067 struct dsa_bridge bridge) 3068 { 3069 struct mv88e6xxx_chip *chip = ds->priv; 3070 int err; 3071 3072 mv88e6xxx_reg_lock(chip); 3073 3074 if (bridge.tx_fwd_offload && 3075 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3076 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3077 3078 if (mv88e6xxx_bridge_map(chip, bridge) || 3079 mv88e6xxx_port_vlan_map(chip, port)) 3080 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3081 3082 err = mv88e6xxx_port_set_map_da(chip, port, false); 3083 if (err) 3084 dev_err(ds->dev, 3085 "port %d failed to restore map-DA: %pe\n", 3086 port, ERR_PTR(err)); 3087 3088 err = mv88e6xxx_port_commit_pvid(chip, port); 3089 if (err) 3090 dev_err(ds->dev, 3091 "port %d failed to restore standalone pvid: %pe\n", 3092 port, ERR_PTR(err)); 3093 3094 mv88e6xxx_reg_unlock(chip); 3095 } 3096 3097 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3098 int tree_index, int sw_index, 3099 int port, struct dsa_bridge bridge, 3100 struct netlink_ext_ack *extack) 3101 { 3102 struct mv88e6xxx_chip *chip = ds->priv; 3103 int err; 3104 3105 if (tree_index != ds->dst->index) 3106 return 0; 3107 3108 mv88e6xxx_reg_lock(chip); 3109 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3110 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3111 mv88e6xxx_reg_unlock(chip); 3112 3113 return err; 3114 } 3115 3116 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3117 int tree_index, int sw_index, 3118 int port, struct dsa_bridge bridge) 3119 { 3120 struct mv88e6xxx_chip *chip = ds->priv; 3121 3122 if (tree_index != ds->dst->index) 3123 return; 3124 3125 mv88e6xxx_reg_lock(chip); 3126 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3127 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3128 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3129 mv88e6xxx_reg_unlock(chip); 3130 } 3131 3132 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3133 { 3134 if (chip->info->ops->reset) 3135 return chip->info->ops->reset(chip); 3136 3137 return 0; 3138 } 3139 3140 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3141 { 3142 struct gpio_desc *gpiod = chip->reset; 3143 int err; 3144 3145 /* If there is a GPIO connected to the reset pin, toggle it */ 3146 if (gpiod) { 3147 /* If the switch has just been reset and not yet completed 3148 * loading EEPROM, the reset may interrupt the I2C transaction 3149 * mid-byte, causing the first EEPROM read after the reset 3150 * from the wrong location resulting in the switch booting 3151 * to wrong mode and inoperable. 3152 * For this reason, switch families with EEPROM support 3153 * generally wait for EEPROM loads to complete as their pre- 3154 * and post-reset handlers. 3155 */ 3156 if (chip->info->ops->hardware_reset_pre) { 3157 err = chip->info->ops->hardware_reset_pre(chip); 3158 if (err) 3159 dev_err(chip->dev, "pre-reset error: %d\n", err); 3160 } 3161 3162 gpiod_set_value_cansleep(gpiod, 1); 3163 usleep_range(10000, 20000); 3164 gpiod_set_value_cansleep(gpiod, 0); 3165 usleep_range(10000, 20000); 3166 3167 if (chip->info->ops->hardware_reset_post) { 3168 err = chip->info->ops->hardware_reset_post(chip); 3169 if (err) 3170 dev_err(chip->dev, "post-reset error: %d\n", err); 3171 } 3172 } 3173 } 3174 3175 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3176 { 3177 int i, err; 3178 3179 /* Set all ports to the Disabled state */ 3180 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3181 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3182 if (err) 3183 return err; 3184 } 3185 3186 /* Wait for transmit queues to drain, 3187 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3188 */ 3189 usleep_range(2000, 4000); 3190 3191 return 0; 3192 } 3193 3194 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3195 { 3196 int err; 3197 3198 err = mv88e6xxx_disable_ports(chip); 3199 if (err) 3200 return err; 3201 3202 mv88e6xxx_hardware_reset(chip); 3203 3204 return mv88e6xxx_software_reset(chip); 3205 } 3206 3207 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3208 enum mv88e6xxx_frame_mode frame, 3209 enum mv88e6xxx_egress_mode egress, u16 etype) 3210 { 3211 int err; 3212 3213 if (!chip->info->ops->port_set_frame_mode) 3214 return -EOPNOTSUPP; 3215 3216 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3217 if (err) 3218 return err; 3219 3220 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3221 if (err) 3222 return err; 3223 3224 if (chip->info->ops->port_set_ether_type) 3225 return chip->info->ops->port_set_ether_type(chip, port, etype); 3226 3227 return 0; 3228 } 3229 3230 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3231 { 3232 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3233 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3234 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3235 } 3236 3237 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3238 { 3239 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3240 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3241 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3242 } 3243 3244 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3245 { 3246 return mv88e6xxx_set_port_mode(chip, port, 3247 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3248 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3249 ETH_P_EDSA); 3250 } 3251 3252 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3253 { 3254 if (dsa_is_dsa_port(chip->ds, port)) 3255 return mv88e6xxx_set_port_mode_dsa(chip, port); 3256 3257 if (dsa_is_user_port(chip->ds, port)) 3258 return mv88e6xxx_set_port_mode_normal(chip, port); 3259 3260 /* Setup CPU port mode depending on its supported tag format */ 3261 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3262 return mv88e6xxx_set_port_mode_dsa(chip, port); 3263 3264 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3265 return mv88e6xxx_set_port_mode_edsa(chip, port); 3266 3267 return -EINVAL; 3268 } 3269 3270 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3271 { 3272 bool message = dsa_is_dsa_port(chip->ds, port); 3273 3274 return mv88e6xxx_port_set_message_port(chip, port, message); 3275 } 3276 3277 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3278 { 3279 int err; 3280 3281 if (chip->info->ops->port_set_ucast_flood) { 3282 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3283 if (err) 3284 return err; 3285 } 3286 if (chip->info->ops->port_set_mcast_flood) { 3287 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3288 if (err) 3289 return err; 3290 } 3291 3292 return 0; 3293 } 3294 3295 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3296 enum mv88e6xxx_egress_direction direction, 3297 int port) 3298 { 3299 int err; 3300 3301 if (!chip->info->ops->set_egress_port) 3302 return -EOPNOTSUPP; 3303 3304 err = chip->info->ops->set_egress_port(chip, direction, port); 3305 if (err) 3306 return err; 3307 3308 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3309 chip->ingress_dest_port = port; 3310 else 3311 chip->egress_dest_port = port; 3312 3313 return 0; 3314 } 3315 3316 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3317 { 3318 struct dsa_switch *ds = chip->ds; 3319 int upstream_port; 3320 int err; 3321 3322 upstream_port = dsa_upstream_port(ds, port); 3323 if (chip->info->ops->port_set_upstream_port) { 3324 err = chip->info->ops->port_set_upstream_port(chip, port, 3325 upstream_port); 3326 if (err) 3327 return err; 3328 } 3329 3330 if (port == upstream_port) { 3331 if (chip->info->ops->set_cpu_port) { 3332 err = chip->info->ops->set_cpu_port(chip, 3333 upstream_port); 3334 if (err) 3335 return err; 3336 } 3337 3338 err = mv88e6xxx_set_egress_port(chip, 3339 MV88E6XXX_EGRESS_DIR_INGRESS, 3340 upstream_port); 3341 if (err && err != -EOPNOTSUPP) 3342 return err; 3343 3344 err = mv88e6xxx_set_egress_port(chip, 3345 MV88E6XXX_EGRESS_DIR_EGRESS, 3346 upstream_port); 3347 if (err && err != -EOPNOTSUPP) 3348 return err; 3349 } 3350 3351 return 0; 3352 } 3353 3354 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3355 { 3356 struct device_node *phy_handle = NULL; 3357 struct fwnode_handle *ports_fwnode; 3358 struct fwnode_handle *port_fwnode; 3359 struct dsa_switch *ds = chip->ds; 3360 struct mv88e6xxx_port *p; 3361 struct dsa_port *dp; 3362 int tx_amp; 3363 int err; 3364 u16 reg; 3365 u32 val; 3366 3367 p = &chip->ports[port]; 3368 p->chip = chip; 3369 p->port = port; 3370 3371 /* Look up corresponding fwnode if any */ 3372 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3373 if (!ports_fwnode) 3374 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3375 if (ports_fwnode) { 3376 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3377 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3378 continue; 3379 if (val == port) { 3380 p->fwnode = port_fwnode; 3381 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3382 break; 3383 } 3384 } 3385 fwnode_handle_put(ports_fwnode); 3386 } else { 3387 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3388 } 3389 3390 if (chip->info->ops->port_setup_leds) { 3391 err = chip->info->ops->port_setup_leds(chip, port); 3392 if (err && err != -EOPNOTSUPP) 3393 return err; 3394 } 3395 3396 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3397 SPEED_UNFORCED, DUPLEX_UNFORCED, 3398 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3399 if (err) 3400 return err; 3401 3402 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3403 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3404 * tunneling, determine priority by looking at 802.1p and IP 3405 * priority fields (IP prio has precedence), and set STP state 3406 * to Forwarding. 3407 * 3408 * If this is the CPU link, use DSA or EDSA tagging depending 3409 * on which tagging mode was configured. 3410 * 3411 * If this is a link to another switch, use DSA tagging mode. 3412 * 3413 * If this is the upstream port for this switch, enable 3414 * forwarding of unknown unicasts and multicasts. 3415 */ 3416 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3417 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3418 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3419 * by a USER port to the CPU port to allow snooping. 3420 */ 3421 if (dsa_is_user_port(ds, port)) 3422 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3423 3424 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3425 if (err) 3426 return err; 3427 3428 err = mv88e6xxx_setup_port_mode(chip, port); 3429 if (err) 3430 return err; 3431 3432 err = mv88e6xxx_setup_egress_floods(chip, port); 3433 if (err) 3434 return err; 3435 3436 /* Port Control 2: don't force a good FCS, set the MTU size to 3437 * 10222 bytes, disable 802.1q tags checking, don't discard 3438 * tagged or untagged frames on this port, skip destination 3439 * address lookup on user ports, disable ARP mirroring and don't 3440 * send a copy of all transmitted/received frames on this port 3441 * to the CPU. 3442 */ 3443 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3444 if (err) 3445 return err; 3446 3447 err = mv88e6xxx_setup_upstream_port(chip, port); 3448 if (err) 3449 return err; 3450 3451 /* On chips that support it, set all downstream DSA ports' 3452 * VLAN policy to TRAP. In combination with loading 3453 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3454 * provides a better isolation barrier between standalone 3455 * ports, as the ATU is bypassed on any intermediate switches 3456 * between the incoming port and the CPU. 3457 */ 3458 if (dsa_is_downstream_port(ds, port) && 3459 chip->info->ops->port_set_policy) { 3460 err = chip->info->ops->port_set_policy(chip, port, 3461 MV88E6XXX_POLICY_MAPPING_VTU, 3462 MV88E6XXX_POLICY_ACTION_TRAP); 3463 if (err) 3464 return err; 3465 } 3466 3467 /* User ports start out in standalone mode and 802.1Q is 3468 * therefore disabled. On DSA ports, all valid VIDs are always 3469 * loaded in the VTU - therefore, enable 802.1Q in order to take 3470 * advantage of VLAN policy on chips that supports it. 3471 */ 3472 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3473 dsa_is_user_port(ds, port) ? 3474 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3475 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3476 if (err) 3477 return err; 3478 3479 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3480 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3481 * the first free FID. This will be used as the private PVID for 3482 * unbridged ports. Shared (DSA and CPU) ports must also be 3483 * members of this VID, in order to trap all frames assigned to 3484 * it to the CPU. 3485 */ 3486 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3487 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3488 false); 3489 if (err) 3490 return err; 3491 3492 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3493 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3494 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3495 * as the private PVID on ports under a VLAN-unaware bridge. 3496 * Shared (DSA and CPU) ports must also be members of it, to translate 3497 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3498 * relying on their port default FID. 3499 */ 3500 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3501 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3502 false); 3503 if (err) 3504 return err; 3505 3506 if (chip->info->ops->port_set_jumbo_size) { 3507 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3508 if (err) 3509 return err; 3510 } 3511 3512 /* Port Association Vector: disable automatic address learning 3513 * on all user ports since they start out in standalone 3514 * mode. When joining a bridge, learning will be configured to 3515 * match the bridge port settings. Enable learning on all 3516 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3517 * learning process. 3518 * 3519 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3520 * and RefreshLocked. I.e. setup standard automatic learning. 3521 */ 3522 if (dsa_is_user_port(ds, port)) 3523 reg = 0; 3524 else 3525 reg = 1 << port; 3526 3527 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3528 reg); 3529 if (err) 3530 return err; 3531 3532 /* Egress rate control 2: disable egress rate control. */ 3533 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3534 0x0000); 3535 if (err) 3536 return err; 3537 3538 if (chip->info->ops->port_pause_limit) { 3539 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3540 if (err) 3541 return err; 3542 } 3543 3544 if (chip->info->ops->port_disable_learn_limit) { 3545 err = chip->info->ops->port_disable_learn_limit(chip, port); 3546 if (err) 3547 return err; 3548 } 3549 3550 if (chip->info->ops->port_disable_pri_override) { 3551 err = chip->info->ops->port_disable_pri_override(chip, port); 3552 if (err) 3553 return err; 3554 } 3555 3556 if (chip->info->ops->port_tag_remap) { 3557 err = chip->info->ops->port_tag_remap(chip, port); 3558 if (err) 3559 return err; 3560 } 3561 3562 if (chip->info->ops->port_egress_rate_limiting) { 3563 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3564 if (err) 3565 return err; 3566 } 3567 3568 if (chip->info->ops->port_setup_message_port) { 3569 err = chip->info->ops->port_setup_message_port(chip, port); 3570 if (err) 3571 return err; 3572 } 3573 3574 if (chip->info->ops->serdes_set_tx_amplitude) { 3575 dp = dsa_to_port(ds, port); 3576 if (dp) 3577 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3578 3579 if (phy_handle && !of_property_read_u32(phy_handle, 3580 "tx-p2p-microvolt", 3581 &tx_amp)) 3582 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3583 port, tx_amp); 3584 if (phy_handle) { 3585 of_node_put(phy_handle); 3586 if (err) 3587 return err; 3588 } 3589 } 3590 3591 /* Port based VLAN map: give each port the same default address 3592 * database, and allow bidirectional communication between the 3593 * CPU and DSA port(s), and the other ports. 3594 */ 3595 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3596 if (err) 3597 return err; 3598 3599 err = mv88e6xxx_port_vlan_map(chip, port); 3600 if (err) 3601 return err; 3602 3603 /* Default VLAN ID and priority: don't set a default VLAN 3604 * ID, and set the default packet priority to zero. 3605 */ 3606 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3607 } 3608 3609 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3610 { 3611 struct mv88e6xxx_chip *chip = ds->priv; 3612 3613 if (chip->info->ops->port_set_jumbo_size) 3614 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3615 else if (chip->info->ops->set_max_frame_size) 3616 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3617 return ETH_DATA_LEN; 3618 } 3619 3620 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3621 { 3622 struct mv88e6xxx_chip *chip = ds->priv; 3623 int ret = 0; 3624 3625 /* For families where we don't know how to alter the MTU, 3626 * just accept any value up to ETH_DATA_LEN 3627 */ 3628 if (!chip->info->ops->port_set_jumbo_size && 3629 !chip->info->ops->set_max_frame_size) { 3630 if (new_mtu > ETH_DATA_LEN) 3631 return -EINVAL; 3632 3633 return 0; 3634 } 3635 3636 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3637 new_mtu += EDSA_HLEN; 3638 3639 mv88e6xxx_reg_lock(chip); 3640 if (chip->info->ops->port_set_jumbo_size) 3641 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3642 else if (chip->info->ops->set_max_frame_size && 3643 dsa_is_cpu_port(ds, port)) 3644 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3645 mv88e6xxx_reg_unlock(chip); 3646 3647 return ret; 3648 } 3649 3650 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3651 unsigned int ageing_time) 3652 { 3653 struct mv88e6xxx_chip *chip = ds->priv; 3654 int err; 3655 3656 mv88e6xxx_reg_lock(chip); 3657 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3658 mv88e6xxx_reg_unlock(chip); 3659 3660 return err; 3661 } 3662 3663 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3664 { 3665 int err; 3666 3667 /* Initialize the statistics unit */ 3668 if (chip->info->ops->stats_set_histogram) { 3669 err = chip->info->ops->stats_set_histogram(chip); 3670 if (err) 3671 return err; 3672 } 3673 3674 return mv88e6xxx_g1_stats_clear(chip); 3675 } 3676 3677 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip) 3678 { 3679 u16 dummy; 3680 int err; 3681 3682 /* Workaround for erratum 3683 * 3.3 RGMII timing may be out of spec when transmit delay is enabled 3684 */ 3685 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000); 3686 if (err) 3687 return err; 3688 3689 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy); 3690 } 3691 3692 /* Check if the errata has already been applied. */ 3693 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3694 { 3695 int port; 3696 int err; 3697 u16 val; 3698 3699 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3700 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3701 if (err) { 3702 dev_err(chip->dev, 3703 "Error reading hidden register: %d\n", err); 3704 return false; 3705 } 3706 if (val != 0x01c0) 3707 return false; 3708 } 3709 3710 return true; 3711 } 3712 3713 /* The 6390 copper ports have an errata which require poking magic 3714 * values into undocumented hidden registers and then performing a 3715 * software reset. 3716 */ 3717 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3718 { 3719 int port; 3720 int err; 3721 3722 if (mv88e6390_setup_errata_applied(chip)) 3723 return 0; 3724 3725 /* Set the ports into blocking mode */ 3726 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3727 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3728 if (err) 3729 return err; 3730 } 3731 3732 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3733 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3734 if (err) 3735 return err; 3736 } 3737 3738 return mv88e6xxx_software_reset(chip); 3739 } 3740 3741 /* prod_id for switch families which do not have a PHY model number */ 3742 static const u16 family_prod_id_table[] = { 3743 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3744 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3745 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3746 }; 3747 3748 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3749 { 3750 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3751 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3752 u16 prod_id; 3753 u16 val; 3754 int err; 3755 3756 if (!chip->info->ops->phy_read) 3757 return -EOPNOTSUPP; 3758 3759 mv88e6xxx_reg_lock(chip); 3760 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3761 mv88e6xxx_reg_unlock(chip); 3762 3763 /* Some internal PHYs don't have a model number. */ 3764 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3765 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3766 prod_id = family_prod_id_table[chip->info->family]; 3767 if (prod_id) 3768 val |= prod_id >> 4; 3769 } 3770 3771 return err ? err : val; 3772 } 3773 3774 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3775 int reg) 3776 { 3777 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3778 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3779 u16 val; 3780 int err; 3781 3782 if (!chip->info->ops->phy_read_c45) 3783 return -ENODEV; 3784 3785 mv88e6xxx_reg_lock(chip); 3786 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3787 mv88e6xxx_reg_unlock(chip); 3788 3789 return err ? err : val; 3790 } 3791 3792 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3793 { 3794 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3795 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3796 int err; 3797 3798 if (!chip->info->ops->phy_write) 3799 return -EOPNOTSUPP; 3800 3801 mv88e6xxx_reg_lock(chip); 3802 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3803 mv88e6xxx_reg_unlock(chip); 3804 3805 return err; 3806 } 3807 3808 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3809 int reg, u16 val) 3810 { 3811 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3812 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3813 int err; 3814 3815 if (!chip->info->ops->phy_write_c45) 3816 return -EOPNOTSUPP; 3817 3818 mv88e6xxx_reg_lock(chip); 3819 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3820 mv88e6xxx_reg_unlock(chip); 3821 3822 return err; 3823 } 3824 3825 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3826 struct device_node *np, 3827 bool external) 3828 { 3829 static int index; 3830 struct mv88e6xxx_mdio_bus *mdio_bus; 3831 struct mii_bus *bus; 3832 int err; 3833 3834 if (external) { 3835 mv88e6xxx_reg_lock(chip); 3836 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3837 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3838 else 3839 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3840 mv88e6xxx_reg_unlock(chip); 3841 3842 if (err) 3843 return err; 3844 } 3845 3846 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3847 if (!bus) 3848 return -ENOMEM; 3849 3850 mdio_bus = bus->priv; 3851 mdio_bus->bus = bus; 3852 mdio_bus->chip = chip; 3853 INIT_LIST_HEAD(&mdio_bus->list); 3854 mdio_bus->external = external; 3855 3856 if (np) { 3857 bus->name = np->full_name; 3858 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3859 } else { 3860 bus->name = "mv88e6xxx SMI"; 3861 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3862 } 3863 3864 bus->read = mv88e6xxx_mdio_read; 3865 bus->write = mv88e6xxx_mdio_write; 3866 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3867 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3868 bus->parent = chip->dev; 3869 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3870 mv88e6xxx_num_ports(chip) - 1, 3871 chip->info->phy_base_addr); 3872 3873 if (!external) { 3874 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3875 if (err) 3876 goto out; 3877 } 3878 3879 err = of_mdiobus_register(bus, np); 3880 if (err) { 3881 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3882 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3883 goto out; 3884 } 3885 3886 if (external) 3887 list_add_tail(&mdio_bus->list, &chip->mdios); 3888 else 3889 list_add(&mdio_bus->list, &chip->mdios); 3890 3891 return 0; 3892 3893 out: 3894 mdiobus_free(bus); 3895 return err; 3896 } 3897 3898 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3899 3900 { 3901 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3902 struct mii_bus *bus; 3903 3904 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3905 bus = mdio_bus->bus; 3906 3907 if (!mdio_bus->external) 3908 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3909 3910 mdiobus_unregister(bus); 3911 mdiobus_free(bus); 3912 } 3913 } 3914 3915 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3916 { 3917 struct device_node *np = chip->dev->of_node; 3918 struct device_node *child; 3919 int err; 3920 3921 /* Always register one mdio bus for the internal/default mdio 3922 * bus. This maybe represented in the device tree, but is 3923 * optional. 3924 */ 3925 child = of_get_child_by_name(np, "mdio"); 3926 err = mv88e6xxx_mdio_register(chip, child, false); 3927 of_node_put(child); 3928 if (err) 3929 return err; 3930 3931 /* Walk the device tree, and see if there are any other nodes 3932 * which say they are compatible with the external mdio 3933 * bus. 3934 */ 3935 for_each_available_child_of_node(np, child) { 3936 if (of_device_is_compatible( 3937 child, "marvell,mv88e6xxx-mdio-external")) { 3938 err = mv88e6xxx_mdio_register(chip, child, true); 3939 if (err) { 3940 mv88e6xxx_mdios_unregister(chip); 3941 of_node_put(child); 3942 return err; 3943 } 3944 } 3945 } 3946 3947 return 0; 3948 } 3949 3950 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3951 { 3952 struct mv88e6xxx_chip *chip = ds->priv; 3953 3954 mv88e6xxx_teardown_devlink_params(ds); 3955 dsa_devlink_resources_unregister(ds); 3956 mv88e6xxx_teardown_devlink_regions_global(ds); 3957 mv88e6xxx_mdios_unregister(chip); 3958 } 3959 3960 static int mv88e6xxx_setup(struct dsa_switch *ds) 3961 { 3962 struct mv88e6xxx_chip *chip = ds->priv; 3963 u8 cmode; 3964 int err; 3965 int i; 3966 3967 err = mv88e6xxx_mdios_register(chip); 3968 if (err) 3969 return err; 3970 3971 chip->ds = ds; 3972 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3973 3974 /* Since virtual bridges are mapped in the PVT, the number we support 3975 * depends on the physical switch topology. We need to let DSA figure 3976 * that out and therefore we cannot set this at dsa_register_switch() 3977 * time. 3978 */ 3979 if (mv88e6xxx_has_pvt(chip)) 3980 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3981 ds->dst->last_switch - 1; 3982 3983 mv88e6xxx_reg_lock(chip); 3984 3985 if (chip->info->ops->setup_errata) { 3986 err = chip->info->ops->setup_errata(chip); 3987 if (err) 3988 goto unlock; 3989 } 3990 3991 /* Cache the cmode of each port. */ 3992 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3993 if (chip->info->ops->port_get_cmode) { 3994 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3995 if (err) 3996 goto unlock; 3997 3998 chip->ports[i].cmode = cmode; 3999 } 4000 } 4001 4002 err = mv88e6xxx_vtu_setup(chip); 4003 if (err) 4004 goto unlock; 4005 4006 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 4007 * VTU, thereby also flushing the STU). 4008 */ 4009 err = mv88e6xxx_stu_setup(chip); 4010 if (err) 4011 goto unlock; 4012 4013 /* Setup Switch Port Registers */ 4014 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4015 if (dsa_is_unused_port(ds, i)) 4016 continue; 4017 4018 /* Prevent the use of an invalid port. */ 4019 if (mv88e6xxx_is_invalid_port(chip, i)) { 4020 dev_err(chip->dev, "port %d is invalid\n", i); 4021 err = -EINVAL; 4022 goto unlock; 4023 } 4024 4025 err = mv88e6xxx_setup_port(chip, i); 4026 if (err) 4027 goto unlock; 4028 } 4029 4030 err = mv88e6xxx_irl_setup(chip); 4031 if (err) 4032 goto unlock; 4033 4034 err = mv88e6xxx_mac_setup(chip); 4035 if (err) 4036 goto unlock; 4037 4038 err = mv88e6xxx_phy_setup(chip); 4039 if (err) 4040 goto unlock; 4041 4042 err = mv88e6xxx_pvt_setup(chip); 4043 if (err) 4044 goto unlock; 4045 4046 err = mv88e6xxx_atu_setup(chip); 4047 if (err) 4048 goto unlock; 4049 4050 err = mv88e6xxx_broadcast_setup(chip, 0); 4051 if (err) 4052 goto unlock; 4053 4054 err = mv88e6xxx_pot_setup(chip); 4055 if (err) 4056 goto unlock; 4057 4058 err = mv88e6xxx_rmu_setup(chip); 4059 if (err) 4060 goto unlock; 4061 4062 err = mv88e6xxx_rsvd2cpu_setup(chip); 4063 if (err) 4064 goto unlock; 4065 4066 err = mv88e6xxx_trunk_setup(chip); 4067 if (err) 4068 goto unlock; 4069 4070 err = mv88e6xxx_devmap_setup(chip); 4071 if (err) 4072 goto unlock; 4073 4074 err = mv88e6xxx_pri_setup(chip); 4075 if (err) 4076 goto unlock; 4077 4078 /* Setup PTP Hardware Clock and timestamping */ 4079 if (chip->info->ptp_support) { 4080 err = mv88e6xxx_ptp_setup(chip); 4081 if (err) 4082 goto unlock; 4083 4084 err = mv88e6xxx_hwtstamp_setup(chip); 4085 if (err) 4086 goto unlock; 4087 } 4088 4089 err = mv88e6xxx_stats_setup(chip); 4090 if (err) 4091 goto unlock; 4092 4093 unlock: 4094 mv88e6xxx_reg_unlock(chip); 4095 4096 if (err) 4097 goto out_mdios; 4098 4099 /* Have to be called without holding the register lock, since 4100 * they take the devlink lock, and we later take the locks in 4101 * the reverse order when getting/setting parameters or 4102 * resource occupancy. 4103 */ 4104 err = mv88e6xxx_setup_devlink_resources(ds); 4105 if (err) 4106 goto out_mdios; 4107 4108 err = mv88e6xxx_setup_devlink_params(ds); 4109 if (err) 4110 goto out_resources; 4111 4112 err = mv88e6xxx_setup_devlink_regions_global(ds); 4113 if (err) 4114 goto out_params; 4115 4116 return 0; 4117 4118 out_params: 4119 mv88e6xxx_teardown_devlink_params(ds); 4120 out_resources: 4121 dsa_devlink_resources_unregister(ds); 4122 out_mdios: 4123 mv88e6xxx_mdios_unregister(chip); 4124 4125 return err; 4126 } 4127 4128 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4129 { 4130 struct mv88e6xxx_chip *chip = ds->priv; 4131 int err; 4132 4133 if (chip->info->ops->pcs_ops && 4134 chip->info->ops->pcs_ops->pcs_init) { 4135 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4136 if (err) 4137 return err; 4138 } 4139 4140 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4141 } 4142 4143 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4144 { 4145 struct mv88e6xxx_chip *chip = ds->priv; 4146 4147 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4148 4149 if (chip->info->ops->pcs_ops && 4150 chip->info->ops->pcs_ops->pcs_teardown) 4151 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4152 } 4153 4154 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4155 { 4156 struct mv88e6xxx_chip *chip = ds->priv; 4157 4158 return chip->eeprom_len; 4159 } 4160 4161 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4162 struct ethtool_eeprom *eeprom, u8 *data) 4163 { 4164 struct mv88e6xxx_chip *chip = ds->priv; 4165 int err; 4166 4167 if (!chip->info->ops->get_eeprom) 4168 return -EOPNOTSUPP; 4169 4170 mv88e6xxx_reg_lock(chip); 4171 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4172 mv88e6xxx_reg_unlock(chip); 4173 4174 if (err) 4175 return err; 4176 4177 eeprom->magic = 0xc3ec4951; 4178 4179 return 0; 4180 } 4181 4182 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4183 struct ethtool_eeprom *eeprom, u8 *data) 4184 { 4185 struct mv88e6xxx_chip *chip = ds->priv; 4186 int err; 4187 4188 if (!chip->info->ops->set_eeprom) 4189 return -EOPNOTSUPP; 4190 4191 if (eeprom->magic != 0xc3ec4951) 4192 return -EINVAL; 4193 4194 mv88e6xxx_reg_lock(chip); 4195 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4196 mv88e6xxx_reg_unlock(chip); 4197 4198 return err; 4199 } 4200 4201 static const struct mv88e6xxx_ops mv88e6085_ops = { 4202 /* MV88E6XXX_FAMILY_6097 */ 4203 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4204 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4205 .irl_init_all = mv88e6352_g2_irl_init_all, 4206 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4207 .phy_read = mv88e6185_phy_ppu_read, 4208 .phy_write = mv88e6185_phy_ppu_write, 4209 .port_set_link = mv88e6xxx_port_set_link, 4210 .port_sync_link = mv88e6xxx_port_sync_link, 4211 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4212 .port_tag_remap = mv88e6095_port_tag_remap, 4213 .port_set_policy = mv88e6352_port_set_policy, 4214 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4215 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4216 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4217 .port_set_ether_type = mv88e6351_port_set_ether_type, 4218 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4219 .port_pause_limit = mv88e6097_port_pause_limit, 4220 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4222 .port_get_cmode = mv88e6185_port_get_cmode, 4223 .port_setup_message_port = mv88e6xxx_setup_message_port, 4224 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4225 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4226 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4227 .stats_get_strings = mv88e6095_stats_get_strings, 4228 .stats_get_stat = mv88e6095_stats_get_stat, 4229 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4230 .set_egress_port = mv88e6095_g1_set_egress_port, 4231 .watchdog_ops = &mv88e6097_watchdog_ops, 4232 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4233 .pot_clear = mv88e6xxx_g2_pot_clear, 4234 .ppu_enable = mv88e6185_g1_ppu_enable, 4235 .ppu_disable = mv88e6185_g1_ppu_disable, 4236 .reset = mv88e6185_g1_reset, 4237 .rmu_disable = mv88e6085_g1_rmu_disable, 4238 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4239 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4240 .stu_getnext = mv88e6352_g1_stu_getnext, 4241 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4242 .phylink_get_caps = mv88e6185_phylink_get_caps, 4243 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4244 }; 4245 4246 static const struct mv88e6xxx_ops mv88e6095_ops = { 4247 /* MV88E6XXX_FAMILY_6095 */ 4248 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4249 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4250 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4251 .phy_read = mv88e6185_phy_ppu_read, 4252 .phy_write = mv88e6185_phy_ppu_write, 4253 .port_set_link = mv88e6xxx_port_set_link, 4254 .port_sync_link = mv88e6185_port_sync_link, 4255 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4256 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4257 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4258 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4259 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4260 .port_get_cmode = mv88e6185_port_get_cmode, 4261 .port_setup_message_port = mv88e6xxx_setup_message_port, 4262 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4263 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4264 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4265 .stats_get_strings = mv88e6095_stats_get_strings, 4266 .stats_get_stat = mv88e6095_stats_get_stat, 4267 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4268 .ppu_enable = mv88e6185_g1_ppu_enable, 4269 .ppu_disable = mv88e6185_g1_ppu_disable, 4270 .reset = mv88e6185_g1_reset, 4271 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4272 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4273 .phylink_get_caps = mv88e6095_phylink_get_caps, 4274 .pcs_ops = &mv88e6185_pcs_ops, 4275 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4276 }; 4277 4278 static const struct mv88e6xxx_ops mv88e6097_ops = { 4279 /* MV88E6XXX_FAMILY_6097 */ 4280 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4281 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4282 .irl_init_all = mv88e6352_g2_irl_init_all, 4283 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4284 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4285 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4286 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4287 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4288 .port_set_link = mv88e6xxx_port_set_link, 4289 .port_sync_link = mv88e6185_port_sync_link, 4290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4291 .port_tag_remap = mv88e6095_port_tag_remap, 4292 .port_set_policy = mv88e6352_port_set_policy, 4293 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4294 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4295 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4296 .port_set_ether_type = mv88e6351_port_set_ether_type, 4297 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4298 .port_pause_limit = mv88e6097_port_pause_limit, 4299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4301 .port_get_cmode = mv88e6185_port_get_cmode, 4302 .port_setup_message_port = mv88e6xxx_setup_message_port, 4303 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4304 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4305 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4306 .stats_get_strings = mv88e6095_stats_get_strings, 4307 .stats_get_stat = mv88e6095_stats_get_stat, 4308 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4309 .set_egress_port = mv88e6095_g1_set_egress_port, 4310 .watchdog_ops = &mv88e6097_watchdog_ops, 4311 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4312 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4313 .pot_clear = mv88e6xxx_g2_pot_clear, 4314 .reset = mv88e6352_g1_reset, 4315 .rmu_disable = mv88e6085_g1_rmu_disable, 4316 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4317 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4318 .phylink_get_caps = mv88e6095_phylink_get_caps, 4319 .pcs_ops = &mv88e6185_pcs_ops, 4320 .stu_getnext = mv88e6352_g1_stu_getnext, 4321 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4322 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4323 }; 4324 4325 static const struct mv88e6xxx_ops mv88e6123_ops = { 4326 /* MV88E6XXX_FAMILY_6165 */ 4327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4328 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4329 .irl_init_all = mv88e6352_g2_irl_init_all, 4330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4331 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4332 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4333 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4334 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4335 .port_set_link = mv88e6xxx_port_set_link, 4336 .port_sync_link = mv88e6xxx_port_sync_link, 4337 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4338 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4339 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4340 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4341 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4342 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4343 .port_get_cmode = mv88e6185_port_get_cmode, 4344 .port_setup_message_port = mv88e6xxx_setup_message_port, 4345 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4346 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4347 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4348 .stats_get_strings = mv88e6095_stats_get_strings, 4349 .stats_get_stat = mv88e6095_stats_get_stat, 4350 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4351 .set_egress_port = mv88e6095_g1_set_egress_port, 4352 .watchdog_ops = &mv88e6097_watchdog_ops, 4353 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4354 .pot_clear = mv88e6xxx_g2_pot_clear, 4355 .reset = mv88e6352_g1_reset, 4356 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4357 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4358 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4359 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4360 .stu_getnext = mv88e6352_g1_stu_getnext, 4361 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4362 .phylink_get_caps = mv88e6185_phylink_get_caps, 4363 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4364 }; 4365 4366 static const struct mv88e6xxx_ops mv88e6131_ops = { 4367 /* MV88E6XXX_FAMILY_6185 */ 4368 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4369 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4370 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4371 .phy_read = mv88e6185_phy_ppu_read, 4372 .phy_write = mv88e6185_phy_ppu_write, 4373 .port_set_link = mv88e6xxx_port_set_link, 4374 .port_sync_link = mv88e6xxx_port_sync_link, 4375 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4376 .port_tag_remap = mv88e6095_port_tag_remap, 4377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4378 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4379 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4380 .port_set_ether_type = mv88e6351_port_set_ether_type, 4381 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4382 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4383 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4384 .port_pause_limit = mv88e6097_port_pause_limit, 4385 .port_set_pause = mv88e6185_port_set_pause, 4386 .port_get_cmode = mv88e6185_port_get_cmode, 4387 .port_setup_message_port = mv88e6xxx_setup_message_port, 4388 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4389 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4390 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4391 .stats_get_strings = mv88e6095_stats_get_strings, 4392 .stats_get_stat = mv88e6095_stats_get_stat, 4393 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4394 .set_egress_port = mv88e6095_g1_set_egress_port, 4395 .watchdog_ops = &mv88e6097_watchdog_ops, 4396 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4397 .ppu_enable = mv88e6185_g1_ppu_enable, 4398 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4399 .ppu_disable = mv88e6185_g1_ppu_disable, 4400 .reset = mv88e6185_g1_reset, 4401 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4402 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4403 .phylink_get_caps = mv88e6185_phylink_get_caps, 4404 }; 4405 4406 static const struct mv88e6xxx_ops mv88e6141_ops = { 4407 /* MV88E6XXX_FAMILY_6341 */ 4408 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4409 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4410 .irl_init_all = mv88e6352_g2_irl_init_all, 4411 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4412 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4414 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4415 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4416 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4417 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4418 .port_set_link = mv88e6xxx_port_set_link, 4419 .port_sync_link = mv88e6xxx_port_sync_link, 4420 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4421 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4422 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4423 .port_tag_remap = mv88e6095_port_tag_remap, 4424 .port_set_policy = mv88e6352_port_set_policy, 4425 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4426 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4427 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4428 .port_set_ether_type = mv88e6351_port_set_ether_type, 4429 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4430 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4431 .port_pause_limit = mv88e6097_port_pause_limit, 4432 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4433 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4434 .port_get_cmode = mv88e6352_port_get_cmode, 4435 .port_set_cmode = mv88e6341_port_set_cmode, 4436 .port_setup_message_port = mv88e6xxx_setup_message_port, 4437 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4438 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4439 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4440 .stats_get_strings = mv88e6320_stats_get_strings, 4441 .stats_get_stat = mv88e6390_stats_get_stat, 4442 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4443 .set_egress_port = mv88e6390_g1_set_egress_port, 4444 .watchdog_ops = &mv88e6390_watchdog_ops, 4445 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4446 .pot_clear = mv88e6xxx_g2_pot_clear, 4447 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4448 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4449 .reset = mv88e6352_g1_reset, 4450 .rmu_disable = mv88e6390_g1_rmu_disable, 4451 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4452 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4453 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4454 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4455 .stu_getnext = mv88e6352_g1_stu_getnext, 4456 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4457 .serdes_get_lane = mv88e6341_serdes_get_lane, 4458 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4459 .gpio_ops = &mv88e6352_gpio_ops, 4460 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4461 .serdes_get_strings = mv88e6390_serdes_get_strings, 4462 .serdes_get_stats = mv88e6390_serdes_get_stats, 4463 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4464 .serdes_get_regs = mv88e6390_serdes_get_regs, 4465 .phylink_get_caps = mv88e6341_phylink_get_caps, 4466 .pcs_ops = &mv88e6390_pcs_ops, 4467 }; 4468 4469 static const struct mv88e6xxx_ops mv88e6161_ops = { 4470 /* MV88E6XXX_FAMILY_6165 */ 4471 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4472 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4473 .irl_init_all = mv88e6352_g2_irl_init_all, 4474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4475 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4476 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4477 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4478 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4479 .port_set_link = mv88e6xxx_port_set_link, 4480 .port_sync_link = mv88e6xxx_port_sync_link, 4481 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4482 .port_tag_remap = mv88e6095_port_tag_remap, 4483 .port_set_policy = mv88e6352_port_set_policy, 4484 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4485 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4486 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4487 .port_set_ether_type = mv88e6351_port_set_ether_type, 4488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4489 .port_pause_limit = mv88e6097_port_pause_limit, 4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4492 .port_get_cmode = mv88e6185_port_get_cmode, 4493 .port_setup_message_port = mv88e6xxx_setup_message_port, 4494 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4497 .stats_get_strings = mv88e6095_stats_get_strings, 4498 .stats_get_stat = mv88e6095_stats_get_stat, 4499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4500 .set_egress_port = mv88e6095_g1_set_egress_port, 4501 .watchdog_ops = &mv88e6097_watchdog_ops, 4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4503 .pot_clear = mv88e6xxx_g2_pot_clear, 4504 .reset = mv88e6352_g1_reset, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .stu_getnext = mv88e6352_g1_stu_getnext, 4510 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4511 .avb_ops = &mv88e6165_avb_ops, 4512 .ptp_ops = &mv88e6165_ptp_ops, 4513 .phylink_get_caps = mv88e6185_phylink_get_caps, 4514 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4515 }; 4516 4517 static const struct mv88e6xxx_ops mv88e6165_ops = { 4518 /* MV88E6XXX_FAMILY_6165 */ 4519 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4520 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4521 .irl_init_all = mv88e6352_g2_irl_init_all, 4522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4523 .phy_read = mv88e6165_phy_read, 4524 .phy_write = mv88e6165_phy_write, 4525 .port_set_link = mv88e6xxx_port_set_link, 4526 .port_sync_link = mv88e6xxx_port_sync_link, 4527 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4528 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4529 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4530 .port_get_cmode = mv88e6185_port_get_cmode, 4531 .port_setup_message_port = mv88e6xxx_setup_message_port, 4532 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4533 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4534 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4535 .stats_get_strings = mv88e6095_stats_get_strings, 4536 .stats_get_stat = mv88e6095_stats_get_stat, 4537 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4538 .set_egress_port = mv88e6095_g1_set_egress_port, 4539 .watchdog_ops = &mv88e6097_watchdog_ops, 4540 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4541 .pot_clear = mv88e6xxx_g2_pot_clear, 4542 .reset = mv88e6352_g1_reset, 4543 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4544 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4545 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4546 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4547 .stu_getnext = mv88e6352_g1_stu_getnext, 4548 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4549 .avb_ops = &mv88e6165_avb_ops, 4550 .ptp_ops = &mv88e6165_ptp_ops, 4551 .phylink_get_caps = mv88e6185_phylink_get_caps, 4552 }; 4553 4554 static const struct mv88e6xxx_ops mv88e6171_ops = { 4555 /* MV88E6XXX_FAMILY_6351 */ 4556 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4557 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4558 .irl_init_all = mv88e6352_g2_irl_init_all, 4559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4560 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4561 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4562 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4563 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4564 .port_set_link = mv88e6xxx_port_set_link, 4565 .port_sync_link = mv88e6xxx_port_sync_link, 4566 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4567 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4568 .port_tag_remap = mv88e6095_port_tag_remap, 4569 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4570 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4571 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4572 .port_set_ether_type = mv88e6351_port_set_ether_type, 4573 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4574 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4575 .port_pause_limit = mv88e6097_port_pause_limit, 4576 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4577 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4578 .port_get_cmode = mv88e6352_port_get_cmode, 4579 .port_setup_message_port = mv88e6xxx_setup_message_port, 4580 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4581 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4582 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4583 .stats_get_strings = mv88e6095_stats_get_strings, 4584 .stats_get_stat = mv88e6095_stats_get_stat, 4585 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4586 .set_egress_port = mv88e6095_g1_set_egress_port, 4587 .watchdog_ops = &mv88e6097_watchdog_ops, 4588 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4589 .pot_clear = mv88e6xxx_g2_pot_clear, 4590 .reset = mv88e6352_g1_reset, 4591 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4592 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4593 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4595 .stu_getnext = mv88e6352_g1_stu_getnext, 4596 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4597 .phylink_get_caps = mv88e6351_phylink_get_caps, 4598 }; 4599 4600 static const struct mv88e6xxx_ops mv88e6172_ops = { 4601 /* MV88E6XXX_FAMILY_6352 */ 4602 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4603 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4604 .irl_init_all = mv88e6352_g2_irl_init_all, 4605 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4606 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4608 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4609 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4610 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4611 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4612 .port_set_link = mv88e6xxx_port_set_link, 4613 .port_sync_link = mv88e6xxx_port_sync_link, 4614 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4615 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4616 .port_tag_remap = mv88e6095_port_tag_remap, 4617 .port_set_policy = mv88e6352_port_set_policy, 4618 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4619 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4620 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4621 .port_set_ether_type = mv88e6351_port_set_ether_type, 4622 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4623 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4624 .port_pause_limit = mv88e6097_port_pause_limit, 4625 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4626 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4627 .port_get_cmode = mv88e6352_port_get_cmode, 4628 .port_setup_leds = mv88e6xxx_port_setup_leds, 4629 .port_setup_message_port = mv88e6xxx_setup_message_port, 4630 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4631 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4632 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4633 .stats_get_strings = mv88e6095_stats_get_strings, 4634 .stats_get_stat = mv88e6095_stats_get_stat, 4635 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4636 .set_egress_port = mv88e6095_g1_set_egress_port, 4637 .watchdog_ops = &mv88e6097_watchdog_ops, 4638 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4639 .pot_clear = mv88e6xxx_g2_pot_clear, 4640 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4641 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4642 .reset = mv88e6352_g1_reset, 4643 .rmu_disable = mv88e6352_g1_rmu_disable, 4644 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4645 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4646 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4647 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4648 .stu_getnext = mv88e6352_g1_stu_getnext, 4649 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4650 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4651 .serdes_get_regs = mv88e6352_serdes_get_regs, 4652 .gpio_ops = &mv88e6352_gpio_ops, 4653 .phylink_get_caps = mv88e6352_phylink_get_caps, 4654 .pcs_ops = &mv88e6352_pcs_ops, 4655 }; 4656 4657 static const struct mv88e6xxx_ops mv88e6175_ops = { 4658 /* MV88E6XXX_FAMILY_6351 */ 4659 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4660 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4661 .irl_init_all = mv88e6352_g2_irl_init_all, 4662 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4663 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4664 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4665 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4666 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4667 .port_set_link = mv88e6xxx_port_set_link, 4668 .port_sync_link = mv88e6xxx_port_sync_link, 4669 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4670 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4671 .port_tag_remap = mv88e6095_port_tag_remap, 4672 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4673 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4674 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4675 .port_set_ether_type = mv88e6351_port_set_ether_type, 4676 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4677 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4678 .port_pause_limit = mv88e6097_port_pause_limit, 4679 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4680 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4681 .port_get_cmode = mv88e6352_port_get_cmode, 4682 .port_setup_message_port = mv88e6xxx_setup_message_port, 4683 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4684 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4685 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4686 .stats_get_strings = mv88e6095_stats_get_strings, 4687 .stats_get_stat = mv88e6095_stats_get_stat, 4688 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4689 .set_egress_port = mv88e6095_g1_set_egress_port, 4690 .watchdog_ops = &mv88e6097_watchdog_ops, 4691 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4692 .pot_clear = mv88e6xxx_g2_pot_clear, 4693 .reset = mv88e6352_g1_reset, 4694 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4695 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4696 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4697 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4698 .stu_getnext = mv88e6352_g1_stu_getnext, 4699 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4700 .phylink_get_caps = mv88e6351_phylink_get_caps, 4701 }; 4702 4703 static const struct mv88e6xxx_ops mv88e6176_ops = { 4704 /* MV88E6XXX_FAMILY_6352 */ 4705 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4706 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4707 .irl_init_all = mv88e6352_g2_irl_init_all, 4708 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4709 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4710 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4711 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4712 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4713 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4714 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4715 .port_set_link = mv88e6xxx_port_set_link, 4716 .port_sync_link = mv88e6xxx_port_sync_link, 4717 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4718 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4719 .port_tag_remap = mv88e6095_port_tag_remap, 4720 .port_set_policy = mv88e6352_port_set_policy, 4721 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4722 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4723 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4724 .port_set_ether_type = mv88e6351_port_set_ether_type, 4725 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4726 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4727 .port_pause_limit = mv88e6097_port_pause_limit, 4728 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4729 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4730 .port_get_cmode = mv88e6352_port_get_cmode, 4731 .port_setup_leds = mv88e6xxx_port_setup_leds, 4732 .port_setup_message_port = mv88e6xxx_setup_message_port, 4733 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4734 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4735 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4736 .stats_get_strings = mv88e6095_stats_get_strings, 4737 .stats_get_stat = mv88e6095_stats_get_stat, 4738 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4739 .set_egress_port = mv88e6095_g1_set_egress_port, 4740 .watchdog_ops = &mv88e6097_watchdog_ops, 4741 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4742 .pot_clear = mv88e6xxx_g2_pot_clear, 4743 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4744 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4745 .reset = mv88e6352_g1_reset, 4746 .rmu_disable = mv88e6352_g1_rmu_disable, 4747 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4748 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4749 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4750 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4751 .stu_getnext = mv88e6352_g1_stu_getnext, 4752 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4753 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4754 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4755 .serdes_get_regs = mv88e6352_serdes_get_regs, 4756 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4757 .gpio_ops = &mv88e6352_gpio_ops, 4758 .phylink_get_caps = mv88e6352_phylink_get_caps, 4759 .pcs_ops = &mv88e6352_pcs_ops, 4760 }; 4761 4762 static const struct mv88e6xxx_ops mv88e6185_ops = { 4763 /* MV88E6XXX_FAMILY_6185 */ 4764 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4765 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4766 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4767 .phy_read = mv88e6185_phy_ppu_read, 4768 .phy_write = mv88e6185_phy_ppu_write, 4769 .port_set_link = mv88e6xxx_port_set_link, 4770 .port_sync_link = mv88e6185_port_sync_link, 4771 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4772 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4773 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4774 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4775 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4776 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4777 .port_set_pause = mv88e6185_port_set_pause, 4778 .port_get_cmode = mv88e6185_port_get_cmode, 4779 .port_setup_message_port = mv88e6xxx_setup_message_port, 4780 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4781 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4782 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4783 .stats_get_strings = mv88e6095_stats_get_strings, 4784 .stats_get_stat = mv88e6095_stats_get_stat, 4785 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4786 .set_egress_port = mv88e6095_g1_set_egress_port, 4787 .watchdog_ops = &mv88e6097_watchdog_ops, 4788 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4789 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4790 .ppu_enable = mv88e6185_g1_ppu_enable, 4791 .ppu_disable = mv88e6185_g1_ppu_disable, 4792 .reset = mv88e6185_g1_reset, 4793 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4794 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4795 .phylink_get_caps = mv88e6185_phylink_get_caps, 4796 .pcs_ops = &mv88e6185_pcs_ops, 4797 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4798 }; 4799 4800 static const struct mv88e6xxx_ops mv88e6190_ops = { 4801 /* MV88E6XXX_FAMILY_6390 */ 4802 .setup_errata = mv88e6390_setup_errata, 4803 .irl_init_all = mv88e6390_g2_irl_init_all, 4804 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4805 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4807 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4808 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4809 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4810 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4811 .port_set_link = mv88e6xxx_port_set_link, 4812 .port_sync_link = mv88e6xxx_port_sync_link, 4813 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4814 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4815 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4816 .port_tag_remap = mv88e6390_port_tag_remap, 4817 .port_set_policy = mv88e6352_port_set_policy, 4818 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4819 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4820 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4821 .port_set_ether_type = mv88e6351_port_set_ether_type, 4822 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4823 .port_pause_limit = mv88e6390_port_pause_limit, 4824 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4825 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4826 .port_get_cmode = mv88e6352_port_get_cmode, 4827 .port_set_cmode = mv88e6390_port_set_cmode, 4828 .port_setup_message_port = mv88e6xxx_setup_message_port, 4829 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4830 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4831 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4832 .stats_get_strings = mv88e6320_stats_get_strings, 4833 .stats_get_stat = mv88e6390_stats_get_stat, 4834 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4835 .set_egress_port = mv88e6390_g1_set_egress_port, 4836 .watchdog_ops = &mv88e6390_watchdog_ops, 4837 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4838 .pot_clear = mv88e6xxx_g2_pot_clear, 4839 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4840 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4841 .reset = mv88e6352_g1_reset, 4842 .rmu_disable = mv88e6390_g1_rmu_disable, 4843 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4844 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4845 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4846 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4847 .stu_getnext = mv88e6390_g1_stu_getnext, 4848 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4849 .serdes_get_lane = mv88e6390_serdes_get_lane, 4850 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4851 .serdes_get_strings = mv88e6390_serdes_get_strings, 4852 .serdes_get_stats = mv88e6390_serdes_get_stats, 4853 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4854 .serdes_get_regs = mv88e6390_serdes_get_regs, 4855 .gpio_ops = &mv88e6352_gpio_ops, 4856 .phylink_get_caps = mv88e6390_phylink_get_caps, 4857 .pcs_ops = &mv88e6390_pcs_ops, 4858 }; 4859 4860 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4861 /* MV88E6XXX_FAMILY_6390 */ 4862 .setup_errata = mv88e6390_setup_errata, 4863 .irl_init_all = mv88e6390_g2_irl_init_all, 4864 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4865 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4866 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4867 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4868 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4869 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4870 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4871 .port_set_link = mv88e6xxx_port_set_link, 4872 .port_sync_link = mv88e6xxx_port_sync_link, 4873 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4874 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4875 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4876 .port_tag_remap = mv88e6390_port_tag_remap, 4877 .port_set_policy = mv88e6352_port_set_policy, 4878 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4879 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4880 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4881 .port_set_ether_type = mv88e6351_port_set_ether_type, 4882 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4883 .port_pause_limit = mv88e6390_port_pause_limit, 4884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4886 .port_get_cmode = mv88e6352_port_get_cmode, 4887 .port_set_cmode = mv88e6390x_port_set_cmode, 4888 .port_setup_message_port = mv88e6xxx_setup_message_port, 4889 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4890 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4891 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4892 .stats_get_strings = mv88e6320_stats_get_strings, 4893 .stats_get_stat = mv88e6390_stats_get_stat, 4894 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4895 .set_egress_port = mv88e6390_g1_set_egress_port, 4896 .watchdog_ops = &mv88e6390_watchdog_ops, 4897 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4898 .pot_clear = mv88e6xxx_g2_pot_clear, 4899 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4900 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4901 .reset = mv88e6352_g1_reset, 4902 .rmu_disable = mv88e6390_g1_rmu_disable, 4903 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4904 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4905 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4906 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4907 .stu_getnext = mv88e6390_g1_stu_getnext, 4908 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4909 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4910 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4911 .serdes_get_strings = mv88e6390_serdes_get_strings, 4912 .serdes_get_stats = mv88e6390_serdes_get_stats, 4913 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4914 .serdes_get_regs = mv88e6390_serdes_get_regs, 4915 .gpio_ops = &mv88e6352_gpio_ops, 4916 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4917 .pcs_ops = &mv88e6390_pcs_ops, 4918 }; 4919 4920 static const struct mv88e6xxx_ops mv88e6191_ops = { 4921 /* MV88E6XXX_FAMILY_6390 */ 4922 .setup_errata = mv88e6390_setup_errata, 4923 .irl_init_all = mv88e6390_g2_irl_init_all, 4924 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4925 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4926 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4927 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4928 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4929 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4930 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4931 .port_set_link = mv88e6xxx_port_set_link, 4932 .port_sync_link = mv88e6xxx_port_sync_link, 4933 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4934 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4935 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4936 .port_tag_remap = mv88e6390_port_tag_remap, 4937 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4938 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4939 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4940 .port_set_ether_type = mv88e6351_port_set_ether_type, 4941 .port_pause_limit = mv88e6390_port_pause_limit, 4942 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4943 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4944 .port_get_cmode = mv88e6352_port_get_cmode, 4945 .port_set_cmode = mv88e6390_port_set_cmode, 4946 .port_setup_message_port = mv88e6xxx_setup_message_port, 4947 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4948 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4949 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4950 .stats_get_strings = mv88e6320_stats_get_strings, 4951 .stats_get_stat = mv88e6390_stats_get_stat, 4952 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4953 .set_egress_port = mv88e6390_g1_set_egress_port, 4954 .watchdog_ops = &mv88e6390_watchdog_ops, 4955 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4956 .pot_clear = mv88e6xxx_g2_pot_clear, 4957 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4958 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4959 .reset = mv88e6352_g1_reset, 4960 .rmu_disable = mv88e6390_g1_rmu_disable, 4961 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4962 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4963 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4964 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4965 .stu_getnext = mv88e6390_g1_stu_getnext, 4966 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4967 .serdes_get_lane = mv88e6390_serdes_get_lane, 4968 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4969 .serdes_get_strings = mv88e6390_serdes_get_strings, 4970 .serdes_get_stats = mv88e6390_serdes_get_stats, 4971 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4972 .serdes_get_regs = mv88e6390_serdes_get_regs, 4973 .avb_ops = &mv88e6390_avb_ops, 4974 .ptp_ops = &mv88e6352_ptp_ops, 4975 .phylink_get_caps = mv88e6390_phylink_get_caps, 4976 .pcs_ops = &mv88e6390_pcs_ops, 4977 }; 4978 4979 static const struct mv88e6xxx_ops mv88e6240_ops = { 4980 /* MV88E6XXX_FAMILY_6352 */ 4981 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4982 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4983 .irl_init_all = mv88e6352_g2_irl_init_all, 4984 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4985 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4986 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4987 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4988 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4989 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4990 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4991 .port_set_link = mv88e6xxx_port_set_link, 4992 .port_sync_link = mv88e6xxx_port_sync_link, 4993 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4994 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4995 .port_tag_remap = mv88e6095_port_tag_remap, 4996 .port_set_policy = mv88e6352_port_set_policy, 4997 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4998 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4999 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5000 .port_set_ether_type = mv88e6351_port_set_ether_type, 5001 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5002 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5003 .port_pause_limit = mv88e6097_port_pause_limit, 5004 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5005 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5006 .port_get_cmode = mv88e6352_port_get_cmode, 5007 .port_setup_leds = mv88e6xxx_port_setup_leds, 5008 .port_setup_message_port = mv88e6xxx_setup_message_port, 5009 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5010 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5011 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5012 .stats_get_strings = mv88e6095_stats_get_strings, 5013 .stats_get_stat = mv88e6095_stats_get_stat, 5014 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5015 .set_egress_port = mv88e6095_g1_set_egress_port, 5016 .watchdog_ops = &mv88e6097_watchdog_ops, 5017 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5018 .pot_clear = mv88e6xxx_g2_pot_clear, 5019 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5020 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5021 .reset = mv88e6352_g1_reset, 5022 .rmu_disable = mv88e6352_g1_rmu_disable, 5023 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5024 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5025 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5026 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5027 .stu_getnext = mv88e6352_g1_stu_getnext, 5028 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5029 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5030 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5031 .serdes_get_regs = mv88e6352_serdes_get_regs, 5032 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5033 .gpio_ops = &mv88e6352_gpio_ops, 5034 .avb_ops = &mv88e6352_avb_ops, 5035 .ptp_ops = &mv88e6352_ptp_ops, 5036 .phylink_get_caps = mv88e6352_phylink_get_caps, 5037 .pcs_ops = &mv88e6352_pcs_ops, 5038 }; 5039 5040 static const struct mv88e6xxx_ops mv88e6250_ops = { 5041 /* MV88E6XXX_FAMILY_6250 */ 5042 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5043 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5044 .irl_init_all = mv88e6352_g2_irl_init_all, 5045 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5046 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5047 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5048 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5049 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5050 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5051 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5052 .port_set_link = mv88e6xxx_port_set_link, 5053 .port_sync_link = mv88e6xxx_port_sync_link, 5054 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5055 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5056 .port_tag_remap = mv88e6095_port_tag_remap, 5057 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5058 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5059 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5060 .port_set_ether_type = mv88e6351_port_set_ether_type, 5061 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5062 .port_pause_limit = mv88e6097_port_pause_limit, 5063 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5064 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5065 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5066 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5067 .stats_get_strings = mv88e6250_stats_get_strings, 5068 .stats_get_stat = mv88e6250_stats_get_stat, 5069 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5070 .set_egress_port = mv88e6095_g1_set_egress_port, 5071 .watchdog_ops = &mv88e6250_watchdog_ops, 5072 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5073 .pot_clear = mv88e6xxx_g2_pot_clear, 5074 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5075 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5076 .reset = mv88e6250_g1_reset, 5077 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5078 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5079 .avb_ops = &mv88e6352_avb_ops, 5080 .ptp_ops = &mv88e6250_ptp_ops, 5081 .phylink_get_caps = mv88e6250_phylink_get_caps, 5082 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5083 }; 5084 5085 static const struct mv88e6xxx_ops mv88e6290_ops = { 5086 /* MV88E6XXX_FAMILY_6390 */ 5087 .setup_errata = mv88e6390_setup_errata, 5088 .irl_init_all = mv88e6390_g2_irl_init_all, 5089 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5090 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5091 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5092 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5093 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5094 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5095 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5096 .port_set_link = mv88e6xxx_port_set_link, 5097 .port_sync_link = mv88e6xxx_port_sync_link, 5098 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5099 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5100 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5101 .port_tag_remap = mv88e6390_port_tag_remap, 5102 .port_set_policy = mv88e6352_port_set_policy, 5103 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5104 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5105 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5106 .port_set_ether_type = mv88e6351_port_set_ether_type, 5107 .port_pause_limit = mv88e6390_port_pause_limit, 5108 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5109 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5110 .port_get_cmode = mv88e6352_port_get_cmode, 5111 .port_set_cmode = mv88e6390_port_set_cmode, 5112 .port_setup_message_port = mv88e6xxx_setup_message_port, 5113 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5114 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5115 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5116 .stats_get_strings = mv88e6320_stats_get_strings, 5117 .stats_get_stat = mv88e6390_stats_get_stat, 5118 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5119 .set_egress_port = mv88e6390_g1_set_egress_port, 5120 .watchdog_ops = &mv88e6390_watchdog_ops, 5121 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5122 .pot_clear = mv88e6xxx_g2_pot_clear, 5123 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5124 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5125 .reset = mv88e6352_g1_reset, 5126 .rmu_disable = mv88e6390_g1_rmu_disable, 5127 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5128 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5129 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5130 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5131 .stu_getnext = mv88e6390_g1_stu_getnext, 5132 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5133 .serdes_get_lane = mv88e6390_serdes_get_lane, 5134 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5135 .serdes_get_strings = mv88e6390_serdes_get_strings, 5136 .serdes_get_stats = mv88e6390_serdes_get_stats, 5137 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5138 .serdes_get_regs = mv88e6390_serdes_get_regs, 5139 .gpio_ops = &mv88e6352_gpio_ops, 5140 .avb_ops = &mv88e6390_avb_ops, 5141 .ptp_ops = &mv88e6390_ptp_ops, 5142 .phylink_get_caps = mv88e6390_phylink_get_caps, 5143 .pcs_ops = &mv88e6390_pcs_ops, 5144 }; 5145 5146 static const struct mv88e6xxx_ops mv88e6320_ops = { 5147 /* MV88E6XXX_FAMILY_6320 */ 5148 .setup_errata = mv88e6320_setup_errata, 5149 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5150 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5151 .irl_init_all = mv88e6352_g2_irl_init_all, 5152 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5153 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5154 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5155 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5156 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5157 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5158 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5159 .port_set_link = mv88e6xxx_port_set_link, 5160 .port_sync_link = mv88e6xxx_port_sync_link, 5161 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5162 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5163 .port_tag_remap = mv88e6095_port_tag_remap, 5164 .port_set_policy = mv88e6352_port_set_policy, 5165 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5166 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5167 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5168 .port_set_ether_type = mv88e6351_port_set_ether_type, 5169 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5170 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5171 .port_pause_limit = mv88e6097_port_pause_limit, 5172 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5173 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5174 .port_get_cmode = mv88e6352_port_get_cmode, 5175 .port_setup_message_port = mv88e6xxx_setup_message_port, 5176 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5177 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5178 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5179 .stats_get_strings = mv88e6320_stats_get_strings, 5180 .stats_get_stat = mv88e6320_stats_get_stat, 5181 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5182 .set_egress_port = mv88e6095_g1_set_egress_port, 5183 .watchdog_ops = &mv88e6390_watchdog_ops, 5184 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5185 .pot_clear = mv88e6xxx_g2_pot_clear, 5186 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5187 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5188 .reset = mv88e6352_g1_reset, 5189 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5190 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5191 .stu_getnext = mv88e6352_g1_stu_getnext, 5192 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5193 .gpio_ops = &mv88e6352_gpio_ops, 5194 .avb_ops = &mv88e6352_avb_ops, 5195 .ptp_ops = &mv88e6352_ptp_ops, 5196 .phylink_get_caps = mv88e632x_phylink_get_caps, 5197 }; 5198 5199 static const struct mv88e6xxx_ops mv88e6321_ops = { 5200 /* MV88E6XXX_FAMILY_6320 */ 5201 .setup_errata = mv88e6320_setup_errata, 5202 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5203 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5204 .irl_init_all = mv88e6352_g2_irl_init_all, 5205 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5206 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5207 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5208 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5209 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5210 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5211 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5212 .port_set_link = mv88e6xxx_port_set_link, 5213 .port_sync_link = mv88e6xxx_port_sync_link, 5214 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5215 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5216 .port_tag_remap = mv88e6095_port_tag_remap, 5217 .port_set_policy = mv88e6352_port_set_policy, 5218 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5219 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5220 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5221 .port_set_ether_type = mv88e6351_port_set_ether_type, 5222 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5223 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5224 .port_pause_limit = mv88e6097_port_pause_limit, 5225 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5226 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5227 .port_get_cmode = mv88e6352_port_get_cmode, 5228 .port_setup_message_port = mv88e6xxx_setup_message_port, 5229 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5230 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5231 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5232 .stats_get_strings = mv88e6320_stats_get_strings, 5233 .stats_get_stat = mv88e6320_stats_get_stat, 5234 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5235 .set_egress_port = mv88e6095_g1_set_egress_port, 5236 .watchdog_ops = &mv88e6390_watchdog_ops, 5237 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5238 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5239 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5240 .reset = mv88e6352_g1_reset, 5241 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5242 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5243 .stu_getnext = mv88e6352_g1_stu_getnext, 5244 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5245 .gpio_ops = &mv88e6352_gpio_ops, 5246 .avb_ops = &mv88e6352_avb_ops, 5247 .ptp_ops = &mv88e6352_ptp_ops, 5248 .phylink_get_caps = mv88e632x_phylink_get_caps, 5249 }; 5250 5251 static const struct mv88e6xxx_ops mv88e6341_ops = { 5252 /* MV88E6XXX_FAMILY_6341 */ 5253 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5254 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5255 .irl_init_all = mv88e6352_g2_irl_init_all, 5256 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5257 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5259 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5260 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5261 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5262 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5263 .port_set_link = mv88e6xxx_port_set_link, 5264 .port_sync_link = mv88e6xxx_port_sync_link, 5265 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5266 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5267 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5268 .port_tag_remap = mv88e6095_port_tag_remap, 5269 .port_set_policy = mv88e6352_port_set_policy, 5270 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5271 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5272 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5273 .port_set_ether_type = mv88e6351_port_set_ether_type, 5274 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5275 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5276 .port_pause_limit = mv88e6097_port_pause_limit, 5277 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5278 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5279 .port_get_cmode = mv88e6352_port_get_cmode, 5280 .port_set_cmode = mv88e6341_port_set_cmode, 5281 .port_setup_message_port = mv88e6xxx_setup_message_port, 5282 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5283 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5284 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5285 .stats_get_strings = mv88e6320_stats_get_strings, 5286 .stats_get_stat = mv88e6390_stats_get_stat, 5287 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5288 .set_egress_port = mv88e6390_g1_set_egress_port, 5289 .watchdog_ops = &mv88e6390_watchdog_ops, 5290 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5291 .pot_clear = mv88e6xxx_g2_pot_clear, 5292 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5293 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5294 .reset = mv88e6352_g1_reset, 5295 .rmu_disable = mv88e6390_g1_rmu_disable, 5296 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5297 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5298 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5299 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5300 .stu_getnext = mv88e6352_g1_stu_getnext, 5301 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5302 .serdes_get_lane = mv88e6341_serdes_get_lane, 5303 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5304 .gpio_ops = &mv88e6352_gpio_ops, 5305 .avb_ops = &mv88e6390_avb_ops, 5306 .ptp_ops = &mv88e6352_ptp_ops, 5307 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5308 .serdes_get_strings = mv88e6390_serdes_get_strings, 5309 .serdes_get_stats = mv88e6390_serdes_get_stats, 5310 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5311 .serdes_get_regs = mv88e6390_serdes_get_regs, 5312 .phylink_get_caps = mv88e6341_phylink_get_caps, 5313 .pcs_ops = &mv88e6390_pcs_ops, 5314 }; 5315 5316 static const struct mv88e6xxx_ops mv88e6350_ops = { 5317 /* MV88E6XXX_FAMILY_6351 */ 5318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5319 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5320 .irl_init_all = mv88e6352_g2_irl_init_all, 5321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5322 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5323 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5324 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5325 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5326 .port_set_link = mv88e6xxx_port_set_link, 5327 .port_sync_link = mv88e6xxx_port_sync_link, 5328 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5329 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5330 .port_tag_remap = mv88e6095_port_tag_remap, 5331 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5332 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5333 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5334 .port_set_ether_type = mv88e6351_port_set_ether_type, 5335 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5336 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5337 .port_pause_limit = mv88e6097_port_pause_limit, 5338 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5339 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5340 .port_get_cmode = mv88e6352_port_get_cmode, 5341 .port_setup_message_port = mv88e6xxx_setup_message_port, 5342 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5343 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5344 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5345 .stats_get_strings = mv88e6095_stats_get_strings, 5346 .stats_get_stat = mv88e6095_stats_get_stat, 5347 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5348 .set_egress_port = mv88e6095_g1_set_egress_port, 5349 .watchdog_ops = &mv88e6097_watchdog_ops, 5350 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5351 .pot_clear = mv88e6xxx_g2_pot_clear, 5352 .reset = mv88e6352_g1_reset, 5353 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5354 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5355 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5357 .stu_getnext = mv88e6352_g1_stu_getnext, 5358 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5359 .phylink_get_caps = mv88e6351_phylink_get_caps, 5360 }; 5361 5362 static const struct mv88e6xxx_ops mv88e6351_ops = { 5363 /* MV88E6XXX_FAMILY_6351 */ 5364 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5365 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5366 .irl_init_all = mv88e6352_g2_irl_init_all, 5367 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5368 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5369 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5370 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5371 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5372 .port_set_link = mv88e6xxx_port_set_link, 5373 .port_sync_link = mv88e6xxx_port_sync_link, 5374 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5375 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5376 .port_tag_remap = mv88e6095_port_tag_remap, 5377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5380 .port_set_ether_type = mv88e6351_port_set_ether_type, 5381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5383 .port_pause_limit = mv88e6097_port_pause_limit, 5384 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5385 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5386 .port_get_cmode = mv88e6352_port_get_cmode, 5387 .port_setup_message_port = mv88e6xxx_setup_message_port, 5388 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5389 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5390 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5391 .stats_get_strings = mv88e6095_stats_get_strings, 5392 .stats_get_stat = mv88e6095_stats_get_stat, 5393 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5394 .set_egress_port = mv88e6095_g1_set_egress_port, 5395 .watchdog_ops = &mv88e6097_watchdog_ops, 5396 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5397 .pot_clear = mv88e6xxx_g2_pot_clear, 5398 .reset = mv88e6352_g1_reset, 5399 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5400 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5401 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5402 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5403 .stu_getnext = mv88e6352_g1_stu_getnext, 5404 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5405 .avb_ops = &mv88e6352_avb_ops, 5406 .ptp_ops = &mv88e6352_ptp_ops, 5407 .phylink_get_caps = mv88e6351_phylink_get_caps, 5408 }; 5409 5410 static const struct mv88e6xxx_ops mv88e6352_ops = { 5411 /* MV88E6XXX_FAMILY_6352 */ 5412 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5413 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5414 .irl_init_all = mv88e6352_g2_irl_init_all, 5415 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5416 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5417 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5418 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5419 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5420 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5421 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5422 .port_set_link = mv88e6xxx_port_set_link, 5423 .port_sync_link = mv88e6xxx_port_sync_link, 5424 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5425 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5426 .port_tag_remap = mv88e6095_port_tag_remap, 5427 .port_set_policy = mv88e6352_port_set_policy, 5428 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5429 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5430 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5431 .port_set_ether_type = mv88e6351_port_set_ether_type, 5432 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5433 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5434 .port_pause_limit = mv88e6097_port_pause_limit, 5435 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5436 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5437 .port_get_cmode = mv88e6352_port_get_cmode, 5438 .port_setup_leds = mv88e6xxx_port_setup_leds, 5439 .port_setup_message_port = mv88e6xxx_setup_message_port, 5440 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5441 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5442 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5443 .stats_get_strings = mv88e6095_stats_get_strings, 5444 .stats_get_stat = mv88e6095_stats_get_stat, 5445 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5446 .set_egress_port = mv88e6095_g1_set_egress_port, 5447 .watchdog_ops = &mv88e6097_watchdog_ops, 5448 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5449 .pot_clear = mv88e6xxx_g2_pot_clear, 5450 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5451 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5452 .reset = mv88e6352_g1_reset, 5453 .rmu_disable = mv88e6352_g1_rmu_disable, 5454 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5455 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5456 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5457 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5458 .stu_getnext = mv88e6352_g1_stu_getnext, 5459 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5460 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5461 .gpio_ops = &mv88e6352_gpio_ops, 5462 .avb_ops = &mv88e6352_avb_ops, 5463 .ptp_ops = &mv88e6352_ptp_ops, 5464 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5465 .serdes_get_strings = mv88e6352_serdes_get_strings, 5466 .serdes_get_stats = mv88e6352_serdes_get_stats, 5467 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5468 .serdes_get_regs = mv88e6352_serdes_get_regs, 5469 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5470 .phylink_get_caps = mv88e6352_phylink_get_caps, 5471 .pcs_ops = &mv88e6352_pcs_ops, 5472 }; 5473 5474 static const struct mv88e6xxx_ops mv88e6390_ops = { 5475 /* MV88E6XXX_FAMILY_6390 */ 5476 .setup_errata = mv88e6390_setup_errata, 5477 .irl_init_all = mv88e6390_g2_irl_init_all, 5478 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5479 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5481 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5482 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5483 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5484 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5485 .port_set_link = mv88e6xxx_port_set_link, 5486 .port_sync_link = mv88e6xxx_port_sync_link, 5487 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5488 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5489 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5490 .port_tag_remap = mv88e6390_port_tag_remap, 5491 .port_set_policy = mv88e6352_port_set_policy, 5492 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5493 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5494 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5495 .port_set_ether_type = mv88e6351_port_set_ether_type, 5496 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5497 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5498 .port_pause_limit = mv88e6390_port_pause_limit, 5499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5501 .port_get_cmode = mv88e6352_port_get_cmode, 5502 .port_set_cmode = mv88e6390_port_set_cmode, 5503 .port_setup_message_port = mv88e6xxx_setup_message_port, 5504 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5505 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5506 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5507 .stats_get_strings = mv88e6320_stats_get_strings, 5508 .stats_get_stat = mv88e6390_stats_get_stat, 5509 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5510 .set_egress_port = mv88e6390_g1_set_egress_port, 5511 .watchdog_ops = &mv88e6390_watchdog_ops, 5512 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5513 .pot_clear = mv88e6xxx_g2_pot_clear, 5514 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5515 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5516 .reset = mv88e6352_g1_reset, 5517 .rmu_disable = mv88e6390_g1_rmu_disable, 5518 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5519 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5520 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5521 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5522 .stu_getnext = mv88e6390_g1_stu_getnext, 5523 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5524 .serdes_get_lane = mv88e6390_serdes_get_lane, 5525 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5526 .gpio_ops = &mv88e6352_gpio_ops, 5527 .avb_ops = &mv88e6390_avb_ops, 5528 .ptp_ops = &mv88e6390_ptp_ops, 5529 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5530 .serdes_get_strings = mv88e6390_serdes_get_strings, 5531 .serdes_get_stats = mv88e6390_serdes_get_stats, 5532 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5533 .serdes_get_regs = mv88e6390_serdes_get_regs, 5534 .phylink_get_caps = mv88e6390_phylink_get_caps, 5535 .pcs_ops = &mv88e6390_pcs_ops, 5536 }; 5537 5538 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5539 /* MV88E6XXX_FAMILY_6390 */ 5540 .setup_errata = mv88e6390_setup_errata, 5541 .irl_init_all = mv88e6390_g2_irl_init_all, 5542 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5543 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5544 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5545 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5546 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5547 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5548 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5549 .port_set_link = mv88e6xxx_port_set_link, 5550 .port_sync_link = mv88e6xxx_port_sync_link, 5551 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5552 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5553 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5554 .port_tag_remap = mv88e6390_port_tag_remap, 5555 .port_set_policy = mv88e6352_port_set_policy, 5556 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5557 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5558 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5559 .port_set_ether_type = mv88e6351_port_set_ether_type, 5560 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5561 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5562 .port_pause_limit = mv88e6390_port_pause_limit, 5563 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5564 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5565 .port_get_cmode = mv88e6352_port_get_cmode, 5566 .port_set_cmode = mv88e6390x_port_set_cmode, 5567 .port_setup_message_port = mv88e6xxx_setup_message_port, 5568 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5569 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5570 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5571 .stats_get_strings = mv88e6320_stats_get_strings, 5572 .stats_get_stat = mv88e6390_stats_get_stat, 5573 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5574 .set_egress_port = mv88e6390_g1_set_egress_port, 5575 .watchdog_ops = &mv88e6390_watchdog_ops, 5576 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5577 .pot_clear = mv88e6xxx_g2_pot_clear, 5578 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5579 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5580 .reset = mv88e6352_g1_reset, 5581 .rmu_disable = mv88e6390_g1_rmu_disable, 5582 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5583 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5584 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5585 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5586 .stu_getnext = mv88e6390_g1_stu_getnext, 5587 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5588 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5589 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5590 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5591 .serdes_get_strings = mv88e6390_serdes_get_strings, 5592 .serdes_get_stats = mv88e6390_serdes_get_stats, 5593 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5594 .serdes_get_regs = mv88e6390_serdes_get_regs, 5595 .gpio_ops = &mv88e6352_gpio_ops, 5596 .avb_ops = &mv88e6390_avb_ops, 5597 .ptp_ops = &mv88e6390_ptp_ops, 5598 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5599 .pcs_ops = &mv88e6390_pcs_ops, 5600 }; 5601 5602 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5603 /* MV88E6XXX_FAMILY_6393 */ 5604 .irl_init_all = mv88e6390_g2_irl_init_all, 5605 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5606 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5608 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5609 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5610 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5611 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5612 .port_set_link = mv88e6xxx_port_set_link, 5613 .port_sync_link = mv88e6xxx_port_sync_link, 5614 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5615 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5616 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5617 .port_tag_remap = mv88e6390_port_tag_remap, 5618 .port_set_policy = mv88e6393x_port_set_policy, 5619 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5620 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5621 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5622 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5623 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5624 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5625 .port_pause_limit = mv88e6390_port_pause_limit, 5626 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5627 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5628 .port_get_cmode = mv88e6352_port_get_cmode, 5629 .port_set_cmode = mv88e6393x_port_set_cmode, 5630 .port_setup_message_port = mv88e6xxx_setup_message_port, 5631 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5632 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5633 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5634 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5635 .stats_get_strings = mv88e6320_stats_get_strings, 5636 .stats_get_stat = mv88e6390_stats_get_stat, 5637 /* .set_cpu_port is missing because this family does not support a global 5638 * CPU port, only per port CPU port which is set via 5639 * .port_set_upstream_port method. 5640 */ 5641 .set_egress_port = mv88e6393x_set_egress_port, 5642 .watchdog_ops = &mv88e6393x_watchdog_ops, 5643 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5644 .pot_clear = mv88e6xxx_g2_pot_clear, 5645 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5646 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5647 .reset = mv88e6352_g1_reset, 5648 .rmu_disable = mv88e6390_g1_rmu_disable, 5649 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5650 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5651 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5652 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5653 .stu_getnext = mv88e6390_g1_stu_getnext, 5654 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5655 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5656 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5657 /* TODO: serdes stats */ 5658 .gpio_ops = &mv88e6352_gpio_ops, 5659 .avb_ops = &mv88e6390_avb_ops, 5660 .ptp_ops = &mv88e6352_ptp_ops, 5661 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5662 .pcs_ops = &mv88e6393x_pcs_ops, 5663 }; 5664 5665 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5666 [MV88E6020] = { 5667 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5668 .family = MV88E6XXX_FAMILY_6250, 5669 .name = "Marvell 88E6020", 5670 .num_databases = 64, 5671 /* Ports 2-4 are not routed to pins 5672 * => usable ports 0, 1, 5, 6 5673 */ 5674 .num_ports = 7, 5675 .num_internal_phys = 2, 5676 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5677 .max_vid = 4095, 5678 .port_base_addr = 0x8, 5679 .phy_base_addr = 0x0, 5680 .global1_addr = 0xf, 5681 .global2_addr = 0x7, 5682 .age_time_coeff = 15000, 5683 .g1_irqs = 9, 5684 .g2_irqs = 5, 5685 .stats_type = STATS_TYPE_BANK0, 5686 .atu_move_port_mask = 0xf, 5687 .dual_chip = true, 5688 .ops = &mv88e6250_ops, 5689 }, 5690 5691 [MV88E6071] = { 5692 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5693 .family = MV88E6XXX_FAMILY_6250, 5694 .name = "Marvell 88E6071", 5695 .num_databases = 64, 5696 .num_ports = 7, 5697 .num_internal_phys = 5, 5698 .max_vid = 4095, 5699 .port_base_addr = 0x08, 5700 .phy_base_addr = 0x00, 5701 .global1_addr = 0x0f, 5702 .global2_addr = 0x07, 5703 .age_time_coeff = 15000, 5704 .g1_irqs = 9, 5705 .g2_irqs = 5, 5706 .stats_type = STATS_TYPE_BANK0, 5707 .atu_move_port_mask = 0xf, 5708 .dual_chip = true, 5709 .ops = &mv88e6250_ops, 5710 }, 5711 5712 [MV88E6085] = { 5713 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5714 .family = MV88E6XXX_FAMILY_6097, 5715 .name = "Marvell 88E6085", 5716 .num_databases = 4096, 5717 .num_macs = 8192, 5718 .num_ports = 10, 5719 .num_internal_phys = 5, 5720 .max_vid = 4095, 5721 .max_sid = 63, 5722 .port_base_addr = 0x10, 5723 .phy_base_addr = 0x0, 5724 .global1_addr = 0x1b, 5725 .global2_addr = 0x1c, 5726 .age_time_coeff = 15000, 5727 .g1_irqs = 8, 5728 .g2_irqs = 10, 5729 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5730 .atu_move_port_mask = 0xf, 5731 .pvt = true, 5732 .multi_chip = true, 5733 .ops = &mv88e6085_ops, 5734 }, 5735 5736 [MV88E6095] = { 5737 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5738 .family = MV88E6XXX_FAMILY_6095, 5739 .name = "Marvell 88E6095/88E6095F", 5740 .num_databases = 256, 5741 .num_macs = 8192, 5742 .num_ports = 11, 5743 .num_internal_phys = 0, 5744 .max_vid = 4095, 5745 .port_base_addr = 0x10, 5746 .phy_base_addr = 0x0, 5747 .global1_addr = 0x1b, 5748 .global2_addr = 0x1c, 5749 .age_time_coeff = 15000, 5750 .g1_irqs = 8, 5751 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5752 .atu_move_port_mask = 0xf, 5753 .multi_chip = true, 5754 .ops = &mv88e6095_ops, 5755 }, 5756 5757 [MV88E6097] = { 5758 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5759 .family = MV88E6XXX_FAMILY_6097, 5760 .name = "Marvell 88E6097/88E6097F", 5761 .num_databases = 4096, 5762 .num_macs = 8192, 5763 .num_ports = 11, 5764 .num_internal_phys = 8, 5765 .max_vid = 4095, 5766 .max_sid = 63, 5767 .port_base_addr = 0x10, 5768 .phy_base_addr = 0x0, 5769 .global1_addr = 0x1b, 5770 .global2_addr = 0x1c, 5771 .age_time_coeff = 15000, 5772 .g1_irqs = 8, 5773 .g2_irqs = 10, 5774 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5775 .atu_move_port_mask = 0xf, 5776 .pvt = true, 5777 .multi_chip = true, 5778 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5779 .ops = &mv88e6097_ops, 5780 }, 5781 5782 [MV88E6123] = { 5783 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5784 .family = MV88E6XXX_FAMILY_6165, 5785 .name = "Marvell 88E6123", 5786 .num_databases = 4096, 5787 .num_macs = 1024, 5788 .num_ports = 3, 5789 .num_internal_phys = 5, 5790 .max_vid = 4095, 5791 .max_sid = 63, 5792 .port_base_addr = 0x10, 5793 .phy_base_addr = 0x0, 5794 .global1_addr = 0x1b, 5795 .global2_addr = 0x1c, 5796 .age_time_coeff = 15000, 5797 .g1_irqs = 9, 5798 .g2_irqs = 10, 5799 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5800 .atu_move_port_mask = 0xf, 5801 .pvt = true, 5802 .multi_chip = true, 5803 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5804 .ops = &mv88e6123_ops, 5805 }, 5806 5807 [MV88E6131] = { 5808 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5809 .family = MV88E6XXX_FAMILY_6185, 5810 .name = "Marvell 88E6131", 5811 .num_databases = 256, 5812 .num_macs = 8192, 5813 .num_ports = 8, 5814 .num_internal_phys = 0, 5815 .max_vid = 4095, 5816 .port_base_addr = 0x10, 5817 .phy_base_addr = 0x0, 5818 .global1_addr = 0x1b, 5819 .global2_addr = 0x1c, 5820 .age_time_coeff = 15000, 5821 .g1_irqs = 9, 5822 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5823 .atu_move_port_mask = 0xf, 5824 .multi_chip = true, 5825 .ops = &mv88e6131_ops, 5826 }, 5827 5828 [MV88E6141] = { 5829 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5830 .family = MV88E6XXX_FAMILY_6341, 5831 .name = "Marvell 88E6141", 5832 .num_databases = 256, 5833 .num_macs = 2048, 5834 .num_ports = 6, 5835 .num_internal_phys = 5, 5836 .num_gpio = 11, 5837 .max_vid = 4095, 5838 .max_sid = 63, 5839 .port_base_addr = 0x10, 5840 .phy_base_addr = 0x10, 5841 .global1_addr = 0x1b, 5842 .global2_addr = 0x1c, 5843 .age_time_coeff = 3750, 5844 .atu_move_port_mask = 0xf, 5845 .g1_irqs = 9, 5846 .g2_irqs = 10, 5847 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5848 .pvt = true, 5849 .multi_chip = true, 5850 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5851 .ops = &mv88e6141_ops, 5852 }, 5853 5854 [MV88E6161] = { 5855 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5856 .family = MV88E6XXX_FAMILY_6165, 5857 .name = "Marvell 88E6161", 5858 .num_databases = 4096, 5859 .num_macs = 1024, 5860 .num_ports = 6, 5861 .num_internal_phys = 5, 5862 .max_vid = 4095, 5863 .max_sid = 63, 5864 .port_base_addr = 0x10, 5865 .phy_base_addr = 0x0, 5866 .global1_addr = 0x1b, 5867 .global2_addr = 0x1c, 5868 .age_time_coeff = 15000, 5869 .g1_irqs = 9, 5870 .g2_irqs = 10, 5871 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5872 .atu_move_port_mask = 0xf, 5873 .pvt = true, 5874 .multi_chip = true, 5875 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5876 .ptp_support = true, 5877 .ops = &mv88e6161_ops, 5878 }, 5879 5880 [MV88E6165] = { 5881 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5882 .family = MV88E6XXX_FAMILY_6165, 5883 .name = "Marvell 88E6165", 5884 .num_databases = 4096, 5885 .num_macs = 8192, 5886 .num_ports = 6, 5887 .num_internal_phys = 0, 5888 .max_vid = 4095, 5889 .max_sid = 63, 5890 .port_base_addr = 0x10, 5891 .phy_base_addr = 0x0, 5892 .global1_addr = 0x1b, 5893 .global2_addr = 0x1c, 5894 .age_time_coeff = 15000, 5895 .g1_irqs = 9, 5896 .g2_irqs = 10, 5897 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5898 .atu_move_port_mask = 0xf, 5899 .pvt = true, 5900 .multi_chip = true, 5901 .ptp_support = true, 5902 .ops = &mv88e6165_ops, 5903 }, 5904 5905 [MV88E6171] = { 5906 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5907 .family = MV88E6XXX_FAMILY_6351, 5908 .name = "Marvell 88E6171", 5909 .num_databases = 4096, 5910 .num_macs = 8192, 5911 .num_ports = 7, 5912 .num_internal_phys = 5, 5913 .max_vid = 4095, 5914 .max_sid = 63, 5915 .port_base_addr = 0x10, 5916 .phy_base_addr = 0x0, 5917 .global1_addr = 0x1b, 5918 .global2_addr = 0x1c, 5919 .age_time_coeff = 15000, 5920 .g1_irqs = 9, 5921 .g2_irqs = 10, 5922 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5923 .atu_move_port_mask = 0xf, 5924 .pvt = true, 5925 .multi_chip = true, 5926 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5927 .ops = &mv88e6171_ops, 5928 }, 5929 5930 [MV88E6172] = { 5931 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5932 .family = MV88E6XXX_FAMILY_6352, 5933 .name = "Marvell 88E6172", 5934 .num_databases = 4096, 5935 .num_macs = 8192, 5936 .num_ports = 7, 5937 .num_internal_phys = 5, 5938 .num_gpio = 15, 5939 .max_vid = 4095, 5940 .max_sid = 63, 5941 .port_base_addr = 0x10, 5942 .phy_base_addr = 0x0, 5943 .global1_addr = 0x1b, 5944 .global2_addr = 0x1c, 5945 .age_time_coeff = 15000, 5946 .g1_irqs = 9, 5947 .g2_irqs = 10, 5948 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5949 .atu_move_port_mask = 0xf, 5950 .pvt = true, 5951 .multi_chip = true, 5952 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5953 .ops = &mv88e6172_ops, 5954 }, 5955 5956 [MV88E6175] = { 5957 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5958 .family = MV88E6XXX_FAMILY_6351, 5959 .name = "Marvell 88E6175", 5960 .num_databases = 4096, 5961 .num_macs = 8192, 5962 .num_ports = 7, 5963 .num_internal_phys = 5, 5964 .max_vid = 4095, 5965 .max_sid = 63, 5966 .port_base_addr = 0x10, 5967 .phy_base_addr = 0x0, 5968 .global1_addr = 0x1b, 5969 .global2_addr = 0x1c, 5970 .age_time_coeff = 15000, 5971 .g1_irqs = 9, 5972 .g2_irqs = 10, 5973 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5974 .atu_move_port_mask = 0xf, 5975 .pvt = true, 5976 .multi_chip = true, 5977 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5978 .ops = &mv88e6175_ops, 5979 }, 5980 5981 [MV88E6176] = { 5982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5983 .family = MV88E6XXX_FAMILY_6352, 5984 .name = "Marvell 88E6176", 5985 .num_databases = 4096, 5986 .num_macs = 8192, 5987 .num_ports = 7, 5988 .num_internal_phys = 5, 5989 .num_gpio = 15, 5990 .max_vid = 4095, 5991 .max_sid = 63, 5992 .port_base_addr = 0x10, 5993 .phy_base_addr = 0x0, 5994 .global1_addr = 0x1b, 5995 .global2_addr = 0x1c, 5996 .age_time_coeff = 15000, 5997 .g1_irqs = 9, 5998 .g2_irqs = 10, 5999 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6000 .atu_move_port_mask = 0xf, 6001 .pvt = true, 6002 .multi_chip = true, 6003 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6004 .ops = &mv88e6176_ops, 6005 }, 6006 6007 [MV88E6185] = { 6008 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 6009 .family = MV88E6XXX_FAMILY_6185, 6010 .name = "Marvell 88E6185", 6011 .num_databases = 256, 6012 .num_macs = 8192, 6013 .num_ports = 10, 6014 .num_internal_phys = 0, 6015 .max_vid = 4095, 6016 .port_base_addr = 0x10, 6017 .phy_base_addr = 0x0, 6018 .global1_addr = 0x1b, 6019 .global2_addr = 0x1c, 6020 .age_time_coeff = 15000, 6021 .g1_irqs = 8, 6022 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6023 .atu_move_port_mask = 0xf, 6024 .multi_chip = true, 6025 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6026 .ops = &mv88e6185_ops, 6027 }, 6028 6029 [MV88E6190] = { 6030 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6031 .family = MV88E6XXX_FAMILY_6390, 6032 .name = "Marvell 88E6190", 6033 .num_databases = 4096, 6034 .num_macs = 16384, 6035 .num_ports = 11, /* 10 + Z80 */ 6036 .num_internal_phys = 9, 6037 .num_gpio = 16, 6038 .max_vid = 8191, 6039 .max_sid = 63, 6040 .port_base_addr = 0x0, 6041 .phy_base_addr = 0x0, 6042 .global1_addr = 0x1b, 6043 .global2_addr = 0x1c, 6044 .age_time_coeff = 3750, 6045 .g1_irqs = 9, 6046 .g2_irqs = 14, 6047 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6048 .pvt = true, 6049 .multi_chip = true, 6050 .atu_move_port_mask = 0x1f, 6051 .ops = &mv88e6190_ops, 6052 }, 6053 6054 [MV88E6190X] = { 6055 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6056 .family = MV88E6XXX_FAMILY_6390, 6057 .name = "Marvell 88E6190X", 6058 .num_databases = 4096, 6059 .num_macs = 16384, 6060 .num_ports = 11, /* 10 + Z80 */ 6061 .num_internal_phys = 9, 6062 .num_gpio = 16, 6063 .max_vid = 8191, 6064 .max_sid = 63, 6065 .port_base_addr = 0x0, 6066 .phy_base_addr = 0x0, 6067 .global1_addr = 0x1b, 6068 .global2_addr = 0x1c, 6069 .age_time_coeff = 3750, 6070 .g1_irqs = 9, 6071 .g2_irqs = 14, 6072 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6073 .atu_move_port_mask = 0x1f, 6074 .pvt = true, 6075 .multi_chip = true, 6076 .ops = &mv88e6190x_ops, 6077 }, 6078 6079 [MV88E6191] = { 6080 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6081 .family = MV88E6XXX_FAMILY_6390, 6082 .name = "Marvell 88E6191", 6083 .num_databases = 4096, 6084 .num_macs = 16384, 6085 .num_ports = 11, /* 10 + Z80 */ 6086 .num_internal_phys = 9, 6087 .max_vid = 8191, 6088 .max_sid = 63, 6089 .port_base_addr = 0x0, 6090 .phy_base_addr = 0x0, 6091 .global1_addr = 0x1b, 6092 .global2_addr = 0x1c, 6093 .age_time_coeff = 3750, 6094 .g1_irqs = 9, 6095 .g2_irqs = 14, 6096 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6097 .atu_move_port_mask = 0x1f, 6098 .pvt = true, 6099 .multi_chip = true, 6100 .ptp_support = true, 6101 .ops = &mv88e6191_ops, 6102 }, 6103 6104 [MV88E6191X] = { 6105 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6106 .family = MV88E6XXX_FAMILY_6393, 6107 .name = "Marvell 88E6191X", 6108 .num_databases = 4096, 6109 .num_ports = 11, /* 10 + Z80 */ 6110 .num_internal_phys = 8, 6111 .internal_phys_offset = 1, 6112 .max_vid = 8191, 6113 .max_sid = 63, 6114 .port_base_addr = 0x0, 6115 .phy_base_addr = 0x0, 6116 .global1_addr = 0x1b, 6117 .global2_addr = 0x1c, 6118 .age_time_coeff = 3750, 6119 .g1_irqs = 10, 6120 .g2_irqs = 14, 6121 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6122 .atu_move_port_mask = 0x1f, 6123 .pvt = true, 6124 .multi_chip = true, 6125 .ptp_support = true, 6126 .ops = &mv88e6393x_ops, 6127 }, 6128 6129 [MV88E6193X] = { 6130 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6131 .family = MV88E6XXX_FAMILY_6393, 6132 .name = "Marvell 88E6193X", 6133 .num_databases = 4096, 6134 .num_ports = 11, /* 10 + Z80 */ 6135 .num_internal_phys = 8, 6136 .internal_phys_offset = 1, 6137 .max_vid = 8191, 6138 .max_sid = 63, 6139 .port_base_addr = 0x0, 6140 .phy_base_addr = 0x0, 6141 .global1_addr = 0x1b, 6142 .global2_addr = 0x1c, 6143 .age_time_coeff = 3750, 6144 .g1_irqs = 10, 6145 .g2_irqs = 14, 6146 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6147 .atu_move_port_mask = 0x1f, 6148 .pvt = true, 6149 .multi_chip = true, 6150 .ptp_support = true, 6151 .ops = &mv88e6393x_ops, 6152 }, 6153 6154 [MV88E6220] = { 6155 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6156 .family = MV88E6XXX_FAMILY_6250, 6157 .name = "Marvell 88E6220", 6158 .num_databases = 64, 6159 6160 /* Ports 2-4 are not routed to pins 6161 * => usable ports 0, 1, 5, 6 6162 */ 6163 .num_ports = 7, 6164 .num_internal_phys = 2, 6165 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6166 .max_vid = 4095, 6167 .port_base_addr = 0x08, 6168 .phy_base_addr = 0x00, 6169 .global1_addr = 0x0f, 6170 .global2_addr = 0x07, 6171 .age_time_coeff = 15000, 6172 .g1_irqs = 9, 6173 .g2_irqs = 10, 6174 .stats_type = STATS_TYPE_BANK0, 6175 .atu_move_port_mask = 0xf, 6176 .dual_chip = true, 6177 .ptp_support = true, 6178 .ops = &mv88e6250_ops, 6179 }, 6180 6181 [MV88E6240] = { 6182 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6183 .family = MV88E6XXX_FAMILY_6352, 6184 .name = "Marvell 88E6240", 6185 .num_databases = 4096, 6186 .num_macs = 8192, 6187 .num_ports = 7, 6188 .num_internal_phys = 5, 6189 .num_gpio = 15, 6190 .max_vid = 4095, 6191 .max_sid = 63, 6192 .port_base_addr = 0x10, 6193 .phy_base_addr = 0x0, 6194 .global1_addr = 0x1b, 6195 .global2_addr = 0x1c, 6196 .age_time_coeff = 15000, 6197 .g1_irqs = 9, 6198 .g2_irqs = 10, 6199 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6200 .atu_move_port_mask = 0xf, 6201 .pvt = true, 6202 .multi_chip = true, 6203 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6204 .ptp_support = true, 6205 .ops = &mv88e6240_ops, 6206 }, 6207 6208 [MV88E6250] = { 6209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6210 .family = MV88E6XXX_FAMILY_6250, 6211 .name = "Marvell 88E6250", 6212 .num_databases = 64, 6213 .num_ports = 7, 6214 .num_internal_phys = 5, 6215 .max_vid = 4095, 6216 .port_base_addr = 0x08, 6217 .phy_base_addr = 0x00, 6218 .global1_addr = 0x0f, 6219 .global2_addr = 0x07, 6220 .age_time_coeff = 15000, 6221 .g1_irqs = 9, 6222 .g2_irqs = 10, 6223 .stats_type = STATS_TYPE_BANK0, 6224 .atu_move_port_mask = 0xf, 6225 .dual_chip = true, 6226 .ptp_support = true, 6227 .ops = &mv88e6250_ops, 6228 }, 6229 6230 [MV88E6290] = { 6231 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6232 .family = MV88E6XXX_FAMILY_6390, 6233 .name = "Marvell 88E6290", 6234 .num_databases = 4096, 6235 .num_ports = 11, /* 10 + Z80 */ 6236 .num_internal_phys = 9, 6237 .num_gpio = 16, 6238 .max_vid = 8191, 6239 .max_sid = 63, 6240 .port_base_addr = 0x0, 6241 .phy_base_addr = 0x0, 6242 .global1_addr = 0x1b, 6243 .global2_addr = 0x1c, 6244 .age_time_coeff = 3750, 6245 .g1_irqs = 9, 6246 .g2_irqs = 14, 6247 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6248 .atu_move_port_mask = 0x1f, 6249 .pvt = true, 6250 .multi_chip = true, 6251 .ptp_support = true, 6252 .ops = &mv88e6290_ops, 6253 }, 6254 6255 [MV88E6320] = { 6256 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6257 .family = MV88E6XXX_FAMILY_6320, 6258 .name = "Marvell 88E6320", 6259 .num_databases = 4096, 6260 .num_macs = 8192, 6261 .num_ports = 7, 6262 .num_internal_phys = 2, 6263 .internal_phys_offset = 3, 6264 .num_gpio = 15, 6265 .max_vid = 4095, 6266 .max_sid = 63, 6267 .port_base_addr = 0x10, 6268 .phy_base_addr = 0x0, 6269 .global1_addr = 0x1b, 6270 .global2_addr = 0x1c, 6271 .age_time_coeff = 15000, 6272 .g1_irqs = 8, 6273 .g2_irqs = 10, 6274 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6275 .atu_move_port_mask = 0xf, 6276 .pvt = true, 6277 .multi_chip = true, 6278 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6279 .ptp_support = true, 6280 .ops = &mv88e6320_ops, 6281 }, 6282 6283 [MV88E6321] = { 6284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6285 .family = MV88E6XXX_FAMILY_6320, 6286 .name = "Marvell 88E6321", 6287 .num_databases = 4096, 6288 .num_macs = 8192, 6289 .num_ports = 7, 6290 .num_internal_phys = 2, 6291 .internal_phys_offset = 3, 6292 .num_gpio = 15, 6293 .max_vid = 4095, 6294 .max_sid = 63, 6295 .port_base_addr = 0x10, 6296 .phy_base_addr = 0x0, 6297 .global1_addr = 0x1b, 6298 .global2_addr = 0x1c, 6299 .age_time_coeff = 15000, 6300 .g1_irqs = 8, 6301 .g2_irqs = 10, 6302 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6303 .atu_move_port_mask = 0xf, 6304 .pvt = true, 6305 .multi_chip = true, 6306 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6307 .ptp_support = true, 6308 .ops = &mv88e6321_ops, 6309 }, 6310 6311 [MV88E6341] = { 6312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6313 .family = MV88E6XXX_FAMILY_6341, 6314 .name = "Marvell 88E6341", 6315 .num_databases = 256, 6316 .num_macs = 2048, 6317 .num_internal_phys = 5, 6318 .num_ports = 6, 6319 .num_gpio = 11, 6320 .max_vid = 4095, 6321 .max_sid = 63, 6322 .port_base_addr = 0x10, 6323 .phy_base_addr = 0x10, 6324 .global1_addr = 0x1b, 6325 .global2_addr = 0x1c, 6326 .age_time_coeff = 3750, 6327 .atu_move_port_mask = 0xf, 6328 .g1_irqs = 9, 6329 .g2_irqs = 10, 6330 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6331 .pvt = true, 6332 .multi_chip = true, 6333 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6334 .ptp_support = true, 6335 .ops = &mv88e6341_ops, 6336 }, 6337 6338 [MV88E6350] = { 6339 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6340 .family = MV88E6XXX_FAMILY_6351, 6341 .name = "Marvell 88E6350", 6342 .num_databases = 4096, 6343 .num_macs = 8192, 6344 .num_ports = 7, 6345 .num_internal_phys = 5, 6346 .max_vid = 4095, 6347 .max_sid = 63, 6348 .port_base_addr = 0x10, 6349 .phy_base_addr = 0x0, 6350 .global1_addr = 0x1b, 6351 .global2_addr = 0x1c, 6352 .age_time_coeff = 15000, 6353 .g1_irqs = 9, 6354 .g2_irqs = 10, 6355 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6356 .atu_move_port_mask = 0xf, 6357 .pvt = true, 6358 .multi_chip = true, 6359 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6360 .ops = &mv88e6350_ops, 6361 }, 6362 6363 [MV88E6351] = { 6364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6365 .family = MV88E6XXX_FAMILY_6351, 6366 .name = "Marvell 88E6351", 6367 .num_databases = 4096, 6368 .num_macs = 8192, 6369 .num_ports = 7, 6370 .num_internal_phys = 5, 6371 .max_vid = 4095, 6372 .max_sid = 63, 6373 .port_base_addr = 0x10, 6374 .phy_base_addr = 0x0, 6375 .global1_addr = 0x1b, 6376 .global2_addr = 0x1c, 6377 .age_time_coeff = 15000, 6378 .g1_irqs = 9, 6379 .g2_irqs = 10, 6380 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6381 .atu_move_port_mask = 0xf, 6382 .pvt = true, 6383 .multi_chip = true, 6384 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6385 .ops = &mv88e6351_ops, 6386 }, 6387 6388 [MV88E6352] = { 6389 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6390 .family = MV88E6XXX_FAMILY_6352, 6391 .name = "Marvell 88E6352", 6392 .num_databases = 4096, 6393 .num_macs = 8192, 6394 .num_ports = 7, 6395 .num_internal_phys = 5, 6396 .num_gpio = 15, 6397 .max_vid = 4095, 6398 .max_sid = 63, 6399 .port_base_addr = 0x10, 6400 .phy_base_addr = 0x0, 6401 .global1_addr = 0x1b, 6402 .global2_addr = 0x1c, 6403 .age_time_coeff = 15000, 6404 .g1_irqs = 9, 6405 .g2_irqs = 10, 6406 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6407 .atu_move_port_mask = 0xf, 6408 .pvt = true, 6409 .multi_chip = true, 6410 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6411 .ptp_support = true, 6412 .ops = &mv88e6352_ops, 6413 }, 6414 [MV88E6361] = { 6415 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6416 .family = MV88E6XXX_FAMILY_6393, 6417 .name = "Marvell 88E6361", 6418 .num_databases = 4096, 6419 .num_macs = 16384, 6420 .num_ports = 11, 6421 /* Ports 1, 2 and 8 are not routed */ 6422 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6423 .num_internal_phys = 5, 6424 .internal_phys_offset = 3, 6425 .max_vid = 8191, 6426 .max_sid = 63, 6427 .port_base_addr = 0x0, 6428 .phy_base_addr = 0x0, 6429 .global1_addr = 0x1b, 6430 .global2_addr = 0x1c, 6431 .age_time_coeff = 3750, 6432 .g1_irqs = 10, 6433 .g2_irqs = 14, 6434 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6435 .atu_move_port_mask = 0x1f, 6436 .pvt = true, 6437 .multi_chip = true, 6438 .ptp_support = true, 6439 .ops = &mv88e6393x_ops, 6440 }, 6441 [MV88E6390] = { 6442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6443 .family = MV88E6XXX_FAMILY_6390, 6444 .name = "Marvell 88E6390", 6445 .num_databases = 4096, 6446 .num_macs = 16384, 6447 .num_ports = 11, /* 10 + Z80 */ 6448 .num_internal_phys = 9, 6449 .num_gpio = 16, 6450 .max_vid = 8191, 6451 .max_sid = 63, 6452 .port_base_addr = 0x0, 6453 .phy_base_addr = 0x0, 6454 .global1_addr = 0x1b, 6455 .global2_addr = 0x1c, 6456 .age_time_coeff = 3750, 6457 .g1_irqs = 9, 6458 .g2_irqs = 14, 6459 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6460 .atu_move_port_mask = 0x1f, 6461 .pvt = true, 6462 .multi_chip = true, 6463 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6464 .ptp_support = true, 6465 .ops = &mv88e6390_ops, 6466 }, 6467 [MV88E6390X] = { 6468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6469 .family = MV88E6XXX_FAMILY_6390, 6470 .name = "Marvell 88E6390X", 6471 .num_databases = 4096, 6472 .num_macs = 16384, 6473 .num_ports = 11, /* 10 + Z80 */ 6474 .num_internal_phys = 9, 6475 .num_gpio = 16, 6476 .max_vid = 8191, 6477 .max_sid = 63, 6478 .port_base_addr = 0x0, 6479 .phy_base_addr = 0x0, 6480 .global1_addr = 0x1b, 6481 .global2_addr = 0x1c, 6482 .age_time_coeff = 3750, 6483 .g1_irqs = 9, 6484 .g2_irqs = 14, 6485 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6486 .atu_move_port_mask = 0x1f, 6487 .pvt = true, 6488 .multi_chip = true, 6489 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6490 .ptp_support = true, 6491 .ops = &mv88e6390x_ops, 6492 }, 6493 6494 [MV88E6393X] = { 6495 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6496 .family = MV88E6XXX_FAMILY_6393, 6497 .name = "Marvell 88E6393X", 6498 .num_databases = 4096, 6499 .num_ports = 11, /* 10 + Z80 */ 6500 .num_internal_phys = 8, 6501 .internal_phys_offset = 1, 6502 .max_vid = 8191, 6503 .max_sid = 63, 6504 .port_base_addr = 0x0, 6505 .phy_base_addr = 0x0, 6506 .global1_addr = 0x1b, 6507 .global2_addr = 0x1c, 6508 .age_time_coeff = 3750, 6509 .g1_irqs = 10, 6510 .g2_irqs = 14, 6511 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6512 .atu_move_port_mask = 0x1f, 6513 .pvt = true, 6514 .multi_chip = true, 6515 .ptp_support = true, 6516 .ops = &mv88e6393x_ops, 6517 }, 6518 }; 6519 6520 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6521 { 6522 int i; 6523 6524 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6525 if (mv88e6xxx_table[i].prod_num == prod_num) 6526 return &mv88e6xxx_table[i]; 6527 6528 return NULL; 6529 } 6530 6531 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6532 { 6533 const struct mv88e6xxx_info *info; 6534 unsigned int prod_num, rev; 6535 u16 id; 6536 int err; 6537 6538 mv88e6xxx_reg_lock(chip); 6539 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6540 mv88e6xxx_reg_unlock(chip); 6541 if (err) 6542 return err; 6543 6544 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6545 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6546 6547 info = mv88e6xxx_lookup_info(prod_num); 6548 if (!info) 6549 return -ENODEV; 6550 6551 /* Update the compatible info with the probed one */ 6552 chip->info = info; 6553 6554 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6555 chip->info->prod_num, chip->info->name, rev); 6556 6557 return 0; 6558 } 6559 6560 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6561 struct mdio_device *mdiodev) 6562 { 6563 int err; 6564 6565 /* dual_chip takes precedence over single/multi-chip modes */ 6566 if (chip->info->dual_chip) 6567 return -EINVAL; 6568 6569 /* If the mdio addr is 16 indicating the first port address of a switch 6570 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6571 * configured in single chip addressing mode. Setup the smi access as 6572 * single chip addressing mode and attempt to detect the model of the 6573 * switch, if this fails the device is not configured in single chip 6574 * addressing mode. 6575 */ 6576 if (mdiodev->addr != 16) 6577 return -EINVAL; 6578 6579 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6580 if (err) 6581 return err; 6582 6583 return mv88e6xxx_detect(chip); 6584 } 6585 6586 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6587 { 6588 struct mv88e6xxx_chip *chip; 6589 6590 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6591 if (!chip) 6592 return NULL; 6593 6594 chip->dev = dev; 6595 6596 mutex_init(&chip->reg_lock); 6597 INIT_LIST_HEAD(&chip->mdios); 6598 idr_init(&chip->policies); 6599 INIT_LIST_HEAD(&chip->msts); 6600 6601 return chip; 6602 } 6603 6604 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6605 int port, 6606 enum dsa_tag_protocol m) 6607 { 6608 struct mv88e6xxx_chip *chip = ds->priv; 6609 6610 return chip->tag_protocol; 6611 } 6612 6613 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6614 enum dsa_tag_protocol proto) 6615 { 6616 struct mv88e6xxx_chip *chip = ds->priv; 6617 enum dsa_tag_protocol old_protocol; 6618 struct dsa_port *cpu_dp; 6619 int err; 6620 6621 switch (proto) { 6622 case DSA_TAG_PROTO_EDSA: 6623 switch (chip->info->edsa_support) { 6624 case MV88E6XXX_EDSA_UNSUPPORTED: 6625 return -EPROTONOSUPPORT; 6626 case MV88E6XXX_EDSA_UNDOCUMENTED: 6627 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6628 fallthrough; 6629 case MV88E6XXX_EDSA_SUPPORTED: 6630 break; 6631 } 6632 break; 6633 case DSA_TAG_PROTO_DSA: 6634 break; 6635 default: 6636 return -EPROTONOSUPPORT; 6637 } 6638 6639 old_protocol = chip->tag_protocol; 6640 chip->tag_protocol = proto; 6641 6642 mv88e6xxx_reg_lock(chip); 6643 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6644 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6645 if (err) { 6646 mv88e6xxx_reg_unlock(chip); 6647 goto unwind; 6648 } 6649 } 6650 mv88e6xxx_reg_unlock(chip); 6651 6652 return 0; 6653 6654 unwind: 6655 chip->tag_protocol = old_protocol; 6656 6657 mv88e6xxx_reg_lock(chip); 6658 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6659 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6660 mv88e6xxx_reg_unlock(chip); 6661 6662 return err; 6663 } 6664 6665 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6666 const struct switchdev_obj_port_mdb *mdb, 6667 struct dsa_db db) 6668 { 6669 struct mv88e6xxx_chip *chip = ds->priv; 6670 int err; 6671 6672 mv88e6xxx_reg_lock(chip); 6673 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6674 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6675 if (err) 6676 goto out; 6677 6678 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid)) 6679 err = -ENOSPC; 6680 6681 out: 6682 mv88e6xxx_reg_unlock(chip); 6683 6684 return err; 6685 } 6686 6687 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6688 const struct switchdev_obj_port_mdb *mdb, 6689 struct dsa_db db) 6690 { 6691 struct mv88e6xxx_chip *chip = ds->priv; 6692 int err; 6693 6694 mv88e6xxx_reg_lock(chip); 6695 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6696 mv88e6xxx_reg_unlock(chip); 6697 6698 return err; 6699 } 6700 6701 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6702 struct dsa_mall_mirror_tc_entry *mirror, 6703 bool ingress, 6704 struct netlink_ext_ack *extack) 6705 { 6706 enum mv88e6xxx_egress_direction direction = ingress ? 6707 MV88E6XXX_EGRESS_DIR_INGRESS : 6708 MV88E6XXX_EGRESS_DIR_EGRESS; 6709 struct mv88e6xxx_chip *chip = ds->priv; 6710 bool other_mirrors = false; 6711 int i; 6712 int err; 6713 6714 mutex_lock(&chip->reg_lock); 6715 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6716 mirror->to_local_port) { 6717 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6718 other_mirrors |= ingress ? 6719 chip->ports[i].mirror_ingress : 6720 chip->ports[i].mirror_egress; 6721 6722 /* Can't change egress port when other mirror is active */ 6723 if (other_mirrors) { 6724 err = -EBUSY; 6725 goto out; 6726 } 6727 6728 err = mv88e6xxx_set_egress_port(chip, direction, 6729 mirror->to_local_port); 6730 if (err) 6731 goto out; 6732 } 6733 6734 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6735 out: 6736 mutex_unlock(&chip->reg_lock); 6737 6738 return err; 6739 } 6740 6741 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6742 struct dsa_mall_mirror_tc_entry *mirror) 6743 { 6744 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6745 MV88E6XXX_EGRESS_DIR_INGRESS : 6746 MV88E6XXX_EGRESS_DIR_EGRESS; 6747 struct mv88e6xxx_chip *chip = ds->priv; 6748 bool other_mirrors = false; 6749 int i; 6750 6751 mutex_lock(&chip->reg_lock); 6752 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6753 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6754 6755 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6756 other_mirrors |= mirror->ingress ? 6757 chip->ports[i].mirror_ingress : 6758 chip->ports[i].mirror_egress; 6759 6760 /* Reset egress port when no other mirror is active */ 6761 if (!other_mirrors) { 6762 if (mv88e6xxx_set_egress_port(chip, direction, 6763 dsa_upstream_port(ds, port))) 6764 dev_err(ds->dev, "failed to set egress port\n"); 6765 } 6766 6767 mutex_unlock(&chip->reg_lock); 6768 } 6769 6770 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6771 struct switchdev_brport_flags flags, 6772 struct netlink_ext_ack *extack) 6773 { 6774 struct mv88e6xxx_chip *chip = ds->priv; 6775 const struct mv88e6xxx_ops *ops; 6776 6777 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6778 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6779 return -EINVAL; 6780 6781 ops = chip->info->ops; 6782 6783 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6784 return -EINVAL; 6785 6786 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6787 return -EINVAL; 6788 6789 return 0; 6790 } 6791 6792 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6793 struct switchdev_brport_flags flags, 6794 struct netlink_ext_ack *extack) 6795 { 6796 struct mv88e6xxx_chip *chip = ds->priv; 6797 int err = 0; 6798 6799 mv88e6xxx_reg_lock(chip); 6800 6801 if (flags.mask & BR_LEARNING) { 6802 bool learning = !!(flags.val & BR_LEARNING); 6803 u16 pav = learning ? (1 << port) : 0; 6804 6805 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6806 if (err) 6807 goto out; 6808 } 6809 6810 if (flags.mask & BR_FLOOD) { 6811 bool unicast = !!(flags.val & BR_FLOOD); 6812 6813 err = chip->info->ops->port_set_ucast_flood(chip, port, 6814 unicast); 6815 if (err) 6816 goto out; 6817 } 6818 6819 if (flags.mask & BR_MCAST_FLOOD) { 6820 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6821 6822 err = chip->info->ops->port_set_mcast_flood(chip, port, 6823 multicast); 6824 if (err) 6825 goto out; 6826 } 6827 6828 if (flags.mask & BR_BCAST_FLOOD) { 6829 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6830 6831 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6832 if (err) 6833 goto out; 6834 } 6835 6836 if (flags.mask & BR_PORT_MAB) { 6837 bool mab = !!(flags.val & BR_PORT_MAB); 6838 6839 mv88e6xxx_port_set_mab(chip, port, mab); 6840 } 6841 6842 if (flags.mask & BR_PORT_LOCKED) { 6843 bool locked = !!(flags.val & BR_PORT_LOCKED); 6844 6845 err = mv88e6xxx_port_set_lock(chip, port, locked); 6846 if (err) 6847 goto out; 6848 } 6849 out: 6850 mv88e6xxx_reg_unlock(chip); 6851 6852 return err; 6853 } 6854 6855 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6856 struct dsa_lag lag, 6857 struct netdev_lag_upper_info *info, 6858 struct netlink_ext_ack *extack) 6859 { 6860 struct mv88e6xxx_chip *chip = ds->priv; 6861 struct dsa_port *dp; 6862 int members = 0; 6863 6864 if (!mv88e6xxx_has_lag(chip)) { 6865 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6866 return false; 6867 } 6868 6869 if (!lag.id) 6870 return false; 6871 6872 dsa_lag_foreach_port(dp, ds->dst, &lag) 6873 /* Includes the port joining the LAG */ 6874 members++; 6875 6876 if (members > 8) { 6877 NL_SET_ERR_MSG_MOD(extack, 6878 "Cannot offload more than 8 LAG ports"); 6879 return false; 6880 } 6881 6882 /* We could potentially relax this to include active 6883 * backup in the future. 6884 */ 6885 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6886 NL_SET_ERR_MSG_MOD(extack, 6887 "Can only offload LAG using hash TX type"); 6888 return false; 6889 } 6890 6891 /* Ideally we would also validate that the hash type matches 6892 * the hardware. Alas, this is always set to unknown on team 6893 * interfaces. 6894 */ 6895 return true; 6896 } 6897 6898 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6899 { 6900 struct mv88e6xxx_chip *chip = ds->priv; 6901 struct dsa_port *dp; 6902 u16 map = 0; 6903 int id; 6904 6905 /* DSA LAG IDs are one-based, hardware is zero-based */ 6906 id = lag.id - 1; 6907 6908 /* Build the map of all ports to distribute flows destined for 6909 * this LAG. This can be either a local user port, or a DSA 6910 * port if the LAG port is on a remote chip. 6911 */ 6912 dsa_lag_foreach_port(dp, ds->dst, &lag) 6913 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6914 6915 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6916 } 6917 6918 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6919 /* Row number corresponds to the number of active members in a 6920 * LAG. Each column states which of the eight hash buckets are 6921 * mapped to the column:th port in the LAG. 6922 * 6923 * Example: In a LAG with three active ports, the second port 6924 * ([2][1]) would be selected for traffic mapped to buckets 6925 * 3,4,5 (0x38). 6926 */ 6927 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6928 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6929 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6930 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6931 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6932 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6933 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6934 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6935 }; 6936 6937 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6938 int num_tx, int nth) 6939 { 6940 u8 active = 0; 6941 int i; 6942 6943 num_tx = num_tx <= 8 ? num_tx : 8; 6944 if (nth < num_tx) 6945 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6946 6947 for (i = 0; i < 8; i++) { 6948 if (BIT(i) & active) 6949 mask[i] |= BIT(port); 6950 } 6951 } 6952 6953 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6954 { 6955 struct mv88e6xxx_chip *chip = ds->priv; 6956 unsigned int id, num_tx; 6957 struct dsa_port *dp; 6958 struct dsa_lag *lag; 6959 int i, err, nth; 6960 u16 mask[8]; 6961 u16 ivec; 6962 6963 /* Assume no port is a member of any LAG. */ 6964 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6965 6966 /* Disable all masks for ports that _are_ members of a LAG. */ 6967 dsa_switch_for_each_port(dp, ds) { 6968 if (!dp->lag) 6969 continue; 6970 6971 ivec &= ~BIT(dp->index); 6972 } 6973 6974 for (i = 0; i < 8; i++) 6975 mask[i] = ivec; 6976 6977 /* Enable the correct subset of masks for all LAG ports that 6978 * are in the Tx set. 6979 */ 6980 dsa_lags_foreach_id(id, ds->dst) { 6981 lag = dsa_lag_by_id(ds->dst, id); 6982 if (!lag) 6983 continue; 6984 6985 num_tx = 0; 6986 dsa_lag_foreach_port(dp, ds->dst, lag) { 6987 if (dp->lag_tx_enabled) 6988 num_tx++; 6989 } 6990 6991 if (!num_tx) 6992 continue; 6993 6994 nth = 0; 6995 dsa_lag_foreach_port(dp, ds->dst, lag) { 6996 if (!dp->lag_tx_enabled) 6997 continue; 6998 6999 if (dp->ds == ds) 7000 mv88e6xxx_lag_set_port_mask(mask, dp->index, 7001 num_tx, nth); 7002 7003 nth++; 7004 } 7005 } 7006 7007 for (i = 0; i < 8; i++) { 7008 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 7009 if (err) 7010 return err; 7011 } 7012 7013 return 0; 7014 } 7015 7016 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 7017 struct dsa_lag lag) 7018 { 7019 int err; 7020 7021 err = mv88e6xxx_lag_sync_masks(ds); 7022 7023 if (!err) 7024 err = mv88e6xxx_lag_sync_map(ds, lag); 7025 7026 return err; 7027 } 7028 7029 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 7030 { 7031 struct mv88e6xxx_chip *chip = ds->priv; 7032 int err; 7033 7034 mv88e6xxx_reg_lock(chip); 7035 err = mv88e6xxx_lag_sync_masks(ds); 7036 mv88e6xxx_reg_unlock(chip); 7037 return err; 7038 } 7039 7040 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7041 struct dsa_lag lag, 7042 struct netdev_lag_upper_info *info, 7043 struct netlink_ext_ack *extack) 7044 { 7045 struct mv88e6xxx_chip *chip = ds->priv; 7046 int err, id; 7047 7048 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7049 return -EOPNOTSUPP; 7050 7051 /* DSA LAG IDs are one-based */ 7052 id = lag.id - 1; 7053 7054 mv88e6xxx_reg_lock(chip); 7055 7056 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7057 if (err) 7058 goto err_unlock; 7059 7060 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7061 if (err) 7062 goto err_clear_trunk; 7063 7064 mv88e6xxx_reg_unlock(chip); 7065 return 0; 7066 7067 err_clear_trunk: 7068 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7069 err_unlock: 7070 mv88e6xxx_reg_unlock(chip); 7071 return err; 7072 } 7073 7074 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7075 struct dsa_lag lag) 7076 { 7077 struct mv88e6xxx_chip *chip = ds->priv; 7078 int err_sync, err_trunk; 7079 7080 mv88e6xxx_reg_lock(chip); 7081 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7082 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7083 mv88e6xxx_reg_unlock(chip); 7084 return err_sync ? : err_trunk; 7085 } 7086 7087 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7088 int port) 7089 { 7090 struct mv88e6xxx_chip *chip = ds->priv; 7091 int err; 7092 7093 mv88e6xxx_reg_lock(chip); 7094 err = mv88e6xxx_lag_sync_masks(ds); 7095 mv88e6xxx_reg_unlock(chip); 7096 return err; 7097 } 7098 7099 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7100 int port, struct dsa_lag lag, 7101 struct netdev_lag_upper_info *info, 7102 struct netlink_ext_ack *extack) 7103 { 7104 struct mv88e6xxx_chip *chip = ds->priv; 7105 int err; 7106 7107 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7108 return -EOPNOTSUPP; 7109 7110 mv88e6xxx_reg_lock(chip); 7111 7112 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7113 if (err) 7114 goto unlock; 7115 7116 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7117 7118 unlock: 7119 mv88e6xxx_reg_unlock(chip); 7120 return err; 7121 } 7122 7123 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7124 int port, struct dsa_lag lag) 7125 { 7126 struct mv88e6xxx_chip *chip = ds->priv; 7127 int err_sync, err_pvt; 7128 7129 mv88e6xxx_reg_lock(chip); 7130 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7131 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7132 mv88e6xxx_reg_unlock(chip); 7133 return err_sync ? : err_pvt; 7134 } 7135 7136 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7137 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7138 .mac_prepare = mv88e6xxx_mac_prepare, 7139 .mac_config = mv88e6xxx_mac_config, 7140 .mac_finish = mv88e6xxx_mac_finish, 7141 .mac_link_down = mv88e6xxx_mac_link_down, 7142 .mac_link_up = mv88e6xxx_mac_link_up, 7143 }; 7144 7145 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7146 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7147 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7148 .setup = mv88e6xxx_setup, 7149 .teardown = mv88e6xxx_teardown, 7150 .port_setup = mv88e6xxx_port_setup, 7151 .port_teardown = mv88e6xxx_port_teardown, 7152 .phylink_get_caps = mv88e6xxx_get_caps, 7153 .get_strings = mv88e6xxx_get_strings, 7154 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7155 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7156 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7157 .get_sset_count = mv88e6xxx_get_sset_count, 7158 .port_max_mtu = mv88e6xxx_get_max_mtu, 7159 .port_change_mtu = mv88e6xxx_change_mtu, 7160 .support_eee = dsa_supports_eee, 7161 .set_mac_eee = mv88e6xxx_set_mac_eee, 7162 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7163 .get_eeprom = mv88e6xxx_get_eeprom, 7164 .set_eeprom = mv88e6xxx_set_eeprom, 7165 .get_regs_len = mv88e6xxx_get_regs_len, 7166 .get_regs = mv88e6xxx_get_regs, 7167 .get_rxnfc = mv88e6xxx_get_rxnfc, 7168 .set_rxnfc = mv88e6xxx_set_rxnfc, 7169 .set_ageing_time = mv88e6xxx_set_ageing_time, 7170 .port_bridge_join = mv88e6xxx_port_bridge_join, 7171 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7172 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7173 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7174 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7175 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7176 .port_fast_age = mv88e6xxx_port_fast_age, 7177 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7178 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7179 .port_vlan_add = mv88e6xxx_port_vlan_add, 7180 .port_vlan_del = mv88e6xxx_port_vlan_del, 7181 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7182 .port_fdb_add = mv88e6xxx_port_fdb_add, 7183 .port_fdb_del = mv88e6xxx_port_fdb_del, 7184 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7185 .port_mdb_add = mv88e6xxx_port_mdb_add, 7186 .port_mdb_del = mv88e6xxx_port_mdb_del, 7187 .port_mirror_add = mv88e6xxx_port_mirror_add, 7188 .port_mirror_del = mv88e6xxx_port_mirror_del, 7189 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7190 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7191 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7192 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7193 .port_txtstamp = mv88e6xxx_port_txtstamp, 7194 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7195 .get_ts_info = mv88e6xxx_get_ts_info, 7196 .devlink_param_get = mv88e6xxx_devlink_param_get, 7197 .devlink_param_set = mv88e6xxx_devlink_param_set, 7198 .devlink_info_get = mv88e6xxx_devlink_info_get, 7199 .port_lag_change = mv88e6xxx_port_lag_change, 7200 .port_lag_join = mv88e6xxx_port_lag_join, 7201 .port_lag_leave = mv88e6xxx_port_lag_leave, 7202 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7203 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7204 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7205 }; 7206 7207 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7208 { 7209 struct device *dev = chip->dev; 7210 struct dsa_switch *ds; 7211 7212 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7213 if (!ds) 7214 return -ENOMEM; 7215 7216 ds->dev = dev; 7217 ds->num_ports = mv88e6xxx_num_ports(chip); 7218 ds->priv = chip; 7219 ds->dev = dev; 7220 ds->ops = &mv88e6xxx_switch_ops; 7221 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7222 ds->ageing_time_min = chip->info->age_time_coeff; 7223 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7224 7225 /* Some chips support up to 32, but that requires enabling the 7226 * 5-bit port mode, which we do not support. 640k^W16 ought to 7227 * be enough for anyone. 7228 */ 7229 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7230 7231 dev_set_drvdata(dev, ds); 7232 7233 return dsa_register_switch(ds); 7234 } 7235 7236 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7237 { 7238 dsa_unregister_switch(chip->ds); 7239 } 7240 7241 static const void *pdata_device_get_match_data(struct device *dev) 7242 { 7243 const struct of_device_id *matches = dev->driver->of_match_table; 7244 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7245 7246 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7247 matches++) { 7248 if (!strcmp(pdata->compatible, matches->compatible)) 7249 return matches->data; 7250 } 7251 return NULL; 7252 } 7253 7254 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7255 * would be lost after a power cycle so prevent it to be suspended. 7256 */ 7257 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7258 { 7259 return -EOPNOTSUPP; 7260 } 7261 7262 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7263 { 7264 return 0; 7265 } 7266 7267 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7268 7269 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7270 { 7271 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7272 const struct mv88e6xxx_info *compat_info = NULL; 7273 struct device *dev = &mdiodev->dev; 7274 struct device_node *np = dev->of_node; 7275 struct mv88e6xxx_chip *chip; 7276 int port; 7277 int err; 7278 7279 if (!np && !pdata) 7280 return -EINVAL; 7281 7282 if (np) 7283 compat_info = of_device_get_match_data(dev); 7284 7285 if (pdata) { 7286 compat_info = pdata_device_get_match_data(dev); 7287 7288 if (!pdata->netdev) 7289 return -EINVAL; 7290 7291 for (port = 0; port < DSA_MAX_PORTS; port++) { 7292 if (!(pdata->enabled_ports & (1 << port))) 7293 continue; 7294 if (strcmp(pdata->cd.port_names[port], "cpu")) 7295 continue; 7296 pdata->cd.netdev[port] = &pdata->netdev->dev; 7297 break; 7298 } 7299 } 7300 7301 if (!compat_info) 7302 return -EINVAL; 7303 7304 chip = mv88e6xxx_alloc_chip(dev); 7305 if (!chip) { 7306 err = -ENOMEM; 7307 goto out; 7308 } 7309 7310 chip->info = compat_info; 7311 7312 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7313 if (IS_ERR(chip->reset)) { 7314 err = PTR_ERR(chip->reset); 7315 goto out; 7316 } 7317 if (chip->reset) 7318 usleep_range(10000, 20000); 7319 7320 /* Detect if the device is configured in single chip addressing mode, 7321 * otherwise continue with address specific smi init/detection. 7322 */ 7323 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7324 if (err) { 7325 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7326 if (err) 7327 goto out; 7328 7329 err = mv88e6xxx_detect(chip); 7330 if (err) 7331 goto out; 7332 } 7333 7334 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7335 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7336 else 7337 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7338 7339 mv88e6xxx_phy_init(chip); 7340 7341 if (chip->info->ops->get_eeprom) { 7342 if (np) 7343 of_property_read_u32(np, "eeprom-length", 7344 &chip->eeprom_len); 7345 else 7346 chip->eeprom_len = pdata->eeprom_len; 7347 } 7348 7349 mv88e6xxx_reg_lock(chip); 7350 err = mv88e6xxx_switch_reset(chip); 7351 mv88e6xxx_reg_unlock(chip); 7352 if (err) 7353 goto out_phy; 7354 7355 if (np) { 7356 chip->irq = of_irq_get(np, 0); 7357 if (chip->irq == -EPROBE_DEFER) { 7358 err = chip->irq; 7359 goto out_phy; 7360 } 7361 } 7362 7363 if (pdata) 7364 chip->irq = pdata->irq; 7365 7366 /* Has to be performed before the MDIO bus is created, because 7367 * the PHYs will link their interrupts to these interrupt 7368 * controllers 7369 */ 7370 mv88e6xxx_reg_lock(chip); 7371 if (chip->irq > 0) 7372 err = mv88e6xxx_g1_irq_setup(chip); 7373 else 7374 err = mv88e6xxx_irq_poll_setup(chip); 7375 mv88e6xxx_reg_unlock(chip); 7376 7377 if (err) 7378 goto out_phy; 7379 7380 if (chip->info->g2_irqs > 0) { 7381 err = mv88e6xxx_g2_irq_setup(chip); 7382 if (err) 7383 goto out_g1_irq; 7384 } 7385 7386 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7387 if (err) 7388 goto out_g2_irq; 7389 7390 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7391 if (err) 7392 goto out_g1_atu_prob_irq; 7393 7394 err = mv88e6xxx_register_switch(chip); 7395 if (err) 7396 goto out_g1_vtu_prob_irq; 7397 7398 return 0; 7399 7400 out_g1_vtu_prob_irq: 7401 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7402 out_g1_atu_prob_irq: 7403 mv88e6xxx_g1_atu_prob_irq_free(chip); 7404 out_g2_irq: 7405 if (chip->info->g2_irqs > 0) 7406 mv88e6xxx_g2_irq_free(chip); 7407 out_g1_irq: 7408 if (chip->irq > 0) 7409 mv88e6xxx_g1_irq_free(chip); 7410 else 7411 mv88e6xxx_irq_poll_free(chip); 7412 out_phy: 7413 mv88e6xxx_phy_destroy(chip); 7414 out: 7415 if (pdata) 7416 dev_put(pdata->netdev); 7417 7418 return err; 7419 } 7420 7421 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7422 { 7423 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7424 struct mv88e6xxx_chip *chip; 7425 7426 if (!ds) 7427 return; 7428 7429 chip = ds->priv; 7430 7431 if (chip->info->ptp_support) { 7432 mv88e6xxx_hwtstamp_free(chip); 7433 mv88e6xxx_ptp_free(chip); 7434 } 7435 7436 mv88e6xxx_unregister_switch(chip); 7437 7438 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7439 mv88e6xxx_g1_atu_prob_irq_free(chip); 7440 7441 if (chip->info->g2_irqs > 0) 7442 mv88e6xxx_g2_irq_free(chip); 7443 7444 if (chip->irq > 0) 7445 mv88e6xxx_g1_irq_free(chip); 7446 else 7447 mv88e6xxx_irq_poll_free(chip); 7448 7449 mv88e6xxx_phy_destroy(chip); 7450 } 7451 7452 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7453 { 7454 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7455 7456 if (!ds) 7457 return; 7458 7459 dsa_switch_shutdown(ds); 7460 7461 dev_set_drvdata(&mdiodev->dev, NULL); 7462 } 7463 7464 static const struct of_device_id mv88e6xxx_of_match[] = { 7465 { 7466 .compatible = "marvell,mv88e6085", 7467 .data = &mv88e6xxx_table[MV88E6085], 7468 }, 7469 { 7470 .compatible = "marvell,mv88e6190", 7471 .data = &mv88e6xxx_table[MV88E6190], 7472 }, 7473 { 7474 .compatible = "marvell,mv88e6250", 7475 .data = &mv88e6xxx_table[MV88E6250], 7476 }, 7477 { /* sentinel */ }, 7478 }; 7479 7480 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7481 7482 static struct mdio_driver mv88e6xxx_driver = { 7483 .probe = mv88e6xxx_probe, 7484 .remove = mv88e6xxx_remove, 7485 .shutdown = mv88e6xxx_shutdown, 7486 .mdiodrv.driver = { 7487 .name = "mv88e6085", 7488 .of_match_table = mv88e6xxx_of_match, 7489 .pm = &mv88e6xxx_pm_ops, 7490 }, 7491 }; 7492 7493 mdio_module_driver(mv88e6xxx_driver); 7494 7495 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7496 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7497 MODULE_LICENSE("GPL"); 7498