1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 /* The 88e6250 family does not have the PHY detect bit. Instead, 475 * report whether the port is internal. 476 */ 477 if (chip->info->family == MV88E6XXX_FAMILY_6250) 478 return port < chip->info->num_internal_phys; 479 480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 481 if (err) { 482 dev_err(chip->dev, 483 "p%d: %s: failed to read port status\n", 484 port, __func__); 485 return err; 486 } 487 488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 489 } 490 491 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 492 struct phylink_link_state *state) 493 { 494 struct mv88e6xxx_chip *chip = ds->priv; 495 int lane; 496 int err; 497 498 mv88e6xxx_reg_lock(chip); 499 lane = mv88e6xxx_serdes_get_lane(chip, port); 500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 502 state); 503 else 504 err = -EOPNOTSUPP; 505 mv88e6xxx_reg_unlock(chip); 506 507 return err; 508 } 509 510 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 511 unsigned int mode, 512 phy_interface_t interface, 513 const unsigned long *advertise) 514 { 515 const struct mv88e6xxx_ops *ops = chip->info->ops; 516 int lane; 517 518 if (ops->serdes_pcs_config) { 519 lane = mv88e6xxx_serdes_get_lane(chip, port); 520 if (lane >= 0) 521 return ops->serdes_pcs_config(chip, port, lane, mode, 522 interface, advertise); 523 } 524 525 return 0; 526 } 527 528 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 529 { 530 struct mv88e6xxx_chip *chip = ds->priv; 531 const struct mv88e6xxx_ops *ops; 532 int err = 0; 533 int lane; 534 535 ops = chip->info->ops; 536 537 if (ops->serdes_pcs_an_restart) { 538 mv88e6xxx_reg_lock(chip); 539 lane = mv88e6xxx_serdes_get_lane(chip, port); 540 if (lane >= 0) 541 err = ops->serdes_pcs_an_restart(chip, port, lane); 542 mv88e6xxx_reg_unlock(chip); 543 544 if (err) 545 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 546 } 547 } 548 549 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 550 unsigned int mode, 551 int speed, int duplex) 552 { 553 const struct mv88e6xxx_ops *ops = chip->info->ops; 554 int lane; 555 556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 557 lane = mv88e6xxx_serdes_get_lane(chip, port); 558 if (lane >= 0) 559 return ops->serdes_pcs_link_up(chip, port, lane, 560 speed, duplex); 561 } 562 563 return 0; 564 } 565 566 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 567 unsigned long *mask, 568 struct phylink_link_state *state) 569 { 570 if (!phy_interface_mode_is_8023z(state->interface)) { 571 /* 10M and 100M are only supported in non-802.3z mode */ 572 phylink_set(mask, 10baseT_Half); 573 phylink_set(mask, 10baseT_Full); 574 phylink_set(mask, 100baseT_Half); 575 phylink_set(mask, 100baseT_Full); 576 } 577 } 578 579 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 580 unsigned long *mask, 581 struct phylink_link_state *state) 582 { 583 /* FIXME: if the port is in 1000Base-X mode, then it only supports 584 * 1000M FD speeds. In this case, CMODE will indicate 5. 585 */ 586 phylink_set(mask, 1000baseT_Full); 587 phylink_set(mask, 1000baseX_Full); 588 589 mv88e6065_phylink_validate(chip, port, mask, state); 590 } 591 592 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 593 unsigned long *mask, 594 struct phylink_link_state *state) 595 { 596 if (port >= 5) 597 phylink_set(mask, 2500baseX_Full); 598 599 /* No ethtool bits for 200Mbps */ 600 phylink_set(mask, 1000baseT_Full); 601 phylink_set(mask, 1000baseX_Full); 602 603 mv88e6065_phylink_validate(chip, port, mask, state); 604 } 605 606 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 607 unsigned long *mask, 608 struct phylink_link_state *state) 609 { 610 /* No ethtool bits for 200Mbps */ 611 phylink_set(mask, 1000baseT_Full); 612 phylink_set(mask, 1000baseX_Full); 613 614 mv88e6065_phylink_validate(chip, port, mask, state); 615 } 616 617 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 618 unsigned long *mask, 619 struct phylink_link_state *state) 620 { 621 if (port >= 9) { 622 phylink_set(mask, 2500baseX_Full); 623 phylink_set(mask, 2500baseT_Full); 624 } 625 626 /* No ethtool bits for 200Mbps */ 627 phylink_set(mask, 1000baseT_Full); 628 phylink_set(mask, 1000baseX_Full); 629 630 mv88e6065_phylink_validate(chip, port, mask, state); 631 } 632 633 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 634 unsigned long *mask, 635 struct phylink_link_state *state) 636 { 637 if (port >= 9) { 638 phylink_set(mask, 10000baseT_Full); 639 phylink_set(mask, 10000baseKR_Full); 640 } 641 642 mv88e6390_phylink_validate(chip, port, mask, state); 643 } 644 645 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 646 unsigned long *mask, 647 struct phylink_link_state *state) 648 { 649 bool is_6191x = 650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 651 652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 653 phylink_set(mask, 10000baseT_Full); 654 phylink_set(mask, 10000baseKR_Full); 655 phylink_set(mask, 10000baseCR_Full); 656 phylink_set(mask, 10000baseSR_Full); 657 phylink_set(mask, 10000baseLR_Full); 658 phylink_set(mask, 10000baseLRM_Full); 659 phylink_set(mask, 10000baseER_Full); 660 phylink_set(mask, 5000baseT_Full); 661 phylink_set(mask, 2500baseX_Full); 662 phylink_set(mask, 2500baseT_Full); 663 } 664 665 phylink_set(mask, 1000baseT_Full); 666 phylink_set(mask, 1000baseX_Full); 667 668 mv88e6065_phylink_validate(chip, port, mask, state); 669 } 670 671 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 672 unsigned long *supported, 673 struct phylink_link_state *state) 674 { 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 676 struct mv88e6xxx_chip *chip = ds->priv; 677 678 /* Allow all the expected bits */ 679 phylink_set(mask, Autoneg); 680 phylink_set(mask, Pause); 681 phylink_set_port_modes(mask); 682 683 if (chip->info->ops->phylink_validate) 684 chip->info->ops->phylink_validate(chip, port, mask, state); 685 686 linkmode_and(supported, supported, mask); 687 linkmode_and(state->advertising, state->advertising, mask); 688 689 /* We can only operate at 2500BaseX or 1000BaseX. If requested 690 * to advertise both, only report advertising at 2500BaseX. 691 */ 692 phylink_helper_basex_speed(state); 693 } 694 695 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 696 unsigned int mode, 697 const struct phylink_link_state *state) 698 { 699 struct mv88e6xxx_chip *chip = ds->priv; 700 struct mv88e6xxx_port *p; 701 int err = 0; 702 703 p = &chip->ports[port]; 704 705 mv88e6xxx_reg_lock(chip); 706 707 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 708 /* In inband mode, the link may come up at any time while the 709 * link is not forced down. Force the link down while we 710 * reconfigure the interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && 713 p->interface != state->interface && 714 chip->info->ops->port_set_link) 715 chip->info->ops->port_set_link(chip, port, 716 LINK_FORCED_DOWN); 717 718 err = mv88e6xxx_port_config_interface(chip, port, 719 state->interface); 720 if (err && err != -EOPNOTSUPP) 721 goto err_unlock; 722 723 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 724 state->interface, 725 state->advertising); 726 /* FIXME: we should restart negotiation if something changed - 727 * which is something we get if we convert to using phylinks 728 * PCS operations. 729 */ 730 if (err > 0) 731 err = 0; 732 } 733 734 /* Undo the forced down state above after completing configuration 735 * irrespective of its state on entry, which allows the link to come 736 * up in the in-band case where there is no separate SERDES. Also 737 * ensure that the link can come up if the PPU is in use and we are 738 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 739 */ 740 if (chip->info->ops->port_set_link && 741 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 742 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 743 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 744 745 p->interface = state->interface; 746 747 err_unlock: 748 mv88e6xxx_reg_unlock(chip); 749 750 if (err && err != -EOPNOTSUPP) 751 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 752 } 753 754 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 755 unsigned int mode, 756 phy_interface_t interface) 757 { 758 struct mv88e6xxx_chip *chip = ds->priv; 759 const struct mv88e6xxx_ops *ops; 760 int err = 0; 761 762 ops = chip->info->ops; 763 764 mv88e6xxx_reg_lock(chip); 765 /* Force the link down if we know the port may not be automatically 766 * updated by the switch or if we are using fixed-link mode. 767 */ 768 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 769 mode == MLO_AN_FIXED) && ops->port_sync_link) 770 err = ops->port_sync_link(chip, port, mode, false); 771 mv88e6xxx_reg_unlock(chip); 772 773 if (err) 774 dev_err(chip->dev, 775 "p%d: failed to force MAC link down\n", port); 776 } 777 778 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 779 unsigned int mode, phy_interface_t interface, 780 struct phy_device *phydev, 781 int speed, int duplex, 782 bool tx_pause, bool rx_pause) 783 { 784 struct mv88e6xxx_chip *chip = ds->priv; 785 const struct mv88e6xxx_ops *ops; 786 int err = 0; 787 788 ops = chip->info->ops; 789 790 mv88e6xxx_reg_lock(chip); 791 /* Configure and force the link up if we know that the port may not 792 * automatically updated by the switch or if we are using fixed-link 793 * mode. 794 */ 795 if (!mv88e6xxx_port_ppu_updates(chip, port) || 796 mode == MLO_AN_FIXED) { 797 /* FIXME: for an automedia port, should we force the link 798 * down here - what if the link comes up due to "other" media 799 * while we're bringing the port up, how is the exclusivity 800 * handled in the Marvell hardware? E.g. port 2 on 88E6390 801 * shared between internal PHY and Serdes. 802 */ 803 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 804 duplex); 805 if (err) 806 goto error; 807 808 if (ops->port_set_speed_duplex) { 809 err = ops->port_set_speed_duplex(chip, port, 810 speed, duplex); 811 if (err && err != -EOPNOTSUPP) 812 goto error; 813 } 814 815 if (ops->port_sync_link) 816 err = ops->port_sync_link(chip, port, mode, true); 817 } 818 error: 819 mv88e6xxx_reg_unlock(chip); 820 821 if (err && err != -EOPNOTSUPP) 822 dev_err(ds->dev, 823 "p%d: failed to configure MAC link up\n", port); 824 } 825 826 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 827 { 828 if (!chip->info->ops->stats_snapshot) 829 return -EOPNOTSUPP; 830 831 return chip->info->ops->stats_snapshot(chip, port); 832 } 833 834 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 835 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 836 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 837 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 838 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 839 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 840 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 841 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 842 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 843 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 844 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 845 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 846 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 847 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 848 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 849 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 850 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 851 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 852 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 853 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 854 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 855 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 856 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 857 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 858 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 859 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 860 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 861 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 862 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 863 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 864 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 865 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 866 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 867 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 868 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 869 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 870 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 871 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 872 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 873 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 874 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 875 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 876 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 877 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 878 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 879 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 880 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 881 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 882 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 883 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 884 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 885 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 886 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 887 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 888 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 889 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 890 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 891 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 892 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 893 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 894 }; 895 896 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 897 struct mv88e6xxx_hw_stat *s, 898 int port, u16 bank1_select, 899 u16 histogram) 900 { 901 u32 low; 902 u32 high = 0; 903 u16 reg = 0; 904 int err; 905 u64 value; 906 907 switch (s->type) { 908 case STATS_TYPE_PORT: 909 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 910 if (err) 911 return U64_MAX; 912 913 low = reg; 914 if (s->size == 4) { 915 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 916 if (err) 917 return U64_MAX; 918 low |= ((u32)reg) << 16; 919 } 920 break; 921 case STATS_TYPE_BANK1: 922 reg = bank1_select; 923 fallthrough; 924 case STATS_TYPE_BANK0: 925 reg |= s->reg | histogram; 926 mv88e6xxx_g1_stats_read(chip, reg, &low); 927 if (s->size == 8) 928 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 929 break; 930 default: 931 return U64_MAX; 932 } 933 value = (((u64)high) << 32) | low; 934 return value; 935 } 936 937 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 938 uint8_t *data, int types) 939 { 940 struct mv88e6xxx_hw_stat *stat; 941 int i, j; 942 943 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 944 stat = &mv88e6xxx_hw_stats[i]; 945 if (stat->type & types) { 946 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 947 ETH_GSTRING_LEN); 948 j++; 949 } 950 } 951 952 return j; 953 } 954 955 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 956 uint8_t *data) 957 { 958 return mv88e6xxx_stats_get_strings(chip, data, 959 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 960 } 961 962 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 963 uint8_t *data) 964 { 965 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 966 } 967 968 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 969 uint8_t *data) 970 { 971 return mv88e6xxx_stats_get_strings(chip, data, 972 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 973 } 974 975 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 976 "atu_member_violation", 977 "atu_miss_violation", 978 "atu_full_violation", 979 "vtu_member_violation", 980 "vtu_miss_violation", 981 }; 982 983 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 984 { 985 unsigned int i; 986 987 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 988 strlcpy(data + i * ETH_GSTRING_LEN, 989 mv88e6xxx_atu_vtu_stats_strings[i], 990 ETH_GSTRING_LEN); 991 } 992 993 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 994 u32 stringset, uint8_t *data) 995 { 996 struct mv88e6xxx_chip *chip = ds->priv; 997 int count = 0; 998 999 if (stringset != ETH_SS_STATS) 1000 return; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 1004 if (chip->info->ops->stats_get_strings) 1005 count = chip->info->ops->stats_get_strings(chip, data); 1006 1007 if (chip->info->ops->serdes_get_strings) { 1008 data += count * ETH_GSTRING_LEN; 1009 count = chip->info->ops->serdes_get_strings(chip, port, data); 1010 } 1011 1012 data += count * ETH_GSTRING_LEN; 1013 mv88e6xxx_atu_vtu_get_strings(data); 1014 1015 mv88e6xxx_reg_unlock(chip); 1016 } 1017 1018 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1019 int types) 1020 { 1021 struct mv88e6xxx_hw_stat *stat; 1022 int i, j; 1023 1024 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1025 stat = &mv88e6xxx_hw_stats[i]; 1026 if (stat->type & types) 1027 j++; 1028 } 1029 return j; 1030 } 1031 1032 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1033 { 1034 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1035 STATS_TYPE_PORT); 1036 } 1037 1038 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1039 { 1040 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1041 } 1042 1043 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1044 { 1045 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1046 STATS_TYPE_BANK1); 1047 } 1048 1049 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1050 { 1051 struct mv88e6xxx_chip *chip = ds->priv; 1052 int serdes_count = 0; 1053 int count = 0; 1054 1055 if (sset != ETH_SS_STATS) 1056 return 0; 1057 1058 mv88e6xxx_reg_lock(chip); 1059 if (chip->info->ops->stats_get_sset_count) 1060 count = chip->info->ops->stats_get_sset_count(chip); 1061 if (count < 0) 1062 goto out; 1063 1064 if (chip->info->ops->serdes_get_sset_count) 1065 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1066 port); 1067 if (serdes_count < 0) { 1068 count = serdes_count; 1069 goto out; 1070 } 1071 count += serdes_count; 1072 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1073 1074 out: 1075 mv88e6xxx_reg_unlock(chip); 1076 1077 return count; 1078 } 1079 1080 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1081 uint64_t *data, int types, 1082 u16 bank1_select, u16 histogram) 1083 { 1084 struct mv88e6xxx_hw_stat *stat; 1085 int i, j; 1086 1087 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1088 stat = &mv88e6xxx_hw_stats[i]; 1089 if (stat->type & types) { 1090 mv88e6xxx_reg_lock(chip); 1091 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1092 bank1_select, 1093 histogram); 1094 mv88e6xxx_reg_unlock(chip); 1095 1096 j++; 1097 } 1098 } 1099 return j; 1100 } 1101 1102 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1103 uint64_t *data) 1104 { 1105 return mv88e6xxx_stats_get_stats(chip, port, data, 1106 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1107 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1108 } 1109 1110 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1111 uint64_t *data) 1112 { 1113 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1114 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1115 } 1116 1117 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1118 uint64_t *data) 1119 { 1120 return mv88e6xxx_stats_get_stats(chip, port, data, 1121 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1122 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1123 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1124 } 1125 1126 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1127 uint64_t *data) 1128 { 1129 return mv88e6xxx_stats_get_stats(chip, port, data, 1130 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1131 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1132 0); 1133 } 1134 1135 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1136 uint64_t *data) 1137 { 1138 *data++ = chip->ports[port].atu_member_violation; 1139 *data++ = chip->ports[port].atu_miss_violation; 1140 *data++ = chip->ports[port].atu_full_violation; 1141 *data++ = chip->ports[port].vtu_member_violation; 1142 *data++ = chip->ports[port].vtu_miss_violation; 1143 } 1144 1145 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1146 uint64_t *data) 1147 { 1148 int count = 0; 1149 1150 if (chip->info->ops->stats_get_stats) 1151 count = chip->info->ops->stats_get_stats(chip, port, data); 1152 1153 mv88e6xxx_reg_lock(chip); 1154 if (chip->info->ops->serdes_get_stats) { 1155 data += count; 1156 count = chip->info->ops->serdes_get_stats(chip, port, data); 1157 } 1158 data += count; 1159 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1160 mv88e6xxx_reg_unlock(chip); 1161 } 1162 1163 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1164 uint64_t *data) 1165 { 1166 struct mv88e6xxx_chip *chip = ds->priv; 1167 int ret; 1168 1169 mv88e6xxx_reg_lock(chip); 1170 1171 ret = mv88e6xxx_stats_snapshot(chip, port); 1172 mv88e6xxx_reg_unlock(chip); 1173 1174 if (ret < 0) 1175 return; 1176 1177 mv88e6xxx_get_stats(chip, port, data); 1178 1179 } 1180 1181 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1182 { 1183 struct mv88e6xxx_chip *chip = ds->priv; 1184 int len; 1185 1186 len = 32 * sizeof(u16); 1187 if (chip->info->ops->serdes_get_regs_len) 1188 len += chip->info->ops->serdes_get_regs_len(chip, port); 1189 1190 return len; 1191 } 1192 1193 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1194 struct ethtool_regs *regs, void *_p) 1195 { 1196 struct mv88e6xxx_chip *chip = ds->priv; 1197 int err; 1198 u16 reg; 1199 u16 *p = _p; 1200 int i; 1201 1202 regs->version = chip->info->prod_num; 1203 1204 memset(p, 0xff, 32 * sizeof(u16)); 1205 1206 mv88e6xxx_reg_lock(chip); 1207 1208 for (i = 0; i < 32; i++) { 1209 1210 err = mv88e6xxx_port_read(chip, port, i, ®); 1211 if (!err) 1212 p[i] = reg; 1213 } 1214 1215 if (chip->info->ops->serdes_get_regs) 1216 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1217 1218 mv88e6xxx_reg_unlock(chip); 1219 } 1220 1221 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1222 struct ethtool_eee *e) 1223 { 1224 /* Nothing to do on the port's MAC */ 1225 return 0; 1226 } 1227 1228 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1229 struct ethtool_eee *e) 1230 { 1231 /* Nothing to do on the port's MAC */ 1232 return 0; 1233 } 1234 1235 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1236 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1237 { 1238 struct dsa_switch *ds = chip->ds; 1239 struct dsa_switch_tree *dst = ds->dst; 1240 struct dsa_port *dp, *other_dp; 1241 bool found = false; 1242 u16 pvlan; 1243 1244 /* dev is a physical switch */ 1245 if (dev <= dst->last_switch) { 1246 list_for_each_entry(dp, &dst->ports, list) { 1247 if (dp->ds->index == dev && dp->index == port) { 1248 /* dp might be a DSA link or a user port, so it 1249 * might or might not have a bridge. 1250 * Use the "found" variable for both cases. 1251 */ 1252 found = true; 1253 break; 1254 } 1255 } 1256 /* dev is a virtual bridge */ 1257 } else { 1258 list_for_each_entry(dp, &dst->ports, list) { 1259 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1260 1261 if (!bridge_num) 1262 continue; 1263 1264 if (bridge_num + dst->last_switch != dev) 1265 continue; 1266 1267 found = true; 1268 break; 1269 } 1270 } 1271 1272 /* Prevent frames from unknown switch or virtual bridge */ 1273 if (!found) 1274 return 0; 1275 1276 /* Frames from DSA links and CPU ports can egress any local port */ 1277 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1278 return mv88e6xxx_port_mask(chip); 1279 1280 pvlan = 0; 1281 1282 /* Frames from user ports can egress any local DSA links and CPU ports, 1283 * as well as any local member of their bridge group. 1284 */ 1285 dsa_switch_for_each_port(other_dp, ds) 1286 if (other_dp->type == DSA_PORT_TYPE_CPU || 1287 other_dp->type == DSA_PORT_TYPE_DSA || 1288 dsa_port_bridge_same(dp, other_dp)) 1289 pvlan |= BIT(other_dp->index); 1290 1291 return pvlan; 1292 } 1293 1294 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1295 { 1296 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1297 1298 /* prevent frames from going back out of the port they came in on */ 1299 output_ports &= ~BIT(port); 1300 1301 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1302 } 1303 1304 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1305 u8 state) 1306 { 1307 struct mv88e6xxx_chip *chip = ds->priv; 1308 int err; 1309 1310 mv88e6xxx_reg_lock(chip); 1311 err = mv88e6xxx_port_set_state(chip, port, state); 1312 mv88e6xxx_reg_unlock(chip); 1313 1314 if (err) 1315 dev_err(ds->dev, "p%d: failed to update state\n", port); 1316 } 1317 1318 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 int err; 1321 1322 if (chip->info->ops->ieee_pri_map) { 1323 err = chip->info->ops->ieee_pri_map(chip); 1324 if (err) 1325 return err; 1326 } 1327 1328 if (chip->info->ops->ip_pri_map) { 1329 err = chip->info->ops->ip_pri_map(chip); 1330 if (err) 1331 return err; 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1338 { 1339 struct dsa_switch *ds = chip->ds; 1340 int target, port; 1341 int err; 1342 1343 if (!chip->info->global2_addr) 1344 return 0; 1345 1346 /* Initialize the routing port to the 32 possible target devices */ 1347 for (target = 0; target < 32; target++) { 1348 port = dsa_routing_port(ds, target); 1349 if (port == ds->num_ports) 1350 port = 0x1f; 1351 1352 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1353 if (err) 1354 return err; 1355 } 1356 1357 if (chip->info->ops->set_cascade_port) { 1358 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1359 err = chip->info->ops->set_cascade_port(chip, port); 1360 if (err) 1361 return err; 1362 } 1363 1364 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1365 if (err) 1366 return err; 1367 1368 return 0; 1369 } 1370 1371 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1372 { 1373 /* Clear all trunk masks and mapping */ 1374 if (chip->info->global2_addr) 1375 return mv88e6xxx_g2_trunk_clear(chip); 1376 1377 return 0; 1378 } 1379 1380 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1381 { 1382 if (chip->info->ops->rmu_disable) 1383 return chip->info->ops->rmu_disable(chip); 1384 1385 return 0; 1386 } 1387 1388 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1389 { 1390 if (chip->info->ops->pot_clear) 1391 return chip->info->ops->pot_clear(chip); 1392 1393 return 0; 1394 } 1395 1396 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1397 { 1398 if (chip->info->ops->mgmt_rsvd2cpu) 1399 return chip->info->ops->mgmt_rsvd2cpu(chip); 1400 1401 return 0; 1402 } 1403 1404 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1405 { 1406 int err; 1407 1408 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1409 if (err) 1410 return err; 1411 1412 /* The chips that have a "learn2all" bit in Global1, ATU 1413 * Control are precisely those whose port registers have a 1414 * Message Port bit in Port Control 1 and hence implement 1415 * ->port_setup_message_port. 1416 */ 1417 if (chip->info->ops->port_setup_message_port) { 1418 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1419 if (err) 1420 return err; 1421 } 1422 1423 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1424 } 1425 1426 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1427 { 1428 int port; 1429 int err; 1430 1431 if (!chip->info->ops->irl_init_all) 1432 return 0; 1433 1434 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1435 /* Disable ingress rate limiting by resetting all per port 1436 * ingress rate limit resources to their initial state. 1437 */ 1438 err = chip->info->ops->irl_init_all(chip, port); 1439 if (err) 1440 return err; 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1447 { 1448 if (chip->info->ops->set_switch_mac) { 1449 u8 addr[ETH_ALEN]; 1450 1451 eth_random_addr(addr); 1452 1453 return chip->info->ops->set_switch_mac(chip, addr); 1454 } 1455 1456 return 0; 1457 } 1458 1459 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1460 { 1461 struct dsa_switch_tree *dst = chip->ds->dst; 1462 struct dsa_switch *ds; 1463 struct dsa_port *dp; 1464 u16 pvlan = 0; 1465 1466 if (!mv88e6xxx_has_pvt(chip)) 1467 return 0; 1468 1469 /* Skip the local source device, which uses in-chip port VLAN */ 1470 if (dev != chip->ds->index) { 1471 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1472 1473 ds = dsa_switch_find(dst->index, dev); 1474 dp = ds ? dsa_to_port(ds, port) : NULL; 1475 if (dp && dp->lag_dev) { 1476 /* As the PVT is used to limit flooding of 1477 * FORWARD frames, which use the LAG ID as the 1478 * source port, we must translate dev/port to 1479 * the special "LAG device" in the PVT, using 1480 * the LAG ID as the port number. 1481 */ 1482 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1483 port = dsa_lag_id(dst, dp->lag_dev); 1484 } 1485 } 1486 1487 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1488 } 1489 1490 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1491 { 1492 int dev, port; 1493 int err; 1494 1495 if (!mv88e6xxx_has_pvt(chip)) 1496 return 0; 1497 1498 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1499 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1500 */ 1501 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1502 if (err) 1503 return err; 1504 1505 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1506 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1507 err = mv88e6xxx_pvt_map(chip, dev, port); 1508 if (err) 1509 return err; 1510 } 1511 } 1512 1513 return 0; 1514 } 1515 1516 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1517 { 1518 struct mv88e6xxx_chip *chip = ds->priv; 1519 int err; 1520 1521 if (dsa_to_port(ds, port)->lag_dev) 1522 /* Hardware is incapable of fast-aging a LAG through a 1523 * regular ATU move operation. Until we have something 1524 * more fancy in place this is a no-op. 1525 */ 1526 return; 1527 1528 mv88e6xxx_reg_lock(chip); 1529 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1530 mv88e6xxx_reg_unlock(chip); 1531 1532 if (err) 1533 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1534 } 1535 1536 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1537 { 1538 if (!mv88e6xxx_max_vid(chip)) 1539 return 0; 1540 1541 return mv88e6xxx_g1_vtu_flush(chip); 1542 } 1543 1544 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1545 struct mv88e6xxx_vtu_entry *entry) 1546 { 1547 int err; 1548 1549 if (!chip->info->ops->vtu_getnext) 1550 return -EOPNOTSUPP; 1551 1552 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1553 entry->valid = false; 1554 1555 err = chip->info->ops->vtu_getnext(chip, entry); 1556 1557 if (entry->vid != vid) 1558 entry->valid = false; 1559 1560 return err; 1561 } 1562 1563 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1564 int (*cb)(struct mv88e6xxx_chip *chip, 1565 const struct mv88e6xxx_vtu_entry *entry, 1566 void *priv), 1567 void *priv) 1568 { 1569 struct mv88e6xxx_vtu_entry entry = { 1570 .vid = mv88e6xxx_max_vid(chip), 1571 .valid = false, 1572 }; 1573 int err; 1574 1575 if (!chip->info->ops->vtu_getnext) 1576 return -EOPNOTSUPP; 1577 1578 do { 1579 err = chip->info->ops->vtu_getnext(chip, &entry); 1580 if (err) 1581 return err; 1582 1583 if (!entry.valid) 1584 break; 1585 1586 err = cb(chip, &entry, priv); 1587 if (err) 1588 return err; 1589 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1590 1591 return 0; 1592 } 1593 1594 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1595 struct mv88e6xxx_vtu_entry *entry) 1596 { 1597 if (!chip->info->ops->vtu_loadpurge) 1598 return -EOPNOTSUPP; 1599 1600 return chip->info->ops->vtu_loadpurge(chip, entry); 1601 } 1602 1603 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1604 const struct mv88e6xxx_vtu_entry *entry, 1605 void *_fid_bitmap) 1606 { 1607 unsigned long *fid_bitmap = _fid_bitmap; 1608 1609 set_bit(entry->fid, fid_bitmap); 1610 return 0; 1611 } 1612 1613 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1614 { 1615 int i, err; 1616 u16 fid; 1617 1618 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1619 1620 /* Set every FID bit used by the (un)bridged ports */ 1621 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1622 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1623 if (err) 1624 return err; 1625 1626 set_bit(fid, fid_bitmap); 1627 } 1628 1629 /* Set every FID bit used by the VLAN entries */ 1630 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1631 } 1632 1633 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1634 { 1635 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1636 int err; 1637 1638 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1639 if (err) 1640 return err; 1641 1642 /* The reset value 0x000 is used to indicate that multiple address 1643 * databases are not needed. Return the next positive available. 1644 */ 1645 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1646 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1647 return -ENOSPC; 1648 1649 /* Clear the database */ 1650 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1651 } 1652 1653 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1654 u16 vid) 1655 { 1656 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1657 struct mv88e6xxx_chip *chip = ds->priv; 1658 struct mv88e6xxx_vtu_entry vlan; 1659 int err; 1660 1661 /* DSA and CPU ports have to be members of multiple vlans */ 1662 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1663 return 0; 1664 1665 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1666 if (err) 1667 return err; 1668 1669 if (!vlan.valid) 1670 return 0; 1671 1672 dsa_switch_for_each_user_port(other_dp, ds) { 1673 struct net_device *other_br; 1674 1675 if (vlan.member[other_dp->index] == 1676 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1677 continue; 1678 1679 if (dsa_port_bridge_same(dp, other_dp)) 1680 break; /* same bridge, check next VLAN */ 1681 1682 other_br = dsa_port_bridge_dev_get(other_dp); 1683 if (!other_br) 1684 continue; 1685 1686 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1687 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1688 return -EOPNOTSUPP; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1695 { 1696 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1697 struct net_device *br = dsa_port_bridge_dev_get(dp); 1698 struct mv88e6xxx_port *p = &chip->ports[port]; 1699 u16 pvid = MV88E6XXX_VID_STANDALONE; 1700 bool drop_untagged = false; 1701 int err; 1702 1703 if (br) { 1704 if (br_vlan_enabled(br)) { 1705 pvid = p->bridge_pvid.vid; 1706 drop_untagged = !p->bridge_pvid.valid; 1707 } else { 1708 pvid = MV88E6XXX_VID_BRIDGED; 1709 } 1710 } 1711 1712 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1713 if (err) 1714 return err; 1715 1716 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1717 } 1718 1719 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1720 bool vlan_filtering, 1721 struct netlink_ext_ack *extack) 1722 { 1723 struct mv88e6xxx_chip *chip = ds->priv; 1724 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1725 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1726 int err; 1727 1728 if (!mv88e6xxx_max_vid(chip)) 1729 return -EOPNOTSUPP; 1730 1731 mv88e6xxx_reg_lock(chip); 1732 1733 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1734 if (err) 1735 goto unlock; 1736 1737 err = mv88e6xxx_port_commit_pvid(chip, port); 1738 if (err) 1739 goto unlock; 1740 1741 unlock: 1742 mv88e6xxx_reg_unlock(chip); 1743 1744 return err; 1745 } 1746 1747 static int 1748 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1749 const struct switchdev_obj_port_vlan *vlan) 1750 { 1751 struct mv88e6xxx_chip *chip = ds->priv; 1752 int err; 1753 1754 if (!mv88e6xxx_max_vid(chip)) 1755 return -EOPNOTSUPP; 1756 1757 /* If the requested port doesn't belong to the same bridge as the VLAN 1758 * members, do not support it (yet) and fallback to software VLAN. 1759 */ 1760 mv88e6xxx_reg_lock(chip); 1761 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1762 mv88e6xxx_reg_unlock(chip); 1763 1764 return err; 1765 } 1766 1767 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1768 const unsigned char *addr, u16 vid, 1769 u8 state) 1770 { 1771 struct mv88e6xxx_atu_entry entry; 1772 struct mv88e6xxx_vtu_entry vlan; 1773 u16 fid; 1774 int err; 1775 1776 /* Ports have two private address databases: one for when the port is 1777 * standalone and one for when the port is under a bridge and the 1778 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1779 * address database to remain 100% empty, so we never load an ATU entry 1780 * into a standalone port's database. Therefore, translate the null 1781 * VLAN ID into the port's database used for VLAN-unaware bridging. 1782 */ 1783 if (vid == 0) { 1784 fid = MV88E6XXX_FID_BRIDGED; 1785 } else { 1786 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1787 if (err) 1788 return err; 1789 1790 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1791 if (!vlan.valid) 1792 return -EOPNOTSUPP; 1793 1794 fid = vlan.fid; 1795 } 1796 1797 entry.state = 0; 1798 ether_addr_copy(entry.mac, addr); 1799 eth_addr_dec(entry.mac); 1800 1801 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1802 if (err) 1803 return err; 1804 1805 /* Initialize a fresh ATU entry if it isn't found */ 1806 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1807 memset(&entry, 0, sizeof(entry)); 1808 ether_addr_copy(entry.mac, addr); 1809 } 1810 1811 /* Purge the ATU entry only if no port is using it anymore */ 1812 if (!state) { 1813 entry.portvec &= ~BIT(port); 1814 if (!entry.portvec) 1815 entry.state = 0; 1816 } else { 1817 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1818 entry.portvec = BIT(port); 1819 else 1820 entry.portvec |= BIT(port); 1821 1822 entry.state = state; 1823 } 1824 1825 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1826 } 1827 1828 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1829 const struct mv88e6xxx_policy *policy) 1830 { 1831 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1832 enum mv88e6xxx_policy_action action = policy->action; 1833 const u8 *addr = policy->addr; 1834 u16 vid = policy->vid; 1835 u8 state; 1836 int err; 1837 int id; 1838 1839 if (!chip->info->ops->port_set_policy) 1840 return -EOPNOTSUPP; 1841 1842 switch (mapping) { 1843 case MV88E6XXX_POLICY_MAPPING_DA: 1844 case MV88E6XXX_POLICY_MAPPING_SA: 1845 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1846 state = 0; /* Dissociate the port and address */ 1847 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1848 is_multicast_ether_addr(addr)) 1849 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1850 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1851 is_unicast_ether_addr(addr)) 1852 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1853 else 1854 return -EOPNOTSUPP; 1855 1856 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1857 state); 1858 if (err) 1859 return err; 1860 break; 1861 default: 1862 return -EOPNOTSUPP; 1863 } 1864 1865 /* Skip the port's policy clearing if the mapping is still in use */ 1866 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1867 idr_for_each_entry(&chip->policies, policy, id) 1868 if (policy->port == port && 1869 policy->mapping == mapping && 1870 policy->action != action) 1871 return 0; 1872 1873 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1874 } 1875 1876 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1877 struct ethtool_rx_flow_spec *fs) 1878 { 1879 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1880 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1881 enum mv88e6xxx_policy_mapping mapping; 1882 enum mv88e6xxx_policy_action action; 1883 struct mv88e6xxx_policy *policy; 1884 u16 vid = 0; 1885 u8 *addr; 1886 int err; 1887 int id; 1888 1889 if (fs->location != RX_CLS_LOC_ANY) 1890 return -EINVAL; 1891 1892 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1893 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1894 else 1895 return -EOPNOTSUPP; 1896 1897 switch (fs->flow_type & ~FLOW_EXT) { 1898 case ETHER_FLOW: 1899 if (!is_zero_ether_addr(mac_mask->h_dest) && 1900 is_zero_ether_addr(mac_mask->h_source)) { 1901 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1902 addr = mac_entry->h_dest; 1903 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1904 !is_zero_ether_addr(mac_mask->h_source)) { 1905 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1906 addr = mac_entry->h_source; 1907 } else { 1908 /* Cannot support DA and SA mapping in the same rule */ 1909 return -EOPNOTSUPP; 1910 } 1911 break; 1912 default: 1913 return -EOPNOTSUPP; 1914 } 1915 1916 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1917 if (fs->m_ext.vlan_tci != htons(0xffff)) 1918 return -EOPNOTSUPP; 1919 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1920 } 1921 1922 idr_for_each_entry(&chip->policies, policy, id) { 1923 if (policy->port == port && policy->mapping == mapping && 1924 policy->action == action && policy->vid == vid && 1925 ether_addr_equal(policy->addr, addr)) 1926 return -EEXIST; 1927 } 1928 1929 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1930 if (!policy) 1931 return -ENOMEM; 1932 1933 fs->location = 0; 1934 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1935 GFP_KERNEL); 1936 if (err) { 1937 devm_kfree(chip->dev, policy); 1938 return err; 1939 } 1940 1941 memcpy(&policy->fs, fs, sizeof(*fs)); 1942 ether_addr_copy(policy->addr, addr); 1943 policy->mapping = mapping; 1944 policy->action = action; 1945 policy->port = port; 1946 policy->vid = vid; 1947 1948 err = mv88e6xxx_policy_apply(chip, port, policy); 1949 if (err) { 1950 idr_remove(&chip->policies, fs->location); 1951 devm_kfree(chip->dev, policy); 1952 return err; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1959 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1960 { 1961 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1962 struct mv88e6xxx_chip *chip = ds->priv; 1963 struct mv88e6xxx_policy *policy; 1964 int err; 1965 int id; 1966 1967 mv88e6xxx_reg_lock(chip); 1968 1969 switch (rxnfc->cmd) { 1970 case ETHTOOL_GRXCLSRLCNT: 1971 rxnfc->data = 0; 1972 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1973 rxnfc->rule_cnt = 0; 1974 idr_for_each_entry(&chip->policies, policy, id) 1975 if (policy->port == port) 1976 rxnfc->rule_cnt++; 1977 err = 0; 1978 break; 1979 case ETHTOOL_GRXCLSRULE: 1980 err = -ENOENT; 1981 policy = idr_find(&chip->policies, fs->location); 1982 if (policy) { 1983 memcpy(fs, &policy->fs, sizeof(*fs)); 1984 err = 0; 1985 } 1986 break; 1987 case ETHTOOL_GRXCLSRLALL: 1988 rxnfc->data = 0; 1989 rxnfc->rule_cnt = 0; 1990 idr_for_each_entry(&chip->policies, policy, id) 1991 if (policy->port == port) 1992 rule_locs[rxnfc->rule_cnt++] = id; 1993 err = 0; 1994 break; 1995 default: 1996 err = -EOPNOTSUPP; 1997 break; 1998 } 1999 2000 mv88e6xxx_reg_unlock(chip); 2001 2002 return err; 2003 } 2004 2005 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2006 struct ethtool_rxnfc *rxnfc) 2007 { 2008 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2009 struct mv88e6xxx_chip *chip = ds->priv; 2010 struct mv88e6xxx_policy *policy; 2011 int err; 2012 2013 mv88e6xxx_reg_lock(chip); 2014 2015 switch (rxnfc->cmd) { 2016 case ETHTOOL_SRXCLSRLINS: 2017 err = mv88e6xxx_policy_insert(chip, port, fs); 2018 break; 2019 case ETHTOOL_SRXCLSRLDEL: 2020 err = -ENOENT; 2021 policy = idr_remove(&chip->policies, fs->location); 2022 if (policy) { 2023 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2024 err = mv88e6xxx_policy_apply(chip, port, policy); 2025 devm_kfree(chip->dev, policy); 2026 } 2027 break; 2028 default: 2029 err = -EOPNOTSUPP; 2030 break; 2031 } 2032 2033 mv88e6xxx_reg_unlock(chip); 2034 2035 return err; 2036 } 2037 2038 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2039 u16 vid) 2040 { 2041 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2042 u8 broadcast[ETH_ALEN]; 2043 2044 eth_broadcast_addr(broadcast); 2045 2046 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2047 } 2048 2049 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2050 { 2051 int port; 2052 int err; 2053 2054 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2055 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2056 struct net_device *brport; 2057 2058 if (dsa_is_unused_port(chip->ds, port)) 2059 continue; 2060 2061 brport = dsa_port_to_bridge_port(dp); 2062 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2063 /* Skip bridged user ports where broadcast 2064 * flooding is disabled. 2065 */ 2066 continue; 2067 2068 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2069 if (err) 2070 return err; 2071 } 2072 2073 return 0; 2074 } 2075 2076 struct mv88e6xxx_port_broadcast_sync_ctx { 2077 int port; 2078 bool flood; 2079 }; 2080 2081 static int 2082 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2083 const struct mv88e6xxx_vtu_entry *vlan, 2084 void *_ctx) 2085 { 2086 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2087 u8 broadcast[ETH_ALEN]; 2088 u8 state; 2089 2090 if (ctx->flood) 2091 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2092 else 2093 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2094 2095 eth_broadcast_addr(broadcast); 2096 2097 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2098 vlan->vid, state); 2099 } 2100 2101 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2102 bool flood) 2103 { 2104 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2105 .port = port, 2106 .flood = flood, 2107 }; 2108 struct mv88e6xxx_vtu_entry vid0 = { 2109 .vid = 0, 2110 }; 2111 int err; 2112 2113 /* Update the port's private database... */ 2114 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2115 if (err) 2116 return err; 2117 2118 /* ...and the database for all VLANs. */ 2119 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2120 &ctx); 2121 } 2122 2123 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2124 u16 vid, u8 member, bool warn) 2125 { 2126 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2127 struct mv88e6xxx_vtu_entry vlan; 2128 int i, err; 2129 2130 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2131 if (err) 2132 return err; 2133 2134 if (!vlan.valid) { 2135 memset(&vlan, 0, sizeof(vlan)); 2136 2137 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2138 if (err) 2139 return err; 2140 2141 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2142 if (i == port) 2143 vlan.member[i] = member; 2144 else 2145 vlan.member[i] = non_member; 2146 2147 vlan.vid = vid; 2148 vlan.valid = true; 2149 2150 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2151 if (err) 2152 return err; 2153 2154 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2155 if (err) 2156 return err; 2157 } else if (vlan.member[port] != member) { 2158 vlan.member[port] = member; 2159 2160 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2161 if (err) 2162 return err; 2163 } else if (warn) { 2164 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2165 port, vid); 2166 } 2167 2168 return 0; 2169 } 2170 2171 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2172 const struct switchdev_obj_port_vlan *vlan, 2173 struct netlink_ext_ack *extack) 2174 { 2175 struct mv88e6xxx_chip *chip = ds->priv; 2176 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2177 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2178 struct mv88e6xxx_port *p = &chip->ports[port]; 2179 bool warn; 2180 u8 member; 2181 int err; 2182 2183 if (!vlan->vid) 2184 return 0; 2185 2186 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2187 if (err) 2188 return err; 2189 2190 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2191 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2192 else if (untagged) 2193 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2194 else 2195 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2196 2197 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2198 * and then the CPU port. Do not warn for duplicates for the CPU port. 2199 */ 2200 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2201 2202 mv88e6xxx_reg_lock(chip); 2203 2204 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2205 if (err) { 2206 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2207 vlan->vid, untagged ? 'u' : 't'); 2208 goto out; 2209 } 2210 2211 if (pvid) { 2212 p->bridge_pvid.vid = vlan->vid; 2213 p->bridge_pvid.valid = true; 2214 2215 err = mv88e6xxx_port_commit_pvid(chip, port); 2216 if (err) 2217 goto out; 2218 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2219 /* The old pvid was reinstalled as a non-pvid VLAN */ 2220 p->bridge_pvid.valid = false; 2221 2222 err = mv88e6xxx_port_commit_pvid(chip, port); 2223 if (err) 2224 goto out; 2225 } 2226 2227 out: 2228 mv88e6xxx_reg_unlock(chip); 2229 2230 return err; 2231 } 2232 2233 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2234 int port, u16 vid) 2235 { 2236 struct mv88e6xxx_vtu_entry vlan; 2237 int i, err; 2238 2239 if (!vid) 2240 return 0; 2241 2242 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2243 if (err) 2244 return err; 2245 2246 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2247 * tell switchdev that this VLAN is likely handled in software. 2248 */ 2249 if (!vlan.valid || 2250 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2251 return -EOPNOTSUPP; 2252 2253 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2254 2255 /* keep the VLAN unless all ports are excluded */ 2256 vlan.valid = false; 2257 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2258 if (vlan.member[i] != 2259 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2260 vlan.valid = true; 2261 break; 2262 } 2263 } 2264 2265 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2266 if (err) 2267 return err; 2268 2269 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2270 } 2271 2272 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2273 const struct switchdev_obj_port_vlan *vlan) 2274 { 2275 struct mv88e6xxx_chip *chip = ds->priv; 2276 struct mv88e6xxx_port *p = &chip->ports[port]; 2277 int err = 0; 2278 u16 pvid; 2279 2280 if (!mv88e6xxx_max_vid(chip)) 2281 return -EOPNOTSUPP; 2282 2283 mv88e6xxx_reg_lock(chip); 2284 2285 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2286 if (err) 2287 goto unlock; 2288 2289 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2290 if (err) 2291 goto unlock; 2292 2293 if (vlan->vid == pvid) { 2294 p->bridge_pvid.valid = false; 2295 2296 err = mv88e6xxx_port_commit_pvid(chip, port); 2297 if (err) 2298 goto unlock; 2299 } 2300 2301 unlock: 2302 mv88e6xxx_reg_unlock(chip); 2303 2304 return err; 2305 } 2306 2307 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2308 const unsigned char *addr, u16 vid) 2309 { 2310 struct mv88e6xxx_chip *chip = ds->priv; 2311 int err; 2312 2313 mv88e6xxx_reg_lock(chip); 2314 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2315 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2316 mv88e6xxx_reg_unlock(chip); 2317 2318 return err; 2319 } 2320 2321 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2322 const unsigned char *addr, u16 vid) 2323 { 2324 struct mv88e6xxx_chip *chip = ds->priv; 2325 int err; 2326 2327 mv88e6xxx_reg_lock(chip); 2328 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2329 mv88e6xxx_reg_unlock(chip); 2330 2331 return err; 2332 } 2333 2334 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2335 u16 fid, u16 vid, int port, 2336 dsa_fdb_dump_cb_t *cb, void *data) 2337 { 2338 struct mv88e6xxx_atu_entry addr; 2339 bool is_static; 2340 int err; 2341 2342 addr.state = 0; 2343 eth_broadcast_addr(addr.mac); 2344 2345 do { 2346 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2347 if (err) 2348 return err; 2349 2350 if (!addr.state) 2351 break; 2352 2353 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2354 continue; 2355 2356 if (!is_unicast_ether_addr(addr.mac)) 2357 continue; 2358 2359 is_static = (addr.state == 2360 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2361 err = cb(addr.mac, vid, is_static, data); 2362 if (err) 2363 return err; 2364 } while (!is_broadcast_ether_addr(addr.mac)); 2365 2366 return err; 2367 } 2368 2369 struct mv88e6xxx_port_db_dump_vlan_ctx { 2370 int port; 2371 dsa_fdb_dump_cb_t *cb; 2372 void *data; 2373 }; 2374 2375 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2376 const struct mv88e6xxx_vtu_entry *entry, 2377 void *_data) 2378 { 2379 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2380 2381 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2382 ctx->port, ctx->cb, ctx->data); 2383 } 2384 2385 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2386 dsa_fdb_dump_cb_t *cb, void *data) 2387 { 2388 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2389 .port = port, 2390 .cb = cb, 2391 .data = data, 2392 }; 2393 u16 fid; 2394 int err; 2395 2396 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2397 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2398 if (err) 2399 return err; 2400 2401 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2402 if (err) 2403 return err; 2404 2405 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2406 } 2407 2408 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2409 dsa_fdb_dump_cb_t *cb, void *data) 2410 { 2411 struct mv88e6xxx_chip *chip = ds->priv; 2412 int err; 2413 2414 mv88e6xxx_reg_lock(chip); 2415 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2416 mv88e6xxx_reg_unlock(chip); 2417 2418 return err; 2419 } 2420 2421 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2422 struct dsa_bridge bridge) 2423 { 2424 struct dsa_switch *ds = chip->ds; 2425 struct dsa_switch_tree *dst = ds->dst; 2426 struct dsa_port *dp; 2427 int err; 2428 2429 list_for_each_entry(dp, &dst->ports, list) { 2430 if (dsa_port_offloads_bridge(dp, &bridge)) { 2431 if (dp->ds == ds) { 2432 /* This is a local bridge group member, 2433 * remap its Port VLAN Map. 2434 */ 2435 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2436 if (err) 2437 return err; 2438 } else { 2439 /* This is an external bridge group member, 2440 * remap its cross-chip Port VLAN Table entry. 2441 */ 2442 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2443 dp->index); 2444 if (err) 2445 return err; 2446 } 2447 } 2448 } 2449 2450 return 0; 2451 } 2452 2453 /* Treat the software bridge as a virtual single-port switch behind the 2454 * CPU and map in the PVT. First dst->last_switch elements are taken by 2455 * physical switches, so start from beyond that range. 2456 */ 2457 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2458 unsigned int bridge_num) 2459 { 2460 u8 dev = bridge_num + ds->dst->last_switch; 2461 struct mv88e6xxx_chip *chip = ds->priv; 2462 2463 return mv88e6xxx_pvt_map(chip, dev, 0); 2464 } 2465 2466 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2467 struct dsa_bridge bridge, 2468 bool *tx_fwd_offload) 2469 { 2470 struct mv88e6xxx_chip *chip = ds->priv; 2471 int err; 2472 2473 mv88e6xxx_reg_lock(chip); 2474 2475 err = mv88e6xxx_bridge_map(chip, bridge); 2476 if (err) 2477 goto unlock; 2478 2479 err = mv88e6xxx_port_commit_pvid(chip, port); 2480 if (err) 2481 goto unlock; 2482 2483 if (mv88e6xxx_has_pvt(chip)) { 2484 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2485 if (err) 2486 goto unlock; 2487 2488 *tx_fwd_offload = true; 2489 } 2490 2491 unlock: 2492 mv88e6xxx_reg_unlock(chip); 2493 2494 return err; 2495 } 2496 2497 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2498 struct dsa_bridge bridge) 2499 { 2500 struct mv88e6xxx_chip *chip = ds->priv; 2501 int err; 2502 2503 mv88e6xxx_reg_lock(chip); 2504 2505 if (bridge.tx_fwd_offload && 2506 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2507 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2508 2509 if (mv88e6xxx_bridge_map(chip, bridge) || 2510 mv88e6xxx_port_vlan_map(chip, port)) 2511 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2512 2513 err = mv88e6xxx_port_commit_pvid(chip, port); 2514 if (err) 2515 dev_err(ds->dev, 2516 "port %d failed to restore standalone pvid: %pe\n", 2517 port, ERR_PTR(err)); 2518 2519 mv88e6xxx_reg_unlock(chip); 2520 } 2521 2522 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2523 int tree_index, int sw_index, 2524 int port, struct dsa_bridge bridge) 2525 { 2526 struct mv88e6xxx_chip *chip = ds->priv; 2527 int err; 2528 2529 if (tree_index != ds->dst->index) 2530 return 0; 2531 2532 mv88e6xxx_reg_lock(chip); 2533 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2534 mv88e6xxx_reg_unlock(chip); 2535 2536 return err; 2537 } 2538 2539 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2540 int tree_index, int sw_index, 2541 int port, struct dsa_bridge bridge) 2542 { 2543 struct mv88e6xxx_chip *chip = ds->priv; 2544 2545 if (tree_index != ds->dst->index) 2546 return; 2547 2548 mv88e6xxx_reg_lock(chip); 2549 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2550 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2551 mv88e6xxx_reg_unlock(chip); 2552 } 2553 2554 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2555 { 2556 if (chip->info->ops->reset) 2557 return chip->info->ops->reset(chip); 2558 2559 return 0; 2560 } 2561 2562 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2563 { 2564 struct gpio_desc *gpiod = chip->reset; 2565 2566 /* If there is a GPIO connected to the reset pin, toggle it */ 2567 if (gpiod) { 2568 gpiod_set_value_cansleep(gpiod, 1); 2569 usleep_range(10000, 20000); 2570 gpiod_set_value_cansleep(gpiod, 0); 2571 usleep_range(10000, 20000); 2572 2573 mv88e6xxx_g1_wait_eeprom_done(chip); 2574 } 2575 } 2576 2577 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2578 { 2579 int i, err; 2580 2581 /* Set all ports to the Disabled state */ 2582 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2583 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2584 if (err) 2585 return err; 2586 } 2587 2588 /* Wait for transmit queues to drain, 2589 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2590 */ 2591 usleep_range(2000, 4000); 2592 2593 return 0; 2594 } 2595 2596 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2597 { 2598 int err; 2599 2600 err = mv88e6xxx_disable_ports(chip); 2601 if (err) 2602 return err; 2603 2604 mv88e6xxx_hardware_reset(chip); 2605 2606 return mv88e6xxx_software_reset(chip); 2607 } 2608 2609 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2610 enum mv88e6xxx_frame_mode frame, 2611 enum mv88e6xxx_egress_mode egress, u16 etype) 2612 { 2613 int err; 2614 2615 if (!chip->info->ops->port_set_frame_mode) 2616 return -EOPNOTSUPP; 2617 2618 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2619 if (err) 2620 return err; 2621 2622 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2623 if (err) 2624 return err; 2625 2626 if (chip->info->ops->port_set_ether_type) 2627 return chip->info->ops->port_set_ether_type(chip, port, etype); 2628 2629 return 0; 2630 } 2631 2632 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2633 { 2634 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2635 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2636 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2637 } 2638 2639 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2640 { 2641 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2642 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2643 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2644 } 2645 2646 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2647 { 2648 return mv88e6xxx_set_port_mode(chip, port, 2649 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2650 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2651 ETH_P_EDSA); 2652 } 2653 2654 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2655 { 2656 if (dsa_is_dsa_port(chip->ds, port)) 2657 return mv88e6xxx_set_port_mode_dsa(chip, port); 2658 2659 if (dsa_is_user_port(chip->ds, port)) 2660 return mv88e6xxx_set_port_mode_normal(chip, port); 2661 2662 /* Setup CPU port mode depending on its supported tag format */ 2663 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2664 return mv88e6xxx_set_port_mode_dsa(chip, port); 2665 2666 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2667 return mv88e6xxx_set_port_mode_edsa(chip, port); 2668 2669 return -EINVAL; 2670 } 2671 2672 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2673 { 2674 bool message = dsa_is_dsa_port(chip->ds, port); 2675 2676 return mv88e6xxx_port_set_message_port(chip, port, message); 2677 } 2678 2679 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2680 { 2681 int err; 2682 2683 if (chip->info->ops->port_set_ucast_flood) { 2684 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2685 if (err) 2686 return err; 2687 } 2688 if (chip->info->ops->port_set_mcast_flood) { 2689 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2690 if (err) 2691 return err; 2692 } 2693 2694 return 0; 2695 } 2696 2697 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2698 { 2699 struct mv88e6xxx_port *mvp = dev_id; 2700 struct mv88e6xxx_chip *chip = mvp->chip; 2701 irqreturn_t ret = IRQ_NONE; 2702 int port = mvp->port; 2703 int lane; 2704 2705 mv88e6xxx_reg_lock(chip); 2706 lane = mv88e6xxx_serdes_get_lane(chip, port); 2707 if (lane >= 0) 2708 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2709 mv88e6xxx_reg_unlock(chip); 2710 2711 return ret; 2712 } 2713 2714 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2715 int lane) 2716 { 2717 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2718 unsigned int irq; 2719 int err; 2720 2721 /* Nothing to request if this SERDES port has no IRQ */ 2722 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2723 if (!irq) 2724 return 0; 2725 2726 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2727 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2728 2729 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2730 mv88e6xxx_reg_unlock(chip); 2731 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2732 IRQF_ONESHOT, dev_id->serdes_irq_name, 2733 dev_id); 2734 mv88e6xxx_reg_lock(chip); 2735 if (err) 2736 return err; 2737 2738 dev_id->serdes_irq = irq; 2739 2740 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2741 } 2742 2743 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2744 int lane) 2745 { 2746 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2747 unsigned int irq = dev_id->serdes_irq; 2748 int err; 2749 2750 /* Nothing to free if no IRQ has been requested */ 2751 if (!irq) 2752 return 0; 2753 2754 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2755 2756 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2757 mv88e6xxx_reg_unlock(chip); 2758 free_irq(irq, dev_id); 2759 mv88e6xxx_reg_lock(chip); 2760 2761 dev_id->serdes_irq = 0; 2762 2763 return err; 2764 } 2765 2766 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2767 bool on) 2768 { 2769 int lane; 2770 int err; 2771 2772 lane = mv88e6xxx_serdes_get_lane(chip, port); 2773 if (lane < 0) 2774 return 0; 2775 2776 if (on) { 2777 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2778 if (err) 2779 return err; 2780 2781 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2782 } else { 2783 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2784 if (err) 2785 return err; 2786 2787 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2788 } 2789 2790 return err; 2791 } 2792 2793 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2794 enum mv88e6xxx_egress_direction direction, 2795 int port) 2796 { 2797 int err; 2798 2799 if (!chip->info->ops->set_egress_port) 2800 return -EOPNOTSUPP; 2801 2802 err = chip->info->ops->set_egress_port(chip, direction, port); 2803 if (err) 2804 return err; 2805 2806 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2807 chip->ingress_dest_port = port; 2808 else 2809 chip->egress_dest_port = port; 2810 2811 return 0; 2812 } 2813 2814 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2815 { 2816 struct dsa_switch *ds = chip->ds; 2817 int upstream_port; 2818 int err; 2819 2820 upstream_port = dsa_upstream_port(ds, port); 2821 if (chip->info->ops->port_set_upstream_port) { 2822 err = chip->info->ops->port_set_upstream_port(chip, port, 2823 upstream_port); 2824 if (err) 2825 return err; 2826 } 2827 2828 if (port == upstream_port) { 2829 if (chip->info->ops->set_cpu_port) { 2830 err = chip->info->ops->set_cpu_port(chip, 2831 upstream_port); 2832 if (err) 2833 return err; 2834 } 2835 2836 err = mv88e6xxx_set_egress_port(chip, 2837 MV88E6XXX_EGRESS_DIR_INGRESS, 2838 upstream_port); 2839 if (err && err != -EOPNOTSUPP) 2840 return err; 2841 2842 err = mv88e6xxx_set_egress_port(chip, 2843 MV88E6XXX_EGRESS_DIR_EGRESS, 2844 upstream_port); 2845 if (err && err != -EOPNOTSUPP) 2846 return err; 2847 } 2848 2849 return 0; 2850 } 2851 2852 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2853 { 2854 struct dsa_switch *ds = chip->ds; 2855 int err; 2856 u16 reg; 2857 2858 chip->ports[port].chip = chip; 2859 chip->ports[port].port = port; 2860 2861 /* MAC Forcing register: don't force link, speed, duplex or flow control 2862 * state to any particular values on physical ports, but force the CPU 2863 * port and all DSA ports to their maximum bandwidth and full duplex. 2864 */ 2865 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2866 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2867 SPEED_MAX, DUPLEX_FULL, 2868 PAUSE_OFF, 2869 PHY_INTERFACE_MODE_NA); 2870 else 2871 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2872 SPEED_UNFORCED, DUPLEX_UNFORCED, 2873 PAUSE_ON, 2874 PHY_INTERFACE_MODE_NA); 2875 if (err) 2876 return err; 2877 2878 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2879 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2880 * tunneling, determine priority by looking at 802.1p and IP 2881 * priority fields (IP prio has precedence), and set STP state 2882 * to Forwarding. 2883 * 2884 * If this is the CPU link, use DSA or EDSA tagging depending 2885 * on which tagging mode was configured. 2886 * 2887 * If this is a link to another switch, use DSA tagging mode. 2888 * 2889 * If this is the upstream port for this switch, enable 2890 * forwarding of unknown unicasts and multicasts. 2891 */ 2892 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2893 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2894 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2895 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2896 if (err) 2897 return err; 2898 2899 err = mv88e6xxx_setup_port_mode(chip, port); 2900 if (err) 2901 return err; 2902 2903 err = mv88e6xxx_setup_egress_floods(chip, port); 2904 if (err) 2905 return err; 2906 2907 /* Port Control 2: don't force a good FCS, set the MTU size to 2908 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2909 * untagged frames on this port, do a destination address lookup on all 2910 * received packets as usual, disable ARP mirroring and don't send a 2911 * copy of all transmitted/received frames on this port to the CPU. 2912 */ 2913 err = mv88e6xxx_port_set_map_da(chip, port); 2914 if (err) 2915 return err; 2916 2917 err = mv88e6xxx_setup_upstream_port(chip, port); 2918 if (err) 2919 return err; 2920 2921 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2922 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2923 if (err) 2924 return err; 2925 2926 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2927 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2928 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2929 * as the private PVID on ports under a VLAN-unaware bridge. 2930 * Shared (DSA and CPU) ports must also be members of it, to translate 2931 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2932 * relying on their port default FID. 2933 */ 2934 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2935 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2936 false); 2937 if (err) 2938 return err; 2939 2940 if (chip->info->ops->port_set_jumbo_size) { 2941 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2942 if (err) 2943 return err; 2944 } 2945 2946 /* Port Association Vector: disable automatic address learning 2947 * on all user ports since they start out in standalone 2948 * mode. When joining a bridge, learning will be configured to 2949 * match the bridge port settings. Enable learning on all 2950 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2951 * learning process. 2952 * 2953 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2954 * and RefreshLocked. I.e. setup standard automatic learning. 2955 */ 2956 if (dsa_is_user_port(ds, port)) 2957 reg = 0; 2958 else 2959 reg = 1 << port; 2960 2961 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2962 reg); 2963 if (err) 2964 return err; 2965 2966 /* Egress rate control 2: disable egress rate control. */ 2967 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2968 0x0000); 2969 if (err) 2970 return err; 2971 2972 if (chip->info->ops->port_pause_limit) { 2973 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2974 if (err) 2975 return err; 2976 } 2977 2978 if (chip->info->ops->port_disable_learn_limit) { 2979 err = chip->info->ops->port_disable_learn_limit(chip, port); 2980 if (err) 2981 return err; 2982 } 2983 2984 if (chip->info->ops->port_disable_pri_override) { 2985 err = chip->info->ops->port_disable_pri_override(chip, port); 2986 if (err) 2987 return err; 2988 } 2989 2990 if (chip->info->ops->port_tag_remap) { 2991 err = chip->info->ops->port_tag_remap(chip, port); 2992 if (err) 2993 return err; 2994 } 2995 2996 if (chip->info->ops->port_egress_rate_limiting) { 2997 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2998 if (err) 2999 return err; 3000 } 3001 3002 if (chip->info->ops->port_setup_message_port) { 3003 err = chip->info->ops->port_setup_message_port(chip, port); 3004 if (err) 3005 return err; 3006 } 3007 3008 /* Port based VLAN map: give each port the same default address 3009 * database, and allow bidirectional communication between the 3010 * CPU and DSA port(s), and the other ports. 3011 */ 3012 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3013 if (err) 3014 return err; 3015 3016 err = mv88e6xxx_port_vlan_map(chip, port); 3017 if (err) 3018 return err; 3019 3020 /* Default VLAN ID and priority: don't set a default VLAN 3021 * ID, and set the default packet priority to zero. 3022 */ 3023 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3024 } 3025 3026 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3027 { 3028 struct mv88e6xxx_chip *chip = ds->priv; 3029 3030 if (chip->info->ops->port_set_jumbo_size) 3031 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3032 else if (chip->info->ops->set_max_frame_size) 3033 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3034 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3035 } 3036 3037 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3038 { 3039 struct mv88e6xxx_chip *chip = ds->priv; 3040 int ret = 0; 3041 3042 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3043 new_mtu += EDSA_HLEN; 3044 3045 mv88e6xxx_reg_lock(chip); 3046 if (chip->info->ops->port_set_jumbo_size) 3047 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3048 else if (chip->info->ops->set_max_frame_size) 3049 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3050 else 3051 if (new_mtu > 1522) 3052 ret = -EINVAL; 3053 mv88e6xxx_reg_unlock(chip); 3054 3055 return ret; 3056 } 3057 3058 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3059 struct phy_device *phydev) 3060 { 3061 struct mv88e6xxx_chip *chip = ds->priv; 3062 int err; 3063 3064 mv88e6xxx_reg_lock(chip); 3065 err = mv88e6xxx_serdes_power(chip, port, true); 3066 mv88e6xxx_reg_unlock(chip); 3067 3068 return err; 3069 } 3070 3071 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3072 { 3073 struct mv88e6xxx_chip *chip = ds->priv; 3074 3075 mv88e6xxx_reg_lock(chip); 3076 if (mv88e6xxx_serdes_power(chip, port, false)) 3077 dev_err(chip->dev, "failed to power off SERDES\n"); 3078 mv88e6xxx_reg_unlock(chip); 3079 } 3080 3081 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3082 unsigned int ageing_time) 3083 { 3084 struct mv88e6xxx_chip *chip = ds->priv; 3085 int err; 3086 3087 mv88e6xxx_reg_lock(chip); 3088 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3089 mv88e6xxx_reg_unlock(chip); 3090 3091 return err; 3092 } 3093 3094 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3095 { 3096 int err; 3097 3098 /* Initialize the statistics unit */ 3099 if (chip->info->ops->stats_set_histogram) { 3100 err = chip->info->ops->stats_set_histogram(chip); 3101 if (err) 3102 return err; 3103 } 3104 3105 return mv88e6xxx_g1_stats_clear(chip); 3106 } 3107 3108 /* Check if the errata has already been applied. */ 3109 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3110 { 3111 int port; 3112 int err; 3113 u16 val; 3114 3115 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3116 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3117 if (err) { 3118 dev_err(chip->dev, 3119 "Error reading hidden register: %d\n", err); 3120 return false; 3121 } 3122 if (val != 0x01c0) 3123 return false; 3124 } 3125 3126 return true; 3127 } 3128 3129 /* The 6390 copper ports have an errata which require poking magic 3130 * values into undocumented hidden registers and then performing a 3131 * software reset. 3132 */ 3133 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3134 { 3135 int port; 3136 int err; 3137 3138 if (mv88e6390_setup_errata_applied(chip)) 3139 return 0; 3140 3141 /* Set the ports into blocking mode */ 3142 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3143 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3144 if (err) 3145 return err; 3146 } 3147 3148 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3149 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3150 if (err) 3151 return err; 3152 } 3153 3154 return mv88e6xxx_software_reset(chip); 3155 } 3156 3157 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3158 { 3159 mv88e6xxx_teardown_devlink_params(ds); 3160 dsa_devlink_resources_unregister(ds); 3161 mv88e6xxx_teardown_devlink_regions_global(ds); 3162 } 3163 3164 static int mv88e6xxx_setup(struct dsa_switch *ds) 3165 { 3166 struct mv88e6xxx_chip *chip = ds->priv; 3167 u8 cmode; 3168 int err; 3169 int i; 3170 3171 chip->ds = ds; 3172 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3173 3174 /* Since virtual bridges are mapped in the PVT, the number we support 3175 * depends on the physical switch topology. We need to let DSA figure 3176 * that out and therefore we cannot set this at dsa_register_switch() 3177 * time. 3178 */ 3179 if (mv88e6xxx_has_pvt(chip)) 3180 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3181 ds->dst->last_switch - 1; 3182 3183 mv88e6xxx_reg_lock(chip); 3184 3185 if (chip->info->ops->setup_errata) { 3186 err = chip->info->ops->setup_errata(chip); 3187 if (err) 3188 goto unlock; 3189 } 3190 3191 /* Cache the cmode of each port. */ 3192 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3193 if (chip->info->ops->port_get_cmode) { 3194 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3195 if (err) 3196 goto unlock; 3197 3198 chip->ports[i].cmode = cmode; 3199 } 3200 } 3201 3202 err = mv88e6xxx_vtu_setup(chip); 3203 if (err) 3204 goto unlock; 3205 3206 /* Setup Switch Port Registers */ 3207 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3208 if (dsa_is_unused_port(ds, i)) 3209 continue; 3210 3211 /* Prevent the use of an invalid port. */ 3212 if (mv88e6xxx_is_invalid_port(chip, i)) { 3213 dev_err(chip->dev, "port %d is invalid\n", i); 3214 err = -EINVAL; 3215 goto unlock; 3216 } 3217 3218 err = mv88e6xxx_setup_port(chip, i); 3219 if (err) 3220 goto unlock; 3221 } 3222 3223 err = mv88e6xxx_irl_setup(chip); 3224 if (err) 3225 goto unlock; 3226 3227 err = mv88e6xxx_mac_setup(chip); 3228 if (err) 3229 goto unlock; 3230 3231 err = mv88e6xxx_phy_setup(chip); 3232 if (err) 3233 goto unlock; 3234 3235 err = mv88e6xxx_pvt_setup(chip); 3236 if (err) 3237 goto unlock; 3238 3239 err = mv88e6xxx_atu_setup(chip); 3240 if (err) 3241 goto unlock; 3242 3243 err = mv88e6xxx_broadcast_setup(chip, 0); 3244 if (err) 3245 goto unlock; 3246 3247 err = mv88e6xxx_pot_setup(chip); 3248 if (err) 3249 goto unlock; 3250 3251 err = mv88e6xxx_rmu_setup(chip); 3252 if (err) 3253 goto unlock; 3254 3255 err = mv88e6xxx_rsvd2cpu_setup(chip); 3256 if (err) 3257 goto unlock; 3258 3259 err = mv88e6xxx_trunk_setup(chip); 3260 if (err) 3261 goto unlock; 3262 3263 err = mv88e6xxx_devmap_setup(chip); 3264 if (err) 3265 goto unlock; 3266 3267 err = mv88e6xxx_pri_setup(chip); 3268 if (err) 3269 goto unlock; 3270 3271 /* Setup PTP Hardware Clock and timestamping */ 3272 if (chip->info->ptp_support) { 3273 err = mv88e6xxx_ptp_setup(chip); 3274 if (err) 3275 goto unlock; 3276 3277 err = mv88e6xxx_hwtstamp_setup(chip); 3278 if (err) 3279 goto unlock; 3280 } 3281 3282 err = mv88e6xxx_stats_setup(chip); 3283 if (err) 3284 goto unlock; 3285 3286 unlock: 3287 mv88e6xxx_reg_unlock(chip); 3288 3289 if (err) 3290 return err; 3291 3292 /* Have to be called without holding the register lock, since 3293 * they take the devlink lock, and we later take the locks in 3294 * the reverse order when getting/setting parameters or 3295 * resource occupancy. 3296 */ 3297 err = mv88e6xxx_setup_devlink_resources(ds); 3298 if (err) 3299 return err; 3300 3301 err = mv88e6xxx_setup_devlink_params(ds); 3302 if (err) 3303 goto out_resources; 3304 3305 err = mv88e6xxx_setup_devlink_regions_global(ds); 3306 if (err) 3307 goto out_params; 3308 3309 return 0; 3310 3311 out_params: 3312 mv88e6xxx_teardown_devlink_params(ds); 3313 out_resources: 3314 dsa_devlink_resources_unregister(ds); 3315 3316 return err; 3317 } 3318 3319 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3320 { 3321 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3322 } 3323 3324 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3325 { 3326 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3327 } 3328 3329 /* prod_id for switch families which do not have a PHY model number */ 3330 static const u16 family_prod_id_table[] = { 3331 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3332 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3333 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3334 }; 3335 3336 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3337 { 3338 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3339 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3340 u16 prod_id; 3341 u16 val; 3342 int err; 3343 3344 if (!chip->info->ops->phy_read) 3345 return -EOPNOTSUPP; 3346 3347 mv88e6xxx_reg_lock(chip); 3348 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3349 mv88e6xxx_reg_unlock(chip); 3350 3351 /* Some internal PHYs don't have a model number. */ 3352 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3353 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3354 prod_id = family_prod_id_table[chip->info->family]; 3355 if (prod_id) 3356 val |= prod_id >> 4; 3357 } 3358 3359 return err ? err : val; 3360 } 3361 3362 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3363 { 3364 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3365 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3366 int err; 3367 3368 if (!chip->info->ops->phy_write) 3369 return -EOPNOTSUPP; 3370 3371 mv88e6xxx_reg_lock(chip); 3372 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3373 mv88e6xxx_reg_unlock(chip); 3374 3375 return err; 3376 } 3377 3378 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3379 struct device_node *np, 3380 bool external) 3381 { 3382 static int index; 3383 struct mv88e6xxx_mdio_bus *mdio_bus; 3384 struct mii_bus *bus; 3385 int err; 3386 3387 if (external) { 3388 mv88e6xxx_reg_lock(chip); 3389 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3390 mv88e6xxx_reg_unlock(chip); 3391 3392 if (err) 3393 return err; 3394 } 3395 3396 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3397 if (!bus) 3398 return -ENOMEM; 3399 3400 mdio_bus = bus->priv; 3401 mdio_bus->bus = bus; 3402 mdio_bus->chip = chip; 3403 INIT_LIST_HEAD(&mdio_bus->list); 3404 mdio_bus->external = external; 3405 3406 if (np) { 3407 bus->name = np->full_name; 3408 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3409 } else { 3410 bus->name = "mv88e6xxx SMI"; 3411 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3412 } 3413 3414 bus->read = mv88e6xxx_mdio_read; 3415 bus->write = mv88e6xxx_mdio_write; 3416 bus->parent = chip->dev; 3417 3418 if (!external) { 3419 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3420 if (err) 3421 return err; 3422 } 3423 3424 err = of_mdiobus_register(bus, np); 3425 if (err) { 3426 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3427 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3428 return err; 3429 } 3430 3431 if (external) 3432 list_add_tail(&mdio_bus->list, &chip->mdios); 3433 else 3434 list_add(&mdio_bus->list, &chip->mdios); 3435 3436 return 0; 3437 } 3438 3439 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3440 3441 { 3442 struct mv88e6xxx_mdio_bus *mdio_bus; 3443 struct mii_bus *bus; 3444 3445 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3446 bus = mdio_bus->bus; 3447 3448 if (!mdio_bus->external) 3449 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3450 3451 mdiobus_unregister(bus); 3452 } 3453 } 3454 3455 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3456 struct device_node *np) 3457 { 3458 struct device_node *child; 3459 int err; 3460 3461 /* Always register one mdio bus for the internal/default mdio 3462 * bus. This maybe represented in the device tree, but is 3463 * optional. 3464 */ 3465 child = of_get_child_by_name(np, "mdio"); 3466 err = mv88e6xxx_mdio_register(chip, child, false); 3467 if (err) 3468 return err; 3469 3470 /* Walk the device tree, and see if there are any other nodes 3471 * which say they are compatible with the external mdio 3472 * bus. 3473 */ 3474 for_each_available_child_of_node(np, child) { 3475 if (of_device_is_compatible( 3476 child, "marvell,mv88e6xxx-mdio-external")) { 3477 err = mv88e6xxx_mdio_register(chip, child, true); 3478 if (err) { 3479 mv88e6xxx_mdios_unregister(chip); 3480 of_node_put(child); 3481 return err; 3482 } 3483 } 3484 } 3485 3486 return 0; 3487 } 3488 3489 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3490 { 3491 struct mv88e6xxx_chip *chip = ds->priv; 3492 3493 return chip->eeprom_len; 3494 } 3495 3496 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3497 struct ethtool_eeprom *eeprom, u8 *data) 3498 { 3499 struct mv88e6xxx_chip *chip = ds->priv; 3500 int err; 3501 3502 if (!chip->info->ops->get_eeprom) 3503 return -EOPNOTSUPP; 3504 3505 mv88e6xxx_reg_lock(chip); 3506 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3507 mv88e6xxx_reg_unlock(chip); 3508 3509 if (err) 3510 return err; 3511 3512 eeprom->magic = 0xc3ec4951; 3513 3514 return 0; 3515 } 3516 3517 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3518 struct ethtool_eeprom *eeprom, u8 *data) 3519 { 3520 struct mv88e6xxx_chip *chip = ds->priv; 3521 int err; 3522 3523 if (!chip->info->ops->set_eeprom) 3524 return -EOPNOTSUPP; 3525 3526 if (eeprom->magic != 0xc3ec4951) 3527 return -EINVAL; 3528 3529 mv88e6xxx_reg_lock(chip); 3530 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3531 mv88e6xxx_reg_unlock(chip); 3532 3533 return err; 3534 } 3535 3536 static const struct mv88e6xxx_ops mv88e6085_ops = { 3537 /* MV88E6XXX_FAMILY_6097 */ 3538 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3539 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3540 .irl_init_all = mv88e6352_g2_irl_init_all, 3541 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3542 .phy_read = mv88e6185_phy_ppu_read, 3543 .phy_write = mv88e6185_phy_ppu_write, 3544 .port_set_link = mv88e6xxx_port_set_link, 3545 .port_sync_link = mv88e6xxx_port_sync_link, 3546 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3547 .port_tag_remap = mv88e6095_port_tag_remap, 3548 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3549 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3550 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3551 .port_set_ether_type = mv88e6351_port_set_ether_type, 3552 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3553 .port_pause_limit = mv88e6097_port_pause_limit, 3554 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3555 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3556 .port_get_cmode = mv88e6185_port_get_cmode, 3557 .port_setup_message_port = mv88e6xxx_setup_message_port, 3558 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3559 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3560 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3561 .stats_get_strings = mv88e6095_stats_get_strings, 3562 .stats_get_stats = mv88e6095_stats_get_stats, 3563 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3564 .set_egress_port = mv88e6095_g1_set_egress_port, 3565 .watchdog_ops = &mv88e6097_watchdog_ops, 3566 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3567 .pot_clear = mv88e6xxx_g2_pot_clear, 3568 .ppu_enable = mv88e6185_g1_ppu_enable, 3569 .ppu_disable = mv88e6185_g1_ppu_disable, 3570 .reset = mv88e6185_g1_reset, 3571 .rmu_disable = mv88e6085_g1_rmu_disable, 3572 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3573 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3574 .phylink_validate = mv88e6185_phylink_validate, 3575 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3576 }; 3577 3578 static const struct mv88e6xxx_ops mv88e6095_ops = { 3579 /* MV88E6XXX_FAMILY_6095 */ 3580 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3581 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3582 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3583 .phy_read = mv88e6185_phy_ppu_read, 3584 .phy_write = mv88e6185_phy_ppu_write, 3585 .port_set_link = mv88e6xxx_port_set_link, 3586 .port_sync_link = mv88e6185_port_sync_link, 3587 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3588 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3589 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3590 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3591 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3592 .port_get_cmode = mv88e6185_port_get_cmode, 3593 .port_setup_message_port = mv88e6xxx_setup_message_port, 3594 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3595 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3596 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3597 .stats_get_strings = mv88e6095_stats_get_strings, 3598 .stats_get_stats = mv88e6095_stats_get_stats, 3599 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3600 .serdes_power = mv88e6185_serdes_power, 3601 .serdes_get_lane = mv88e6185_serdes_get_lane, 3602 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3603 .ppu_enable = mv88e6185_g1_ppu_enable, 3604 .ppu_disable = mv88e6185_g1_ppu_disable, 3605 .reset = mv88e6185_g1_reset, 3606 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3607 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3608 .phylink_validate = mv88e6185_phylink_validate, 3609 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3610 }; 3611 3612 static const struct mv88e6xxx_ops mv88e6097_ops = { 3613 /* MV88E6XXX_FAMILY_6097 */ 3614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3615 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3616 .irl_init_all = mv88e6352_g2_irl_init_all, 3617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3618 .phy_read = mv88e6xxx_g2_smi_phy_read, 3619 .phy_write = mv88e6xxx_g2_smi_phy_write, 3620 .port_set_link = mv88e6xxx_port_set_link, 3621 .port_sync_link = mv88e6185_port_sync_link, 3622 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3623 .port_tag_remap = mv88e6095_port_tag_remap, 3624 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3625 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3626 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3627 .port_set_ether_type = mv88e6351_port_set_ether_type, 3628 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3629 .port_pause_limit = mv88e6097_port_pause_limit, 3630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3632 .port_get_cmode = mv88e6185_port_get_cmode, 3633 .port_setup_message_port = mv88e6xxx_setup_message_port, 3634 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3635 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3636 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3637 .stats_get_strings = mv88e6095_stats_get_strings, 3638 .stats_get_stats = mv88e6095_stats_get_stats, 3639 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3640 .set_egress_port = mv88e6095_g1_set_egress_port, 3641 .watchdog_ops = &mv88e6097_watchdog_ops, 3642 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3643 .serdes_power = mv88e6185_serdes_power, 3644 .serdes_get_lane = mv88e6185_serdes_get_lane, 3645 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3646 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3647 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3648 .serdes_irq_status = mv88e6097_serdes_irq_status, 3649 .pot_clear = mv88e6xxx_g2_pot_clear, 3650 .reset = mv88e6352_g1_reset, 3651 .rmu_disable = mv88e6085_g1_rmu_disable, 3652 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3653 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3654 .phylink_validate = mv88e6185_phylink_validate, 3655 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3656 }; 3657 3658 static const struct mv88e6xxx_ops mv88e6123_ops = { 3659 /* MV88E6XXX_FAMILY_6165 */ 3660 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3661 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3662 .irl_init_all = mv88e6352_g2_irl_init_all, 3663 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3664 .phy_read = mv88e6xxx_g2_smi_phy_read, 3665 .phy_write = mv88e6xxx_g2_smi_phy_write, 3666 .port_set_link = mv88e6xxx_port_set_link, 3667 .port_sync_link = mv88e6xxx_port_sync_link, 3668 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3669 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3670 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3671 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3674 .port_get_cmode = mv88e6185_port_get_cmode, 3675 .port_setup_message_port = mv88e6xxx_setup_message_port, 3676 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3677 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3678 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3679 .stats_get_strings = mv88e6095_stats_get_strings, 3680 .stats_get_stats = mv88e6095_stats_get_stats, 3681 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3682 .set_egress_port = mv88e6095_g1_set_egress_port, 3683 .watchdog_ops = &mv88e6097_watchdog_ops, 3684 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3685 .pot_clear = mv88e6xxx_g2_pot_clear, 3686 .reset = mv88e6352_g1_reset, 3687 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3688 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3689 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3690 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3691 .phylink_validate = mv88e6185_phylink_validate, 3692 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3693 }; 3694 3695 static const struct mv88e6xxx_ops mv88e6131_ops = { 3696 /* MV88E6XXX_FAMILY_6185 */ 3697 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3698 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3699 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3700 .phy_read = mv88e6185_phy_ppu_read, 3701 .phy_write = mv88e6185_phy_ppu_write, 3702 .port_set_link = mv88e6xxx_port_set_link, 3703 .port_sync_link = mv88e6xxx_port_sync_link, 3704 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3705 .port_tag_remap = mv88e6095_port_tag_remap, 3706 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3707 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3708 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3709 .port_set_ether_type = mv88e6351_port_set_ether_type, 3710 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3711 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3712 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3713 .port_pause_limit = mv88e6097_port_pause_limit, 3714 .port_set_pause = mv88e6185_port_set_pause, 3715 .port_get_cmode = mv88e6185_port_get_cmode, 3716 .port_setup_message_port = mv88e6xxx_setup_message_port, 3717 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3718 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3719 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3720 .stats_get_strings = mv88e6095_stats_get_strings, 3721 .stats_get_stats = mv88e6095_stats_get_stats, 3722 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3723 .set_egress_port = mv88e6095_g1_set_egress_port, 3724 .watchdog_ops = &mv88e6097_watchdog_ops, 3725 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3726 .ppu_enable = mv88e6185_g1_ppu_enable, 3727 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3728 .ppu_disable = mv88e6185_g1_ppu_disable, 3729 .reset = mv88e6185_g1_reset, 3730 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3731 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3732 .phylink_validate = mv88e6185_phylink_validate, 3733 }; 3734 3735 static const struct mv88e6xxx_ops mv88e6141_ops = { 3736 /* MV88E6XXX_FAMILY_6341 */ 3737 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3738 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3739 .irl_init_all = mv88e6352_g2_irl_init_all, 3740 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3741 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3742 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3743 .phy_read = mv88e6xxx_g2_smi_phy_read, 3744 .phy_write = mv88e6xxx_g2_smi_phy_write, 3745 .port_set_link = mv88e6xxx_port_set_link, 3746 .port_sync_link = mv88e6xxx_port_sync_link, 3747 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3748 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3749 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3750 .port_tag_remap = mv88e6095_port_tag_remap, 3751 .port_set_policy = mv88e6352_port_set_policy, 3752 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3753 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3754 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3755 .port_set_ether_type = mv88e6351_port_set_ether_type, 3756 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3757 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3758 .port_pause_limit = mv88e6097_port_pause_limit, 3759 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3760 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3761 .port_get_cmode = mv88e6352_port_get_cmode, 3762 .port_set_cmode = mv88e6341_port_set_cmode, 3763 .port_setup_message_port = mv88e6xxx_setup_message_port, 3764 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3765 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3766 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3767 .stats_get_strings = mv88e6320_stats_get_strings, 3768 .stats_get_stats = mv88e6390_stats_get_stats, 3769 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3770 .set_egress_port = mv88e6390_g1_set_egress_port, 3771 .watchdog_ops = &mv88e6390_watchdog_ops, 3772 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3773 .pot_clear = mv88e6xxx_g2_pot_clear, 3774 .reset = mv88e6352_g1_reset, 3775 .rmu_disable = mv88e6390_g1_rmu_disable, 3776 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3777 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3778 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3779 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3780 .serdes_power = mv88e6390_serdes_power, 3781 .serdes_get_lane = mv88e6341_serdes_get_lane, 3782 /* Check status register pause & lpa register */ 3783 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3784 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3785 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3786 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3787 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3788 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3789 .serdes_irq_status = mv88e6390_serdes_irq_status, 3790 .gpio_ops = &mv88e6352_gpio_ops, 3791 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3792 .serdes_get_strings = mv88e6390_serdes_get_strings, 3793 .serdes_get_stats = mv88e6390_serdes_get_stats, 3794 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3795 .serdes_get_regs = mv88e6390_serdes_get_regs, 3796 .phylink_validate = mv88e6341_phylink_validate, 3797 }; 3798 3799 static const struct mv88e6xxx_ops mv88e6161_ops = { 3800 /* MV88E6XXX_FAMILY_6165 */ 3801 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3802 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3803 .irl_init_all = mv88e6352_g2_irl_init_all, 3804 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3805 .phy_read = mv88e6xxx_g2_smi_phy_read, 3806 .phy_write = mv88e6xxx_g2_smi_phy_write, 3807 .port_set_link = mv88e6xxx_port_set_link, 3808 .port_sync_link = mv88e6xxx_port_sync_link, 3809 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3810 .port_tag_remap = mv88e6095_port_tag_remap, 3811 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3812 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3813 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3814 .port_set_ether_type = mv88e6351_port_set_ether_type, 3815 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3816 .port_pause_limit = mv88e6097_port_pause_limit, 3817 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3818 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3819 .port_get_cmode = mv88e6185_port_get_cmode, 3820 .port_setup_message_port = mv88e6xxx_setup_message_port, 3821 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3822 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3823 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3824 .stats_get_strings = mv88e6095_stats_get_strings, 3825 .stats_get_stats = mv88e6095_stats_get_stats, 3826 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3827 .set_egress_port = mv88e6095_g1_set_egress_port, 3828 .watchdog_ops = &mv88e6097_watchdog_ops, 3829 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3830 .pot_clear = mv88e6xxx_g2_pot_clear, 3831 .reset = mv88e6352_g1_reset, 3832 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3833 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3834 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3835 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3836 .avb_ops = &mv88e6165_avb_ops, 3837 .ptp_ops = &mv88e6165_ptp_ops, 3838 .phylink_validate = mv88e6185_phylink_validate, 3839 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3840 }; 3841 3842 static const struct mv88e6xxx_ops mv88e6165_ops = { 3843 /* MV88E6XXX_FAMILY_6165 */ 3844 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3845 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3846 .irl_init_all = mv88e6352_g2_irl_init_all, 3847 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3848 .phy_read = mv88e6165_phy_read, 3849 .phy_write = mv88e6165_phy_write, 3850 .port_set_link = mv88e6xxx_port_set_link, 3851 .port_sync_link = mv88e6xxx_port_sync_link, 3852 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3853 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3854 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3855 .port_get_cmode = mv88e6185_port_get_cmode, 3856 .port_setup_message_port = mv88e6xxx_setup_message_port, 3857 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3858 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3859 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3860 .stats_get_strings = mv88e6095_stats_get_strings, 3861 .stats_get_stats = mv88e6095_stats_get_stats, 3862 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3863 .set_egress_port = mv88e6095_g1_set_egress_port, 3864 .watchdog_ops = &mv88e6097_watchdog_ops, 3865 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3866 .pot_clear = mv88e6xxx_g2_pot_clear, 3867 .reset = mv88e6352_g1_reset, 3868 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3869 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3870 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3871 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3872 .avb_ops = &mv88e6165_avb_ops, 3873 .ptp_ops = &mv88e6165_ptp_ops, 3874 .phylink_validate = mv88e6185_phylink_validate, 3875 }; 3876 3877 static const struct mv88e6xxx_ops mv88e6171_ops = { 3878 /* MV88E6XXX_FAMILY_6351 */ 3879 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3880 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3881 .irl_init_all = mv88e6352_g2_irl_init_all, 3882 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3883 .phy_read = mv88e6xxx_g2_smi_phy_read, 3884 .phy_write = mv88e6xxx_g2_smi_phy_write, 3885 .port_set_link = mv88e6xxx_port_set_link, 3886 .port_sync_link = mv88e6xxx_port_sync_link, 3887 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3888 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3889 .port_tag_remap = mv88e6095_port_tag_remap, 3890 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3891 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3892 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3893 .port_set_ether_type = mv88e6351_port_set_ether_type, 3894 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3895 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3896 .port_pause_limit = mv88e6097_port_pause_limit, 3897 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3898 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3899 .port_get_cmode = mv88e6352_port_get_cmode, 3900 .port_setup_message_port = mv88e6xxx_setup_message_port, 3901 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3902 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3903 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3904 .stats_get_strings = mv88e6095_stats_get_strings, 3905 .stats_get_stats = mv88e6095_stats_get_stats, 3906 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3907 .set_egress_port = mv88e6095_g1_set_egress_port, 3908 .watchdog_ops = &mv88e6097_watchdog_ops, 3909 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3910 .pot_clear = mv88e6xxx_g2_pot_clear, 3911 .reset = mv88e6352_g1_reset, 3912 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3913 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3914 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3915 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3916 .phylink_validate = mv88e6185_phylink_validate, 3917 }; 3918 3919 static const struct mv88e6xxx_ops mv88e6172_ops = { 3920 /* MV88E6XXX_FAMILY_6352 */ 3921 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3922 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3923 .irl_init_all = mv88e6352_g2_irl_init_all, 3924 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3925 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3926 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3927 .phy_read = mv88e6xxx_g2_smi_phy_read, 3928 .phy_write = mv88e6xxx_g2_smi_phy_write, 3929 .port_set_link = mv88e6xxx_port_set_link, 3930 .port_sync_link = mv88e6xxx_port_sync_link, 3931 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3932 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3933 .port_tag_remap = mv88e6095_port_tag_remap, 3934 .port_set_policy = mv88e6352_port_set_policy, 3935 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3936 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3937 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3938 .port_set_ether_type = mv88e6351_port_set_ether_type, 3939 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3940 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3941 .port_pause_limit = mv88e6097_port_pause_limit, 3942 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3943 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3944 .port_get_cmode = mv88e6352_port_get_cmode, 3945 .port_setup_message_port = mv88e6xxx_setup_message_port, 3946 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3947 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3948 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3949 .stats_get_strings = mv88e6095_stats_get_strings, 3950 .stats_get_stats = mv88e6095_stats_get_stats, 3951 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3952 .set_egress_port = mv88e6095_g1_set_egress_port, 3953 .watchdog_ops = &mv88e6097_watchdog_ops, 3954 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3955 .pot_clear = mv88e6xxx_g2_pot_clear, 3956 .reset = mv88e6352_g1_reset, 3957 .rmu_disable = mv88e6352_g1_rmu_disable, 3958 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3959 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3960 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3961 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3962 .serdes_get_lane = mv88e6352_serdes_get_lane, 3963 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3964 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3965 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3966 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3967 .serdes_power = mv88e6352_serdes_power, 3968 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3969 .serdes_get_regs = mv88e6352_serdes_get_regs, 3970 .gpio_ops = &mv88e6352_gpio_ops, 3971 .phylink_validate = mv88e6352_phylink_validate, 3972 }; 3973 3974 static const struct mv88e6xxx_ops mv88e6175_ops = { 3975 /* MV88E6XXX_FAMILY_6351 */ 3976 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3977 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3978 .irl_init_all = mv88e6352_g2_irl_init_all, 3979 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3980 .phy_read = mv88e6xxx_g2_smi_phy_read, 3981 .phy_write = mv88e6xxx_g2_smi_phy_write, 3982 .port_set_link = mv88e6xxx_port_set_link, 3983 .port_sync_link = mv88e6xxx_port_sync_link, 3984 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3985 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3986 .port_tag_remap = mv88e6095_port_tag_remap, 3987 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3988 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3989 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3990 .port_set_ether_type = mv88e6351_port_set_ether_type, 3991 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3992 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3993 .port_pause_limit = mv88e6097_port_pause_limit, 3994 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3995 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3996 .port_get_cmode = mv88e6352_port_get_cmode, 3997 .port_setup_message_port = mv88e6xxx_setup_message_port, 3998 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3999 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4000 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4001 .stats_get_strings = mv88e6095_stats_get_strings, 4002 .stats_get_stats = mv88e6095_stats_get_stats, 4003 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4004 .set_egress_port = mv88e6095_g1_set_egress_port, 4005 .watchdog_ops = &mv88e6097_watchdog_ops, 4006 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4007 .pot_clear = mv88e6xxx_g2_pot_clear, 4008 .reset = mv88e6352_g1_reset, 4009 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4010 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4011 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4012 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4013 .phylink_validate = mv88e6185_phylink_validate, 4014 }; 4015 4016 static const struct mv88e6xxx_ops mv88e6176_ops = { 4017 /* MV88E6XXX_FAMILY_6352 */ 4018 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4019 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4020 .irl_init_all = mv88e6352_g2_irl_init_all, 4021 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4022 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4023 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4024 .phy_read = mv88e6xxx_g2_smi_phy_read, 4025 .phy_write = mv88e6xxx_g2_smi_phy_write, 4026 .port_set_link = mv88e6xxx_port_set_link, 4027 .port_sync_link = mv88e6xxx_port_sync_link, 4028 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4029 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4030 .port_tag_remap = mv88e6095_port_tag_remap, 4031 .port_set_policy = mv88e6352_port_set_policy, 4032 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4033 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4034 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4035 .port_set_ether_type = mv88e6351_port_set_ether_type, 4036 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4037 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4038 .port_pause_limit = mv88e6097_port_pause_limit, 4039 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4040 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4041 .port_get_cmode = mv88e6352_port_get_cmode, 4042 .port_setup_message_port = mv88e6xxx_setup_message_port, 4043 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4044 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4045 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4046 .stats_get_strings = mv88e6095_stats_get_strings, 4047 .stats_get_stats = mv88e6095_stats_get_stats, 4048 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4049 .set_egress_port = mv88e6095_g1_set_egress_port, 4050 .watchdog_ops = &mv88e6097_watchdog_ops, 4051 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4052 .pot_clear = mv88e6xxx_g2_pot_clear, 4053 .reset = mv88e6352_g1_reset, 4054 .rmu_disable = mv88e6352_g1_rmu_disable, 4055 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4056 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4057 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4058 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4059 .serdes_get_lane = mv88e6352_serdes_get_lane, 4060 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4061 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4062 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4063 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4064 .serdes_power = mv88e6352_serdes_power, 4065 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4066 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4067 .serdes_irq_status = mv88e6352_serdes_irq_status, 4068 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4069 .serdes_get_regs = mv88e6352_serdes_get_regs, 4070 .gpio_ops = &mv88e6352_gpio_ops, 4071 .phylink_validate = mv88e6352_phylink_validate, 4072 }; 4073 4074 static const struct mv88e6xxx_ops mv88e6185_ops = { 4075 /* MV88E6XXX_FAMILY_6185 */ 4076 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4077 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4078 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4079 .phy_read = mv88e6185_phy_ppu_read, 4080 .phy_write = mv88e6185_phy_ppu_write, 4081 .port_set_link = mv88e6xxx_port_set_link, 4082 .port_sync_link = mv88e6185_port_sync_link, 4083 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4084 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4085 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4086 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4087 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4088 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4089 .port_set_pause = mv88e6185_port_set_pause, 4090 .port_get_cmode = mv88e6185_port_get_cmode, 4091 .port_setup_message_port = mv88e6xxx_setup_message_port, 4092 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4093 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4094 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4095 .stats_get_strings = mv88e6095_stats_get_strings, 4096 .stats_get_stats = mv88e6095_stats_get_stats, 4097 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4098 .set_egress_port = mv88e6095_g1_set_egress_port, 4099 .watchdog_ops = &mv88e6097_watchdog_ops, 4100 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4101 .serdes_power = mv88e6185_serdes_power, 4102 .serdes_get_lane = mv88e6185_serdes_get_lane, 4103 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4104 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4105 .ppu_enable = mv88e6185_g1_ppu_enable, 4106 .ppu_disable = mv88e6185_g1_ppu_disable, 4107 .reset = mv88e6185_g1_reset, 4108 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4109 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4110 .phylink_validate = mv88e6185_phylink_validate, 4111 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4112 }; 4113 4114 static const struct mv88e6xxx_ops mv88e6190_ops = { 4115 /* MV88E6XXX_FAMILY_6390 */ 4116 .setup_errata = mv88e6390_setup_errata, 4117 .irl_init_all = mv88e6390_g2_irl_init_all, 4118 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4119 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4121 .phy_read = mv88e6xxx_g2_smi_phy_read, 4122 .phy_write = mv88e6xxx_g2_smi_phy_write, 4123 .port_set_link = mv88e6xxx_port_set_link, 4124 .port_sync_link = mv88e6xxx_port_sync_link, 4125 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4126 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4127 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4128 .port_tag_remap = mv88e6390_port_tag_remap, 4129 .port_set_policy = mv88e6352_port_set_policy, 4130 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4131 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4132 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4133 .port_set_ether_type = mv88e6351_port_set_ether_type, 4134 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4135 .port_pause_limit = mv88e6390_port_pause_limit, 4136 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4137 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4138 .port_get_cmode = mv88e6352_port_get_cmode, 4139 .port_set_cmode = mv88e6390_port_set_cmode, 4140 .port_setup_message_port = mv88e6xxx_setup_message_port, 4141 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4142 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4143 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4144 .stats_get_strings = mv88e6320_stats_get_strings, 4145 .stats_get_stats = mv88e6390_stats_get_stats, 4146 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4147 .set_egress_port = mv88e6390_g1_set_egress_port, 4148 .watchdog_ops = &mv88e6390_watchdog_ops, 4149 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4150 .pot_clear = mv88e6xxx_g2_pot_clear, 4151 .reset = mv88e6352_g1_reset, 4152 .rmu_disable = mv88e6390_g1_rmu_disable, 4153 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4154 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4155 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4156 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4157 .serdes_power = mv88e6390_serdes_power, 4158 .serdes_get_lane = mv88e6390_serdes_get_lane, 4159 /* Check status register pause & lpa register */ 4160 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4161 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4162 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4163 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4164 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4165 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4166 .serdes_irq_status = mv88e6390_serdes_irq_status, 4167 .serdes_get_strings = mv88e6390_serdes_get_strings, 4168 .serdes_get_stats = mv88e6390_serdes_get_stats, 4169 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4170 .serdes_get_regs = mv88e6390_serdes_get_regs, 4171 .gpio_ops = &mv88e6352_gpio_ops, 4172 .phylink_validate = mv88e6390_phylink_validate, 4173 }; 4174 4175 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4176 /* MV88E6XXX_FAMILY_6390 */ 4177 .setup_errata = mv88e6390_setup_errata, 4178 .irl_init_all = mv88e6390_g2_irl_init_all, 4179 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4180 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4181 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4182 .phy_read = mv88e6xxx_g2_smi_phy_read, 4183 .phy_write = mv88e6xxx_g2_smi_phy_write, 4184 .port_set_link = mv88e6xxx_port_set_link, 4185 .port_sync_link = mv88e6xxx_port_sync_link, 4186 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4187 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4188 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4189 .port_tag_remap = mv88e6390_port_tag_remap, 4190 .port_set_policy = mv88e6352_port_set_policy, 4191 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4192 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4193 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4194 .port_set_ether_type = mv88e6351_port_set_ether_type, 4195 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4196 .port_pause_limit = mv88e6390_port_pause_limit, 4197 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4198 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4199 .port_get_cmode = mv88e6352_port_get_cmode, 4200 .port_set_cmode = mv88e6390x_port_set_cmode, 4201 .port_setup_message_port = mv88e6xxx_setup_message_port, 4202 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4203 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4204 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4205 .stats_get_strings = mv88e6320_stats_get_strings, 4206 .stats_get_stats = mv88e6390_stats_get_stats, 4207 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4208 .set_egress_port = mv88e6390_g1_set_egress_port, 4209 .watchdog_ops = &mv88e6390_watchdog_ops, 4210 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4211 .pot_clear = mv88e6xxx_g2_pot_clear, 4212 .reset = mv88e6352_g1_reset, 4213 .rmu_disable = mv88e6390_g1_rmu_disable, 4214 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4215 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4216 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4217 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4218 .serdes_power = mv88e6390_serdes_power, 4219 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4220 /* Check status register pause & lpa register */ 4221 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4222 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4223 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4224 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4225 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4226 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4227 .serdes_irq_status = mv88e6390_serdes_irq_status, 4228 .serdes_get_strings = mv88e6390_serdes_get_strings, 4229 .serdes_get_stats = mv88e6390_serdes_get_stats, 4230 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4231 .serdes_get_regs = mv88e6390_serdes_get_regs, 4232 .gpio_ops = &mv88e6352_gpio_ops, 4233 .phylink_validate = mv88e6390x_phylink_validate, 4234 }; 4235 4236 static const struct mv88e6xxx_ops mv88e6191_ops = { 4237 /* MV88E6XXX_FAMILY_6390 */ 4238 .setup_errata = mv88e6390_setup_errata, 4239 .irl_init_all = mv88e6390_g2_irl_init_all, 4240 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4241 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4243 .phy_read = mv88e6xxx_g2_smi_phy_read, 4244 .phy_write = mv88e6xxx_g2_smi_phy_write, 4245 .port_set_link = mv88e6xxx_port_set_link, 4246 .port_sync_link = mv88e6xxx_port_sync_link, 4247 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4248 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4249 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4250 .port_tag_remap = mv88e6390_port_tag_remap, 4251 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4252 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4253 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4254 .port_set_ether_type = mv88e6351_port_set_ether_type, 4255 .port_pause_limit = mv88e6390_port_pause_limit, 4256 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4257 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4258 .port_get_cmode = mv88e6352_port_get_cmode, 4259 .port_set_cmode = mv88e6390_port_set_cmode, 4260 .port_setup_message_port = mv88e6xxx_setup_message_port, 4261 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4262 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4263 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4264 .stats_get_strings = mv88e6320_stats_get_strings, 4265 .stats_get_stats = mv88e6390_stats_get_stats, 4266 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4267 .set_egress_port = mv88e6390_g1_set_egress_port, 4268 .watchdog_ops = &mv88e6390_watchdog_ops, 4269 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4270 .pot_clear = mv88e6xxx_g2_pot_clear, 4271 .reset = mv88e6352_g1_reset, 4272 .rmu_disable = mv88e6390_g1_rmu_disable, 4273 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4274 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4275 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4276 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4277 .serdes_power = mv88e6390_serdes_power, 4278 .serdes_get_lane = mv88e6390_serdes_get_lane, 4279 /* Check status register pause & lpa register */ 4280 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4281 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4282 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4283 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4284 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4285 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4286 .serdes_irq_status = mv88e6390_serdes_irq_status, 4287 .serdes_get_strings = mv88e6390_serdes_get_strings, 4288 .serdes_get_stats = mv88e6390_serdes_get_stats, 4289 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4290 .serdes_get_regs = mv88e6390_serdes_get_regs, 4291 .avb_ops = &mv88e6390_avb_ops, 4292 .ptp_ops = &mv88e6352_ptp_ops, 4293 .phylink_validate = mv88e6390_phylink_validate, 4294 }; 4295 4296 static const struct mv88e6xxx_ops mv88e6240_ops = { 4297 /* MV88E6XXX_FAMILY_6352 */ 4298 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4299 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4300 .irl_init_all = mv88e6352_g2_irl_init_all, 4301 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4302 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4304 .phy_read = mv88e6xxx_g2_smi_phy_read, 4305 .phy_write = mv88e6xxx_g2_smi_phy_write, 4306 .port_set_link = mv88e6xxx_port_set_link, 4307 .port_sync_link = mv88e6xxx_port_sync_link, 4308 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4309 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4310 .port_tag_remap = mv88e6095_port_tag_remap, 4311 .port_set_policy = mv88e6352_port_set_policy, 4312 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4313 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4314 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4315 .port_set_ether_type = mv88e6351_port_set_ether_type, 4316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4318 .port_pause_limit = mv88e6097_port_pause_limit, 4319 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4320 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4321 .port_get_cmode = mv88e6352_port_get_cmode, 4322 .port_setup_message_port = mv88e6xxx_setup_message_port, 4323 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4324 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4325 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4326 .stats_get_strings = mv88e6095_stats_get_strings, 4327 .stats_get_stats = mv88e6095_stats_get_stats, 4328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4329 .set_egress_port = mv88e6095_g1_set_egress_port, 4330 .watchdog_ops = &mv88e6097_watchdog_ops, 4331 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4332 .pot_clear = mv88e6xxx_g2_pot_clear, 4333 .reset = mv88e6352_g1_reset, 4334 .rmu_disable = mv88e6352_g1_rmu_disable, 4335 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4336 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4337 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4338 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4339 .serdes_get_lane = mv88e6352_serdes_get_lane, 4340 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4341 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4342 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4343 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4344 .serdes_power = mv88e6352_serdes_power, 4345 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4346 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4347 .serdes_irq_status = mv88e6352_serdes_irq_status, 4348 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4349 .serdes_get_regs = mv88e6352_serdes_get_regs, 4350 .gpio_ops = &mv88e6352_gpio_ops, 4351 .avb_ops = &mv88e6352_avb_ops, 4352 .ptp_ops = &mv88e6352_ptp_ops, 4353 .phylink_validate = mv88e6352_phylink_validate, 4354 }; 4355 4356 static const struct mv88e6xxx_ops mv88e6250_ops = { 4357 /* MV88E6XXX_FAMILY_6250 */ 4358 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4359 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4360 .irl_init_all = mv88e6352_g2_irl_init_all, 4361 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4362 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4364 .phy_read = mv88e6xxx_g2_smi_phy_read, 4365 .phy_write = mv88e6xxx_g2_smi_phy_write, 4366 .port_set_link = mv88e6xxx_port_set_link, 4367 .port_sync_link = mv88e6xxx_port_sync_link, 4368 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4369 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4370 .port_tag_remap = mv88e6095_port_tag_remap, 4371 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4372 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4373 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4374 .port_set_ether_type = mv88e6351_port_set_ether_type, 4375 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4376 .port_pause_limit = mv88e6097_port_pause_limit, 4377 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4378 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4379 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4380 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4381 .stats_get_strings = mv88e6250_stats_get_strings, 4382 .stats_get_stats = mv88e6250_stats_get_stats, 4383 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4384 .set_egress_port = mv88e6095_g1_set_egress_port, 4385 .watchdog_ops = &mv88e6250_watchdog_ops, 4386 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4387 .pot_clear = mv88e6xxx_g2_pot_clear, 4388 .reset = mv88e6250_g1_reset, 4389 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4390 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4391 .avb_ops = &mv88e6352_avb_ops, 4392 .ptp_ops = &mv88e6250_ptp_ops, 4393 .phylink_validate = mv88e6065_phylink_validate, 4394 }; 4395 4396 static const struct mv88e6xxx_ops mv88e6290_ops = { 4397 /* MV88E6XXX_FAMILY_6390 */ 4398 .setup_errata = mv88e6390_setup_errata, 4399 .irl_init_all = mv88e6390_g2_irl_init_all, 4400 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4401 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4402 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4403 .phy_read = mv88e6xxx_g2_smi_phy_read, 4404 .phy_write = mv88e6xxx_g2_smi_phy_write, 4405 .port_set_link = mv88e6xxx_port_set_link, 4406 .port_sync_link = mv88e6xxx_port_sync_link, 4407 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4408 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4409 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4410 .port_tag_remap = mv88e6390_port_tag_remap, 4411 .port_set_policy = mv88e6352_port_set_policy, 4412 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4413 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4414 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4415 .port_set_ether_type = mv88e6351_port_set_ether_type, 4416 .port_pause_limit = mv88e6390_port_pause_limit, 4417 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4418 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4419 .port_get_cmode = mv88e6352_port_get_cmode, 4420 .port_set_cmode = mv88e6390_port_set_cmode, 4421 .port_setup_message_port = mv88e6xxx_setup_message_port, 4422 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4423 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4424 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4425 .stats_get_strings = mv88e6320_stats_get_strings, 4426 .stats_get_stats = mv88e6390_stats_get_stats, 4427 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4428 .set_egress_port = mv88e6390_g1_set_egress_port, 4429 .watchdog_ops = &mv88e6390_watchdog_ops, 4430 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4431 .pot_clear = mv88e6xxx_g2_pot_clear, 4432 .reset = mv88e6352_g1_reset, 4433 .rmu_disable = mv88e6390_g1_rmu_disable, 4434 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4435 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4436 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4437 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4438 .serdes_power = mv88e6390_serdes_power, 4439 .serdes_get_lane = mv88e6390_serdes_get_lane, 4440 /* Check status register pause & lpa register */ 4441 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4442 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4443 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4444 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4445 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4446 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4447 .serdes_irq_status = mv88e6390_serdes_irq_status, 4448 .serdes_get_strings = mv88e6390_serdes_get_strings, 4449 .serdes_get_stats = mv88e6390_serdes_get_stats, 4450 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4451 .serdes_get_regs = mv88e6390_serdes_get_regs, 4452 .gpio_ops = &mv88e6352_gpio_ops, 4453 .avb_ops = &mv88e6390_avb_ops, 4454 .ptp_ops = &mv88e6352_ptp_ops, 4455 .phylink_validate = mv88e6390_phylink_validate, 4456 }; 4457 4458 static const struct mv88e6xxx_ops mv88e6320_ops = { 4459 /* MV88E6XXX_FAMILY_6320 */ 4460 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4461 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4462 .irl_init_all = mv88e6352_g2_irl_init_all, 4463 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4464 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4465 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4466 .phy_read = mv88e6xxx_g2_smi_phy_read, 4467 .phy_write = mv88e6xxx_g2_smi_phy_write, 4468 .port_set_link = mv88e6xxx_port_set_link, 4469 .port_sync_link = mv88e6xxx_port_sync_link, 4470 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4471 .port_tag_remap = mv88e6095_port_tag_remap, 4472 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4473 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4474 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4475 .port_set_ether_type = mv88e6351_port_set_ether_type, 4476 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4477 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4478 .port_pause_limit = mv88e6097_port_pause_limit, 4479 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4480 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4481 .port_get_cmode = mv88e6352_port_get_cmode, 4482 .port_setup_message_port = mv88e6xxx_setup_message_port, 4483 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4484 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4485 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4486 .stats_get_strings = mv88e6320_stats_get_strings, 4487 .stats_get_stats = mv88e6320_stats_get_stats, 4488 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4489 .set_egress_port = mv88e6095_g1_set_egress_port, 4490 .watchdog_ops = &mv88e6390_watchdog_ops, 4491 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4492 .pot_clear = mv88e6xxx_g2_pot_clear, 4493 .reset = mv88e6352_g1_reset, 4494 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4495 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4496 .gpio_ops = &mv88e6352_gpio_ops, 4497 .avb_ops = &mv88e6352_avb_ops, 4498 .ptp_ops = &mv88e6352_ptp_ops, 4499 .phylink_validate = mv88e6185_phylink_validate, 4500 }; 4501 4502 static const struct mv88e6xxx_ops mv88e6321_ops = { 4503 /* MV88E6XXX_FAMILY_6320 */ 4504 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4505 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4506 .irl_init_all = mv88e6352_g2_irl_init_all, 4507 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4508 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4509 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4510 .phy_read = mv88e6xxx_g2_smi_phy_read, 4511 .phy_write = mv88e6xxx_g2_smi_phy_write, 4512 .port_set_link = mv88e6xxx_port_set_link, 4513 .port_sync_link = mv88e6xxx_port_sync_link, 4514 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4515 .port_tag_remap = mv88e6095_port_tag_remap, 4516 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4517 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4518 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4519 .port_set_ether_type = mv88e6351_port_set_ether_type, 4520 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4521 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4522 .port_pause_limit = mv88e6097_port_pause_limit, 4523 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4524 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4525 .port_get_cmode = mv88e6352_port_get_cmode, 4526 .port_setup_message_port = mv88e6xxx_setup_message_port, 4527 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4528 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4529 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4530 .stats_get_strings = mv88e6320_stats_get_strings, 4531 .stats_get_stats = mv88e6320_stats_get_stats, 4532 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4533 .set_egress_port = mv88e6095_g1_set_egress_port, 4534 .watchdog_ops = &mv88e6390_watchdog_ops, 4535 .reset = mv88e6352_g1_reset, 4536 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4537 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4538 .gpio_ops = &mv88e6352_gpio_ops, 4539 .avb_ops = &mv88e6352_avb_ops, 4540 .ptp_ops = &mv88e6352_ptp_ops, 4541 .phylink_validate = mv88e6185_phylink_validate, 4542 }; 4543 4544 static const struct mv88e6xxx_ops mv88e6341_ops = { 4545 /* MV88E6XXX_FAMILY_6341 */ 4546 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4547 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4548 .irl_init_all = mv88e6352_g2_irl_init_all, 4549 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4550 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4551 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4552 .phy_read = mv88e6xxx_g2_smi_phy_read, 4553 .phy_write = mv88e6xxx_g2_smi_phy_write, 4554 .port_set_link = mv88e6xxx_port_set_link, 4555 .port_sync_link = mv88e6xxx_port_sync_link, 4556 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4557 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4558 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4559 .port_tag_remap = mv88e6095_port_tag_remap, 4560 .port_set_policy = mv88e6352_port_set_policy, 4561 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4562 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4563 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4564 .port_set_ether_type = mv88e6351_port_set_ether_type, 4565 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4566 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4567 .port_pause_limit = mv88e6097_port_pause_limit, 4568 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4569 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4570 .port_get_cmode = mv88e6352_port_get_cmode, 4571 .port_set_cmode = mv88e6341_port_set_cmode, 4572 .port_setup_message_port = mv88e6xxx_setup_message_port, 4573 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4574 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4575 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4576 .stats_get_strings = mv88e6320_stats_get_strings, 4577 .stats_get_stats = mv88e6390_stats_get_stats, 4578 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4579 .set_egress_port = mv88e6390_g1_set_egress_port, 4580 .watchdog_ops = &mv88e6390_watchdog_ops, 4581 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4582 .pot_clear = mv88e6xxx_g2_pot_clear, 4583 .reset = mv88e6352_g1_reset, 4584 .rmu_disable = mv88e6390_g1_rmu_disable, 4585 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4586 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4587 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4588 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4589 .serdes_power = mv88e6390_serdes_power, 4590 .serdes_get_lane = mv88e6341_serdes_get_lane, 4591 /* Check status register pause & lpa register */ 4592 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4593 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4594 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4595 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4596 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4597 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4598 .serdes_irq_status = mv88e6390_serdes_irq_status, 4599 .gpio_ops = &mv88e6352_gpio_ops, 4600 .avb_ops = &mv88e6390_avb_ops, 4601 .ptp_ops = &mv88e6352_ptp_ops, 4602 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4603 .serdes_get_strings = mv88e6390_serdes_get_strings, 4604 .serdes_get_stats = mv88e6390_serdes_get_stats, 4605 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4606 .serdes_get_regs = mv88e6390_serdes_get_regs, 4607 .phylink_validate = mv88e6341_phylink_validate, 4608 }; 4609 4610 static const struct mv88e6xxx_ops mv88e6350_ops = { 4611 /* MV88E6XXX_FAMILY_6351 */ 4612 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4613 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4614 .irl_init_all = mv88e6352_g2_irl_init_all, 4615 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4616 .phy_read = mv88e6xxx_g2_smi_phy_read, 4617 .phy_write = mv88e6xxx_g2_smi_phy_write, 4618 .port_set_link = mv88e6xxx_port_set_link, 4619 .port_sync_link = mv88e6xxx_port_sync_link, 4620 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4621 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4622 .port_tag_remap = mv88e6095_port_tag_remap, 4623 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4624 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4625 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4626 .port_set_ether_type = mv88e6351_port_set_ether_type, 4627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4629 .port_pause_limit = mv88e6097_port_pause_limit, 4630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4632 .port_get_cmode = mv88e6352_port_get_cmode, 4633 .port_setup_message_port = mv88e6xxx_setup_message_port, 4634 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4635 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4636 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4637 .stats_get_strings = mv88e6095_stats_get_strings, 4638 .stats_get_stats = mv88e6095_stats_get_stats, 4639 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4640 .set_egress_port = mv88e6095_g1_set_egress_port, 4641 .watchdog_ops = &mv88e6097_watchdog_ops, 4642 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4643 .pot_clear = mv88e6xxx_g2_pot_clear, 4644 .reset = mv88e6352_g1_reset, 4645 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4646 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4647 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4648 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4649 .phylink_validate = mv88e6185_phylink_validate, 4650 }; 4651 4652 static const struct mv88e6xxx_ops mv88e6351_ops = { 4653 /* MV88E6XXX_FAMILY_6351 */ 4654 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4655 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4656 .irl_init_all = mv88e6352_g2_irl_init_all, 4657 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4658 .phy_read = mv88e6xxx_g2_smi_phy_read, 4659 .phy_write = mv88e6xxx_g2_smi_phy_write, 4660 .port_set_link = mv88e6xxx_port_set_link, 4661 .port_sync_link = mv88e6xxx_port_sync_link, 4662 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4663 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4664 .port_tag_remap = mv88e6095_port_tag_remap, 4665 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4666 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4667 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4668 .port_set_ether_type = mv88e6351_port_set_ether_type, 4669 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4670 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4671 .port_pause_limit = mv88e6097_port_pause_limit, 4672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4674 .port_get_cmode = mv88e6352_port_get_cmode, 4675 .port_setup_message_port = mv88e6xxx_setup_message_port, 4676 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4677 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4678 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4679 .stats_get_strings = mv88e6095_stats_get_strings, 4680 .stats_get_stats = mv88e6095_stats_get_stats, 4681 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4682 .set_egress_port = mv88e6095_g1_set_egress_port, 4683 .watchdog_ops = &mv88e6097_watchdog_ops, 4684 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4685 .pot_clear = mv88e6xxx_g2_pot_clear, 4686 .reset = mv88e6352_g1_reset, 4687 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4688 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4689 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4690 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4691 .avb_ops = &mv88e6352_avb_ops, 4692 .ptp_ops = &mv88e6352_ptp_ops, 4693 .phylink_validate = mv88e6185_phylink_validate, 4694 }; 4695 4696 static const struct mv88e6xxx_ops mv88e6352_ops = { 4697 /* MV88E6XXX_FAMILY_6352 */ 4698 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4699 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4700 .irl_init_all = mv88e6352_g2_irl_init_all, 4701 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4702 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4703 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4704 .phy_read = mv88e6xxx_g2_smi_phy_read, 4705 .phy_write = mv88e6xxx_g2_smi_phy_write, 4706 .port_set_link = mv88e6xxx_port_set_link, 4707 .port_sync_link = mv88e6xxx_port_sync_link, 4708 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4709 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4710 .port_tag_remap = mv88e6095_port_tag_remap, 4711 .port_set_policy = mv88e6352_port_set_policy, 4712 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4713 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4714 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4715 .port_set_ether_type = mv88e6351_port_set_ether_type, 4716 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4717 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4718 .port_pause_limit = mv88e6097_port_pause_limit, 4719 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4720 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4721 .port_get_cmode = mv88e6352_port_get_cmode, 4722 .port_setup_message_port = mv88e6xxx_setup_message_port, 4723 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4724 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4725 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4726 .stats_get_strings = mv88e6095_stats_get_strings, 4727 .stats_get_stats = mv88e6095_stats_get_stats, 4728 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4729 .set_egress_port = mv88e6095_g1_set_egress_port, 4730 .watchdog_ops = &mv88e6097_watchdog_ops, 4731 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4732 .pot_clear = mv88e6xxx_g2_pot_clear, 4733 .reset = mv88e6352_g1_reset, 4734 .rmu_disable = mv88e6352_g1_rmu_disable, 4735 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4736 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4737 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4738 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4739 .serdes_get_lane = mv88e6352_serdes_get_lane, 4740 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4741 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4742 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4743 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4744 .serdes_power = mv88e6352_serdes_power, 4745 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4746 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4747 .serdes_irq_status = mv88e6352_serdes_irq_status, 4748 .gpio_ops = &mv88e6352_gpio_ops, 4749 .avb_ops = &mv88e6352_avb_ops, 4750 .ptp_ops = &mv88e6352_ptp_ops, 4751 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4752 .serdes_get_strings = mv88e6352_serdes_get_strings, 4753 .serdes_get_stats = mv88e6352_serdes_get_stats, 4754 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4755 .serdes_get_regs = mv88e6352_serdes_get_regs, 4756 .phylink_validate = mv88e6352_phylink_validate, 4757 }; 4758 4759 static const struct mv88e6xxx_ops mv88e6390_ops = { 4760 /* MV88E6XXX_FAMILY_6390 */ 4761 .setup_errata = mv88e6390_setup_errata, 4762 .irl_init_all = mv88e6390_g2_irl_init_all, 4763 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4764 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4765 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4766 .phy_read = mv88e6xxx_g2_smi_phy_read, 4767 .phy_write = mv88e6xxx_g2_smi_phy_write, 4768 .port_set_link = mv88e6xxx_port_set_link, 4769 .port_sync_link = mv88e6xxx_port_sync_link, 4770 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4771 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4772 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4773 .port_tag_remap = mv88e6390_port_tag_remap, 4774 .port_set_policy = mv88e6352_port_set_policy, 4775 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4776 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4777 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4778 .port_set_ether_type = mv88e6351_port_set_ether_type, 4779 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4780 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4781 .port_pause_limit = mv88e6390_port_pause_limit, 4782 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4783 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4784 .port_get_cmode = mv88e6352_port_get_cmode, 4785 .port_set_cmode = mv88e6390_port_set_cmode, 4786 .port_setup_message_port = mv88e6xxx_setup_message_port, 4787 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4788 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4789 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4790 .stats_get_strings = mv88e6320_stats_get_strings, 4791 .stats_get_stats = mv88e6390_stats_get_stats, 4792 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4793 .set_egress_port = mv88e6390_g1_set_egress_port, 4794 .watchdog_ops = &mv88e6390_watchdog_ops, 4795 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4796 .pot_clear = mv88e6xxx_g2_pot_clear, 4797 .reset = mv88e6352_g1_reset, 4798 .rmu_disable = mv88e6390_g1_rmu_disable, 4799 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4800 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4801 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4802 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4803 .serdes_power = mv88e6390_serdes_power, 4804 .serdes_get_lane = mv88e6390_serdes_get_lane, 4805 /* Check status register pause & lpa register */ 4806 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4807 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4808 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4809 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4810 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4811 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4812 .serdes_irq_status = mv88e6390_serdes_irq_status, 4813 .gpio_ops = &mv88e6352_gpio_ops, 4814 .avb_ops = &mv88e6390_avb_ops, 4815 .ptp_ops = &mv88e6352_ptp_ops, 4816 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4817 .serdes_get_strings = mv88e6390_serdes_get_strings, 4818 .serdes_get_stats = mv88e6390_serdes_get_stats, 4819 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4820 .serdes_get_regs = mv88e6390_serdes_get_regs, 4821 .phylink_validate = mv88e6390_phylink_validate, 4822 }; 4823 4824 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4825 /* MV88E6XXX_FAMILY_6390 */ 4826 .setup_errata = mv88e6390_setup_errata, 4827 .irl_init_all = mv88e6390_g2_irl_init_all, 4828 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4829 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4830 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4831 .phy_read = mv88e6xxx_g2_smi_phy_read, 4832 .phy_write = mv88e6xxx_g2_smi_phy_write, 4833 .port_set_link = mv88e6xxx_port_set_link, 4834 .port_sync_link = mv88e6xxx_port_sync_link, 4835 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4836 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4837 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4838 .port_tag_remap = mv88e6390_port_tag_remap, 4839 .port_set_policy = mv88e6352_port_set_policy, 4840 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4841 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4842 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4843 .port_set_ether_type = mv88e6351_port_set_ether_type, 4844 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4845 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4846 .port_pause_limit = mv88e6390_port_pause_limit, 4847 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4848 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4849 .port_get_cmode = mv88e6352_port_get_cmode, 4850 .port_set_cmode = mv88e6390x_port_set_cmode, 4851 .port_setup_message_port = mv88e6xxx_setup_message_port, 4852 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4853 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4854 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4855 .stats_get_strings = mv88e6320_stats_get_strings, 4856 .stats_get_stats = mv88e6390_stats_get_stats, 4857 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4858 .set_egress_port = mv88e6390_g1_set_egress_port, 4859 .watchdog_ops = &mv88e6390_watchdog_ops, 4860 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4861 .pot_clear = mv88e6xxx_g2_pot_clear, 4862 .reset = mv88e6352_g1_reset, 4863 .rmu_disable = mv88e6390_g1_rmu_disable, 4864 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4865 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4866 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4867 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4868 .serdes_power = mv88e6390_serdes_power, 4869 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4870 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4871 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4872 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4873 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4874 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4875 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4876 .serdes_irq_status = mv88e6390_serdes_irq_status, 4877 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4878 .serdes_get_strings = mv88e6390_serdes_get_strings, 4879 .serdes_get_stats = mv88e6390_serdes_get_stats, 4880 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4881 .serdes_get_regs = mv88e6390_serdes_get_regs, 4882 .gpio_ops = &mv88e6352_gpio_ops, 4883 .avb_ops = &mv88e6390_avb_ops, 4884 .ptp_ops = &mv88e6352_ptp_ops, 4885 .phylink_validate = mv88e6390x_phylink_validate, 4886 }; 4887 4888 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4889 /* MV88E6XXX_FAMILY_6393 */ 4890 .setup_errata = mv88e6393x_serdes_setup_errata, 4891 .irl_init_all = mv88e6390_g2_irl_init_all, 4892 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4893 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4895 .phy_read = mv88e6xxx_g2_smi_phy_read, 4896 .phy_write = mv88e6xxx_g2_smi_phy_write, 4897 .port_set_link = mv88e6xxx_port_set_link, 4898 .port_sync_link = mv88e6xxx_port_sync_link, 4899 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4900 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4901 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4902 .port_tag_remap = mv88e6390_port_tag_remap, 4903 .port_set_policy = mv88e6393x_port_set_policy, 4904 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4905 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4906 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4907 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4909 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4910 .port_pause_limit = mv88e6390_port_pause_limit, 4911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4913 .port_get_cmode = mv88e6352_port_get_cmode, 4914 .port_set_cmode = mv88e6393x_port_set_cmode, 4915 .port_setup_message_port = mv88e6xxx_setup_message_port, 4916 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4917 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4918 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4919 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4920 .stats_get_strings = mv88e6320_stats_get_strings, 4921 .stats_get_stats = mv88e6390_stats_get_stats, 4922 /* .set_cpu_port is missing because this family does not support a global 4923 * CPU port, only per port CPU port which is set via 4924 * .port_set_upstream_port method. 4925 */ 4926 .set_egress_port = mv88e6393x_set_egress_port, 4927 .watchdog_ops = &mv88e6390_watchdog_ops, 4928 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4929 .pot_clear = mv88e6xxx_g2_pot_clear, 4930 .reset = mv88e6352_g1_reset, 4931 .rmu_disable = mv88e6390_g1_rmu_disable, 4932 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4933 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4934 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4935 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4936 .serdes_power = mv88e6393x_serdes_power, 4937 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4938 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4939 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4940 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4941 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4942 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4943 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4944 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4945 /* TODO: serdes stats */ 4946 .gpio_ops = &mv88e6352_gpio_ops, 4947 .avb_ops = &mv88e6390_avb_ops, 4948 .ptp_ops = &mv88e6352_ptp_ops, 4949 .phylink_validate = mv88e6393x_phylink_validate, 4950 }; 4951 4952 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4953 [MV88E6085] = { 4954 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4955 .family = MV88E6XXX_FAMILY_6097, 4956 .name = "Marvell 88E6085", 4957 .num_databases = 4096, 4958 .num_macs = 8192, 4959 .num_ports = 10, 4960 .num_internal_phys = 5, 4961 .max_vid = 4095, 4962 .port_base_addr = 0x10, 4963 .phy_base_addr = 0x0, 4964 .global1_addr = 0x1b, 4965 .global2_addr = 0x1c, 4966 .age_time_coeff = 15000, 4967 .g1_irqs = 8, 4968 .g2_irqs = 10, 4969 .atu_move_port_mask = 0xf, 4970 .pvt = true, 4971 .multi_chip = true, 4972 .ops = &mv88e6085_ops, 4973 }, 4974 4975 [MV88E6095] = { 4976 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4977 .family = MV88E6XXX_FAMILY_6095, 4978 .name = "Marvell 88E6095/88E6095F", 4979 .num_databases = 256, 4980 .num_macs = 8192, 4981 .num_ports = 11, 4982 .num_internal_phys = 0, 4983 .max_vid = 4095, 4984 .port_base_addr = 0x10, 4985 .phy_base_addr = 0x0, 4986 .global1_addr = 0x1b, 4987 .global2_addr = 0x1c, 4988 .age_time_coeff = 15000, 4989 .g1_irqs = 8, 4990 .atu_move_port_mask = 0xf, 4991 .multi_chip = true, 4992 .ops = &mv88e6095_ops, 4993 }, 4994 4995 [MV88E6097] = { 4996 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4997 .family = MV88E6XXX_FAMILY_6097, 4998 .name = "Marvell 88E6097/88E6097F", 4999 .num_databases = 4096, 5000 .num_macs = 8192, 5001 .num_ports = 11, 5002 .num_internal_phys = 8, 5003 .max_vid = 4095, 5004 .port_base_addr = 0x10, 5005 .phy_base_addr = 0x0, 5006 .global1_addr = 0x1b, 5007 .global2_addr = 0x1c, 5008 .age_time_coeff = 15000, 5009 .g1_irqs = 8, 5010 .g2_irqs = 10, 5011 .atu_move_port_mask = 0xf, 5012 .pvt = true, 5013 .multi_chip = true, 5014 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5015 .ops = &mv88e6097_ops, 5016 }, 5017 5018 [MV88E6123] = { 5019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5020 .family = MV88E6XXX_FAMILY_6165, 5021 .name = "Marvell 88E6123", 5022 .num_databases = 4096, 5023 .num_macs = 1024, 5024 .num_ports = 3, 5025 .num_internal_phys = 5, 5026 .max_vid = 4095, 5027 .port_base_addr = 0x10, 5028 .phy_base_addr = 0x0, 5029 .global1_addr = 0x1b, 5030 .global2_addr = 0x1c, 5031 .age_time_coeff = 15000, 5032 .g1_irqs = 9, 5033 .g2_irqs = 10, 5034 .atu_move_port_mask = 0xf, 5035 .pvt = true, 5036 .multi_chip = true, 5037 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5038 .ops = &mv88e6123_ops, 5039 }, 5040 5041 [MV88E6131] = { 5042 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5043 .family = MV88E6XXX_FAMILY_6185, 5044 .name = "Marvell 88E6131", 5045 .num_databases = 256, 5046 .num_macs = 8192, 5047 .num_ports = 8, 5048 .num_internal_phys = 0, 5049 .max_vid = 4095, 5050 .port_base_addr = 0x10, 5051 .phy_base_addr = 0x0, 5052 .global1_addr = 0x1b, 5053 .global2_addr = 0x1c, 5054 .age_time_coeff = 15000, 5055 .g1_irqs = 9, 5056 .atu_move_port_mask = 0xf, 5057 .multi_chip = true, 5058 .ops = &mv88e6131_ops, 5059 }, 5060 5061 [MV88E6141] = { 5062 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5063 .family = MV88E6XXX_FAMILY_6341, 5064 .name = "Marvell 88E6141", 5065 .num_databases = 4096, 5066 .num_macs = 2048, 5067 .num_ports = 6, 5068 .num_internal_phys = 5, 5069 .num_gpio = 11, 5070 .max_vid = 4095, 5071 .port_base_addr = 0x10, 5072 .phy_base_addr = 0x10, 5073 .global1_addr = 0x1b, 5074 .global2_addr = 0x1c, 5075 .age_time_coeff = 3750, 5076 .atu_move_port_mask = 0x1f, 5077 .g1_irqs = 9, 5078 .g2_irqs = 10, 5079 .pvt = true, 5080 .multi_chip = true, 5081 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5082 .ops = &mv88e6141_ops, 5083 }, 5084 5085 [MV88E6161] = { 5086 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5087 .family = MV88E6XXX_FAMILY_6165, 5088 .name = "Marvell 88E6161", 5089 .num_databases = 4096, 5090 .num_macs = 1024, 5091 .num_ports = 6, 5092 .num_internal_phys = 5, 5093 .max_vid = 4095, 5094 .port_base_addr = 0x10, 5095 .phy_base_addr = 0x0, 5096 .global1_addr = 0x1b, 5097 .global2_addr = 0x1c, 5098 .age_time_coeff = 15000, 5099 .g1_irqs = 9, 5100 .g2_irqs = 10, 5101 .atu_move_port_mask = 0xf, 5102 .pvt = true, 5103 .multi_chip = true, 5104 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5105 .ptp_support = true, 5106 .ops = &mv88e6161_ops, 5107 }, 5108 5109 [MV88E6165] = { 5110 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5111 .family = MV88E6XXX_FAMILY_6165, 5112 .name = "Marvell 88E6165", 5113 .num_databases = 4096, 5114 .num_macs = 8192, 5115 .num_ports = 6, 5116 .num_internal_phys = 0, 5117 .max_vid = 4095, 5118 .port_base_addr = 0x10, 5119 .phy_base_addr = 0x0, 5120 .global1_addr = 0x1b, 5121 .global2_addr = 0x1c, 5122 .age_time_coeff = 15000, 5123 .g1_irqs = 9, 5124 .g2_irqs = 10, 5125 .atu_move_port_mask = 0xf, 5126 .pvt = true, 5127 .multi_chip = true, 5128 .ptp_support = true, 5129 .ops = &mv88e6165_ops, 5130 }, 5131 5132 [MV88E6171] = { 5133 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5134 .family = MV88E6XXX_FAMILY_6351, 5135 .name = "Marvell 88E6171", 5136 .num_databases = 4096, 5137 .num_macs = 8192, 5138 .num_ports = 7, 5139 .num_internal_phys = 5, 5140 .max_vid = 4095, 5141 .port_base_addr = 0x10, 5142 .phy_base_addr = 0x0, 5143 .global1_addr = 0x1b, 5144 .global2_addr = 0x1c, 5145 .age_time_coeff = 15000, 5146 .g1_irqs = 9, 5147 .g2_irqs = 10, 5148 .atu_move_port_mask = 0xf, 5149 .pvt = true, 5150 .multi_chip = true, 5151 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5152 .ops = &mv88e6171_ops, 5153 }, 5154 5155 [MV88E6172] = { 5156 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5157 .family = MV88E6XXX_FAMILY_6352, 5158 .name = "Marvell 88E6172", 5159 .num_databases = 4096, 5160 .num_macs = 8192, 5161 .num_ports = 7, 5162 .num_internal_phys = 5, 5163 .num_gpio = 15, 5164 .max_vid = 4095, 5165 .port_base_addr = 0x10, 5166 .phy_base_addr = 0x0, 5167 .global1_addr = 0x1b, 5168 .global2_addr = 0x1c, 5169 .age_time_coeff = 15000, 5170 .g1_irqs = 9, 5171 .g2_irqs = 10, 5172 .atu_move_port_mask = 0xf, 5173 .pvt = true, 5174 .multi_chip = true, 5175 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5176 .ops = &mv88e6172_ops, 5177 }, 5178 5179 [MV88E6175] = { 5180 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5181 .family = MV88E6XXX_FAMILY_6351, 5182 .name = "Marvell 88E6175", 5183 .num_databases = 4096, 5184 .num_macs = 8192, 5185 .num_ports = 7, 5186 .num_internal_phys = 5, 5187 .max_vid = 4095, 5188 .port_base_addr = 0x10, 5189 .phy_base_addr = 0x0, 5190 .global1_addr = 0x1b, 5191 .global2_addr = 0x1c, 5192 .age_time_coeff = 15000, 5193 .g1_irqs = 9, 5194 .g2_irqs = 10, 5195 .atu_move_port_mask = 0xf, 5196 .pvt = true, 5197 .multi_chip = true, 5198 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5199 .ops = &mv88e6175_ops, 5200 }, 5201 5202 [MV88E6176] = { 5203 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5204 .family = MV88E6XXX_FAMILY_6352, 5205 .name = "Marvell 88E6176", 5206 .num_databases = 4096, 5207 .num_macs = 8192, 5208 .num_ports = 7, 5209 .num_internal_phys = 5, 5210 .num_gpio = 15, 5211 .max_vid = 4095, 5212 .port_base_addr = 0x10, 5213 .phy_base_addr = 0x0, 5214 .global1_addr = 0x1b, 5215 .global2_addr = 0x1c, 5216 .age_time_coeff = 15000, 5217 .g1_irqs = 9, 5218 .g2_irqs = 10, 5219 .atu_move_port_mask = 0xf, 5220 .pvt = true, 5221 .multi_chip = true, 5222 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5223 .ops = &mv88e6176_ops, 5224 }, 5225 5226 [MV88E6185] = { 5227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5228 .family = MV88E6XXX_FAMILY_6185, 5229 .name = "Marvell 88E6185", 5230 .num_databases = 256, 5231 .num_macs = 8192, 5232 .num_ports = 10, 5233 .num_internal_phys = 0, 5234 .max_vid = 4095, 5235 .port_base_addr = 0x10, 5236 .phy_base_addr = 0x0, 5237 .global1_addr = 0x1b, 5238 .global2_addr = 0x1c, 5239 .age_time_coeff = 15000, 5240 .g1_irqs = 8, 5241 .atu_move_port_mask = 0xf, 5242 .multi_chip = true, 5243 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5244 .ops = &mv88e6185_ops, 5245 }, 5246 5247 [MV88E6190] = { 5248 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5249 .family = MV88E6XXX_FAMILY_6390, 5250 .name = "Marvell 88E6190", 5251 .num_databases = 4096, 5252 .num_macs = 16384, 5253 .num_ports = 11, /* 10 + Z80 */ 5254 .num_internal_phys = 9, 5255 .num_gpio = 16, 5256 .max_vid = 8191, 5257 .port_base_addr = 0x0, 5258 .phy_base_addr = 0x0, 5259 .global1_addr = 0x1b, 5260 .global2_addr = 0x1c, 5261 .age_time_coeff = 3750, 5262 .g1_irqs = 9, 5263 .g2_irqs = 14, 5264 .pvt = true, 5265 .multi_chip = true, 5266 .atu_move_port_mask = 0x1f, 5267 .ops = &mv88e6190_ops, 5268 }, 5269 5270 [MV88E6190X] = { 5271 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5272 .family = MV88E6XXX_FAMILY_6390, 5273 .name = "Marvell 88E6190X", 5274 .num_databases = 4096, 5275 .num_macs = 16384, 5276 .num_ports = 11, /* 10 + Z80 */ 5277 .num_internal_phys = 9, 5278 .num_gpio = 16, 5279 .max_vid = 8191, 5280 .port_base_addr = 0x0, 5281 .phy_base_addr = 0x0, 5282 .global1_addr = 0x1b, 5283 .global2_addr = 0x1c, 5284 .age_time_coeff = 3750, 5285 .g1_irqs = 9, 5286 .g2_irqs = 14, 5287 .atu_move_port_mask = 0x1f, 5288 .pvt = true, 5289 .multi_chip = true, 5290 .ops = &mv88e6190x_ops, 5291 }, 5292 5293 [MV88E6191] = { 5294 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5295 .family = MV88E6XXX_FAMILY_6390, 5296 .name = "Marvell 88E6191", 5297 .num_databases = 4096, 5298 .num_macs = 16384, 5299 .num_ports = 11, /* 10 + Z80 */ 5300 .num_internal_phys = 9, 5301 .max_vid = 8191, 5302 .port_base_addr = 0x0, 5303 .phy_base_addr = 0x0, 5304 .global1_addr = 0x1b, 5305 .global2_addr = 0x1c, 5306 .age_time_coeff = 3750, 5307 .g1_irqs = 9, 5308 .g2_irqs = 14, 5309 .atu_move_port_mask = 0x1f, 5310 .pvt = true, 5311 .multi_chip = true, 5312 .ptp_support = true, 5313 .ops = &mv88e6191_ops, 5314 }, 5315 5316 [MV88E6191X] = { 5317 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5318 .family = MV88E6XXX_FAMILY_6393, 5319 .name = "Marvell 88E6191X", 5320 .num_databases = 4096, 5321 .num_ports = 11, /* 10 + Z80 */ 5322 .num_internal_phys = 9, 5323 .max_vid = 8191, 5324 .port_base_addr = 0x0, 5325 .phy_base_addr = 0x0, 5326 .global1_addr = 0x1b, 5327 .global2_addr = 0x1c, 5328 .age_time_coeff = 3750, 5329 .g1_irqs = 10, 5330 .g2_irqs = 14, 5331 .atu_move_port_mask = 0x1f, 5332 .pvt = true, 5333 .multi_chip = true, 5334 .ptp_support = true, 5335 .ops = &mv88e6393x_ops, 5336 }, 5337 5338 [MV88E6193X] = { 5339 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5340 .family = MV88E6XXX_FAMILY_6393, 5341 .name = "Marvell 88E6193X", 5342 .num_databases = 4096, 5343 .num_ports = 11, /* 10 + Z80 */ 5344 .num_internal_phys = 9, 5345 .max_vid = 8191, 5346 .port_base_addr = 0x0, 5347 .phy_base_addr = 0x0, 5348 .global1_addr = 0x1b, 5349 .global2_addr = 0x1c, 5350 .age_time_coeff = 3750, 5351 .g1_irqs = 10, 5352 .g2_irqs = 14, 5353 .atu_move_port_mask = 0x1f, 5354 .pvt = true, 5355 .multi_chip = true, 5356 .ptp_support = true, 5357 .ops = &mv88e6393x_ops, 5358 }, 5359 5360 [MV88E6220] = { 5361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5362 .family = MV88E6XXX_FAMILY_6250, 5363 .name = "Marvell 88E6220", 5364 .num_databases = 64, 5365 5366 /* Ports 2-4 are not routed to pins 5367 * => usable ports 0, 1, 5, 6 5368 */ 5369 .num_ports = 7, 5370 .num_internal_phys = 2, 5371 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5372 .max_vid = 4095, 5373 .port_base_addr = 0x08, 5374 .phy_base_addr = 0x00, 5375 .global1_addr = 0x0f, 5376 .global2_addr = 0x07, 5377 .age_time_coeff = 15000, 5378 .g1_irqs = 9, 5379 .g2_irqs = 10, 5380 .atu_move_port_mask = 0xf, 5381 .dual_chip = true, 5382 .ptp_support = true, 5383 .ops = &mv88e6250_ops, 5384 }, 5385 5386 [MV88E6240] = { 5387 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5388 .family = MV88E6XXX_FAMILY_6352, 5389 .name = "Marvell 88E6240", 5390 .num_databases = 4096, 5391 .num_macs = 8192, 5392 .num_ports = 7, 5393 .num_internal_phys = 5, 5394 .num_gpio = 15, 5395 .max_vid = 4095, 5396 .port_base_addr = 0x10, 5397 .phy_base_addr = 0x0, 5398 .global1_addr = 0x1b, 5399 .global2_addr = 0x1c, 5400 .age_time_coeff = 15000, 5401 .g1_irqs = 9, 5402 .g2_irqs = 10, 5403 .atu_move_port_mask = 0xf, 5404 .pvt = true, 5405 .multi_chip = true, 5406 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5407 .ptp_support = true, 5408 .ops = &mv88e6240_ops, 5409 }, 5410 5411 [MV88E6250] = { 5412 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5413 .family = MV88E6XXX_FAMILY_6250, 5414 .name = "Marvell 88E6250", 5415 .num_databases = 64, 5416 .num_ports = 7, 5417 .num_internal_phys = 5, 5418 .max_vid = 4095, 5419 .port_base_addr = 0x08, 5420 .phy_base_addr = 0x00, 5421 .global1_addr = 0x0f, 5422 .global2_addr = 0x07, 5423 .age_time_coeff = 15000, 5424 .g1_irqs = 9, 5425 .g2_irqs = 10, 5426 .atu_move_port_mask = 0xf, 5427 .dual_chip = true, 5428 .ptp_support = true, 5429 .ops = &mv88e6250_ops, 5430 }, 5431 5432 [MV88E6290] = { 5433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5434 .family = MV88E6XXX_FAMILY_6390, 5435 .name = "Marvell 88E6290", 5436 .num_databases = 4096, 5437 .num_ports = 11, /* 10 + Z80 */ 5438 .num_internal_phys = 9, 5439 .num_gpio = 16, 5440 .max_vid = 8191, 5441 .port_base_addr = 0x0, 5442 .phy_base_addr = 0x0, 5443 .global1_addr = 0x1b, 5444 .global2_addr = 0x1c, 5445 .age_time_coeff = 3750, 5446 .g1_irqs = 9, 5447 .g2_irqs = 14, 5448 .atu_move_port_mask = 0x1f, 5449 .pvt = true, 5450 .multi_chip = true, 5451 .ptp_support = true, 5452 .ops = &mv88e6290_ops, 5453 }, 5454 5455 [MV88E6320] = { 5456 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5457 .family = MV88E6XXX_FAMILY_6320, 5458 .name = "Marvell 88E6320", 5459 .num_databases = 4096, 5460 .num_macs = 8192, 5461 .num_ports = 7, 5462 .num_internal_phys = 5, 5463 .num_gpio = 15, 5464 .max_vid = 4095, 5465 .port_base_addr = 0x10, 5466 .phy_base_addr = 0x0, 5467 .global1_addr = 0x1b, 5468 .global2_addr = 0x1c, 5469 .age_time_coeff = 15000, 5470 .g1_irqs = 8, 5471 .g2_irqs = 10, 5472 .atu_move_port_mask = 0xf, 5473 .pvt = true, 5474 .multi_chip = true, 5475 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5476 .ptp_support = true, 5477 .ops = &mv88e6320_ops, 5478 }, 5479 5480 [MV88E6321] = { 5481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5482 .family = MV88E6XXX_FAMILY_6320, 5483 .name = "Marvell 88E6321", 5484 .num_databases = 4096, 5485 .num_macs = 8192, 5486 .num_ports = 7, 5487 .num_internal_phys = 5, 5488 .num_gpio = 15, 5489 .max_vid = 4095, 5490 .port_base_addr = 0x10, 5491 .phy_base_addr = 0x0, 5492 .global1_addr = 0x1b, 5493 .global2_addr = 0x1c, 5494 .age_time_coeff = 15000, 5495 .g1_irqs = 8, 5496 .g2_irqs = 10, 5497 .atu_move_port_mask = 0xf, 5498 .multi_chip = true, 5499 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5500 .ptp_support = true, 5501 .ops = &mv88e6321_ops, 5502 }, 5503 5504 [MV88E6341] = { 5505 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5506 .family = MV88E6XXX_FAMILY_6341, 5507 .name = "Marvell 88E6341", 5508 .num_databases = 4096, 5509 .num_macs = 2048, 5510 .num_internal_phys = 5, 5511 .num_ports = 6, 5512 .num_gpio = 11, 5513 .max_vid = 4095, 5514 .port_base_addr = 0x10, 5515 .phy_base_addr = 0x10, 5516 .global1_addr = 0x1b, 5517 .global2_addr = 0x1c, 5518 .age_time_coeff = 3750, 5519 .atu_move_port_mask = 0x1f, 5520 .g1_irqs = 9, 5521 .g2_irqs = 10, 5522 .pvt = true, 5523 .multi_chip = true, 5524 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5525 .ptp_support = true, 5526 .ops = &mv88e6341_ops, 5527 }, 5528 5529 [MV88E6350] = { 5530 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5531 .family = MV88E6XXX_FAMILY_6351, 5532 .name = "Marvell 88E6350", 5533 .num_databases = 4096, 5534 .num_macs = 8192, 5535 .num_ports = 7, 5536 .num_internal_phys = 5, 5537 .max_vid = 4095, 5538 .port_base_addr = 0x10, 5539 .phy_base_addr = 0x0, 5540 .global1_addr = 0x1b, 5541 .global2_addr = 0x1c, 5542 .age_time_coeff = 15000, 5543 .g1_irqs = 9, 5544 .g2_irqs = 10, 5545 .atu_move_port_mask = 0xf, 5546 .pvt = true, 5547 .multi_chip = true, 5548 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5549 .ops = &mv88e6350_ops, 5550 }, 5551 5552 [MV88E6351] = { 5553 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5554 .family = MV88E6XXX_FAMILY_6351, 5555 .name = "Marvell 88E6351", 5556 .num_databases = 4096, 5557 .num_macs = 8192, 5558 .num_ports = 7, 5559 .num_internal_phys = 5, 5560 .max_vid = 4095, 5561 .port_base_addr = 0x10, 5562 .phy_base_addr = 0x0, 5563 .global1_addr = 0x1b, 5564 .global2_addr = 0x1c, 5565 .age_time_coeff = 15000, 5566 .g1_irqs = 9, 5567 .g2_irqs = 10, 5568 .atu_move_port_mask = 0xf, 5569 .pvt = true, 5570 .multi_chip = true, 5571 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5572 .ops = &mv88e6351_ops, 5573 }, 5574 5575 [MV88E6352] = { 5576 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5577 .family = MV88E6XXX_FAMILY_6352, 5578 .name = "Marvell 88E6352", 5579 .num_databases = 4096, 5580 .num_macs = 8192, 5581 .num_ports = 7, 5582 .num_internal_phys = 5, 5583 .num_gpio = 15, 5584 .max_vid = 4095, 5585 .port_base_addr = 0x10, 5586 .phy_base_addr = 0x0, 5587 .global1_addr = 0x1b, 5588 .global2_addr = 0x1c, 5589 .age_time_coeff = 15000, 5590 .g1_irqs = 9, 5591 .g2_irqs = 10, 5592 .atu_move_port_mask = 0xf, 5593 .pvt = true, 5594 .multi_chip = true, 5595 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5596 .ptp_support = true, 5597 .ops = &mv88e6352_ops, 5598 }, 5599 [MV88E6390] = { 5600 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5601 .family = MV88E6XXX_FAMILY_6390, 5602 .name = "Marvell 88E6390", 5603 .num_databases = 4096, 5604 .num_macs = 16384, 5605 .num_ports = 11, /* 10 + Z80 */ 5606 .num_internal_phys = 9, 5607 .num_gpio = 16, 5608 .max_vid = 8191, 5609 .port_base_addr = 0x0, 5610 .phy_base_addr = 0x0, 5611 .global1_addr = 0x1b, 5612 .global2_addr = 0x1c, 5613 .age_time_coeff = 3750, 5614 .g1_irqs = 9, 5615 .g2_irqs = 14, 5616 .atu_move_port_mask = 0x1f, 5617 .pvt = true, 5618 .multi_chip = true, 5619 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5620 .ptp_support = true, 5621 .ops = &mv88e6390_ops, 5622 }, 5623 [MV88E6390X] = { 5624 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5625 .family = MV88E6XXX_FAMILY_6390, 5626 .name = "Marvell 88E6390X", 5627 .num_databases = 4096, 5628 .num_macs = 16384, 5629 .num_ports = 11, /* 10 + Z80 */ 5630 .num_internal_phys = 9, 5631 .num_gpio = 16, 5632 .max_vid = 8191, 5633 .port_base_addr = 0x0, 5634 .phy_base_addr = 0x0, 5635 .global1_addr = 0x1b, 5636 .global2_addr = 0x1c, 5637 .age_time_coeff = 3750, 5638 .g1_irqs = 9, 5639 .g2_irqs = 14, 5640 .atu_move_port_mask = 0x1f, 5641 .pvt = true, 5642 .multi_chip = true, 5643 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5644 .ptp_support = true, 5645 .ops = &mv88e6390x_ops, 5646 }, 5647 5648 [MV88E6393X] = { 5649 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5650 .family = MV88E6XXX_FAMILY_6393, 5651 .name = "Marvell 88E6393X", 5652 .num_databases = 4096, 5653 .num_ports = 11, /* 10 + Z80 */ 5654 .num_internal_phys = 9, 5655 .max_vid = 8191, 5656 .port_base_addr = 0x0, 5657 .phy_base_addr = 0x0, 5658 .global1_addr = 0x1b, 5659 .global2_addr = 0x1c, 5660 .age_time_coeff = 3750, 5661 .g1_irqs = 10, 5662 .g2_irqs = 14, 5663 .atu_move_port_mask = 0x1f, 5664 .pvt = true, 5665 .multi_chip = true, 5666 .ptp_support = true, 5667 .ops = &mv88e6393x_ops, 5668 }, 5669 }; 5670 5671 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5672 { 5673 int i; 5674 5675 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5676 if (mv88e6xxx_table[i].prod_num == prod_num) 5677 return &mv88e6xxx_table[i]; 5678 5679 return NULL; 5680 } 5681 5682 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5683 { 5684 const struct mv88e6xxx_info *info; 5685 unsigned int prod_num, rev; 5686 u16 id; 5687 int err; 5688 5689 mv88e6xxx_reg_lock(chip); 5690 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5691 mv88e6xxx_reg_unlock(chip); 5692 if (err) 5693 return err; 5694 5695 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5696 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5697 5698 info = mv88e6xxx_lookup_info(prod_num); 5699 if (!info) 5700 return -ENODEV; 5701 5702 /* Update the compatible info with the probed one */ 5703 chip->info = info; 5704 5705 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5706 chip->info->prod_num, chip->info->name, rev); 5707 5708 return 0; 5709 } 5710 5711 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5712 { 5713 struct mv88e6xxx_chip *chip; 5714 5715 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5716 if (!chip) 5717 return NULL; 5718 5719 chip->dev = dev; 5720 5721 mutex_init(&chip->reg_lock); 5722 INIT_LIST_HEAD(&chip->mdios); 5723 idr_init(&chip->policies); 5724 5725 return chip; 5726 } 5727 5728 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5729 int port, 5730 enum dsa_tag_protocol m) 5731 { 5732 struct mv88e6xxx_chip *chip = ds->priv; 5733 5734 return chip->tag_protocol; 5735 } 5736 5737 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5738 enum dsa_tag_protocol proto) 5739 { 5740 struct mv88e6xxx_chip *chip = ds->priv; 5741 enum dsa_tag_protocol old_protocol; 5742 int err; 5743 5744 switch (proto) { 5745 case DSA_TAG_PROTO_EDSA: 5746 switch (chip->info->edsa_support) { 5747 case MV88E6XXX_EDSA_UNSUPPORTED: 5748 return -EPROTONOSUPPORT; 5749 case MV88E6XXX_EDSA_UNDOCUMENTED: 5750 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5751 fallthrough; 5752 case MV88E6XXX_EDSA_SUPPORTED: 5753 break; 5754 } 5755 break; 5756 case DSA_TAG_PROTO_DSA: 5757 break; 5758 default: 5759 return -EPROTONOSUPPORT; 5760 } 5761 5762 old_protocol = chip->tag_protocol; 5763 chip->tag_protocol = proto; 5764 5765 mv88e6xxx_reg_lock(chip); 5766 err = mv88e6xxx_setup_port_mode(chip, port); 5767 mv88e6xxx_reg_unlock(chip); 5768 5769 if (err) 5770 chip->tag_protocol = old_protocol; 5771 5772 return err; 5773 } 5774 5775 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5776 const struct switchdev_obj_port_mdb *mdb) 5777 { 5778 struct mv88e6xxx_chip *chip = ds->priv; 5779 int err; 5780 5781 mv88e6xxx_reg_lock(chip); 5782 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5783 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5784 mv88e6xxx_reg_unlock(chip); 5785 5786 return err; 5787 } 5788 5789 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5790 const struct switchdev_obj_port_mdb *mdb) 5791 { 5792 struct mv88e6xxx_chip *chip = ds->priv; 5793 int err; 5794 5795 mv88e6xxx_reg_lock(chip); 5796 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5797 mv88e6xxx_reg_unlock(chip); 5798 5799 return err; 5800 } 5801 5802 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5803 struct dsa_mall_mirror_tc_entry *mirror, 5804 bool ingress) 5805 { 5806 enum mv88e6xxx_egress_direction direction = ingress ? 5807 MV88E6XXX_EGRESS_DIR_INGRESS : 5808 MV88E6XXX_EGRESS_DIR_EGRESS; 5809 struct mv88e6xxx_chip *chip = ds->priv; 5810 bool other_mirrors = false; 5811 int i; 5812 int err; 5813 5814 mutex_lock(&chip->reg_lock); 5815 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5816 mirror->to_local_port) { 5817 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5818 other_mirrors |= ingress ? 5819 chip->ports[i].mirror_ingress : 5820 chip->ports[i].mirror_egress; 5821 5822 /* Can't change egress port when other mirror is active */ 5823 if (other_mirrors) { 5824 err = -EBUSY; 5825 goto out; 5826 } 5827 5828 err = mv88e6xxx_set_egress_port(chip, direction, 5829 mirror->to_local_port); 5830 if (err) 5831 goto out; 5832 } 5833 5834 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5835 out: 5836 mutex_unlock(&chip->reg_lock); 5837 5838 return err; 5839 } 5840 5841 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5842 struct dsa_mall_mirror_tc_entry *mirror) 5843 { 5844 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5845 MV88E6XXX_EGRESS_DIR_INGRESS : 5846 MV88E6XXX_EGRESS_DIR_EGRESS; 5847 struct mv88e6xxx_chip *chip = ds->priv; 5848 bool other_mirrors = false; 5849 int i; 5850 5851 mutex_lock(&chip->reg_lock); 5852 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5853 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5854 5855 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5856 other_mirrors |= mirror->ingress ? 5857 chip->ports[i].mirror_ingress : 5858 chip->ports[i].mirror_egress; 5859 5860 /* Reset egress port when no other mirror is active */ 5861 if (!other_mirrors) { 5862 if (mv88e6xxx_set_egress_port(chip, direction, 5863 dsa_upstream_port(ds, port))) 5864 dev_err(ds->dev, "failed to set egress port\n"); 5865 } 5866 5867 mutex_unlock(&chip->reg_lock); 5868 } 5869 5870 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5871 struct switchdev_brport_flags flags, 5872 struct netlink_ext_ack *extack) 5873 { 5874 struct mv88e6xxx_chip *chip = ds->priv; 5875 const struct mv88e6xxx_ops *ops; 5876 5877 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5878 BR_BCAST_FLOOD)) 5879 return -EINVAL; 5880 5881 ops = chip->info->ops; 5882 5883 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5884 return -EINVAL; 5885 5886 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5887 return -EINVAL; 5888 5889 return 0; 5890 } 5891 5892 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5893 struct switchdev_brport_flags flags, 5894 struct netlink_ext_ack *extack) 5895 { 5896 struct mv88e6xxx_chip *chip = ds->priv; 5897 int err = -EOPNOTSUPP; 5898 5899 mv88e6xxx_reg_lock(chip); 5900 5901 if (flags.mask & BR_LEARNING) { 5902 bool learning = !!(flags.val & BR_LEARNING); 5903 u16 pav = learning ? (1 << port) : 0; 5904 5905 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5906 if (err) 5907 goto out; 5908 } 5909 5910 if (flags.mask & BR_FLOOD) { 5911 bool unicast = !!(flags.val & BR_FLOOD); 5912 5913 err = chip->info->ops->port_set_ucast_flood(chip, port, 5914 unicast); 5915 if (err) 5916 goto out; 5917 } 5918 5919 if (flags.mask & BR_MCAST_FLOOD) { 5920 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5921 5922 err = chip->info->ops->port_set_mcast_flood(chip, port, 5923 multicast); 5924 if (err) 5925 goto out; 5926 } 5927 5928 if (flags.mask & BR_BCAST_FLOOD) { 5929 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5930 5931 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5932 if (err) 5933 goto out; 5934 } 5935 5936 out: 5937 mv88e6xxx_reg_unlock(chip); 5938 5939 return err; 5940 } 5941 5942 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5943 struct net_device *lag, 5944 struct netdev_lag_upper_info *info) 5945 { 5946 struct mv88e6xxx_chip *chip = ds->priv; 5947 struct dsa_port *dp; 5948 int id, members = 0; 5949 5950 if (!mv88e6xxx_has_lag(chip)) 5951 return false; 5952 5953 id = dsa_lag_id(ds->dst, lag); 5954 if (id < 0 || id >= ds->num_lag_ids) 5955 return false; 5956 5957 dsa_lag_foreach_port(dp, ds->dst, lag) 5958 /* Includes the port joining the LAG */ 5959 members++; 5960 5961 if (members > 8) 5962 return false; 5963 5964 /* We could potentially relax this to include active 5965 * backup in the future. 5966 */ 5967 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5968 return false; 5969 5970 /* Ideally we would also validate that the hash type matches 5971 * the hardware. Alas, this is always set to unknown on team 5972 * interfaces. 5973 */ 5974 return true; 5975 } 5976 5977 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5978 { 5979 struct mv88e6xxx_chip *chip = ds->priv; 5980 struct dsa_port *dp; 5981 u16 map = 0; 5982 int id; 5983 5984 id = dsa_lag_id(ds->dst, lag); 5985 5986 /* Build the map of all ports to distribute flows destined for 5987 * this LAG. This can be either a local user port, or a DSA 5988 * port if the LAG port is on a remote chip. 5989 */ 5990 dsa_lag_foreach_port(dp, ds->dst, lag) 5991 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5992 5993 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5994 } 5995 5996 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5997 /* Row number corresponds to the number of active members in a 5998 * LAG. Each column states which of the eight hash buckets are 5999 * mapped to the column:th port in the LAG. 6000 * 6001 * Example: In a LAG with three active ports, the second port 6002 * ([2][1]) would be selected for traffic mapped to buckets 6003 * 3,4,5 (0x38). 6004 */ 6005 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6006 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6007 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6008 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6009 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6010 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6011 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6012 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6013 }; 6014 6015 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6016 int num_tx, int nth) 6017 { 6018 u8 active = 0; 6019 int i; 6020 6021 num_tx = num_tx <= 8 ? num_tx : 8; 6022 if (nth < num_tx) 6023 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6024 6025 for (i = 0; i < 8; i++) { 6026 if (BIT(i) & active) 6027 mask[i] |= BIT(port); 6028 } 6029 } 6030 6031 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6032 { 6033 struct mv88e6xxx_chip *chip = ds->priv; 6034 unsigned int id, num_tx; 6035 struct net_device *lag; 6036 struct dsa_port *dp; 6037 int i, err, nth; 6038 u16 mask[8]; 6039 u16 ivec; 6040 6041 /* Assume no port is a member of any LAG. */ 6042 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6043 6044 /* Disable all masks for ports that _are_ members of a LAG. */ 6045 list_for_each_entry(dp, &ds->dst->ports, list) { 6046 if (!dp->lag_dev || dp->ds != ds) 6047 continue; 6048 6049 ivec &= ~BIT(dp->index); 6050 } 6051 6052 for (i = 0; i < 8; i++) 6053 mask[i] = ivec; 6054 6055 /* Enable the correct subset of masks for all LAG ports that 6056 * are in the Tx set. 6057 */ 6058 dsa_lags_foreach_id(id, ds->dst) { 6059 lag = dsa_lag_dev(ds->dst, id); 6060 if (!lag) 6061 continue; 6062 6063 num_tx = 0; 6064 dsa_lag_foreach_port(dp, ds->dst, lag) { 6065 if (dp->lag_tx_enabled) 6066 num_tx++; 6067 } 6068 6069 if (!num_tx) 6070 continue; 6071 6072 nth = 0; 6073 dsa_lag_foreach_port(dp, ds->dst, lag) { 6074 if (!dp->lag_tx_enabled) 6075 continue; 6076 6077 if (dp->ds == ds) 6078 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6079 num_tx, nth); 6080 6081 nth++; 6082 } 6083 } 6084 6085 for (i = 0; i < 8; i++) { 6086 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6087 if (err) 6088 return err; 6089 } 6090 6091 return 0; 6092 } 6093 6094 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6095 struct net_device *lag) 6096 { 6097 int err; 6098 6099 err = mv88e6xxx_lag_sync_masks(ds); 6100 6101 if (!err) 6102 err = mv88e6xxx_lag_sync_map(ds, lag); 6103 6104 return err; 6105 } 6106 6107 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6108 { 6109 struct mv88e6xxx_chip *chip = ds->priv; 6110 int err; 6111 6112 mv88e6xxx_reg_lock(chip); 6113 err = mv88e6xxx_lag_sync_masks(ds); 6114 mv88e6xxx_reg_unlock(chip); 6115 return err; 6116 } 6117 6118 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6119 struct net_device *lag, 6120 struct netdev_lag_upper_info *info) 6121 { 6122 struct mv88e6xxx_chip *chip = ds->priv; 6123 int err, id; 6124 6125 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6126 return -EOPNOTSUPP; 6127 6128 id = dsa_lag_id(ds->dst, lag); 6129 6130 mv88e6xxx_reg_lock(chip); 6131 6132 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6133 if (err) 6134 goto err_unlock; 6135 6136 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6137 if (err) 6138 goto err_clear_trunk; 6139 6140 mv88e6xxx_reg_unlock(chip); 6141 return 0; 6142 6143 err_clear_trunk: 6144 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6145 err_unlock: 6146 mv88e6xxx_reg_unlock(chip); 6147 return err; 6148 } 6149 6150 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6151 struct net_device *lag) 6152 { 6153 struct mv88e6xxx_chip *chip = ds->priv; 6154 int err_sync, err_trunk; 6155 6156 mv88e6xxx_reg_lock(chip); 6157 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6158 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6159 mv88e6xxx_reg_unlock(chip); 6160 return err_sync ? : err_trunk; 6161 } 6162 6163 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6164 int port) 6165 { 6166 struct mv88e6xxx_chip *chip = ds->priv; 6167 int err; 6168 6169 mv88e6xxx_reg_lock(chip); 6170 err = mv88e6xxx_lag_sync_masks(ds); 6171 mv88e6xxx_reg_unlock(chip); 6172 return err; 6173 } 6174 6175 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6176 int port, struct net_device *lag, 6177 struct netdev_lag_upper_info *info) 6178 { 6179 struct mv88e6xxx_chip *chip = ds->priv; 6180 int err; 6181 6182 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6183 return -EOPNOTSUPP; 6184 6185 mv88e6xxx_reg_lock(chip); 6186 6187 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6188 if (err) 6189 goto unlock; 6190 6191 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6192 6193 unlock: 6194 mv88e6xxx_reg_unlock(chip); 6195 return err; 6196 } 6197 6198 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6199 int port, struct net_device *lag) 6200 { 6201 struct mv88e6xxx_chip *chip = ds->priv; 6202 int err_sync, err_pvt; 6203 6204 mv88e6xxx_reg_lock(chip); 6205 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6206 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6207 mv88e6xxx_reg_unlock(chip); 6208 return err_sync ? : err_pvt; 6209 } 6210 6211 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6212 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6213 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6214 .setup = mv88e6xxx_setup, 6215 .teardown = mv88e6xxx_teardown, 6216 .port_setup = mv88e6xxx_port_setup, 6217 .port_teardown = mv88e6xxx_port_teardown, 6218 .phylink_validate = mv88e6xxx_validate, 6219 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6220 .phylink_mac_config = mv88e6xxx_mac_config, 6221 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6222 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6223 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6224 .get_strings = mv88e6xxx_get_strings, 6225 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6226 .get_sset_count = mv88e6xxx_get_sset_count, 6227 .port_enable = mv88e6xxx_port_enable, 6228 .port_disable = mv88e6xxx_port_disable, 6229 .port_max_mtu = mv88e6xxx_get_max_mtu, 6230 .port_change_mtu = mv88e6xxx_change_mtu, 6231 .get_mac_eee = mv88e6xxx_get_mac_eee, 6232 .set_mac_eee = mv88e6xxx_set_mac_eee, 6233 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6234 .get_eeprom = mv88e6xxx_get_eeprom, 6235 .set_eeprom = mv88e6xxx_set_eeprom, 6236 .get_regs_len = mv88e6xxx_get_regs_len, 6237 .get_regs = mv88e6xxx_get_regs, 6238 .get_rxnfc = mv88e6xxx_get_rxnfc, 6239 .set_rxnfc = mv88e6xxx_set_rxnfc, 6240 .set_ageing_time = mv88e6xxx_set_ageing_time, 6241 .port_bridge_join = mv88e6xxx_port_bridge_join, 6242 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6243 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6244 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6245 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6246 .port_fast_age = mv88e6xxx_port_fast_age, 6247 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6248 .port_vlan_add = mv88e6xxx_port_vlan_add, 6249 .port_vlan_del = mv88e6xxx_port_vlan_del, 6250 .port_fdb_add = mv88e6xxx_port_fdb_add, 6251 .port_fdb_del = mv88e6xxx_port_fdb_del, 6252 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6253 .port_mdb_add = mv88e6xxx_port_mdb_add, 6254 .port_mdb_del = mv88e6xxx_port_mdb_del, 6255 .port_mirror_add = mv88e6xxx_port_mirror_add, 6256 .port_mirror_del = mv88e6xxx_port_mirror_del, 6257 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6258 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6259 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6260 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6261 .port_txtstamp = mv88e6xxx_port_txtstamp, 6262 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6263 .get_ts_info = mv88e6xxx_get_ts_info, 6264 .devlink_param_get = mv88e6xxx_devlink_param_get, 6265 .devlink_param_set = mv88e6xxx_devlink_param_set, 6266 .devlink_info_get = mv88e6xxx_devlink_info_get, 6267 .port_lag_change = mv88e6xxx_port_lag_change, 6268 .port_lag_join = mv88e6xxx_port_lag_join, 6269 .port_lag_leave = mv88e6xxx_port_lag_leave, 6270 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6271 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6272 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6273 }; 6274 6275 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6276 { 6277 struct device *dev = chip->dev; 6278 struct dsa_switch *ds; 6279 6280 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6281 if (!ds) 6282 return -ENOMEM; 6283 6284 ds->dev = dev; 6285 ds->num_ports = mv88e6xxx_num_ports(chip); 6286 ds->priv = chip; 6287 ds->dev = dev; 6288 ds->ops = &mv88e6xxx_switch_ops; 6289 ds->ageing_time_min = chip->info->age_time_coeff; 6290 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6291 6292 /* Some chips support up to 32, but that requires enabling the 6293 * 5-bit port mode, which we do not support. 640k^W16 ought to 6294 * be enough for anyone. 6295 */ 6296 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6297 6298 dev_set_drvdata(dev, ds); 6299 6300 return dsa_register_switch(ds); 6301 } 6302 6303 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6304 { 6305 dsa_unregister_switch(chip->ds); 6306 } 6307 6308 static const void *pdata_device_get_match_data(struct device *dev) 6309 { 6310 const struct of_device_id *matches = dev->driver->of_match_table; 6311 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6312 6313 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6314 matches++) { 6315 if (!strcmp(pdata->compatible, matches->compatible)) 6316 return matches->data; 6317 } 6318 return NULL; 6319 } 6320 6321 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6322 * would be lost after a power cycle so prevent it to be suspended. 6323 */ 6324 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6325 { 6326 return -EOPNOTSUPP; 6327 } 6328 6329 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6330 { 6331 return 0; 6332 } 6333 6334 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6335 6336 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6337 { 6338 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6339 const struct mv88e6xxx_info *compat_info = NULL; 6340 struct device *dev = &mdiodev->dev; 6341 struct device_node *np = dev->of_node; 6342 struct mv88e6xxx_chip *chip; 6343 int port; 6344 int err; 6345 6346 if (!np && !pdata) 6347 return -EINVAL; 6348 6349 if (np) 6350 compat_info = of_device_get_match_data(dev); 6351 6352 if (pdata) { 6353 compat_info = pdata_device_get_match_data(dev); 6354 6355 if (!pdata->netdev) 6356 return -EINVAL; 6357 6358 for (port = 0; port < DSA_MAX_PORTS; port++) { 6359 if (!(pdata->enabled_ports & (1 << port))) 6360 continue; 6361 if (strcmp(pdata->cd.port_names[port], "cpu")) 6362 continue; 6363 pdata->cd.netdev[port] = &pdata->netdev->dev; 6364 break; 6365 } 6366 } 6367 6368 if (!compat_info) 6369 return -EINVAL; 6370 6371 chip = mv88e6xxx_alloc_chip(dev); 6372 if (!chip) { 6373 err = -ENOMEM; 6374 goto out; 6375 } 6376 6377 chip->info = compat_info; 6378 6379 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6380 if (err) 6381 goto out; 6382 6383 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6384 if (IS_ERR(chip->reset)) { 6385 err = PTR_ERR(chip->reset); 6386 goto out; 6387 } 6388 if (chip->reset) 6389 usleep_range(1000, 2000); 6390 6391 err = mv88e6xxx_detect(chip); 6392 if (err) 6393 goto out; 6394 6395 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6396 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6397 else 6398 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6399 6400 mv88e6xxx_phy_init(chip); 6401 6402 if (chip->info->ops->get_eeprom) { 6403 if (np) 6404 of_property_read_u32(np, "eeprom-length", 6405 &chip->eeprom_len); 6406 else 6407 chip->eeprom_len = pdata->eeprom_len; 6408 } 6409 6410 mv88e6xxx_reg_lock(chip); 6411 err = mv88e6xxx_switch_reset(chip); 6412 mv88e6xxx_reg_unlock(chip); 6413 if (err) 6414 goto out; 6415 6416 if (np) { 6417 chip->irq = of_irq_get(np, 0); 6418 if (chip->irq == -EPROBE_DEFER) { 6419 err = chip->irq; 6420 goto out; 6421 } 6422 } 6423 6424 if (pdata) 6425 chip->irq = pdata->irq; 6426 6427 /* Has to be performed before the MDIO bus is created, because 6428 * the PHYs will link their interrupts to these interrupt 6429 * controllers 6430 */ 6431 mv88e6xxx_reg_lock(chip); 6432 if (chip->irq > 0) 6433 err = mv88e6xxx_g1_irq_setup(chip); 6434 else 6435 err = mv88e6xxx_irq_poll_setup(chip); 6436 mv88e6xxx_reg_unlock(chip); 6437 6438 if (err) 6439 goto out; 6440 6441 if (chip->info->g2_irqs > 0) { 6442 err = mv88e6xxx_g2_irq_setup(chip); 6443 if (err) 6444 goto out_g1_irq; 6445 } 6446 6447 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6448 if (err) 6449 goto out_g2_irq; 6450 6451 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6452 if (err) 6453 goto out_g1_atu_prob_irq; 6454 6455 err = mv88e6xxx_mdios_register(chip, np); 6456 if (err) 6457 goto out_g1_vtu_prob_irq; 6458 6459 err = mv88e6xxx_register_switch(chip); 6460 if (err) 6461 goto out_mdio; 6462 6463 return 0; 6464 6465 out_mdio: 6466 mv88e6xxx_mdios_unregister(chip); 6467 out_g1_vtu_prob_irq: 6468 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6469 out_g1_atu_prob_irq: 6470 mv88e6xxx_g1_atu_prob_irq_free(chip); 6471 out_g2_irq: 6472 if (chip->info->g2_irqs > 0) 6473 mv88e6xxx_g2_irq_free(chip); 6474 out_g1_irq: 6475 if (chip->irq > 0) 6476 mv88e6xxx_g1_irq_free(chip); 6477 else 6478 mv88e6xxx_irq_poll_free(chip); 6479 out: 6480 if (pdata) 6481 dev_put(pdata->netdev); 6482 6483 return err; 6484 } 6485 6486 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6487 { 6488 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6489 struct mv88e6xxx_chip *chip; 6490 6491 if (!ds) 6492 return; 6493 6494 chip = ds->priv; 6495 6496 if (chip->info->ptp_support) { 6497 mv88e6xxx_hwtstamp_free(chip); 6498 mv88e6xxx_ptp_free(chip); 6499 } 6500 6501 mv88e6xxx_phy_destroy(chip); 6502 mv88e6xxx_unregister_switch(chip); 6503 mv88e6xxx_mdios_unregister(chip); 6504 6505 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6506 mv88e6xxx_g1_atu_prob_irq_free(chip); 6507 6508 if (chip->info->g2_irqs > 0) 6509 mv88e6xxx_g2_irq_free(chip); 6510 6511 if (chip->irq > 0) 6512 mv88e6xxx_g1_irq_free(chip); 6513 else 6514 mv88e6xxx_irq_poll_free(chip); 6515 6516 dev_set_drvdata(&mdiodev->dev, NULL); 6517 } 6518 6519 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6520 { 6521 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6522 6523 if (!ds) 6524 return; 6525 6526 dsa_switch_shutdown(ds); 6527 6528 dev_set_drvdata(&mdiodev->dev, NULL); 6529 } 6530 6531 static const struct of_device_id mv88e6xxx_of_match[] = { 6532 { 6533 .compatible = "marvell,mv88e6085", 6534 .data = &mv88e6xxx_table[MV88E6085], 6535 }, 6536 { 6537 .compatible = "marvell,mv88e6190", 6538 .data = &mv88e6xxx_table[MV88E6190], 6539 }, 6540 { 6541 .compatible = "marvell,mv88e6250", 6542 .data = &mv88e6xxx_table[MV88E6250], 6543 }, 6544 { /* sentinel */ }, 6545 }; 6546 6547 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6548 6549 static struct mdio_driver mv88e6xxx_driver = { 6550 .probe = mv88e6xxx_probe, 6551 .remove = mv88e6xxx_remove, 6552 .shutdown = mv88e6xxx_shutdown, 6553 .mdiodrv.driver = { 6554 .name = "mv88e6085", 6555 .of_match_table = mv88e6xxx_of_match, 6556 .pm = &mv88e6xxx_pm_ops, 6557 }, 6558 }; 6559 6560 mdio_module_driver(mv88e6xxx_driver); 6561 6562 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6563 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6564 MODULE_LICENSE("GPL"); 6565