1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 475 if (err) { 476 dev_err(chip->dev, 477 "p%d: %s: failed to read port status\n", 478 port, __func__); 479 return err; 480 } 481 482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 483 } 484 485 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 486 struct phylink_link_state *state) 487 { 488 struct mv88e6xxx_chip *chip = ds->priv; 489 int lane; 490 int err; 491 492 mv88e6xxx_reg_lock(chip); 493 lane = mv88e6xxx_serdes_get_lane(chip, port); 494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 496 state); 497 else 498 err = -EOPNOTSUPP; 499 mv88e6xxx_reg_unlock(chip); 500 501 return err; 502 } 503 504 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 505 unsigned int mode, 506 phy_interface_t interface, 507 const unsigned long *advertise) 508 { 509 const struct mv88e6xxx_ops *ops = chip->info->ops; 510 int lane; 511 512 if (ops->serdes_pcs_config) { 513 lane = mv88e6xxx_serdes_get_lane(chip, port); 514 if (lane >= 0) 515 return ops->serdes_pcs_config(chip, port, lane, mode, 516 interface, advertise); 517 } 518 519 return 0; 520 } 521 522 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 523 { 524 struct mv88e6xxx_chip *chip = ds->priv; 525 const struct mv88e6xxx_ops *ops; 526 int err = 0; 527 int lane; 528 529 ops = chip->info->ops; 530 531 if (ops->serdes_pcs_an_restart) { 532 mv88e6xxx_reg_lock(chip); 533 lane = mv88e6xxx_serdes_get_lane(chip, port); 534 if (lane >= 0) 535 err = ops->serdes_pcs_an_restart(chip, port, lane); 536 mv88e6xxx_reg_unlock(chip); 537 538 if (err) 539 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 540 } 541 } 542 543 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 544 unsigned int mode, 545 int speed, int duplex) 546 { 547 const struct mv88e6xxx_ops *ops = chip->info->ops; 548 int lane; 549 550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 551 lane = mv88e6xxx_serdes_get_lane(chip, port); 552 if (lane >= 0) 553 return ops->serdes_pcs_link_up(chip, port, lane, 554 speed, duplex); 555 } 556 557 return 0; 558 } 559 560 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 561 unsigned long *mask, 562 struct phylink_link_state *state) 563 { 564 if (!phy_interface_mode_is_8023z(state->interface)) { 565 /* 10M and 100M are only supported in non-802.3z mode */ 566 phylink_set(mask, 10baseT_Half); 567 phylink_set(mask, 10baseT_Full); 568 phylink_set(mask, 100baseT_Half); 569 phylink_set(mask, 100baseT_Full); 570 } 571 } 572 573 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 574 unsigned long *mask, 575 struct phylink_link_state *state) 576 { 577 /* FIXME: if the port is in 1000Base-X mode, then it only supports 578 * 1000M FD speeds. In this case, CMODE will indicate 5. 579 */ 580 phylink_set(mask, 1000baseT_Full); 581 phylink_set(mask, 1000baseX_Full); 582 583 mv88e6065_phylink_validate(chip, port, mask, state); 584 } 585 586 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 587 unsigned long *mask, 588 struct phylink_link_state *state) 589 { 590 if (port >= 5) 591 phylink_set(mask, 2500baseX_Full); 592 593 /* No ethtool bits for 200Mbps */ 594 phylink_set(mask, 1000baseT_Full); 595 phylink_set(mask, 1000baseX_Full); 596 597 mv88e6065_phylink_validate(chip, port, mask, state); 598 } 599 600 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 601 unsigned long *mask, 602 struct phylink_link_state *state) 603 { 604 /* No ethtool bits for 200Mbps */ 605 phylink_set(mask, 1000baseT_Full); 606 phylink_set(mask, 1000baseX_Full); 607 608 mv88e6065_phylink_validate(chip, port, mask, state); 609 } 610 611 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 612 unsigned long *mask, 613 struct phylink_link_state *state) 614 { 615 if (port >= 9) { 616 phylink_set(mask, 2500baseX_Full); 617 phylink_set(mask, 2500baseT_Full); 618 } 619 620 /* No ethtool bits for 200Mbps */ 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseX_Full); 623 624 mv88e6065_phylink_validate(chip, port, mask, state); 625 } 626 627 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 628 unsigned long *mask, 629 struct phylink_link_state *state) 630 { 631 if (port >= 9) { 632 phylink_set(mask, 10000baseT_Full); 633 phylink_set(mask, 10000baseKR_Full); 634 } 635 636 mv88e6390_phylink_validate(chip, port, mask, state); 637 } 638 639 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 640 unsigned long *mask, 641 struct phylink_link_state *state) 642 { 643 bool is_6191x = 644 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 645 646 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 647 phylink_set(mask, 10000baseT_Full); 648 phylink_set(mask, 10000baseKR_Full); 649 phylink_set(mask, 10000baseCR_Full); 650 phylink_set(mask, 10000baseSR_Full); 651 phylink_set(mask, 10000baseLR_Full); 652 phylink_set(mask, 10000baseLRM_Full); 653 phylink_set(mask, 10000baseER_Full); 654 phylink_set(mask, 5000baseT_Full); 655 phylink_set(mask, 2500baseX_Full); 656 phylink_set(mask, 2500baseT_Full); 657 } 658 659 phylink_set(mask, 1000baseT_Full); 660 phylink_set(mask, 1000baseX_Full); 661 662 mv88e6065_phylink_validate(chip, port, mask, state); 663 } 664 665 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 666 unsigned long *supported, 667 struct phylink_link_state *state) 668 { 669 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 670 struct mv88e6xxx_chip *chip = ds->priv; 671 672 /* Allow all the expected bits */ 673 phylink_set(mask, Autoneg); 674 phylink_set(mask, Pause); 675 phylink_set_port_modes(mask); 676 677 if (chip->info->ops->phylink_validate) 678 chip->info->ops->phylink_validate(chip, port, mask, state); 679 680 linkmode_and(supported, supported, mask); 681 linkmode_and(state->advertising, state->advertising, mask); 682 683 /* We can only operate at 2500BaseX or 1000BaseX. If requested 684 * to advertise both, only report advertising at 2500BaseX. 685 */ 686 phylink_helper_basex_speed(state); 687 } 688 689 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 690 unsigned int mode, 691 const struct phylink_link_state *state) 692 { 693 struct mv88e6xxx_chip *chip = ds->priv; 694 struct mv88e6xxx_port *p; 695 int err; 696 697 p = &chip->ports[port]; 698 699 /* FIXME: is this the correct test? If we're in fixed mode on an 700 * internal port, why should we process this any different from 701 * PHY mode? On the other hand, the port may be automedia between 702 * an internal PHY and the serdes... 703 */ 704 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 705 return; 706 707 mv88e6xxx_reg_lock(chip); 708 /* In inband mode, the link may come up at any time while the link 709 * is not forced down. Force the link down while we reconfigure the 710 * interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && p->interface != state->interface && 713 chip->info->ops->port_set_link) 714 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 715 716 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 717 if (err && err != -EOPNOTSUPP) 718 goto err_unlock; 719 720 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 721 state->advertising); 722 /* FIXME: we should restart negotiation if something changed - which 723 * is something we get if we convert to using phylinks PCS operations. 724 */ 725 if (err > 0) 726 err = 0; 727 728 /* Undo the forced down state above after completing configuration 729 * irrespective of its state on entry, which allows the link to come up. 730 */ 731 if (mode == MLO_AN_INBAND && p->interface != state->interface && 732 chip->info->ops->port_set_link) 733 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 734 735 p->interface = state->interface; 736 737 err_unlock: 738 mv88e6xxx_reg_unlock(chip); 739 740 if (err && err != -EOPNOTSUPP) 741 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 742 } 743 744 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 745 unsigned int mode, 746 phy_interface_t interface) 747 { 748 struct mv88e6xxx_chip *chip = ds->priv; 749 const struct mv88e6xxx_ops *ops; 750 int err = 0; 751 752 ops = chip->info->ops; 753 754 mv88e6xxx_reg_lock(chip); 755 /* Internal PHYs propagate their configuration directly to the MAC. 756 * External PHYs depend on whether the PPU is enabled for this port. 757 */ 758 if (((!mv88e6xxx_phy_is_internal(ds, port) && 759 !mv88e6xxx_port_ppu_updates(chip, port)) || 760 mode == MLO_AN_FIXED) && ops->port_sync_link) 761 err = ops->port_sync_link(chip, port, mode, false); 762 mv88e6xxx_reg_unlock(chip); 763 764 if (err) 765 dev_err(chip->dev, 766 "p%d: failed to force MAC link down\n", port); 767 } 768 769 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 770 unsigned int mode, phy_interface_t interface, 771 struct phy_device *phydev, 772 int speed, int duplex, 773 bool tx_pause, bool rx_pause) 774 { 775 struct mv88e6xxx_chip *chip = ds->priv; 776 const struct mv88e6xxx_ops *ops; 777 int err = 0; 778 779 ops = chip->info->ops; 780 781 mv88e6xxx_reg_lock(chip); 782 /* Internal PHYs propagate their configuration directly to the MAC. 783 * External PHYs depend on whether the PPU is enabled for this port. 784 */ 785 if ((!mv88e6xxx_phy_is_internal(ds, port) && 786 !mv88e6xxx_port_ppu_updates(chip, port)) || 787 mode == MLO_AN_FIXED) { 788 /* FIXME: for an automedia port, should we force the link 789 * down here - what if the link comes up due to "other" media 790 * while we're bringing the port up, how is the exclusivity 791 * handled in the Marvell hardware? E.g. port 2 on 88E6390 792 * shared between internal PHY and Serdes. 793 */ 794 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 795 duplex); 796 if (err) 797 goto error; 798 799 if (ops->port_set_speed_duplex) { 800 err = ops->port_set_speed_duplex(chip, port, 801 speed, duplex); 802 if (err && err != -EOPNOTSUPP) 803 goto error; 804 } 805 806 if (ops->port_sync_link) 807 err = ops->port_sync_link(chip, port, mode, true); 808 } 809 error: 810 mv88e6xxx_reg_unlock(chip); 811 812 if (err && err != -EOPNOTSUPP) 813 dev_err(ds->dev, 814 "p%d: failed to configure MAC link up\n", port); 815 } 816 817 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 818 { 819 if (!chip->info->ops->stats_snapshot) 820 return -EOPNOTSUPP; 821 822 return chip->info->ops->stats_snapshot(chip, port); 823 } 824 825 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 826 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 827 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 828 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 829 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 830 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 831 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 832 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 833 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 834 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 835 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 836 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 837 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 838 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 839 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 840 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 841 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 842 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 843 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 844 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 845 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 846 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 847 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 848 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 849 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 850 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 851 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 852 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 853 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 854 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 855 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 856 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 857 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 858 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 859 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 860 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 861 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 862 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 863 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 864 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 865 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 866 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 867 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 868 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 869 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 870 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 871 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 872 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 873 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 874 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 875 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 876 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 877 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 878 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 879 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 880 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 881 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 882 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 883 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 884 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 885 }; 886 887 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 888 struct mv88e6xxx_hw_stat *s, 889 int port, u16 bank1_select, 890 u16 histogram) 891 { 892 u32 low; 893 u32 high = 0; 894 u16 reg = 0; 895 int err; 896 u64 value; 897 898 switch (s->type) { 899 case STATS_TYPE_PORT: 900 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 901 if (err) 902 return U64_MAX; 903 904 low = reg; 905 if (s->size == 4) { 906 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 907 if (err) 908 return U64_MAX; 909 low |= ((u32)reg) << 16; 910 } 911 break; 912 case STATS_TYPE_BANK1: 913 reg = bank1_select; 914 fallthrough; 915 case STATS_TYPE_BANK0: 916 reg |= s->reg | histogram; 917 mv88e6xxx_g1_stats_read(chip, reg, &low); 918 if (s->size == 8) 919 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 920 break; 921 default: 922 return U64_MAX; 923 } 924 value = (((u64)high) << 32) | low; 925 return value; 926 } 927 928 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 929 uint8_t *data, int types) 930 { 931 struct mv88e6xxx_hw_stat *stat; 932 int i, j; 933 934 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 935 stat = &mv88e6xxx_hw_stats[i]; 936 if (stat->type & types) { 937 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 938 ETH_GSTRING_LEN); 939 j++; 940 } 941 } 942 943 return j; 944 } 945 946 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 947 uint8_t *data) 948 { 949 return mv88e6xxx_stats_get_strings(chip, data, 950 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 951 } 952 953 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 954 uint8_t *data) 955 { 956 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 957 } 958 959 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 960 uint8_t *data) 961 { 962 return mv88e6xxx_stats_get_strings(chip, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 964 } 965 966 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 967 "atu_member_violation", 968 "atu_miss_violation", 969 "atu_full_violation", 970 "vtu_member_violation", 971 "vtu_miss_violation", 972 }; 973 974 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 975 { 976 unsigned int i; 977 978 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 979 strlcpy(data + i * ETH_GSTRING_LEN, 980 mv88e6xxx_atu_vtu_stats_strings[i], 981 ETH_GSTRING_LEN); 982 } 983 984 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 985 u32 stringset, uint8_t *data) 986 { 987 struct mv88e6xxx_chip *chip = ds->priv; 988 int count = 0; 989 990 if (stringset != ETH_SS_STATS) 991 return; 992 993 mv88e6xxx_reg_lock(chip); 994 995 if (chip->info->ops->stats_get_strings) 996 count = chip->info->ops->stats_get_strings(chip, data); 997 998 if (chip->info->ops->serdes_get_strings) { 999 data += count * ETH_GSTRING_LEN; 1000 count = chip->info->ops->serdes_get_strings(chip, port, data); 1001 } 1002 1003 data += count * ETH_GSTRING_LEN; 1004 mv88e6xxx_atu_vtu_get_strings(data); 1005 1006 mv88e6xxx_reg_unlock(chip); 1007 } 1008 1009 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1010 int types) 1011 { 1012 struct mv88e6xxx_hw_stat *stat; 1013 int i, j; 1014 1015 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1016 stat = &mv88e6xxx_hw_stats[i]; 1017 if (stat->type & types) 1018 j++; 1019 } 1020 return j; 1021 } 1022 1023 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1024 { 1025 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1026 STATS_TYPE_PORT); 1027 } 1028 1029 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1030 { 1031 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1032 } 1033 1034 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1035 { 1036 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1037 STATS_TYPE_BANK1); 1038 } 1039 1040 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1041 { 1042 struct mv88e6xxx_chip *chip = ds->priv; 1043 int serdes_count = 0; 1044 int count = 0; 1045 1046 if (sset != ETH_SS_STATS) 1047 return 0; 1048 1049 mv88e6xxx_reg_lock(chip); 1050 if (chip->info->ops->stats_get_sset_count) 1051 count = chip->info->ops->stats_get_sset_count(chip); 1052 if (count < 0) 1053 goto out; 1054 1055 if (chip->info->ops->serdes_get_sset_count) 1056 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1057 port); 1058 if (serdes_count < 0) { 1059 count = serdes_count; 1060 goto out; 1061 } 1062 count += serdes_count; 1063 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1064 1065 out: 1066 mv88e6xxx_reg_unlock(chip); 1067 1068 return count; 1069 } 1070 1071 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1072 uint64_t *data, int types, 1073 u16 bank1_select, u16 histogram) 1074 { 1075 struct mv88e6xxx_hw_stat *stat; 1076 int i, j; 1077 1078 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1079 stat = &mv88e6xxx_hw_stats[i]; 1080 if (stat->type & types) { 1081 mv88e6xxx_reg_lock(chip); 1082 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1083 bank1_select, 1084 histogram); 1085 mv88e6xxx_reg_unlock(chip); 1086 1087 j++; 1088 } 1089 } 1090 return j; 1091 } 1092 1093 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1094 uint64_t *data) 1095 { 1096 return mv88e6xxx_stats_get_stats(chip, port, data, 1097 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1098 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1099 } 1100 1101 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1105 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1106 } 1107 1108 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1109 uint64_t *data) 1110 { 1111 return mv88e6xxx_stats_get_stats(chip, port, data, 1112 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1113 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1114 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1115 } 1116 1117 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1118 uint64_t *data) 1119 { 1120 return mv88e6xxx_stats_get_stats(chip, port, data, 1121 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1122 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1123 0); 1124 } 1125 1126 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1127 uint64_t *data) 1128 { 1129 *data++ = chip->ports[port].atu_member_violation; 1130 *data++ = chip->ports[port].atu_miss_violation; 1131 *data++ = chip->ports[port].atu_full_violation; 1132 *data++ = chip->ports[port].vtu_member_violation; 1133 *data++ = chip->ports[port].vtu_miss_violation; 1134 } 1135 1136 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1137 uint64_t *data) 1138 { 1139 int count = 0; 1140 1141 if (chip->info->ops->stats_get_stats) 1142 count = chip->info->ops->stats_get_stats(chip, port, data); 1143 1144 mv88e6xxx_reg_lock(chip); 1145 if (chip->info->ops->serdes_get_stats) { 1146 data += count; 1147 count = chip->info->ops->serdes_get_stats(chip, port, data); 1148 } 1149 data += count; 1150 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1151 mv88e6xxx_reg_unlock(chip); 1152 } 1153 1154 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1155 uint64_t *data) 1156 { 1157 struct mv88e6xxx_chip *chip = ds->priv; 1158 int ret; 1159 1160 mv88e6xxx_reg_lock(chip); 1161 1162 ret = mv88e6xxx_stats_snapshot(chip, port); 1163 mv88e6xxx_reg_unlock(chip); 1164 1165 if (ret < 0) 1166 return; 1167 1168 mv88e6xxx_get_stats(chip, port, data); 1169 1170 } 1171 1172 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1173 { 1174 struct mv88e6xxx_chip *chip = ds->priv; 1175 int len; 1176 1177 len = 32 * sizeof(u16); 1178 if (chip->info->ops->serdes_get_regs_len) 1179 len += chip->info->ops->serdes_get_regs_len(chip, port); 1180 1181 return len; 1182 } 1183 1184 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1185 struct ethtool_regs *regs, void *_p) 1186 { 1187 struct mv88e6xxx_chip *chip = ds->priv; 1188 int err; 1189 u16 reg; 1190 u16 *p = _p; 1191 int i; 1192 1193 regs->version = chip->info->prod_num; 1194 1195 memset(p, 0xff, 32 * sizeof(u16)); 1196 1197 mv88e6xxx_reg_lock(chip); 1198 1199 for (i = 0; i < 32; i++) { 1200 1201 err = mv88e6xxx_port_read(chip, port, i, ®); 1202 if (!err) 1203 p[i] = reg; 1204 } 1205 1206 if (chip->info->ops->serdes_get_regs) 1207 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1208 1209 mv88e6xxx_reg_unlock(chip); 1210 } 1211 1212 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1213 struct ethtool_eee *e) 1214 { 1215 /* Nothing to do on the port's MAC */ 1216 return 0; 1217 } 1218 1219 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1220 struct ethtool_eee *e) 1221 { 1222 /* Nothing to do on the port's MAC */ 1223 return 0; 1224 } 1225 1226 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1227 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1228 { 1229 struct dsa_switch *ds = chip->ds; 1230 struct dsa_switch_tree *dst = ds->dst; 1231 struct dsa_port *dp, *other_dp; 1232 bool found = false; 1233 u16 pvlan; 1234 1235 /* dev is a physical switch */ 1236 if (dev <= dst->last_switch) { 1237 list_for_each_entry(dp, &dst->ports, list) { 1238 if (dp->ds->index == dev && dp->index == port) { 1239 /* dp might be a DSA link or a user port, so it 1240 * might or might not have a bridge. 1241 * Use the "found" variable for both cases. 1242 */ 1243 found = true; 1244 break; 1245 } 1246 } 1247 /* dev is a virtual bridge */ 1248 } else { 1249 list_for_each_entry(dp, &dst->ports, list) { 1250 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1251 1252 if (!bridge_num) 1253 continue; 1254 1255 if (bridge_num + dst->last_switch != dev) 1256 continue; 1257 1258 found = true; 1259 break; 1260 } 1261 } 1262 1263 /* Prevent frames from unknown switch or virtual bridge */ 1264 if (!found) 1265 return 0; 1266 1267 /* Frames from DSA links and CPU ports can egress any local port */ 1268 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1269 return mv88e6xxx_port_mask(chip); 1270 1271 pvlan = 0; 1272 1273 /* Frames from user ports can egress any local DSA links and CPU ports, 1274 * as well as any local member of their bridge group. 1275 */ 1276 dsa_switch_for_each_port(other_dp, ds) 1277 if (other_dp->type == DSA_PORT_TYPE_CPU || 1278 other_dp->type == DSA_PORT_TYPE_DSA || 1279 dsa_port_bridge_same(dp, other_dp)) 1280 pvlan |= BIT(other_dp->index); 1281 1282 return pvlan; 1283 } 1284 1285 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1286 { 1287 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1288 1289 /* prevent frames from going back out of the port they came in on */ 1290 output_ports &= ~BIT(port); 1291 1292 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1293 } 1294 1295 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1296 u8 state) 1297 { 1298 struct mv88e6xxx_chip *chip = ds->priv; 1299 int err; 1300 1301 mv88e6xxx_reg_lock(chip); 1302 err = mv88e6xxx_port_set_state(chip, port, state); 1303 mv88e6xxx_reg_unlock(chip); 1304 1305 if (err) 1306 dev_err(ds->dev, "p%d: failed to update state\n", port); 1307 } 1308 1309 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 int err; 1312 1313 if (chip->info->ops->ieee_pri_map) { 1314 err = chip->info->ops->ieee_pri_map(chip); 1315 if (err) 1316 return err; 1317 } 1318 1319 if (chip->info->ops->ip_pri_map) { 1320 err = chip->info->ops->ip_pri_map(chip); 1321 if (err) 1322 return err; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1329 { 1330 struct dsa_switch *ds = chip->ds; 1331 int target, port; 1332 int err; 1333 1334 if (!chip->info->global2_addr) 1335 return 0; 1336 1337 /* Initialize the routing port to the 32 possible target devices */ 1338 for (target = 0; target < 32; target++) { 1339 port = dsa_routing_port(ds, target); 1340 if (port == ds->num_ports) 1341 port = 0x1f; 1342 1343 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1344 if (err) 1345 return err; 1346 } 1347 1348 if (chip->info->ops->set_cascade_port) { 1349 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1350 err = chip->info->ops->set_cascade_port(chip, port); 1351 if (err) 1352 return err; 1353 } 1354 1355 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1356 if (err) 1357 return err; 1358 1359 return 0; 1360 } 1361 1362 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1363 { 1364 /* Clear all trunk masks and mapping */ 1365 if (chip->info->global2_addr) 1366 return mv88e6xxx_g2_trunk_clear(chip); 1367 1368 return 0; 1369 } 1370 1371 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1372 { 1373 if (chip->info->ops->rmu_disable) 1374 return chip->info->ops->rmu_disable(chip); 1375 1376 return 0; 1377 } 1378 1379 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1380 { 1381 if (chip->info->ops->pot_clear) 1382 return chip->info->ops->pot_clear(chip); 1383 1384 return 0; 1385 } 1386 1387 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 if (chip->info->ops->mgmt_rsvd2cpu) 1390 return chip->info->ops->mgmt_rsvd2cpu(chip); 1391 1392 return 0; 1393 } 1394 1395 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1396 { 1397 int err; 1398 1399 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1400 if (err) 1401 return err; 1402 1403 /* The chips that have a "learn2all" bit in Global1, ATU 1404 * Control are precisely those whose port registers have a 1405 * Message Port bit in Port Control 1 and hence implement 1406 * ->port_setup_message_port. 1407 */ 1408 if (chip->info->ops->port_setup_message_port) { 1409 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1410 if (err) 1411 return err; 1412 } 1413 1414 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1415 } 1416 1417 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1418 { 1419 int port; 1420 int err; 1421 1422 if (!chip->info->ops->irl_init_all) 1423 return 0; 1424 1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1426 /* Disable ingress rate limiting by resetting all per port 1427 * ingress rate limit resources to their initial state. 1428 */ 1429 err = chip->info->ops->irl_init_all(chip, port); 1430 if (err) 1431 return err; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1438 { 1439 if (chip->info->ops->set_switch_mac) { 1440 u8 addr[ETH_ALEN]; 1441 1442 eth_random_addr(addr); 1443 1444 return chip->info->ops->set_switch_mac(chip, addr); 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1451 { 1452 struct dsa_switch_tree *dst = chip->ds->dst; 1453 struct dsa_switch *ds; 1454 struct dsa_port *dp; 1455 u16 pvlan = 0; 1456 1457 if (!mv88e6xxx_has_pvt(chip)) 1458 return 0; 1459 1460 /* Skip the local source device, which uses in-chip port VLAN */ 1461 if (dev != chip->ds->index) { 1462 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1463 1464 ds = dsa_switch_find(dst->index, dev); 1465 dp = ds ? dsa_to_port(ds, port) : NULL; 1466 if (dp && dp->lag_dev) { 1467 /* As the PVT is used to limit flooding of 1468 * FORWARD frames, which use the LAG ID as the 1469 * source port, we must translate dev/port to 1470 * the special "LAG device" in the PVT, using 1471 * the LAG ID as the port number. 1472 */ 1473 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1474 port = dsa_lag_id(dst, dp->lag_dev); 1475 } 1476 } 1477 1478 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1479 } 1480 1481 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1482 { 1483 int dev, port; 1484 int err; 1485 1486 if (!mv88e6xxx_has_pvt(chip)) 1487 return 0; 1488 1489 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1490 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1491 */ 1492 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1493 if (err) 1494 return err; 1495 1496 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1497 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1498 err = mv88e6xxx_pvt_map(chip, dev, port); 1499 if (err) 1500 return err; 1501 } 1502 } 1503 1504 return 0; 1505 } 1506 1507 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1508 { 1509 struct mv88e6xxx_chip *chip = ds->priv; 1510 int err; 1511 1512 if (dsa_to_port(ds, port)->lag_dev) 1513 /* Hardware is incapable of fast-aging a LAG through a 1514 * regular ATU move operation. Until we have something 1515 * more fancy in place this is a no-op. 1516 */ 1517 return; 1518 1519 mv88e6xxx_reg_lock(chip); 1520 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1521 mv88e6xxx_reg_unlock(chip); 1522 1523 if (err) 1524 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1525 } 1526 1527 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1528 { 1529 if (!mv88e6xxx_max_vid(chip)) 1530 return 0; 1531 1532 return mv88e6xxx_g1_vtu_flush(chip); 1533 } 1534 1535 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1536 struct mv88e6xxx_vtu_entry *entry) 1537 { 1538 int err; 1539 1540 if (!chip->info->ops->vtu_getnext) 1541 return -EOPNOTSUPP; 1542 1543 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1544 entry->valid = false; 1545 1546 err = chip->info->ops->vtu_getnext(chip, entry); 1547 1548 if (entry->vid != vid) 1549 entry->valid = false; 1550 1551 return err; 1552 } 1553 1554 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1555 int (*cb)(struct mv88e6xxx_chip *chip, 1556 const struct mv88e6xxx_vtu_entry *entry, 1557 void *priv), 1558 void *priv) 1559 { 1560 struct mv88e6xxx_vtu_entry entry = { 1561 .vid = mv88e6xxx_max_vid(chip), 1562 .valid = false, 1563 }; 1564 int err; 1565 1566 if (!chip->info->ops->vtu_getnext) 1567 return -EOPNOTSUPP; 1568 1569 do { 1570 err = chip->info->ops->vtu_getnext(chip, &entry); 1571 if (err) 1572 return err; 1573 1574 if (!entry.valid) 1575 break; 1576 1577 err = cb(chip, &entry, priv); 1578 if (err) 1579 return err; 1580 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1581 1582 return 0; 1583 } 1584 1585 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1586 struct mv88e6xxx_vtu_entry *entry) 1587 { 1588 if (!chip->info->ops->vtu_loadpurge) 1589 return -EOPNOTSUPP; 1590 1591 return chip->info->ops->vtu_loadpurge(chip, entry); 1592 } 1593 1594 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1595 const struct mv88e6xxx_vtu_entry *entry, 1596 void *_fid_bitmap) 1597 { 1598 unsigned long *fid_bitmap = _fid_bitmap; 1599 1600 set_bit(entry->fid, fid_bitmap); 1601 return 0; 1602 } 1603 1604 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1605 { 1606 int i, err; 1607 u16 fid; 1608 1609 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1610 1611 /* Set every FID bit used by the (un)bridged ports */ 1612 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1613 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1614 if (err) 1615 return err; 1616 1617 set_bit(fid, fid_bitmap); 1618 } 1619 1620 /* Set every FID bit used by the VLAN entries */ 1621 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1622 } 1623 1624 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1625 { 1626 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1627 int err; 1628 1629 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1630 if (err) 1631 return err; 1632 1633 /* The reset value 0x000 is used to indicate that multiple address 1634 * databases are not needed. Return the next positive available. 1635 */ 1636 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1637 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1638 return -ENOSPC; 1639 1640 /* Clear the database */ 1641 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1642 } 1643 1644 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1645 u16 vid) 1646 { 1647 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1648 struct mv88e6xxx_chip *chip = ds->priv; 1649 struct mv88e6xxx_vtu_entry vlan; 1650 int err; 1651 1652 /* DSA and CPU ports have to be members of multiple vlans */ 1653 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1654 return 0; 1655 1656 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1657 if (err) 1658 return err; 1659 1660 if (!vlan.valid) 1661 return 0; 1662 1663 dsa_switch_for_each_user_port(other_dp, ds) { 1664 struct net_device *other_br; 1665 1666 if (vlan.member[other_dp->index] == 1667 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1668 continue; 1669 1670 if (dsa_port_bridge_same(dp, other_dp)) 1671 break; /* same bridge, check next VLAN */ 1672 1673 other_br = dsa_port_bridge_dev_get(other_dp); 1674 if (!other_br) 1675 continue; 1676 1677 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1678 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1679 return -EOPNOTSUPP; 1680 } 1681 1682 return 0; 1683 } 1684 1685 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1686 { 1687 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1688 struct net_device *br = dsa_port_bridge_dev_get(dp); 1689 struct mv88e6xxx_port *p = &chip->ports[port]; 1690 u16 pvid = MV88E6XXX_VID_STANDALONE; 1691 bool drop_untagged = false; 1692 int err; 1693 1694 if (br) { 1695 if (br_vlan_enabled(br)) { 1696 pvid = p->bridge_pvid.vid; 1697 drop_untagged = !p->bridge_pvid.valid; 1698 } else { 1699 pvid = MV88E6XXX_VID_BRIDGED; 1700 } 1701 } 1702 1703 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1704 if (err) 1705 return err; 1706 1707 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1708 } 1709 1710 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1711 bool vlan_filtering, 1712 struct netlink_ext_ack *extack) 1713 { 1714 struct mv88e6xxx_chip *chip = ds->priv; 1715 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1716 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1717 int err; 1718 1719 if (!mv88e6xxx_max_vid(chip)) 1720 return -EOPNOTSUPP; 1721 1722 mv88e6xxx_reg_lock(chip); 1723 1724 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1725 if (err) 1726 goto unlock; 1727 1728 err = mv88e6xxx_port_commit_pvid(chip, port); 1729 if (err) 1730 goto unlock; 1731 1732 unlock: 1733 mv88e6xxx_reg_unlock(chip); 1734 1735 return err; 1736 } 1737 1738 static int 1739 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1740 const struct switchdev_obj_port_vlan *vlan) 1741 { 1742 struct mv88e6xxx_chip *chip = ds->priv; 1743 int err; 1744 1745 if (!mv88e6xxx_max_vid(chip)) 1746 return -EOPNOTSUPP; 1747 1748 /* If the requested port doesn't belong to the same bridge as the VLAN 1749 * members, do not support it (yet) and fallback to software VLAN. 1750 */ 1751 mv88e6xxx_reg_lock(chip); 1752 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1753 mv88e6xxx_reg_unlock(chip); 1754 1755 return err; 1756 } 1757 1758 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1759 const unsigned char *addr, u16 vid, 1760 u8 state) 1761 { 1762 struct mv88e6xxx_atu_entry entry; 1763 struct mv88e6xxx_vtu_entry vlan; 1764 u16 fid; 1765 int err; 1766 1767 /* Ports have two private address databases: one for when the port is 1768 * standalone and one for when the port is under a bridge and the 1769 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1770 * address database to remain 100% empty, so we never load an ATU entry 1771 * into a standalone port's database. Therefore, translate the null 1772 * VLAN ID into the port's database used for VLAN-unaware bridging. 1773 */ 1774 if (vid == 0) { 1775 fid = MV88E6XXX_FID_BRIDGED; 1776 } else { 1777 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1778 if (err) 1779 return err; 1780 1781 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1782 if (!vlan.valid) 1783 return -EOPNOTSUPP; 1784 1785 fid = vlan.fid; 1786 } 1787 1788 entry.state = 0; 1789 ether_addr_copy(entry.mac, addr); 1790 eth_addr_dec(entry.mac); 1791 1792 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1793 if (err) 1794 return err; 1795 1796 /* Initialize a fresh ATU entry if it isn't found */ 1797 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1798 memset(&entry, 0, sizeof(entry)); 1799 ether_addr_copy(entry.mac, addr); 1800 } 1801 1802 /* Purge the ATU entry only if no port is using it anymore */ 1803 if (!state) { 1804 entry.portvec &= ~BIT(port); 1805 if (!entry.portvec) 1806 entry.state = 0; 1807 } else { 1808 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1809 entry.portvec = BIT(port); 1810 else 1811 entry.portvec |= BIT(port); 1812 1813 entry.state = state; 1814 } 1815 1816 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1817 } 1818 1819 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1820 const struct mv88e6xxx_policy *policy) 1821 { 1822 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1823 enum mv88e6xxx_policy_action action = policy->action; 1824 const u8 *addr = policy->addr; 1825 u16 vid = policy->vid; 1826 u8 state; 1827 int err; 1828 int id; 1829 1830 if (!chip->info->ops->port_set_policy) 1831 return -EOPNOTSUPP; 1832 1833 switch (mapping) { 1834 case MV88E6XXX_POLICY_MAPPING_DA: 1835 case MV88E6XXX_POLICY_MAPPING_SA: 1836 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1837 state = 0; /* Dissociate the port and address */ 1838 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1839 is_multicast_ether_addr(addr)) 1840 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1841 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1842 is_unicast_ether_addr(addr)) 1843 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1844 else 1845 return -EOPNOTSUPP; 1846 1847 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1848 state); 1849 if (err) 1850 return err; 1851 break; 1852 default: 1853 return -EOPNOTSUPP; 1854 } 1855 1856 /* Skip the port's policy clearing if the mapping is still in use */ 1857 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1858 idr_for_each_entry(&chip->policies, policy, id) 1859 if (policy->port == port && 1860 policy->mapping == mapping && 1861 policy->action != action) 1862 return 0; 1863 1864 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1865 } 1866 1867 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1868 struct ethtool_rx_flow_spec *fs) 1869 { 1870 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1871 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1872 enum mv88e6xxx_policy_mapping mapping; 1873 enum mv88e6xxx_policy_action action; 1874 struct mv88e6xxx_policy *policy; 1875 u16 vid = 0; 1876 u8 *addr; 1877 int err; 1878 int id; 1879 1880 if (fs->location != RX_CLS_LOC_ANY) 1881 return -EINVAL; 1882 1883 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1884 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1885 else 1886 return -EOPNOTSUPP; 1887 1888 switch (fs->flow_type & ~FLOW_EXT) { 1889 case ETHER_FLOW: 1890 if (!is_zero_ether_addr(mac_mask->h_dest) && 1891 is_zero_ether_addr(mac_mask->h_source)) { 1892 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1893 addr = mac_entry->h_dest; 1894 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1895 !is_zero_ether_addr(mac_mask->h_source)) { 1896 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1897 addr = mac_entry->h_source; 1898 } else { 1899 /* Cannot support DA and SA mapping in the same rule */ 1900 return -EOPNOTSUPP; 1901 } 1902 break; 1903 default: 1904 return -EOPNOTSUPP; 1905 } 1906 1907 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1908 if (fs->m_ext.vlan_tci != htons(0xffff)) 1909 return -EOPNOTSUPP; 1910 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1911 } 1912 1913 idr_for_each_entry(&chip->policies, policy, id) { 1914 if (policy->port == port && policy->mapping == mapping && 1915 policy->action == action && policy->vid == vid && 1916 ether_addr_equal(policy->addr, addr)) 1917 return -EEXIST; 1918 } 1919 1920 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1921 if (!policy) 1922 return -ENOMEM; 1923 1924 fs->location = 0; 1925 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1926 GFP_KERNEL); 1927 if (err) { 1928 devm_kfree(chip->dev, policy); 1929 return err; 1930 } 1931 1932 memcpy(&policy->fs, fs, sizeof(*fs)); 1933 ether_addr_copy(policy->addr, addr); 1934 policy->mapping = mapping; 1935 policy->action = action; 1936 policy->port = port; 1937 policy->vid = vid; 1938 1939 err = mv88e6xxx_policy_apply(chip, port, policy); 1940 if (err) { 1941 idr_remove(&chip->policies, fs->location); 1942 devm_kfree(chip->dev, policy); 1943 return err; 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1950 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1951 { 1952 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1953 struct mv88e6xxx_chip *chip = ds->priv; 1954 struct mv88e6xxx_policy *policy; 1955 int err; 1956 int id; 1957 1958 mv88e6xxx_reg_lock(chip); 1959 1960 switch (rxnfc->cmd) { 1961 case ETHTOOL_GRXCLSRLCNT: 1962 rxnfc->data = 0; 1963 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1964 rxnfc->rule_cnt = 0; 1965 idr_for_each_entry(&chip->policies, policy, id) 1966 if (policy->port == port) 1967 rxnfc->rule_cnt++; 1968 err = 0; 1969 break; 1970 case ETHTOOL_GRXCLSRULE: 1971 err = -ENOENT; 1972 policy = idr_find(&chip->policies, fs->location); 1973 if (policy) { 1974 memcpy(fs, &policy->fs, sizeof(*fs)); 1975 err = 0; 1976 } 1977 break; 1978 case ETHTOOL_GRXCLSRLALL: 1979 rxnfc->data = 0; 1980 rxnfc->rule_cnt = 0; 1981 idr_for_each_entry(&chip->policies, policy, id) 1982 if (policy->port == port) 1983 rule_locs[rxnfc->rule_cnt++] = id; 1984 err = 0; 1985 break; 1986 default: 1987 err = -EOPNOTSUPP; 1988 break; 1989 } 1990 1991 mv88e6xxx_reg_unlock(chip); 1992 1993 return err; 1994 } 1995 1996 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1997 struct ethtool_rxnfc *rxnfc) 1998 { 1999 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2000 struct mv88e6xxx_chip *chip = ds->priv; 2001 struct mv88e6xxx_policy *policy; 2002 int err; 2003 2004 mv88e6xxx_reg_lock(chip); 2005 2006 switch (rxnfc->cmd) { 2007 case ETHTOOL_SRXCLSRLINS: 2008 err = mv88e6xxx_policy_insert(chip, port, fs); 2009 break; 2010 case ETHTOOL_SRXCLSRLDEL: 2011 err = -ENOENT; 2012 policy = idr_remove(&chip->policies, fs->location); 2013 if (policy) { 2014 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2015 err = mv88e6xxx_policy_apply(chip, port, policy); 2016 devm_kfree(chip->dev, policy); 2017 } 2018 break; 2019 default: 2020 err = -EOPNOTSUPP; 2021 break; 2022 } 2023 2024 mv88e6xxx_reg_unlock(chip); 2025 2026 return err; 2027 } 2028 2029 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2030 u16 vid) 2031 { 2032 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2033 u8 broadcast[ETH_ALEN]; 2034 2035 eth_broadcast_addr(broadcast); 2036 2037 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2038 } 2039 2040 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2041 { 2042 int port; 2043 int err; 2044 2045 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2046 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2047 struct net_device *brport; 2048 2049 if (dsa_is_unused_port(chip->ds, port)) 2050 continue; 2051 2052 brport = dsa_port_to_bridge_port(dp); 2053 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2054 /* Skip bridged user ports where broadcast 2055 * flooding is disabled. 2056 */ 2057 continue; 2058 2059 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2060 if (err) 2061 return err; 2062 } 2063 2064 return 0; 2065 } 2066 2067 struct mv88e6xxx_port_broadcast_sync_ctx { 2068 int port; 2069 bool flood; 2070 }; 2071 2072 static int 2073 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2074 const struct mv88e6xxx_vtu_entry *vlan, 2075 void *_ctx) 2076 { 2077 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2078 u8 broadcast[ETH_ALEN]; 2079 u8 state; 2080 2081 if (ctx->flood) 2082 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2083 else 2084 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2085 2086 eth_broadcast_addr(broadcast); 2087 2088 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2089 vlan->vid, state); 2090 } 2091 2092 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2093 bool flood) 2094 { 2095 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2096 .port = port, 2097 .flood = flood, 2098 }; 2099 struct mv88e6xxx_vtu_entry vid0 = { 2100 .vid = 0, 2101 }; 2102 int err; 2103 2104 /* Update the port's private database... */ 2105 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2106 if (err) 2107 return err; 2108 2109 /* ...and the database for all VLANs. */ 2110 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2111 &ctx); 2112 } 2113 2114 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2115 u16 vid, u8 member, bool warn) 2116 { 2117 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2118 struct mv88e6xxx_vtu_entry vlan; 2119 int i, err; 2120 2121 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2122 if (err) 2123 return err; 2124 2125 if (!vlan.valid) { 2126 memset(&vlan, 0, sizeof(vlan)); 2127 2128 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2129 if (err) 2130 return err; 2131 2132 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2133 if (i == port) 2134 vlan.member[i] = member; 2135 else 2136 vlan.member[i] = non_member; 2137 2138 vlan.vid = vid; 2139 vlan.valid = true; 2140 2141 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2142 if (err) 2143 return err; 2144 2145 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2146 if (err) 2147 return err; 2148 } else if (vlan.member[port] != member) { 2149 vlan.member[port] = member; 2150 2151 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2152 if (err) 2153 return err; 2154 } else if (warn) { 2155 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2156 port, vid); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2163 const struct switchdev_obj_port_vlan *vlan, 2164 struct netlink_ext_ack *extack) 2165 { 2166 struct mv88e6xxx_chip *chip = ds->priv; 2167 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2168 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2169 struct mv88e6xxx_port *p = &chip->ports[port]; 2170 bool warn; 2171 u8 member; 2172 int err; 2173 2174 if (!vlan->vid) 2175 return 0; 2176 2177 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2178 if (err) 2179 return err; 2180 2181 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2182 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2183 else if (untagged) 2184 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2185 else 2186 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2187 2188 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2189 * and then the CPU port. Do not warn for duplicates for the CPU port. 2190 */ 2191 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2192 2193 mv88e6xxx_reg_lock(chip); 2194 2195 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2196 if (err) { 2197 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2198 vlan->vid, untagged ? 'u' : 't'); 2199 goto out; 2200 } 2201 2202 if (pvid) { 2203 p->bridge_pvid.vid = vlan->vid; 2204 p->bridge_pvid.valid = true; 2205 2206 err = mv88e6xxx_port_commit_pvid(chip, port); 2207 if (err) 2208 goto out; 2209 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2210 /* The old pvid was reinstalled as a non-pvid VLAN */ 2211 p->bridge_pvid.valid = false; 2212 2213 err = mv88e6xxx_port_commit_pvid(chip, port); 2214 if (err) 2215 goto out; 2216 } 2217 2218 out: 2219 mv88e6xxx_reg_unlock(chip); 2220 2221 return err; 2222 } 2223 2224 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2225 int port, u16 vid) 2226 { 2227 struct mv88e6xxx_vtu_entry vlan; 2228 int i, err; 2229 2230 if (!vid) 2231 return 0; 2232 2233 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2234 if (err) 2235 return err; 2236 2237 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2238 * tell switchdev that this VLAN is likely handled in software. 2239 */ 2240 if (!vlan.valid || 2241 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2242 return -EOPNOTSUPP; 2243 2244 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2245 2246 /* keep the VLAN unless all ports are excluded */ 2247 vlan.valid = false; 2248 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2249 if (vlan.member[i] != 2250 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2251 vlan.valid = true; 2252 break; 2253 } 2254 } 2255 2256 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2257 if (err) 2258 return err; 2259 2260 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2261 } 2262 2263 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2264 const struct switchdev_obj_port_vlan *vlan) 2265 { 2266 struct mv88e6xxx_chip *chip = ds->priv; 2267 struct mv88e6xxx_port *p = &chip->ports[port]; 2268 int err = 0; 2269 u16 pvid; 2270 2271 if (!mv88e6xxx_max_vid(chip)) 2272 return -EOPNOTSUPP; 2273 2274 mv88e6xxx_reg_lock(chip); 2275 2276 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2277 if (err) 2278 goto unlock; 2279 2280 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2281 if (err) 2282 goto unlock; 2283 2284 if (vlan->vid == pvid) { 2285 p->bridge_pvid.valid = false; 2286 2287 err = mv88e6xxx_port_commit_pvid(chip, port); 2288 if (err) 2289 goto unlock; 2290 } 2291 2292 unlock: 2293 mv88e6xxx_reg_unlock(chip); 2294 2295 return err; 2296 } 2297 2298 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2299 const unsigned char *addr, u16 vid) 2300 { 2301 struct mv88e6xxx_chip *chip = ds->priv; 2302 int err; 2303 2304 mv88e6xxx_reg_lock(chip); 2305 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2306 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2307 mv88e6xxx_reg_unlock(chip); 2308 2309 return err; 2310 } 2311 2312 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2313 const unsigned char *addr, u16 vid) 2314 { 2315 struct mv88e6xxx_chip *chip = ds->priv; 2316 int err; 2317 2318 mv88e6xxx_reg_lock(chip); 2319 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2320 mv88e6xxx_reg_unlock(chip); 2321 2322 return err; 2323 } 2324 2325 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2326 u16 fid, u16 vid, int port, 2327 dsa_fdb_dump_cb_t *cb, void *data) 2328 { 2329 struct mv88e6xxx_atu_entry addr; 2330 bool is_static; 2331 int err; 2332 2333 addr.state = 0; 2334 eth_broadcast_addr(addr.mac); 2335 2336 do { 2337 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2338 if (err) 2339 return err; 2340 2341 if (!addr.state) 2342 break; 2343 2344 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2345 continue; 2346 2347 if (!is_unicast_ether_addr(addr.mac)) 2348 continue; 2349 2350 is_static = (addr.state == 2351 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2352 err = cb(addr.mac, vid, is_static, data); 2353 if (err) 2354 return err; 2355 } while (!is_broadcast_ether_addr(addr.mac)); 2356 2357 return err; 2358 } 2359 2360 struct mv88e6xxx_port_db_dump_vlan_ctx { 2361 int port; 2362 dsa_fdb_dump_cb_t *cb; 2363 void *data; 2364 }; 2365 2366 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2367 const struct mv88e6xxx_vtu_entry *entry, 2368 void *_data) 2369 { 2370 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2371 2372 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2373 ctx->port, ctx->cb, ctx->data); 2374 } 2375 2376 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2377 dsa_fdb_dump_cb_t *cb, void *data) 2378 { 2379 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2380 .port = port, 2381 .cb = cb, 2382 .data = data, 2383 }; 2384 u16 fid; 2385 int err; 2386 2387 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2388 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2389 if (err) 2390 return err; 2391 2392 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2393 if (err) 2394 return err; 2395 2396 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2397 } 2398 2399 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2400 dsa_fdb_dump_cb_t *cb, void *data) 2401 { 2402 struct mv88e6xxx_chip *chip = ds->priv; 2403 int err; 2404 2405 mv88e6xxx_reg_lock(chip); 2406 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2407 mv88e6xxx_reg_unlock(chip); 2408 2409 return err; 2410 } 2411 2412 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2413 struct dsa_bridge bridge) 2414 { 2415 struct dsa_switch *ds = chip->ds; 2416 struct dsa_switch_tree *dst = ds->dst; 2417 struct dsa_port *dp; 2418 int err; 2419 2420 list_for_each_entry(dp, &dst->ports, list) { 2421 if (dsa_port_offloads_bridge(dp, &bridge)) { 2422 if (dp->ds == ds) { 2423 /* This is a local bridge group member, 2424 * remap its Port VLAN Map. 2425 */ 2426 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2427 if (err) 2428 return err; 2429 } else { 2430 /* This is an external bridge group member, 2431 * remap its cross-chip Port VLAN Table entry. 2432 */ 2433 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2434 dp->index); 2435 if (err) 2436 return err; 2437 } 2438 } 2439 } 2440 2441 return 0; 2442 } 2443 2444 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2445 struct dsa_bridge bridge, 2446 bool *tx_fwd_offload) 2447 { 2448 struct mv88e6xxx_chip *chip = ds->priv; 2449 int err; 2450 2451 mv88e6xxx_reg_lock(chip); 2452 2453 err = mv88e6xxx_bridge_map(chip, bridge); 2454 if (err) 2455 goto unlock; 2456 2457 err = mv88e6xxx_port_commit_pvid(chip, port); 2458 if (err) 2459 goto unlock; 2460 2461 unlock: 2462 mv88e6xxx_reg_unlock(chip); 2463 2464 return err; 2465 } 2466 2467 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2468 struct dsa_bridge bridge) 2469 { 2470 struct mv88e6xxx_chip *chip = ds->priv; 2471 int err; 2472 2473 mv88e6xxx_reg_lock(chip); 2474 2475 if (mv88e6xxx_bridge_map(chip, bridge) || 2476 mv88e6xxx_port_vlan_map(chip, port)) 2477 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2478 2479 err = mv88e6xxx_port_commit_pvid(chip, port); 2480 if (err) 2481 dev_err(ds->dev, 2482 "port %d failed to restore standalone pvid: %pe\n", 2483 port, ERR_PTR(err)); 2484 2485 mv88e6xxx_reg_unlock(chip); 2486 } 2487 2488 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2489 int tree_index, int sw_index, 2490 int port, struct dsa_bridge bridge) 2491 { 2492 struct mv88e6xxx_chip *chip = ds->priv; 2493 int err; 2494 2495 if (tree_index != ds->dst->index) 2496 return 0; 2497 2498 mv88e6xxx_reg_lock(chip); 2499 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2500 mv88e6xxx_reg_unlock(chip); 2501 2502 return err; 2503 } 2504 2505 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2506 int tree_index, int sw_index, 2507 int port, struct dsa_bridge bridge) 2508 { 2509 struct mv88e6xxx_chip *chip = ds->priv; 2510 2511 if (tree_index != ds->dst->index) 2512 return; 2513 2514 mv88e6xxx_reg_lock(chip); 2515 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2516 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2517 mv88e6xxx_reg_unlock(chip); 2518 } 2519 2520 /* Treat the software bridge as a virtual single-port switch behind the 2521 * CPU and map in the PVT. First dst->last_switch elements are taken by 2522 * physical switches, so start from beyond that range. 2523 */ 2524 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2525 unsigned int bridge_num) 2526 { 2527 u8 dev = bridge_num + ds->dst->last_switch; 2528 struct mv88e6xxx_chip *chip = ds->priv; 2529 int err; 2530 2531 mv88e6xxx_reg_lock(chip); 2532 err = mv88e6xxx_pvt_map(chip, dev, 0); 2533 mv88e6xxx_reg_unlock(chip); 2534 2535 return err; 2536 } 2537 2538 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2539 struct dsa_bridge bridge) 2540 { 2541 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2542 } 2543 2544 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2545 struct dsa_bridge bridge) 2546 { 2547 int err; 2548 2549 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2550 if (err) { 2551 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2552 ERR_PTR(err)); 2553 } 2554 } 2555 2556 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2557 { 2558 if (chip->info->ops->reset) 2559 return chip->info->ops->reset(chip); 2560 2561 return 0; 2562 } 2563 2564 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2565 { 2566 struct gpio_desc *gpiod = chip->reset; 2567 2568 /* If there is a GPIO connected to the reset pin, toggle it */ 2569 if (gpiod) { 2570 gpiod_set_value_cansleep(gpiod, 1); 2571 usleep_range(10000, 20000); 2572 gpiod_set_value_cansleep(gpiod, 0); 2573 usleep_range(10000, 20000); 2574 2575 mv88e6xxx_g1_wait_eeprom_done(chip); 2576 } 2577 } 2578 2579 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2580 { 2581 int i, err; 2582 2583 /* Set all ports to the Disabled state */ 2584 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2585 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2586 if (err) 2587 return err; 2588 } 2589 2590 /* Wait for transmit queues to drain, 2591 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2592 */ 2593 usleep_range(2000, 4000); 2594 2595 return 0; 2596 } 2597 2598 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2599 { 2600 int err; 2601 2602 err = mv88e6xxx_disable_ports(chip); 2603 if (err) 2604 return err; 2605 2606 mv88e6xxx_hardware_reset(chip); 2607 2608 return mv88e6xxx_software_reset(chip); 2609 } 2610 2611 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2612 enum mv88e6xxx_frame_mode frame, 2613 enum mv88e6xxx_egress_mode egress, u16 etype) 2614 { 2615 int err; 2616 2617 if (!chip->info->ops->port_set_frame_mode) 2618 return -EOPNOTSUPP; 2619 2620 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2621 if (err) 2622 return err; 2623 2624 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2625 if (err) 2626 return err; 2627 2628 if (chip->info->ops->port_set_ether_type) 2629 return chip->info->ops->port_set_ether_type(chip, port, etype); 2630 2631 return 0; 2632 } 2633 2634 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2635 { 2636 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2637 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2638 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2639 } 2640 2641 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2642 { 2643 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2644 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2645 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2646 } 2647 2648 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2649 { 2650 return mv88e6xxx_set_port_mode(chip, port, 2651 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2652 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2653 ETH_P_EDSA); 2654 } 2655 2656 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2657 { 2658 if (dsa_is_dsa_port(chip->ds, port)) 2659 return mv88e6xxx_set_port_mode_dsa(chip, port); 2660 2661 if (dsa_is_user_port(chip->ds, port)) 2662 return mv88e6xxx_set_port_mode_normal(chip, port); 2663 2664 /* Setup CPU port mode depending on its supported tag format */ 2665 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2666 return mv88e6xxx_set_port_mode_dsa(chip, port); 2667 2668 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2669 return mv88e6xxx_set_port_mode_edsa(chip, port); 2670 2671 return -EINVAL; 2672 } 2673 2674 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2675 { 2676 bool message = dsa_is_dsa_port(chip->ds, port); 2677 2678 return mv88e6xxx_port_set_message_port(chip, port, message); 2679 } 2680 2681 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2682 { 2683 int err; 2684 2685 if (chip->info->ops->port_set_ucast_flood) { 2686 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2687 if (err) 2688 return err; 2689 } 2690 if (chip->info->ops->port_set_mcast_flood) { 2691 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2692 if (err) 2693 return err; 2694 } 2695 2696 return 0; 2697 } 2698 2699 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2700 { 2701 struct mv88e6xxx_port *mvp = dev_id; 2702 struct mv88e6xxx_chip *chip = mvp->chip; 2703 irqreturn_t ret = IRQ_NONE; 2704 int port = mvp->port; 2705 int lane; 2706 2707 mv88e6xxx_reg_lock(chip); 2708 lane = mv88e6xxx_serdes_get_lane(chip, port); 2709 if (lane >= 0) 2710 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2711 mv88e6xxx_reg_unlock(chip); 2712 2713 return ret; 2714 } 2715 2716 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2717 int lane) 2718 { 2719 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2720 unsigned int irq; 2721 int err; 2722 2723 /* Nothing to request if this SERDES port has no IRQ */ 2724 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2725 if (!irq) 2726 return 0; 2727 2728 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2729 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2730 2731 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2732 mv88e6xxx_reg_unlock(chip); 2733 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2734 IRQF_ONESHOT, dev_id->serdes_irq_name, 2735 dev_id); 2736 mv88e6xxx_reg_lock(chip); 2737 if (err) 2738 return err; 2739 2740 dev_id->serdes_irq = irq; 2741 2742 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2743 } 2744 2745 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2746 int lane) 2747 { 2748 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2749 unsigned int irq = dev_id->serdes_irq; 2750 int err; 2751 2752 /* Nothing to free if no IRQ has been requested */ 2753 if (!irq) 2754 return 0; 2755 2756 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2757 2758 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2759 mv88e6xxx_reg_unlock(chip); 2760 free_irq(irq, dev_id); 2761 mv88e6xxx_reg_lock(chip); 2762 2763 dev_id->serdes_irq = 0; 2764 2765 return err; 2766 } 2767 2768 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2769 bool on) 2770 { 2771 int lane; 2772 int err; 2773 2774 lane = mv88e6xxx_serdes_get_lane(chip, port); 2775 if (lane < 0) 2776 return 0; 2777 2778 if (on) { 2779 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2780 if (err) 2781 return err; 2782 2783 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2784 } else { 2785 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2786 if (err) 2787 return err; 2788 2789 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2790 } 2791 2792 return err; 2793 } 2794 2795 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2796 enum mv88e6xxx_egress_direction direction, 2797 int port) 2798 { 2799 int err; 2800 2801 if (!chip->info->ops->set_egress_port) 2802 return -EOPNOTSUPP; 2803 2804 err = chip->info->ops->set_egress_port(chip, direction, port); 2805 if (err) 2806 return err; 2807 2808 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2809 chip->ingress_dest_port = port; 2810 else 2811 chip->egress_dest_port = port; 2812 2813 return 0; 2814 } 2815 2816 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2817 { 2818 struct dsa_switch *ds = chip->ds; 2819 int upstream_port; 2820 int err; 2821 2822 upstream_port = dsa_upstream_port(ds, port); 2823 if (chip->info->ops->port_set_upstream_port) { 2824 err = chip->info->ops->port_set_upstream_port(chip, port, 2825 upstream_port); 2826 if (err) 2827 return err; 2828 } 2829 2830 if (port == upstream_port) { 2831 if (chip->info->ops->set_cpu_port) { 2832 err = chip->info->ops->set_cpu_port(chip, 2833 upstream_port); 2834 if (err) 2835 return err; 2836 } 2837 2838 err = mv88e6xxx_set_egress_port(chip, 2839 MV88E6XXX_EGRESS_DIR_INGRESS, 2840 upstream_port); 2841 if (err && err != -EOPNOTSUPP) 2842 return err; 2843 2844 err = mv88e6xxx_set_egress_port(chip, 2845 MV88E6XXX_EGRESS_DIR_EGRESS, 2846 upstream_port); 2847 if (err && err != -EOPNOTSUPP) 2848 return err; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2855 { 2856 struct dsa_switch *ds = chip->ds; 2857 int err; 2858 u16 reg; 2859 2860 chip->ports[port].chip = chip; 2861 chip->ports[port].port = port; 2862 2863 /* MAC Forcing register: don't force link, speed, duplex or flow control 2864 * state to any particular values on physical ports, but force the CPU 2865 * port and all DSA ports to their maximum bandwidth and full duplex. 2866 */ 2867 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2868 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2869 SPEED_MAX, DUPLEX_FULL, 2870 PAUSE_OFF, 2871 PHY_INTERFACE_MODE_NA); 2872 else 2873 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2874 SPEED_UNFORCED, DUPLEX_UNFORCED, 2875 PAUSE_ON, 2876 PHY_INTERFACE_MODE_NA); 2877 if (err) 2878 return err; 2879 2880 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2881 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2882 * tunneling, determine priority by looking at 802.1p and IP 2883 * priority fields (IP prio has precedence), and set STP state 2884 * to Forwarding. 2885 * 2886 * If this is the CPU link, use DSA or EDSA tagging depending 2887 * on which tagging mode was configured. 2888 * 2889 * If this is a link to another switch, use DSA tagging mode. 2890 * 2891 * If this is the upstream port for this switch, enable 2892 * forwarding of unknown unicasts and multicasts. 2893 */ 2894 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2895 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2896 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2897 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2898 if (err) 2899 return err; 2900 2901 err = mv88e6xxx_setup_port_mode(chip, port); 2902 if (err) 2903 return err; 2904 2905 err = mv88e6xxx_setup_egress_floods(chip, port); 2906 if (err) 2907 return err; 2908 2909 /* Port Control 2: don't force a good FCS, set the MTU size to 2910 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2911 * untagged frames on this port, do a destination address lookup on all 2912 * received packets as usual, disable ARP mirroring and don't send a 2913 * copy of all transmitted/received frames on this port to the CPU. 2914 */ 2915 err = mv88e6xxx_port_set_map_da(chip, port); 2916 if (err) 2917 return err; 2918 2919 err = mv88e6xxx_setup_upstream_port(chip, port); 2920 if (err) 2921 return err; 2922 2923 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2924 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2925 if (err) 2926 return err; 2927 2928 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2929 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2930 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2931 * as the private PVID on ports under a VLAN-unaware bridge. 2932 * Shared (DSA and CPU) ports must also be members of it, to translate 2933 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2934 * relying on their port default FID. 2935 */ 2936 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2937 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2938 false); 2939 if (err) 2940 return err; 2941 2942 if (chip->info->ops->port_set_jumbo_size) { 2943 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2944 if (err) 2945 return err; 2946 } 2947 2948 /* Port Association Vector: disable automatic address learning 2949 * on all user ports since they start out in standalone 2950 * mode. When joining a bridge, learning will be configured to 2951 * match the bridge port settings. Enable learning on all 2952 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2953 * learning process. 2954 * 2955 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2956 * and RefreshLocked. I.e. setup standard automatic learning. 2957 */ 2958 if (dsa_is_user_port(ds, port)) 2959 reg = 0; 2960 else 2961 reg = 1 << port; 2962 2963 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2964 reg); 2965 if (err) 2966 return err; 2967 2968 /* Egress rate control 2: disable egress rate control. */ 2969 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2970 0x0000); 2971 if (err) 2972 return err; 2973 2974 if (chip->info->ops->port_pause_limit) { 2975 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2976 if (err) 2977 return err; 2978 } 2979 2980 if (chip->info->ops->port_disable_learn_limit) { 2981 err = chip->info->ops->port_disable_learn_limit(chip, port); 2982 if (err) 2983 return err; 2984 } 2985 2986 if (chip->info->ops->port_disable_pri_override) { 2987 err = chip->info->ops->port_disable_pri_override(chip, port); 2988 if (err) 2989 return err; 2990 } 2991 2992 if (chip->info->ops->port_tag_remap) { 2993 err = chip->info->ops->port_tag_remap(chip, port); 2994 if (err) 2995 return err; 2996 } 2997 2998 if (chip->info->ops->port_egress_rate_limiting) { 2999 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3000 if (err) 3001 return err; 3002 } 3003 3004 if (chip->info->ops->port_setup_message_port) { 3005 err = chip->info->ops->port_setup_message_port(chip, port); 3006 if (err) 3007 return err; 3008 } 3009 3010 /* Port based VLAN map: give each port the same default address 3011 * database, and allow bidirectional communication between the 3012 * CPU and DSA port(s), and the other ports. 3013 */ 3014 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3015 if (err) 3016 return err; 3017 3018 err = mv88e6xxx_port_vlan_map(chip, port); 3019 if (err) 3020 return err; 3021 3022 /* Default VLAN ID and priority: don't set a default VLAN 3023 * ID, and set the default packet priority to zero. 3024 */ 3025 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3026 } 3027 3028 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3029 { 3030 struct mv88e6xxx_chip *chip = ds->priv; 3031 3032 if (chip->info->ops->port_set_jumbo_size) 3033 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3034 else if (chip->info->ops->set_max_frame_size) 3035 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3036 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3037 } 3038 3039 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3040 { 3041 struct mv88e6xxx_chip *chip = ds->priv; 3042 int ret = 0; 3043 3044 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3045 new_mtu += EDSA_HLEN; 3046 3047 mv88e6xxx_reg_lock(chip); 3048 if (chip->info->ops->port_set_jumbo_size) 3049 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3050 else if (chip->info->ops->set_max_frame_size) 3051 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3052 else 3053 if (new_mtu > 1522) 3054 ret = -EINVAL; 3055 mv88e6xxx_reg_unlock(chip); 3056 3057 return ret; 3058 } 3059 3060 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3061 struct phy_device *phydev) 3062 { 3063 struct mv88e6xxx_chip *chip = ds->priv; 3064 int err; 3065 3066 mv88e6xxx_reg_lock(chip); 3067 err = mv88e6xxx_serdes_power(chip, port, true); 3068 mv88e6xxx_reg_unlock(chip); 3069 3070 return err; 3071 } 3072 3073 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3074 { 3075 struct mv88e6xxx_chip *chip = ds->priv; 3076 3077 mv88e6xxx_reg_lock(chip); 3078 if (mv88e6xxx_serdes_power(chip, port, false)) 3079 dev_err(chip->dev, "failed to power off SERDES\n"); 3080 mv88e6xxx_reg_unlock(chip); 3081 } 3082 3083 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3084 unsigned int ageing_time) 3085 { 3086 struct mv88e6xxx_chip *chip = ds->priv; 3087 int err; 3088 3089 mv88e6xxx_reg_lock(chip); 3090 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3091 mv88e6xxx_reg_unlock(chip); 3092 3093 return err; 3094 } 3095 3096 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3097 { 3098 int err; 3099 3100 /* Initialize the statistics unit */ 3101 if (chip->info->ops->stats_set_histogram) { 3102 err = chip->info->ops->stats_set_histogram(chip); 3103 if (err) 3104 return err; 3105 } 3106 3107 return mv88e6xxx_g1_stats_clear(chip); 3108 } 3109 3110 /* Check if the errata has already been applied. */ 3111 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3112 { 3113 int port; 3114 int err; 3115 u16 val; 3116 3117 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3118 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3119 if (err) { 3120 dev_err(chip->dev, 3121 "Error reading hidden register: %d\n", err); 3122 return false; 3123 } 3124 if (val != 0x01c0) 3125 return false; 3126 } 3127 3128 return true; 3129 } 3130 3131 /* The 6390 copper ports have an errata which require poking magic 3132 * values into undocumented hidden registers and then performing a 3133 * software reset. 3134 */ 3135 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3136 { 3137 int port; 3138 int err; 3139 3140 if (mv88e6390_setup_errata_applied(chip)) 3141 return 0; 3142 3143 /* Set the ports into blocking mode */ 3144 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3145 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3146 if (err) 3147 return err; 3148 } 3149 3150 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3151 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3152 if (err) 3153 return err; 3154 } 3155 3156 return mv88e6xxx_software_reset(chip); 3157 } 3158 3159 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3160 { 3161 mv88e6xxx_teardown_devlink_params(ds); 3162 dsa_devlink_resources_unregister(ds); 3163 mv88e6xxx_teardown_devlink_regions_global(ds); 3164 } 3165 3166 static int mv88e6xxx_setup(struct dsa_switch *ds) 3167 { 3168 struct mv88e6xxx_chip *chip = ds->priv; 3169 u8 cmode; 3170 int err; 3171 int i; 3172 3173 chip->ds = ds; 3174 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3175 3176 /* Since virtual bridges are mapped in the PVT, the number we support 3177 * depends on the physical switch topology. We need to let DSA figure 3178 * that out and therefore we cannot set this at dsa_register_switch() 3179 * time. 3180 */ 3181 if (mv88e6xxx_has_pvt(chip)) 3182 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3183 ds->dst->last_switch - 1; 3184 3185 mv88e6xxx_reg_lock(chip); 3186 3187 if (chip->info->ops->setup_errata) { 3188 err = chip->info->ops->setup_errata(chip); 3189 if (err) 3190 goto unlock; 3191 } 3192 3193 /* Cache the cmode of each port. */ 3194 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3195 if (chip->info->ops->port_get_cmode) { 3196 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3197 if (err) 3198 goto unlock; 3199 3200 chip->ports[i].cmode = cmode; 3201 } 3202 } 3203 3204 err = mv88e6xxx_vtu_setup(chip); 3205 if (err) 3206 goto unlock; 3207 3208 /* Setup Switch Port Registers */ 3209 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3210 if (dsa_is_unused_port(ds, i)) 3211 continue; 3212 3213 /* Prevent the use of an invalid port. */ 3214 if (mv88e6xxx_is_invalid_port(chip, i)) { 3215 dev_err(chip->dev, "port %d is invalid\n", i); 3216 err = -EINVAL; 3217 goto unlock; 3218 } 3219 3220 err = mv88e6xxx_setup_port(chip, i); 3221 if (err) 3222 goto unlock; 3223 } 3224 3225 err = mv88e6xxx_irl_setup(chip); 3226 if (err) 3227 goto unlock; 3228 3229 err = mv88e6xxx_mac_setup(chip); 3230 if (err) 3231 goto unlock; 3232 3233 err = mv88e6xxx_phy_setup(chip); 3234 if (err) 3235 goto unlock; 3236 3237 err = mv88e6xxx_pvt_setup(chip); 3238 if (err) 3239 goto unlock; 3240 3241 err = mv88e6xxx_atu_setup(chip); 3242 if (err) 3243 goto unlock; 3244 3245 err = mv88e6xxx_broadcast_setup(chip, 0); 3246 if (err) 3247 goto unlock; 3248 3249 err = mv88e6xxx_pot_setup(chip); 3250 if (err) 3251 goto unlock; 3252 3253 err = mv88e6xxx_rmu_setup(chip); 3254 if (err) 3255 goto unlock; 3256 3257 err = mv88e6xxx_rsvd2cpu_setup(chip); 3258 if (err) 3259 goto unlock; 3260 3261 err = mv88e6xxx_trunk_setup(chip); 3262 if (err) 3263 goto unlock; 3264 3265 err = mv88e6xxx_devmap_setup(chip); 3266 if (err) 3267 goto unlock; 3268 3269 err = mv88e6xxx_pri_setup(chip); 3270 if (err) 3271 goto unlock; 3272 3273 /* Setup PTP Hardware Clock and timestamping */ 3274 if (chip->info->ptp_support) { 3275 err = mv88e6xxx_ptp_setup(chip); 3276 if (err) 3277 goto unlock; 3278 3279 err = mv88e6xxx_hwtstamp_setup(chip); 3280 if (err) 3281 goto unlock; 3282 } 3283 3284 err = mv88e6xxx_stats_setup(chip); 3285 if (err) 3286 goto unlock; 3287 3288 unlock: 3289 mv88e6xxx_reg_unlock(chip); 3290 3291 if (err) 3292 return err; 3293 3294 /* Have to be called without holding the register lock, since 3295 * they take the devlink lock, and we later take the locks in 3296 * the reverse order when getting/setting parameters or 3297 * resource occupancy. 3298 */ 3299 err = mv88e6xxx_setup_devlink_resources(ds); 3300 if (err) 3301 return err; 3302 3303 err = mv88e6xxx_setup_devlink_params(ds); 3304 if (err) 3305 goto out_resources; 3306 3307 err = mv88e6xxx_setup_devlink_regions_global(ds); 3308 if (err) 3309 goto out_params; 3310 3311 return 0; 3312 3313 out_params: 3314 mv88e6xxx_teardown_devlink_params(ds); 3315 out_resources: 3316 dsa_devlink_resources_unregister(ds); 3317 3318 return err; 3319 } 3320 3321 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3322 { 3323 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3324 } 3325 3326 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3327 { 3328 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3329 } 3330 3331 /* prod_id for switch families which do not have a PHY model number */ 3332 static const u16 family_prod_id_table[] = { 3333 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3334 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3335 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3336 }; 3337 3338 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3339 { 3340 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3341 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3342 u16 prod_id; 3343 u16 val; 3344 int err; 3345 3346 if (!chip->info->ops->phy_read) 3347 return -EOPNOTSUPP; 3348 3349 mv88e6xxx_reg_lock(chip); 3350 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3351 mv88e6xxx_reg_unlock(chip); 3352 3353 /* Some internal PHYs don't have a model number. */ 3354 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3355 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3356 prod_id = family_prod_id_table[chip->info->family]; 3357 if (prod_id) 3358 val |= prod_id >> 4; 3359 } 3360 3361 return err ? err : val; 3362 } 3363 3364 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3365 { 3366 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3367 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3368 int err; 3369 3370 if (!chip->info->ops->phy_write) 3371 return -EOPNOTSUPP; 3372 3373 mv88e6xxx_reg_lock(chip); 3374 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3375 mv88e6xxx_reg_unlock(chip); 3376 3377 return err; 3378 } 3379 3380 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3381 struct device_node *np, 3382 bool external) 3383 { 3384 static int index; 3385 struct mv88e6xxx_mdio_bus *mdio_bus; 3386 struct mii_bus *bus; 3387 int err; 3388 3389 if (external) { 3390 mv88e6xxx_reg_lock(chip); 3391 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3392 mv88e6xxx_reg_unlock(chip); 3393 3394 if (err) 3395 return err; 3396 } 3397 3398 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3399 if (!bus) 3400 return -ENOMEM; 3401 3402 mdio_bus = bus->priv; 3403 mdio_bus->bus = bus; 3404 mdio_bus->chip = chip; 3405 INIT_LIST_HEAD(&mdio_bus->list); 3406 mdio_bus->external = external; 3407 3408 if (np) { 3409 bus->name = np->full_name; 3410 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3411 } else { 3412 bus->name = "mv88e6xxx SMI"; 3413 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3414 } 3415 3416 bus->read = mv88e6xxx_mdio_read; 3417 bus->write = mv88e6xxx_mdio_write; 3418 bus->parent = chip->dev; 3419 3420 if (!external) { 3421 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3422 if (err) 3423 return err; 3424 } 3425 3426 err = of_mdiobus_register(bus, np); 3427 if (err) { 3428 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3429 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3430 return err; 3431 } 3432 3433 if (external) 3434 list_add_tail(&mdio_bus->list, &chip->mdios); 3435 else 3436 list_add(&mdio_bus->list, &chip->mdios); 3437 3438 return 0; 3439 } 3440 3441 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3442 3443 { 3444 struct mv88e6xxx_mdio_bus *mdio_bus; 3445 struct mii_bus *bus; 3446 3447 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3448 bus = mdio_bus->bus; 3449 3450 if (!mdio_bus->external) 3451 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3452 3453 mdiobus_unregister(bus); 3454 } 3455 } 3456 3457 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3458 struct device_node *np) 3459 { 3460 struct device_node *child; 3461 int err; 3462 3463 /* Always register one mdio bus for the internal/default mdio 3464 * bus. This maybe represented in the device tree, but is 3465 * optional. 3466 */ 3467 child = of_get_child_by_name(np, "mdio"); 3468 err = mv88e6xxx_mdio_register(chip, child, false); 3469 if (err) 3470 return err; 3471 3472 /* Walk the device tree, and see if there are any other nodes 3473 * which say they are compatible with the external mdio 3474 * bus. 3475 */ 3476 for_each_available_child_of_node(np, child) { 3477 if (of_device_is_compatible( 3478 child, "marvell,mv88e6xxx-mdio-external")) { 3479 err = mv88e6xxx_mdio_register(chip, child, true); 3480 if (err) { 3481 mv88e6xxx_mdios_unregister(chip); 3482 of_node_put(child); 3483 return err; 3484 } 3485 } 3486 } 3487 3488 return 0; 3489 } 3490 3491 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3492 { 3493 struct mv88e6xxx_chip *chip = ds->priv; 3494 3495 return chip->eeprom_len; 3496 } 3497 3498 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3499 struct ethtool_eeprom *eeprom, u8 *data) 3500 { 3501 struct mv88e6xxx_chip *chip = ds->priv; 3502 int err; 3503 3504 if (!chip->info->ops->get_eeprom) 3505 return -EOPNOTSUPP; 3506 3507 mv88e6xxx_reg_lock(chip); 3508 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3509 mv88e6xxx_reg_unlock(chip); 3510 3511 if (err) 3512 return err; 3513 3514 eeprom->magic = 0xc3ec4951; 3515 3516 return 0; 3517 } 3518 3519 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3520 struct ethtool_eeprom *eeprom, u8 *data) 3521 { 3522 struct mv88e6xxx_chip *chip = ds->priv; 3523 int err; 3524 3525 if (!chip->info->ops->set_eeprom) 3526 return -EOPNOTSUPP; 3527 3528 if (eeprom->magic != 0xc3ec4951) 3529 return -EINVAL; 3530 3531 mv88e6xxx_reg_lock(chip); 3532 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3533 mv88e6xxx_reg_unlock(chip); 3534 3535 return err; 3536 } 3537 3538 static const struct mv88e6xxx_ops mv88e6085_ops = { 3539 /* MV88E6XXX_FAMILY_6097 */ 3540 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3541 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3542 .irl_init_all = mv88e6352_g2_irl_init_all, 3543 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3544 .phy_read = mv88e6185_phy_ppu_read, 3545 .phy_write = mv88e6185_phy_ppu_write, 3546 .port_set_link = mv88e6xxx_port_set_link, 3547 .port_sync_link = mv88e6xxx_port_sync_link, 3548 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3549 .port_tag_remap = mv88e6095_port_tag_remap, 3550 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3551 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3552 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3553 .port_set_ether_type = mv88e6351_port_set_ether_type, 3554 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3555 .port_pause_limit = mv88e6097_port_pause_limit, 3556 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3557 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3558 .port_get_cmode = mv88e6185_port_get_cmode, 3559 .port_setup_message_port = mv88e6xxx_setup_message_port, 3560 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3561 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3562 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3563 .stats_get_strings = mv88e6095_stats_get_strings, 3564 .stats_get_stats = mv88e6095_stats_get_stats, 3565 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3566 .set_egress_port = mv88e6095_g1_set_egress_port, 3567 .watchdog_ops = &mv88e6097_watchdog_ops, 3568 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3569 .pot_clear = mv88e6xxx_g2_pot_clear, 3570 .ppu_enable = mv88e6185_g1_ppu_enable, 3571 .ppu_disable = mv88e6185_g1_ppu_disable, 3572 .reset = mv88e6185_g1_reset, 3573 .rmu_disable = mv88e6085_g1_rmu_disable, 3574 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3575 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3576 .phylink_validate = mv88e6185_phylink_validate, 3577 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3578 }; 3579 3580 static const struct mv88e6xxx_ops mv88e6095_ops = { 3581 /* MV88E6XXX_FAMILY_6095 */ 3582 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3583 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3584 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3585 .phy_read = mv88e6185_phy_ppu_read, 3586 .phy_write = mv88e6185_phy_ppu_write, 3587 .port_set_link = mv88e6xxx_port_set_link, 3588 .port_sync_link = mv88e6185_port_sync_link, 3589 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3590 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3591 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3592 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3593 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3594 .port_get_cmode = mv88e6185_port_get_cmode, 3595 .port_setup_message_port = mv88e6xxx_setup_message_port, 3596 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3598 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3599 .stats_get_strings = mv88e6095_stats_get_strings, 3600 .stats_get_stats = mv88e6095_stats_get_stats, 3601 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3602 .serdes_power = mv88e6185_serdes_power, 3603 .serdes_get_lane = mv88e6185_serdes_get_lane, 3604 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3605 .ppu_enable = mv88e6185_g1_ppu_enable, 3606 .ppu_disable = mv88e6185_g1_ppu_disable, 3607 .reset = mv88e6185_g1_reset, 3608 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3609 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3610 .phylink_validate = mv88e6185_phylink_validate, 3611 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3612 }; 3613 3614 static const struct mv88e6xxx_ops mv88e6097_ops = { 3615 /* MV88E6XXX_FAMILY_6097 */ 3616 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3617 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3618 .irl_init_all = mv88e6352_g2_irl_init_all, 3619 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3620 .phy_read = mv88e6xxx_g2_smi_phy_read, 3621 .phy_write = mv88e6xxx_g2_smi_phy_write, 3622 .port_set_link = mv88e6xxx_port_set_link, 3623 .port_sync_link = mv88e6185_port_sync_link, 3624 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3625 .port_tag_remap = mv88e6095_port_tag_remap, 3626 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3627 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3628 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3629 .port_set_ether_type = mv88e6351_port_set_ether_type, 3630 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3631 .port_pause_limit = mv88e6097_port_pause_limit, 3632 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3633 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3634 .port_get_cmode = mv88e6185_port_get_cmode, 3635 .port_setup_message_port = mv88e6xxx_setup_message_port, 3636 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3637 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3638 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3639 .stats_get_strings = mv88e6095_stats_get_strings, 3640 .stats_get_stats = mv88e6095_stats_get_stats, 3641 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3642 .set_egress_port = mv88e6095_g1_set_egress_port, 3643 .watchdog_ops = &mv88e6097_watchdog_ops, 3644 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3645 .serdes_power = mv88e6185_serdes_power, 3646 .serdes_get_lane = mv88e6185_serdes_get_lane, 3647 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3648 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3649 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3650 .serdes_irq_status = mv88e6097_serdes_irq_status, 3651 .pot_clear = mv88e6xxx_g2_pot_clear, 3652 .reset = mv88e6352_g1_reset, 3653 .rmu_disable = mv88e6085_g1_rmu_disable, 3654 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3655 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3656 .phylink_validate = mv88e6185_phylink_validate, 3657 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3658 }; 3659 3660 static const struct mv88e6xxx_ops mv88e6123_ops = { 3661 /* MV88E6XXX_FAMILY_6165 */ 3662 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3663 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3664 .irl_init_all = mv88e6352_g2_irl_init_all, 3665 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3666 .phy_read = mv88e6xxx_g2_smi_phy_read, 3667 .phy_write = mv88e6xxx_g2_smi_phy_write, 3668 .port_set_link = mv88e6xxx_port_set_link, 3669 .port_sync_link = mv88e6xxx_port_sync_link, 3670 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3671 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3672 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3673 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3674 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3675 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3676 .port_get_cmode = mv88e6185_port_get_cmode, 3677 .port_setup_message_port = mv88e6xxx_setup_message_port, 3678 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3680 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3681 .stats_get_strings = mv88e6095_stats_get_strings, 3682 .stats_get_stats = mv88e6095_stats_get_stats, 3683 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3684 .set_egress_port = mv88e6095_g1_set_egress_port, 3685 .watchdog_ops = &mv88e6097_watchdog_ops, 3686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3687 .pot_clear = mv88e6xxx_g2_pot_clear, 3688 .reset = mv88e6352_g1_reset, 3689 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3690 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3691 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3693 .phylink_validate = mv88e6185_phylink_validate, 3694 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3695 }; 3696 3697 static const struct mv88e6xxx_ops mv88e6131_ops = { 3698 /* MV88E6XXX_FAMILY_6185 */ 3699 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3700 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3701 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3702 .phy_read = mv88e6185_phy_ppu_read, 3703 .phy_write = mv88e6185_phy_ppu_write, 3704 .port_set_link = mv88e6xxx_port_set_link, 3705 .port_sync_link = mv88e6xxx_port_sync_link, 3706 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3707 .port_tag_remap = mv88e6095_port_tag_remap, 3708 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3709 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3710 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3711 .port_set_ether_type = mv88e6351_port_set_ether_type, 3712 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3713 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3714 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3715 .port_pause_limit = mv88e6097_port_pause_limit, 3716 .port_set_pause = mv88e6185_port_set_pause, 3717 .port_get_cmode = mv88e6185_port_get_cmode, 3718 .port_setup_message_port = mv88e6xxx_setup_message_port, 3719 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3720 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3721 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3722 .stats_get_strings = mv88e6095_stats_get_strings, 3723 .stats_get_stats = mv88e6095_stats_get_stats, 3724 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3725 .set_egress_port = mv88e6095_g1_set_egress_port, 3726 .watchdog_ops = &mv88e6097_watchdog_ops, 3727 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3728 .ppu_enable = mv88e6185_g1_ppu_enable, 3729 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3730 .ppu_disable = mv88e6185_g1_ppu_disable, 3731 .reset = mv88e6185_g1_reset, 3732 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3733 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3734 .phylink_validate = mv88e6185_phylink_validate, 3735 }; 3736 3737 static const struct mv88e6xxx_ops mv88e6141_ops = { 3738 /* MV88E6XXX_FAMILY_6341 */ 3739 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3740 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3741 .irl_init_all = mv88e6352_g2_irl_init_all, 3742 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3743 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3744 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3745 .phy_read = mv88e6xxx_g2_smi_phy_read, 3746 .phy_write = mv88e6xxx_g2_smi_phy_write, 3747 .port_set_link = mv88e6xxx_port_set_link, 3748 .port_sync_link = mv88e6xxx_port_sync_link, 3749 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3750 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3751 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3752 .port_tag_remap = mv88e6095_port_tag_remap, 3753 .port_set_policy = mv88e6352_port_set_policy, 3754 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3755 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3756 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3757 .port_set_ether_type = mv88e6351_port_set_ether_type, 3758 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3759 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3760 .port_pause_limit = mv88e6097_port_pause_limit, 3761 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3762 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3763 .port_get_cmode = mv88e6352_port_get_cmode, 3764 .port_set_cmode = mv88e6341_port_set_cmode, 3765 .port_setup_message_port = mv88e6xxx_setup_message_port, 3766 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3767 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3768 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3769 .stats_get_strings = mv88e6320_stats_get_strings, 3770 .stats_get_stats = mv88e6390_stats_get_stats, 3771 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3772 .set_egress_port = mv88e6390_g1_set_egress_port, 3773 .watchdog_ops = &mv88e6390_watchdog_ops, 3774 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3775 .pot_clear = mv88e6xxx_g2_pot_clear, 3776 .reset = mv88e6352_g1_reset, 3777 .rmu_disable = mv88e6390_g1_rmu_disable, 3778 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3779 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3780 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3781 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3782 .serdes_power = mv88e6390_serdes_power, 3783 .serdes_get_lane = mv88e6341_serdes_get_lane, 3784 /* Check status register pause & lpa register */ 3785 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3786 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3787 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3788 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3789 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3790 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3791 .serdes_irq_status = mv88e6390_serdes_irq_status, 3792 .gpio_ops = &mv88e6352_gpio_ops, 3793 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3794 .serdes_get_strings = mv88e6390_serdes_get_strings, 3795 .serdes_get_stats = mv88e6390_serdes_get_stats, 3796 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3797 .serdes_get_regs = mv88e6390_serdes_get_regs, 3798 .phylink_validate = mv88e6341_phylink_validate, 3799 }; 3800 3801 static const struct mv88e6xxx_ops mv88e6161_ops = { 3802 /* MV88E6XXX_FAMILY_6165 */ 3803 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3804 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3805 .irl_init_all = mv88e6352_g2_irl_init_all, 3806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3807 .phy_read = mv88e6xxx_g2_smi_phy_read, 3808 .phy_write = mv88e6xxx_g2_smi_phy_write, 3809 .port_set_link = mv88e6xxx_port_set_link, 3810 .port_sync_link = mv88e6xxx_port_sync_link, 3811 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3812 .port_tag_remap = mv88e6095_port_tag_remap, 3813 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3814 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3815 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3816 .port_set_ether_type = mv88e6351_port_set_ether_type, 3817 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3818 .port_pause_limit = mv88e6097_port_pause_limit, 3819 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3820 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3821 .port_get_cmode = mv88e6185_port_get_cmode, 3822 .port_setup_message_port = mv88e6xxx_setup_message_port, 3823 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3824 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3825 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3826 .stats_get_strings = mv88e6095_stats_get_strings, 3827 .stats_get_stats = mv88e6095_stats_get_stats, 3828 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3829 .set_egress_port = mv88e6095_g1_set_egress_port, 3830 .watchdog_ops = &mv88e6097_watchdog_ops, 3831 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3832 .pot_clear = mv88e6xxx_g2_pot_clear, 3833 .reset = mv88e6352_g1_reset, 3834 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3835 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3836 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3837 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3838 .avb_ops = &mv88e6165_avb_ops, 3839 .ptp_ops = &mv88e6165_ptp_ops, 3840 .phylink_validate = mv88e6185_phylink_validate, 3841 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3842 }; 3843 3844 static const struct mv88e6xxx_ops mv88e6165_ops = { 3845 /* MV88E6XXX_FAMILY_6165 */ 3846 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3847 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3848 .irl_init_all = mv88e6352_g2_irl_init_all, 3849 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3850 .phy_read = mv88e6165_phy_read, 3851 .phy_write = mv88e6165_phy_write, 3852 .port_set_link = mv88e6xxx_port_set_link, 3853 .port_sync_link = mv88e6xxx_port_sync_link, 3854 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3857 .port_get_cmode = mv88e6185_port_get_cmode, 3858 .port_setup_message_port = mv88e6xxx_setup_message_port, 3859 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3860 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3861 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3862 .stats_get_strings = mv88e6095_stats_get_strings, 3863 .stats_get_stats = mv88e6095_stats_get_stats, 3864 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3865 .set_egress_port = mv88e6095_g1_set_egress_port, 3866 .watchdog_ops = &mv88e6097_watchdog_ops, 3867 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3868 .pot_clear = mv88e6xxx_g2_pot_clear, 3869 .reset = mv88e6352_g1_reset, 3870 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3871 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3872 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3873 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3874 .avb_ops = &mv88e6165_avb_ops, 3875 .ptp_ops = &mv88e6165_ptp_ops, 3876 .phylink_validate = mv88e6185_phylink_validate, 3877 }; 3878 3879 static const struct mv88e6xxx_ops mv88e6171_ops = { 3880 /* MV88E6XXX_FAMILY_6351 */ 3881 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3882 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3883 .irl_init_all = mv88e6352_g2_irl_init_all, 3884 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3885 .phy_read = mv88e6xxx_g2_smi_phy_read, 3886 .phy_write = mv88e6xxx_g2_smi_phy_write, 3887 .port_set_link = mv88e6xxx_port_set_link, 3888 .port_sync_link = mv88e6xxx_port_sync_link, 3889 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3890 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3891 .port_tag_remap = mv88e6095_port_tag_remap, 3892 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3893 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3894 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3895 .port_set_ether_type = mv88e6351_port_set_ether_type, 3896 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3897 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3898 .port_pause_limit = mv88e6097_port_pause_limit, 3899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3901 .port_get_cmode = mv88e6352_port_get_cmode, 3902 .port_setup_message_port = mv88e6xxx_setup_message_port, 3903 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3904 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3905 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3906 .stats_get_strings = mv88e6095_stats_get_strings, 3907 .stats_get_stats = mv88e6095_stats_get_stats, 3908 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3909 .set_egress_port = mv88e6095_g1_set_egress_port, 3910 .watchdog_ops = &mv88e6097_watchdog_ops, 3911 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3912 .pot_clear = mv88e6xxx_g2_pot_clear, 3913 .reset = mv88e6352_g1_reset, 3914 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3915 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3916 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3917 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3918 .phylink_validate = mv88e6185_phylink_validate, 3919 }; 3920 3921 static const struct mv88e6xxx_ops mv88e6172_ops = { 3922 /* MV88E6XXX_FAMILY_6352 */ 3923 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3924 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3925 .irl_init_all = mv88e6352_g2_irl_init_all, 3926 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3927 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3928 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3929 .phy_read = mv88e6xxx_g2_smi_phy_read, 3930 .phy_write = mv88e6xxx_g2_smi_phy_write, 3931 .port_set_link = mv88e6xxx_port_set_link, 3932 .port_sync_link = mv88e6xxx_port_sync_link, 3933 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3934 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3935 .port_tag_remap = mv88e6095_port_tag_remap, 3936 .port_set_policy = mv88e6352_port_set_policy, 3937 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3938 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3939 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3940 .port_set_ether_type = mv88e6351_port_set_ether_type, 3941 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3942 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3943 .port_pause_limit = mv88e6097_port_pause_limit, 3944 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3945 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3946 .port_get_cmode = mv88e6352_port_get_cmode, 3947 .port_setup_message_port = mv88e6xxx_setup_message_port, 3948 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3949 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3950 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3951 .stats_get_strings = mv88e6095_stats_get_strings, 3952 .stats_get_stats = mv88e6095_stats_get_stats, 3953 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3954 .set_egress_port = mv88e6095_g1_set_egress_port, 3955 .watchdog_ops = &mv88e6097_watchdog_ops, 3956 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3957 .pot_clear = mv88e6xxx_g2_pot_clear, 3958 .reset = mv88e6352_g1_reset, 3959 .rmu_disable = mv88e6352_g1_rmu_disable, 3960 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3961 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3962 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3963 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3964 .serdes_get_lane = mv88e6352_serdes_get_lane, 3965 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3966 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3967 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3968 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3969 .serdes_power = mv88e6352_serdes_power, 3970 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3971 .serdes_get_regs = mv88e6352_serdes_get_regs, 3972 .gpio_ops = &mv88e6352_gpio_ops, 3973 .phylink_validate = mv88e6352_phylink_validate, 3974 }; 3975 3976 static const struct mv88e6xxx_ops mv88e6175_ops = { 3977 /* MV88E6XXX_FAMILY_6351 */ 3978 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3979 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3980 .irl_init_all = mv88e6352_g2_irl_init_all, 3981 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3982 .phy_read = mv88e6xxx_g2_smi_phy_read, 3983 .phy_write = mv88e6xxx_g2_smi_phy_write, 3984 .port_set_link = mv88e6xxx_port_set_link, 3985 .port_sync_link = mv88e6xxx_port_sync_link, 3986 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3987 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3988 .port_tag_remap = mv88e6095_port_tag_remap, 3989 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3990 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3991 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3992 .port_set_ether_type = mv88e6351_port_set_ether_type, 3993 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3994 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3995 .port_pause_limit = mv88e6097_port_pause_limit, 3996 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3997 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3998 .port_get_cmode = mv88e6352_port_get_cmode, 3999 .port_setup_message_port = mv88e6xxx_setup_message_port, 4000 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4001 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4002 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4003 .stats_get_strings = mv88e6095_stats_get_strings, 4004 .stats_get_stats = mv88e6095_stats_get_stats, 4005 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4006 .set_egress_port = mv88e6095_g1_set_egress_port, 4007 .watchdog_ops = &mv88e6097_watchdog_ops, 4008 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4009 .pot_clear = mv88e6xxx_g2_pot_clear, 4010 .reset = mv88e6352_g1_reset, 4011 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4012 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4013 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4014 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4015 .phylink_validate = mv88e6185_phylink_validate, 4016 }; 4017 4018 static const struct mv88e6xxx_ops mv88e6176_ops = { 4019 /* MV88E6XXX_FAMILY_6352 */ 4020 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4021 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4022 .irl_init_all = mv88e6352_g2_irl_init_all, 4023 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4024 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4025 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4026 .phy_read = mv88e6xxx_g2_smi_phy_read, 4027 .phy_write = mv88e6xxx_g2_smi_phy_write, 4028 .port_set_link = mv88e6xxx_port_set_link, 4029 .port_sync_link = mv88e6xxx_port_sync_link, 4030 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4031 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4032 .port_tag_remap = mv88e6095_port_tag_remap, 4033 .port_set_policy = mv88e6352_port_set_policy, 4034 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4035 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4036 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4037 .port_set_ether_type = mv88e6351_port_set_ether_type, 4038 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4039 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4040 .port_pause_limit = mv88e6097_port_pause_limit, 4041 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4042 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4043 .port_get_cmode = mv88e6352_port_get_cmode, 4044 .port_setup_message_port = mv88e6xxx_setup_message_port, 4045 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4046 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4047 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4048 .stats_get_strings = mv88e6095_stats_get_strings, 4049 .stats_get_stats = mv88e6095_stats_get_stats, 4050 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4051 .set_egress_port = mv88e6095_g1_set_egress_port, 4052 .watchdog_ops = &mv88e6097_watchdog_ops, 4053 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4054 .pot_clear = mv88e6xxx_g2_pot_clear, 4055 .reset = mv88e6352_g1_reset, 4056 .rmu_disable = mv88e6352_g1_rmu_disable, 4057 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4058 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4059 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4060 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4061 .serdes_get_lane = mv88e6352_serdes_get_lane, 4062 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4063 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4064 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4065 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4066 .serdes_power = mv88e6352_serdes_power, 4067 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4068 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4069 .serdes_irq_status = mv88e6352_serdes_irq_status, 4070 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4071 .serdes_get_regs = mv88e6352_serdes_get_regs, 4072 .gpio_ops = &mv88e6352_gpio_ops, 4073 .phylink_validate = mv88e6352_phylink_validate, 4074 }; 4075 4076 static const struct mv88e6xxx_ops mv88e6185_ops = { 4077 /* MV88E6XXX_FAMILY_6185 */ 4078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4079 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4080 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4081 .phy_read = mv88e6185_phy_ppu_read, 4082 .phy_write = mv88e6185_phy_ppu_write, 4083 .port_set_link = mv88e6xxx_port_set_link, 4084 .port_sync_link = mv88e6185_port_sync_link, 4085 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4086 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4087 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4088 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4089 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4090 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4091 .port_set_pause = mv88e6185_port_set_pause, 4092 .port_get_cmode = mv88e6185_port_get_cmode, 4093 .port_setup_message_port = mv88e6xxx_setup_message_port, 4094 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4095 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4096 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4097 .stats_get_strings = mv88e6095_stats_get_strings, 4098 .stats_get_stats = mv88e6095_stats_get_stats, 4099 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4100 .set_egress_port = mv88e6095_g1_set_egress_port, 4101 .watchdog_ops = &mv88e6097_watchdog_ops, 4102 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4103 .serdes_power = mv88e6185_serdes_power, 4104 .serdes_get_lane = mv88e6185_serdes_get_lane, 4105 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4106 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4107 .ppu_enable = mv88e6185_g1_ppu_enable, 4108 .ppu_disable = mv88e6185_g1_ppu_disable, 4109 .reset = mv88e6185_g1_reset, 4110 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4111 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4112 .phylink_validate = mv88e6185_phylink_validate, 4113 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4114 }; 4115 4116 static const struct mv88e6xxx_ops mv88e6190_ops = { 4117 /* MV88E6XXX_FAMILY_6390 */ 4118 .setup_errata = mv88e6390_setup_errata, 4119 .irl_init_all = mv88e6390_g2_irl_init_all, 4120 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4121 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4122 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4123 .phy_read = mv88e6xxx_g2_smi_phy_read, 4124 .phy_write = mv88e6xxx_g2_smi_phy_write, 4125 .port_set_link = mv88e6xxx_port_set_link, 4126 .port_sync_link = mv88e6xxx_port_sync_link, 4127 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4128 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4129 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4130 .port_tag_remap = mv88e6390_port_tag_remap, 4131 .port_set_policy = mv88e6352_port_set_policy, 4132 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4133 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4134 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4135 .port_set_ether_type = mv88e6351_port_set_ether_type, 4136 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4137 .port_pause_limit = mv88e6390_port_pause_limit, 4138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4140 .port_get_cmode = mv88e6352_port_get_cmode, 4141 .port_set_cmode = mv88e6390_port_set_cmode, 4142 .port_setup_message_port = mv88e6xxx_setup_message_port, 4143 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4144 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4145 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4146 .stats_get_strings = mv88e6320_stats_get_strings, 4147 .stats_get_stats = mv88e6390_stats_get_stats, 4148 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4149 .set_egress_port = mv88e6390_g1_set_egress_port, 4150 .watchdog_ops = &mv88e6390_watchdog_ops, 4151 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4152 .pot_clear = mv88e6xxx_g2_pot_clear, 4153 .reset = mv88e6352_g1_reset, 4154 .rmu_disable = mv88e6390_g1_rmu_disable, 4155 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4156 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4157 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4158 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4159 .serdes_power = mv88e6390_serdes_power, 4160 .serdes_get_lane = mv88e6390_serdes_get_lane, 4161 /* Check status register pause & lpa register */ 4162 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4163 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4164 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4165 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4166 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4167 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4168 .serdes_irq_status = mv88e6390_serdes_irq_status, 4169 .serdes_get_strings = mv88e6390_serdes_get_strings, 4170 .serdes_get_stats = mv88e6390_serdes_get_stats, 4171 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4172 .serdes_get_regs = mv88e6390_serdes_get_regs, 4173 .gpio_ops = &mv88e6352_gpio_ops, 4174 .phylink_validate = mv88e6390_phylink_validate, 4175 }; 4176 4177 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4178 /* MV88E6XXX_FAMILY_6390 */ 4179 .setup_errata = mv88e6390_setup_errata, 4180 .irl_init_all = mv88e6390_g2_irl_init_all, 4181 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4182 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4183 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4184 .phy_read = mv88e6xxx_g2_smi_phy_read, 4185 .phy_write = mv88e6xxx_g2_smi_phy_write, 4186 .port_set_link = mv88e6xxx_port_set_link, 4187 .port_sync_link = mv88e6xxx_port_sync_link, 4188 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4189 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4190 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4191 .port_tag_remap = mv88e6390_port_tag_remap, 4192 .port_set_policy = mv88e6352_port_set_policy, 4193 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4194 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4195 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4196 .port_set_ether_type = mv88e6351_port_set_ether_type, 4197 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4198 .port_pause_limit = mv88e6390_port_pause_limit, 4199 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4200 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4201 .port_get_cmode = mv88e6352_port_get_cmode, 4202 .port_set_cmode = mv88e6390x_port_set_cmode, 4203 .port_setup_message_port = mv88e6xxx_setup_message_port, 4204 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4205 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4206 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4207 .stats_get_strings = mv88e6320_stats_get_strings, 4208 .stats_get_stats = mv88e6390_stats_get_stats, 4209 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4210 .set_egress_port = mv88e6390_g1_set_egress_port, 4211 .watchdog_ops = &mv88e6390_watchdog_ops, 4212 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4213 .pot_clear = mv88e6xxx_g2_pot_clear, 4214 .reset = mv88e6352_g1_reset, 4215 .rmu_disable = mv88e6390_g1_rmu_disable, 4216 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4217 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4218 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4219 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4220 .serdes_power = mv88e6390_serdes_power, 4221 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4222 /* Check status register pause & lpa register */ 4223 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4224 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4225 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4226 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4227 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4228 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4229 .serdes_irq_status = mv88e6390_serdes_irq_status, 4230 .serdes_get_strings = mv88e6390_serdes_get_strings, 4231 .serdes_get_stats = mv88e6390_serdes_get_stats, 4232 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4233 .serdes_get_regs = mv88e6390_serdes_get_regs, 4234 .gpio_ops = &mv88e6352_gpio_ops, 4235 .phylink_validate = mv88e6390x_phylink_validate, 4236 }; 4237 4238 static const struct mv88e6xxx_ops mv88e6191_ops = { 4239 /* MV88E6XXX_FAMILY_6390 */ 4240 .setup_errata = mv88e6390_setup_errata, 4241 .irl_init_all = mv88e6390_g2_irl_init_all, 4242 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4243 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4244 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4245 .phy_read = mv88e6xxx_g2_smi_phy_read, 4246 .phy_write = mv88e6xxx_g2_smi_phy_write, 4247 .port_set_link = mv88e6xxx_port_set_link, 4248 .port_sync_link = mv88e6xxx_port_sync_link, 4249 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4250 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4251 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4252 .port_tag_remap = mv88e6390_port_tag_remap, 4253 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4254 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4255 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4256 .port_set_ether_type = mv88e6351_port_set_ether_type, 4257 .port_pause_limit = mv88e6390_port_pause_limit, 4258 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4259 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4260 .port_get_cmode = mv88e6352_port_get_cmode, 4261 .port_set_cmode = mv88e6390_port_set_cmode, 4262 .port_setup_message_port = mv88e6xxx_setup_message_port, 4263 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4264 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4265 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4266 .stats_get_strings = mv88e6320_stats_get_strings, 4267 .stats_get_stats = mv88e6390_stats_get_stats, 4268 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4269 .set_egress_port = mv88e6390_g1_set_egress_port, 4270 .watchdog_ops = &mv88e6390_watchdog_ops, 4271 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4272 .pot_clear = mv88e6xxx_g2_pot_clear, 4273 .reset = mv88e6352_g1_reset, 4274 .rmu_disable = mv88e6390_g1_rmu_disable, 4275 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4276 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4277 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4278 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4279 .serdes_power = mv88e6390_serdes_power, 4280 .serdes_get_lane = mv88e6390_serdes_get_lane, 4281 /* Check status register pause & lpa register */ 4282 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4283 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4284 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4285 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4286 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4287 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4288 .serdes_irq_status = mv88e6390_serdes_irq_status, 4289 .serdes_get_strings = mv88e6390_serdes_get_strings, 4290 .serdes_get_stats = mv88e6390_serdes_get_stats, 4291 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4292 .serdes_get_regs = mv88e6390_serdes_get_regs, 4293 .avb_ops = &mv88e6390_avb_ops, 4294 .ptp_ops = &mv88e6352_ptp_ops, 4295 .phylink_validate = mv88e6390_phylink_validate, 4296 }; 4297 4298 static const struct mv88e6xxx_ops mv88e6240_ops = { 4299 /* MV88E6XXX_FAMILY_6352 */ 4300 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4301 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4302 .irl_init_all = mv88e6352_g2_irl_init_all, 4303 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4304 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4305 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4306 .phy_read = mv88e6xxx_g2_smi_phy_read, 4307 .phy_write = mv88e6xxx_g2_smi_phy_write, 4308 .port_set_link = mv88e6xxx_port_set_link, 4309 .port_sync_link = mv88e6xxx_port_sync_link, 4310 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4311 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4312 .port_tag_remap = mv88e6095_port_tag_remap, 4313 .port_set_policy = mv88e6352_port_set_policy, 4314 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4315 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4316 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4317 .port_set_ether_type = mv88e6351_port_set_ether_type, 4318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4320 .port_pause_limit = mv88e6097_port_pause_limit, 4321 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4322 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4323 .port_get_cmode = mv88e6352_port_get_cmode, 4324 .port_setup_message_port = mv88e6xxx_setup_message_port, 4325 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4326 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4327 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4328 .stats_get_strings = mv88e6095_stats_get_strings, 4329 .stats_get_stats = mv88e6095_stats_get_stats, 4330 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4331 .set_egress_port = mv88e6095_g1_set_egress_port, 4332 .watchdog_ops = &mv88e6097_watchdog_ops, 4333 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4334 .pot_clear = mv88e6xxx_g2_pot_clear, 4335 .reset = mv88e6352_g1_reset, 4336 .rmu_disable = mv88e6352_g1_rmu_disable, 4337 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4338 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4339 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4340 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4341 .serdes_get_lane = mv88e6352_serdes_get_lane, 4342 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4343 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4344 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4345 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4346 .serdes_power = mv88e6352_serdes_power, 4347 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4348 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4349 .serdes_irq_status = mv88e6352_serdes_irq_status, 4350 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4351 .serdes_get_regs = mv88e6352_serdes_get_regs, 4352 .gpio_ops = &mv88e6352_gpio_ops, 4353 .avb_ops = &mv88e6352_avb_ops, 4354 .ptp_ops = &mv88e6352_ptp_ops, 4355 .phylink_validate = mv88e6352_phylink_validate, 4356 }; 4357 4358 static const struct mv88e6xxx_ops mv88e6250_ops = { 4359 /* MV88E6XXX_FAMILY_6250 */ 4360 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4361 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4362 .irl_init_all = mv88e6352_g2_irl_init_all, 4363 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4364 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4365 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4366 .phy_read = mv88e6xxx_g2_smi_phy_read, 4367 .phy_write = mv88e6xxx_g2_smi_phy_write, 4368 .port_set_link = mv88e6xxx_port_set_link, 4369 .port_sync_link = mv88e6xxx_port_sync_link, 4370 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4371 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4372 .port_tag_remap = mv88e6095_port_tag_remap, 4373 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4376 .port_set_ether_type = mv88e6351_port_set_ether_type, 4377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4378 .port_pause_limit = mv88e6097_port_pause_limit, 4379 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4380 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4381 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4382 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4383 .stats_get_strings = mv88e6250_stats_get_strings, 4384 .stats_get_stats = mv88e6250_stats_get_stats, 4385 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4386 .set_egress_port = mv88e6095_g1_set_egress_port, 4387 .watchdog_ops = &mv88e6250_watchdog_ops, 4388 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4389 .pot_clear = mv88e6xxx_g2_pot_clear, 4390 .reset = mv88e6250_g1_reset, 4391 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4392 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4393 .avb_ops = &mv88e6352_avb_ops, 4394 .ptp_ops = &mv88e6250_ptp_ops, 4395 .phylink_validate = mv88e6065_phylink_validate, 4396 }; 4397 4398 static const struct mv88e6xxx_ops mv88e6290_ops = { 4399 /* MV88E6XXX_FAMILY_6390 */ 4400 .setup_errata = mv88e6390_setup_errata, 4401 .irl_init_all = mv88e6390_g2_irl_init_all, 4402 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4403 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4405 .phy_read = mv88e6xxx_g2_smi_phy_read, 4406 .phy_write = mv88e6xxx_g2_smi_phy_write, 4407 .port_set_link = mv88e6xxx_port_set_link, 4408 .port_sync_link = mv88e6xxx_port_sync_link, 4409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4410 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4411 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4412 .port_tag_remap = mv88e6390_port_tag_remap, 4413 .port_set_policy = mv88e6352_port_set_policy, 4414 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4415 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4416 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4417 .port_set_ether_type = mv88e6351_port_set_ether_type, 4418 .port_pause_limit = mv88e6390_port_pause_limit, 4419 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4420 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4421 .port_get_cmode = mv88e6352_port_get_cmode, 4422 .port_set_cmode = mv88e6390_port_set_cmode, 4423 .port_setup_message_port = mv88e6xxx_setup_message_port, 4424 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4425 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4426 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4427 .stats_get_strings = mv88e6320_stats_get_strings, 4428 .stats_get_stats = mv88e6390_stats_get_stats, 4429 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4430 .set_egress_port = mv88e6390_g1_set_egress_port, 4431 .watchdog_ops = &mv88e6390_watchdog_ops, 4432 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4433 .pot_clear = mv88e6xxx_g2_pot_clear, 4434 .reset = mv88e6352_g1_reset, 4435 .rmu_disable = mv88e6390_g1_rmu_disable, 4436 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4437 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4438 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4439 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4440 .serdes_power = mv88e6390_serdes_power, 4441 .serdes_get_lane = mv88e6390_serdes_get_lane, 4442 /* Check status register pause & lpa register */ 4443 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4444 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4445 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4446 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4447 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4448 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4449 .serdes_irq_status = mv88e6390_serdes_irq_status, 4450 .serdes_get_strings = mv88e6390_serdes_get_strings, 4451 .serdes_get_stats = mv88e6390_serdes_get_stats, 4452 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4453 .serdes_get_regs = mv88e6390_serdes_get_regs, 4454 .gpio_ops = &mv88e6352_gpio_ops, 4455 .avb_ops = &mv88e6390_avb_ops, 4456 .ptp_ops = &mv88e6352_ptp_ops, 4457 .phylink_validate = mv88e6390_phylink_validate, 4458 }; 4459 4460 static const struct mv88e6xxx_ops mv88e6320_ops = { 4461 /* MV88E6XXX_FAMILY_6320 */ 4462 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4463 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4464 .irl_init_all = mv88e6352_g2_irl_init_all, 4465 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4466 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4468 .phy_read = mv88e6xxx_g2_smi_phy_read, 4469 .phy_write = mv88e6xxx_g2_smi_phy_write, 4470 .port_set_link = mv88e6xxx_port_set_link, 4471 .port_sync_link = mv88e6xxx_port_sync_link, 4472 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4473 .port_tag_remap = mv88e6095_port_tag_remap, 4474 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4475 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4476 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4477 .port_set_ether_type = mv88e6351_port_set_ether_type, 4478 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4479 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4480 .port_pause_limit = mv88e6097_port_pause_limit, 4481 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4482 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4483 .port_get_cmode = mv88e6352_port_get_cmode, 4484 .port_setup_message_port = mv88e6xxx_setup_message_port, 4485 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4486 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4487 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4488 .stats_get_strings = mv88e6320_stats_get_strings, 4489 .stats_get_stats = mv88e6320_stats_get_stats, 4490 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4491 .set_egress_port = mv88e6095_g1_set_egress_port, 4492 .watchdog_ops = &mv88e6390_watchdog_ops, 4493 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4494 .pot_clear = mv88e6xxx_g2_pot_clear, 4495 .reset = mv88e6352_g1_reset, 4496 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4497 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4498 .gpio_ops = &mv88e6352_gpio_ops, 4499 .avb_ops = &mv88e6352_avb_ops, 4500 .ptp_ops = &mv88e6352_ptp_ops, 4501 .phylink_validate = mv88e6185_phylink_validate, 4502 }; 4503 4504 static const struct mv88e6xxx_ops mv88e6321_ops = { 4505 /* MV88E6XXX_FAMILY_6320 */ 4506 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4507 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4508 .irl_init_all = mv88e6352_g2_irl_init_all, 4509 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4510 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4511 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4512 .phy_read = mv88e6xxx_g2_smi_phy_read, 4513 .phy_write = mv88e6xxx_g2_smi_phy_write, 4514 .port_set_link = mv88e6xxx_port_set_link, 4515 .port_sync_link = mv88e6xxx_port_sync_link, 4516 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4517 .port_tag_remap = mv88e6095_port_tag_remap, 4518 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4519 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4520 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4521 .port_set_ether_type = mv88e6351_port_set_ether_type, 4522 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4523 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4524 .port_pause_limit = mv88e6097_port_pause_limit, 4525 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4526 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4527 .port_get_cmode = mv88e6352_port_get_cmode, 4528 .port_setup_message_port = mv88e6xxx_setup_message_port, 4529 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4530 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4531 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4532 .stats_get_strings = mv88e6320_stats_get_strings, 4533 .stats_get_stats = mv88e6320_stats_get_stats, 4534 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4535 .set_egress_port = mv88e6095_g1_set_egress_port, 4536 .watchdog_ops = &mv88e6390_watchdog_ops, 4537 .reset = mv88e6352_g1_reset, 4538 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4539 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4540 .gpio_ops = &mv88e6352_gpio_ops, 4541 .avb_ops = &mv88e6352_avb_ops, 4542 .ptp_ops = &mv88e6352_ptp_ops, 4543 .phylink_validate = mv88e6185_phylink_validate, 4544 }; 4545 4546 static const struct mv88e6xxx_ops mv88e6341_ops = { 4547 /* MV88E6XXX_FAMILY_6341 */ 4548 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4549 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4550 .irl_init_all = mv88e6352_g2_irl_init_all, 4551 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4552 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4553 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4554 .phy_read = mv88e6xxx_g2_smi_phy_read, 4555 .phy_write = mv88e6xxx_g2_smi_phy_write, 4556 .port_set_link = mv88e6xxx_port_set_link, 4557 .port_sync_link = mv88e6xxx_port_sync_link, 4558 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4559 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4560 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4561 .port_tag_remap = mv88e6095_port_tag_remap, 4562 .port_set_policy = mv88e6352_port_set_policy, 4563 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4564 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4565 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4566 .port_set_ether_type = mv88e6351_port_set_ether_type, 4567 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4568 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4569 .port_pause_limit = mv88e6097_port_pause_limit, 4570 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4571 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4572 .port_get_cmode = mv88e6352_port_get_cmode, 4573 .port_set_cmode = mv88e6341_port_set_cmode, 4574 .port_setup_message_port = mv88e6xxx_setup_message_port, 4575 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4576 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4577 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4578 .stats_get_strings = mv88e6320_stats_get_strings, 4579 .stats_get_stats = mv88e6390_stats_get_stats, 4580 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4581 .set_egress_port = mv88e6390_g1_set_egress_port, 4582 .watchdog_ops = &mv88e6390_watchdog_ops, 4583 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4584 .pot_clear = mv88e6xxx_g2_pot_clear, 4585 .reset = mv88e6352_g1_reset, 4586 .rmu_disable = mv88e6390_g1_rmu_disable, 4587 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4588 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4589 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4591 .serdes_power = mv88e6390_serdes_power, 4592 .serdes_get_lane = mv88e6341_serdes_get_lane, 4593 /* Check status register pause & lpa register */ 4594 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4595 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4596 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4597 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4598 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4599 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4600 .serdes_irq_status = mv88e6390_serdes_irq_status, 4601 .gpio_ops = &mv88e6352_gpio_ops, 4602 .avb_ops = &mv88e6390_avb_ops, 4603 .ptp_ops = &mv88e6352_ptp_ops, 4604 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4605 .serdes_get_strings = mv88e6390_serdes_get_strings, 4606 .serdes_get_stats = mv88e6390_serdes_get_stats, 4607 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4608 .serdes_get_regs = mv88e6390_serdes_get_regs, 4609 .phylink_validate = mv88e6341_phylink_validate, 4610 }; 4611 4612 static const struct mv88e6xxx_ops mv88e6350_ops = { 4613 /* MV88E6XXX_FAMILY_6351 */ 4614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4615 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4616 .irl_init_all = mv88e6352_g2_irl_init_all, 4617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4618 .phy_read = mv88e6xxx_g2_smi_phy_read, 4619 .phy_write = mv88e6xxx_g2_smi_phy_write, 4620 .port_set_link = mv88e6xxx_port_set_link, 4621 .port_sync_link = mv88e6xxx_port_sync_link, 4622 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4623 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4624 .port_tag_remap = mv88e6095_port_tag_remap, 4625 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4626 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4627 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4628 .port_set_ether_type = mv88e6351_port_set_ether_type, 4629 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4630 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4631 .port_pause_limit = mv88e6097_port_pause_limit, 4632 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4633 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4634 .port_get_cmode = mv88e6352_port_get_cmode, 4635 .port_setup_message_port = mv88e6xxx_setup_message_port, 4636 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4637 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4638 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4639 .stats_get_strings = mv88e6095_stats_get_strings, 4640 .stats_get_stats = mv88e6095_stats_get_stats, 4641 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4642 .set_egress_port = mv88e6095_g1_set_egress_port, 4643 .watchdog_ops = &mv88e6097_watchdog_ops, 4644 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4645 .pot_clear = mv88e6xxx_g2_pot_clear, 4646 .reset = mv88e6352_g1_reset, 4647 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4648 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4649 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4650 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4651 .phylink_validate = mv88e6185_phylink_validate, 4652 }; 4653 4654 static const struct mv88e6xxx_ops mv88e6351_ops = { 4655 /* MV88E6XXX_FAMILY_6351 */ 4656 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4657 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4658 .irl_init_all = mv88e6352_g2_irl_init_all, 4659 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4660 .phy_read = mv88e6xxx_g2_smi_phy_read, 4661 .phy_write = mv88e6xxx_g2_smi_phy_write, 4662 .port_set_link = mv88e6xxx_port_set_link, 4663 .port_sync_link = mv88e6xxx_port_sync_link, 4664 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4665 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4666 .port_tag_remap = mv88e6095_port_tag_remap, 4667 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4668 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4669 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4670 .port_set_ether_type = mv88e6351_port_set_ether_type, 4671 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4672 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4673 .port_pause_limit = mv88e6097_port_pause_limit, 4674 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4675 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4676 .port_get_cmode = mv88e6352_port_get_cmode, 4677 .port_setup_message_port = mv88e6xxx_setup_message_port, 4678 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4680 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4681 .stats_get_strings = mv88e6095_stats_get_strings, 4682 .stats_get_stats = mv88e6095_stats_get_stats, 4683 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4684 .set_egress_port = mv88e6095_g1_set_egress_port, 4685 .watchdog_ops = &mv88e6097_watchdog_ops, 4686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4687 .pot_clear = mv88e6xxx_g2_pot_clear, 4688 .reset = mv88e6352_g1_reset, 4689 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4690 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4691 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4693 .avb_ops = &mv88e6352_avb_ops, 4694 .ptp_ops = &mv88e6352_ptp_ops, 4695 .phylink_validate = mv88e6185_phylink_validate, 4696 }; 4697 4698 static const struct mv88e6xxx_ops mv88e6352_ops = { 4699 /* MV88E6XXX_FAMILY_6352 */ 4700 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4701 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4702 .irl_init_all = mv88e6352_g2_irl_init_all, 4703 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4704 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4705 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4706 .phy_read = mv88e6xxx_g2_smi_phy_read, 4707 .phy_write = mv88e6xxx_g2_smi_phy_write, 4708 .port_set_link = mv88e6xxx_port_set_link, 4709 .port_sync_link = mv88e6xxx_port_sync_link, 4710 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4711 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4712 .port_tag_remap = mv88e6095_port_tag_remap, 4713 .port_set_policy = mv88e6352_port_set_policy, 4714 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4715 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4716 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4717 .port_set_ether_type = mv88e6351_port_set_ether_type, 4718 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4719 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4720 .port_pause_limit = mv88e6097_port_pause_limit, 4721 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4722 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4723 .port_get_cmode = mv88e6352_port_get_cmode, 4724 .port_setup_message_port = mv88e6xxx_setup_message_port, 4725 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4726 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4727 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4728 .stats_get_strings = mv88e6095_stats_get_strings, 4729 .stats_get_stats = mv88e6095_stats_get_stats, 4730 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4731 .set_egress_port = mv88e6095_g1_set_egress_port, 4732 .watchdog_ops = &mv88e6097_watchdog_ops, 4733 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4734 .pot_clear = mv88e6xxx_g2_pot_clear, 4735 .reset = mv88e6352_g1_reset, 4736 .rmu_disable = mv88e6352_g1_rmu_disable, 4737 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4738 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4739 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4740 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4741 .serdes_get_lane = mv88e6352_serdes_get_lane, 4742 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4743 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4744 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4745 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4746 .serdes_power = mv88e6352_serdes_power, 4747 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4748 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4749 .serdes_irq_status = mv88e6352_serdes_irq_status, 4750 .gpio_ops = &mv88e6352_gpio_ops, 4751 .avb_ops = &mv88e6352_avb_ops, 4752 .ptp_ops = &mv88e6352_ptp_ops, 4753 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4754 .serdes_get_strings = mv88e6352_serdes_get_strings, 4755 .serdes_get_stats = mv88e6352_serdes_get_stats, 4756 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4757 .serdes_get_regs = mv88e6352_serdes_get_regs, 4758 .phylink_validate = mv88e6352_phylink_validate, 4759 }; 4760 4761 static const struct mv88e6xxx_ops mv88e6390_ops = { 4762 /* MV88E6XXX_FAMILY_6390 */ 4763 .setup_errata = mv88e6390_setup_errata, 4764 .irl_init_all = mv88e6390_g2_irl_init_all, 4765 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4766 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4767 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4768 .phy_read = mv88e6xxx_g2_smi_phy_read, 4769 .phy_write = mv88e6xxx_g2_smi_phy_write, 4770 .port_set_link = mv88e6xxx_port_set_link, 4771 .port_sync_link = mv88e6xxx_port_sync_link, 4772 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4773 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4774 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4775 .port_tag_remap = mv88e6390_port_tag_remap, 4776 .port_set_policy = mv88e6352_port_set_policy, 4777 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4778 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4779 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4780 .port_set_ether_type = mv88e6351_port_set_ether_type, 4781 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4782 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4783 .port_pause_limit = mv88e6390_port_pause_limit, 4784 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4785 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4786 .port_get_cmode = mv88e6352_port_get_cmode, 4787 .port_set_cmode = mv88e6390_port_set_cmode, 4788 .port_setup_message_port = mv88e6xxx_setup_message_port, 4789 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4790 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4791 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4792 .stats_get_strings = mv88e6320_stats_get_strings, 4793 .stats_get_stats = mv88e6390_stats_get_stats, 4794 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4795 .set_egress_port = mv88e6390_g1_set_egress_port, 4796 .watchdog_ops = &mv88e6390_watchdog_ops, 4797 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4798 .pot_clear = mv88e6xxx_g2_pot_clear, 4799 .reset = mv88e6352_g1_reset, 4800 .rmu_disable = mv88e6390_g1_rmu_disable, 4801 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4802 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4803 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4804 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4805 .serdes_power = mv88e6390_serdes_power, 4806 .serdes_get_lane = mv88e6390_serdes_get_lane, 4807 /* Check status register pause & lpa register */ 4808 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4809 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4810 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4811 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4812 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4813 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4814 .serdes_irq_status = mv88e6390_serdes_irq_status, 4815 .gpio_ops = &mv88e6352_gpio_ops, 4816 .avb_ops = &mv88e6390_avb_ops, 4817 .ptp_ops = &mv88e6352_ptp_ops, 4818 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4819 .serdes_get_strings = mv88e6390_serdes_get_strings, 4820 .serdes_get_stats = mv88e6390_serdes_get_stats, 4821 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4822 .serdes_get_regs = mv88e6390_serdes_get_regs, 4823 .phylink_validate = mv88e6390_phylink_validate, 4824 }; 4825 4826 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4827 /* MV88E6XXX_FAMILY_6390 */ 4828 .setup_errata = mv88e6390_setup_errata, 4829 .irl_init_all = mv88e6390_g2_irl_init_all, 4830 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4831 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4832 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4833 .phy_read = mv88e6xxx_g2_smi_phy_read, 4834 .phy_write = mv88e6xxx_g2_smi_phy_write, 4835 .port_set_link = mv88e6xxx_port_set_link, 4836 .port_sync_link = mv88e6xxx_port_sync_link, 4837 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4838 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4839 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4840 .port_tag_remap = mv88e6390_port_tag_remap, 4841 .port_set_policy = mv88e6352_port_set_policy, 4842 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4843 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4844 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4845 .port_set_ether_type = mv88e6351_port_set_ether_type, 4846 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4847 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4848 .port_pause_limit = mv88e6390_port_pause_limit, 4849 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4850 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4851 .port_get_cmode = mv88e6352_port_get_cmode, 4852 .port_set_cmode = mv88e6390x_port_set_cmode, 4853 .port_setup_message_port = mv88e6xxx_setup_message_port, 4854 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4855 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4856 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4857 .stats_get_strings = mv88e6320_stats_get_strings, 4858 .stats_get_stats = mv88e6390_stats_get_stats, 4859 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4860 .set_egress_port = mv88e6390_g1_set_egress_port, 4861 .watchdog_ops = &mv88e6390_watchdog_ops, 4862 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4863 .pot_clear = mv88e6xxx_g2_pot_clear, 4864 .reset = mv88e6352_g1_reset, 4865 .rmu_disable = mv88e6390_g1_rmu_disable, 4866 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4867 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4868 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4869 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4870 .serdes_power = mv88e6390_serdes_power, 4871 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4872 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4873 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4874 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4875 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4876 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4877 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4878 .serdes_irq_status = mv88e6390_serdes_irq_status, 4879 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4880 .serdes_get_strings = mv88e6390_serdes_get_strings, 4881 .serdes_get_stats = mv88e6390_serdes_get_stats, 4882 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4883 .serdes_get_regs = mv88e6390_serdes_get_regs, 4884 .gpio_ops = &mv88e6352_gpio_ops, 4885 .avb_ops = &mv88e6390_avb_ops, 4886 .ptp_ops = &mv88e6352_ptp_ops, 4887 .phylink_validate = mv88e6390x_phylink_validate, 4888 }; 4889 4890 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4891 /* MV88E6XXX_FAMILY_6393 */ 4892 .setup_errata = mv88e6393x_serdes_setup_errata, 4893 .irl_init_all = mv88e6390_g2_irl_init_all, 4894 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4895 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4896 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4897 .phy_read = mv88e6xxx_g2_smi_phy_read, 4898 .phy_write = mv88e6xxx_g2_smi_phy_write, 4899 .port_set_link = mv88e6xxx_port_set_link, 4900 .port_sync_link = mv88e6xxx_port_sync_link, 4901 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4902 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4903 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4904 .port_tag_remap = mv88e6390_port_tag_remap, 4905 .port_set_policy = mv88e6393x_port_set_policy, 4906 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4907 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4908 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4909 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4910 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4911 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4912 .port_pause_limit = mv88e6390_port_pause_limit, 4913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4915 .port_get_cmode = mv88e6352_port_get_cmode, 4916 .port_set_cmode = mv88e6393x_port_set_cmode, 4917 .port_setup_message_port = mv88e6xxx_setup_message_port, 4918 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4919 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4920 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4921 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4922 .stats_get_strings = mv88e6320_stats_get_strings, 4923 .stats_get_stats = mv88e6390_stats_get_stats, 4924 /* .set_cpu_port is missing because this family does not support a global 4925 * CPU port, only per port CPU port which is set via 4926 * .port_set_upstream_port method. 4927 */ 4928 .set_egress_port = mv88e6393x_set_egress_port, 4929 .watchdog_ops = &mv88e6390_watchdog_ops, 4930 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4931 .pot_clear = mv88e6xxx_g2_pot_clear, 4932 .reset = mv88e6352_g1_reset, 4933 .rmu_disable = mv88e6390_g1_rmu_disable, 4934 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4935 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4936 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4937 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4938 .serdes_power = mv88e6393x_serdes_power, 4939 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4940 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4941 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4942 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4943 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4944 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4945 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4946 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4947 /* TODO: serdes stats */ 4948 .gpio_ops = &mv88e6352_gpio_ops, 4949 .avb_ops = &mv88e6390_avb_ops, 4950 .ptp_ops = &mv88e6352_ptp_ops, 4951 .phylink_validate = mv88e6393x_phylink_validate, 4952 }; 4953 4954 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4955 [MV88E6085] = { 4956 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4957 .family = MV88E6XXX_FAMILY_6097, 4958 .name = "Marvell 88E6085", 4959 .num_databases = 4096, 4960 .num_macs = 8192, 4961 .num_ports = 10, 4962 .num_internal_phys = 5, 4963 .max_vid = 4095, 4964 .port_base_addr = 0x10, 4965 .phy_base_addr = 0x0, 4966 .global1_addr = 0x1b, 4967 .global2_addr = 0x1c, 4968 .age_time_coeff = 15000, 4969 .g1_irqs = 8, 4970 .g2_irqs = 10, 4971 .atu_move_port_mask = 0xf, 4972 .pvt = true, 4973 .multi_chip = true, 4974 .ops = &mv88e6085_ops, 4975 }, 4976 4977 [MV88E6095] = { 4978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4979 .family = MV88E6XXX_FAMILY_6095, 4980 .name = "Marvell 88E6095/88E6095F", 4981 .num_databases = 256, 4982 .num_macs = 8192, 4983 .num_ports = 11, 4984 .num_internal_phys = 0, 4985 .max_vid = 4095, 4986 .port_base_addr = 0x10, 4987 .phy_base_addr = 0x0, 4988 .global1_addr = 0x1b, 4989 .global2_addr = 0x1c, 4990 .age_time_coeff = 15000, 4991 .g1_irqs = 8, 4992 .atu_move_port_mask = 0xf, 4993 .multi_chip = true, 4994 .ops = &mv88e6095_ops, 4995 }, 4996 4997 [MV88E6097] = { 4998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4999 .family = MV88E6XXX_FAMILY_6097, 5000 .name = "Marvell 88E6097/88E6097F", 5001 .num_databases = 4096, 5002 .num_macs = 8192, 5003 .num_ports = 11, 5004 .num_internal_phys = 8, 5005 .max_vid = 4095, 5006 .port_base_addr = 0x10, 5007 .phy_base_addr = 0x0, 5008 .global1_addr = 0x1b, 5009 .global2_addr = 0x1c, 5010 .age_time_coeff = 15000, 5011 .g1_irqs = 8, 5012 .g2_irqs = 10, 5013 .atu_move_port_mask = 0xf, 5014 .pvt = true, 5015 .multi_chip = true, 5016 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5017 .ops = &mv88e6097_ops, 5018 }, 5019 5020 [MV88E6123] = { 5021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5022 .family = MV88E6XXX_FAMILY_6165, 5023 .name = "Marvell 88E6123", 5024 .num_databases = 4096, 5025 .num_macs = 1024, 5026 .num_ports = 3, 5027 .num_internal_phys = 5, 5028 .max_vid = 4095, 5029 .port_base_addr = 0x10, 5030 .phy_base_addr = 0x0, 5031 .global1_addr = 0x1b, 5032 .global2_addr = 0x1c, 5033 .age_time_coeff = 15000, 5034 .g1_irqs = 9, 5035 .g2_irqs = 10, 5036 .atu_move_port_mask = 0xf, 5037 .pvt = true, 5038 .multi_chip = true, 5039 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5040 .ops = &mv88e6123_ops, 5041 }, 5042 5043 [MV88E6131] = { 5044 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5045 .family = MV88E6XXX_FAMILY_6185, 5046 .name = "Marvell 88E6131", 5047 .num_databases = 256, 5048 .num_macs = 8192, 5049 .num_ports = 8, 5050 .num_internal_phys = 0, 5051 .max_vid = 4095, 5052 .port_base_addr = 0x10, 5053 .phy_base_addr = 0x0, 5054 .global1_addr = 0x1b, 5055 .global2_addr = 0x1c, 5056 .age_time_coeff = 15000, 5057 .g1_irqs = 9, 5058 .atu_move_port_mask = 0xf, 5059 .multi_chip = true, 5060 .ops = &mv88e6131_ops, 5061 }, 5062 5063 [MV88E6141] = { 5064 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5065 .family = MV88E6XXX_FAMILY_6341, 5066 .name = "Marvell 88E6141", 5067 .num_databases = 4096, 5068 .num_macs = 2048, 5069 .num_ports = 6, 5070 .num_internal_phys = 5, 5071 .num_gpio = 11, 5072 .max_vid = 4095, 5073 .port_base_addr = 0x10, 5074 .phy_base_addr = 0x10, 5075 .global1_addr = 0x1b, 5076 .global2_addr = 0x1c, 5077 .age_time_coeff = 3750, 5078 .atu_move_port_mask = 0x1f, 5079 .g1_irqs = 9, 5080 .g2_irqs = 10, 5081 .pvt = true, 5082 .multi_chip = true, 5083 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5084 .ops = &mv88e6141_ops, 5085 }, 5086 5087 [MV88E6161] = { 5088 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5089 .family = MV88E6XXX_FAMILY_6165, 5090 .name = "Marvell 88E6161", 5091 .num_databases = 4096, 5092 .num_macs = 1024, 5093 .num_ports = 6, 5094 .num_internal_phys = 5, 5095 .max_vid = 4095, 5096 .port_base_addr = 0x10, 5097 .phy_base_addr = 0x0, 5098 .global1_addr = 0x1b, 5099 .global2_addr = 0x1c, 5100 .age_time_coeff = 15000, 5101 .g1_irqs = 9, 5102 .g2_irqs = 10, 5103 .atu_move_port_mask = 0xf, 5104 .pvt = true, 5105 .multi_chip = true, 5106 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5107 .ptp_support = true, 5108 .ops = &mv88e6161_ops, 5109 }, 5110 5111 [MV88E6165] = { 5112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5113 .family = MV88E6XXX_FAMILY_6165, 5114 .name = "Marvell 88E6165", 5115 .num_databases = 4096, 5116 .num_macs = 8192, 5117 .num_ports = 6, 5118 .num_internal_phys = 0, 5119 .max_vid = 4095, 5120 .port_base_addr = 0x10, 5121 .phy_base_addr = 0x0, 5122 .global1_addr = 0x1b, 5123 .global2_addr = 0x1c, 5124 .age_time_coeff = 15000, 5125 .g1_irqs = 9, 5126 .g2_irqs = 10, 5127 .atu_move_port_mask = 0xf, 5128 .pvt = true, 5129 .multi_chip = true, 5130 .ptp_support = true, 5131 .ops = &mv88e6165_ops, 5132 }, 5133 5134 [MV88E6171] = { 5135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5136 .family = MV88E6XXX_FAMILY_6351, 5137 .name = "Marvell 88E6171", 5138 .num_databases = 4096, 5139 .num_macs = 8192, 5140 .num_ports = 7, 5141 .num_internal_phys = 5, 5142 .max_vid = 4095, 5143 .port_base_addr = 0x10, 5144 .phy_base_addr = 0x0, 5145 .global1_addr = 0x1b, 5146 .global2_addr = 0x1c, 5147 .age_time_coeff = 15000, 5148 .g1_irqs = 9, 5149 .g2_irqs = 10, 5150 .atu_move_port_mask = 0xf, 5151 .pvt = true, 5152 .multi_chip = true, 5153 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5154 .ops = &mv88e6171_ops, 5155 }, 5156 5157 [MV88E6172] = { 5158 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5159 .family = MV88E6XXX_FAMILY_6352, 5160 .name = "Marvell 88E6172", 5161 .num_databases = 4096, 5162 .num_macs = 8192, 5163 .num_ports = 7, 5164 .num_internal_phys = 5, 5165 .num_gpio = 15, 5166 .max_vid = 4095, 5167 .port_base_addr = 0x10, 5168 .phy_base_addr = 0x0, 5169 .global1_addr = 0x1b, 5170 .global2_addr = 0x1c, 5171 .age_time_coeff = 15000, 5172 .g1_irqs = 9, 5173 .g2_irqs = 10, 5174 .atu_move_port_mask = 0xf, 5175 .pvt = true, 5176 .multi_chip = true, 5177 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5178 .ops = &mv88e6172_ops, 5179 }, 5180 5181 [MV88E6175] = { 5182 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5183 .family = MV88E6XXX_FAMILY_6351, 5184 .name = "Marvell 88E6175", 5185 .num_databases = 4096, 5186 .num_macs = 8192, 5187 .num_ports = 7, 5188 .num_internal_phys = 5, 5189 .max_vid = 4095, 5190 .port_base_addr = 0x10, 5191 .phy_base_addr = 0x0, 5192 .global1_addr = 0x1b, 5193 .global2_addr = 0x1c, 5194 .age_time_coeff = 15000, 5195 .g1_irqs = 9, 5196 .g2_irqs = 10, 5197 .atu_move_port_mask = 0xf, 5198 .pvt = true, 5199 .multi_chip = true, 5200 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5201 .ops = &mv88e6175_ops, 5202 }, 5203 5204 [MV88E6176] = { 5205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5206 .family = MV88E6XXX_FAMILY_6352, 5207 .name = "Marvell 88E6176", 5208 .num_databases = 4096, 5209 .num_macs = 8192, 5210 .num_ports = 7, 5211 .num_internal_phys = 5, 5212 .num_gpio = 15, 5213 .max_vid = 4095, 5214 .port_base_addr = 0x10, 5215 .phy_base_addr = 0x0, 5216 .global1_addr = 0x1b, 5217 .global2_addr = 0x1c, 5218 .age_time_coeff = 15000, 5219 .g1_irqs = 9, 5220 .g2_irqs = 10, 5221 .atu_move_port_mask = 0xf, 5222 .pvt = true, 5223 .multi_chip = true, 5224 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5225 .ops = &mv88e6176_ops, 5226 }, 5227 5228 [MV88E6185] = { 5229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5230 .family = MV88E6XXX_FAMILY_6185, 5231 .name = "Marvell 88E6185", 5232 .num_databases = 256, 5233 .num_macs = 8192, 5234 .num_ports = 10, 5235 .num_internal_phys = 0, 5236 .max_vid = 4095, 5237 .port_base_addr = 0x10, 5238 .phy_base_addr = 0x0, 5239 .global1_addr = 0x1b, 5240 .global2_addr = 0x1c, 5241 .age_time_coeff = 15000, 5242 .g1_irqs = 8, 5243 .atu_move_port_mask = 0xf, 5244 .multi_chip = true, 5245 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5246 .ops = &mv88e6185_ops, 5247 }, 5248 5249 [MV88E6190] = { 5250 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5251 .family = MV88E6XXX_FAMILY_6390, 5252 .name = "Marvell 88E6190", 5253 .num_databases = 4096, 5254 .num_macs = 16384, 5255 .num_ports = 11, /* 10 + Z80 */ 5256 .num_internal_phys = 9, 5257 .num_gpio = 16, 5258 .max_vid = 8191, 5259 .port_base_addr = 0x0, 5260 .phy_base_addr = 0x0, 5261 .global1_addr = 0x1b, 5262 .global2_addr = 0x1c, 5263 .age_time_coeff = 3750, 5264 .g1_irqs = 9, 5265 .g2_irqs = 14, 5266 .pvt = true, 5267 .multi_chip = true, 5268 .atu_move_port_mask = 0x1f, 5269 .ops = &mv88e6190_ops, 5270 }, 5271 5272 [MV88E6190X] = { 5273 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5274 .family = MV88E6XXX_FAMILY_6390, 5275 .name = "Marvell 88E6190X", 5276 .num_databases = 4096, 5277 .num_macs = 16384, 5278 .num_ports = 11, /* 10 + Z80 */ 5279 .num_internal_phys = 9, 5280 .num_gpio = 16, 5281 .max_vid = 8191, 5282 .port_base_addr = 0x0, 5283 .phy_base_addr = 0x0, 5284 .global1_addr = 0x1b, 5285 .global2_addr = 0x1c, 5286 .age_time_coeff = 3750, 5287 .g1_irqs = 9, 5288 .g2_irqs = 14, 5289 .atu_move_port_mask = 0x1f, 5290 .pvt = true, 5291 .multi_chip = true, 5292 .ops = &mv88e6190x_ops, 5293 }, 5294 5295 [MV88E6191] = { 5296 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5297 .family = MV88E6XXX_FAMILY_6390, 5298 .name = "Marvell 88E6191", 5299 .num_databases = 4096, 5300 .num_macs = 16384, 5301 .num_ports = 11, /* 10 + Z80 */ 5302 .num_internal_phys = 9, 5303 .max_vid = 8191, 5304 .port_base_addr = 0x0, 5305 .phy_base_addr = 0x0, 5306 .global1_addr = 0x1b, 5307 .global2_addr = 0x1c, 5308 .age_time_coeff = 3750, 5309 .g1_irqs = 9, 5310 .g2_irqs = 14, 5311 .atu_move_port_mask = 0x1f, 5312 .pvt = true, 5313 .multi_chip = true, 5314 .ptp_support = true, 5315 .ops = &mv88e6191_ops, 5316 }, 5317 5318 [MV88E6191X] = { 5319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5320 .family = MV88E6XXX_FAMILY_6393, 5321 .name = "Marvell 88E6191X", 5322 .num_databases = 4096, 5323 .num_ports = 11, /* 10 + Z80 */ 5324 .num_internal_phys = 9, 5325 .max_vid = 8191, 5326 .port_base_addr = 0x0, 5327 .phy_base_addr = 0x0, 5328 .global1_addr = 0x1b, 5329 .global2_addr = 0x1c, 5330 .age_time_coeff = 3750, 5331 .g1_irqs = 10, 5332 .g2_irqs = 14, 5333 .atu_move_port_mask = 0x1f, 5334 .pvt = true, 5335 .multi_chip = true, 5336 .ptp_support = true, 5337 .ops = &mv88e6393x_ops, 5338 }, 5339 5340 [MV88E6193X] = { 5341 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5342 .family = MV88E6XXX_FAMILY_6393, 5343 .name = "Marvell 88E6193X", 5344 .num_databases = 4096, 5345 .num_ports = 11, /* 10 + Z80 */ 5346 .num_internal_phys = 9, 5347 .max_vid = 8191, 5348 .port_base_addr = 0x0, 5349 .phy_base_addr = 0x0, 5350 .global1_addr = 0x1b, 5351 .global2_addr = 0x1c, 5352 .age_time_coeff = 3750, 5353 .g1_irqs = 10, 5354 .g2_irqs = 14, 5355 .atu_move_port_mask = 0x1f, 5356 .pvt = true, 5357 .multi_chip = true, 5358 .ptp_support = true, 5359 .ops = &mv88e6393x_ops, 5360 }, 5361 5362 [MV88E6220] = { 5363 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5364 .family = MV88E6XXX_FAMILY_6250, 5365 .name = "Marvell 88E6220", 5366 .num_databases = 64, 5367 5368 /* Ports 2-4 are not routed to pins 5369 * => usable ports 0, 1, 5, 6 5370 */ 5371 .num_ports = 7, 5372 .num_internal_phys = 2, 5373 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5374 .max_vid = 4095, 5375 .port_base_addr = 0x08, 5376 .phy_base_addr = 0x00, 5377 .global1_addr = 0x0f, 5378 .global2_addr = 0x07, 5379 .age_time_coeff = 15000, 5380 .g1_irqs = 9, 5381 .g2_irqs = 10, 5382 .atu_move_port_mask = 0xf, 5383 .dual_chip = true, 5384 .ptp_support = true, 5385 .ops = &mv88e6250_ops, 5386 }, 5387 5388 [MV88E6240] = { 5389 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5390 .family = MV88E6XXX_FAMILY_6352, 5391 .name = "Marvell 88E6240", 5392 .num_databases = 4096, 5393 .num_macs = 8192, 5394 .num_ports = 7, 5395 .num_internal_phys = 5, 5396 .num_gpio = 15, 5397 .max_vid = 4095, 5398 .port_base_addr = 0x10, 5399 .phy_base_addr = 0x0, 5400 .global1_addr = 0x1b, 5401 .global2_addr = 0x1c, 5402 .age_time_coeff = 15000, 5403 .g1_irqs = 9, 5404 .g2_irqs = 10, 5405 .atu_move_port_mask = 0xf, 5406 .pvt = true, 5407 .multi_chip = true, 5408 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5409 .ptp_support = true, 5410 .ops = &mv88e6240_ops, 5411 }, 5412 5413 [MV88E6250] = { 5414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5415 .family = MV88E6XXX_FAMILY_6250, 5416 .name = "Marvell 88E6250", 5417 .num_databases = 64, 5418 .num_ports = 7, 5419 .num_internal_phys = 5, 5420 .max_vid = 4095, 5421 .port_base_addr = 0x08, 5422 .phy_base_addr = 0x00, 5423 .global1_addr = 0x0f, 5424 .global2_addr = 0x07, 5425 .age_time_coeff = 15000, 5426 .g1_irqs = 9, 5427 .g2_irqs = 10, 5428 .atu_move_port_mask = 0xf, 5429 .dual_chip = true, 5430 .ptp_support = true, 5431 .ops = &mv88e6250_ops, 5432 }, 5433 5434 [MV88E6290] = { 5435 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5436 .family = MV88E6XXX_FAMILY_6390, 5437 .name = "Marvell 88E6290", 5438 .num_databases = 4096, 5439 .num_ports = 11, /* 10 + Z80 */ 5440 .num_internal_phys = 9, 5441 .num_gpio = 16, 5442 .max_vid = 8191, 5443 .port_base_addr = 0x0, 5444 .phy_base_addr = 0x0, 5445 .global1_addr = 0x1b, 5446 .global2_addr = 0x1c, 5447 .age_time_coeff = 3750, 5448 .g1_irqs = 9, 5449 .g2_irqs = 14, 5450 .atu_move_port_mask = 0x1f, 5451 .pvt = true, 5452 .multi_chip = true, 5453 .ptp_support = true, 5454 .ops = &mv88e6290_ops, 5455 }, 5456 5457 [MV88E6320] = { 5458 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5459 .family = MV88E6XXX_FAMILY_6320, 5460 .name = "Marvell 88E6320", 5461 .num_databases = 4096, 5462 .num_macs = 8192, 5463 .num_ports = 7, 5464 .num_internal_phys = 5, 5465 .num_gpio = 15, 5466 .max_vid = 4095, 5467 .port_base_addr = 0x10, 5468 .phy_base_addr = 0x0, 5469 .global1_addr = 0x1b, 5470 .global2_addr = 0x1c, 5471 .age_time_coeff = 15000, 5472 .g1_irqs = 8, 5473 .g2_irqs = 10, 5474 .atu_move_port_mask = 0xf, 5475 .pvt = true, 5476 .multi_chip = true, 5477 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5478 .ptp_support = true, 5479 .ops = &mv88e6320_ops, 5480 }, 5481 5482 [MV88E6321] = { 5483 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5484 .family = MV88E6XXX_FAMILY_6320, 5485 .name = "Marvell 88E6321", 5486 .num_databases = 4096, 5487 .num_macs = 8192, 5488 .num_ports = 7, 5489 .num_internal_phys = 5, 5490 .num_gpio = 15, 5491 .max_vid = 4095, 5492 .port_base_addr = 0x10, 5493 .phy_base_addr = 0x0, 5494 .global1_addr = 0x1b, 5495 .global2_addr = 0x1c, 5496 .age_time_coeff = 15000, 5497 .g1_irqs = 8, 5498 .g2_irqs = 10, 5499 .atu_move_port_mask = 0xf, 5500 .multi_chip = true, 5501 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5502 .ptp_support = true, 5503 .ops = &mv88e6321_ops, 5504 }, 5505 5506 [MV88E6341] = { 5507 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5508 .family = MV88E6XXX_FAMILY_6341, 5509 .name = "Marvell 88E6341", 5510 .num_databases = 4096, 5511 .num_macs = 2048, 5512 .num_internal_phys = 5, 5513 .num_ports = 6, 5514 .num_gpio = 11, 5515 .max_vid = 4095, 5516 .port_base_addr = 0x10, 5517 .phy_base_addr = 0x10, 5518 .global1_addr = 0x1b, 5519 .global2_addr = 0x1c, 5520 .age_time_coeff = 3750, 5521 .atu_move_port_mask = 0x1f, 5522 .g1_irqs = 9, 5523 .g2_irqs = 10, 5524 .pvt = true, 5525 .multi_chip = true, 5526 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5527 .ptp_support = true, 5528 .ops = &mv88e6341_ops, 5529 }, 5530 5531 [MV88E6350] = { 5532 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5533 .family = MV88E6XXX_FAMILY_6351, 5534 .name = "Marvell 88E6350", 5535 .num_databases = 4096, 5536 .num_macs = 8192, 5537 .num_ports = 7, 5538 .num_internal_phys = 5, 5539 .max_vid = 4095, 5540 .port_base_addr = 0x10, 5541 .phy_base_addr = 0x0, 5542 .global1_addr = 0x1b, 5543 .global2_addr = 0x1c, 5544 .age_time_coeff = 15000, 5545 .g1_irqs = 9, 5546 .g2_irqs = 10, 5547 .atu_move_port_mask = 0xf, 5548 .pvt = true, 5549 .multi_chip = true, 5550 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5551 .ops = &mv88e6350_ops, 5552 }, 5553 5554 [MV88E6351] = { 5555 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5556 .family = MV88E6XXX_FAMILY_6351, 5557 .name = "Marvell 88E6351", 5558 .num_databases = 4096, 5559 .num_macs = 8192, 5560 .num_ports = 7, 5561 .num_internal_phys = 5, 5562 .max_vid = 4095, 5563 .port_base_addr = 0x10, 5564 .phy_base_addr = 0x0, 5565 .global1_addr = 0x1b, 5566 .global2_addr = 0x1c, 5567 .age_time_coeff = 15000, 5568 .g1_irqs = 9, 5569 .g2_irqs = 10, 5570 .atu_move_port_mask = 0xf, 5571 .pvt = true, 5572 .multi_chip = true, 5573 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5574 .ops = &mv88e6351_ops, 5575 }, 5576 5577 [MV88E6352] = { 5578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5579 .family = MV88E6XXX_FAMILY_6352, 5580 .name = "Marvell 88E6352", 5581 .num_databases = 4096, 5582 .num_macs = 8192, 5583 .num_ports = 7, 5584 .num_internal_phys = 5, 5585 .num_gpio = 15, 5586 .max_vid = 4095, 5587 .port_base_addr = 0x10, 5588 .phy_base_addr = 0x0, 5589 .global1_addr = 0x1b, 5590 .global2_addr = 0x1c, 5591 .age_time_coeff = 15000, 5592 .g1_irqs = 9, 5593 .g2_irqs = 10, 5594 .atu_move_port_mask = 0xf, 5595 .pvt = true, 5596 .multi_chip = true, 5597 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5598 .ptp_support = true, 5599 .ops = &mv88e6352_ops, 5600 }, 5601 [MV88E6390] = { 5602 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5603 .family = MV88E6XXX_FAMILY_6390, 5604 .name = "Marvell 88E6390", 5605 .num_databases = 4096, 5606 .num_macs = 16384, 5607 .num_ports = 11, /* 10 + Z80 */ 5608 .num_internal_phys = 9, 5609 .num_gpio = 16, 5610 .max_vid = 8191, 5611 .port_base_addr = 0x0, 5612 .phy_base_addr = 0x0, 5613 .global1_addr = 0x1b, 5614 .global2_addr = 0x1c, 5615 .age_time_coeff = 3750, 5616 .g1_irqs = 9, 5617 .g2_irqs = 14, 5618 .atu_move_port_mask = 0x1f, 5619 .pvt = true, 5620 .multi_chip = true, 5621 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5622 .ptp_support = true, 5623 .ops = &mv88e6390_ops, 5624 }, 5625 [MV88E6390X] = { 5626 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5627 .family = MV88E6XXX_FAMILY_6390, 5628 .name = "Marvell 88E6390X", 5629 .num_databases = 4096, 5630 .num_macs = 16384, 5631 .num_ports = 11, /* 10 + Z80 */ 5632 .num_internal_phys = 9, 5633 .num_gpio = 16, 5634 .max_vid = 8191, 5635 .port_base_addr = 0x0, 5636 .phy_base_addr = 0x0, 5637 .global1_addr = 0x1b, 5638 .global2_addr = 0x1c, 5639 .age_time_coeff = 3750, 5640 .g1_irqs = 9, 5641 .g2_irqs = 14, 5642 .atu_move_port_mask = 0x1f, 5643 .pvt = true, 5644 .multi_chip = true, 5645 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5646 .ptp_support = true, 5647 .ops = &mv88e6390x_ops, 5648 }, 5649 5650 [MV88E6393X] = { 5651 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5652 .family = MV88E6XXX_FAMILY_6393, 5653 .name = "Marvell 88E6393X", 5654 .num_databases = 4096, 5655 .num_ports = 11, /* 10 + Z80 */ 5656 .num_internal_phys = 9, 5657 .max_vid = 8191, 5658 .port_base_addr = 0x0, 5659 .phy_base_addr = 0x0, 5660 .global1_addr = 0x1b, 5661 .global2_addr = 0x1c, 5662 .age_time_coeff = 3750, 5663 .g1_irqs = 10, 5664 .g2_irqs = 14, 5665 .atu_move_port_mask = 0x1f, 5666 .pvt = true, 5667 .multi_chip = true, 5668 .ptp_support = true, 5669 .ops = &mv88e6393x_ops, 5670 }, 5671 }; 5672 5673 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5674 { 5675 int i; 5676 5677 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5678 if (mv88e6xxx_table[i].prod_num == prod_num) 5679 return &mv88e6xxx_table[i]; 5680 5681 return NULL; 5682 } 5683 5684 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5685 { 5686 const struct mv88e6xxx_info *info; 5687 unsigned int prod_num, rev; 5688 u16 id; 5689 int err; 5690 5691 mv88e6xxx_reg_lock(chip); 5692 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5693 mv88e6xxx_reg_unlock(chip); 5694 if (err) 5695 return err; 5696 5697 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5698 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5699 5700 info = mv88e6xxx_lookup_info(prod_num); 5701 if (!info) 5702 return -ENODEV; 5703 5704 /* Update the compatible info with the probed one */ 5705 chip->info = info; 5706 5707 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5708 chip->info->prod_num, chip->info->name, rev); 5709 5710 return 0; 5711 } 5712 5713 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5714 { 5715 struct mv88e6xxx_chip *chip; 5716 5717 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5718 if (!chip) 5719 return NULL; 5720 5721 chip->dev = dev; 5722 5723 mutex_init(&chip->reg_lock); 5724 INIT_LIST_HEAD(&chip->mdios); 5725 idr_init(&chip->policies); 5726 5727 return chip; 5728 } 5729 5730 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5731 int port, 5732 enum dsa_tag_protocol m) 5733 { 5734 struct mv88e6xxx_chip *chip = ds->priv; 5735 5736 return chip->tag_protocol; 5737 } 5738 5739 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5740 enum dsa_tag_protocol proto) 5741 { 5742 struct mv88e6xxx_chip *chip = ds->priv; 5743 enum dsa_tag_protocol old_protocol; 5744 int err; 5745 5746 switch (proto) { 5747 case DSA_TAG_PROTO_EDSA: 5748 switch (chip->info->edsa_support) { 5749 case MV88E6XXX_EDSA_UNSUPPORTED: 5750 return -EPROTONOSUPPORT; 5751 case MV88E6XXX_EDSA_UNDOCUMENTED: 5752 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5753 fallthrough; 5754 case MV88E6XXX_EDSA_SUPPORTED: 5755 break; 5756 } 5757 break; 5758 case DSA_TAG_PROTO_DSA: 5759 break; 5760 default: 5761 return -EPROTONOSUPPORT; 5762 } 5763 5764 old_protocol = chip->tag_protocol; 5765 chip->tag_protocol = proto; 5766 5767 mv88e6xxx_reg_lock(chip); 5768 err = mv88e6xxx_setup_port_mode(chip, port); 5769 mv88e6xxx_reg_unlock(chip); 5770 5771 if (err) 5772 chip->tag_protocol = old_protocol; 5773 5774 return err; 5775 } 5776 5777 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5778 const struct switchdev_obj_port_mdb *mdb) 5779 { 5780 struct mv88e6xxx_chip *chip = ds->priv; 5781 int err; 5782 5783 mv88e6xxx_reg_lock(chip); 5784 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5785 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5786 mv88e6xxx_reg_unlock(chip); 5787 5788 return err; 5789 } 5790 5791 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5792 const struct switchdev_obj_port_mdb *mdb) 5793 { 5794 struct mv88e6xxx_chip *chip = ds->priv; 5795 int err; 5796 5797 mv88e6xxx_reg_lock(chip); 5798 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5799 mv88e6xxx_reg_unlock(chip); 5800 5801 return err; 5802 } 5803 5804 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5805 struct dsa_mall_mirror_tc_entry *mirror, 5806 bool ingress) 5807 { 5808 enum mv88e6xxx_egress_direction direction = ingress ? 5809 MV88E6XXX_EGRESS_DIR_INGRESS : 5810 MV88E6XXX_EGRESS_DIR_EGRESS; 5811 struct mv88e6xxx_chip *chip = ds->priv; 5812 bool other_mirrors = false; 5813 int i; 5814 int err; 5815 5816 mutex_lock(&chip->reg_lock); 5817 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5818 mirror->to_local_port) { 5819 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5820 other_mirrors |= ingress ? 5821 chip->ports[i].mirror_ingress : 5822 chip->ports[i].mirror_egress; 5823 5824 /* Can't change egress port when other mirror is active */ 5825 if (other_mirrors) { 5826 err = -EBUSY; 5827 goto out; 5828 } 5829 5830 err = mv88e6xxx_set_egress_port(chip, direction, 5831 mirror->to_local_port); 5832 if (err) 5833 goto out; 5834 } 5835 5836 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5837 out: 5838 mutex_unlock(&chip->reg_lock); 5839 5840 return err; 5841 } 5842 5843 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5844 struct dsa_mall_mirror_tc_entry *mirror) 5845 { 5846 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5847 MV88E6XXX_EGRESS_DIR_INGRESS : 5848 MV88E6XXX_EGRESS_DIR_EGRESS; 5849 struct mv88e6xxx_chip *chip = ds->priv; 5850 bool other_mirrors = false; 5851 int i; 5852 5853 mutex_lock(&chip->reg_lock); 5854 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5855 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5856 5857 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5858 other_mirrors |= mirror->ingress ? 5859 chip->ports[i].mirror_ingress : 5860 chip->ports[i].mirror_egress; 5861 5862 /* Reset egress port when no other mirror is active */ 5863 if (!other_mirrors) { 5864 if (mv88e6xxx_set_egress_port(chip, direction, 5865 dsa_upstream_port(ds, port))) 5866 dev_err(ds->dev, "failed to set egress port\n"); 5867 } 5868 5869 mutex_unlock(&chip->reg_lock); 5870 } 5871 5872 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5873 struct switchdev_brport_flags flags, 5874 struct netlink_ext_ack *extack) 5875 { 5876 struct mv88e6xxx_chip *chip = ds->priv; 5877 const struct mv88e6xxx_ops *ops; 5878 5879 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5880 BR_BCAST_FLOOD)) 5881 return -EINVAL; 5882 5883 ops = chip->info->ops; 5884 5885 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5886 return -EINVAL; 5887 5888 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5889 return -EINVAL; 5890 5891 return 0; 5892 } 5893 5894 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5895 struct switchdev_brport_flags flags, 5896 struct netlink_ext_ack *extack) 5897 { 5898 struct mv88e6xxx_chip *chip = ds->priv; 5899 int err = -EOPNOTSUPP; 5900 5901 mv88e6xxx_reg_lock(chip); 5902 5903 if (flags.mask & BR_LEARNING) { 5904 bool learning = !!(flags.val & BR_LEARNING); 5905 u16 pav = learning ? (1 << port) : 0; 5906 5907 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5908 if (err) 5909 goto out; 5910 } 5911 5912 if (flags.mask & BR_FLOOD) { 5913 bool unicast = !!(flags.val & BR_FLOOD); 5914 5915 err = chip->info->ops->port_set_ucast_flood(chip, port, 5916 unicast); 5917 if (err) 5918 goto out; 5919 } 5920 5921 if (flags.mask & BR_MCAST_FLOOD) { 5922 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5923 5924 err = chip->info->ops->port_set_mcast_flood(chip, port, 5925 multicast); 5926 if (err) 5927 goto out; 5928 } 5929 5930 if (flags.mask & BR_BCAST_FLOOD) { 5931 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5932 5933 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5934 if (err) 5935 goto out; 5936 } 5937 5938 out: 5939 mv88e6xxx_reg_unlock(chip); 5940 5941 return err; 5942 } 5943 5944 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5945 struct net_device *lag, 5946 struct netdev_lag_upper_info *info) 5947 { 5948 struct mv88e6xxx_chip *chip = ds->priv; 5949 struct dsa_port *dp; 5950 int id, members = 0; 5951 5952 if (!mv88e6xxx_has_lag(chip)) 5953 return false; 5954 5955 id = dsa_lag_id(ds->dst, lag); 5956 if (id < 0 || id >= ds->num_lag_ids) 5957 return false; 5958 5959 dsa_lag_foreach_port(dp, ds->dst, lag) 5960 /* Includes the port joining the LAG */ 5961 members++; 5962 5963 if (members > 8) 5964 return false; 5965 5966 /* We could potentially relax this to include active 5967 * backup in the future. 5968 */ 5969 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5970 return false; 5971 5972 /* Ideally we would also validate that the hash type matches 5973 * the hardware. Alas, this is always set to unknown on team 5974 * interfaces. 5975 */ 5976 return true; 5977 } 5978 5979 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5980 { 5981 struct mv88e6xxx_chip *chip = ds->priv; 5982 struct dsa_port *dp; 5983 u16 map = 0; 5984 int id; 5985 5986 id = dsa_lag_id(ds->dst, lag); 5987 5988 /* Build the map of all ports to distribute flows destined for 5989 * this LAG. This can be either a local user port, or a DSA 5990 * port if the LAG port is on a remote chip. 5991 */ 5992 dsa_lag_foreach_port(dp, ds->dst, lag) 5993 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5994 5995 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5996 } 5997 5998 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5999 /* Row number corresponds to the number of active members in a 6000 * LAG. Each column states which of the eight hash buckets are 6001 * mapped to the column:th port in the LAG. 6002 * 6003 * Example: In a LAG with three active ports, the second port 6004 * ([2][1]) would be selected for traffic mapped to buckets 6005 * 3,4,5 (0x38). 6006 */ 6007 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6008 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6009 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6010 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6011 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6012 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6013 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6014 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6015 }; 6016 6017 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6018 int num_tx, int nth) 6019 { 6020 u8 active = 0; 6021 int i; 6022 6023 num_tx = num_tx <= 8 ? num_tx : 8; 6024 if (nth < num_tx) 6025 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6026 6027 for (i = 0; i < 8; i++) { 6028 if (BIT(i) & active) 6029 mask[i] |= BIT(port); 6030 } 6031 } 6032 6033 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6034 { 6035 struct mv88e6xxx_chip *chip = ds->priv; 6036 unsigned int id, num_tx; 6037 struct net_device *lag; 6038 struct dsa_port *dp; 6039 int i, err, nth; 6040 u16 mask[8]; 6041 u16 ivec; 6042 6043 /* Assume no port is a member of any LAG. */ 6044 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6045 6046 /* Disable all masks for ports that _are_ members of a LAG. */ 6047 list_for_each_entry(dp, &ds->dst->ports, list) { 6048 if (!dp->lag_dev || dp->ds != ds) 6049 continue; 6050 6051 ivec &= ~BIT(dp->index); 6052 } 6053 6054 for (i = 0; i < 8; i++) 6055 mask[i] = ivec; 6056 6057 /* Enable the correct subset of masks for all LAG ports that 6058 * are in the Tx set. 6059 */ 6060 dsa_lags_foreach_id(id, ds->dst) { 6061 lag = dsa_lag_dev(ds->dst, id); 6062 if (!lag) 6063 continue; 6064 6065 num_tx = 0; 6066 dsa_lag_foreach_port(dp, ds->dst, lag) { 6067 if (dp->lag_tx_enabled) 6068 num_tx++; 6069 } 6070 6071 if (!num_tx) 6072 continue; 6073 6074 nth = 0; 6075 dsa_lag_foreach_port(dp, ds->dst, lag) { 6076 if (!dp->lag_tx_enabled) 6077 continue; 6078 6079 if (dp->ds == ds) 6080 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6081 num_tx, nth); 6082 6083 nth++; 6084 } 6085 } 6086 6087 for (i = 0; i < 8; i++) { 6088 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6089 if (err) 6090 return err; 6091 } 6092 6093 return 0; 6094 } 6095 6096 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6097 struct net_device *lag) 6098 { 6099 int err; 6100 6101 err = mv88e6xxx_lag_sync_masks(ds); 6102 6103 if (!err) 6104 err = mv88e6xxx_lag_sync_map(ds, lag); 6105 6106 return err; 6107 } 6108 6109 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6110 { 6111 struct mv88e6xxx_chip *chip = ds->priv; 6112 int err; 6113 6114 mv88e6xxx_reg_lock(chip); 6115 err = mv88e6xxx_lag_sync_masks(ds); 6116 mv88e6xxx_reg_unlock(chip); 6117 return err; 6118 } 6119 6120 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6121 struct net_device *lag, 6122 struct netdev_lag_upper_info *info) 6123 { 6124 struct mv88e6xxx_chip *chip = ds->priv; 6125 int err, id; 6126 6127 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6128 return -EOPNOTSUPP; 6129 6130 id = dsa_lag_id(ds->dst, lag); 6131 6132 mv88e6xxx_reg_lock(chip); 6133 6134 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6135 if (err) 6136 goto err_unlock; 6137 6138 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6139 if (err) 6140 goto err_clear_trunk; 6141 6142 mv88e6xxx_reg_unlock(chip); 6143 return 0; 6144 6145 err_clear_trunk: 6146 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6147 err_unlock: 6148 mv88e6xxx_reg_unlock(chip); 6149 return err; 6150 } 6151 6152 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6153 struct net_device *lag) 6154 { 6155 struct mv88e6xxx_chip *chip = ds->priv; 6156 int err_sync, err_trunk; 6157 6158 mv88e6xxx_reg_lock(chip); 6159 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6160 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6161 mv88e6xxx_reg_unlock(chip); 6162 return err_sync ? : err_trunk; 6163 } 6164 6165 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6166 int port) 6167 { 6168 struct mv88e6xxx_chip *chip = ds->priv; 6169 int err; 6170 6171 mv88e6xxx_reg_lock(chip); 6172 err = mv88e6xxx_lag_sync_masks(ds); 6173 mv88e6xxx_reg_unlock(chip); 6174 return err; 6175 } 6176 6177 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6178 int port, struct net_device *lag, 6179 struct netdev_lag_upper_info *info) 6180 { 6181 struct mv88e6xxx_chip *chip = ds->priv; 6182 int err; 6183 6184 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6185 return -EOPNOTSUPP; 6186 6187 mv88e6xxx_reg_lock(chip); 6188 6189 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6190 if (err) 6191 goto unlock; 6192 6193 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6194 6195 unlock: 6196 mv88e6xxx_reg_unlock(chip); 6197 return err; 6198 } 6199 6200 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6201 int port, struct net_device *lag) 6202 { 6203 struct mv88e6xxx_chip *chip = ds->priv; 6204 int err_sync, err_pvt; 6205 6206 mv88e6xxx_reg_lock(chip); 6207 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6208 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6209 mv88e6xxx_reg_unlock(chip); 6210 return err_sync ? : err_pvt; 6211 } 6212 6213 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6214 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6215 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6216 .setup = mv88e6xxx_setup, 6217 .teardown = mv88e6xxx_teardown, 6218 .port_setup = mv88e6xxx_port_setup, 6219 .port_teardown = mv88e6xxx_port_teardown, 6220 .phylink_validate = mv88e6xxx_validate, 6221 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6222 .phylink_mac_config = mv88e6xxx_mac_config, 6223 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6224 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6225 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6226 .get_strings = mv88e6xxx_get_strings, 6227 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6228 .get_sset_count = mv88e6xxx_get_sset_count, 6229 .port_enable = mv88e6xxx_port_enable, 6230 .port_disable = mv88e6xxx_port_disable, 6231 .port_max_mtu = mv88e6xxx_get_max_mtu, 6232 .port_change_mtu = mv88e6xxx_change_mtu, 6233 .get_mac_eee = mv88e6xxx_get_mac_eee, 6234 .set_mac_eee = mv88e6xxx_set_mac_eee, 6235 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6236 .get_eeprom = mv88e6xxx_get_eeprom, 6237 .set_eeprom = mv88e6xxx_set_eeprom, 6238 .get_regs_len = mv88e6xxx_get_regs_len, 6239 .get_regs = mv88e6xxx_get_regs, 6240 .get_rxnfc = mv88e6xxx_get_rxnfc, 6241 .set_rxnfc = mv88e6xxx_set_rxnfc, 6242 .set_ageing_time = mv88e6xxx_set_ageing_time, 6243 .port_bridge_join = mv88e6xxx_port_bridge_join, 6244 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6245 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6246 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6247 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6248 .port_fast_age = mv88e6xxx_port_fast_age, 6249 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6250 .port_vlan_add = mv88e6xxx_port_vlan_add, 6251 .port_vlan_del = mv88e6xxx_port_vlan_del, 6252 .port_fdb_add = mv88e6xxx_port_fdb_add, 6253 .port_fdb_del = mv88e6xxx_port_fdb_del, 6254 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6255 .port_mdb_add = mv88e6xxx_port_mdb_add, 6256 .port_mdb_del = mv88e6xxx_port_mdb_del, 6257 .port_mirror_add = mv88e6xxx_port_mirror_add, 6258 .port_mirror_del = mv88e6xxx_port_mirror_del, 6259 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6260 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6261 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6262 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6263 .port_txtstamp = mv88e6xxx_port_txtstamp, 6264 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6265 .get_ts_info = mv88e6xxx_get_ts_info, 6266 .devlink_param_get = mv88e6xxx_devlink_param_get, 6267 .devlink_param_set = mv88e6xxx_devlink_param_set, 6268 .devlink_info_get = mv88e6xxx_devlink_info_get, 6269 .port_lag_change = mv88e6xxx_port_lag_change, 6270 .port_lag_join = mv88e6xxx_port_lag_join, 6271 .port_lag_leave = mv88e6xxx_port_lag_leave, 6272 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6273 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6274 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6275 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6276 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6277 }; 6278 6279 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6280 { 6281 struct device *dev = chip->dev; 6282 struct dsa_switch *ds; 6283 6284 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6285 if (!ds) 6286 return -ENOMEM; 6287 6288 ds->dev = dev; 6289 ds->num_ports = mv88e6xxx_num_ports(chip); 6290 ds->priv = chip; 6291 ds->dev = dev; 6292 ds->ops = &mv88e6xxx_switch_ops; 6293 ds->ageing_time_min = chip->info->age_time_coeff; 6294 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6295 6296 /* Some chips support up to 32, but that requires enabling the 6297 * 5-bit port mode, which we do not support. 640k^W16 ought to 6298 * be enough for anyone. 6299 */ 6300 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6301 6302 dev_set_drvdata(dev, ds); 6303 6304 return dsa_register_switch(ds); 6305 } 6306 6307 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6308 { 6309 dsa_unregister_switch(chip->ds); 6310 } 6311 6312 static const void *pdata_device_get_match_data(struct device *dev) 6313 { 6314 const struct of_device_id *matches = dev->driver->of_match_table; 6315 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6316 6317 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6318 matches++) { 6319 if (!strcmp(pdata->compatible, matches->compatible)) 6320 return matches->data; 6321 } 6322 return NULL; 6323 } 6324 6325 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6326 * would be lost after a power cycle so prevent it to be suspended. 6327 */ 6328 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6329 { 6330 return -EOPNOTSUPP; 6331 } 6332 6333 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6334 { 6335 return 0; 6336 } 6337 6338 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6339 6340 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6341 { 6342 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6343 const struct mv88e6xxx_info *compat_info = NULL; 6344 struct device *dev = &mdiodev->dev; 6345 struct device_node *np = dev->of_node; 6346 struct mv88e6xxx_chip *chip; 6347 int port; 6348 int err; 6349 6350 if (!np && !pdata) 6351 return -EINVAL; 6352 6353 if (np) 6354 compat_info = of_device_get_match_data(dev); 6355 6356 if (pdata) { 6357 compat_info = pdata_device_get_match_data(dev); 6358 6359 if (!pdata->netdev) 6360 return -EINVAL; 6361 6362 for (port = 0; port < DSA_MAX_PORTS; port++) { 6363 if (!(pdata->enabled_ports & (1 << port))) 6364 continue; 6365 if (strcmp(pdata->cd.port_names[port], "cpu")) 6366 continue; 6367 pdata->cd.netdev[port] = &pdata->netdev->dev; 6368 break; 6369 } 6370 } 6371 6372 if (!compat_info) 6373 return -EINVAL; 6374 6375 chip = mv88e6xxx_alloc_chip(dev); 6376 if (!chip) { 6377 err = -ENOMEM; 6378 goto out; 6379 } 6380 6381 chip->info = compat_info; 6382 6383 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6384 if (err) 6385 goto out; 6386 6387 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6388 if (IS_ERR(chip->reset)) { 6389 err = PTR_ERR(chip->reset); 6390 goto out; 6391 } 6392 if (chip->reset) 6393 usleep_range(1000, 2000); 6394 6395 err = mv88e6xxx_detect(chip); 6396 if (err) 6397 goto out; 6398 6399 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6400 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6401 else 6402 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6403 6404 mv88e6xxx_phy_init(chip); 6405 6406 if (chip->info->ops->get_eeprom) { 6407 if (np) 6408 of_property_read_u32(np, "eeprom-length", 6409 &chip->eeprom_len); 6410 else 6411 chip->eeprom_len = pdata->eeprom_len; 6412 } 6413 6414 mv88e6xxx_reg_lock(chip); 6415 err = mv88e6xxx_switch_reset(chip); 6416 mv88e6xxx_reg_unlock(chip); 6417 if (err) 6418 goto out; 6419 6420 if (np) { 6421 chip->irq = of_irq_get(np, 0); 6422 if (chip->irq == -EPROBE_DEFER) { 6423 err = chip->irq; 6424 goto out; 6425 } 6426 } 6427 6428 if (pdata) 6429 chip->irq = pdata->irq; 6430 6431 /* Has to be performed before the MDIO bus is created, because 6432 * the PHYs will link their interrupts to these interrupt 6433 * controllers 6434 */ 6435 mv88e6xxx_reg_lock(chip); 6436 if (chip->irq > 0) 6437 err = mv88e6xxx_g1_irq_setup(chip); 6438 else 6439 err = mv88e6xxx_irq_poll_setup(chip); 6440 mv88e6xxx_reg_unlock(chip); 6441 6442 if (err) 6443 goto out; 6444 6445 if (chip->info->g2_irqs > 0) { 6446 err = mv88e6xxx_g2_irq_setup(chip); 6447 if (err) 6448 goto out_g1_irq; 6449 } 6450 6451 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6452 if (err) 6453 goto out_g2_irq; 6454 6455 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6456 if (err) 6457 goto out_g1_atu_prob_irq; 6458 6459 err = mv88e6xxx_mdios_register(chip, np); 6460 if (err) 6461 goto out_g1_vtu_prob_irq; 6462 6463 err = mv88e6xxx_register_switch(chip); 6464 if (err) 6465 goto out_mdio; 6466 6467 return 0; 6468 6469 out_mdio: 6470 mv88e6xxx_mdios_unregister(chip); 6471 out_g1_vtu_prob_irq: 6472 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6473 out_g1_atu_prob_irq: 6474 mv88e6xxx_g1_atu_prob_irq_free(chip); 6475 out_g2_irq: 6476 if (chip->info->g2_irqs > 0) 6477 mv88e6xxx_g2_irq_free(chip); 6478 out_g1_irq: 6479 if (chip->irq > 0) 6480 mv88e6xxx_g1_irq_free(chip); 6481 else 6482 mv88e6xxx_irq_poll_free(chip); 6483 out: 6484 if (pdata) 6485 dev_put(pdata->netdev); 6486 6487 return err; 6488 } 6489 6490 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6491 { 6492 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6493 struct mv88e6xxx_chip *chip; 6494 6495 if (!ds) 6496 return; 6497 6498 chip = ds->priv; 6499 6500 if (chip->info->ptp_support) { 6501 mv88e6xxx_hwtstamp_free(chip); 6502 mv88e6xxx_ptp_free(chip); 6503 } 6504 6505 mv88e6xxx_phy_destroy(chip); 6506 mv88e6xxx_unregister_switch(chip); 6507 mv88e6xxx_mdios_unregister(chip); 6508 6509 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6510 mv88e6xxx_g1_atu_prob_irq_free(chip); 6511 6512 if (chip->info->g2_irqs > 0) 6513 mv88e6xxx_g2_irq_free(chip); 6514 6515 if (chip->irq > 0) 6516 mv88e6xxx_g1_irq_free(chip); 6517 else 6518 mv88e6xxx_irq_poll_free(chip); 6519 6520 dev_set_drvdata(&mdiodev->dev, NULL); 6521 } 6522 6523 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6524 { 6525 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6526 6527 if (!ds) 6528 return; 6529 6530 dsa_switch_shutdown(ds); 6531 6532 dev_set_drvdata(&mdiodev->dev, NULL); 6533 } 6534 6535 static const struct of_device_id mv88e6xxx_of_match[] = { 6536 { 6537 .compatible = "marvell,mv88e6085", 6538 .data = &mv88e6xxx_table[MV88E6085], 6539 }, 6540 { 6541 .compatible = "marvell,mv88e6190", 6542 .data = &mv88e6xxx_table[MV88E6190], 6543 }, 6544 { 6545 .compatible = "marvell,mv88e6250", 6546 .data = &mv88e6xxx_table[MV88E6250], 6547 }, 6548 { /* sentinel */ }, 6549 }; 6550 6551 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6552 6553 static struct mdio_driver mv88e6xxx_driver = { 6554 .probe = mv88e6xxx_probe, 6555 .remove = mv88e6xxx_remove, 6556 .shutdown = mv88e6xxx_shutdown, 6557 .mdiodrv.driver = { 6558 .name = "mv88e6085", 6559 .of_match_table = mv88e6xxx_of_match, 6560 .pm = &mv88e6xxx_pm_ops, 6561 }, 6562 }; 6563 6564 mdio_module_driver(mv88e6xxx_driver); 6565 6566 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6567 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6568 MODULE_LICENSE("GPL"); 6569