1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <linux/phylink.h> 35 #include <net/dsa.h> 36 37 #include "chip.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 55 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 56 * 57 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 58 * is the only device connected to the SMI master. In this mode it responds to 59 * all 32 possible SMI addresses, and thus maps directly the internal devices. 60 * 61 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 62 * multiple devices to share the SMI interface. In this mode it responds to only 63 * 2 registers, used to indirectly access the internal SMI devices. 64 */ 65 66 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 67 int addr, int reg, u16 *val) 68 { 69 if (!chip->smi_ops) 70 return -EOPNOTSUPP; 71 72 return chip->smi_ops->read(chip, addr, reg, val); 73 } 74 75 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 76 int addr, int reg, u16 val) 77 { 78 if (!chip->smi_ops) 79 return -EOPNOTSUPP; 80 81 return chip->smi_ops->write(chip, addr, reg, val); 82 } 83 84 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 85 int addr, int reg, u16 *val) 86 { 87 int ret; 88 89 ret = mdiobus_read_nested(chip->bus, addr, reg); 90 if (ret < 0) 91 return ret; 92 93 *val = ret & 0xffff; 94 95 return 0; 96 } 97 98 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 99 int addr, int reg, u16 val) 100 { 101 int ret; 102 103 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 104 if (ret < 0) 105 return ret; 106 107 return 0; 108 } 109 110 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 111 .read = mv88e6xxx_smi_single_chip_read, 112 .write = mv88e6xxx_smi_single_chip_write, 113 }; 114 115 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 116 { 117 int ret; 118 int i; 119 120 for (i = 0; i < 16; i++) { 121 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 122 if (ret < 0) 123 return ret; 124 125 if ((ret & SMI_CMD_BUSY) == 0) 126 return 0; 127 } 128 129 return -ETIMEDOUT; 130 } 131 132 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 133 int addr, int reg, u16 *val) 134 { 135 int ret; 136 137 /* Wait for the bus to become free. */ 138 ret = mv88e6xxx_smi_multi_chip_wait(chip); 139 if (ret < 0) 140 return ret; 141 142 /* Transmit the read command. */ 143 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 144 SMI_CMD_OP_22_READ | (addr << 5) | reg); 145 if (ret < 0) 146 return ret; 147 148 /* Wait for the read command to complete. */ 149 ret = mv88e6xxx_smi_multi_chip_wait(chip); 150 if (ret < 0) 151 return ret; 152 153 /* Read the data. */ 154 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 155 if (ret < 0) 156 return ret; 157 158 *val = ret & 0xffff; 159 160 return 0; 161 } 162 163 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 164 int addr, int reg, u16 val) 165 { 166 int ret; 167 168 /* Wait for the bus to become free. */ 169 ret = mv88e6xxx_smi_multi_chip_wait(chip); 170 if (ret < 0) 171 return ret; 172 173 /* Transmit the data to write. */ 174 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 175 if (ret < 0) 176 return ret; 177 178 /* Transmit the write command. */ 179 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 180 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 181 if (ret < 0) 182 return ret; 183 184 /* Wait for the write command to complete. */ 185 ret = mv88e6xxx_smi_multi_chip_wait(chip); 186 if (ret < 0) 187 return ret; 188 189 return 0; 190 } 191 192 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 193 .read = mv88e6xxx_smi_multi_chip_read, 194 .write = mv88e6xxx_smi_multi_chip_write, 195 }; 196 197 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 198 { 199 int err; 200 201 assert_reg_lock(chip); 202 203 err = mv88e6xxx_smi_read(chip, addr, reg, val); 204 if (err) 205 return err; 206 207 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 208 addr, reg, *val); 209 210 return 0; 211 } 212 213 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 214 { 215 int err; 216 217 assert_reg_lock(chip); 218 219 err = mv88e6xxx_smi_write(chip, addr, reg, val); 220 if (err) 221 return err; 222 223 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 224 addr, reg, val); 225 226 return 0; 227 } 228 229 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 230 { 231 struct mv88e6xxx_mdio_bus *mdio_bus; 232 233 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 234 list); 235 if (!mdio_bus) 236 return NULL; 237 238 return mdio_bus->bus; 239 } 240 241 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 242 { 243 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 244 unsigned int n = d->hwirq; 245 246 chip->g1_irq.masked |= (1 << n); 247 } 248 249 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 250 { 251 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 252 unsigned int n = d->hwirq; 253 254 chip->g1_irq.masked &= ~(1 << n); 255 } 256 257 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 258 { 259 unsigned int nhandled = 0; 260 unsigned int sub_irq; 261 unsigned int n; 262 u16 reg; 263 int err; 264 265 mutex_lock(&chip->reg_lock); 266 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 267 mutex_unlock(&chip->reg_lock); 268 269 if (err) 270 goto out; 271 272 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 273 if (reg & (1 << n)) { 274 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 275 handle_nested_irq(sub_irq); 276 ++nhandled; 277 } 278 } 279 out: 280 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 281 } 282 283 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 284 { 285 struct mv88e6xxx_chip *chip = dev_id; 286 287 return mv88e6xxx_g1_irq_thread_work(chip); 288 } 289 290 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 291 { 292 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 293 294 mutex_lock(&chip->reg_lock); 295 } 296 297 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 298 { 299 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 300 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 301 u16 reg; 302 int err; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 305 if (err) 306 goto out; 307 308 reg &= ~mask; 309 reg |= (~chip->g1_irq.masked & mask); 310 311 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 312 if (err) 313 goto out; 314 315 out: 316 mutex_unlock(&chip->reg_lock); 317 } 318 319 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 320 .name = "mv88e6xxx-g1", 321 .irq_mask = mv88e6xxx_g1_irq_mask, 322 .irq_unmask = mv88e6xxx_g1_irq_unmask, 323 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 324 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 325 }; 326 327 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 328 unsigned int irq, 329 irq_hw_number_t hwirq) 330 { 331 struct mv88e6xxx_chip *chip = d->host_data; 332 333 irq_set_chip_data(irq, d->host_data); 334 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 335 irq_set_noprobe(irq); 336 337 return 0; 338 } 339 340 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 341 .map = mv88e6xxx_g1_irq_domain_map, 342 .xlate = irq_domain_xlate_twocell, 343 }; 344 345 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 346 { 347 int irq, virq; 348 u16 mask; 349 350 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 351 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 352 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 353 354 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 355 virq = irq_find_mapping(chip->g1_irq.domain, irq); 356 irq_dispose_mapping(virq); 357 } 358 359 irq_domain_remove(chip->g1_irq.domain); 360 } 361 362 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 363 { 364 mv88e6xxx_g1_irq_free_common(chip); 365 366 free_irq(chip->irq, chip); 367 } 368 369 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 370 { 371 int err, irq, virq; 372 u16 reg, mask; 373 374 chip->g1_irq.nirqs = chip->info->g1_irqs; 375 chip->g1_irq.domain = irq_domain_add_simple( 376 NULL, chip->g1_irq.nirqs, 0, 377 &mv88e6xxx_g1_irq_domain_ops, chip); 378 if (!chip->g1_irq.domain) 379 return -ENOMEM; 380 381 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 382 irq_create_mapping(chip->g1_irq.domain, irq); 383 384 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 385 chip->g1_irq.masked = ~0; 386 387 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 388 if (err) 389 goto out_mapping; 390 391 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 392 393 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 394 if (err) 395 goto out_disable; 396 397 /* Reading the interrupt status clears (most of) them */ 398 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 399 if (err) 400 goto out_disable; 401 402 return 0; 403 404 out_disable: 405 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 406 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 407 408 out_mapping: 409 for (irq = 0; irq < 16; irq++) { 410 virq = irq_find_mapping(chip->g1_irq.domain, irq); 411 irq_dispose_mapping(virq); 412 } 413 414 irq_domain_remove(chip->g1_irq.domain); 415 416 return err; 417 } 418 419 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 420 { 421 int err; 422 423 err = mv88e6xxx_g1_irq_setup_common(chip); 424 if (err) 425 return err; 426 427 err = request_threaded_irq(chip->irq, NULL, 428 mv88e6xxx_g1_irq_thread_fn, 429 IRQF_ONESHOT, 430 dev_name(chip->dev), chip); 431 if (err) 432 mv88e6xxx_g1_irq_free_common(chip); 433 434 return err; 435 } 436 437 static void mv88e6xxx_irq_poll(struct kthread_work *work) 438 { 439 struct mv88e6xxx_chip *chip = container_of(work, 440 struct mv88e6xxx_chip, 441 irq_poll_work.work); 442 mv88e6xxx_g1_irq_thread_work(chip); 443 444 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 445 msecs_to_jiffies(100)); 446 } 447 448 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 449 { 450 int err; 451 452 err = mv88e6xxx_g1_irq_setup_common(chip); 453 if (err) 454 return err; 455 456 kthread_init_delayed_work(&chip->irq_poll_work, 457 mv88e6xxx_irq_poll); 458 459 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 460 if (IS_ERR(chip->kworker)) 461 return PTR_ERR(chip->kworker); 462 463 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 464 msecs_to_jiffies(100)); 465 466 return 0; 467 } 468 469 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 470 { 471 mv88e6xxx_g1_irq_free_common(chip); 472 473 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 474 kthread_destroy_worker(chip->kworker); 475 } 476 477 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 478 { 479 int i; 480 481 for (i = 0; i < 16; i++) { 482 u16 val; 483 int err; 484 485 err = mv88e6xxx_read(chip, addr, reg, &val); 486 if (err) 487 return err; 488 489 if (!(val & mask)) 490 return 0; 491 492 usleep_range(1000, 2000); 493 } 494 495 dev_err(chip->dev, "Timeout while waiting for switch\n"); 496 return -ETIMEDOUT; 497 } 498 499 /* Indirect write to single pointer-data register with an Update bit */ 500 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 501 { 502 u16 val; 503 int err; 504 505 /* Wait until the previous operation is completed */ 506 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 507 if (err) 508 return err; 509 510 /* Set the Update bit to trigger a write operation */ 511 val = BIT(15) | update; 512 513 return mv88e6xxx_write(chip, addr, reg, val); 514 } 515 516 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 517 int link, int speed, int duplex, 518 phy_interface_t mode) 519 { 520 int err; 521 522 if (!chip->info->ops->port_set_link) 523 return 0; 524 525 /* Port's MAC control must not be changed unless the link is down */ 526 err = chip->info->ops->port_set_link(chip, port, 0); 527 if (err) 528 return err; 529 530 if (chip->info->ops->port_set_speed) { 531 err = chip->info->ops->port_set_speed(chip, port, speed); 532 if (err && err != -EOPNOTSUPP) 533 goto restore_link; 534 } 535 536 if (chip->info->ops->port_set_duplex) { 537 err = chip->info->ops->port_set_duplex(chip, port, duplex); 538 if (err && err != -EOPNOTSUPP) 539 goto restore_link; 540 } 541 542 if (chip->info->ops->port_set_rgmii_delay) { 543 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 544 if (err && err != -EOPNOTSUPP) 545 goto restore_link; 546 } 547 548 if (chip->info->ops->port_set_cmode) { 549 err = chip->info->ops->port_set_cmode(chip, port, mode); 550 if (err && err != -EOPNOTSUPP) 551 goto restore_link; 552 } 553 554 err = 0; 555 restore_link: 556 if (chip->info->ops->port_set_link(chip, port, link)) 557 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 558 559 return err; 560 } 561 562 /* We expect the switch to perform auto negotiation if there is a real 563 * phy. However, in the case of a fixed link phy, we force the port 564 * settings from the fixed link settings. 565 */ 566 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 567 struct phy_device *phydev) 568 { 569 struct mv88e6xxx_chip *chip = ds->priv; 570 int err; 571 572 if (!phy_is_pseudo_fixed_link(phydev)) 573 return; 574 575 mutex_lock(&chip->reg_lock); 576 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 577 phydev->duplex, phydev->interface); 578 mutex_unlock(&chip->reg_lock); 579 580 if (err && err != -EOPNOTSUPP) 581 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 582 } 583 584 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 585 unsigned long *supported, 586 struct phylink_link_state *state) 587 { 588 } 589 590 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 591 struct phylink_link_state *state) 592 { 593 struct mv88e6xxx_chip *chip = ds->priv; 594 int err; 595 596 mutex_lock(&chip->reg_lock); 597 err = mv88e6xxx_port_link_state(chip, port, state); 598 mutex_unlock(&chip->reg_lock); 599 600 return err; 601 } 602 603 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 604 unsigned int mode, 605 const struct phylink_link_state *state) 606 { 607 struct mv88e6xxx_chip *chip = ds->priv; 608 int speed, duplex, link, err; 609 610 if (mode == MLO_AN_PHY) 611 return; 612 613 if (mode == MLO_AN_FIXED) { 614 link = LINK_FORCED_UP; 615 speed = state->speed; 616 duplex = state->duplex; 617 } else { 618 speed = SPEED_UNFORCED; 619 duplex = DUPLEX_UNFORCED; 620 link = LINK_UNFORCED; 621 } 622 623 mutex_lock(&chip->reg_lock); 624 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, 625 state->interface); 626 mutex_unlock(&chip->reg_lock); 627 628 if (err && err != -EOPNOTSUPP) 629 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 630 } 631 632 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 633 { 634 struct mv88e6xxx_chip *chip = ds->priv; 635 int err; 636 637 mutex_lock(&chip->reg_lock); 638 err = chip->info->ops->port_set_link(chip, port, link); 639 mutex_unlock(&chip->reg_lock); 640 641 if (err) 642 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 643 } 644 645 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 646 unsigned int mode, 647 phy_interface_t interface) 648 { 649 if (mode == MLO_AN_FIXED) 650 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 651 } 652 653 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 654 unsigned int mode, phy_interface_t interface, 655 struct phy_device *phydev) 656 { 657 if (mode == MLO_AN_FIXED) 658 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 659 } 660 661 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 662 { 663 if (!chip->info->ops->stats_snapshot) 664 return -EOPNOTSUPP; 665 666 return chip->info->ops->stats_snapshot(chip, port); 667 } 668 669 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 670 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 671 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 672 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 673 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 674 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 675 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 676 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 677 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 678 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 679 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 680 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 681 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 682 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 683 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 684 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 685 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 686 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 687 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 688 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 689 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 690 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 691 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 692 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 693 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 694 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 695 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 696 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 697 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 698 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 699 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 700 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 701 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 702 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 703 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 704 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 705 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 706 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 707 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 708 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 709 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 710 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 711 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 712 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 713 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 714 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 715 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 716 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 717 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 718 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 719 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 720 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 721 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 722 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 723 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 724 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 725 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 726 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 727 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 728 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 729 }; 730 731 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 732 struct mv88e6xxx_hw_stat *s, 733 int port, u16 bank1_select, 734 u16 histogram) 735 { 736 u32 low; 737 u32 high = 0; 738 u16 reg = 0; 739 int err; 740 u64 value; 741 742 switch (s->type) { 743 case STATS_TYPE_PORT: 744 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 745 if (err) 746 return U64_MAX; 747 748 low = reg; 749 if (s->size == 4) { 750 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 751 if (err) 752 return U64_MAX; 753 high = reg; 754 } 755 break; 756 case STATS_TYPE_BANK1: 757 reg = bank1_select; 758 /* fall through */ 759 case STATS_TYPE_BANK0: 760 reg |= s->reg | histogram; 761 mv88e6xxx_g1_stats_read(chip, reg, &low); 762 if (s->size == 8) 763 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 764 break; 765 default: 766 return U64_MAX; 767 } 768 value = (((u64)high) << 16) | low; 769 return value; 770 } 771 772 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 773 uint8_t *data, int types) 774 { 775 struct mv88e6xxx_hw_stat *stat; 776 int i, j; 777 778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 779 stat = &mv88e6xxx_hw_stats[i]; 780 if (stat->type & types) { 781 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 782 ETH_GSTRING_LEN); 783 j++; 784 } 785 } 786 787 return j; 788 } 789 790 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 791 uint8_t *data) 792 { 793 return mv88e6xxx_stats_get_strings(chip, data, 794 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 795 } 796 797 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 798 uint8_t *data) 799 { 800 return mv88e6xxx_stats_get_strings(chip, data, 801 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 802 } 803 804 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 805 "atu_member_violation", 806 "atu_miss_violation", 807 "atu_full_violation", 808 "vtu_member_violation", 809 "vtu_miss_violation", 810 }; 811 812 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 813 { 814 unsigned int i; 815 816 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 817 strlcpy(data + i * ETH_GSTRING_LEN, 818 mv88e6xxx_atu_vtu_stats_strings[i], 819 ETH_GSTRING_LEN); 820 } 821 822 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 823 u32 stringset, uint8_t *data) 824 { 825 struct mv88e6xxx_chip *chip = ds->priv; 826 int count = 0; 827 828 if (stringset != ETH_SS_STATS) 829 return; 830 831 mutex_lock(&chip->reg_lock); 832 833 if (chip->info->ops->stats_get_strings) 834 count = chip->info->ops->stats_get_strings(chip, data); 835 836 if (chip->info->ops->serdes_get_strings) { 837 data += count * ETH_GSTRING_LEN; 838 count = chip->info->ops->serdes_get_strings(chip, port, data); 839 } 840 841 data += count * ETH_GSTRING_LEN; 842 mv88e6xxx_atu_vtu_get_strings(data); 843 844 mutex_unlock(&chip->reg_lock); 845 } 846 847 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 848 int types) 849 { 850 struct mv88e6xxx_hw_stat *stat; 851 int i, j; 852 853 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 854 stat = &mv88e6xxx_hw_stats[i]; 855 if (stat->type & types) 856 j++; 857 } 858 return j; 859 } 860 861 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 862 { 863 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 864 STATS_TYPE_PORT); 865 } 866 867 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 868 { 869 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 870 STATS_TYPE_BANK1); 871 } 872 873 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 874 { 875 struct mv88e6xxx_chip *chip = ds->priv; 876 int serdes_count = 0; 877 int count = 0; 878 879 if (sset != ETH_SS_STATS) 880 return 0; 881 882 mutex_lock(&chip->reg_lock); 883 if (chip->info->ops->stats_get_sset_count) 884 count = chip->info->ops->stats_get_sset_count(chip); 885 if (count < 0) 886 goto out; 887 888 if (chip->info->ops->serdes_get_sset_count) 889 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 890 port); 891 if (serdes_count < 0) { 892 count = serdes_count; 893 goto out; 894 } 895 count += serdes_count; 896 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 897 898 out: 899 mutex_unlock(&chip->reg_lock); 900 901 return count; 902 } 903 904 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 905 uint64_t *data, int types, 906 u16 bank1_select, u16 histogram) 907 { 908 struct mv88e6xxx_hw_stat *stat; 909 int i, j; 910 911 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 912 stat = &mv88e6xxx_hw_stats[i]; 913 if (stat->type & types) { 914 mutex_lock(&chip->reg_lock); 915 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 916 bank1_select, 917 histogram); 918 mutex_unlock(&chip->reg_lock); 919 920 j++; 921 } 922 } 923 return j; 924 } 925 926 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 927 uint64_t *data) 928 { 929 return mv88e6xxx_stats_get_stats(chip, port, data, 930 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 931 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 932 } 933 934 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 935 uint64_t *data) 936 { 937 return mv88e6xxx_stats_get_stats(chip, port, data, 938 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 939 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 940 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 941 } 942 943 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 944 uint64_t *data) 945 { 946 return mv88e6xxx_stats_get_stats(chip, port, data, 947 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 948 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 949 0); 950 } 951 952 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 953 uint64_t *data) 954 { 955 *data++ = chip->ports[port].atu_member_violation; 956 *data++ = chip->ports[port].atu_miss_violation; 957 *data++ = chip->ports[port].atu_full_violation; 958 *data++ = chip->ports[port].vtu_member_violation; 959 *data++ = chip->ports[port].vtu_miss_violation; 960 } 961 962 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 963 uint64_t *data) 964 { 965 int count = 0; 966 967 if (chip->info->ops->stats_get_stats) 968 count = chip->info->ops->stats_get_stats(chip, port, data); 969 970 mutex_lock(&chip->reg_lock); 971 if (chip->info->ops->serdes_get_stats) { 972 data += count; 973 count = chip->info->ops->serdes_get_stats(chip, port, data); 974 } 975 data += count; 976 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 977 mutex_unlock(&chip->reg_lock); 978 } 979 980 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 981 uint64_t *data) 982 { 983 struct mv88e6xxx_chip *chip = ds->priv; 984 int ret; 985 986 mutex_lock(&chip->reg_lock); 987 988 ret = mv88e6xxx_stats_snapshot(chip, port); 989 mutex_unlock(&chip->reg_lock); 990 991 if (ret < 0) 992 return; 993 994 mv88e6xxx_get_stats(chip, port, data); 995 996 } 997 998 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 999 { 1000 return 32 * sizeof(u16); 1001 } 1002 1003 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1004 struct ethtool_regs *regs, void *_p) 1005 { 1006 struct mv88e6xxx_chip *chip = ds->priv; 1007 int err; 1008 u16 reg; 1009 u16 *p = _p; 1010 int i; 1011 1012 regs->version = 0; 1013 1014 memset(p, 0xff, 32 * sizeof(u16)); 1015 1016 mutex_lock(&chip->reg_lock); 1017 1018 for (i = 0; i < 32; i++) { 1019 1020 err = mv88e6xxx_port_read(chip, port, i, ®); 1021 if (!err) 1022 p[i] = reg; 1023 } 1024 1025 mutex_unlock(&chip->reg_lock); 1026 } 1027 1028 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1029 struct ethtool_eee *e) 1030 { 1031 /* Nothing to do on the port's MAC */ 1032 return 0; 1033 } 1034 1035 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1036 struct ethtool_eee *e) 1037 { 1038 /* Nothing to do on the port's MAC */ 1039 return 0; 1040 } 1041 1042 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1043 { 1044 struct dsa_switch *ds = NULL; 1045 struct net_device *br; 1046 u16 pvlan; 1047 int i; 1048 1049 if (dev < DSA_MAX_SWITCHES) 1050 ds = chip->ds->dst->ds[dev]; 1051 1052 /* Prevent frames from unknown switch or port */ 1053 if (!ds || port >= ds->num_ports) 1054 return 0; 1055 1056 /* Frames from DSA links and CPU ports can egress any local port */ 1057 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1058 return mv88e6xxx_port_mask(chip); 1059 1060 br = ds->ports[port].bridge_dev; 1061 pvlan = 0; 1062 1063 /* Frames from user ports can egress any local DSA links and CPU ports, 1064 * as well as any local member of their bridge group. 1065 */ 1066 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1067 if (dsa_is_cpu_port(chip->ds, i) || 1068 dsa_is_dsa_port(chip->ds, i) || 1069 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1070 pvlan |= BIT(i); 1071 1072 return pvlan; 1073 } 1074 1075 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1076 { 1077 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1078 1079 /* prevent frames from going back out of the port they came in on */ 1080 output_ports &= ~BIT(port); 1081 1082 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1083 } 1084 1085 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1086 u8 state) 1087 { 1088 struct mv88e6xxx_chip *chip = ds->priv; 1089 int err; 1090 1091 mutex_lock(&chip->reg_lock); 1092 err = mv88e6xxx_port_set_state(chip, port, state); 1093 mutex_unlock(&chip->reg_lock); 1094 1095 if (err) 1096 dev_err(ds->dev, "p%d: failed to update state\n", port); 1097 } 1098 1099 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1100 { 1101 int err; 1102 1103 if (chip->info->ops->ieee_pri_map) { 1104 err = chip->info->ops->ieee_pri_map(chip); 1105 if (err) 1106 return err; 1107 } 1108 1109 if (chip->info->ops->ip_pri_map) { 1110 err = chip->info->ops->ip_pri_map(chip); 1111 if (err) 1112 return err; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1119 { 1120 int target, port; 1121 int err; 1122 1123 if (!chip->info->global2_addr) 1124 return 0; 1125 1126 /* Initialize the routing port to the 32 possible target devices */ 1127 for (target = 0; target < 32; target++) { 1128 port = 0x1f; 1129 if (target < DSA_MAX_SWITCHES) 1130 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1131 port = chip->ds->rtable[target]; 1132 1133 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1134 if (err) 1135 return err; 1136 } 1137 1138 if (chip->info->ops->set_cascade_port) { 1139 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1140 err = chip->info->ops->set_cascade_port(chip, port); 1141 if (err) 1142 return err; 1143 } 1144 1145 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1146 if (err) 1147 return err; 1148 1149 return 0; 1150 } 1151 1152 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1153 { 1154 /* Clear all trunk masks and mapping */ 1155 if (chip->info->global2_addr) 1156 return mv88e6xxx_g2_trunk_clear(chip); 1157 1158 return 0; 1159 } 1160 1161 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1162 { 1163 if (chip->info->ops->rmu_disable) 1164 return chip->info->ops->rmu_disable(chip); 1165 1166 return 0; 1167 } 1168 1169 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1170 { 1171 if (chip->info->ops->pot_clear) 1172 return chip->info->ops->pot_clear(chip); 1173 1174 return 0; 1175 } 1176 1177 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1178 { 1179 if (chip->info->ops->mgmt_rsvd2cpu) 1180 return chip->info->ops->mgmt_rsvd2cpu(chip); 1181 1182 return 0; 1183 } 1184 1185 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1186 { 1187 int err; 1188 1189 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1190 if (err) 1191 return err; 1192 1193 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1194 if (err) 1195 return err; 1196 1197 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1198 } 1199 1200 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1201 { 1202 int port; 1203 int err; 1204 1205 if (!chip->info->ops->irl_init_all) 1206 return 0; 1207 1208 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1209 /* Disable ingress rate limiting by resetting all per port 1210 * ingress rate limit resources to their initial state. 1211 */ 1212 err = chip->info->ops->irl_init_all(chip, port); 1213 if (err) 1214 return err; 1215 } 1216 1217 return 0; 1218 } 1219 1220 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1221 { 1222 if (chip->info->ops->set_switch_mac) { 1223 u8 addr[ETH_ALEN]; 1224 1225 eth_random_addr(addr); 1226 1227 return chip->info->ops->set_switch_mac(chip, addr); 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1234 { 1235 u16 pvlan = 0; 1236 1237 if (!mv88e6xxx_has_pvt(chip)) 1238 return -EOPNOTSUPP; 1239 1240 /* Skip the local source device, which uses in-chip port VLAN */ 1241 if (dev != chip->ds->index) 1242 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1243 1244 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1245 } 1246 1247 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1248 { 1249 int dev, port; 1250 int err; 1251 1252 if (!mv88e6xxx_has_pvt(chip)) 1253 return 0; 1254 1255 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1256 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1257 */ 1258 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1259 if (err) 1260 return err; 1261 1262 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1263 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1264 err = mv88e6xxx_pvt_map(chip, dev, port); 1265 if (err) 1266 return err; 1267 } 1268 } 1269 1270 return 0; 1271 } 1272 1273 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1274 { 1275 struct mv88e6xxx_chip *chip = ds->priv; 1276 int err; 1277 1278 mutex_lock(&chip->reg_lock); 1279 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1280 mutex_unlock(&chip->reg_lock); 1281 1282 if (err) 1283 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1284 } 1285 1286 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1287 { 1288 if (!chip->info->max_vid) 1289 return 0; 1290 1291 return mv88e6xxx_g1_vtu_flush(chip); 1292 } 1293 1294 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1295 struct mv88e6xxx_vtu_entry *entry) 1296 { 1297 if (!chip->info->ops->vtu_getnext) 1298 return -EOPNOTSUPP; 1299 1300 return chip->info->ops->vtu_getnext(chip, entry); 1301 } 1302 1303 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1304 struct mv88e6xxx_vtu_entry *entry) 1305 { 1306 if (!chip->info->ops->vtu_loadpurge) 1307 return -EOPNOTSUPP; 1308 1309 return chip->info->ops->vtu_loadpurge(chip, entry); 1310 } 1311 1312 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1313 { 1314 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1315 struct mv88e6xxx_vtu_entry vlan = { 1316 .vid = chip->info->max_vid, 1317 }; 1318 int i, err; 1319 1320 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1321 1322 /* Set every FID bit used by the (un)bridged ports */ 1323 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1324 err = mv88e6xxx_port_get_fid(chip, i, fid); 1325 if (err) 1326 return err; 1327 1328 set_bit(*fid, fid_bitmap); 1329 } 1330 1331 /* Set every FID bit used by the VLAN entries */ 1332 do { 1333 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1334 if (err) 1335 return err; 1336 1337 if (!vlan.valid) 1338 break; 1339 1340 set_bit(vlan.fid, fid_bitmap); 1341 } while (vlan.vid < chip->info->max_vid); 1342 1343 /* The reset value 0x000 is used to indicate that multiple address 1344 * databases are not needed. Return the next positive available. 1345 */ 1346 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1347 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1348 return -ENOSPC; 1349 1350 /* Clear the database */ 1351 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1352 } 1353 1354 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1355 struct mv88e6xxx_vtu_entry *entry, bool new) 1356 { 1357 int err; 1358 1359 if (!vid) 1360 return -EINVAL; 1361 1362 entry->vid = vid - 1; 1363 entry->valid = false; 1364 1365 err = mv88e6xxx_vtu_getnext(chip, entry); 1366 if (err) 1367 return err; 1368 1369 if (entry->vid == vid && entry->valid) 1370 return 0; 1371 1372 if (new) { 1373 int i; 1374 1375 /* Initialize a fresh VLAN entry */ 1376 memset(entry, 0, sizeof(*entry)); 1377 entry->valid = true; 1378 entry->vid = vid; 1379 1380 /* Exclude all ports */ 1381 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1382 entry->member[i] = 1383 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1384 1385 return mv88e6xxx_atu_new(chip, &entry->fid); 1386 } 1387 1388 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1389 return -EOPNOTSUPP; 1390 } 1391 1392 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1393 u16 vid_begin, u16 vid_end) 1394 { 1395 struct mv88e6xxx_chip *chip = ds->priv; 1396 struct mv88e6xxx_vtu_entry vlan = { 1397 .vid = vid_begin - 1, 1398 }; 1399 int i, err; 1400 1401 /* DSA and CPU ports have to be members of multiple vlans */ 1402 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1403 return 0; 1404 1405 if (!vid_begin) 1406 return -EOPNOTSUPP; 1407 1408 mutex_lock(&chip->reg_lock); 1409 1410 do { 1411 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1412 if (err) 1413 goto unlock; 1414 1415 if (!vlan.valid) 1416 break; 1417 1418 if (vlan.vid > vid_end) 1419 break; 1420 1421 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1422 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1423 continue; 1424 1425 if (!ds->ports[i].slave) 1426 continue; 1427 1428 if (vlan.member[i] == 1429 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1430 continue; 1431 1432 if (dsa_to_port(ds, i)->bridge_dev == 1433 ds->ports[port].bridge_dev) 1434 break; /* same bridge, check next VLAN */ 1435 1436 if (!dsa_to_port(ds, i)->bridge_dev) 1437 continue; 1438 1439 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1440 port, vlan.vid, i, 1441 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1442 err = -EOPNOTSUPP; 1443 goto unlock; 1444 } 1445 } while (vlan.vid < vid_end); 1446 1447 unlock: 1448 mutex_unlock(&chip->reg_lock); 1449 1450 return err; 1451 } 1452 1453 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1454 bool vlan_filtering) 1455 { 1456 struct mv88e6xxx_chip *chip = ds->priv; 1457 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1458 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1459 int err; 1460 1461 if (!chip->info->max_vid) 1462 return -EOPNOTSUPP; 1463 1464 mutex_lock(&chip->reg_lock); 1465 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1466 mutex_unlock(&chip->reg_lock); 1467 1468 return err; 1469 } 1470 1471 static int 1472 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1473 const struct switchdev_obj_port_vlan *vlan) 1474 { 1475 struct mv88e6xxx_chip *chip = ds->priv; 1476 int err; 1477 1478 if (!chip->info->max_vid) 1479 return -EOPNOTSUPP; 1480 1481 /* If the requested port doesn't belong to the same bridge as the VLAN 1482 * members, do not support it (yet) and fallback to software VLAN. 1483 */ 1484 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1485 vlan->vid_end); 1486 if (err) 1487 return err; 1488 1489 /* We don't need any dynamic resource from the kernel (yet), 1490 * so skip the prepare phase. 1491 */ 1492 return 0; 1493 } 1494 1495 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1496 const unsigned char *addr, u16 vid, 1497 u8 state) 1498 { 1499 struct mv88e6xxx_vtu_entry vlan; 1500 struct mv88e6xxx_atu_entry entry; 1501 int err; 1502 1503 /* Null VLAN ID corresponds to the port private database */ 1504 if (vid == 0) 1505 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1506 else 1507 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1508 if (err) 1509 return err; 1510 1511 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1512 ether_addr_copy(entry.mac, addr); 1513 eth_addr_dec(entry.mac); 1514 1515 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1516 if (err) 1517 return err; 1518 1519 /* Initialize a fresh ATU entry if it isn't found */ 1520 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1521 !ether_addr_equal(entry.mac, addr)) { 1522 memset(&entry, 0, sizeof(entry)); 1523 ether_addr_copy(entry.mac, addr); 1524 } 1525 1526 /* Purge the ATU entry only if no port is using it anymore */ 1527 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1528 entry.portvec &= ~BIT(port); 1529 if (!entry.portvec) 1530 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1531 } else { 1532 entry.portvec |= BIT(port); 1533 entry.state = state; 1534 } 1535 1536 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1537 } 1538 1539 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1540 u16 vid) 1541 { 1542 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1543 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1544 1545 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1546 } 1547 1548 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1549 { 1550 int port; 1551 int err; 1552 1553 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1554 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1555 if (err) 1556 return err; 1557 } 1558 1559 return 0; 1560 } 1561 1562 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1563 u16 vid, u8 member) 1564 { 1565 struct mv88e6xxx_vtu_entry vlan; 1566 int err; 1567 1568 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1569 if (err) 1570 return err; 1571 1572 vlan.member[port] = member; 1573 1574 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1575 if (err) 1576 return err; 1577 1578 return mv88e6xxx_broadcast_setup(chip, vid); 1579 } 1580 1581 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1582 const struct switchdev_obj_port_vlan *vlan) 1583 { 1584 struct mv88e6xxx_chip *chip = ds->priv; 1585 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1586 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1587 u8 member; 1588 u16 vid; 1589 1590 if (!chip->info->max_vid) 1591 return; 1592 1593 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1594 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1595 else if (untagged) 1596 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1597 else 1598 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1599 1600 mutex_lock(&chip->reg_lock); 1601 1602 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1603 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1604 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1605 vid, untagged ? 'u' : 't'); 1606 1607 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1608 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1609 vlan->vid_end); 1610 1611 mutex_unlock(&chip->reg_lock); 1612 } 1613 1614 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1615 int port, u16 vid) 1616 { 1617 struct mv88e6xxx_vtu_entry vlan; 1618 int i, err; 1619 1620 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1621 if (err) 1622 return err; 1623 1624 /* Tell switchdev if this VLAN is handled in software */ 1625 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1626 return -EOPNOTSUPP; 1627 1628 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1629 1630 /* keep the VLAN unless all ports are excluded */ 1631 vlan.valid = false; 1632 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1633 if (vlan.member[i] != 1634 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1635 vlan.valid = true; 1636 break; 1637 } 1638 } 1639 1640 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1641 if (err) 1642 return err; 1643 1644 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1645 } 1646 1647 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1648 const struct switchdev_obj_port_vlan *vlan) 1649 { 1650 struct mv88e6xxx_chip *chip = ds->priv; 1651 u16 pvid, vid; 1652 int err = 0; 1653 1654 if (!chip->info->max_vid) 1655 return -EOPNOTSUPP; 1656 1657 mutex_lock(&chip->reg_lock); 1658 1659 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1660 if (err) 1661 goto unlock; 1662 1663 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1664 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1665 if (err) 1666 goto unlock; 1667 1668 if (vid == pvid) { 1669 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1670 if (err) 1671 goto unlock; 1672 } 1673 } 1674 1675 unlock: 1676 mutex_unlock(&chip->reg_lock); 1677 1678 return err; 1679 } 1680 1681 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1682 const unsigned char *addr, u16 vid) 1683 { 1684 struct mv88e6xxx_chip *chip = ds->priv; 1685 int err; 1686 1687 mutex_lock(&chip->reg_lock); 1688 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1689 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1690 mutex_unlock(&chip->reg_lock); 1691 1692 return err; 1693 } 1694 1695 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1696 const unsigned char *addr, u16 vid) 1697 { 1698 struct mv88e6xxx_chip *chip = ds->priv; 1699 int err; 1700 1701 mutex_lock(&chip->reg_lock); 1702 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1703 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1704 mutex_unlock(&chip->reg_lock); 1705 1706 return err; 1707 } 1708 1709 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1710 u16 fid, u16 vid, int port, 1711 dsa_fdb_dump_cb_t *cb, void *data) 1712 { 1713 struct mv88e6xxx_atu_entry addr; 1714 bool is_static; 1715 int err; 1716 1717 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1718 eth_broadcast_addr(addr.mac); 1719 1720 do { 1721 mutex_lock(&chip->reg_lock); 1722 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1723 mutex_unlock(&chip->reg_lock); 1724 if (err) 1725 return err; 1726 1727 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1728 break; 1729 1730 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1731 continue; 1732 1733 if (!is_unicast_ether_addr(addr.mac)) 1734 continue; 1735 1736 is_static = (addr.state == 1737 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1738 err = cb(addr.mac, vid, is_static, data); 1739 if (err) 1740 return err; 1741 } while (!is_broadcast_ether_addr(addr.mac)); 1742 1743 return err; 1744 } 1745 1746 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1747 dsa_fdb_dump_cb_t *cb, void *data) 1748 { 1749 struct mv88e6xxx_vtu_entry vlan = { 1750 .vid = chip->info->max_vid, 1751 }; 1752 u16 fid; 1753 int err; 1754 1755 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1756 mutex_lock(&chip->reg_lock); 1757 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1758 mutex_unlock(&chip->reg_lock); 1759 1760 if (err) 1761 return err; 1762 1763 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1764 if (err) 1765 return err; 1766 1767 /* Dump VLANs' Filtering Information Databases */ 1768 do { 1769 mutex_lock(&chip->reg_lock); 1770 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1771 mutex_unlock(&chip->reg_lock); 1772 if (err) 1773 return err; 1774 1775 if (!vlan.valid) 1776 break; 1777 1778 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1779 cb, data); 1780 if (err) 1781 return err; 1782 } while (vlan.vid < chip->info->max_vid); 1783 1784 return err; 1785 } 1786 1787 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1788 dsa_fdb_dump_cb_t *cb, void *data) 1789 { 1790 struct mv88e6xxx_chip *chip = ds->priv; 1791 1792 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1793 } 1794 1795 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1796 struct net_device *br) 1797 { 1798 struct dsa_switch *ds; 1799 int port; 1800 int dev; 1801 int err; 1802 1803 /* Remap the Port VLAN of each local bridge group member */ 1804 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1805 if (chip->ds->ports[port].bridge_dev == br) { 1806 err = mv88e6xxx_port_vlan_map(chip, port); 1807 if (err) 1808 return err; 1809 } 1810 } 1811 1812 if (!mv88e6xxx_has_pvt(chip)) 1813 return 0; 1814 1815 /* Remap the Port VLAN of each cross-chip bridge group member */ 1816 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1817 ds = chip->ds->dst->ds[dev]; 1818 if (!ds) 1819 break; 1820 1821 for (port = 0; port < ds->num_ports; ++port) { 1822 if (ds->ports[port].bridge_dev == br) { 1823 err = mv88e6xxx_pvt_map(chip, dev, port); 1824 if (err) 1825 return err; 1826 } 1827 } 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1834 struct net_device *br) 1835 { 1836 struct mv88e6xxx_chip *chip = ds->priv; 1837 int err; 1838 1839 mutex_lock(&chip->reg_lock); 1840 err = mv88e6xxx_bridge_map(chip, br); 1841 mutex_unlock(&chip->reg_lock); 1842 1843 return err; 1844 } 1845 1846 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1847 struct net_device *br) 1848 { 1849 struct mv88e6xxx_chip *chip = ds->priv; 1850 1851 mutex_lock(&chip->reg_lock); 1852 if (mv88e6xxx_bridge_map(chip, br) || 1853 mv88e6xxx_port_vlan_map(chip, port)) 1854 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1855 mutex_unlock(&chip->reg_lock); 1856 } 1857 1858 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1859 int port, struct net_device *br) 1860 { 1861 struct mv88e6xxx_chip *chip = ds->priv; 1862 int err; 1863 1864 if (!mv88e6xxx_has_pvt(chip)) 1865 return 0; 1866 1867 mutex_lock(&chip->reg_lock); 1868 err = mv88e6xxx_pvt_map(chip, dev, port); 1869 mutex_unlock(&chip->reg_lock); 1870 1871 return err; 1872 } 1873 1874 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1875 int port, struct net_device *br) 1876 { 1877 struct mv88e6xxx_chip *chip = ds->priv; 1878 1879 if (!mv88e6xxx_has_pvt(chip)) 1880 return; 1881 1882 mutex_lock(&chip->reg_lock); 1883 if (mv88e6xxx_pvt_map(chip, dev, port)) 1884 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1885 mutex_unlock(&chip->reg_lock); 1886 } 1887 1888 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1889 { 1890 if (chip->info->ops->reset) 1891 return chip->info->ops->reset(chip); 1892 1893 return 0; 1894 } 1895 1896 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1897 { 1898 struct gpio_desc *gpiod = chip->reset; 1899 1900 /* If there is a GPIO connected to the reset pin, toggle it */ 1901 if (gpiod) { 1902 gpiod_set_value_cansleep(gpiod, 1); 1903 usleep_range(10000, 20000); 1904 gpiod_set_value_cansleep(gpiod, 0); 1905 usleep_range(10000, 20000); 1906 } 1907 } 1908 1909 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1910 { 1911 int i, err; 1912 1913 /* Set all ports to the Disabled state */ 1914 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1915 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1916 if (err) 1917 return err; 1918 } 1919 1920 /* Wait for transmit queues to drain, 1921 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1922 */ 1923 usleep_range(2000, 4000); 1924 1925 return 0; 1926 } 1927 1928 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1929 { 1930 int err; 1931 1932 err = mv88e6xxx_disable_ports(chip); 1933 if (err) 1934 return err; 1935 1936 mv88e6xxx_hardware_reset(chip); 1937 1938 return mv88e6xxx_software_reset(chip); 1939 } 1940 1941 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1942 enum mv88e6xxx_frame_mode frame, 1943 enum mv88e6xxx_egress_mode egress, u16 etype) 1944 { 1945 int err; 1946 1947 if (!chip->info->ops->port_set_frame_mode) 1948 return -EOPNOTSUPP; 1949 1950 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1951 if (err) 1952 return err; 1953 1954 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1955 if (err) 1956 return err; 1957 1958 if (chip->info->ops->port_set_ether_type) 1959 return chip->info->ops->port_set_ether_type(chip, port, etype); 1960 1961 return 0; 1962 } 1963 1964 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1965 { 1966 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1967 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1968 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1969 } 1970 1971 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1972 { 1973 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1974 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1975 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1976 } 1977 1978 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1979 { 1980 return mv88e6xxx_set_port_mode(chip, port, 1981 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1982 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1983 ETH_P_EDSA); 1984 } 1985 1986 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1987 { 1988 if (dsa_is_dsa_port(chip->ds, port)) 1989 return mv88e6xxx_set_port_mode_dsa(chip, port); 1990 1991 if (dsa_is_user_port(chip->ds, port)) 1992 return mv88e6xxx_set_port_mode_normal(chip, port); 1993 1994 /* Setup CPU port mode depending on its supported tag format */ 1995 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1996 return mv88e6xxx_set_port_mode_dsa(chip, port); 1997 1998 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1999 return mv88e6xxx_set_port_mode_edsa(chip, port); 2000 2001 return -EINVAL; 2002 } 2003 2004 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2005 { 2006 bool message = dsa_is_dsa_port(chip->ds, port); 2007 2008 return mv88e6xxx_port_set_message_port(chip, port, message); 2009 } 2010 2011 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2012 { 2013 struct dsa_switch *ds = chip->ds; 2014 bool flood; 2015 2016 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2017 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2018 if (chip->info->ops->port_set_egress_floods) 2019 return chip->info->ops->port_set_egress_floods(chip, port, 2020 flood, flood); 2021 2022 return 0; 2023 } 2024 2025 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2026 bool on) 2027 { 2028 if (chip->info->ops->serdes_power) 2029 return chip->info->ops->serdes_power(chip, port, on); 2030 2031 return 0; 2032 } 2033 2034 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2035 { 2036 struct dsa_switch *ds = chip->ds; 2037 int upstream_port; 2038 int err; 2039 2040 upstream_port = dsa_upstream_port(ds, port); 2041 if (chip->info->ops->port_set_upstream_port) { 2042 err = chip->info->ops->port_set_upstream_port(chip, port, 2043 upstream_port); 2044 if (err) 2045 return err; 2046 } 2047 2048 if (port == upstream_port) { 2049 if (chip->info->ops->set_cpu_port) { 2050 err = chip->info->ops->set_cpu_port(chip, 2051 upstream_port); 2052 if (err) 2053 return err; 2054 } 2055 2056 if (chip->info->ops->set_egress_port) { 2057 err = chip->info->ops->set_egress_port(chip, 2058 upstream_port); 2059 if (err) 2060 return err; 2061 } 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2068 { 2069 struct dsa_switch *ds = chip->ds; 2070 int err; 2071 u16 reg; 2072 2073 /* MAC Forcing register: don't force link, speed, duplex or flow control 2074 * state to any particular values on physical ports, but force the CPU 2075 * port and all DSA ports to their maximum bandwidth and full duplex. 2076 */ 2077 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2078 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2079 SPEED_MAX, DUPLEX_FULL, 2080 PHY_INTERFACE_MODE_NA); 2081 else 2082 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2083 SPEED_UNFORCED, DUPLEX_UNFORCED, 2084 PHY_INTERFACE_MODE_NA); 2085 if (err) 2086 return err; 2087 2088 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2089 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2090 * tunneling, determine priority by looking at 802.1p and IP 2091 * priority fields (IP prio has precedence), and set STP state 2092 * to Forwarding. 2093 * 2094 * If this is the CPU link, use DSA or EDSA tagging depending 2095 * on which tagging mode was configured. 2096 * 2097 * If this is a link to another switch, use DSA tagging mode. 2098 * 2099 * If this is the upstream port for this switch, enable 2100 * forwarding of unknown unicasts and multicasts. 2101 */ 2102 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2103 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2104 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2105 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2106 if (err) 2107 return err; 2108 2109 err = mv88e6xxx_setup_port_mode(chip, port); 2110 if (err) 2111 return err; 2112 2113 err = mv88e6xxx_setup_egress_floods(chip, port); 2114 if (err) 2115 return err; 2116 2117 /* Enable the SERDES interface for DSA and CPU ports. Normal 2118 * ports SERDES are enabled when the port is enabled, thus 2119 * saving a bit of power. 2120 */ 2121 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2122 err = mv88e6xxx_serdes_power(chip, port, true); 2123 if (err) 2124 return err; 2125 } 2126 2127 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2128 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2129 * untagged frames on this port, do a destination address lookup on all 2130 * received packets as usual, disable ARP mirroring and don't send a 2131 * copy of all transmitted/received frames on this port to the CPU. 2132 */ 2133 err = mv88e6xxx_port_set_map_da(chip, port); 2134 if (err) 2135 return err; 2136 2137 err = mv88e6xxx_setup_upstream_port(chip, port); 2138 if (err) 2139 return err; 2140 2141 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2142 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2143 if (err) 2144 return err; 2145 2146 if (chip->info->ops->port_set_jumbo_size) { 2147 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2148 if (err) 2149 return err; 2150 } 2151 2152 /* Port Association Vector: when learning source addresses 2153 * of packets, add the address to the address database using 2154 * a port bitmap that has only the bit for this port set and 2155 * the other bits clear. 2156 */ 2157 reg = 1 << port; 2158 /* Disable learning for CPU port */ 2159 if (dsa_is_cpu_port(ds, port)) 2160 reg = 0; 2161 2162 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2163 reg); 2164 if (err) 2165 return err; 2166 2167 /* Egress rate control 2: disable egress rate control. */ 2168 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2169 0x0000); 2170 if (err) 2171 return err; 2172 2173 if (chip->info->ops->port_pause_limit) { 2174 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2175 if (err) 2176 return err; 2177 } 2178 2179 if (chip->info->ops->port_disable_learn_limit) { 2180 err = chip->info->ops->port_disable_learn_limit(chip, port); 2181 if (err) 2182 return err; 2183 } 2184 2185 if (chip->info->ops->port_disable_pri_override) { 2186 err = chip->info->ops->port_disable_pri_override(chip, port); 2187 if (err) 2188 return err; 2189 } 2190 2191 if (chip->info->ops->port_tag_remap) { 2192 err = chip->info->ops->port_tag_remap(chip, port); 2193 if (err) 2194 return err; 2195 } 2196 2197 if (chip->info->ops->port_egress_rate_limiting) { 2198 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2199 if (err) 2200 return err; 2201 } 2202 2203 err = mv88e6xxx_setup_message_port(chip, port); 2204 if (err) 2205 return err; 2206 2207 /* Port based VLAN map: give each port the same default address 2208 * database, and allow bidirectional communication between the 2209 * CPU and DSA port(s), and the other ports. 2210 */ 2211 err = mv88e6xxx_port_set_fid(chip, port, 0); 2212 if (err) 2213 return err; 2214 2215 err = mv88e6xxx_port_vlan_map(chip, port); 2216 if (err) 2217 return err; 2218 2219 /* Default VLAN ID and priority: don't set a default VLAN 2220 * ID, and set the default packet priority to zero. 2221 */ 2222 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2223 } 2224 2225 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2226 struct phy_device *phydev) 2227 { 2228 struct mv88e6xxx_chip *chip = ds->priv; 2229 int err; 2230 2231 mutex_lock(&chip->reg_lock); 2232 err = mv88e6xxx_serdes_power(chip, port, true); 2233 mutex_unlock(&chip->reg_lock); 2234 2235 return err; 2236 } 2237 2238 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2239 struct phy_device *phydev) 2240 { 2241 struct mv88e6xxx_chip *chip = ds->priv; 2242 2243 mutex_lock(&chip->reg_lock); 2244 if (mv88e6xxx_serdes_power(chip, port, false)) 2245 dev_err(chip->dev, "failed to power off SERDES\n"); 2246 mutex_unlock(&chip->reg_lock); 2247 } 2248 2249 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2250 unsigned int ageing_time) 2251 { 2252 struct mv88e6xxx_chip *chip = ds->priv; 2253 int err; 2254 2255 mutex_lock(&chip->reg_lock); 2256 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2257 mutex_unlock(&chip->reg_lock); 2258 2259 return err; 2260 } 2261 2262 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2263 { 2264 int err; 2265 2266 /* Initialize the statistics unit */ 2267 if (chip->info->ops->stats_set_histogram) { 2268 err = chip->info->ops->stats_set_histogram(chip); 2269 if (err) 2270 return err; 2271 } 2272 2273 return mv88e6xxx_g1_stats_clear(chip); 2274 } 2275 2276 static int mv88e6xxx_setup(struct dsa_switch *ds) 2277 { 2278 struct mv88e6xxx_chip *chip = ds->priv; 2279 int err; 2280 int i; 2281 2282 chip->ds = ds; 2283 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2284 2285 mutex_lock(&chip->reg_lock); 2286 2287 /* Setup Switch Port Registers */ 2288 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2289 if (dsa_is_unused_port(ds, i)) 2290 continue; 2291 2292 err = mv88e6xxx_setup_port(chip, i); 2293 if (err) 2294 goto unlock; 2295 } 2296 2297 err = mv88e6xxx_irl_setup(chip); 2298 if (err) 2299 goto unlock; 2300 2301 err = mv88e6xxx_mac_setup(chip); 2302 if (err) 2303 goto unlock; 2304 2305 err = mv88e6xxx_phy_setup(chip); 2306 if (err) 2307 goto unlock; 2308 2309 err = mv88e6xxx_vtu_setup(chip); 2310 if (err) 2311 goto unlock; 2312 2313 err = mv88e6xxx_pvt_setup(chip); 2314 if (err) 2315 goto unlock; 2316 2317 err = mv88e6xxx_atu_setup(chip); 2318 if (err) 2319 goto unlock; 2320 2321 err = mv88e6xxx_broadcast_setup(chip, 0); 2322 if (err) 2323 goto unlock; 2324 2325 err = mv88e6xxx_pot_setup(chip); 2326 if (err) 2327 goto unlock; 2328 2329 err = mv88e6xxx_rmu_setup(chip); 2330 if (err) 2331 goto unlock; 2332 2333 err = mv88e6xxx_rsvd2cpu_setup(chip); 2334 if (err) 2335 goto unlock; 2336 2337 err = mv88e6xxx_trunk_setup(chip); 2338 if (err) 2339 goto unlock; 2340 2341 err = mv88e6xxx_devmap_setup(chip); 2342 if (err) 2343 goto unlock; 2344 2345 err = mv88e6xxx_pri_setup(chip); 2346 if (err) 2347 goto unlock; 2348 2349 /* Setup PTP Hardware Clock and timestamping */ 2350 if (chip->info->ptp_support) { 2351 err = mv88e6xxx_ptp_setup(chip); 2352 if (err) 2353 goto unlock; 2354 2355 err = mv88e6xxx_hwtstamp_setup(chip); 2356 if (err) 2357 goto unlock; 2358 } 2359 2360 err = mv88e6xxx_stats_setup(chip); 2361 if (err) 2362 goto unlock; 2363 2364 unlock: 2365 mutex_unlock(&chip->reg_lock); 2366 2367 return err; 2368 } 2369 2370 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2371 { 2372 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2373 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2374 u16 val; 2375 int err; 2376 2377 if (!chip->info->ops->phy_read) 2378 return -EOPNOTSUPP; 2379 2380 mutex_lock(&chip->reg_lock); 2381 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2382 mutex_unlock(&chip->reg_lock); 2383 2384 if (reg == MII_PHYSID2) { 2385 /* Some internal PHYS don't have a model number. Use 2386 * the mv88e6390 family model number instead. 2387 */ 2388 if (!(val & 0x3f0)) 2389 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2390 } 2391 2392 return err ? err : val; 2393 } 2394 2395 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2396 { 2397 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2398 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2399 int err; 2400 2401 if (!chip->info->ops->phy_write) 2402 return -EOPNOTSUPP; 2403 2404 mutex_lock(&chip->reg_lock); 2405 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2406 mutex_unlock(&chip->reg_lock); 2407 2408 return err; 2409 } 2410 2411 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2412 struct device_node *np, 2413 bool external) 2414 { 2415 static int index; 2416 struct mv88e6xxx_mdio_bus *mdio_bus; 2417 struct mii_bus *bus; 2418 int err; 2419 2420 if (external) { 2421 mutex_lock(&chip->reg_lock); 2422 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2423 mutex_unlock(&chip->reg_lock); 2424 2425 if (err) 2426 return err; 2427 } 2428 2429 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2430 if (!bus) 2431 return -ENOMEM; 2432 2433 mdio_bus = bus->priv; 2434 mdio_bus->bus = bus; 2435 mdio_bus->chip = chip; 2436 INIT_LIST_HEAD(&mdio_bus->list); 2437 mdio_bus->external = external; 2438 2439 if (np) { 2440 bus->name = np->full_name; 2441 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2442 } else { 2443 bus->name = "mv88e6xxx SMI"; 2444 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2445 } 2446 2447 bus->read = mv88e6xxx_mdio_read; 2448 bus->write = mv88e6xxx_mdio_write; 2449 bus->parent = chip->dev; 2450 2451 if (!external) { 2452 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2453 if (err) 2454 return err; 2455 } 2456 2457 err = of_mdiobus_register(bus, np); 2458 if (err) { 2459 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2460 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2461 return err; 2462 } 2463 2464 if (external) 2465 list_add_tail(&mdio_bus->list, &chip->mdios); 2466 else 2467 list_add(&mdio_bus->list, &chip->mdios); 2468 2469 return 0; 2470 } 2471 2472 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2473 { .compatible = "marvell,mv88e6xxx-mdio-external", 2474 .data = (void *)true }, 2475 { }, 2476 }; 2477 2478 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2479 2480 { 2481 struct mv88e6xxx_mdio_bus *mdio_bus; 2482 struct mii_bus *bus; 2483 2484 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2485 bus = mdio_bus->bus; 2486 2487 if (!mdio_bus->external) 2488 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2489 2490 mdiobus_unregister(bus); 2491 } 2492 } 2493 2494 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2495 struct device_node *np) 2496 { 2497 const struct of_device_id *match; 2498 struct device_node *child; 2499 int err; 2500 2501 /* Always register one mdio bus for the internal/default mdio 2502 * bus. This maybe represented in the device tree, but is 2503 * optional. 2504 */ 2505 child = of_get_child_by_name(np, "mdio"); 2506 err = mv88e6xxx_mdio_register(chip, child, false); 2507 if (err) 2508 return err; 2509 2510 /* Walk the device tree, and see if there are any other nodes 2511 * which say they are compatible with the external mdio 2512 * bus. 2513 */ 2514 for_each_available_child_of_node(np, child) { 2515 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2516 if (match) { 2517 err = mv88e6xxx_mdio_register(chip, child, true); 2518 if (err) { 2519 mv88e6xxx_mdios_unregister(chip); 2520 return err; 2521 } 2522 } 2523 } 2524 2525 return 0; 2526 } 2527 2528 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2529 { 2530 struct mv88e6xxx_chip *chip = ds->priv; 2531 2532 return chip->eeprom_len; 2533 } 2534 2535 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2536 struct ethtool_eeprom *eeprom, u8 *data) 2537 { 2538 struct mv88e6xxx_chip *chip = ds->priv; 2539 int err; 2540 2541 if (!chip->info->ops->get_eeprom) 2542 return -EOPNOTSUPP; 2543 2544 mutex_lock(&chip->reg_lock); 2545 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2546 mutex_unlock(&chip->reg_lock); 2547 2548 if (err) 2549 return err; 2550 2551 eeprom->magic = 0xc3ec4951; 2552 2553 return 0; 2554 } 2555 2556 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2557 struct ethtool_eeprom *eeprom, u8 *data) 2558 { 2559 struct mv88e6xxx_chip *chip = ds->priv; 2560 int err; 2561 2562 if (!chip->info->ops->set_eeprom) 2563 return -EOPNOTSUPP; 2564 2565 if (eeprom->magic != 0xc3ec4951) 2566 return -EINVAL; 2567 2568 mutex_lock(&chip->reg_lock); 2569 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2570 mutex_unlock(&chip->reg_lock); 2571 2572 return err; 2573 } 2574 2575 static const struct mv88e6xxx_ops mv88e6085_ops = { 2576 /* MV88E6XXX_FAMILY_6097 */ 2577 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2578 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2579 .irl_init_all = mv88e6352_g2_irl_init_all, 2580 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2581 .phy_read = mv88e6185_phy_ppu_read, 2582 .phy_write = mv88e6185_phy_ppu_write, 2583 .port_set_link = mv88e6xxx_port_set_link, 2584 .port_set_duplex = mv88e6xxx_port_set_duplex, 2585 .port_set_speed = mv88e6185_port_set_speed, 2586 .port_tag_remap = mv88e6095_port_tag_remap, 2587 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2588 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2589 .port_set_ether_type = mv88e6351_port_set_ether_type, 2590 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2591 .port_pause_limit = mv88e6097_port_pause_limit, 2592 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2593 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2594 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2595 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2596 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2597 .stats_get_strings = mv88e6095_stats_get_strings, 2598 .stats_get_stats = mv88e6095_stats_get_stats, 2599 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2600 .set_egress_port = mv88e6095_g1_set_egress_port, 2601 .watchdog_ops = &mv88e6097_watchdog_ops, 2602 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2603 .pot_clear = mv88e6xxx_g2_pot_clear, 2604 .ppu_enable = mv88e6185_g1_ppu_enable, 2605 .ppu_disable = mv88e6185_g1_ppu_disable, 2606 .reset = mv88e6185_g1_reset, 2607 .rmu_disable = mv88e6085_g1_rmu_disable, 2608 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2609 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2610 .serdes_power = mv88e6341_serdes_power, 2611 }; 2612 2613 static const struct mv88e6xxx_ops mv88e6095_ops = { 2614 /* MV88E6XXX_FAMILY_6095 */ 2615 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2616 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2617 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2618 .phy_read = mv88e6185_phy_ppu_read, 2619 .phy_write = mv88e6185_phy_ppu_write, 2620 .port_set_link = mv88e6xxx_port_set_link, 2621 .port_set_duplex = mv88e6xxx_port_set_duplex, 2622 .port_set_speed = mv88e6185_port_set_speed, 2623 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2624 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2625 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2626 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2627 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2628 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2629 .stats_get_strings = mv88e6095_stats_get_strings, 2630 .stats_get_stats = mv88e6095_stats_get_stats, 2631 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2632 .ppu_enable = mv88e6185_g1_ppu_enable, 2633 .ppu_disable = mv88e6185_g1_ppu_disable, 2634 .reset = mv88e6185_g1_reset, 2635 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2636 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2637 }; 2638 2639 static const struct mv88e6xxx_ops mv88e6097_ops = { 2640 /* MV88E6XXX_FAMILY_6097 */ 2641 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2642 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2643 .irl_init_all = mv88e6352_g2_irl_init_all, 2644 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2645 .phy_read = mv88e6xxx_g2_smi_phy_read, 2646 .phy_write = mv88e6xxx_g2_smi_phy_write, 2647 .port_set_link = mv88e6xxx_port_set_link, 2648 .port_set_duplex = mv88e6xxx_port_set_duplex, 2649 .port_set_speed = mv88e6185_port_set_speed, 2650 .port_tag_remap = mv88e6095_port_tag_remap, 2651 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2652 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2653 .port_set_ether_type = mv88e6351_port_set_ether_type, 2654 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2655 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2656 .port_pause_limit = mv88e6097_port_pause_limit, 2657 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2658 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2659 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2660 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2661 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2662 .stats_get_strings = mv88e6095_stats_get_strings, 2663 .stats_get_stats = mv88e6095_stats_get_stats, 2664 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2665 .set_egress_port = mv88e6095_g1_set_egress_port, 2666 .watchdog_ops = &mv88e6097_watchdog_ops, 2667 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2668 .pot_clear = mv88e6xxx_g2_pot_clear, 2669 .reset = mv88e6352_g1_reset, 2670 .rmu_disable = mv88e6085_g1_rmu_disable, 2671 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2672 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2673 }; 2674 2675 static const struct mv88e6xxx_ops mv88e6123_ops = { 2676 /* MV88E6XXX_FAMILY_6165 */ 2677 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2678 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2679 .irl_init_all = mv88e6352_g2_irl_init_all, 2680 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2681 .phy_read = mv88e6xxx_g2_smi_phy_read, 2682 .phy_write = mv88e6xxx_g2_smi_phy_write, 2683 .port_set_link = mv88e6xxx_port_set_link, 2684 .port_set_duplex = mv88e6xxx_port_set_duplex, 2685 .port_set_speed = mv88e6185_port_set_speed, 2686 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2687 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2688 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2689 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2690 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2692 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2693 .stats_get_strings = mv88e6095_stats_get_strings, 2694 .stats_get_stats = mv88e6095_stats_get_stats, 2695 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2696 .set_egress_port = mv88e6095_g1_set_egress_port, 2697 .watchdog_ops = &mv88e6097_watchdog_ops, 2698 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2699 .pot_clear = mv88e6xxx_g2_pot_clear, 2700 .reset = mv88e6352_g1_reset, 2701 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2702 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2703 }; 2704 2705 static const struct mv88e6xxx_ops mv88e6131_ops = { 2706 /* MV88E6XXX_FAMILY_6185 */ 2707 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2708 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2709 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2710 .phy_read = mv88e6185_phy_ppu_read, 2711 .phy_write = mv88e6185_phy_ppu_write, 2712 .port_set_link = mv88e6xxx_port_set_link, 2713 .port_set_duplex = mv88e6xxx_port_set_duplex, 2714 .port_set_speed = mv88e6185_port_set_speed, 2715 .port_tag_remap = mv88e6095_port_tag_remap, 2716 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2717 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2718 .port_set_ether_type = mv88e6351_port_set_ether_type, 2719 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2720 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2721 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2722 .port_pause_limit = mv88e6097_port_pause_limit, 2723 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2724 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2725 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2726 .stats_get_strings = mv88e6095_stats_get_strings, 2727 .stats_get_stats = mv88e6095_stats_get_stats, 2728 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2729 .set_egress_port = mv88e6095_g1_set_egress_port, 2730 .watchdog_ops = &mv88e6097_watchdog_ops, 2731 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2732 .ppu_enable = mv88e6185_g1_ppu_enable, 2733 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2734 .ppu_disable = mv88e6185_g1_ppu_disable, 2735 .reset = mv88e6185_g1_reset, 2736 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2737 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2738 }; 2739 2740 static const struct mv88e6xxx_ops mv88e6141_ops = { 2741 /* MV88E6XXX_FAMILY_6341 */ 2742 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2743 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2744 .irl_init_all = mv88e6352_g2_irl_init_all, 2745 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2746 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2747 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2748 .phy_read = mv88e6xxx_g2_smi_phy_read, 2749 .phy_write = mv88e6xxx_g2_smi_phy_write, 2750 .port_set_link = mv88e6xxx_port_set_link, 2751 .port_set_duplex = mv88e6xxx_port_set_duplex, 2752 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2753 .port_set_speed = mv88e6390_port_set_speed, 2754 .port_tag_remap = mv88e6095_port_tag_remap, 2755 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2756 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2757 .port_set_ether_type = mv88e6351_port_set_ether_type, 2758 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2759 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2760 .port_pause_limit = mv88e6097_port_pause_limit, 2761 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2762 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2763 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2764 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2765 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2766 .stats_get_strings = mv88e6320_stats_get_strings, 2767 .stats_get_stats = mv88e6390_stats_get_stats, 2768 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2769 .set_egress_port = mv88e6390_g1_set_egress_port, 2770 .watchdog_ops = &mv88e6390_watchdog_ops, 2771 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2772 .pot_clear = mv88e6xxx_g2_pot_clear, 2773 .reset = mv88e6352_g1_reset, 2774 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2775 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2776 .gpio_ops = &mv88e6352_gpio_ops, 2777 }; 2778 2779 static const struct mv88e6xxx_ops mv88e6161_ops = { 2780 /* MV88E6XXX_FAMILY_6165 */ 2781 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2782 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2783 .irl_init_all = mv88e6352_g2_irl_init_all, 2784 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2785 .phy_read = mv88e6xxx_g2_smi_phy_read, 2786 .phy_write = mv88e6xxx_g2_smi_phy_write, 2787 .port_set_link = mv88e6xxx_port_set_link, 2788 .port_set_duplex = mv88e6xxx_port_set_duplex, 2789 .port_set_speed = mv88e6185_port_set_speed, 2790 .port_tag_remap = mv88e6095_port_tag_remap, 2791 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2792 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2793 .port_set_ether_type = mv88e6351_port_set_ether_type, 2794 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2795 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2796 .port_pause_limit = mv88e6097_port_pause_limit, 2797 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2798 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2799 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2800 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2801 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2802 .stats_get_strings = mv88e6095_stats_get_strings, 2803 .stats_get_stats = mv88e6095_stats_get_stats, 2804 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2805 .set_egress_port = mv88e6095_g1_set_egress_port, 2806 .watchdog_ops = &mv88e6097_watchdog_ops, 2807 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2808 .pot_clear = mv88e6xxx_g2_pot_clear, 2809 .reset = mv88e6352_g1_reset, 2810 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2811 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2812 }; 2813 2814 static const struct mv88e6xxx_ops mv88e6165_ops = { 2815 /* MV88E6XXX_FAMILY_6165 */ 2816 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2817 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2818 .irl_init_all = mv88e6352_g2_irl_init_all, 2819 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2820 .phy_read = mv88e6165_phy_read, 2821 .phy_write = mv88e6165_phy_write, 2822 .port_set_link = mv88e6xxx_port_set_link, 2823 .port_set_duplex = mv88e6xxx_port_set_duplex, 2824 .port_set_speed = mv88e6185_port_set_speed, 2825 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2826 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2827 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2828 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2829 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2830 .stats_get_strings = mv88e6095_stats_get_strings, 2831 .stats_get_stats = mv88e6095_stats_get_stats, 2832 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2833 .set_egress_port = mv88e6095_g1_set_egress_port, 2834 .watchdog_ops = &mv88e6097_watchdog_ops, 2835 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2836 .pot_clear = mv88e6xxx_g2_pot_clear, 2837 .reset = mv88e6352_g1_reset, 2838 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2839 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2840 }; 2841 2842 static const struct mv88e6xxx_ops mv88e6171_ops = { 2843 /* MV88E6XXX_FAMILY_6351 */ 2844 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2845 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2846 .irl_init_all = mv88e6352_g2_irl_init_all, 2847 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2848 .phy_read = mv88e6xxx_g2_smi_phy_read, 2849 .phy_write = mv88e6xxx_g2_smi_phy_write, 2850 .port_set_link = mv88e6xxx_port_set_link, 2851 .port_set_duplex = mv88e6xxx_port_set_duplex, 2852 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2853 .port_set_speed = mv88e6185_port_set_speed, 2854 .port_tag_remap = mv88e6095_port_tag_remap, 2855 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2856 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2857 .port_set_ether_type = mv88e6351_port_set_ether_type, 2858 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2859 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2860 .port_pause_limit = mv88e6097_port_pause_limit, 2861 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2862 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2863 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2864 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2865 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2866 .stats_get_strings = mv88e6095_stats_get_strings, 2867 .stats_get_stats = mv88e6095_stats_get_stats, 2868 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2869 .set_egress_port = mv88e6095_g1_set_egress_port, 2870 .watchdog_ops = &mv88e6097_watchdog_ops, 2871 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2872 .pot_clear = mv88e6xxx_g2_pot_clear, 2873 .reset = mv88e6352_g1_reset, 2874 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2875 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2876 }; 2877 2878 static const struct mv88e6xxx_ops mv88e6172_ops = { 2879 /* MV88E6XXX_FAMILY_6352 */ 2880 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2881 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2882 .irl_init_all = mv88e6352_g2_irl_init_all, 2883 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2884 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2885 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2886 .phy_read = mv88e6xxx_g2_smi_phy_read, 2887 .phy_write = mv88e6xxx_g2_smi_phy_write, 2888 .port_set_link = mv88e6xxx_port_set_link, 2889 .port_set_duplex = mv88e6xxx_port_set_duplex, 2890 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2891 .port_set_speed = mv88e6352_port_set_speed, 2892 .port_tag_remap = mv88e6095_port_tag_remap, 2893 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2894 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2895 .port_set_ether_type = mv88e6351_port_set_ether_type, 2896 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2897 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2898 .port_pause_limit = mv88e6097_port_pause_limit, 2899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2901 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2902 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2903 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2904 .stats_get_strings = mv88e6095_stats_get_strings, 2905 .stats_get_stats = mv88e6095_stats_get_stats, 2906 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2907 .set_egress_port = mv88e6095_g1_set_egress_port, 2908 .watchdog_ops = &mv88e6097_watchdog_ops, 2909 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2910 .pot_clear = mv88e6xxx_g2_pot_clear, 2911 .reset = mv88e6352_g1_reset, 2912 .rmu_disable = mv88e6352_g1_rmu_disable, 2913 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2914 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2915 .serdes_power = mv88e6352_serdes_power, 2916 .gpio_ops = &mv88e6352_gpio_ops, 2917 }; 2918 2919 static const struct mv88e6xxx_ops mv88e6175_ops = { 2920 /* MV88E6XXX_FAMILY_6351 */ 2921 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2922 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2923 .irl_init_all = mv88e6352_g2_irl_init_all, 2924 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2925 .phy_read = mv88e6xxx_g2_smi_phy_read, 2926 .phy_write = mv88e6xxx_g2_smi_phy_write, 2927 .port_set_link = mv88e6xxx_port_set_link, 2928 .port_set_duplex = mv88e6xxx_port_set_duplex, 2929 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2930 .port_set_speed = mv88e6185_port_set_speed, 2931 .port_tag_remap = mv88e6095_port_tag_remap, 2932 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2933 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2934 .port_set_ether_type = mv88e6351_port_set_ether_type, 2935 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2936 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2937 .port_pause_limit = mv88e6097_port_pause_limit, 2938 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2939 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2940 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2941 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2942 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2943 .stats_get_strings = mv88e6095_stats_get_strings, 2944 .stats_get_stats = mv88e6095_stats_get_stats, 2945 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2946 .set_egress_port = mv88e6095_g1_set_egress_port, 2947 .watchdog_ops = &mv88e6097_watchdog_ops, 2948 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2949 .pot_clear = mv88e6xxx_g2_pot_clear, 2950 .reset = mv88e6352_g1_reset, 2951 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2952 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2953 .serdes_power = mv88e6341_serdes_power, 2954 }; 2955 2956 static const struct mv88e6xxx_ops mv88e6176_ops = { 2957 /* MV88E6XXX_FAMILY_6352 */ 2958 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2959 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2960 .irl_init_all = mv88e6352_g2_irl_init_all, 2961 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2962 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2963 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2964 .phy_read = mv88e6xxx_g2_smi_phy_read, 2965 .phy_write = mv88e6xxx_g2_smi_phy_write, 2966 .port_set_link = mv88e6xxx_port_set_link, 2967 .port_set_duplex = mv88e6xxx_port_set_duplex, 2968 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2969 .port_set_speed = mv88e6352_port_set_speed, 2970 .port_tag_remap = mv88e6095_port_tag_remap, 2971 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2972 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2973 .port_set_ether_type = mv88e6351_port_set_ether_type, 2974 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2975 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2976 .port_pause_limit = mv88e6097_port_pause_limit, 2977 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2978 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2979 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2980 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2981 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2982 .stats_get_strings = mv88e6095_stats_get_strings, 2983 .stats_get_stats = mv88e6095_stats_get_stats, 2984 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2985 .set_egress_port = mv88e6095_g1_set_egress_port, 2986 .watchdog_ops = &mv88e6097_watchdog_ops, 2987 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2988 .pot_clear = mv88e6xxx_g2_pot_clear, 2989 .reset = mv88e6352_g1_reset, 2990 .rmu_disable = mv88e6352_g1_rmu_disable, 2991 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2992 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2993 .serdes_power = mv88e6352_serdes_power, 2994 .gpio_ops = &mv88e6352_gpio_ops, 2995 }; 2996 2997 static const struct mv88e6xxx_ops mv88e6185_ops = { 2998 /* MV88E6XXX_FAMILY_6185 */ 2999 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3000 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3001 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3002 .phy_read = mv88e6185_phy_ppu_read, 3003 .phy_write = mv88e6185_phy_ppu_write, 3004 .port_set_link = mv88e6xxx_port_set_link, 3005 .port_set_duplex = mv88e6xxx_port_set_duplex, 3006 .port_set_speed = mv88e6185_port_set_speed, 3007 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3008 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3009 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3010 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3011 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3012 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3013 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3014 .stats_get_strings = mv88e6095_stats_get_strings, 3015 .stats_get_stats = mv88e6095_stats_get_stats, 3016 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3017 .set_egress_port = mv88e6095_g1_set_egress_port, 3018 .watchdog_ops = &mv88e6097_watchdog_ops, 3019 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3020 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3021 .ppu_enable = mv88e6185_g1_ppu_enable, 3022 .ppu_disable = mv88e6185_g1_ppu_disable, 3023 .reset = mv88e6185_g1_reset, 3024 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3025 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3026 }; 3027 3028 static const struct mv88e6xxx_ops mv88e6190_ops = { 3029 /* MV88E6XXX_FAMILY_6390 */ 3030 .irl_init_all = mv88e6390_g2_irl_init_all, 3031 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3032 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3033 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3034 .phy_read = mv88e6xxx_g2_smi_phy_read, 3035 .phy_write = mv88e6xxx_g2_smi_phy_write, 3036 .port_set_link = mv88e6xxx_port_set_link, 3037 .port_set_duplex = mv88e6xxx_port_set_duplex, 3038 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3039 .port_set_speed = mv88e6390_port_set_speed, 3040 .port_tag_remap = mv88e6390_port_tag_remap, 3041 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3042 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3043 .port_set_ether_type = mv88e6351_port_set_ether_type, 3044 .port_pause_limit = mv88e6390_port_pause_limit, 3045 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3046 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3047 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3048 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3049 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3050 .stats_get_strings = mv88e6320_stats_get_strings, 3051 .stats_get_stats = mv88e6390_stats_get_stats, 3052 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3053 .set_egress_port = mv88e6390_g1_set_egress_port, 3054 .watchdog_ops = &mv88e6390_watchdog_ops, 3055 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3056 .pot_clear = mv88e6xxx_g2_pot_clear, 3057 .reset = mv88e6352_g1_reset, 3058 .rmu_disable = mv88e6390_g1_rmu_disable, 3059 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3060 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3061 .serdes_power = mv88e6390_serdes_power, 3062 .gpio_ops = &mv88e6352_gpio_ops, 3063 }; 3064 3065 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3066 /* MV88E6XXX_FAMILY_6390 */ 3067 .irl_init_all = mv88e6390_g2_irl_init_all, 3068 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3069 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3070 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3071 .phy_read = mv88e6xxx_g2_smi_phy_read, 3072 .phy_write = mv88e6xxx_g2_smi_phy_write, 3073 .port_set_link = mv88e6xxx_port_set_link, 3074 .port_set_duplex = mv88e6xxx_port_set_duplex, 3075 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3076 .port_set_speed = mv88e6390x_port_set_speed, 3077 .port_tag_remap = mv88e6390_port_tag_remap, 3078 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3079 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3080 .port_set_ether_type = mv88e6351_port_set_ether_type, 3081 .port_pause_limit = mv88e6390_port_pause_limit, 3082 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3083 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3084 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3085 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3086 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3087 .stats_get_strings = mv88e6320_stats_get_strings, 3088 .stats_get_stats = mv88e6390_stats_get_stats, 3089 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3090 .set_egress_port = mv88e6390_g1_set_egress_port, 3091 .watchdog_ops = &mv88e6390_watchdog_ops, 3092 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3093 .pot_clear = mv88e6xxx_g2_pot_clear, 3094 .reset = mv88e6352_g1_reset, 3095 .rmu_disable = mv88e6390_g1_rmu_disable, 3096 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3097 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3098 .serdes_power = mv88e6390_serdes_power, 3099 .gpio_ops = &mv88e6352_gpio_ops, 3100 }; 3101 3102 static const struct mv88e6xxx_ops mv88e6191_ops = { 3103 /* MV88E6XXX_FAMILY_6390 */ 3104 .irl_init_all = mv88e6390_g2_irl_init_all, 3105 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3106 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3107 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3108 .phy_read = mv88e6xxx_g2_smi_phy_read, 3109 .phy_write = mv88e6xxx_g2_smi_phy_write, 3110 .port_set_link = mv88e6xxx_port_set_link, 3111 .port_set_duplex = mv88e6xxx_port_set_duplex, 3112 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3113 .port_set_speed = mv88e6390_port_set_speed, 3114 .port_tag_remap = mv88e6390_port_tag_remap, 3115 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3116 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3117 .port_set_ether_type = mv88e6351_port_set_ether_type, 3118 .port_pause_limit = mv88e6390_port_pause_limit, 3119 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3120 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3121 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3122 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3123 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3124 .stats_get_strings = mv88e6320_stats_get_strings, 3125 .stats_get_stats = mv88e6390_stats_get_stats, 3126 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3127 .set_egress_port = mv88e6390_g1_set_egress_port, 3128 .watchdog_ops = &mv88e6390_watchdog_ops, 3129 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3130 .pot_clear = mv88e6xxx_g2_pot_clear, 3131 .reset = mv88e6352_g1_reset, 3132 .rmu_disable = mv88e6390_g1_rmu_disable, 3133 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3134 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3135 .serdes_power = mv88e6390_serdes_power, 3136 }; 3137 3138 static const struct mv88e6xxx_ops mv88e6240_ops = { 3139 /* MV88E6XXX_FAMILY_6352 */ 3140 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3141 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3142 .irl_init_all = mv88e6352_g2_irl_init_all, 3143 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3144 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3145 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3146 .phy_read = mv88e6xxx_g2_smi_phy_read, 3147 .phy_write = mv88e6xxx_g2_smi_phy_write, 3148 .port_set_link = mv88e6xxx_port_set_link, 3149 .port_set_duplex = mv88e6xxx_port_set_duplex, 3150 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3151 .port_set_speed = mv88e6352_port_set_speed, 3152 .port_tag_remap = mv88e6095_port_tag_remap, 3153 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3154 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3155 .port_set_ether_type = mv88e6351_port_set_ether_type, 3156 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3157 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3158 .port_pause_limit = mv88e6097_port_pause_limit, 3159 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3160 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3161 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3162 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3163 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3164 .stats_get_strings = mv88e6095_stats_get_strings, 3165 .stats_get_stats = mv88e6095_stats_get_stats, 3166 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3167 .set_egress_port = mv88e6095_g1_set_egress_port, 3168 .watchdog_ops = &mv88e6097_watchdog_ops, 3169 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3170 .pot_clear = mv88e6xxx_g2_pot_clear, 3171 .reset = mv88e6352_g1_reset, 3172 .rmu_disable = mv88e6352_g1_rmu_disable, 3173 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3174 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3175 .serdes_power = mv88e6352_serdes_power, 3176 .gpio_ops = &mv88e6352_gpio_ops, 3177 .avb_ops = &mv88e6352_avb_ops, 3178 }; 3179 3180 static const struct mv88e6xxx_ops mv88e6290_ops = { 3181 /* MV88E6XXX_FAMILY_6390 */ 3182 .irl_init_all = mv88e6390_g2_irl_init_all, 3183 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3184 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3185 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3186 .phy_read = mv88e6xxx_g2_smi_phy_read, 3187 .phy_write = mv88e6xxx_g2_smi_phy_write, 3188 .port_set_link = mv88e6xxx_port_set_link, 3189 .port_set_duplex = mv88e6xxx_port_set_duplex, 3190 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3191 .port_set_speed = mv88e6390_port_set_speed, 3192 .port_tag_remap = mv88e6390_port_tag_remap, 3193 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3194 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3195 .port_set_ether_type = mv88e6351_port_set_ether_type, 3196 .port_pause_limit = mv88e6390_port_pause_limit, 3197 .port_set_cmode = mv88e6390x_port_set_cmode, 3198 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3199 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3200 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3201 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3202 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3203 .stats_get_strings = mv88e6320_stats_get_strings, 3204 .stats_get_stats = mv88e6390_stats_get_stats, 3205 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3206 .set_egress_port = mv88e6390_g1_set_egress_port, 3207 .watchdog_ops = &mv88e6390_watchdog_ops, 3208 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3209 .pot_clear = mv88e6xxx_g2_pot_clear, 3210 .reset = mv88e6352_g1_reset, 3211 .rmu_disable = mv88e6390_g1_rmu_disable, 3212 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3213 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3214 .serdes_power = mv88e6390_serdes_power, 3215 .gpio_ops = &mv88e6352_gpio_ops, 3216 .avb_ops = &mv88e6390_avb_ops, 3217 }; 3218 3219 static const struct mv88e6xxx_ops mv88e6320_ops = { 3220 /* MV88E6XXX_FAMILY_6320 */ 3221 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3222 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3223 .irl_init_all = mv88e6352_g2_irl_init_all, 3224 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3225 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3226 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3227 .phy_read = mv88e6xxx_g2_smi_phy_read, 3228 .phy_write = mv88e6xxx_g2_smi_phy_write, 3229 .port_set_link = mv88e6xxx_port_set_link, 3230 .port_set_duplex = mv88e6xxx_port_set_duplex, 3231 .port_set_speed = mv88e6185_port_set_speed, 3232 .port_tag_remap = mv88e6095_port_tag_remap, 3233 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3234 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3235 .port_set_ether_type = mv88e6351_port_set_ether_type, 3236 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3237 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3238 .port_pause_limit = mv88e6097_port_pause_limit, 3239 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3240 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3241 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3242 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3243 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3244 .stats_get_strings = mv88e6320_stats_get_strings, 3245 .stats_get_stats = mv88e6320_stats_get_stats, 3246 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3247 .set_egress_port = mv88e6095_g1_set_egress_port, 3248 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3249 .pot_clear = mv88e6xxx_g2_pot_clear, 3250 .reset = mv88e6352_g1_reset, 3251 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3252 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3253 .gpio_ops = &mv88e6352_gpio_ops, 3254 .avb_ops = &mv88e6352_avb_ops, 3255 }; 3256 3257 static const struct mv88e6xxx_ops mv88e6321_ops = { 3258 /* MV88E6XXX_FAMILY_6320 */ 3259 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3260 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3261 .irl_init_all = mv88e6352_g2_irl_init_all, 3262 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3263 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3265 .phy_read = mv88e6xxx_g2_smi_phy_read, 3266 .phy_write = mv88e6xxx_g2_smi_phy_write, 3267 .port_set_link = mv88e6xxx_port_set_link, 3268 .port_set_duplex = mv88e6xxx_port_set_duplex, 3269 .port_set_speed = mv88e6185_port_set_speed, 3270 .port_tag_remap = mv88e6095_port_tag_remap, 3271 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3272 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3273 .port_set_ether_type = mv88e6351_port_set_ether_type, 3274 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3275 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3276 .port_pause_limit = mv88e6097_port_pause_limit, 3277 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3278 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3279 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3280 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3281 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3282 .stats_get_strings = mv88e6320_stats_get_strings, 3283 .stats_get_stats = mv88e6320_stats_get_stats, 3284 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3285 .set_egress_port = mv88e6095_g1_set_egress_port, 3286 .reset = mv88e6352_g1_reset, 3287 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3288 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3289 .gpio_ops = &mv88e6352_gpio_ops, 3290 .avb_ops = &mv88e6352_avb_ops, 3291 }; 3292 3293 static const struct mv88e6xxx_ops mv88e6341_ops = { 3294 /* MV88E6XXX_FAMILY_6341 */ 3295 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3296 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3297 .irl_init_all = mv88e6352_g2_irl_init_all, 3298 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3299 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3301 .phy_read = mv88e6xxx_g2_smi_phy_read, 3302 .phy_write = mv88e6xxx_g2_smi_phy_write, 3303 .port_set_link = mv88e6xxx_port_set_link, 3304 .port_set_duplex = mv88e6xxx_port_set_duplex, 3305 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3306 .port_set_speed = mv88e6390_port_set_speed, 3307 .port_tag_remap = mv88e6095_port_tag_remap, 3308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3309 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3310 .port_set_ether_type = mv88e6351_port_set_ether_type, 3311 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3312 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3313 .port_pause_limit = mv88e6097_port_pause_limit, 3314 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3315 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3316 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3318 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3319 .stats_get_strings = mv88e6320_stats_get_strings, 3320 .stats_get_stats = mv88e6390_stats_get_stats, 3321 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3322 .set_egress_port = mv88e6390_g1_set_egress_port, 3323 .watchdog_ops = &mv88e6390_watchdog_ops, 3324 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3325 .pot_clear = mv88e6xxx_g2_pot_clear, 3326 .reset = mv88e6352_g1_reset, 3327 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3329 .gpio_ops = &mv88e6352_gpio_ops, 3330 .avb_ops = &mv88e6390_avb_ops, 3331 }; 3332 3333 static const struct mv88e6xxx_ops mv88e6350_ops = { 3334 /* MV88E6XXX_FAMILY_6351 */ 3335 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3336 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3337 .irl_init_all = mv88e6352_g2_irl_init_all, 3338 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3339 .phy_read = mv88e6xxx_g2_smi_phy_read, 3340 .phy_write = mv88e6xxx_g2_smi_phy_write, 3341 .port_set_link = mv88e6xxx_port_set_link, 3342 .port_set_duplex = mv88e6xxx_port_set_duplex, 3343 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3344 .port_set_speed = mv88e6185_port_set_speed, 3345 .port_tag_remap = mv88e6095_port_tag_remap, 3346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3347 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3348 .port_set_ether_type = mv88e6351_port_set_ether_type, 3349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3351 .port_pause_limit = mv88e6097_port_pause_limit, 3352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3354 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3355 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3356 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3357 .stats_get_strings = mv88e6095_stats_get_strings, 3358 .stats_get_stats = mv88e6095_stats_get_stats, 3359 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3360 .set_egress_port = mv88e6095_g1_set_egress_port, 3361 .watchdog_ops = &mv88e6097_watchdog_ops, 3362 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3363 .pot_clear = mv88e6xxx_g2_pot_clear, 3364 .reset = mv88e6352_g1_reset, 3365 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3366 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3367 }; 3368 3369 static const struct mv88e6xxx_ops mv88e6351_ops = { 3370 /* MV88E6XXX_FAMILY_6351 */ 3371 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3372 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3373 .irl_init_all = mv88e6352_g2_irl_init_all, 3374 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3375 .phy_read = mv88e6xxx_g2_smi_phy_read, 3376 .phy_write = mv88e6xxx_g2_smi_phy_write, 3377 .port_set_link = mv88e6xxx_port_set_link, 3378 .port_set_duplex = mv88e6xxx_port_set_duplex, 3379 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3380 .port_set_speed = mv88e6185_port_set_speed, 3381 .port_tag_remap = mv88e6095_port_tag_remap, 3382 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3383 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3384 .port_set_ether_type = mv88e6351_port_set_ether_type, 3385 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3386 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3387 .port_pause_limit = mv88e6097_port_pause_limit, 3388 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3389 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3390 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3391 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3392 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3393 .stats_get_strings = mv88e6095_stats_get_strings, 3394 .stats_get_stats = mv88e6095_stats_get_stats, 3395 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3396 .set_egress_port = mv88e6095_g1_set_egress_port, 3397 .watchdog_ops = &mv88e6097_watchdog_ops, 3398 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3399 .pot_clear = mv88e6xxx_g2_pot_clear, 3400 .reset = mv88e6352_g1_reset, 3401 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3402 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3403 .avb_ops = &mv88e6352_avb_ops, 3404 }; 3405 3406 static const struct mv88e6xxx_ops mv88e6352_ops = { 3407 /* MV88E6XXX_FAMILY_6352 */ 3408 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3409 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3410 .irl_init_all = mv88e6352_g2_irl_init_all, 3411 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3412 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3414 .phy_read = mv88e6xxx_g2_smi_phy_read, 3415 .phy_write = mv88e6xxx_g2_smi_phy_write, 3416 .port_set_link = mv88e6xxx_port_set_link, 3417 .port_set_duplex = mv88e6xxx_port_set_duplex, 3418 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3419 .port_set_speed = mv88e6352_port_set_speed, 3420 .port_tag_remap = mv88e6095_port_tag_remap, 3421 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3422 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3423 .port_set_ether_type = mv88e6351_port_set_ether_type, 3424 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3425 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3426 .port_pause_limit = mv88e6097_port_pause_limit, 3427 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3428 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3429 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3431 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3432 .stats_get_strings = mv88e6095_stats_get_strings, 3433 .stats_get_stats = mv88e6095_stats_get_stats, 3434 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3435 .set_egress_port = mv88e6095_g1_set_egress_port, 3436 .watchdog_ops = &mv88e6097_watchdog_ops, 3437 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3438 .pot_clear = mv88e6xxx_g2_pot_clear, 3439 .reset = mv88e6352_g1_reset, 3440 .rmu_disable = mv88e6352_g1_rmu_disable, 3441 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3442 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3443 .serdes_power = mv88e6352_serdes_power, 3444 .gpio_ops = &mv88e6352_gpio_ops, 3445 .avb_ops = &mv88e6352_avb_ops, 3446 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3447 .serdes_get_strings = mv88e6352_serdes_get_strings, 3448 .serdes_get_stats = mv88e6352_serdes_get_stats, 3449 }; 3450 3451 static const struct mv88e6xxx_ops mv88e6390_ops = { 3452 /* MV88E6XXX_FAMILY_6390 */ 3453 .irl_init_all = mv88e6390_g2_irl_init_all, 3454 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3455 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3457 .phy_read = mv88e6xxx_g2_smi_phy_read, 3458 .phy_write = mv88e6xxx_g2_smi_phy_write, 3459 .port_set_link = mv88e6xxx_port_set_link, 3460 .port_set_duplex = mv88e6xxx_port_set_duplex, 3461 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3462 .port_set_speed = mv88e6390_port_set_speed, 3463 .port_tag_remap = mv88e6390_port_tag_remap, 3464 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3465 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3466 .port_set_ether_type = mv88e6351_port_set_ether_type, 3467 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3468 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3469 .port_pause_limit = mv88e6390_port_pause_limit, 3470 .port_set_cmode = mv88e6390x_port_set_cmode, 3471 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3472 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3473 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3474 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3475 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3476 .stats_get_strings = mv88e6320_stats_get_strings, 3477 .stats_get_stats = mv88e6390_stats_get_stats, 3478 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3479 .set_egress_port = mv88e6390_g1_set_egress_port, 3480 .watchdog_ops = &mv88e6390_watchdog_ops, 3481 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3482 .pot_clear = mv88e6xxx_g2_pot_clear, 3483 .reset = mv88e6352_g1_reset, 3484 .rmu_disable = mv88e6390_g1_rmu_disable, 3485 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3486 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3487 .serdes_power = mv88e6390_serdes_power, 3488 .gpio_ops = &mv88e6352_gpio_ops, 3489 .avb_ops = &mv88e6390_avb_ops, 3490 }; 3491 3492 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3493 /* MV88E6XXX_FAMILY_6390 */ 3494 .irl_init_all = mv88e6390_g2_irl_init_all, 3495 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3496 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3497 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3498 .phy_read = mv88e6xxx_g2_smi_phy_read, 3499 .phy_write = mv88e6xxx_g2_smi_phy_write, 3500 .port_set_link = mv88e6xxx_port_set_link, 3501 .port_set_duplex = mv88e6xxx_port_set_duplex, 3502 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3503 .port_set_speed = mv88e6390x_port_set_speed, 3504 .port_tag_remap = mv88e6390_port_tag_remap, 3505 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3506 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3507 .port_set_ether_type = mv88e6351_port_set_ether_type, 3508 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3509 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3510 .port_pause_limit = mv88e6390_port_pause_limit, 3511 .port_set_cmode = mv88e6390x_port_set_cmode, 3512 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3513 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3514 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3515 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3516 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3517 .stats_get_strings = mv88e6320_stats_get_strings, 3518 .stats_get_stats = mv88e6390_stats_get_stats, 3519 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3520 .set_egress_port = mv88e6390_g1_set_egress_port, 3521 .watchdog_ops = &mv88e6390_watchdog_ops, 3522 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3523 .pot_clear = mv88e6xxx_g2_pot_clear, 3524 .reset = mv88e6352_g1_reset, 3525 .rmu_disable = mv88e6390_g1_rmu_disable, 3526 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3527 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3528 .serdes_power = mv88e6390_serdes_power, 3529 .gpio_ops = &mv88e6352_gpio_ops, 3530 .avb_ops = &mv88e6390_avb_ops, 3531 }; 3532 3533 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3534 [MV88E6085] = { 3535 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3536 .family = MV88E6XXX_FAMILY_6097, 3537 .name = "Marvell 88E6085", 3538 .num_databases = 4096, 3539 .num_ports = 10, 3540 .num_internal_phys = 5, 3541 .max_vid = 4095, 3542 .port_base_addr = 0x10, 3543 .phy_base_addr = 0x0, 3544 .global1_addr = 0x1b, 3545 .global2_addr = 0x1c, 3546 .age_time_coeff = 15000, 3547 .g1_irqs = 8, 3548 .g2_irqs = 10, 3549 .atu_move_port_mask = 0xf, 3550 .pvt = true, 3551 .multi_chip = true, 3552 .tag_protocol = DSA_TAG_PROTO_DSA, 3553 .ops = &mv88e6085_ops, 3554 }, 3555 3556 [MV88E6095] = { 3557 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3558 .family = MV88E6XXX_FAMILY_6095, 3559 .name = "Marvell 88E6095/88E6095F", 3560 .num_databases = 256, 3561 .num_ports = 11, 3562 .num_internal_phys = 0, 3563 .max_vid = 4095, 3564 .port_base_addr = 0x10, 3565 .phy_base_addr = 0x0, 3566 .global1_addr = 0x1b, 3567 .global2_addr = 0x1c, 3568 .age_time_coeff = 15000, 3569 .g1_irqs = 8, 3570 .atu_move_port_mask = 0xf, 3571 .multi_chip = true, 3572 .tag_protocol = DSA_TAG_PROTO_DSA, 3573 .ops = &mv88e6095_ops, 3574 }, 3575 3576 [MV88E6097] = { 3577 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3578 .family = MV88E6XXX_FAMILY_6097, 3579 .name = "Marvell 88E6097/88E6097F", 3580 .num_databases = 4096, 3581 .num_ports = 11, 3582 .num_internal_phys = 8, 3583 .max_vid = 4095, 3584 .port_base_addr = 0x10, 3585 .phy_base_addr = 0x0, 3586 .global1_addr = 0x1b, 3587 .global2_addr = 0x1c, 3588 .age_time_coeff = 15000, 3589 .g1_irqs = 8, 3590 .g2_irqs = 10, 3591 .atu_move_port_mask = 0xf, 3592 .pvt = true, 3593 .multi_chip = true, 3594 .tag_protocol = DSA_TAG_PROTO_EDSA, 3595 .ops = &mv88e6097_ops, 3596 }, 3597 3598 [MV88E6123] = { 3599 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3600 .family = MV88E6XXX_FAMILY_6165, 3601 .name = "Marvell 88E6123", 3602 .num_databases = 4096, 3603 .num_ports = 3, 3604 .num_internal_phys = 5, 3605 .max_vid = 4095, 3606 .port_base_addr = 0x10, 3607 .phy_base_addr = 0x0, 3608 .global1_addr = 0x1b, 3609 .global2_addr = 0x1c, 3610 .age_time_coeff = 15000, 3611 .g1_irqs = 9, 3612 .g2_irqs = 10, 3613 .atu_move_port_mask = 0xf, 3614 .pvt = true, 3615 .multi_chip = true, 3616 .tag_protocol = DSA_TAG_PROTO_EDSA, 3617 .ops = &mv88e6123_ops, 3618 }, 3619 3620 [MV88E6131] = { 3621 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3622 .family = MV88E6XXX_FAMILY_6185, 3623 .name = "Marvell 88E6131", 3624 .num_databases = 256, 3625 .num_ports = 8, 3626 .num_internal_phys = 0, 3627 .max_vid = 4095, 3628 .port_base_addr = 0x10, 3629 .phy_base_addr = 0x0, 3630 .global1_addr = 0x1b, 3631 .global2_addr = 0x1c, 3632 .age_time_coeff = 15000, 3633 .g1_irqs = 9, 3634 .atu_move_port_mask = 0xf, 3635 .multi_chip = true, 3636 .tag_protocol = DSA_TAG_PROTO_DSA, 3637 .ops = &mv88e6131_ops, 3638 }, 3639 3640 [MV88E6141] = { 3641 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3642 .family = MV88E6XXX_FAMILY_6341, 3643 .name = "Marvell 88E6141", 3644 .num_databases = 4096, 3645 .num_ports = 6, 3646 .num_internal_phys = 5, 3647 .num_gpio = 11, 3648 .max_vid = 4095, 3649 .port_base_addr = 0x10, 3650 .phy_base_addr = 0x10, 3651 .global1_addr = 0x1b, 3652 .global2_addr = 0x1c, 3653 .age_time_coeff = 3750, 3654 .atu_move_port_mask = 0x1f, 3655 .g1_irqs = 9, 3656 .g2_irqs = 10, 3657 .pvt = true, 3658 .multi_chip = true, 3659 .tag_protocol = DSA_TAG_PROTO_EDSA, 3660 .ops = &mv88e6141_ops, 3661 }, 3662 3663 [MV88E6161] = { 3664 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3665 .family = MV88E6XXX_FAMILY_6165, 3666 .name = "Marvell 88E6161", 3667 .num_databases = 4096, 3668 .num_ports = 6, 3669 .num_internal_phys = 5, 3670 .max_vid = 4095, 3671 .port_base_addr = 0x10, 3672 .phy_base_addr = 0x0, 3673 .global1_addr = 0x1b, 3674 .global2_addr = 0x1c, 3675 .age_time_coeff = 15000, 3676 .g1_irqs = 9, 3677 .g2_irqs = 10, 3678 .atu_move_port_mask = 0xf, 3679 .pvt = true, 3680 .multi_chip = true, 3681 .tag_protocol = DSA_TAG_PROTO_EDSA, 3682 .ops = &mv88e6161_ops, 3683 }, 3684 3685 [MV88E6165] = { 3686 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3687 .family = MV88E6XXX_FAMILY_6165, 3688 .name = "Marvell 88E6165", 3689 .num_databases = 4096, 3690 .num_ports = 6, 3691 .num_internal_phys = 0, 3692 .max_vid = 4095, 3693 .port_base_addr = 0x10, 3694 .phy_base_addr = 0x0, 3695 .global1_addr = 0x1b, 3696 .global2_addr = 0x1c, 3697 .age_time_coeff = 15000, 3698 .g1_irqs = 9, 3699 .g2_irqs = 10, 3700 .atu_move_port_mask = 0xf, 3701 .pvt = true, 3702 .multi_chip = true, 3703 .tag_protocol = DSA_TAG_PROTO_DSA, 3704 .ops = &mv88e6165_ops, 3705 }, 3706 3707 [MV88E6171] = { 3708 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3709 .family = MV88E6XXX_FAMILY_6351, 3710 .name = "Marvell 88E6171", 3711 .num_databases = 4096, 3712 .num_ports = 7, 3713 .num_internal_phys = 5, 3714 .max_vid = 4095, 3715 .port_base_addr = 0x10, 3716 .phy_base_addr = 0x0, 3717 .global1_addr = 0x1b, 3718 .global2_addr = 0x1c, 3719 .age_time_coeff = 15000, 3720 .g1_irqs = 9, 3721 .g2_irqs = 10, 3722 .atu_move_port_mask = 0xf, 3723 .pvt = true, 3724 .multi_chip = true, 3725 .tag_protocol = DSA_TAG_PROTO_EDSA, 3726 .ops = &mv88e6171_ops, 3727 }, 3728 3729 [MV88E6172] = { 3730 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3731 .family = MV88E6XXX_FAMILY_6352, 3732 .name = "Marvell 88E6172", 3733 .num_databases = 4096, 3734 .num_ports = 7, 3735 .num_internal_phys = 5, 3736 .num_gpio = 15, 3737 .max_vid = 4095, 3738 .port_base_addr = 0x10, 3739 .phy_base_addr = 0x0, 3740 .global1_addr = 0x1b, 3741 .global2_addr = 0x1c, 3742 .age_time_coeff = 15000, 3743 .g1_irqs = 9, 3744 .g2_irqs = 10, 3745 .atu_move_port_mask = 0xf, 3746 .pvt = true, 3747 .multi_chip = true, 3748 .tag_protocol = DSA_TAG_PROTO_EDSA, 3749 .ops = &mv88e6172_ops, 3750 }, 3751 3752 [MV88E6175] = { 3753 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3754 .family = MV88E6XXX_FAMILY_6351, 3755 .name = "Marvell 88E6175", 3756 .num_databases = 4096, 3757 .num_ports = 7, 3758 .num_internal_phys = 5, 3759 .max_vid = 4095, 3760 .port_base_addr = 0x10, 3761 .phy_base_addr = 0x0, 3762 .global1_addr = 0x1b, 3763 .global2_addr = 0x1c, 3764 .age_time_coeff = 15000, 3765 .g1_irqs = 9, 3766 .g2_irqs = 10, 3767 .atu_move_port_mask = 0xf, 3768 .pvt = true, 3769 .multi_chip = true, 3770 .tag_protocol = DSA_TAG_PROTO_EDSA, 3771 .ops = &mv88e6175_ops, 3772 }, 3773 3774 [MV88E6176] = { 3775 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3776 .family = MV88E6XXX_FAMILY_6352, 3777 .name = "Marvell 88E6176", 3778 .num_databases = 4096, 3779 .num_ports = 7, 3780 .num_internal_phys = 5, 3781 .num_gpio = 15, 3782 .max_vid = 4095, 3783 .port_base_addr = 0x10, 3784 .phy_base_addr = 0x0, 3785 .global1_addr = 0x1b, 3786 .global2_addr = 0x1c, 3787 .age_time_coeff = 15000, 3788 .g1_irqs = 9, 3789 .g2_irqs = 10, 3790 .atu_move_port_mask = 0xf, 3791 .pvt = true, 3792 .multi_chip = true, 3793 .tag_protocol = DSA_TAG_PROTO_EDSA, 3794 .ops = &mv88e6176_ops, 3795 }, 3796 3797 [MV88E6185] = { 3798 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3799 .family = MV88E6XXX_FAMILY_6185, 3800 .name = "Marvell 88E6185", 3801 .num_databases = 256, 3802 .num_ports = 10, 3803 .num_internal_phys = 0, 3804 .max_vid = 4095, 3805 .port_base_addr = 0x10, 3806 .phy_base_addr = 0x0, 3807 .global1_addr = 0x1b, 3808 .global2_addr = 0x1c, 3809 .age_time_coeff = 15000, 3810 .g1_irqs = 8, 3811 .atu_move_port_mask = 0xf, 3812 .multi_chip = true, 3813 .tag_protocol = DSA_TAG_PROTO_EDSA, 3814 .ops = &mv88e6185_ops, 3815 }, 3816 3817 [MV88E6190] = { 3818 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3819 .family = MV88E6XXX_FAMILY_6390, 3820 .name = "Marvell 88E6190", 3821 .num_databases = 4096, 3822 .num_ports = 11, /* 10 + Z80 */ 3823 .num_internal_phys = 11, 3824 .num_gpio = 16, 3825 .max_vid = 8191, 3826 .port_base_addr = 0x0, 3827 .phy_base_addr = 0x0, 3828 .global1_addr = 0x1b, 3829 .global2_addr = 0x1c, 3830 .tag_protocol = DSA_TAG_PROTO_DSA, 3831 .age_time_coeff = 3750, 3832 .g1_irqs = 9, 3833 .g2_irqs = 14, 3834 .pvt = true, 3835 .multi_chip = true, 3836 .atu_move_port_mask = 0x1f, 3837 .ops = &mv88e6190_ops, 3838 }, 3839 3840 [MV88E6190X] = { 3841 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3842 .family = MV88E6XXX_FAMILY_6390, 3843 .name = "Marvell 88E6190X", 3844 .num_databases = 4096, 3845 .num_ports = 11, /* 10 + Z80 */ 3846 .num_internal_phys = 11, 3847 .num_gpio = 16, 3848 .max_vid = 8191, 3849 .port_base_addr = 0x0, 3850 .phy_base_addr = 0x0, 3851 .global1_addr = 0x1b, 3852 .global2_addr = 0x1c, 3853 .age_time_coeff = 3750, 3854 .g1_irqs = 9, 3855 .g2_irqs = 14, 3856 .atu_move_port_mask = 0x1f, 3857 .pvt = true, 3858 .multi_chip = true, 3859 .tag_protocol = DSA_TAG_PROTO_DSA, 3860 .ops = &mv88e6190x_ops, 3861 }, 3862 3863 [MV88E6191] = { 3864 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3865 .family = MV88E6XXX_FAMILY_6390, 3866 .name = "Marvell 88E6191", 3867 .num_databases = 4096, 3868 .num_ports = 11, /* 10 + Z80 */ 3869 .num_internal_phys = 11, 3870 .max_vid = 8191, 3871 .port_base_addr = 0x0, 3872 .phy_base_addr = 0x0, 3873 .global1_addr = 0x1b, 3874 .global2_addr = 0x1c, 3875 .age_time_coeff = 3750, 3876 .g1_irqs = 9, 3877 .g2_irqs = 14, 3878 .atu_move_port_mask = 0x1f, 3879 .pvt = true, 3880 .multi_chip = true, 3881 .tag_protocol = DSA_TAG_PROTO_DSA, 3882 .ptp_support = true, 3883 .ops = &mv88e6191_ops, 3884 }, 3885 3886 [MV88E6240] = { 3887 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3888 .family = MV88E6XXX_FAMILY_6352, 3889 .name = "Marvell 88E6240", 3890 .num_databases = 4096, 3891 .num_ports = 7, 3892 .num_internal_phys = 5, 3893 .num_gpio = 15, 3894 .max_vid = 4095, 3895 .port_base_addr = 0x10, 3896 .phy_base_addr = 0x0, 3897 .global1_addr = 0x1b, 3898 .global2_addr = 0x1c, 3899 .age_time_coeff = 15000, 3900 .g1_irqs = 9, 3901 .g2_irqs = 10, 3902 .atu_move_port_mask = 0xf, 3903 .pvt = true, 3904 .multi_chip = true, 3905 .tag_protocol = DSA_TAG_PROTO_EDSA, 3906 .ptp_support = true, 3907 .ops = &mv88e6240_ops, 3908 }, 3909 3910 [MV88E6290] = { 3911 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3912 .family = MV88E6XXX_FAMILY_6390, 3913 .name = "Marvell 88E6290", 3914 .num_databases = 4096, 3915 .num_ports = 11, /* 10 + Z80 */ 3916 .num_internal_phys = 11, 3917 .num_gpio = 16, 3918 .max_vid = 8191, 3919 .port_base_addr = 0x0, 3920 .phy_base_addr = 0x0, 3921 .global1_addr = 0x1b, 3922 .global2_addr = 0x1c, 3923 .age_time_coeff = 3750, 3924 .g1_irqs = 9, 3925 .g2_irqs = 14, 3926 .atu_move_port_mask = 0x1f, 3927 .pvt = true, 3928 .multi_chip = true, 3929 .tag_protocol = DSA_TAG_PROTO_DSA, 3930 .ptp_support = true, 3931 .ops = &mv88e6290_ops, 3932 }, 3933 3934 [MV88E6320] = { 3935 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3936 .family = MV88E6XXX_FAMILY_6320, 3937 .name = "Marvell 88E6320", 3938 .num_databases = 4096, 3939 .num_ports = 7, 3940 .num_internal_phys = 5, 3941 .num_gpio = 15, 3942 .max_vid = 4095, 3943 .port_base_addr = 0x10, 3944 .phy_base_addr = 0x0, 3945 .global1_addr = 0x1b, 3946 .global2_addr = 0x1c, 3947 .age_time_coeff = 15000, 3948 .g1_irqs = 8, 3949 .g2_irqs = 10, 3950 .atu_move_port_mask = 0xf, 3951 .pvt = true, 3952 .multi_chip = true, 3953 .tag_protocol = DSA_TAG_PROTO_EDSA, 3954 .ptp_support = true, 3955 .ops = &mv88e6320_ops, 3956 }, 3957 3958 [MV88E6321] = { 3959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3960 .family = MV88E6XXX_FAMILY_6320, 3961 .name = "Marvell 88E6321", 3962 .num_databases = 4096, 3963 .num_ports = 7, 3964 .num_internal_phys = 5, 3965 .num_gpio = 15, 3966 .max_vid = 4095, 3967 .port_base_addr = 0x10, 3968 .phy_base_addr = 0x0, 3969 .global1_addr = 0x1b, 3970 .global2_addr = 0x1c, 3971 .age_time_coeff = 15000, 3972 .g1_irqs = 8, 3973 .g2_irqs = 10, 3974 .atu_move_port_mask = 0xf, 3975 .multi_chip = true, 3976 .tag_protocol = DSA_TAG_PROTO_EDSA, 3977 .ptp_support = true, 3978 .ops = &mv88e6321_ops, 3979 }, 3980 3981 [MV88E6341] = { 3982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3983 .family = MV88E6XXX_FAMILY_6341, 3984 .name = "Marvell 88E6341", 3985 .num_databases = 4096, 3986 .num_internal_phys = 5, 3987 .num_ports = 6, 3988 .num_gpio = 11, 3989 .max_vid = 4095, 3990 .port_base_addr = 0x10, 3991 .phy_base_addr = 0x10, 3992 .global1_addr = 0x1b, 3993 .global2_addr = 0x1c, 3994 .age_time_coeff = 3750, 3995 .atu_move_port_mask = 0x1f, 3996 .g1_irqs = 9, 3997 .g2_irqs = 10, 3998 .pvt = true, 3999 .multi_chip = true, 4000 .tag_protocol = DSA_TAG_PROTO_EDSA, 4001 .ptp_support = true, 4002 .ops = &mv88e6341_ops, 4003 }, 4004 4005 [MV88E6350] = { 4006 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4007 .family = MV88E6XXX_FAMILY_6351, 4008 .name = "Marvell 88E6350", 4009 .num_databases = 4096, 4010 .num_ports = 7, 4011 .num_internal_phys = 5, 4012 .max_vid = 4095, 4013 .port_base_addr = 0x10, 4014 .phy_base_addr = 0x0, 4015 .global1_addr = 0x1b, 4016 .global2_addr = 0x1c, 4017 .age_time_coeff = 15000, 4018 .g1_irqs = 9, 4019 .g2_irqs = 10, 4020 .atu_move_port_mask = 0xf, 4021 .pvt = true, 4022 .multi_chip = true, 4023 .tag_protocol = DSA_TAG_PROTO_EDSA, 4024 .ops = &mv88e6350_ops, 4025 }, 4026 4027 [MV88E6351] = { 4028 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4029 .family = MV88E6XXX_FAMILY_6351, 4030 .name = "Marvell 88E6351", 4031 .num_databases = 4096, 4032 .num_ports = 7, 4033 .num_internal_phys = 5, 4034 .max_vid = 4095, 4035 .port_base_addr = 0x10, 4036 .phy_base_addr = 0x0, 4037 .global1_addr = 0x1b, 4038 .global2_addr = 0x1c, 4039 .age_time_coeff = 15000, 4040 .g1_irqs = 9, 4041 .g2_irqs = 10, 4042 .atu_move_port_mask = 0xf, 4043 .pvt = true, 4044 .multi_chip = true, 4045 .tag_protocol = DSA_TAG_PROTO_EDSA, 4046 .ops = &mv88e6351_ops, 4047 }, 4048 4049 [MV88E6352] = { 4050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4051 .family = MV88E6XXX_FAMILY_6352, 4052 .name = "Marvell 88E6352", 4053 .num_databases = 4096, 4054 .num_ports = 7, 4055 .num_internal_phys = 5, 4056 .num_gpio = 15, 4057 .max_vid = 4095, 4058 .port_base_addr = 0x10, 4059 .phy_base_addr = 0x0, 4060 .global1_addr = 0x1b, 4061 .global2_addr = 0x1c, 4062 .age_time_coeff = 15000, 4063 .g1_irqs = 9, 4064 .g2_irqs = 10, 4065 .atu_move_port_mask = 0xf, 4066 .pvt = true, 4067 .multi_chip = true, 4068 .tag_protocol = DSA_TAG_PROTO_EDSA, 4069 .ptp_support = true, 4070 .ops = &mv88e6352_ops, 4071 }, 4072 [MV88E6390] = { 4073 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4074 .family = MV88E6XXX_FAMILY_6390, 4075 .name = "Marvell 88E6390", 4076 .num_databases = 4096, 4077 .num_ports = 11, /* 10 + Z80 */ 4078 .num_internal_phys = 11, 4079 .num_gpio = 16, 4080 .max_vid = 8191, 4081 .port_base_addr = 0x0, 4082 .phy_base_addr = 0x0, 4083 .global1_addr = 0x1b, 4084 .global2_addr = 0x1c, 4085 .age_time_coeff = 3750, 4086 .g1_irqs = 9, 4087 .g2_irqs = 14, 4088 .atu_move_port_mask = 0x1f, 4089 .pvt = true, 4090 .multi_chip = true, 4091 .tag_protocol = DSA_TAG_PROTO_DSA, 4092 .ptp_support = true, 4093 .ops = &mv88e6390_ops, 4094 }, 4095 [MV88E6390X] = { 4096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4097 .family = MV88E6XXX_FAMILY_6390, 4098 .name = "Marvell 88E6390X", 4099 .num_databases = 4096, 4100 .num_ports = 11, /* 10 + Z80 */ 4101 .num_internal_phys = 11, 4102 .num_gpio = 16, 4103 .max_vid = 8191, 4104 .port_base_addr = 0x0, 4105 .phy_base_addr = 0x0, 4106 .global1_addr = 0x1b, 4107 .global2_addr = 0x1c, 4108 .age_time_coeff = 3750, 4109 .g1_irqs = 9, 4110 .g2_irqs = 14, 4111 .atu_move_port_mask = 0x1f, 4112 .pvt = true, 4113 .multi_chip = true, 4114 .tag_protocol = DSA_TAG_PROTO_DSA, 4115 .ptp_support = true, 4116 .ops = &mv88e6390x_ops, 4117 }, 4118 }; 4119 4120 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4121 { 4122 int i; 4123 4124 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4125 if (mv88e6xxx_table[i].prod_num == prod_num) 4126 return &mv88e6xxx_table[i]; 4127 4128 return NULL; 4129 } 4130 4131 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4132 { 4133 const struct mv88e6xxx_info *info; 4134 unsigned int prod_num, rev; 4135 u16 id; 4136 int err; 4137 4138 mutex_lock(&chip->reg_lock); 4139 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4140 mutex_unlock(&chip->reg_lock); 4141 if (err) 4142 return err; 4143 4144 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4145 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4146 4147 info = mv88e6xxx_lookup_info(prod_num); 4148 if (!info) 4149 return -ENODEV; 4150 4151 /* Update the compatible info with the probed one */ 4152 chip->info = info; 4153 4154 err = mv88e6xxx_g2_require(chip); 4155 if (err) 4156 return err; 4157 4158 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4159 chip->info->prod_num, chip->info->name, rev); 4160 4161 return 0; 4162 } 4163 4164 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4165 { 4166 struct mv88e6xxx_chip *chip; 4167 4168 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4169 if (!chip) 4170 return NULL; 4171 4172 chip->dev = dev; 4173 4174 mutex_init(&chip->reg_lock); 4175 INIT_LIST_HEAD(&chip->mdios); 4176 4177 return chip; 4178 } 4179 4180 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4181 struct mii_bus *bus, int sw_addr) 4182 { 4183 if (sw_addr == 0) 4184 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4185 else if (chip->info->multi_chip) 4186 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4187 else 4188 return -EINVAL; 4189 4190 chip->bus = bus; 4191 chip->sw_addr = sw_addr; 4192 4193 return 0; 4194 } 4195 4196 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4197 int port) 4198 { 4199 struct mv88e6xxx_chip *chip = ds->priv; 4200 4201 return chip->info->tag_protocol; 4202 } 4203 4204 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4205 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4206 struct device *host_dev, int sw_addr, 4207 void **priv) 4208 { 4209 struct mv88e6xxx_chip *chip; 4210 struct mii_bus *bus; 4211 int err; 4212 4213 bus = dsa_host_dev_to_mii_bus(host_dev); 4214 if (!bus) 4215 return NULL; 4216 4217 chip = mv88e6xxx_alloc_chip(dsa_dev); 4218 if (!chip) 4219 return NULL; 4220 4221 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4222 chip->info = &mv88e6xxx_table[MV88E6085]; 4223 4224 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4225 if (err) 4226 goto free; 4227 4228 err = mv88e6xxx_detect(chip); 4229 if (err) 4230 goto free; 4231 4232 mutex_lock(&chip->reg_lock); 4233 err = mv88e6xxx_switch_reset(chip); 4234 mutex_unlock(&chip->reg_lock); 4235 if (err) 4236 goto free; 4237 4238 mv88e6xxx_phy_init(chip); 4239 4240 err = mv88e6xxx_mdios_register(chip, NULL); 4241 if (err) 4242 goto free; 4243 4244 *priv = chip; 4245 4246 return chip->info->name; 4247 free: 4248 devm_kfree(dsa_dev, chip); 4249 4250 return NULL; 4251 } 4252 #endif 4253 4254 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4255 const struct switchdev_obj_port_mdb *mdb) 4256 { 4257 /* We don't need any dynamic resource from the kernel (yet), 4258 * so skip the prepare phase. 4259 */ 4260 4261 return 0; 4262 } 4263 4264 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4265 const struct switchdev_obj_port_mdb *mdb) 4266 { 4267 struct mv88e6xxx_chip *chip = ds->priv; 4268 4269 mutex_lock(&chip->reg_lock); 4270 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4271 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4272 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4273 port); 4274 mutex_unlock(&chip->reg_lock); 4275 } 4276 4277 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4278 const struct switchdev_obj_port_mdb *mdb) 4279 { 4280 struct mv88e6xxx_chip *chip = ds->priv; 4281 int err; 4282 4283 mutex_lock(&chip->reg_lock); 4284 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4285 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4286 mutex_unlock(&chip->reg_lock); 4287 4288 return err; 4289 } 4290 4291 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4292 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4293 .probe = mv88e6xxx_drv_probe, 4294 #endif 4295 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4296 .setup = mv88e6xxx_setup, 4297 .adjust_link = mv88e6xxx_adjust_link, 4298 .phylink_validate = mv88e6xxx_validate, 4299 .phylink_mac_link_state = mv88e6xxx_link_state, 4300 .phylink_mac_config = mv88e6xxx_mac_config, 4301 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4302 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4303 .get_strings = mv88e6xxx_get_strings, 4304 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4305 .get_sset_count = mv88e6xxx_get_sset_count, 4306 .port_enable = mv88e6xxx_port_enable, 4307 .port_disable = mv88e6xxx_port_disable, 4308 .get_mac_eee = mv88e6xxx_get_mac_eee, 4309 .set_mac_eee = mv88e6xxx_set_mac_eee, 4310 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4311 .get_eeprom = mv88e6xxx_get_eeprom, 4312 .set_eeprom = mv88e6xxx_set_eeprom, 4313 .get_regs_len = mv88e6xxx_get_regs_len, 4314 .get_regs = mv88e6xxx_get_regs, 4315 .set_ageing_time = mv88e6xxx_set_ageing_time, 4316 .port_bridge_join = mv88e6xxx_port_bridge_join, 4317 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4318 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4319 .port_fast_age = mv88e6xxx_port_fast_age, 4320 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4321 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4322 .port_vlan_add = mv88e6xxx_port_vlan_add, 4323 .port_vlan_del = mv88e6xxx_port_vlan_del, 4324 .port_fdb_add = mv88e6xxx_port_fdb_add, 4325 .port_fdb_del = mv88e6xxx_port_fdb_del, 4326 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4327 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4328 .port_mdb_add = mv88e6xxx_port_mdb_add, 4329 .port_mdb_del = mv88e6xxx_port_mdb_del, 4330 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4331 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4332 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4333 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4334 .port_txtstamp = mv88e6xxx_port_txtstamp, 4335 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4336 .get_ts_info = mv88e6xxx_get_ts_info, 4337 }; 4338 4339 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4340 .ops = &mv88e6xxx_switch_ops, 4341 }; 4342 4343 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4344 { 4345 struct device *dev = chip->dev; 4346 struct dsa_switch *ds; 4347 4348 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4349 if (!ds) 4350 return -ENOMEM; 4351 4352 ds->priv = chip; 4353 ds->ops = &mv88e6xxx_switch_ops; 4354 ds->ageing_time_min = chip->info->age_time_coeff; 4355 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4356 4357 dev_set_drvdata(dev, ds); 4358 4359 return dsa_register_switch(ds); 4360 } 4361 4362 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4363 { 4364 dsa_unregister_switch(chip->ds); 4365 } 4366 4367 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4368 { 4369 struct device *dev = &mdiodev->dev; 4370 struct device_node *np = dev->of_node; 4371 const struct mv88e6xxx_info *compat_info; 4372 struct mv88e6xxx_chip *chip; 4373 u32 eeprom_len; 4374 int err; 4375 4376 compat_info = of_device_get_match_data(dev); 4377 if (!compat_info) 4378 return -EINVAL; 4379 4380 chip = mv88e6xxx_alloc_chip(dev); 4381 if (!chip) 4382 return -ENOMEM; 4383 4384 chip->info = compat_info; 4385 4386 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4387 if (err) 4388 return err; 4389 4390 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4391 if (IS_ERR(chip->reset)) 4392 return PTR_ERR(chip->reset); 4393 4394 err = mv88e6xxx_detect(chip); 4395 if (err) 4396 return err; 4397 4398 mv88e6xxx_phy_init(chip); 4399 4400 if (chip->info->ops->get_eeprom && 4401 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4402 chip->eeprom_len = eeprom_len; 4403 4404 mutex_lock(&chip->reg_lock); 4405 err = mv88e6xxx_switch_reset(chip); 4406 mutex_unlock(&chip->reg_lock); 4407 if (err) 4408 goto out; 4409 4410 chip->irq = of_irq_get(np, 0); 4411 if (chip->irq == -EPROBE_DEFER) { 4412 err = chip->irq; 4413 goto out; 4414 } 4415 4416 /* Has to be performed before the MDIO bus is created, because 4417 * the PHYs will link their interrupts to these interrupt 4418 * controllers 4419 */ 4420 mutex_lock(&chip->reg_lock); 4421 if (chip->irq > 0) 4422 err = mv88e6xxx_g1_irq_setup(chip); 4423 else 4424 err = mv88e6xxx_irq_poll_setup(chip); 4425 mutex_unlock(&chip->reg_lock); 4426 4427 if (err) 4428 goto out; 4429 4430 if (chip->info->g2_irqs > 0) { 4431 err = mv88e6xxx_g2_irq_setup(chip); 4432 if (err) 4433 goto out_g1_irq; 4434 } 4435 4436 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4437 if (err) 4438 goto out_g2_irq; 4439 4440 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4441 if (err) 4442 goto out_g1_atu_prob_irq; 4443 4444 err = mv88e6xxx_mdios_register(chip, np); 4445 if (err) 4446 goto out_g1_vtu_prob_irq; 4447 4448 err = mv88e6xxx_register_switch(chip); 4449 if (err) 4450 goto out_mdio; 4451 4452 return 0; 4453 4454 out_mdio: 4455 mv88e6xxx_mdios_unregister(chip); 4456 out_g1_vtu_prob_irq: 4457 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4458 out_g1_atu_prob_irq: 4459 mv88e6xxx_g1_atu_prob_irq_free(chip); 4460 out_g2_irq: 4461 if (chip->info->g2_irqs > 0) 4462 mv88e6xxx_g2_irq_free(chip); 4463 out_g1_irq: 4464 mutex_lock(&chip->reg_lock); 4465 if (chip->irq > 0) 4466 mv88e6xxx_g1_irq_free(chip); 4467 else 4468 mv88e6xxx_irq_poll_free(chip); 4469 mutex_unlock(&chip->reg_lock); 4470 out: 4471 return err; 4472 } 4473 4474 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4475 { 4476 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4477 struct mv88e6xxx_chip *chip = ds->priv; 4478 4479 if (chip->info->ptp_support) { 4480 mv88e6xxx_hwtstamp_free(chip); 4481 mv88e6xxx_ptp_free(chip); 4482 } 4483 4484 mv88e6xxx_phy_destroy(chip); 4485 mv88e6xxx_unregister_switch(chip); 4486 mv88e6xxx_mdios_unregister(chip); 4487 4488 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4489 mv88e6xxx_g1_atu_prob_irq_free(chip); 4490 4491 if (chip->info->g2_irqs > 0) 4492 mv88e6xxx_g2_irq_free(chip); 4493 4494 mutex_lock(&chip->reg_lock); 4495 if (chip->irq > 0) 4496 mv88e6xxx_g1_irq_free(chip); 4497 else 4498 mv88e6xxx_irq_poll_free(chip); 4499 mutex_unlock(&chip->reg_lock); 4500 } 4501 4502 static const struct of_device_id mv88e6xxx_of_match[] = { 4503 { 4504 .compatible = "marvell,mv88e6085", 4505 .data = &mv88e6xxx_table[MV88E6085], 4506 }, 4507 { 4508 .compatible = "marvell,mv88e6190", 4509 .data = &mv88e6xxx_table[MV88E6190], 4510 }, 4511 { /* sentinel */ }, 4512 }; 4513 4514 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4515 4516 static struct mdio_driver mv88e6xxx_driver = { 4517 .probe = mv88e6xxx_probe, 4518 .remove = mv88e6xxx_remove, 4519 .mdiodrv.driver = { 4520 .name = "mv88e6085", 4521 .of_match_table = mv88e6xxx_of_match, 4522 }, 4523 }; 4524 4525 static int __init mv88e6xxx_init(void) 4526 { 4527 register_switch_driver(&mv88e6xxx_switch_drv); 4528 return mdio_driver_register(&mv88e6xxx_driver); 4529 } 4530 module_init(mv88e6xxx_init); 4531 4532 static void __exit mv88e6xxx_cleanup(void) 4533 { 4534 mdio_driver_unregister(&mv88e6xxx_driver); 4535 unregister_switch_driver(&mv88e6xxx_switch_drv); 4536 } 4537 module_exit(mv88e6xxx_cleanup); 4538 4539 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4540 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4541 MODULE_LICENSE("GPL"); 4542