1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 u16 ctl1; 265 int err; 266 267 mutex_lock(&chip->reg_lock); 268 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 269 mutex_unlock(&chip->reg_lock); 270 271 if (err) 272 goto out; 273 274 do { 275 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 276 if (reg & (1 << n)) { 277 sub_irq = irq_find_mapping(chip->g1_irq.domain, 278 n); 279 handle_nested_irq(sub_irq); 280 ++nhandled; 281 } 282 } 283 284 mutex_lock(&chip->reg_lock); 285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 286 if (err) 287 goto unlock; 288 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 289 unlock: 290 mutex_unlock(&chip->reg_lock); 291 if (err) 292 goto out; 293 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 294 } while (reg & ctl1); 295 296 out: 297 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 298 } 299 300 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 301 { 302 struct mv88e6xxx_chip *chip = dev_id; 303 304 return mv88e6xxx_g1_irq_thread_work(chip); 305 } 306 307 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 308 { 309 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 310 311 mutex_lock(&chip->reg_lock); 312 } 313 314 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 315 { 316 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 317 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 318 u16 reg; 319 int err; 320 321 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 322 if (err) 323 goto out; 324 325 reg &= ~mask; 326 reg |= (~chip->g1_irq.masked & mask); 327 328 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 329 if (err) 330 goto out; 331 332 out: 333 mutex_unlock(&chip->reg_lock); 334 } 335 336 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 337 .name = "mv88e6xxx-g1", 338 .irq_mask = mv88e6xxx_g1_irq_mask, 339 .irq_unmask = mv88e6xxx_g1_irq_unmask, 340 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 341 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 342 }; 343 344 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 345 unsigned int irq, 346 irq_hw_number_t hwirq) 347 { 348 struct mv88e6xxx_chip *chip = d->host_data; 349 350 irq_set_chip_data(irq, d->host_data); 351 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 352 irq_set_noprobe(irq); 353 354 return 0; 355 } 356 357 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 358 .map = mv88e6xxx_g1_irq_domain_map, 359 .xlate = irq_domain_xlate_twocell, 360 }; 361 362 /* To be called with reg_lock held */ 363 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 364 { 365 int irq, virq; 366 u16 mask; 367 368 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 369 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 370 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 371 372 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 373 virq = irq_find_mapping(chip->g1_irq.domain, irq); 374 irq_dispose_mapping(virq); 375 } 376 377 irq_domain_remove(chip->g1_irq.domain); 378 } 379 380 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 381 { 382 /* 383 * free_irq must be called without reg_lock taken because the irq 384 * handler takes this lock, too. 385 */ 386 free_irq(chip->irq, chip); 387 388 mutex_lock(&chip->reg_lock); 389 mv88e6xxx_g1_irq_free_common(chip); 390 mutex_unlock(&chip->reg_lock); 391 } 392 393 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 394 { 395 int err, irq, virq; 396 u16 reg, mask; 397 398 chip->g1_irq.nirqs = chip->info->g1_irqs; 399 chip->g1_irq.domain = irq_domain_add_simple( 400 NULL, chip->g1_irq.nirqs, 0, 401 &mv88e6xxx_g1_irq_domain_ops, chip); 402 if (!chip->g1_irq.domain) 403 return -ENOMEM; 404 405 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 406 irq_create_mapping(chip->g1_irq.domain, irq); 407 408 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 409 chip->g1_irq.masked = ~0; 410 411 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 412 if (err) 413 goto out_mapping; 414 415 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 416 417 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 418 if (err) 419 goto out_disable; 420 421 /* Reading the interrupt status clears (most of) them */ 422 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 423 if (err) 424 goto out_disable; 425 426 return 0; 427 428 out_disable: 429 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 430 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 431 432 out_mapping: 433 for (irq = 0; irq < 16; irq++) { 434 virq = irq_find_mapping(chip->g1_irq.domain, irq); 435 irq_dispose_mapping(virq); 436 } 437 438 irq_domain_remove(chip->g1_irq.domain); 439 440 return err; 441 } 442 443 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 444 { 445 int err; 446 447 err = mv88e6xxx_g1_irq_setup_common(chip); 448 if (err) 449 return err; 450 451 err = request_threaded_irq(chip->irq, NULL, 452 mv88e6xxx_g1_irq_thread_fn, 453 IRQF_ONESHOT | IRQF_SHARED, 454 dev_name(chip->dev), chip); 455 if (err) 456 mv88e6xxx_g1_irq_free_common(chip); 457 458 return err; 459 } 460 461 static void mv88e6xxx_irq_poll(struct kthread_work *work) 462 { 463 struct mv88e6xxx_chip *chip = container_of(work, 464 struct mv88e6xxx_chip, 465 irq_poll_work.work); 466 mv88e6xxx_g1_irq_thread_work(chip); 467 468 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 469 msecs_to_jiffies(100)); 470 } 471 472 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 473 { 474 int err; 475 476 err = mv88e6xxx_g1_irq_setup_common(chip); 477 if (err) 478 return err; 479 480 kthread_init_delayed_work(&chip->irq_poll_work, 481 mv88e6xxx_irq_poll); 482 483 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 484 if (IS_ERR(chip->kworker)) 485 return PTR_ERR(chip->kworker); 486 487 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 488 msecs_to_jiffies(100)); 489 490 return 0; 491 } 492 493 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 494 { 495 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 496 kthread_destroy_worker(chip->kworker); 497 498 mutex_lock(&chip->reg_lock); 499 mv88e6xxx_g1_irq_free_common(chip); 500 mutex_unlock(&chip->reg_lock); 501 } 502 503 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 504 { 505 int i; 506 507 for (i = 0; i < 16; i++) { 508 u16 val; 509 int err; 510 511 err = mv88e6xxx_read(chip, addr, reg, &val); 512 if (err) 513 return err; 514 515 if (!(val & mask)) 516 return 0; 517 518 usleep_range(1000, 2000); 519 } 520 521 dev_err(chip->dev, "Timeout while waiting for switch\n"); 522 return -ETIMEDOUT; 523 } 524 525 /* Indirect write to single pointer-data register with an Update bit */ 526 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 527 { 528 u16 val; 529 int err; 530 531 /* Wait until the previous operation is completed */ 532 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 533 if (err) 534 return err; 535 536 /* Set the Update bit to trigger a write operation */ 537 val = BIT(15) | update; 538 539 return mv88e6xxx_write(chip, addr, reg, val); 540 } 541 542 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 543 int link, int speed, int duplex, int pause, 544 phy_interface_t mode) 545 { 546 int err; 547 548 if (!chip->info->ops->port_set_link) 549 return 0; 550 551 /* Port's MAC control must not be changed unless the link is down */ 552 err = chip->info->ops->port_set_link(chip, port, 0); 553 if (err) 554 return err; 555 556 if (chip->info->ops->port_set_speed) { 557 err = chip->info->ops->port_set_speed(chip, port, speed); 558 if (err && err != -EOPNOTSUPP) 559 goto restore_link; 560 } 561 562 if (chip->info->ops->port_set_pause) { 563 err = chip->info->ops->port_set_pause(chip, port, pause); 564 if (err) 565 goto restore_link; 566 } 567 568 if (chip->info->ops->port_set_duplex) { 569 err = chip->info->ops->port_set_duplex(chip, port, duplex); 570 if (err && err != -EOPNOTSUPP) 571 goto restore_link; 572 } 573 574 if (chip->info->ops->port_set_rgmii_delay) { 575 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 576 if (err && err != -EOPNOTSUPP) 577 goto restore_link; 578 } 579 580 if (chip->info->ops->port_set_cmode) { 581 err = chip->info->ops->port_set_cmode(chip, port, mode); 582 if (err && err != -EOPNOTSUPP) 583 goto restore_link; 584 } 585 586 err = 0; 587 restore_link: 588 if (chip->info->ops->port_set_link(chip, port, link)) 589 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 590 591 return err; 592 } 593 594 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 595 { 596 struct mv88e6xxx_chip *chip = ds->priv; 597 598 return port < chip->info->num_internal_phys; 599 } 600 601 /* We expect the switch to perform auto negotiation if there is a real 602 * phy. However, in the case of a fixed link phy, we force the port 603 * settings from the fixed link settings. 604 */ 605 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 606 struct phy_device *phydev) 607 { 608 struct mv88e6xxx_chip *chip = ds->priv; 609 int err; 610 611 if (!phy_is_pseudo_fixed_link(phydev) && 612 mv88e6xxx_phy_is_internal(ds, port)) 613 return; 614 615 mutex_lock(&chip->reg_lock); 616 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 617 phydev->duplex, phydev->pause, 618 phydev->interface); 619 mutex_unlock(&chip->reg_lock); 620 621 if (err && err != -EOPNOTSUPP) 622 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 623 } 624 625 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 626 unsigned long *mask, 627 struct phylink_link_state *state) 628 { 629 if (!phy_interface_mode_is_8023z(state->interface)) { 630 /* 10M and 100M are only supported in non-802.3z mode */ 631 phylink_set(mask, 10baseT_Half); 632 phylink_set(mask, 10baseT_Full); 633 phylink_set(mask, 100baseT_Half); 634 phylink_set(mask, 100baseT_Full); 635 } 636 } 637 638 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 639 unsigned long *mask, 640 struct phylink_link_state *state) 641 { 642 /* FIXME: if the port is in 1000Base-X mode, then it only supports 643 * 1000M FD speeds. In this case, CMODE will indicate 5. 644 */ 645 phylink_set(mask, 1000baseT_Full); 646 phylink_set(mask, 1000baseX_Full); 647 648 mv88e6065_phylink_validate(chip, port, mask, state); 649 } 650 651 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 652 unsigned long *mask, 653 struct phylink_link_state *state) 654 { 655 /* No ethtool bits for 200Mbps */ 656 phylink_set(mask, 1000baseT_Full); 657 phylink_set(mask, 1000baseX_Full); 658 659 mv88e6065_phylink_validate(chip, port, mask, state); 660 } 661 662 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 663 unsigned long *mask, 664 struct phylink_link_state *state) 665 { 666 if (port >= 9) { 667 phylink_set(mask, 2500baseX_Full); 668 phylink_set(mask, 2500baseT_Full); 669 } 670 671 /* No ethtool bits for 200Mbps */ 672 phylink_set(mask, 1000baseT_Full); 673 phylink_set(mask, 1000baseX_Full); 674 675 mv88e6065_phylink_validate(chip, port, mask, state); 676 } 677 678 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 679 unsigned long *mask, 680 struct phylink_link_state *state) 681 { 682 if (port >= 9) { 683 phylink_set(mask, 10000baseT_Full); 684 phylink_set(mask, 10000baseKR_Full); 685 } 686 687 mv88e6390_phylink_validate(chip, port, mask, state); 688 } 689 690 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 691 unsigned long *supported, 692 struct phylink_link_state *state) 693 { 694 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 695 struct mv88e6xxx_chip *chip = ds->priv; 696 697 /* Allow all the expected bits */ 698 phylink_set(mask, Autoneg); 699 phylink_set(mask, Pause); 700 phylink_set_port_modes(mask); 701 702 if (chip->info->ops->phylink_validate) 703 chip->info->ops->phylink_validate(chip, port, mask, state); 704 705 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 706 bitmap_and(state->advertising, state->advertising, mask, 707 __ETHTOOL_LINK_MODE_MASK_NBITS); 708 709 /* We can only operate at 2500BaseX or 1000BaseX. If requested 710 * to advertise both, only report advertising at 2500BaseX. 711 */ 712 phylink_helper_basex_speed(state); 713 } 714 715 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 716 struct phylink_link_state *state) 717 { 718 struct mv88e6xxx_chip *chip = ds->priv; 719 int err; 720 721 mutex_lock(&chip->reg_lock); 722 if (chip->info->ops->port_link_state) 723 err = chip->info->ops->port_link_state(chip, port, state); 724 else 725 err = -EOPNOTSUPP; 726 mutex_unlock(&chip->reg_lock); 727 728 return err; 729 } 730 731 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 732 unsigned int mode, 733 const struct phylink_link_state *state) 734 { 735 struct mv88e6xxx_chip *chip = ds->priv; 736 int speed, duplex, link, pause, err; 737 738 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 739 return; 740 741 if (mode == MLO_AN_FIXED) { 742 link = LINK_FORCED_UP; 743 speed = state->speed; 744 duplex = state->duplex; 745 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 746 link = state->link; 747 speed = state->speed; 748 duplex = state->duplex; 749 } else { 750 speed = SPEED_UNFORCED; 751 duplex = DUPLEX_UNFORCED; 752 link = LINK_UNFORCED; 753 } 754 pause = !!phylink_test(state->advertising, Pause); 755 756 mutex_lock(&chip->reg_lock); 757 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 758 state->interface); 759 mutex_unlock(&chip->reg_lock); 760 761 if (err && err != -EOPNOTSUPP) 762 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 763 } 764 765 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 766 { 767 struct mv88e6xxx_chip *chip = ds->priv; 768 int err; 769 770 mutex_lock(&chip->reg_lock); 771 err = chip->info->ops->port_set_link(chip, port, link); 772 mutex_unlock(&chip->reg_lock); 773 774 if (err) 775 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 776 } 777 778 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 779 unsigned int mode, 780 phy_interface_t interface) 781 { 782 if (mode == MLO_AN_FIXED) 783 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 784 } 785 786 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 787 unsigned int mode, phy_interface_t interface, 788 struct phy_device *phydev) 789 { 790 if (mode == MLO_AN_FIXED) 791 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 792 } 793 794 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 795 { 796 if (!chip->info->ops->stats_snapshot) 797 return -EOPNOTSUPP; 798 799 return chip->info->ops->stats_snapshot(chip, port); 800 } 801 802 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 803 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 804 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 805 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 806 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 807 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 808 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 809 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 810 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 811 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 812 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 813 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 814 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 815 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 816 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 817 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 818 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 819 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 820 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 821 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 822 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 823 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 824 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 825 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 826 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 827 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 828 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 829 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 830 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 831 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 832 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 833 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 834 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 835 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 836 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 837 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 838 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 839 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 840 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 841 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 842 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 843 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 844 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 845 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 846 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 847 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 848 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 849 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 850 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 851 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 852 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 853 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 854 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 855 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 856 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 857 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 858 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 859 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 860 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 861 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 862 }; 863 864 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 865 struct mv88e6xxx_hw_stat *s, 866 int port, u16 bank1_select, 867 u16 histogram) 868 { 869 u32 low; 870 u32 high = 0; 871 u16 reg = 0; 872 int err; 873 u64 value; 874 875 switch (s->type) { 876 case STATS_TYPE_PORT: 877 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 878 if (err) 879 return U64_MAX; 880 881 low = reg; 882 if (s->size == 4) { 883 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 884 if (err) 885 return U64_MAX; 886 high = reg; 887 } 888 break; 889 case STATS_TYPE_BANK1: 890 reg = bank1_select; 891 /* fall through */ 892 case STATS_TYPE_BANK0: 893 reg |= s->reg | histogram; 894 mv88e6xxx_g1_stats_read(chip, reg, &low); 895 if (s->size == 8) 896 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 897 break; 898 default: 899 return U64_MAX; 900 } 901 value = (((u64)high) << 16) | low; 902 return value; 903 } 904 905 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 906 uint8_t *data, int types) 907 { 908 struct mv88e6xxx_hw_stat *stat; 909 int i, j; 910 911 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 912 stat = &mv88e6xxx_hw_stats[i]; 913 if (stat->type & types) { 914 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 915 ETH_GSTRING_LEN); 916 j++; 917 } 918 } 919 920 return j; 921 } 922 923 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 924 uint8_t *data) 925 { 926 return mv88e6xxx_stats_get_strings(chip, data, 927 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 928 } 929 930 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 931 uint8_t *data) 932 { 933 return mv88e6xxx_stats_get_strings(chip, data, 934 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 935 } 936 937 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 938 "atu_member_violation", 939 "atu_miss_violation", 940 "atu_full_violation", 941 "vtu_member_violation", 942 "vtu_miss_violation", 943 }; 944 945 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 946 { 947 unsigned int i; 948 949 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 950 strlcpy(data + i * ETH_GSTRING_LEN, 951 mv88e6xxx_atu_vtu_stats_strings[i], 952 ETH_GSTRING_LEN); 953 } 954 955 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 956 u32 stringset, uint8_t *data) 957 { 958 struct mv88e6xxx_chip *chip = ds->priv; 959 int count = 0; 960 961 if (stringset != ETH_SS_STATS) 962 return; 963 964 mutex_lock(&chip->reg_lock); 965 966 if (chip->info->ops->stats_get_strings) 967 count = chip->info->ops->stats_get_strings(chip, data); 968 969 if (chip->info->ops->serdes_get_strings) { 970 data += count * ETH_GSTRING_LEN; 971 count = chip->info->ops->serdes_get_strings(chip, port, data); 972 } 973 974 data += count * ETH_GSTRING_LEN; 975 mv88e6xxx_atu_vtu_get_strings(data); 976 977 mutex_unlock(&chip->reg_lock); 978 } 979 980 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 981 int types) 982 { 983 struct mv88e6xxx_hw_stat *stat; 984 int i, j; 985 986 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 987 stat = &mv88e6xxx_hw_stats[i]; 988 if (stat->type & types) 989 j++; 990 } 991 return j; 992 } 993 994 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 995 { 996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 997 STATS_TYPE_PORT); 998 } 999 1000 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1001 { 1002 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1003 STATS_TYPE_BANK1); 1004 } 1005 1006 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1007 { 1008 struct mv88e6xxx_chip *chip = ds->priv; 1009 int serdes_count = 0; 1010 int count = 0; 1011 1012 if (sset != ETH_SS_STATS) 1013 return 0; 1014 1015 mutex_lock(&chip->reg_lock); 1016 if (chip->info->ops->stats_get_sset_count) 1017 count = chip->info->ops->stats_get_sset_count(chip); 1018 if (count < 0) 1019 goto out; 1020 1021 if (chip->info->ops->serdes_get_sset_count) 1022 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1023 port); 1024 if (serdes_count < 0) { 1025 count = serdes_count; 1026 goto out; 1027 } 1028 count += serdes_count; 1029 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1030 1031 out: 1032 mutex_unlock(&chip->reg_lock); 1033 1034 return count; 1035 } 1036 1037 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1038 uint64_t *data, int types, 1039 u16 bank1_select, u16 histogram) 1040 { 1041 struct mv88e6xxx_hw_stat *stat; 1042 int i, j; 1043 1044 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1045 stat = &mv88e6xxx_hw_stats[i]; 1046 if (stat->type & types) { 1047 mutex_lock(&chip->reg_lock); 1048 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1049 bank1_select, 1050 histogram); 1051 mutex_unlock(&chip->reg_lock); 1052 1053 j++; 1054 } 1055 } 1056 return j; 1057 } 1058 1059 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1060 uint64_t *data) 1061 { 1062 return mv88e6xxx_stats_get_stats(chip, port, data, 1063 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1064 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1065 } 1066 1067 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1068 uint64_t *data) 1069 { 1070 return mv88e6xxx_stats_get_stats(chip, port, data, 1071 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1072 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1073 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1074 } 1075 1076 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1077 uint64_t *data) 1078 { 1079 return mv88e6xxx_stats_get_stats(chip, port, data, 1080 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1081 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1082 0); 1083 } 1084 1085 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1086 uint64_t *data) 1087 { 1088 *data++ = chip->ports[port].atu_member_violation; 1089 *data++ = chip->ports[port].atu_miss_violation; 1090 *data++ = chip->ports[port].atu_full_violation; 1091 *data++ = chip->ports[port].vtu_member_violation; 1092 *data++ = chip->ports[port].vtu_miss_violation; 1093 } 1094 1095 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1096 uint64_t *data) 1097 { 1098 int count = 0; 1099 1100 if (chip->info->ops->stats_get_stats) 1101 count = chip->info->ops->stats_get_stats(chip, port, data); 1102 1103 mutex_lock(&chip->reg_lock); 1104 if (chip->info->ops->serdes_get_stats) { 1105 data += count; 1106 count = chip->info->ops->serdes_get_stats(chip, port, data); 1107 } 1108 data += count; 1109 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1110 mutex_unlock(&chip->reg_lock); 1111 } 1112 1113 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1114 uint64_t *data) 1115 { 1116 struct mv88e6xxx_chip *chip = ds->priv; 1117 int ret; 1118 1119 mutex_lock(&chip->reg_lock); 1120 1121 ret = mv88e6xxx_stats_snapshot(chip, port); 1122 mutex_unlock(&chip->reg_lock); 1123 1124 if (ret < 0) 1125 return; 1126 1127 mv88e6xxx_get_stats(chip, port, data); 1128 1129 } 1130 1131 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1132 { 1133 return 32 * sizeof(u16); 1134 } 1135 1136 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1137 struct ethtool_regs *regs, void *_p) 1138 { 1139 struct mv88e6xxx_chip *chip = ds->priv; 1140 int err; 1141 u16 reg; 1142 u16 *p = _p; 1143 int i; 1144 1145 regs->version = chip->info->prod_num; 1146 1147 memset(p, 0xff, 32 * sizeof(u16)); 1148 1149 mutex_lock(&chip->reg_lock); 1150 1151 for (i = 0; i < 32; i++) { 1152 1153 err = mv88e6xxx_port_read(chip, port, i, ®); 1154 if (!err) 1155 p[i] = reg; 1156 } 1157 1158 mutex_unlock(&chip->reg_lock); 1159 } 1160 1161 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1162 struct ethtool_eee *e) 1163 { 1164 /* Nothing to do on the port's MAC */ 1165 return 0; 1166 } 1167 1168 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1169 struct ethtool_eee *e) 1170 { 1171 /* Nothing to do on the port's MAC */ 1172 return 0; 1173 } 1174 1175 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1176 { 1177 struct dsa_switch *ds = NULL; 1178 struct net_device *br; 1179 u16 pvlan; 1180 int i; 1181 1182 if (dev < DSA_MAX_SWITCHES) 1183 ds = chip->ds->dst->ds[dev]; 1184 1185 /* Prevent frames from unknown switch or port */ 1186 if (!ds || port >= ds->num_ports) 1187 return 0; 1188 1189 /* Frames from DSA links and CPU ports can egress any local port */ 1190 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1191 return mv88e6xxx_port_mask(chip); 1192 1193 br = ds->ports[port].bridge_dev; 1194 pvlan = 0; 1195 1196 /* Frames from user ports can egress any local DSA links and CPU ports, 1197 * as well as any local member of their bridge group. 1198 */ 1199 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1200 if (dsa_is_cpu_port(chip->ds, i) || 1201 dsa_is_dsa_port(chip->ds, i) || 1202 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1203 pvlan |= BIT(i); 1204 1205 return pvlan; 1206 } 1207 1208 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1209 { 1210 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1211 1212 /* prevent frames from going back out of the port they came in on */ 1213 output_ports &= ~BIT(port); 1214 1215 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1216 } 1217 1218 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1219 u8 state) 1220 { 1221 struct mv88e6xxx_chip *chip = ds->priv; 1222 int err; 1223 1224 mutex_lock(&chip->reg_lock); 1225 err = mv88e6xxx_port_set_state(chip, port, state); 1226 mutex_unlock(&chip->reg_lock); 1227 1228 if (err) 1229 dev_err(ds->dev, "p%d: failed to update state\n", port); 1230 } 1231 1232 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1233 { 1234 int err; 1235 1236 if (chip->info->ops->ieee_pri_map) { 1237 err = chip->info->ops->ieee_pri_map(chip); 1238 if (err) 1239 return err; 1240 } 1241 1242 if (chip->info->ops->ip_pri_map) { 1243 err = chip->info->ops->ip_pri_map(chip); 1244 if (err) 1245 return err; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1252 { 1253 int target, port; 1254 int err; 1255 1256 if (!chip->info->global2_addr) 1257 return 0; 1258 1259 /* Initialize the routing port to the 32 possible target devices */ 1260 for (target = 0; target < 32; target++) { 1261 port = 0x1f; 1262 if (target < DSA_MAX_SWITCHES) 1263 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1264 port = chip->ds->rtable[target]; 1265 1266 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1267 if (err) 1268 return err; 1269 } 1270 1271 if (chip->info->ops->set_cascade_port) { 1272 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1273 err = chip->info->ops->set_cascade_port(chip, port); 1274 if (err) 1275 return err; 1276 } 1277 1278 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1279 if (err) 1280 return err; 1281 1282 return 0; 1283 } 1284 1285 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1286 { 1287 /* Clear all trunk masks and mapping */ 1288 if (chip->info->global2_addr) 1289 return mv88e6xxx_g2_trunk_clear(chip); 1290 1291 return 0; 1292 } 1293 1294 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1295 { 1296 if (chip->info->ops->rmu_disable) 1297 return chip->info->ops->rmu_disable(chip); 1298 1299 return 0; 1300 } 1301 1302 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1303 { 1304 if (chip->info->ops->pot_clear) 1305 return chip->info->ops->pot_clear(chip); 1306 1307 return 0; 1308 } 1309 1310 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1311 { 1312 if (chip->info->ops->mgmt_rsvd2cpu) 1313 return chip->info->ops->mgmt_rsvd2cpu(chip); 1314 1315 return 0; 1316 } 1317 1318 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 int err; 1321 1322 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1323 if (err) 1324 return err; 1325 1326 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1327 if (err) 1328 return err; 1329 1330 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1331 } 1332 1333 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1334 { 1335 int port; 1336 int err; 1337 1338 if (!chip->info->ops->irl_init_all) 1339 return 0; 1340 1341 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1342 /* Disable ingress rate limiting by resetting all per port 1343 * ingress rate limit resources to their initial state. 1344 */ 1345 err = chip->info->ops->irl_init_all(chip, port); 1346 if (err) 1347 return err; 1348 } 1349 1350 return 0; 1351 } 1352 1353 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1354 { 1355 if (chip->info->ops->set_switch_mac) { 1356 u8 addr[ETH_ALEN]; 1357 1358 eth_random_addr(addr); 1359 1360 return chip->info->ops->set_switch_mac(chip, addr); 1361 } 1362 1363 return 0; 1364 } 1365 1366 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1367 { 1368 u16 pvlan = 0; 1369 1370 if (!mv88e6xxx_has_pvt(chip)) 1371 return -EOPNOTSUPP; 1372 1373 /* Skip the local source device, which uses in-chip port VLAN */ 1374 if (dev != chip->ds->index) 1375 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1376 1377 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1378 } 1379 1380 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1381 { 1382 int dev, port; 1383 int err; 1384 1385 if (!mv88e6xxx_has_pvt(chip)) 1386 return 0; 1387 1388 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1389 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1390 */ 1391 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1392 if (err) 1393 return err; 1394 1395 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1396 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1397 err = mv88e6xxx_pvt_map(chip, dev, port); 1398 if (err) 1399 return err; 1400 } 1401 } 1402 1403 return 0; 1404 } 1405 1406 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1407 { 1408 struct mv88e6xxx_chip *chip = ds->priv; 1409 int err; 1410 1411 mutex_lock(&chip->reg_lock); 1412 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1413 mutex_unlock(&chip->reg_lock); 1414 1415 if (err) 1416 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1417 } 1418 1419 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1420 { 1421 if (!chip->info->max_vid) 1422 return 0; 1423 1424 return mv88e6xxx_g1_vtu_flush(chip); 1425 } 1426 1427 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1428 struct mv88e6xxx_vtu_entry *entry) 1429 { 1430 if (!chip->info->ops->vtu_getnext) 1431 return -EOPNOTSUPP; 1432 1433 return chip->info->ops->vtu_getnext(chip, entry); 1434 } 1435 1436 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1437 struct mv88e6xxx_vtu_entry *entry) 1438 { 1439 if (!chip->info->ops->vtu_loadpurge) 1440 return -EOPNOTSUPP; 1441 1442 return chip->info->ops->vtu_loadpurge(chip, entry); 1443 } 1444 1445 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1446 { 1447 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1448 struct mv88e6xxx_vtu_entry vlan = { 1449 .vid = chip->info->max_vid, 1450 }; 1451 int i, err; 1452 1453 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1454 1455 /* Set every FID bit used by the (un)bridged ports */ 1456 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1457 err = mv88e6xxx_port_get_fid(chip, i, fid); 1458 if (err) 1459 return err; 1460 1461 set_bit(*fid, fid_bitmap); 1462 } 1463 1464 /* Set every FID bit used by the VLAN entries */ 1465 do { 1466 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1467 if (err) 1468 return err; 1469 1470 if (!vlan.valid) 1471 break; 1472 1473 set_bit(vlan.fid, fid_bitmap); 1474 } while (vlan.vid < chip->info->max_vid); 1475 1476 /* The reset value 0x000 is used to indicate that multiple address 1477 * databases are not needed. Return the next positive available. 1478 */ 1479 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1480 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1481 return -ENOSPC; 1482 1483 /* Clear the database */ 1484 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1485 } 1486 1487 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1488 struct mv88e6xxx_vtu_entry *entry, bool new) 1489 { 1490 int err; 1491 1492 if (!vid) 1493 return -EINVAL; 1494 1495 entry->vid = vid - 1; 1496 entry->valid = false; 1497 1498 err = mv88e6xxx_vtu_getnext(chip, entry); 1499 if (err) 1500 return err; 1501 1502 if (entry->vid == vid && entry->valid) 1503 return 0; 1504 1505 if (new) { 1506 int i; 1507 1508 /* Initialize a fresh VLAN entry */ 1509 memset(entry, 0, sizeof(*entry)); 1510 entry->valid = true; 1511 entry->vid = vid; 1512 1513 /* Exclude all ports */ 1514 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1515 entry->member[i] = 1516 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1517 1518 return mv88e6xxx_atu_new(chip, &entry->fid); 1519 } 1520 1521 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1522 return -EOPNOTSUPP; 1523 } 1524 1525 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1526 u16 vid_begin, u16 vid_end) 1527 { 1528 struct mv88e6xxx_chip *chip = ds->priv; 1529 struct mv88e6xxx_vtu_entry vlan = { 1530 .vid = vid_begin - 1, 1531 }; 1532 int i, err; 1533 1534 /* DSA and CPU ports have to be members of multiple vlans */ 1535 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1536 return 0; 1537 1538 if (!vid_begin) 1539 return -EOPNOTSUPP; 1540 1541 mutex_lock(&chip->reg_lock); 1542 1543 do { 1544 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1545 if (err) 1546 goto unlock; 1547 1548 if (!vlan.valid) 1549 break; 1550 1551 if (vlan.vid > vid_end) 1552 break; 1553 1554 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1555 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1556 continue; 1557 1558 if (!ds->ports[i].slave) 1559 continue; 1560 1561 if (vlan.member[i] == 1562 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1563 continue; 1564 1565 if (dsa_to_port(ds, i)->bridge_dev == 1566 ds->ports[port].bridge_dev) 1567 break; /* same bridge, check next VLAN */ 1568 1569 if (!dsa_to_port(ds, i)->bridge_dev) 1570 continue; 1571 1572 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1573 port, vlan.vid, i, 1574 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1575 err = -EOPNOTSUPP; 1576 goto unlock; 1577 } 1578 } while (vlan.vid < vid_end); 1579 1580 unlock: 1581 mutex_unlock(&chip->reg_lock); 1582 1583 return err; 1584 } 1585 1586 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1587 bool vlan_filtering) 1588 { 1589 struct mv88e6xxx_chip *chip = ds->priv; 1590 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1591 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1592 int err; 1593 1594 if (!chip->info->max_vid) 1595 return -EOPNOTSUPP; 1596 1597 mutex_lock(&chip->reg_lock); 1598 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1599 mutex_unlock(&chip->reg_lock); 1600 1601 return err; 1602 } 1603 1604 static int 1605 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1606 const struct switchdev_obj_port_vlan *vlan) 1607 { 1608 struct mv88e6xxx_chip *chip = ds->priv; 1609 int err; 1610 1611 if (!chip->info->max_vid) 1612 return -EOPNOTSUPP; 1613 1614 /* If the requested port doesn't belong to the same bridge as the VLAN 1615 * members, do not support it (yet) and fallback to software VLAN. 1616 */ 1617 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1618 vlan->vid_end); 1619 if (err) 1620 return err; 1621 1622 /* We don't need any dynamic resource from the kernel (yet), 1623 * so skip the prepare phase. 1624 */ 1625 return 0; 1626 } 1627 1628 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1629 const unsigned char *addr, u16 vid, 1630 u8 state) 1631 { 1632 struct mv88e6xxx_vtu_entry vlan; 1633 struct mv88e6xxx_atu_entry entry; 1634 int err; 1635 1636 /* Null VLAN ID corresponds to the port private database */ 1637 if (vid == 0) 1638 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1639 else 1640 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1641 if (err) 1642 return err; 1643 1644 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1645 ether_addr_copy(entry.mac, addr); 1646 eth_addr_dec(entry.mac); 1647 1648 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1649 if (err) 1650 return err; 1651 1652 /* Initialize a fresh ATU entry if it isn't found */ 1653 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1654 !ether_addr_equal(entry.mac, addr)) { 1655 memset(&entry, 0, sizeof(entry)); 1656 ether_addr_copy(entry.mac, addr); 1657 } 1658 1659 /* Purge the ATU entry only if no port is using it anymore */ 1660 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1661 entry.portvec &= ~BIT(port); 1662 if (!entry.portvec) 1663 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1664 } else { 1665 entry.portvec |= BIT(port); 1666 entry.state = state; 1667 } 1668 1669 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1670 } 1671 1672 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1673 u16 vid) 1674 { 1675 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1676 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1677 1678 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1679 } 1680 1681 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1682 { 1683 int port; 1684 int err; 1685 1686 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1687 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1688 if (err) 1689 return err; 1690 } 1691 1692 return 0; 1693 } 1694 1695 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1696 u16 vid, u8 member) 1697 { 1698 struct mv88e6xxx_vtu_entry vlan; 1699 int err; 1700 1701 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1702 if (err) 1703 return err; 1704 1705 vlan.member[port] = member; 1706 1707 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1708 if (err) 1709 return err; 1710 1711 return mv88e6xxx_broadcast_setup(chip, vid); 1712 } 1713 1714 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1715 const struct switchdev_obj_port_vlan *vlan) 1716 { 1717 struct mv88e6xxx_chip *chip = ds->priv; 1718 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1719 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1720 u8 member; 1721 u16 vid; 1722 1723 if (!chip->info->max_vid) 1724 return; 1725 1726 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1727 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1728 else if (untagged) 1729 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1730 else 1731 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1732 1733 mutex_lock(&chip->reg_lock); 1734 1735 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1736 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1737 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1738 vid, untagged ? 'u' : 't'); 1739 1740 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1741 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1742 vlan->vid_end); 1743 1744 mutex_unlock(&chip->reg_lock); 1745 } 1746 1747 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1748 int port, u16 vid) 1749 { 1750 struct mv88e6xxx_vtu_entry vlan; 1751 int i, err; 1752 1753 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1754 if (err) 1755 return err; 1756 1757 /* Tell switchdev if this VLAN is handled in software */ 1758 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1759 return -EOPNOTSUPP; 1760 1761 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1762 1763 /* keep the VLAN unless all ports are excluded */ 1764 vlan.valid = false; 1765 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1766 if (vlan.member[i] != 1767 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1768 vlan.valid = true; 1769 break; 1770 } 1771 } 1772 1773 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1774 if (err) 1775 return err; 1776 1777 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1778 } 1779 1780 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1781 const struct switchdev_obj_port_vlan *vlan) 1782 { 1783 struct mv88e6xxx_chip *chip = ds->priv; 1784 u16 pvid, vid; 1785 int err = 0; 1786 1787 if (!chip->info->max_vid) 1788 return -EOPNOTSUPP; 1789 1790 mutex_lock(&chip->reg_lock); 1791 1792 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1793 if (err) 1794 goto unlock; 1795 1796 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1797 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1798 if (err) 1799 goto unlock; 1800 1801 if (vid == pvid) { 1802 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1803 if (err) 1804 goto unlock; 1805 } 1806 } 1807 1808 unlock: 1809 mutex_unlock(&chip->reg_lock); 1810 1811 return err; 1812 } 1813 1814 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1815 const unsigned char *addr, u16 vid) 1816 { 1817 struct mv88e6xxx_chip *chip = ds->priv; 1818 int err; 1819 1820 mutex_lock(&chip->reg_lock); 1821 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1822 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1823 mutex_unlock(&chip->reg_lock); 1824 1825 return err; 1826 } 1827 1828 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1829 const unsigned char *addr, u16 vid) 1830 { 1831 struct mv88e6xxx_chip *chip = ds->priv; 1832 int err; 1833 1834 mutex_lock(&chip->reg_lock); 1835 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1836 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1837 mutex_unlock(&chip->reg_lock); 1838 1839 return err; 1840 } 1841 1842 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1843 u16 fid, u16 vid, int port, 1844 dsa_fdb_dump_cb_t *cb, void *data) 1845 { 1846 struct mv88e6xxx_atu_entry addr; 1847 bool is_static; 1848 int err; 1849 1850 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1851 eth_broadcast_addr(addr.mac); 1852 1853 do { 1854 mutex_lock(&chip->reg_lock); 1855 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1856 mutex_unlock(&chip->reg_lock); 1857 if (err) 1858 return err; 1859 1860 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1861 break; 1862 1863 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1864 continue; 1865 1866 if (!is_unicast_ether_addr(addr.mac)) 1867 continue; 1868 1869 is_static = (addr.state == 1870 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1871 err = cb(addr.mac, vid, is_static, data); 1872 if (err) 1873 return err; 1874 } while (!is_broadcast_ether_addr(addr.mac)); 1875 1876 return err; 1877 } 1878 1879 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1880 dsa_fdb_dump_cb_t *cb, void *data) 1881 { 1882 struct mv88e6xxx_vtu_entry vlan = { 1883 .vid = chip->info->max_vid, 1884 }; 1885 u16 fid; 1886 int err; 1887 1888 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1889 mutex_lock(&chip->reg_lock); 1890 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1891 mutex_unlock(&chip->reg_lock); 1892 1893 if (err) 1894 return err; 1895 1896 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1897 if (err) 1898 return err; 1899 1900 /* Dump VLANs' Filtering Information Databases */ 1901 do { 1902 mutex_lock(&chip->reg_lock); 1903 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1904 mutex_unlock(&chip->reg_lock); 1905 if (err) 1906 return err; 1907 1908 if (!vlan.valid) 1909 break; 1910 1911 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1912 cb, data); 1913 if (err) 1914 return err; 1915 } while (vlan.vid < chip->info->max_vid); 1916 1917 return err; 1918 } 1919 1920 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1921 dsa_fdb_dump_cb_t *cb, void *data) 1922 { 1923 struct mv88e6xxx_chip *chip = ds->priv; 1924 1925 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1926 } 1927 1928 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1929 struct net_device *br) 1930 { 1931 struct dsa_switch *ds; 1932 int port; 1933 int dev; 1934 int err; 1935 1936 /* Remap the Port VLAN of each local bridge group member */ 1937 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1938 if (chip->ds->ports[port].bridge_dev == br) { 1939 err = mv88e6xxx_port_vlan_map(chip, port); 1940 if (err) 1941 return err; 1942 } 1943 } 1944 1945 if (!mv88e6xxx_has_pvt(chip)) 1946 return 0; 1947 1948 /* Remap the Port VLAN of each cross-chip bridge group member */ 1949 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1950 ds = chip->ds->dst->ds[dev]; 1951 if (!ds) 1952 break; 1953 1954 for (port = 0; port < ds->num_ports; ++port) { 1955 if (ds->ports[port].bridge_dev == br) { 1956 err = mv88e6xxx_pvt_map(chip, dev, port); 1957 if (err) 1958 return err; 1959 } 1960 } 1961 } 1962 1963 return 0; 1964 } 1965 1966 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1967 struct net_device *br) 1968 { 1969 struct mv88e6xxx_chip *chip = ds->priv; 1970 int err; 1971 1972 mutex_lock(&chip->reg_lock); 1973 err = mv88e6xxx_bridge_map(chip, br); 1974 mutex_unlock(&chip->reg_lock); 1975 1976 return err; 1977 } 1978 1979 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1980 struct net_device *br) 1981 { 1982 struct mv88e6xxx_chip *chip = ds->priv; 1983 1984 mutex_lock(&chip->reg_lock); 1985 if (mv88e6xxx_bridge_map(chip, br) || 1986 mv88e6xxx_port_vlan_map(chip, port)) 1987 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1988 mutex_unlock(&chip->reg_lock); 1989 } 1990 1991 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1992 int port, struct net_device *br) 1993 { 1994 struct mv88e6xxx_chip *chip = ds->priv; 1995 int err; 1996 1997 if (!mv88e6xxx_has_pvt(chip)) 1998 return 0; 1999 2000 mutex_lock(&chip->reg_lock); 2001 err = mv88e6xxx_pvt_map(chip, dev, port); 2002 mutex_unlock(&chip->reg_lock); 2003 2004 return err; 2005 } 2006 2007 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2008 int port, struct net_device *br) 2009 { 2010 struct mv88e6xxx_chip *chip = ds->priv; 2011 2012 if (!mv88e6xxx_has_pvt(chip)) 2013 return; 2014 2015 mutex_lock(&chip->reg_lock); 2016 if (mv88e6xxx_pvt_map(chip, dev, port)) 2017 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2018 mutex_unlock(&chip->reg_lock); 2019 } 2020 2021 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2022 { 2023 if (chip->info->ops->reset) 2024 return chip->info->ops->reset(chip); 2025 2026 return 0; 2027 } 2028 2029 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2030 { 2031 struct gpio_desc *gpiod = chip->reset; 2032 2033 /* If there is a GPIO connected to the reset pin, toggle it */ 2034 if (gpiod) { 2035 gpiod_set_value_cansleep(gpiod, 1); 2036 usleep_range(10000, 20000); 2037 gpiod_set_value_cansleep(gpiod, 0); 2038 usleep_range(10000, 20000); 2039 } 2040 } 2041 2042 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2043 { 2044 int i, err; 2045 2046 /* Set all ports to the Disabled state */ 2047 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2048 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2049 if (err) 2050 return err; 2051 } 2052 2053 /* Wait for transmit queues to drain, 2054 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2055 */ 2056 usleep_range(2000, 4000); 2057 2058 return 0; 2059 } 2060 2061 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2062 { 2063 int err; 2064 2065 err = mv88e6xxx_disable_ports(chip); 2066 if (err) 2067 return err; 2068 2069 mv88e6xxx_hardware_reset(chip); 2070 2071 return mv88e6xxx_software_reset(chip); 2072 } 2073 2074 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2075 enum mv88e6xxx_frame_mode frame, 2076 enum mv88e6xxx_egress_mode egress, u16 etype) 2077 { 2078 int err; 2079 2080 if (!chip->info->ops->port_set_frame_mode) 2081 return -EOPNOTSUPP; 2082 2083 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2084 if (err) 2085 return err; 2086 2087 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2088 if (err) 2089 return err; 2090 2091 if (chip->info->ops->port_set_ether_type) 2092 return chip->info->ops->port_set_ether_type(chip, port, etype); 2093 2094 return 0; 2095 } 2096 2097 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2098 { 2099 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2100 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2101 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2102 } 2103 2104 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2105 { 2106 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2107 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2108 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2109 } 2110 2111 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2112 { 2113 return mv88e6xxx_set_port_mode(chip, port, 2114 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2115 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2116 ETH_P_EDSA); 2117 } 2118 2119 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2120 { 2121 if (dsa_is_dsa_port(chip->ds, port)) 2122 return mv88e6xxx_set_port_mode_dsa(chip, port); 2123 2124 if (dsa_is_user_port(chip->ds, port)) 2125 return mv88e6xxx_set_port_mode_normal(chip, port); 2126 2127 /* Setup CPU port mode depending on its supported tag format */ 2128 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2129 return mv88e6xxx_set_port_mode_dsa(chip, port); 2130 2131 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2132 return mv88e6xxx_set_port_mode_edsa(chip, port); 2133 2134 return -EINVAL; 2135 } 2136 2137 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2138 { 2139 bool message = dsa_is_dsa_port(chip->ds, port); 2140 2141 return mv88e6xxx_port_set_message_port(chip, port, message); 2142 } 2143 2144 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2145 { 2146 struct dsa_switch *ds = chip->ds; 2147 bool flood; 2148 2149 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2150 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2151 if (chip->info->ops->port_set_egress_floods) 2152 return chip->info->ops->port_set_egress_floods(chip, port, 2153 flood, flood); 2154 2155 return 0; 2156 } 2157 2158 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2159 bool on) 2160 { 2161 if (chip->info->ops->serdes_power) 2162 return chip->info->ops->serdes_power(chip, port, on); 2163 2164 return 0; 2165 } 2166 2167 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2168 { 2169 struct dsa_switch *ds = chip->ds; 2170 int upstream_port; 2171 int err; 2172 2173 upstream_port = dsa_upstream_port(ds, port); 2174 if (chip->info->ops->port_set_upstream_port) { 2175 err = chip->info->ops->port_set_upstream_port(chip, port, 2176 upstream_port); 2177 if (err) 2178 return err; 2179 } 2180 2181 if (port == upstream_port) { 2182 if (chip->info->ops->set_cpu_port) { 2183 err = chip->info->ops->set_cpu_port(chip, 2184 upstream_port); 2185 if (err) 2186 return err; 2187 } 2188 2189 if (chip->info->ops->set_egress_port) { 2190 err = chip->info->ops->set_egress_port(chip, 2191 upstream_port); 2192 if (err) 2193 return err; 2194 } 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2201 { 2202 struct dsa_switch *ds = chip->ds; 2203 int err; 2204 u16 reg; 2205 2206 chip->ports[port].chip = chip; 2207 chip->ports[port].port = port; 2208 2209 /* MAC Forcing register: don't force link, speed, duplex or flow control 2210 * state to any particular values on physical ports, but force the CPU 2211 * port and all DSA ports to their maximum bandwidth and full duplex. 2212 */ 2213 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2214 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2215 SPEED_MAX, DUPLEX_FULL, 2216 PAUSE_OFF, 2217 PHY_INTERFACE_MODE_NA); 2218 else 2219 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2220 SPEED_UNFORCED, DUPLEX_UNFORCED, 2221 PAUSE_ON, 2222 PHY_INTERFACE_MODE_NA); 2223 if (err) 2224 return err; 2225 2226 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2227 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2228 * tunneling, determine priority by looking at 802.1p and IP 2229 * priority fields (IP prio has precedence), and set STP state 2230 * to Forwarding. 2231 * 2232 * If this is the CPU link, use DSA or EDSA tagging depending 2233 * on which tagging mode was configured. 2234 * 2235 * If this is a link to another switch, use DSA tagging mode. 2236 * 2237 * If this is the upstream port for this switch, enable 2238 * forwarding of unknown unicasts and multicasts. 2239 */ 2240 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2241 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2242 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2243 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2244 if (err) 2245 return err; 2246 2247 err = mv88e6xxx_setup_port_mode(chip, port); 2248 if (err) 2249 return err; 2250 2251 err = mv88e6xxx_setup_egress_floods(chip, port); 2252 if (err) 2253 return err; 2254 2255 /* Enable the SERDES interface for DSA and CPU ports. Normal 2256 * ports SERDES are enabled when the port is enabled, thus 2257 * saving a bit of power. 2258 */ 2259 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2260 err = mv88e6xxx_serdes_power(chip, port, true); 2261 if (err) 2262 return err; 2263 } 2264 2265 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2266 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2267 * untagged frames on this port, do a destination address lookup on all 2268 * received packets as usual, disable ARP mirroring and don't send a 2269 * copy of all transmitted/received frames on this port to the CPU. 2270 */ 2271 err = mv88e6xxx_port_set_map_da(chip, port); 2272 if (err) 2273 return err; 2274 2275 err = mv88e6xxx_setup_upstream_port(chip, port); 2276 if (err) 2277 return err; 2278 2279 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2280 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2281 if (err) 2282 return err; 2283 2284 if (chip->info->ops->port_set_jumbo_size) { 2285 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2286 if (err) 2287 return err; 2288 } 2289 2290 /* Port Association Vector: when learning source addresses 2291 * of packets, add the address to the address database using 2292 * a port bitmap that has only the bit for this port set and 2293 * the other bits clear. 2294 */ 2295 reg = 1 << port; 2296 /* Disable learning for CPU port */ 2297 if (dsa_is_cpu_port(ds, port)) 2298 reg = 0; 2299 2300 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2301 reg); 2302 if (err) 2303 return err; 2304 2305 /* Egress rate control 2: disable egress rate control. */ 2306 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2307 0x0000); 2308 if (err) 2309 return err; 2310 2311 if (chip->info->ops->port_pause_limit) { 2312 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2313 if (err) 2314 return err; 2315 } 2316 2317 if (chip->info->ops->port_disable_learn_limit) { 2318 err = chip->info->ops->port_disable_learn_limit(chip, port); 2319 if (err) 2320 return err; 2321 } 2322 2323 if (chip->info->ops->port_disable_pri_override) { 2324 err = chip->info->ops->port_disable_pri_override(chip, port); 2325 if (err) 2326 return err; 2327 } 2328 2329 if (chip->info->ops->port_tag_remap) { 2330 err = chip->info->ops->port_tag_remap(chip, port); 2331 if (err) 2332 return err; 2333 } 2334 2335 if (chip->info->ops->port_egress_rate_limiting) { 2336 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2337 if (err) 2338 return err; 2339 } 2340 2341 err = mv88e6xxx_setup_message_port(chip, port); 2342 if (err) 2343 return err; 2344 2345 /* Port based VLAN map: give each port the same default address 2346 * database, and allow bidirectional communication between the 2347 * CPU and DSA port(s), and the other ports. 2348 */ 2349 err = mv88e6xxx_port_set_fid(chip, port, 0); 2350 if (err) 2351 return err; 2352 2353 err = mv88e6xxx_port_vlan_map(chip, port); 2354 if (err) 2355 return err; 2356 2357 /* Default VLAN ID and priority: don't set a default VLAN 2358 * ID, and set the default packet priority to zero. 2359 */ 2360 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2361 } 2362 2363 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2364 struct phy_device *phydev) 2365 { 2366 struct mv88e6xxx_chip *chip = ds->priv; 2367 int err; 2368 2369 mutex_lock(&chip->reg_lock); 2370 2371 err = mv88e6xxx_serdes_power(chip, port, true); 2372 2373 if (!err && chip->info->ops->serdes_irq_setup) 2374 err = chip->info->ops->serdes_irq_setup(chip, port); 2375 2376 mutex_unlock(&chip->reg_lock); 2377 2378 return err; 2379 } 2380 2381 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2382 struct phy_device *phydev) 2383 { 2384 struct mv88e6xxx_chip *chip = ds->priv; 2385 2386 mutex_lock(&chip->reg_lock); 2387 2388 if (chip->info->ops->serdes_irq_free) 2389 chip->info->ops->serdes_irq_free(chip, port); 2390 2391 if (mv88e6xxx_serdes_power(chip, port, false)) 2392 dev_err(chip->dev, "failed to power off SERDES\n"); 2393 2394 mutex_unlock(&chip->reg_lock); 2395 } 2396 2397 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2398 unsigned int ageing_time) 2399 { 2400 struct mv88e6xxx_chip *chip = ds->priv; 2401 int err; 2402 2403 mutex_lock(&chip->reg_lock); 2404 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2405 mutex_unlock(&chip->reg_lock); 2406 2407 return err; 2408 } 2409 2410 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2411 { 2412 int err; 2413 2414 /* Initialize the statistics unit */ 2415 if (chip->info->ops->stats_set_histogram) { 2416 err = chip->info->ops->stats_set_histogram(chip); 2417 if (err) 2418 return err; 2419 } 2420 2421 return mv88e6xxx_g1_stats_clear(chip); 2422 } 2423 2424 /* The mv88e6390 has some hidden registers used for debug and 2425 * development. The errata also makes use of them. 2426 */ 2427 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2428 int reg, u16 val) 2429 { 2430 u16 ctrl; 2431 int err; 2432 2433 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2434 PORT_RESERVED_1A, val); 2435 if (err) 2436 return err; 2437 2438 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2439 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2440 reg; 2441 2442 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2443 PORT_RESERVED_1A, ctrl); 2444 } 2445 2446 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2447 { 2448 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT, 2449 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY); 2450 } 2451 2452 2453 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2454 int reg, u16 *val) 2455 { 2456 u16 ctrl; 2457 int err; 2458 2459 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2460 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2461 reg; 2462 2463 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2464 PORT_RESERVED_1A, ctrl); 2465 if (err) 2466 return err; 2467 2468 err = mv88e6390_hidden_wait(chip); 2469 if (err) 2470 return err; 2471 2472 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2473 PORT_RESERVED_1A, val); 2474 } 2475 2476 /* Check if the errata has already been applied. */ 2477 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2478 { 2479 int port; 2480 int err; 2481 u16 val; 2482 2483 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2484 err = mv88e6390_hidden_read(chip, port, 0, &val); 2485 if (err) { 2486 dev_err(chip->dev, 2487 "Error reading hidden register: %d\n", err); 2488 return false; 2489 } 2490 if (val != 0x01c0) 2491 return false; 2492 } 2493 2494 return true; 2495 } 2496 2497 /* The 6390 copper ports have an errata which require poking magic 2498 * values into undocumented hidden registers and then performing a 2499 * software reset. 2500 */ 2501 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2502 { 2503 int port; 2504 int err; 2505 2506 if (mv88e6390_setup_errata_applied(chip)) 2507 return 0; 2508 2509 /* Set the ports into blocking mode */ 2510 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2511 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2512 if (err) 2513 return err; 2514 } 2515 2516 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2517 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2518 if (err) 2519 return err; 2520 } 2521 2522 return mv88e6xxx_software_reset(chip); 2523 } 2524 2525 static int mv88e6xxx_setup(struct dsa_switch *ds) 2526 { 2527 struct mv88e6xxx_chip *chip = ds->priv; 2528 u8 cmode; 2529 int err; 2530 int i; 2531 2532 chip->ds = ds; 2533 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2534 2535 mutex_lock(&chip->reg_lock); 2536 2537 if (chip->info->ops->setup_errata) { 2538 err = chip->info->ops->setup_errata(chip); 2539 if (err) 2540 goto unlock; 2541 } 2542 2543 /* Cache the cmode of each port. */ 2544 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2545 if (chip->info->ops->port_get_cmode) { 2546 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2547 if (err) 2548 goto unlock; 2549 2550 chip->ports[i].cmode = cmode; 2551 } 2552 } 2553 2554 /* Setup Switch Port Registers */ 2555 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2556 if (dsa_is_unused_port(ds, i)) 2557 continue; 2558 2559 err = mv88e6xxx_setup_port(chip, i); 2560 if (err) 2561 goto unlock; 2562 } 2563 2564 err = mv88e6xxx_irl_setup(chip); 2565 if (err) 2566 goto unlock; 2567 2568 err = mv88e6xxx_mac_setup(chip); 2569 if (err) 2570 goto unlock; 2571 2572 err = mv88e6xxx_phy_setup(chip); 2573 if (err) 2574 goto unlock; 2575 2576 err = mv88e6xxx_vtu_setup(chip); 2577 if (err) 2578 goto unlock; 2579 2580 err = mv88e6xxx_pvt_setup(chip); 2581 if (err) 2582 goto unlock; 2583 2584 err = mv88e6xxx_atu_setup(chip); 2585 if (err) 2586 goto unlock; 2587 2588 err = mv88e6xxx_broadcast_setup(chip, 0); 2589 if (err) 2590 goto unlock; 2591 2592 err = mv88e6xxx_pot_setup(chip); 2593 if (err) 2594 goto unlock; 2595 2596 err = mv88e6xxx_rmu_setup(chip); 2597 if (err) 2598 goto unlock; 2599 2600 err = mv88e6xxx_rsvd2cpu_setup(chip); 2601 if (err) 2602 goto unlock; 2603 2604 err = mv88e6xxx_trunk_setup(chip); 2605 if (err) 2606 goto unlock; 2607 2608 err = mv88e6xxx_devmap_setup(chip); 2609 if (err) 2610 goto unlock; 2611 2612 err = mv88e6xxx_pri_setup(chip); 2613 if (err) 2614 goto unlock; 2615 2616 /* Setup PTP Hardware Clock and timestamping */ 2617 if (chip->info->ptp_support) { 2618 err = mv88e6xxx_ptp_setup(chip); 2619 if (err) 2620 goto unlock; 2621 2622 err = mv88e6xxx_hwtstamp_setup(chip); 2623 if (err) 2624 goto unlock; 2625 } 2626 2627 err = mv88e6xxx_stats_setup(chip); 2628 if (err) 2629 goto unlock; 2630 2631 unlock: 2632 mutex_unlock(&chip->reg_lock); 2633 2634 return err; 2635 } 2636 2637 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2638 { 2639 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2640 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2641 u16 val; 2642 int err; 2643 2644 if (!chip->info->ops->phy_read) 2645 return -EOPNOTSUPP; 2646 2647 mutex_lock(&chip->reg_lock); 2648 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2649 mutex_unlock(&chip->reg_lock); 2650 2651 if (reg == MII_PHYSID2) { 2652 /* Some internal PHYs don't have a model number. */ 2653 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2654 /* Then there is the 6165 family. It gets is 2655 * PHYs correct. But it can also have two 2656 * SERDES interfaces in the PHY address 2657 * space. And these don't have a model 2658 * number. But they are not PHYs, so we don't 2659 * want to give them something a PHY driver 2660 * will recognise. 2661 * 2662 * Use the mv88e6390 family model number 2663 * instead, for anything which really could be 2664 * a PHY, 2665 */ 2666 if (!(val & 0x3f0)) 2667 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2668 } 2669 2670 return err ? err : val; 2671 } 2672 2673 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2674 { 2675 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2676 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2677 int err; 2678 2679 if (!chip->info->ops->phy_write) 2680 return -EOPNOTSUPP; 2681 2682 mutex_lock(&chip->reg_lock); 2683 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2684 mutex_unlock(&chip->reg_lock); 2685 2686 return err; 2687 } 2688 2689 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2690 struct device_node *np, 2691 bool external) 2692 { 2693 static int index; 2694 struct mv88e6xxx_mdio_bus *mdio_bus; 2695 struct mii_bus *bus; 2696 int err; 2697 2698 if (external) { 2699 mutex_lock(&chip->reg_lock); 2700 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2701 mutex_unlock(&chip->reg_lock); 2702 2703 if (err) 2704 return err; 2705 } 2706 2707 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2708 if (!bus) 2709 return -ENOMEM; 2710 2711 mdio_bus = bus->priv; 2712 mdio_bus->bus = bus; 2713 mdio_bus->chip = chip; 2714 INIT_LIST_HEAD(&mdio_bus->list); 2715 mdio_bus->external = external; 2716 2717 if (np) { 2718 bus->name = np->full_name; 2719 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2720 } else { 2721 bus->name = "mv88e6xxx SMI"; 2722 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2723 } 2724 2725 bus->read = mv88e6xxx_mdio_read; 2726 bus->write = mv88e6xxx_mdio_write; 2727 bus->parent = chip->dev; 2728 2729 if (!external) { 2730 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2731 if (err) 2732 return err; 2733 } 2734 2735 err = of_mdiobus_register(bus, np); 2736 if (err) { 2737 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2738 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2739 return err; 2740 } 2741 2742 if (external) 2743 list_add_tail(&mdio_bus->list, &chip->mdios); 2744 else 2745 list_add(&mdio_bus->list, &chip->mdios); 2746 2747 return 0; 2748 } 2749 2750 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2751 { .compatible = "marvell,mv88e6xxx-mdio-external", 2752 .data = (void *)true }, 2753 { }, 2754 }; 2755 2756 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2757 2758 { 2759 struct mv88e6xxx_mdio_bus *mdio_bus; 2760 struct mii_bus *bus; 2761 2762 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2763 bus = mdio_bus->bus; 2764 2765 if (!mdio_bus->external) 2766 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2767 2768 mdiobus_unregister(bus); 2769 } 2770 } 2771 2772 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2773 struct device_node *np) 2774 { 2775 const struct of_device_id *match; 2776 struct device_node *child; 2777 int err; 2778 2779 /* Always register one mdio bus for the internal/default mdio 2780 * bus. This maybe represented in the device tree, but is 2781 * optional. 2782 */ 2783 child = of_get_child_by_name(np, "mdio"); 2784 err = mv88e6xxx_mdio_register(chip, child, false); 2785 if (err) 2786 return err; 2787 2788 /* Walk the device tree, and see if there are any other nodes 2789 * which say they are compatible with the external mdio 2790 * bus. 2791 */ 2792 for_each_available_child_of_node(np, child) { 2793 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2794 if (match) { 2795 err = mv88e6xxx_mdio_register(chip, child, true); 2796 if (err) { 2797 mv88e6xxx_mdios_unregister(chip); 2798 return err; 2799 } 2800 } 2801 } 2802 2803 return 0; 2804 } 2805 2806 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2807 { 2808 struct mv88e6xxx_chip *chip = ds->priv; 2809 2810 return chip->eeprom_len; 2811 } 2812 2813 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2814 struct ethtool_eeprom *eeprom, u8 *data) 2815 { 2816 struct mv88e6xxx_chip *chip = ds->priv; 2817 int err; 2818 2819 if (!chip->info->ops->get_eeprom) 2820 return -EOPNOTSUPP; 2821 2822 mutex_lock(&chip->reg_lock); 2823 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2824 mutex_unlock(&chip->reg_lock); 2825 2826 if (err) 2827 return err; 2828 2829 eeprom->magic = 0xc3ec4951; 2830 2831 return 0; 2832 } 2833 2834 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2835 struct ethtool_eeprom *eeprom, u8 *data) 2836 { 2837 struct mv88e6xxx_chip *chip = ds->priv; 2838 int err; 2839 2840 if (!chip->info->ops->set_eeprom) 2841 return -EOPNOTSUPP; 2842 2843 if (eeprom->magic != 0xc3ec4951) 2844 return -EINVAL; 2845 2846 mutex_lock(&chip->reg_lock); 2847 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2848 mutex_unlock(&chip->reg_lock); 2849 2850 return err; 2851 } 2852 2853 static const struct mv88e6xxx_ops mv88e6085_ops = { 2854 /* MV88E6XXX_FAMILY_6097 */ 2855 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2856 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2857 .irl_init_all = mv88e6352_g2_irl_init_all, 2858 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2859 .phy_read = mv88e6185_phy_ppu_read, 2860 .phy_write = mv88e6185_phy_ppu_write, 2861 .port_set_link = mv88e6xxx_port_set_link, 2862 .port_set_duplex = mv88e6xxx_port_set_duplex, 2863 .port_set_speed = mv88e6185_port_set_speed, 2864 .port_tag_remap = mv88e6095_port_tag_remap, 2865 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2866 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2867 .port_set_ether_type = mv88e6351_port_set_ether_type, 2868 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2869 .port_pause_limit = mv88e6097_port_pause_limit, 2870 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2871 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2872 .port_link_state = mv88e6352_port_link_state, 2873 .port_get_cmode = mv88e6185_port_get_cmode, 2874 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2875 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2876 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2877 .stats_get_strings = mv88e6095_stats_get_strings, 2878 .stats_get_stats = mv88e6095_stats_get_stats, 2879 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2880 .set_egress_port = mv88e6095_g1_set_egress_port, 2881 .watchdog_ops = &mv88e6097_watchdog_ops, 2882 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2883 .pot_clear = mv88e6xxx_g2_pot_clear, 2884 .ppu_enable = mv88e6185_g1_ppu_enable, 2885 .ppu_disable = mv88e6185_g1_ppu_disable, 2886 .reset = mv88e6185_g1_reset, 2887 .rmu_disable = mv88e6085_g1_rmu_disable, 2888 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2889 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2890 .phylink_validate = mv88e6185_phylink_validate, 2891 }; 2892 2893 static const struct mv88e6xxx_ops mv88e6095_ops = { 2894 /* MV88E6XXX_FAMILY_6095 */ 2895 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2896 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2897 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2898 .phy_read = mv88e6185_phy_ppu_read, 2899 .phy_write = mv88e6185_phy_ppu_write, 2900 .port_set_link = mv88e6xxx_port_set_link, 2901 .port_set_duplex = mv88e6xxx_port_set_duplex, 2902 .port_set_speed = mv88e6185_port_set_speed, 2903 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2904 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2905 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2906 .port_link_state = mv88e6185_port_link_state, 2907 .port_get_cmode = mv88e6185_port_get_cmode, 2908 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2909 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2910 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2911 .stats_get_strings = mv88e6095_stats_get_strings, 2912 .stats_get_stats = mv88e6095_stats_get_stats, 2913 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2914 .ppu_enable = mv88e6185_g1_ppu_enable, 2915 .ppu_disable = mv88e6185_g1_ppu_disable, 2916 .reset = mv88e6185_g1_reset, 2917 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2918 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2919 .phylink_validate = mv88e6185_phylink_validate, 2920 }; 2921 2922 static const struct mv88e6xxx_ops mv88e6097_ops = { 2923 /* MV88E6XXX_FAMILY_6097 */ 2924 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2925 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2926 .irl_init_all = mv88e6352_g2_irl_init_all, 2927 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2928 .phy_read = mv88e6xxx_g2_smi_phy_read, 2929 .phy_write = mv88e6xxx_g2_smi_phy_write, 2930 .port_set_link = mv88e6xxx_port_set_link, 2931 .port_set_duplex = mv88e6xxx_port_set_duplex, 2932 .port_set_speed = mv88e6185_port_set_speed, 2933 .port_tag_remap = mv88e6095_port_tag_remap, 2934 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2935 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2936 .port_set_ether_type = mv88e6351_port_set_ether_type, 2937 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2938 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2939 .port_pause_limit = mv88e6097_port_pause_limit, 2940 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2941 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2942 .port_link_state = mv88e6352_port_link_state, 2943 .port_get_cmode = mv88e6185_port_get_cmode, 2944 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2945 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2946 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2947 .stats_get_strings = mv88e6095_stats_get_strings, 2948 .stats_get_stats = mv88e6095_stats_get_stats, 2949 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2950 .set_egress_port = mv88e6095_g1_set_egress_port, 2951 .watchdog_ops = &mv88e6097_watchdog_ops, 2952 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2953 .pot_clear = mv88e6xxx_g2_pot_clear, 2954 .reset = mv88e6352_g1_reset, 2955 .rmu_disable = mv88e6085_g1_rmu_disable, 2956 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2957 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2958 .phylink_validate = mv88e6185_phylink_validate, 2959 }; 2960 2961 static const struct mv88e6xxx_ops mv88e6123_ops = { 2962 /* MV88E6XXX_FAMILY_6165 */ 2963 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2964 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2965 .irl_init_all = mv88e6352_g2_irl_init_all, 2966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2967 .phy_read = mv88e6xxx_g2_smi_phy_read, 2968 .phy_write = mv88e6xxx_g2_smi_phy_write, 2969 .port_set_link = mv88e6xxx_port_set_link, 2970 .port_set_duplex = mv88e6xxx_port_set_duplex, 2971 .port_set_speed = mv88e6185_port_set_speed, 2972 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2973 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2974 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2975 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2976 .port_link_state = mv88e6352_port_link_state, 2977 .port_get_cmode = mv88e6185_port_get_cmode, 2978 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2979 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2980 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2981 .stats_get_strings = mv88e6095_stats_get_strings, 2982 .stats_get_stats = mv88e6095_stats_get_stats, 2983 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2984 .set_egress_port = mv88e6095_g1_set_egress_port, 2985 .watchdog_ops = &mv88e6097_watchdog_ops, 2986 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2987 .pot_clear = mv88e6xxx_g2_pot_clear, 2988 .reset = mv88e6352_g1_reset, 2989 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2990 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2991 .phylink_validate = mv88e6185_phylink_validate, 2992 }; 2993 2994 static const struct mv88e6xxx_ops mv88e6131_ops = { 2995 /* MV88E6XXX_FAMILY_6185 */ 2996 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2997 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2998 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2999 .phy_read = mv88e6185_phy_ppu_read, 3000 .phy_write = mv88e6185_phy_ppu_write, 3001 .port_set_link = mv88e6xxx_port_set_link, 3002 .port_set_duplex = mv88e6xxx_port_set_duplex, 3003 .port_set_speed = mv88e6185_port_set_speed, 3004 .port_tag_remap = mv88e6095_port_tag_remap, 3005 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3006 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3007 .port_set_ether_type = mv88e6351_port_set_ether_type, 3008 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3009 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3010 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3011 .port_pause_limit = mv88e6097_port_pause_limit, 3012 .port_set_pause = mv88e6185_port_set_pause, 3013 .port_link_state = mv88e6352_port_link_state, 3014 .port_get_cmode = mv88e6185_port_get_cmode, 3015 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3016 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3017 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3018 .stats_get_strings = mv88e6095_stats_get_strings, 3019 .stats_get_stats = mv88e6095_stats_get_stats, 3020 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3021 .set_egress_port = mv88e6095_g1_set_egress_port, 3022 .watchdog_ops = &mv88e6097_watchdog_ops, 3023 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3024 .ppu_enable = mv88e6185_g1_ppu_enable, 3025 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3026 .ppu_disable = mv88e6185_g1_ppu_disable, 3027 .reset = mv88e6185_g1_reset, 3028 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3029 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3030 .phylink_validate = mv88e6185_phylink_validate, 3031 }; 3032 3033 static const struct mv88e6xxx_ops mv88e6141_ops = { 3034 /* MV88E6XXX_FAMILY_6341 */ 3035 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3036 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3037 .irl_init_all = mv88e6352_g2_irl_init_all, 3038 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3039 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3040 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3041 .phy_read = mv88e6xxx_g2_smi_phy_read, 3042 .phy_write = mv88e6xxx_g2_smi_phy_write, 3043 .port_set_link = mv88e6xxx_port_set_link, 3044 .port_set_duplex = mv88e6xxx_port_set_duplex, 3045 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3046 .port_set_speed = mv88e6341_port_set_speed, 3047 .port_tag_remap = mv88e6095_port_tag_remap, 3048 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3049 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3050 .port_set_ether_type = mv88e6351_port_set_ether_type, 3051 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3052 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3053 .port_pause_limit = mv88e6097_port_pause_limit, 3054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3056 .port_link_state = mv88e6352_port_link_state, 3057 .port_get_cmode = mv88e6352_port_get_cmode, 3058 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3059 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3060 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3061 .stats_get_strings = mv88e6320_stats_get_strings, 3062 .stats_get_stats = mv88e6390_stats_get_stats, 3063 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3064 .set_egress_port = mv88e6390_g1_set_egress_port, 3065 .watchdog_ops = &mv88e6390_watchdog_ops, 3066 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3067 .pot_clear = mv88e6xxx_g2_pot_clear, 3068 .reset = mv88e6352_g1_reset, 3069 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3070 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3071 .serdes_power = mv88e6341_serdes_power, 3072 .gpio_ops = &mv88e6352_gpio_ops, 3073 .phylink_validate = mv88e6390_phylink_validate, 3074 }; 3075 3076 static const struct mv88e6xxx_ops mv88e6161_ops = { 3077 /* MV88E6XXX_FAMILY_6165 */ 3078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3079 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3080 .irl_init_all = mv88e6352_g2_irl_init_all, 3081 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3082 .phy_read = mv88e6xxx_g2_smi_phy_read, 3083 .phy_write = mv88e6xxx_g2_smi_phy_write, 3084 .port_set_link = mv88e6xxx_port_set_link, 3085 .port_set_duplex = mv88e6xxx_port_set_duplex, 3086 .port_set_speed = mv88e6185_port_set_speed, 3087 .port_tag_remap = mv88e6095_port_tag_remap, 3088 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3089 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3090 .port_set_ether_type = mv88e6351_port_set_ether_type, 3091 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3092 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3093 .port_pause_limit = mv88e6097_port_pause_limit, 3094 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3095 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3096 .port_link_state = mv88e6352_port_link_state, 3097 .port_get_cmode = mv88e6185_port_get_cmode, 3098 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3099 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3100 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3101 .stats_get_strings = mv88e6095_stats_get_strings, 3102 .stats_get_stats = mv88e6095_stats_get_stats, 3103 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3104 .set_egress_port = mv88e6095_g1_set_egress_port, 3105 .watchdog_ops = &mv88e6097_watchdog_ops, 3106 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3107 .pot_clear = mv88e6xxx_g2_pot_clear, 3108 .reset = mv88e6352_g1_reset, 3109 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3110 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3111 .avb_ops = &mv88e6165_avb_ops, 3112 .ptp_ops = &mv88e6165_ptp_ops, 3113 .phylink_validate = mv88e6185_phylink_validate, 3114 }; 3115 3116 static const struct mv88e6xxx_ops mv88e6165_ops = { 3117 /* MV88E6XXX_FAMILY_6165 */ 3118 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3119 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3120 .irl_init_all = mv88e6352_g2_irl_init_all, 3121 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3122 .phy_read = mv88e6165_phy_read, 3123 .phy_write = mv88e6165_phy_write, 3124 .port_set_link = mv88e6xxx_port_set_link, 3125 .port_set_duplex = mv88e6xxx_port_set_duplex, 3126 .port_set_speed = mv88e6185_port_set_speed, 3127 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3128 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3129 .port_link_state = mv88e6352_port_link_state, 3130 .port_get_cmode = mv88e6185_port_get_cmode, 3131 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3132 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3133 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3134 .stats_get_strings = mv88e6095_stats_get_strings, 3135 .stats_get_stats = mv88e6095_stats_get_stats, 3136 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3137 .set_egress_port = mv88e6095_g1_set_egress_port, 3138 .watchdog_ops = &mv88e6097_watchdog_ops, 3139 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3140 .pot_clear = mv88e6xxx_g2_pot_clear, 3141 .reset = mv88e6352_g1_reset, 3142 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3143 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3144 .avb_ops = &mv88e6165_avb_ops, 3145 .ptp_ops = &mv88e6165_ptp_ops, 3146 .phylink_validate = mv88e6185_phylink_validate, 3147 }; 3148 3149 static const struct mv88e6xxx_ops mv88e6171_ops = { 3150 /* MV88E6XXX_FAMILY_6351 */ 3151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3153 .irl_init_all = mv88e6352_g2_irl_init_all, 3154 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3155 .phy_read = mv88e6xxx_g2_smi_phy_read, 3156 .phy_write = mv88e6xxx_g2_smi_phy_write, 3157 .port_set_link = mv88e6xxx_port_set_link, 3158 .port_set_duplex = mv88e6xxx_port_set_duplex, 3159 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3160 .port_set_speed = mv88e6185_port_set_speed, 3161 .port_tag_remap = mv88e6095_port_tag_remap, 3162 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3163 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3164 .port_set_ether_type = mv88e6351_port_set_ether_type, 3165 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3166 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3167 .port_pause_limit = mv88e6097_port_pause_limit, 3168 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3169 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3170 .port_link_state = mv88e6352_port_link_state, 3171 .port_get_cmode = mv88e6352_port_get_cmode, 3172 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3173 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3174 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3175 .stats_get_strings = mv88e6095_stats_get_strings, 3176 .stats_get_stats = mv88e6095_stats_get_stats, 3177 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3178 .set_egress_port = mv88e6095_g1_set_egress_port, 3179 .watchdog_ops = &mv88e6097_watchdog_ops, 3180 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3181 .pot_clear = mv88e6xxx_g2_pot_clear, 3182 .reset = mv88e6352_g1_reset, 3183 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3184 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3185 .phylink_validate = mv88e6185_phylink_validate, 3186 }; 3187 3188 static const struct mv88e6xxx_ops mv88e6172_ops = { 3189 /* MV88E6XXX_FAMILY_6352 */ 3190 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3191 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3192 .irl_init_all = mv88e6352_g2_irl_init_all, 3193 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3194 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3195 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3196 .phy_read = mv88e6xxx_g2_smi_phy_read, 3197 .phy_write = mv88e6xxx_g2_smi_phy_write, 3198 .port_set_link = mv88e6xxx_port_set_link, 3199 .port_set_duplex = mv88e6xxx_port_set_duplex, 3200 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3201 .port_set_speed = mv88e6352_port_set_speed, 3202 .port_tag_remap = mv88e6095_port_tag_remap, 3203 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3204 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3205 .port_set_ether_type = mv88e6351_port_set_ether_type, 3206 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3207 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3208 .port_pause_limit = mv88e6097_port_pause_limit, 3209 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3210 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3211 .port_link_state = mv88e6352_port_link_state, 3212 .port_get_cmode = mv88e6352_port_get_cmode, 3213 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3214 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3215 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3216 .stats_get_strings = mv88e6095_stats_get_strings, 3217 .stats_get_stats = mv88e6095_stats_get_stats, 3218 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3219 .set_egress_port = mv88e6095_g1_set_egress_port, 3220 .watchdog_ops = &mv88e6097_watchdog_ops, 3221 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3222 .pot_clear = mv88e6xxx_g2_pot_clear, 3223 .reset = mv88e6352_g1_reset, 3224 .rmu_disable = mv88e6352_g1_rmu_disable, 3225 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3226 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3227 .serdes_power = mv88e6352_serdes_power, 3228 .gpio_ops = &mv88e6352_gpio_ops, 3229 .phylink_validate = mv88e6352_phylink_validate, 3230 }; 3231 3232 static const struct mv88e6xxx_ops mv88e6175_ops = { 3233 /* MV88E6XXX_FAMILY_6351 */ 3234 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3235 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3236 .irl_init_all = mv88e6352_g2_irl_init_all, 3237 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3238 .phy_read = mv88e6xxx_g2_smi_phy_read, 3239 .phy_write = mv88e6xxx_g2_smi_phy_write, 3240 .port_set_link = mv88e6xxx_port_set_link, 3241 .port_set_duplex = mv88e6xxx_port_set_duplex, 3242 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3243 .port_set_speed = mv88e6185_port_set_speed, 3244 .port_tag_remap = mv88e6095_port_tag_remap, 3245 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3246 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3247 .port_set_ether_type = mv88e6351_port_set_ether_type, 3248 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3249 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3250 .port_pause_limit = mv88e6097_port_pause_limit, 3251 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3252 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3253 .port_link_state = mv88e6352_port_link_state, 3254 .port_get_cmode = mv88e6352_port_get_cmode, 3255 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3256 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3257 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3258 .stats_get_strings = mv88e6095_stats_get_strings, 3259 .stats_get_stats = mv88e6095_stats_get_stats, 3260 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3261 .set_egress_port = mv88e6095_g1_set_egress_port, 3262 .watchdog_ops = &mv88e6097_watchdog_ops, 3263 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3264 .pot_clear = mv88e6xxx_g2_pot_clear, 3265 .reset = mv88e6352_g1_reset, 3266 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3267 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3268 .phylink_validate = mv88e6185_phylink_validate, 3269 }; 3270 3271 static const struct mv88e6xxx_ops mv88e6176_ops = { 3272 /* MV88E6XXX_FAMILY_6352 */ 3273 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3274 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3275 .irl_init_all = mv88e6352_g2_irl_init_all, 3276 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3277 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3279 .phy_read = mv88e6xxx_g2_smi_phy_read, 3280 .phy_write = mv88e6xxx_g2_smi_phy_write, 3281 .port_set_link = mv88e6xxx_port_set_link, 3282 .port_set_duplex = mv88e6xxx_port_set_duplex, 3283 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3284 .port_set_speed = mv88e6352_port_set_speed, 3285 .port_tag_remap = mv88e6095_port_tag_remap, 3286 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3287 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3288 .port_set_ether_type = mv88e6351_port_set_ether_type, 3289 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3290 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3291 .port_pause_limit = mv88e6097_port_pause_limit, 3292 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3293 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3294 .port_link_state = mv88e6352_port_link_state, 3295 .port_get_cmode = mv88e6352_port_get_cmode, 3296 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3297 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3298 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3299 .stats_get_strings = mv88e6095_stats_get_strings, 3300 .stats_get_stats = mv88e6095_stats_get_stats, 3301 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3302 .set_egress_port = mv88e6095_g1_set_egress_port, 3303 .watchdog_ops = &mv88e6097_watchdog_ops, 3304 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3305 .pot_clear = mv88e6xxx_g2_pot_clear, 3306 .reset = mv88e6352_g1_reset, 3307 .rmu_disable = mv88e6352_g1_rmu_disable, 3308 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3309 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3310 .serdes_power = mv88e6352_serdes_power, 3311 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3312 .serdes_irq_free = mv88e6352_serdes_irq_free, 3313 .gpio_ops = &mv88e6352_gpio_ops, 3314 .phylink_validate = mv88e6352_phylink_validate, 3315 }; 3316 3317 static const struct mv88e6xxx_ops mv88e6185_ops = { 3318 /* MV88E6XXX_FAMILY_6185 */ 3319 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3320 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3321 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3322 .phy_read = mv88e6185_phy_ppu_read, 3323 .phy_write = mv88e6185_phy_ppu_write, 3324 .port_set_link = mv88e6xxx_port_set_link, 3325 .port_set_duplex = mv88e6xxx_port_set_duplex, 3326 .port_set_speed = mv88e6185_port_set_speed, 3327 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3328 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3329 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3330 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3331 .port_set_pause = mv88e6185_port_set_pause, 3332 .port_link_state = mv88e6185_port_link_state, 3333 .port_get_cmode = mv88e6185_port_get_cmode, 3334 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3335 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3336 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3337 .stats_get_strings = mv88e6095_stats_get_strings, 3338 .stats_get_stats = mv88e6095_stats_get_stats, 3339 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3340 .set_egress_port = mv88e6095_g1_set_egress_port, 3341 .watchdog_ops = &mv88e6097_watchdog_ops, 3342 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3343 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3344 .ppu_enable = mv88e6185_g1_ppu_enable, 3345 .ppu_disable = mv88e6185_g1_ppu_disable, 3346 .reset = mv88e6185_g1_reset, 3347 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3348 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3349 .phylink_validate = mv88e6185_phylink_validate, 3350 }; 3351 3352 static const struct mv88e6xxx_ops mv88e6190_ops = { 3353 /* MV88E6XXX_FAMILY_6390 */ 3354 .setup_errata = mv88e6390_setup_errata, 3355 .irl_init_all = mv88e6390_g2_irl_init_all, 3356 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3357 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3358 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3359 .phy_read = mv88e6xxx_g2_smi_phy_read, 3360 .phy_write = mv88e6xxx_g2_smi_phy_write, 3361 .port_set_link = mv88e6xxx_port_set_link, 3362 .port_set_duplex = mv88e6xxx_port_set_duplex, 3363 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3364 .port_set_speed = mv88e6390_port_set_speed, 3365 .port_tag_remap = mv88e6390_port_tag_remap, 3366 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3367 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3368 .port_set_ether_type = mv88e6351_port_set_ether_type, 3369 .port_pause_limit = mv88e6390_port_pause_limit, 3370 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3371 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3372 .port_link_state = mv88e6352_port_link_state, 3373 .port_get_cmode = mv88e6352_port_get_cmode, 3374 .port_set_cmode = mv88e6390_port_set_cmode, 3375 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3376 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3377 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3378 .stats_get_strings = mv88e6320_stats_get_strings, 3379 .stats_get_stats = mv88e6390_stats_get_stats, 3380 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3381 .set_egress_port = mv88e6390_g1_set_egress_port, 3382 .watchdog_ops = &mv88e6390_watchdog_ops, 3383 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3384 .pot_clear = mv88e6xxx_g2_pot_clear, 3385 .reset = mv88e6352_g1_reset, 3386 .rmu_disable = mv88e6390_g1_rmu_disable, 3387 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3388 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3389 .serdes_power = mv88e6390_serdes_power, 3390 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3391 .serdes_irq_free = mv88e6390_serdes_irq_free, 3392 .gpio_ops = &mv88e6352_gpio_ops, 3393 .phylink_validate = mv88e6390_phylink_validate, 3394 }; 3395 3396 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3397 /* MV88E6XXX_FAMILY_6390 */ 3398 .setup_errata = mv88e6390_setup_errata, 3399 .irl_init_all = mv88e6390_g2_irl_init_all, 3400 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3401 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3402 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3403 .phy_read = mv88e6xxx_g2_smi_phy_read, 3404 .phy_write = mv88e6xxx_g2_smi_phy_write, 3405 .port_set_link = mv88e6xxx_port_set_link, 3406 .port_set_duplex = mv88e6xxx_port_set_duplex, 3407 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3408 .port_set_speed = mv88e6390x_port_set_speed, 3409 .port_tag_remap = mv88e6390_port_tag_remap, 3410 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3411 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3412 .port_set_ether_type = mv88e6351_port_set_ether_type, 3413 .port_pause_limit = mv88e6390_port_pause_limit, 3414 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3415 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3416 .port_link_state = mv88e6352_port_link_state, 3417 .port_get_cmode = mv88e6352_port_get_cmode, 3418 .port_set_cmode = mv88e6390x_port_set_cmode, 3419 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3420 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3421 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3422 .stats_get_strings = mv88e6320_stats_get_strings, 3423 .stats_get_stats = mv88e6390_stats_get_stats, 3424 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3425 .set_egress_port = mv88e6390_g1_set_egress_port, 3426 .watchdog_ops = &mv88e6390_watchdog_ops, 3427 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3428 .pot_clear = mv88e6xxx_g2_pot_clear, 3429 .reset = mv88e6352_g1_reset, 3430 .rmu_disable = mv88e6390_g1_rmu_disable, 3431 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3432 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3433 .serdes_power = mv88e6390x_serdes_power, 3434 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3435 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3436 .gpio_ops = &mv88e6352_gpio_ops, 3437 .phylink_validate = mv88e6390x_phylink_validate, 3438 }; 3439 3440 static const struct mv88e6xxx_ops mv88e6191_ops = { 3441 /* MV88E6XXX_FAMILY_6390 */ 3442 .setup_errata = mv88e6390_setup_errata, 3443 .irl_init_all = mv88e6390_g2_irl_init_all, 3444 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3445 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3447 .phy_read = mv88e6xxx_g2_smi_phy_read, 3448 .phy_write = mv88e6xxx_g2_smi_phy_write, 3449 .port_set_link = mv88e6xxx_port_set_link, 3450 .port_set_duplex = mv88e6xxx_port_set_duplex, 3451 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3452 .port_set_speed = mv88e6390_port_set_speed, 3453 .port_tag_remap = mv88e6390_port_tag_remap, 3454 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3455 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3456 .port_set_ether_type = mv88e6351_port_set_ether_type, 3457 .port_pause_limit = mv88e6390_port_pause_limit, 3458 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3459 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3460 .port_link_state = mv88e6352_port_link_state, 3461 .port_get_cmode = mv88e6352_port_get_cmode, 3462 .port_set_cmode = mv88e6390_port_set_cmode, 3463 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3464 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3465 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3466 .stats_get_strings = mv88e6320_stats_get_strings, 3467 .stats_get_stats = mv88e6390_stats_get_stats, 3468 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3469 .set_egress_port = mv88e6390_g1_set_egress_port, 3470 .watchdog_ops = &mv88e6390_watchdog_ops, 3471 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3472 .pot_clear = mv88e6xxx_g2_pot_clear, 3473 .reset = mv88e6352_g1_reset, 3474 .rmu_disable = mv88e6390_g1_rmu_disable, 3475 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3476 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3477 .serdes_power = mv88e6390_serdes_power, 3478 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3479 .serdes_irq_free = mv88e6390_serdes_irq_free, 3480 .avb_ops = &mv88e6390_avb_ops, 3481 .ptp_ops = &mv88e6352_ptp_ops, 3482 .phylink_validate = mv88e6390_phylink_validate, 3483 }; 3484 3485 static const struct mv88e6xxx_ops mv88e6240_ops = { 3486 /* MV88E6XXX_FAMILY_6352 */ 3487 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3488 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3489 .irl_init_all = mv88e6352_g2_irl_init_all, 3490 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3491 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3492 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3493 .phy_read = mv88e6xxx_g2_smi_phy_read, 3494 .phy_write = mv88e6xxx_g2_smi_phy_write, 3495 .port_set_link = mv88e6xxx_port_set_link, 3496 .port_set_duplex = mv88e6xxx_port_set_duplex, 3497 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3498 .port_set_speed = mv88e6352_port_set_speed, 3499 .port_tag_remap = mv88e6095_port_tag_remap, 3500 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3501 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3502 .port_set_ether_type = mv88e6351_port_set_ether_type, 3503 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3504 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3505 .port_pause_limit = mv88e6097_port_pause_limit, 3506 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3507 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3508 .port_link_state = mv88e6352_port_link_state, 3509 .port_get_cmode = mv88e6352_port_get_cmode, 3510 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3511 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3512 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3513 .stats_get_strings = mv88e6095_stats_get_strings, 3514 .stats_get_stats = mv88e6095_stats_get_stats, 3515 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3516 .set_egress_port = mv88e6095_g1_set_egress_port, 3517 .watchdog_ops = &mv88e6097_watchdog_ops, 3518 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3519 .pot_clear = mv88e6xxx_g2_pot_clear, 3520 .reset = mv88e6352_g1_reset, 3521 .rmu_disable = mv88e6352_g1_rmu_disable, 3522 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3523 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3524 .serdes_power = mv88e6352_serdes_power, 3525 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3526 .serdes_irq_free = mv88e6352_serdes_irq_free, 3527 .gpio_ops = &mv88e6352_gpio_ops, 3528 .avb_ops = &mv88e6352_avb_ops, 3529 .ptp_ops = &mv88e6352_ptp_ops, 3530 .phylink_validate = mv88e6352_phylink_validate, 3531 }; 3532 3533 static const struct mv88e6xxx_ops mv88e6290_ops = { 3534 /* MV88E6XXX_FAMILY_6390 */ 3535 .setup_errata = mv88e6390_setup_errata, 3536 .irl_init_all = mv88e6390_g2_irl_init_all, 3537 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3538 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3540 .phy_read = mv88e6xxx_g2_smi_phy_read, 3541 .phy_write = mv88e6xxx_g2_smi_phy_write, 3542 .port_set_link = mv88e6xxx_port_set_link, 3543 .port_set_duplex = mv88e6xxx_port_set_duplex, 3544 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3545 .port_set_speed = mv88e6390_port_set_speed, 3546 .port_tag_remap = mv88e6390_port_tag_remap, 3547 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3548 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3549 .port_set_ether_type = mv88e6351_port_set_ether_type, 3550 .port_pause_limit = mv88e6390_port_pause_limit, 3551 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3552 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3553 .port_link_state = mv88e6352_port_link_state, 3554 .port_get_cmode = mv88e6352_port_get_cmode, 3555 .port_set_cmode = mv88e6390_port_set_cmode, 3556 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3557 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3558 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3559 .stats_get_strings = mv88e6320_stats_get_strings, 3560 .stats_get_stats = mv88e6390_stats_get_stats, 3561 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3562 .set_egress_port = mv88e6390_g1_set_egress_port, 3563 .watchdog_ops = &mv88e6390_watchdog_ops, 3564 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3565 .pot_clear = mv88e6xxx_g2_pot_clear, 3566 .reset = mv88e6352_g1_reset, 3567 .rmu_disable = mv88e6390_g1_rmu_disable, 3568 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3569 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3570 .serdes_power = mv88e6390_serdes_power, 3571 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3572 .serdes_irq_free = mv88e6390_serdes_irq_free, 3573 .gpio_ops = &mv88e6352_gpio_ops, 3574 .avb_ops = &mv88e6390_avb_ops, 3575 .ptp_ops = &mv88e6352_ptp_ops, 3576 .phylink_validate = mv88e6390_phylink_validate, 3577 }; 3578 3579 static const struct mv88e6xxx_ops mv88e6320_ops = { 3580 /* MV88E6XXX_FAMILY_6320 */ 3581 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3582 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3583 .irl_init_all = mv88e6352_g2_irl_init_all, 3584 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3585 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3587 .phy_read = mv88e6xxx_g2_smi_phy_read, 3588 .phy_write = mv88e6xxx_g2_smi_phy_write, 3589 .port_set_link = mv88e6xxx_port_set_link, 3590 .port_set_duplex = mv88e6xxx_port_set_duplex, 3591 .port_set_speed = mv88e6185_port_set_speed, 3592 .port_tag_remap = mv88e6095_port_tag_remap, 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3594 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3595 .port_set_ether_type = mv88e6351_port_set_ether_type, 3596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3598 .port_pause_limit = mv88e6097_port_pause_limit, 3599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3601 .port_link_state = mv88e6352_port_link_state, 3602 .port_get_cmode = mv88e6352_port_get_cmode, 3603 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3605 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3606 .stats_get_strings = mv88e6320_stats_get_strings, 3607 .stats_get_stats = mv88e6320_stats_get_stats, 3608 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3609 .set_egress_port = mv88e6095_g1_set_egress_port, 3610 .watchdog_ops = &mv88e6390_watchdog_ops, 3611 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3612 .pot_clear = mv88e6xxx_g2_pot_clear, 3613 .reset = mv88e6352_g1_reset, 3614 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3615 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3616 .gpio_ops = &mv88e6352_gpio_ops, 3617 .avb_ops = &mv88e6352_avb_ops, 3618 .ptp_ops = &mv88e6352_ptp_ops, 3619 .phylink_validate = mv88e6185_phylink_validate, 3620 }; 3621 3622 static const struct mv88e6xxx_ops mv88e6321_ops = { 3623 /* MV88E6XXX_FAMILY_6320 */ 3624 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3625 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3626 .irl_init_all = mv88e6352_g2_irl_init_all, 3627 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3628 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3629 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3630 .phy_read = mv88e6xxx_g2_smi_phy_read, 3631 .phy_write = mv88e6xxx_g2_smi_phy_write, 3632 .port_set_link = mv88e6xxx_port_set_link, 3633 .port_set_duplex = mv88e6xxx_port_set_duplex, 3634 .port_set_speed = mv88e6185_port_set_speed, 3635 .port_tag_remap = mv88e6095_port_tag_remap, 3636 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3637 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3638 .port_set_ether_type = mv88e6351_port_set_ether_type, 3639 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3640 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3641 .port_pause_limit = mv88e6097_port_pause_limit, 3642 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3643 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3644 .port_link_state = mv88e6352_port_link_state, 3645 .port_get_cmode = mv88e6352_port_get_cmode, 3646 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3647 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3648 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3649 .stats_get_strings = mv88e6320_stats_get_strings, 3650 .stats_get_stats = mv88e6320_stats_get_stats, 3651 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3652 .set_egress_port = mv88e6095_g1_set_egress_port, 3653 .watchdog_ops = &mv88e6390_watchdog_ops, 3654 .reset = mv88e6352_g1_reset, 3655 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3656 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3657 .gpio_ops = &mv88e6352_gpio_ops, 3658 .avb_ops = &mv88e6352_avb_ops, 3659 .ptp_ops = &mv88e6352_ptp_ops, 3660 .phylink_validate = mv88e6185_phylink_validate, 3661 }; 3662 3663 static const struct mv88e6xxx_ops mv88e6341_ops = { 3664 /* MV88E6XXX_FAMILY_6341 */ 3665 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3666 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3667 .irl_init_all = mv88e6352_g2_irl_init_all, 3668 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3669 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3670 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3671 .phy_read = mv88e6xxx_g2_smi_phy_read, 3672 .phy_write = mv88e6xxx_g2_smi_phy_write, 3673 .port_set_link = mv88e6xxx_port_set_link, 3674 .port_set_duplex = mv88e6xxx_port_set_duplex, 3675 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3676 .port_set_speed = mv88e6341_port_set_speed, 3677 .port_tag_remap = mv88e6095_port_tag_remap, 3678 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3679 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3680 .port_set_ether_type = mv88e6351_port_set_ether_type, 3681 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3682 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3683 .port_pause_limit = mv88e6097_port_pause_limit, 3684 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3685 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3686 .port_link_state = mv88e6352_port_link_state, 3687 .port_get_cmode = mv88e6352_port_get_cmode, 3688 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3689 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3690 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3691 .stats_get_strings = mv88e6320_stats_get_strings, 3692 .stats_get_stats = mv88e6390_stats_get_stats, 3693 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3694 .set_egress_port = mv88e6390_g1_set_egress_port, 3695 .watchdog_ops = &mv88e6390_watchdog_ops, 3696 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3697 .pot_clear = mv88e6xxx_g2_pot_clear, 3698 .reset = mv88e6352_g1_reset, 3699 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3700 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3701 .serdes_power = mv88e6341_serdes_power, 3702 .gpio_ops = &mv88e6352_gpio_ops, 3703 .avb_ops = &mv88e6390_avb_ops, 3704 .ptp_ops = &mv88e6352_ptp_ops, 3705 .phylink_validate = mv88e6390_phylink_validate, 3706 }; 3707 3708 static const struct mv88e6xxx_ops mv88e6350_ops = { 3709 /* MV88E6XXX_FAMILY_6351 */ 3710 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3711 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3712 .irl_init_all = mv88e6352_g2_irl_init_all, 3713 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3714 .phy_read = mv88e6xxx_g2_smi_phy_read, 3715 .phy_write = mv88e6xxx_g2_smi_phy_write, 3716 .port_set_link = mv88e6xxx_port_set_link, 3717 .port_set_duplex = mv88e6xxx_port_set_duplex, 3718 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3719 .port_set_speed = mv88e6185_port_set_speed, 3720 .port_tag_remap = mv88e6095_port_tag_remap, 3721 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3722 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3723 .port_set_ether_type = mv88e6351_port_set_ether_type, 3724 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3725 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3726 .port_pause_limit = mv88e6097_port_pause_limit, 3727 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3728 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3729 .port_link_state = mv88e6352_port_link_state, 3730 .port_get_cmode = mv88e6352_port_get_cmode, 3731 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3732 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3733 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3734 .stats_get_strings = mv88e6095_stats_get_strings, 3735 .stats_get_stats = mv88e6095_stats_get_stats, 3736 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3737 .set_egress_port = mv88e6095_g1_set_egress_port, 3738 .watchdog_ops = &mv88e6097_watchdog_ops, 3739 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3740 .pot_clear = mv88e6xxx_g2_pot_clear, 3741 .reset = mv88e6352_g1_reset, 3742 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3743 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3744 .phylink_validate = mv88e6185_phylink_validate, 3745 }; 3746 3747 static const struct mv88e6xxx_ops mv88e6351_ops = { 3748 /* MV88E6XXX_FAMILY_6351 */ 3749 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3750 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3751 .irl_init_all = mv88e6352_g2_irl_init_all, 3752 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3753 .phy_read = mv88e6xxx_g2_smi_phy_read, 3754 .phy_write = mv88e6xxx_g2_smi_phy_write, 3755 .port_set_link = mv88e6xxx_port_set_link, 3756 .port_set_duplex = mv88e6xxx_port_set_duplex, 3757 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3758 .port_set_speed = mv88e6185_port_set_speed, 3759 .port_tag_remap = mv88e6095_port_tag_remap, 3760 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3761 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3762 .port_set_ether_type = mv88e6351_port_set_ether_type, 3763 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3764 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3765 .port_pause_limit = mv88e6097_port_pause_limit, 3766 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3767 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3768 .port_link_state = mv88e6352_port_link_state, 3769 .port_get_cmode = mv88e6352_port_get_cmode, 3770 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3771 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3772 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3773 .stats_get_strings = mv88e6095_stats_get_strings, 3774 .stats_get_stats = mv88e6095_stats_get_stats, 3775 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3776 .set_egress_port = mv88e6095_g1_set_egress_port, 3777 .watchdog_ops = &mv88e6097_watchdog_ops, 3778 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3779 .pot_clear = mv88e6xxx_g2_pot_clear, 3780 .reset = mv88e6352_g1_reset, 3781 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3782 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3783 .avb_ops = &mv88e6352_avb_ops, 3784 .ptp_ops = &mv88e6352_ptp_ops, 3785 .phylink_validate = mv88e6185_phylink_validate, 3786 }; 3787 3788 static const struct mv88e6xxx_ops mv88e6352_ops = { 3789 /* MV88E6XXX_FAMILY_6352 */ 3790 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3791 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3792 .irl_init_all = mv88e6352_g2_irl_init_all, 3793 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3794 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3795 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3796 .phy_read = mv88e6xxx_g2_smi_phy_read, 3797 .phy_write = mv88e6xxx_g2_smi_phy_write, 3798 .port_set_link = mv88e6xxx_port_set_link, 3799 .port_set_duplex = mv88e6xxx_port_set_duplex, 3800 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3801 .port_set_speed = mv88e6352_port_set_speed, 3802 .port_tag_remap = mv88e6095_port_tag_remap, 3803 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3804 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3805 .port_set_ether_type = mv88e6351_port_set_ether_type, 3806 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3807 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3808 .port_pause_limit = mv88e6097_port_pause_limit, 3809 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3810 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3811 .port_link_state = mv88e6352_port_link_state, 3812 .port_get_cmode = mv88e6352_port_get_cmode, 3813 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3814 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3815 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3816 .stats_get_strings = mv88e6095_stats_get_strings, 3817 .stats_get_stats = mv88e6095_stats_get_stats, 3818 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3819 .set_egress_port = mv88e6095_g1_set_egress_port, 3820 .watchdog_ops = &mv88e6097_watchdog_ops, 3821 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3822 .pot_clear = mv88e6xxx_g2_pot_clear, 3823 .reset = mv88e6352_g1_reset, 3824 .rmu_disable = mv88e6352_g1_rmu_disable, 3825 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3826 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3827 .serdes_power = mv88e6352_serdes_power, 3828 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3829 .serdes_irq_free = mv88e6352_serdes_irq_free, 3830 .gpio_ops = &mv88e6352_gpio_ops, 3831 .avb_ops = &mv88e6352_avb_ops, 3832 .ptp_ops = &mv88e6352_ptp_ops, 3833 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3834 .serdes_get_strings = mv88e6352_serdes_get_strings, 3835 .serdes_get_stats = mv88e6352_serdes_get_stats, 3836 .phylink_validate = mv88e6352_phylink_validate, 3837 }; 3838 3839 static const struct mv88e6xxx_ops mv88e6390_ops = { 3840 /* MV88E6XXX_FAMILY_6390 */ 3841 .setup_errata = mv88e6390_setup_errata, 3842 .irl_init_all = mv88e6390_g2_irl_init_all, 3843 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3844 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3845 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3846 .phy_read = mv88e6xxx_g2_smi_phy_read, 3847 .phy_write = mv88e6xxx_g2_smi_phy_write, 3848 .port_set_link = mv88e6xxx_port_set_link, 3849 .port_set_duplex = mv88e6xxx_port_set_duplex, 3850 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3851 .port_set_speed = mv88e6390_port_set_speed, 3852 .port_tag_remap = mv88e6390_port_tag_remap, 3853 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3854 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3855 .port_set_ether_type = mv88e6351_port_set_ether_type, 3856 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3857 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3858 .port_pause_limit = mv88e6390_port_pause_limit, 3859 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3860 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3861 .port_link_state = mv88e6352_port_link_state, 3862 .port_get_cmode = mv88e6352_port_get_cmode, 3863 .port_set_cmode = mv88e6390_port_set_cmode, 3864 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3865 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3866 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3867 .stats_get_strings = mv88e6320_stats_get_strings, 3868 .stats_get_stats = mv88e6390_stats_get_stats, 3869 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3870 .set_egress_port = mv88e6390_g1_set_egress_port, 3871 .watchdog_ops = &mv88e6390_watchdog_ops, 3872 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3873 .pot_clear = mv88e6xxx_g2_pot_clear, 3874 .reset = mv88e6352_g1_reset, 3875 .rmu_disable = mv88e6390_g1_rmu_disable, 3876 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3877 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3878 .serdes_power = mv88e6390_serdes_power, 3879 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3880 .serdes_irq_free = mv88e6390_serdes_irq_free, 3881 .gpio_ops = &mv88e6352_gpio_ops, 3882 .avb_ops = &mv88e6390_avb_ops, 3883 .ptp_ops = &mv88e6352_ptp_ops, 3884 .phylink_validate = mv88e6390_phylink_validate, 3885 }; 3886 3887 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3888 /* MV88E6XXX_FAMILY_6390 */ 3889 .setup_errata = mv88e6390_setup_errata, 3890 .irl_init_all = mv88e6390_g2_irl_init_all, 3891 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3892 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3894 .phy_read = mv88e6xxx_g2_smi_phy_read, 3895 .phy_write = mv88e6xxx_g2_smi_phy_write, 3896 .port_set_link = mv88e6xxx_port_set_link, 3897 .port_set_duplex = mv88e6xxx_port_set_duplex, 3898 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3899 .port_set_speed = mv88e6390x_port_set_speed, 3900 .port_tag_remap = mv88e6390_port_tag_remap, 3901 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3902 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3903 .port_set_ether_type = mv88e6351_port_set_ether_type, 3904 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3905 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3906 .port_pause_limit = mv88e6390_port_pause_limit, 3907 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3908 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3909 .port_link_state = mv88e6352_port_link_state, 3910 .port_get_cmode = mv88e6352_port_get_cmode, 3911 .port_set_cmode = mv88e6390x_port_set_cmode, 3912 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3913 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3914 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3915 .stats_get_strings = mv88e6320_stats_get_strings, 3916 .stats_get_stats = mv88e6390_stats_get_stats, 3917 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3918 .set_egress_port = mv88e6390_g1_set_egress_port, 3919 .watchdog_ops = &mv88e6390_watchdog_ops, 3920 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3921 .pot_clear = mv88e6xxx_g2_pot_clear, 3922 .reset = mv88e6352_g1_reset, 3923 .rmu_disable = mv88e6390_g1_rmu_disable, 3924 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3925 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3926 .serdes_power = mv88e6390x_serdes_power, 3927 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3928 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3929 .gpio_ops = &mv88e6352_gpio_ops, 3930 .avb_ops = &mv88e6390_avb_ops, 3931 .ptp_ops = &mv88e6352_ptp_ops, 3932 .phylink_validate = mv88e6390x_phylink_validate, 3933 }; 3934 3935 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3936 [MV88E6085] = { 3937 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3938 .family = MV88E6XXX_FAMILY_6097, 3939 .name = "Marvell 88E6085", 3940 .num_databases = 4096, 3941 .num_ports = 10, 3942 .num_internal_phys = 5, 3943 .max_vid = 4095, 3944 .port_base_addr = 0x10, 3945 .phy_base_addr = 0x0, 3946 .global1_addr = 0x1b, 3947 .global2_addr = 0x1c, 3948 .age_time_coeff = 15000, 3949 .g1_irqs = 8, 3950 .g2_irqs = 10, 3951 .atu_move_port_mask = 0xf, 3952 .pvt = true, 3953 .multi_chip = true, 3954 .tag_protocol = DSA_TAG_PROTO_DSA, 3955 .ops = &mv88e6085_ops, 3956 }, 3957 3958 [MV88E6095] = { 3959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3960 .family = MV88E6XXX_FAMILY_6095, 3961 .name = "Marvell 88E6095/88E6095F", 3962 .num_databases = 256, 3963 .num_ports = 11, 3964 .num_internal_phys = 0, 3965 .max_vid = 4095, 3966 .port_base_addr = 0x10, 3967 .phy_base_addr = 0x0, 3968 .global1_addr = 0x1b, 3969 .global2_addr = 0x1c, 3970 .age_time_coeff = 15000, 3971 .g1_irqs = 8, 3972 .atu_move_port_mask = 0xf, 3973 .multi_chip = true, 3974 .tag_protocol = DSA_TAG_PROTO_DSA, 3975 .ops = &mv88e6095_ops, 3976 }, 3977 3978 [MV88E6097] = { 3979 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3980 .family = MV88E6XXX_FAMILY_6097, 3981 .name = "Marvell 88E6097/88E6097F", 3982 .num_databases = 4096, 3983 .num_ports = 11, 3984 .num_internal_phys = 8, 3985 .max_vid = 4095, 3986 .port_base_addr = 0x10, 3987 .phy_base_addr = 0x0, 3988 .global1_addr = 0x1b, 3989 .global2_addr = 0x1c, 3990 .age_time_coeff = 15000, 3991 .g1_irqs = 8, 3992 .g2_irqs = 10, 3993 .atu_move_port_mask = 0xf, 3994 .pvt = true, 3995 .multi_chip = true, 3996 .tag_protocol = DSA_TAG_PROTO_EDSA, 3997 .ops = &mv88e6097_ops, 3998 }, 3999 4000 [MV88E6123] = { 4001 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4002 .family = MV88E6XXX_FAMILY_6165, 4003 .name = "Marvell 88E6123", 4004 .num_databases = 4096, 4005 .num_ports = 3, 4006 .num_internal_phys = 5, 4007 .max_vid = 4095, 4008 .port_base_addr = 0x10, 4009 .phy_base_addr = 0x0, 4010 .global1_addr = 0x1b, 4011 .global2_addr = 0x1c, 4012 .age_time_coeff = 15000, 4013 .g1_irqs = 9, 4014 .g2_irqs = 10, 4015 .atu_move_port_mask = 0xf, 4016 .pvt = true, 4017 .multi_chip = true, 4018 .tag_protocol = DSA_TAG_PROTO_EDSA, 4019 .ops = &mv88e6123_ops, 4020 }, 4021 4022 [MV88E6131] = { 4023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4024 .family = MV88E6XXX_FAMILY_6185, 4025 .name = "Marvell 88E6131", 4026 .num_databases = 256, 4027 .num_ports = 8, 4028 .num_internal_phys = 0, 4029 .max_vid = 4095, 4030 .port_base_addr = 0x10, 4031 .phy_base_addr = 0x0, 4032 .global1_addr = 0x1b, 4033 .global2_addr = 0x1c, 4034 .age_time_coeff = 15000, 4035 .g1_irqs = 9, 4036 .atu_move_port_mask = 0xf, 4037 .multi_chip = true, 4038 .tag_protocol = DSA_TAG_PROTO_DSA, 4039 .ops = &mv88e6131_ops, 4040 }, 4041 4042 [MV88E6141] = { 4043 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4044 .family = MV88E6XXX_FAMILY_6341, 4045 .name = "Marvell 88E6141", 4046 .num_databases = 4096, 4047 .num_ports = 6, 4048 .num_internal_phys = 5, 4049 .num_gpio = 11, 4050 .max_vid = 4095, 4051 .port_base_addr = 0x10, 4052 .phy_base_addr = 0x10, 4053 .global1_addr = 0x1b, 4054 .global2_addr = 0x1c, 4055 .age_time_coeff = 3750, 4056 .atu_move_port_mask = 0x1f, 4057 .g1_irqs = 9, 4058 .g2_irqs = 10, 4059 .pvt = true, 4060 .multi_chip = true, 4061 .tag_protocol = DSA_TAG_PROTO_EDSA, 4062 .ops = &mv88e6141_ops, 4063 }, 4064 4065 [MV88E6161] = { 4066 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4067 .family = MV88E6XXX_FAMILY_6165, 4068 .name = "Marvell 88E6161", 4069 .num_databases = 4096, 4070 .num_ports = 6, 4071 .num_internal_phys = 5, 4072 .max_vid = 4095, 4073 .port_base_addr = 0x10, 4074 .phy_base_addr = 0x0, 4075 .global1_addr = 0x1b, 4076 .global2_addr = 0x1c, 4077 .age_time_coeff = 15000, 4078 .g1_irqs = 9, 4079 .g2_irqs = 10, 4080 .atu_move_port_mask = 0xf, 4081 .pvt = true, 4082 .multi_chip = true, 4083 .tag_protocol = DSA_TAG_PROTO_EDSA, 4084 .ptp_support = true, 4085 .ops = &mv88e6161_ops, 4086 }, 4087 4088 [MV88E6165] = { 4089 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4090 .family = MV88E6XXX_FAMILY_6165, 4091 .name = "Marvell 88E6165", 4092 .num_databases = 4096, 4093 .num_ports = 6, 4094 .num_internal_phys = 0, 4095 .max_vid = 4095, 4096 .port_base_addr = 0x10, 4097 .phy_base_addr = 0x0, 4098 .global1_addr = 0x1b, 4099 .global2_addr = 0x1c, 4100 .age_time_coeff = 15000, 4101 .g1_irqs = 9, 4102 .g2_irqs = 10, 4103 .atu_move_port_mask = 0xf, 4104 .pvt = true, 4105 .multi_chip = true, 4106 .tag_protocol = DSA_TAG_PROTO_DSA, 4107 .ptp_support = true, 4108 .ops = &mv88e6165_ops, 4109 }, 4110 4111 [MV88E6171] = { 4112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4113 .family = MV88E6XXX_FAMILY_6351, 4114 .name = "Marvell 88E6171", 4115 .num_databases = 4096, 4116 .num_ports = 7, 4117 .num_internal_phys = 5, 4118 .max_vid = 4095, 4119 .port_base_addr = 0x10, 4120 .phy_base_addr = 0x0, 4121 .global1_addr = 0x1b, 4122 .global2_addr = 0x1c, 4123 .age_time_coeff = 15000, 4124 .g1_irqs = 9, 4125 .g2_irqs = 10, 4126 .atu_move_port_mask = 0xf, 4127 .pvt = true, 4128 .multi_chip = true, 4129 .tag_protocol = DSA_TAG_PROTO_EDSA, 4130 .ops = &mv88e6171_ops, 4131 }, 4132 4133 [MV88E6172] = { 4134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4135 .family = MV88E6XXX_FAMILY_6352, 4136 .name = "Marvell 88E6172", 4137 .num_databases = 4096, 4138 .num_ports = 7, 4139 .num_internal_phys = 5, 4140 .num_gpio = 15, 4141 .max_vid = 4095, 4142 .port_base_addr = 0x10, 4143 .phy_base_addr = 0x0, 4144 .global1_addr = 0x1b, 4145 .global2_addr = 0x1c, 4146 .age_time_coeff = 15000, 4147 .g1_irqs = 9, 4148 .g2_irqs = 10, 4149 .atu_move_port_mask = 0xf, 4150 .pvt = true, 4151 .multi_chip = true, 4152 .tag_protocol = DSA_TAG_PROTO_EDSA, 4153 .ops = &mv88e6172_ops, 4154 }, 4155 4156 [MV88E6175] = { 4157 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4158 .family = MV88E6XXX_FAMILY_6351, 4159 .name = "Marvell 88E6175", 4160 .num_databases = 4096, 4161 .num_ports = 7, 4162 .num_internal_phys = 5, 4163 .max_vid = 4095, 4164 .port_base_addr = 0x10, 4165 .phy_base_addr = 0x0, 4166 .global1_addr = 0x1b, 4167 .global2_addr = 0x1c, 4168 .age_time_coeff = 15000, 4169 .g1_irqs = 9, 4170 .g2_irqs = 10, 4171 .atu_move_port_mask = 0xf, 4172 .pvt = true, 4173 .multi_chip = true, 4174 .tag_protocol = DSA_TAG_PROTO_EDSA, 4175 .ops = &mv88e6175_ops, 4176 }, 4177 4178 [MV88E6176] = { 4179 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4180 .family = MV88E6XXX_FAMILY_6352, 4181 .name = "Marvell 88E6176", 4182 .num_databases = 4096, 4183 .num_ports = 7, 4184 .num_internal_phys = 5, 4185 .num_gpio = 15, 4186 .max_vid = 4095, 4187 .port_base_addr = 0x10, 4188 .phy_base_addr = 0x0, 4189 .global1_addr = 0x1b, 4190 .global2_addr = 0x1c, 4191 .age_time_coeff = 15000, 4192 .g1_irqs = 9, 4193 .g2_irqs = 10, 4194 .atu_move_port_mask = 0xf, 4195 .pvt = true, 4196 .multi_chip = true, 4197 .tag_protocol = DSA_TAG_PROTO_EDSA, 4198 .ops = &mv88e6176_ops, 4199 }, 4200 4201 [MV88E6185] = { 4202 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4203 .family = MV88E6XXX_FAMILY_6185, 4204 .name = "Marvell 88E6185", 4205 .num_databases = 256, 4206 .num_ports = 10, 4207 .num_internal_phys = 0, 4208 .max_vid = 4095, 4209 .port_base_addr = 0x10, 4210 .phy_base_addr = 0x0, 4211 .global1_addr = 0x1b, 4212 .global2_addr = 0x1c, 4213 .age_time_coeff = 15000, 4214 .g1_irqs = 8, 4215 .atu_move_port_mask = 0xf, 4216 .multi_chip = true, 4217 .tag_protocol = DSA_TAG_PROTO_EDSA, 4218 .ops = &mv88e6185_ops, 4219 }, 4220 4221 [MV88E6190] = { 4222 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4223 .family = MV88E6XXX_FAMILY_6390, 4224 .name = "Marvell 88E6190", 4225 .num_databases = 4096, 4226 .num_ports = 11, /* 10 + Z80 */ 4227 .num_internal_phys = 11, 4228 .num_gpio = 16, 4229 .max_vid = 8191, 4230 .port_base_addr = 0x0, 4231 .phy_base_addr = 0x0, 4232 .global1_addr = 0x1b, 4233 .global2_addr = 0x1c, 4234 .tag_protocol = DSA_TAG_PROTO_DSA, 4235 .age_time_coeff = 3750, 4236 .g1_irqs = 9, 4237 .g2_irqs = 14, 4238 .pvt = true, 4239 .multi_chip = true, 4240 .atu_move_port_mask = 0x1f, 4241 .ops = &mv88e6190_ops, 4242 }, 4243 4244 [MV88E6190X] = { 4245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4246 .family = MV88E6XXX_FAMILY_6390, 4247 .name = "Marvell 88E6190X", 4248 .num_databases = 4096, 4249 .num_ports = 11, /* 10 + Z80 */ 4250 .num_internal_phys = 11, 4251 .num_gpio = 16, 4252 .max_vid = 8191, 4253 .port_base_addr = 0x0, 4254 .phy_base_addr = 0x0, 4255 .global1_addr = 0x1b, 4256 .global2_addr = 0x1c, 4257 .age_time_coeff = 3750, 4258 .g1_irqs = 9, 4259 .g2_irqs = 14, 4260 .atu_move_port_mask = 0x1f, 4261 .pvt = true, 4262 .multi_chip = true, 4263 .tag_protocol = DSA_TAG_PROTO_DSA, 4264 .ops = &mv88e6190x_ops, 4265 }, 4266 4267 [MV88E6191] = { 4268 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4269 .family = MV88E6XXX_FAMILY_6390, 4270 .name = "Marvell 88E6191", 4271 .num_databases = 4096, 4272 .num_ports = 11, /* 10 + Z80 */ 4273 .num_internal_phys = 11, 4274 .max_vid = 8191, 4275 .port_base_addr = 0x0, 4276 .phy_base_addr = 0x0, 4277 .global1_addr = 0x1b, 4278 .global2_addr = 0x1c, 4279 .age_time_coeff = 3750, 4280 .g1_irqs = 9, 4281 .g2_irqs = 14, 4282 .atu_move_port_mask = 0x1f, 4283 .pvt = true, 4284 .multi_chip = true, 4285 .tag_protocol = DSA_TAG_PROTO_DSA, 4286 .ptp_support = true, 4287 .ops = &mv88e6191_ops, 4288 }, 4289 4290 [MV88E6240] = { 4291 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4292 .family = MV88E6XXX_FAMILY_6352, 4293 .name = "Marvell 88E6240", 4294 .num_databases = 4096, 4295 .num_ports = 7, 4296 .num_internal_phys = 5, 4297 .num_gpio = 15, 4298 .max_vid = 4095, 4299 .port_base_addr = 0x10, 4300 .phy_base_addr = 0x0, 4301 .global1_addr = 0x1b, 4302 .global2_addr = 0x1c, 4303 .age_time_coeff = 15000, 4304 .g1_irqs = 9, 4305 .g2_irqs = 10, 4306 .atu_move_port_mask = 0xf, 4307 .pvt = true, 4308 .multi_chip = true, 4309 .tag_protocol = DSA_TAG_PROTO_EDSA, 4310 .ptp_support = true, 4311 .ops = &mv88e6240_ops, 4312 }, 4313 4314 [MV88E6290] = { 4315 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4316 .family = MV88E6XXX_FAMILY_6390, 4317 .name = "Marvell 88E6290", 4318 .num_databases = 4096, 4319 .num_ports = 11, /* 10 + Z80 */ 4320 .num_internal_phys = 11, 4321 .num_gpio = 16, 4322 .max_vid = 8191, 4323 .port_base_addr = 0x0, 4324 .phy_base_addr = 0x0, 4325 .global1_addr = 0x1b, 4326 .global2_addr = 0x1c, 4327 .age_time_coeff = 3750, 4328 .g1_irqs = 9, 4329 .g2_irqs = 14, 4330 .atu_move_port_mask = 0x1f, 4331 .pvt = true, 4332 .multi_chip = true, 4333 .tag_protocol = DSA_TAG_PROTO_DSA, 4334 .ptp_support = true, 4335 .ops = &mv88e6290_ops, 4336 }, 4337 4338 [MV88E6320] = { 4339 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4340 .family = MV88E6XXX_FAMILY_6320, 4341 .name = "Marvell 88E6320", 4342 .num_databases = 4096, 4343 .num_ports = 7, 4344 .num_internal_phys = 5, 4345 .num_gpio = 15, 4346 .max_vid = 4095, 4347 .port_base_addr = 0x10, 4348 .phy_base_addr = 0x0, 4349 .global1_addr = 0x1b, 4350 .global2_addr = 0x1c, 4351 .age_time_coeff = 15000, 4352 .g1_irqs = 8, 4353 .g2_irqs = 10, 4354 .atu_move_port_mask = 0xf, 4355 .pvt = true, 4356 .multi_chip = true, 4357 .tag_protocol = DSA_TAG_PROTO_EDSA, 4358 .ptp_support = true, 4359 .ops = &mv88e6320_ops, 4360 }, 4361 4362 [MV88E6321] = { 4363 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4364 .family = MV88E6XXX_FAMILY_6320, 4365 .name = "Marvell 88E6321", 4366 .num_databases = 4096, 4367 .num_ports = 7, 4368 .num_internal_phys = 5, 4369 .num_gpio = 15, 4370 .max_vid = 4095, 4371 .port_base_addr = 0x10, 4372 .phy_base_addr = 0x0, 4373 .global1_addr = 0x1b, 4374 .global2_addr = 0x1c, 4375 .age_time_coeff = 15000, 4376 .g1_irqs = 8, 4377 .g2_irqs = 10, 4378 .atu_move_port_mask = 0xf, 4379 .multi_chip = true, 4380 .tag_protocol = DSA_TAG_PROTO_EDSA, 4381 .ptp_support = true, 4382 .ops = &mv88e6321_ops, 4383 }, 4384 4385 [MV88E6341] = { 4386 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4387 .family = MV88E6XXX_FAMILY_6341, 4388 .name = "Marvell 88E6341", 4389 .num_databases = 4096, 4390 .num_internal_phys = 5, 4391 .num_ports = 6, 4392 .num_gpio = 11, 4393 .max_vid = 4095, 4394 .port_base_addr = 0x10, 4395 .phy_base_addr = 0x10, 4396 .global1_addr = 0x1b, 4397 .global2_addr = 0x1c, 4398 .age_time_coeff = 3750, 4399 .atu_move_port_mask = 0x1f, 4400 .g1_irqs = 9, 4401 .g2_irqs = 10, 4402 .pvt = true, 4403 .multi_chip = true, 4404 .tag_protocol = DSA_TAG_PROTO_EDSA, 4405 .ptp_support = true, 4406 .ops = &mv88e6341_ops, 4407 }, 4408 4409 [MV88E6350] = { 4410 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4411 .family = MV88E6XXX_FAMILY_6351, 4412 .name = "Marvell 88E6350", 4413 .num_databases = 4096, 4414 .num_ports = 7, 4415 .num_internal_phys = 5, 4416 .max_vid = 4095, 4417 .port_base_addr = 0x10, 4418 .phy_base_addr = 0x0, 4419 .global1_addr = 0x1b, 4420 .global2_addr = 0x1c, 4421 .age_time_coeff = 15000, 4422 .g1_irqs = 9, 4423 .g2_irqs = 10, 4424 .atu_move_port_mask = 0xf, 4425 .pvt = true, 4426 .multi_chip = true, 4427 .tag_protocol = DSA_TAG_PROTO_EDSA, 4428 .ops = &mv88e6350_ops, 4429 }, 4430 4431 [MV88E6351] = { 4432 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4433 .family = MV88E6XXX_FAMILY_6351, 4434 .name = "Marvell 88E6351", 4435 .num_databases = 4096, 4436 .num_ports = 7, 4437 .num_internal_phys = 5, 4438 .max_vid = 4095, 4439 .port_base_addr = 0x10, 4440 .phy_base_addr = 0x0, 4441 .global1_addr = 0x1b, 4442 .global2_addr = 0x1c, 4443 .age_time_coeff = 15000, 4444 .g1_irqs = 9, 4445 .g2_irqs = 10, 4446 .atu_move_port_mask = 0xf, 4447 .pvt = true, 4448 .multi_chip = true, 4449 .tag_protocol = DSA_TAG_PROTO_EDSA, 4450 .ops = &mv88e6351_ops, 4451 }, 4452 4453 [MV88E6352] = { 4454 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4455 .family = MV88E6XXX_FAMILY_6352, 4456 .name = "Marvell 88E6352", 4457 .num_databases = 4096, 4458 .num_ports = 7, 4459 .num_internal_phys = 5, 4460 .num_gpio = 15, 4461 .max_vid = 4095, 4462 .port_base_addr = 0x10, 4463 .phy_base_addr = 0x0, 4464 .global1_addr = 0x1b, 4465 .global2_addr = 0x1c, 4466 .age_time_coeff = 15000, 4467 .g1_irqs = 9, 4468 .g2_irqs = 10, 4469 .atu_move_port_mask = 0xf, 4470 .pvt = true, 4471 .multi_chip = true, 4472 .tag_protocol = DSA_TAG_PROTO_EDSA, 4473 .ptp_support = true, 4474 .ops = &mv88e6352_ops, 4475 }, 4476 [MV88E6390] = { 4477 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4478 .family = MV88E6XXX_FAMILY_6390, 4479 .name = "Marvell 88E6390", 4480 .num_databases = 4096, 4481 .num_ports = 11, /* 10 + Z80 */ 4482 .num_internal_phys = 11, 4483 .num_gpio = 16, 4484 .max_vid = 8191, 4485 .port_base_addr = 0x0, 4486 .phy_base_addr = 0x0, 4487 .global1_addr = 0x1b, 4488 .global2_addr = 0x1c, 4489 .age_time_coeff = 3750, 4490 .g1_irqs = 9, 4491 .g2_irqs = 14, 4492 .atu_move_port_mask = 0x1f, 4493 .pvt = true, 4494 .multi_chip = true, 4495 .tag_protocol = DSA_TAG_PROTO_DSA, 4496 .ptp_support = true, 4497 .ops = &mv88e6390_ops, 4498 }, 4499 [MV88E6390X] = { 4500 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4501 .family = MV88E6XXX_FAMILY_6390, 4502 .name = "Marvell 88E6390X", 4503 .num_databases = 4096, 4504 .num_ports = 11, /* 10 + Z80 */ 4505 .num_internal_phys = 11, 4506 .num_gpio = 16, 4507 .max_vid = 8191, 4508 .port_base_addr = 0x0, 4509 .phy_base_addr = 0x0, 4510 .global1_addr = 0x1b, 4511 .global2_addr = 0x1c, 4512 .age_time_coeff = 3750, 4513 .g1_irqs = 9, 4514 .g2_irqs = 14, 4515 .atu_move_port_mask = 0x1f, 4516 .pvt = true, 4517 .multi_chip = true, 4518 .tag_protocol = DSA_TAG_PROTO_DSA, 4519 .ptp_support = true, 4520 .ops = &mv88e6390x_ops, 4521 }, 4522 }; 4523 4524 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4525 { 4526 int i; 4527 4528 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4529 if (mv88e6xxx_table[i].prod_num == prod_num) 4530 return &mv88e6xxx_table[i]; 4531 4532 return NULL; 4533 } 4534 4535 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4536 { 4537 const struct mv88e6xxx_info *info; 4538 unsigned int prod_num, rev; 4539 u16 id; 4540 int err; 4541 4542 mutex_lock(&chip->reg_lock); 4543 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4544 mutex_unlock(&chip->reg_lock); 4545 if (err) 4546 return err; 4547 4548 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4549 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4550 4551 info = mv88e6xxx_lookup_info(prod_num); 4552 if (!info) 4553 return -ENODEV; 4554 4555 /* Update the compatible info with the probed one */ 4556 chip->info = info; 4557 4558 err = mv88e6xxx_g2_require(chip); 4559 if (err) 4560 return err; 4561 4562 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4563 chip->info->prod_num, chip->info->name, rev); 4564 4565 return 0; 4566 } 4567 4568 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4569 { 4570 struct mv88e6xxx_chip *chip; 4571 4572 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4573 if (!chip) 4574 return NULL; 4575 4576 chip->dev = dev; 4577 4578 mutex_init(&chip->reg_lock); 4579 INIT_LIST_HEAD(&chip->mdios); 4580 4581 return chip; 4582 } 4583 4584 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4585 struct mii_bus *bus, int sw_addr) 4586 { 4587 if (sw_addr == 0) 4588 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4589 else if (chip->info->multi_chip) 4590 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4591 else 4592 return -EINVAL; 4593 4594 chip->bus = bus; 4595 chip->sw_addr = sw_addr; 4596 4597 return 0; 4598 } 4599 4600 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4601 int port) 4602 { 4603 struct mv88e6xxx_chip *chip = ds->priv; 4604 4605 return chip->info->tag_protocol; 4606 } 4607 4608 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4609 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4610 struct device *host_dev, int sw_addr, 4611 void **priv) 4612 { 4613 struct mv88e6xxx_chip *chip; 4614 struct mii_bus *bus; 4615 int err; 4616 4617 bus = dsa_host_dev_to_mii_bus(host_dev); 4618 if (!bus) 4619 return NULL; 4620 4621 chip = mv88e6xxx_alloc_chip(dsa_dev); 4622 if (!chip) 4623 return NULL; 4624 4625 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4626 chip->info = &mv88e6xxx_table[MV88E6085]; 4627 4628 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4629 if (err) 4630 goto free; 4631 4632 err = mv88e6xxx_detect(chip); 4633 if (err) 4634 goto free; 4635 4636 mutex_lock(&chip->reg_lock); 4637 err = mv88e6xxx_switch_reset(chip); 4638 mutex_unlock(&chip->reg_lock); 4639 if (err) 4640 goto free; 4641 4642 mv88e6xxx_phy_init(chip); 4643 4644 err = mv88e6xxx_mdios_register(chip, NULL); 4645 if (err) 4646 goto free; 4647 4648 *priv = chip; 4649 4650 return chip->info->name; 4651 free: 4652 devm_kfree(dsa_dev, chip); 4653 4654 return NULL; 4655 } 4656 #endif 4657 4658 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4659 const struct switchdev_obj_port_mdb *mdb) 4660 { 4661 /* We don't need any dynamic resource from the kernel (yet), 4662 * so skip the prepare phase. 4663 */ 4664 4665 return 0; 4666 } 4667 4668 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4669 const struct switchdev_obj_port_mdb *mdb) 4670 { 4671 struct mv88e6xxx_chip *chip = ds->priv; 4672 4673 mutex_lock(&chip->reg_lock); 4674 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4675 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4676 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4677 port); 4678 mutex_unlock(&chip->reg_lock); 4679 } 4680 4681 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4682 const struct switchdev_obj_port_mdb *mdb) 4683 { 4684 struct mv88e6xxx_chip *chip = ds->priv; 4685 int err; 4686 4687 mutex_lock(&chip->reg_lock); 4688 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4689 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4690 mutex_unlock(&chip->reg_lock); 4691 4692 return err; 4693 } 4694 4695 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4696 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4697 .probe = mv88e6xxx_drv_probe, 4698 #endif 4699 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4700 .setup = mv88e6xxx_setup, 4701 .adjust_link = mv88e6xxx_adjust_link, 4702 .phylink_validate = mv88e6xxx_validate, 4703 .phylink_mac_link_state = mv88e6xxx_link_state, 4704 .phylink_mac_config = mv88e6xxx_mac_config, 4705 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4706 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4707 .get_strings = mv88e6xxx_get_strings, 4708 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4709 .get_sset_count = mv88e6xxx_get_sset_count, 4710 .port_enable = mv88e6xxx_port_enable, 4711 .port_disable = mv88e6xxx_port_disable, 4712 .get_mac_eee = mv88e6xxx_get_mac_eee, 4713 .set_mac_eee = mv88e6xxx_set_mac_eee, 4714 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4715 .get_eeprom = mv88e6xxx_get_eeprom, 4716 .set_eeprom = mv88e6xxx_set_eeprom, 4717 .get_regs_len = mv88e6xxx_get_regs_len, 4718 .get_regs = mv88e6xxx_get_regs, 4719 .set_ageing_time = mv88e6xxx_set_ageing_time, 4720 .port_bridge_join = mv88e6xxx_port_bridge_join, 4721 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4722 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4723 .port_fast_age = mv88e6xxx_port_fast_age, 4724 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4725 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4726 .port_vlan_add = mv88e6xxx_port_vlan_add, 4727 .port_vlan_del = mv88e6xxx_port_vlan_del, 4728 .port_fdb_add = mv88e6xxx_port_fdb_add, 4729 .port_fdb_del = mv88e6xxx_port_fdb_del, 4730 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4731 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4732 .port_mdb_add = mv88e6xxx_port_mdb_add, 4733 .port_mdb_del = mv88e6xxx_port_mdb_del, 4734 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4735 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4736 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4737 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4738 .port_txtstamp = mv88e6xxx_port_txtstamp, 4739 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4740 .get_ts_info = mv88e6xxx_get_ts_info, 4741 }; 4742 4743 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4744 .ops = &mv88e6xxx_switch_ops, 4745 }; 4746 4747 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4748 { 4749 struct device *dev = chip->dev; 4750 struct dsa_switch *ds; 4751 4752 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4753 if (!ds) 4754 return -ENOMEM; 4755 4756 ds->priv = chip; 4757 ds->dev = dev; 4758 ds->ops = &mv88e6xxx_switch_ops; 4759 ds->ageing_time_min = chip->info->age_time_coeff; 4760 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4761 4762 dev_set_drvdata(dev, ds); 4763 4764 return dsa_register_switch(ds); 4765 } 4766 4767 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4768 { 4769 dsa_unregister_switch(chip->ds); 4770 } 4771 4772 static const void *pdata_device_get_match_data(struct device *dev) 4773 { 4774 const struct of_device_id *matches = dev->driver->of_match_table; 4775 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4776 4777 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4778 matches++) { 4779 if (!strcmp(pdata->compatible, matches->compatible)) 4780 return matches->data; 4781 } 4782 return NULL; 4783 } 4784 4785 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4786 * would be lost after a power cycle so prevent it to be suspended. 4787 */ 4788 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4789 { 4790 return -EOPNOTSUPP; 4791 } 4792 4793 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4794 { 4795 return 0; 4796 } 4797 4798 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4799 4800 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4801 { 4802 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4803 const struct mv88e6xxx_info *compat_info = NULL; 4804 struct device *dev = &mdiodev->dev; 4805 struct device_node *np = dev->of_node; 4806 struct mv88e6xxx_chip *chip; 4807 int port; 4808 int err; 4809 4810 if (!np && !pdata) 4811 return -EINVAL; 4812 4813 if (np) 4814 compat_info = of_device_get_match_data(dev); 4815 4816 if (pdata) { 4817 compat_info = pdata_device_get_match_data(dev); 4818 4819 if (!pdata->netdev) 4820 return -EINVAL; 4821 4822 for (port = 0; port < DSA_MAX_PORTS; port++) { 4823 if (!(pdata->enabled_ports & (1 << port))) 4824 continue; 4825 if (strcmp(pdata->cd.port_names[port], "cpu")) 4826 continue; 4827 pdata->cd.netdev[port] = &pdata->netdev->dev; 4828 break; 4829 } 4830 } 4831 4832 if (!compat_info) 4833 return -EINVAL; 4834 4835 chip = mv88e6xxx_alloc_chip(dev); 4836 if (!chip) { 4837 err = -ENOMEM; 4838 goto out; 4839 } 4840 4841 chip->info = compat_info; 4842 4843 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4844 if (err) 4845 goto out; 4846 4847 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4848 if (IS_ERR(chip->reset)) { 4849 err = PTR_ERR(chip->reset); 4850 goto out; 4851 } 4852 4853 err = mv88e6xxx_detect(chip); 4854 if (err) 4855 goto out; 4856 4857 mv88e6xxx_phy_init(chip); 4858 4859 if (chip->info->ops->get_eeprom) { 4860 if (np) 4861 of_property_read_u32(np, "eeprom-length", 4862 &chip->eeprom_len); 4863 else 4864 chip->eeprom_len = pdata->eeprom_len; 4865 } 4866 4867 mutex_lock(&chip->reg_lock); 4868 err = mv88e6xxx_switch_reset(chip); 4869 mutex_unlock(&chip->reg_lock); 4870 if (err) 4871 goto out; 4872 4873 chip->irq = of_irq_get(np, 0); 4874 if (chip->irq == -EPROBE_DEFER) { 4875 err = chip->irq; 4876 goto out; 4877 } 4878 4879 /* Has to be performed before the MDIO bus is created, because 4880 * the PHYs will link their interrupts to these interrupt 4881 * controllers 4882 */ 4883 mutex_lock(&chip->reg_lock); 4884 if (chip->irq > 0) 4885 err = mv88e6xxx_g1_irq_setup(chip); 4886 else 4887 err = mv88e6xxx_irq_poll_setup(chip); 4888 mutex_unlock(&chip->reg_lock); 4889 4890 if (err) 4891 goto out; 4892 4893 if (chip->info->g2_irqs > 0) { 4894 err = mv88e6xxx_g2_irq_setup(chip); 4895 if (err) 4896 goto out_g1_irq; 4897 } 4898 4899 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4900 if (err) 4901 goto out_g2_irq; 4902 4903 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4904 if (err) 4905 goto out_g1_atu_prob_irq; 4906 4907 err = mv88e6xxx_mdios_register(chip, np); 4908 if (err) 4909 goto out_g1_vtu_prob_irq; 4910 4911 err = mv88e6xxx_register_switch(chip); 4912 if (err) 4913 goto out_mdio; 4914 4915 return 0; 4916 4917 out_mdio: 4918 mv88e6xxx_mdios_unregister(chip); 4919 out_g1_vtu_prob_irq: 4920 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4921 out_g1_atu_prob_irq: 4922 mv88e6xxx_g1_atu_prob_irq_free(chip); 4923 out_g2_irq: 4924 if (chip->info->g2_irqs > 0) 4925 mv88e6xxx_g2_irq_free(chip); 4926 out_g1_irq: 4927 if (chip->irq > 0) 4928 mv88e6xxx_g1_irq_free(chip); 4929 else 4930 mv88e6xxx_irq_poll_free(chip); 4931 out: 4932 if (pdata) 4933 dev_put(pdata->netdev); 4934 4935 return err; 4936 } 4937 4938 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4939 { 4940 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4941 struct mv88e6xxx_chip *chip = ds->priv; 4942 4943 if (chip->info->ptp_support) { 4944 mv88e6xxx_hwtstamp_free(chip); 4945 mv88e6xxx_ptp_free(chip); 4946 } 4947 4948 mv88e6xxx_phy_destroy(chip); 4949 mv88e6xxx_unregister_switch(chip); 4950 mv88e6xxx_mdios_unregister(chip); 4951 4952 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4953 mv88e6xxx_g1_atu_prob_irq_free(chip); 4954 4955 if (chip->info->g2_irqs > 0) 4956 mv88e6xxx_g2_irq_free(chip); 4957 4958 if (chip->irq > 0) 4959 mv88e6xxx_g1_irq_free(chip); 4960 else 4961 mv88e6xxx_irq_poll_free(chip); 4962 } 4963 4964 static const struct of_device_id mv88e6xxx_of_match[] = { 4965 { 4966 .compatible = "marvell,mv88e6085", 4967 .data = &mv88e6xxx_table[MV88E6085], 4968 }, 4969 { 4970 .compatible = "marvell,mv88e6190", 4971 .data = &mv88e6xxx_table[MV88E6190], 4972 }, 4973 { /* sentinel */ }, 4974 }; 4975 4976 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4977 4978 static struct mdio_driver mv88e6xxx_driver = { 4979 .probe = mv88e6xxx_probe, 4980 .remove = mv88e6xxx_remove, 4981 .mdiodrv.driver = { 4982 .name = "mv88e6085", 4983 .of_match_table = mv88e6xxx_of_match, 4984 .pm = &mv88e6xxx_pm_ops, 4985 }, 4986 }; 4987 4988 static int __init mv88e6xxx_init(void) 4989 { 4990 register_switch_driver(&mv88e6xxx_switch_drv); 4991 return mdio_driver_register(&mv88e6xxx_driver); 4992 } 4993 module_init(mv88e6xxx_init); 4994 4995 static void __exit mv88e6xxx_cleanup(void) 4996 { 4997 mdio_driver_unregister(&mv88e6xxx_driver); 4998 unregister_switch_driver(&mv88e6xxx_switch_drv); 4999 } 5000 module_exit(mv88e6xxx_cleanup); 5001 5002 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5003 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5004 MODULE_LICENSE("GPL"); 5005