1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void 570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 571 struct phylink_config *config) 572 { 573 unsigned long *supported = config->supported_interfaces; 574 int err; 575 u16 reg; 576 577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 578 if (err) { 579 dev_err(chip->dev, "p%d: failed to read port status\n", port); 580 return; 581 } 582 583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 589 break; 590 591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 593 __set_bit(PHY_INTERFACE_MODE_MII, supported); 594 break; 595 596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 601 break; 602 603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 605 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 606 break; 607 608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 610 break; 611 612 default: 613 dev_err(chip->dev, 614 "p%d: invalid port mode in status register: %04x\n", 615 port, reg); 616 } 617 } 618 619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 620 struct phylink_config *config) 621 { 622 if (!mv88e6xxx_phy_is_internal(chip, port)) 623 mv88e6250_setup_supported_interfaces(chip, port, config); 624 625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 626 } 627 628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 629 struct phylink_config *config) 630 { 631 unsigned long *supported = config->supported_interfaces; 632 633 /* Translate the default cmode */ 634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 635 636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 637 MAC_1000FD; 638 } 639 640 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 641 { 642 u16 reg, val; 643 int err; 644 645 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 646 if (err) 647 return err; 648 649 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 651 return 0xf; 652 653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 654 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 655 if (err) 656 return err; 657 658 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 659 if (err) 660 return err; 661 662 /* Restore PHY_DETECT value */ 663 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 664 if (err) 665 return err; 666 667 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 668 } 669 670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 671 struct phylink_config *config) 672 { 673 unsigned long *supported = config->supported_interfaces; 674 int err, cmode; 675 676 /* Translate the default cmode */ 677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 678 679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 680 MAC_1000FD; 681 682 /* Port 4 supports automedia if the serdes is associated with it. */ 683 if (port == 4) { 684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 685 if (err < 0) 686 dev_err(chip->dev, "p%d: failed to read scratch\n", 687 port); 688 if (err <= 0) 689 return; 690 691 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 692 if (cmode < 0) 693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 694 port); 695 else 696 mv88e6xxx_translate_cmode(cmode, supported); 697 } 698 } 699 700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 701 struct phylink_config *config) 702 { 703 unsigned long *supported = config->supported_interfaces; 704 int cmode; 705 706 /* Translate the default cmode */ 707 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 708 709 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 710 MAC_1000FD; 711 712 /* Port 0/1 are serdes only ports */ 713 if (port == 0 || port == 1) { 714 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 715 if (cmode < 0) 716 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 717 port); 718 else 719 mv88e6xxx_translate_cmode(cmode, supported); 720 } 721 } 722 723 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 724 struct phylink_config *config) 725 { 726 unsigned long *supported = config->supported_interfaces; 727 728 /* Translate the default cmode */ 729 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 730 731 /* No ethtool bits for 200Mbps */ 732 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 733 MAC_1000FD; 734 735 /* The C_Mode field is programmable on port 5 */ 736 if (port == 5) { 737 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 738 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 739 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 740 741 config->mac_capabilities |= MAC_2500FD; 742 } 743 } 744 745 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 746 struct phylink_config *config) 747 { 748 unsigned long *supported = config->supported_interfaces; 749 750 /* Translate the default cmode */ 751 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 752 753 /* No ethtool bits for 200Mbps */ 754 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 755 MAC_1000FD; 756 757 /* The C_Mode field is programmable on ports 9 and 10 */ 758 if (port == 9 || port == 10) { 759 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 760 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 761 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 762 763 config->mac_capabilities |= MAC_2500FD; 764 } 765 } 766 767 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 768 struct phylink_config *config) 769 { 770 unsigned long *supported = config->supported_interfaces; 771 772 mv88e6390_phylink_get_caps(chip, port, config); 773 774 /* For the 6x90X, ports 2-7 can be in automedia mode. 775 * (Note that 6x90 doesn't support RXAUI nor XAUI). 776 * 777 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 778 * configured for 1000BASE-X, SGMII or 2500BASE-X. 779 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 780 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 781 * 782 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 783 * configured for 1000BASE-X, SGMII or 2500BASE-X. 784 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 785 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 786 * 787 * For now, be permissive (as the old code was) and allow 1000BASE-X 788 * on ports 2..7. 789 */ 790 if (port >= 2 && port <= 7) 791 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 792 793 /* The C_Mode field can also be programmed for 10G speeds */ 794 if (port == 9 || port == 10) { 795 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 796 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 797 798 config->mac_capabilities |= MAC_10000FD; 799 } 800 } 801 802 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 803 struct phylink_config *config) 804 { 805 unsigned long *supported = config->supported_interfaces; 806 bool is_6191x = 807 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 808 bool is_6361 = 809 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 810 811 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 812 813 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 814 MAC_1000FD; 815 816 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 817 if (port == 0 || port == 9 || port == 10) { 818 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 819 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 820 821 /* 6191X supports >1G modes only on port 10 */ 822 if (!is_6191x || port == 10) { 823 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 824 config->mac_capabilities |= MAC_2500FD; 825 826 /* 6361 only supports up to 2500BaseX */ 827 if (!is_6361) { 828 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 829 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 831 config->mac_capabilities |= MAC_5000FD | 832 MAC_10000FD; 833 } 834 } 835 } 836 837 if (port == 0) { 838 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 839 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 843 } 844 } 845 846 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 847 struct phylink_config *config) 848 { 849 struct mv88e6xxx_chip *chip = ds->priv; 850 851 mv88e6xxx_reg_lock(chip); 852 chip->info->ops->phylink_get_caps(chip, port, config); 853 mv88e6xxx_reg_unlock(chip); 854 855 if (mv88e6xxx_phy_is_internal(chip, port)) { 856 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 857 config->supported_interfaces); 858 /* Internal ports with no phy-mode need GMII for PHYLIB */ 859 __set_bit(PHY_INTERFACE_MODE_GMII, 860 config->supported_interfaces); 861 } 862 } 863 864 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, 865 int port, 866 phy_interface_t interface) 867 { 868 struct mv88e6xxx_chip *chip = ds->priv; 869 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 870 871 if (chip->info->ops->pcs_ops) 872 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, 873 interface); 874 875 return pcs; 876 } 877 878 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 879 unsigned int mode, phy_interface_t interface) 880 { 881 struct mv88e6xxx_chip *chip = ds->priv; 882 int err = 0; 883 884 /* In inband mode, the link may come up at any time while the link 885 * is not forced down. Force the link down while we reconfigure the 886 * interface mode. 887 */ 888 if (mode == MLO_AN_INBAND && 889 chip->ports[port].interface != interface && 890 chip->info->ops->port_set_link) { 891 mv88e6xxx_reg_lock(chip); 892 err = chip->info->ops->port_set_link(chip, port, 893 LINK_FORCED_DOWN); 894 mv88e6xxx_reg_unlock(chip); 895 } 896 897 return err; 898 } 899 900 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 901 unsigned int mode, 902 const struct phylink_link_state *state) 903 { 904 struct mv88e6xxx_chip *chip = ds->priv; 905 int err = 0; 906 907 mv88e6xxx_reg_lock(chip); 908 909 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 910 err = mv88e6xxx_port_config_interface(chip, port, 911 state->interface); 912 if (err && err != -EOPNOTSUPP) 913 goto err_unlock; 914 } 915 916 err_unlock: 917 mv88e6xxx_reg_unlock(chip); 918 919 if (err && err != -EOPNOTSUPP) 920 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 921 } 922 923 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 924 unsigned int mode, phy_interface_t interface) 925 { 926 struct mv88e6xxx_chip *chip = ds->priv; 927 int err = 0; 928 929 /* Undo the forced down state above after completing configuration 930 * irrespective of its state on entry, which allows the link to come 931 * up in the in-band case where there is no separate SERDES. Also 932 * ensure that the link can come up if the PPU is in use and we are 933 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 934 */ 935 mv88e6xxx_reg_lock(chip); 936 937 if (chip->info->ops->port_set_link && 938 ((mode == MLO_AN_INBAND && 939 chip->ports[port].interface != interface) || 940 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 941 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 942 943 mv88e6xxx_reg_unlock(chip); 944 945 chip->ports[port].interface = interface; 946 947 return err; 948 } 949 950 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 951 unsigned int mode, 952 phy_interface_t interface) 953 { 954 struct mv88e6xxx_chip *chip = ds->priv; 955 const struct mv88e6xxx_ops *ops; 956 int err = 0; 957 958 ops = chip->info->ops; 959 960 mv88e6xxx_reg_lock(chip); 961 /* Force the link down if we know the port may not be automatically 962 * updated by the switch or if we are using fixed-link mode. 963 */ 964 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 965 mode == MLO_AN_FIXED) && ops->port_sync_link) 966 err = ops->port_sync_link(chip, port, mode, false); 967 968 if (!err && ops->port_set_speed_duplex) 969 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 970 DUPLEX_UNFORCED); 971 mv88e6xxx_reg_unlock(chip); 972 973 if (err) 974 dev_err(chip->dev, 975 "p%d: failed to force MAC link down\n", port); 976 } 977 978 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 979 unsigned int mode, phy_interface_t interface, 980 struct phy_device *phydev, 981 int speed, int duplex, 982 bool tx_pause, bool rx_pause) 983 { 984 struct mv88e6xxx_chip *chip = ds->priv; 985 const struct mv88e6xxx_ops *ops; 986 int err = 0; 987 988 ops = chip->info->ops; 989 990 mv88e6xxx_reg_lock(chip); 991 /* Configure and force the link up if we know that the port may not 992 * automatically updated by the switch or if we are using fixed-link 993 * mode. 994 */ 995 if (!mv88e6xxx_port_ppu_updates(chip, port) || 996 mode == MLO_AN_FIXED) { 997 if (ops->port_set_speed_duplex) { 998 err = ops->port_set_speed_duplex(chip, port, 999 speed, duplex); 1000 if (err && err != -EOPNOTSUPP) 1001 goto error; 1002 } 1003 1004 if (ops->port_sync_link) 1005 err = ops->port_sync_link(chip, port, mode, true); 1006 } 1007 error: 1008 mv88e6xxx_reg_unlock(chip); 1009 1010 if (err && err != -EOPNOTSUPP) 1011 dev_err(ds->dev, 1012 "p%d: failed to configure MAC link up\n", port); 1013 } 1014 1015 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1016 { 1017 int err; 1018 1019 if (!chip->info->ops->stats_snapshot) 1020 return -EOPNOTSUPP; 1021 1022 mv88e6xxx_reg_lock(chip); 1023 err = chip->info->ops->stats_snapshot(chip, port); 1024 mv88e6xxx_reg_unlock(chip); 1025 1026 return err; 1027 } 1028 1029 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1030 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1031 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1032 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1033 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1034 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1035 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1036 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1037 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1038 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1039 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1040 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1041 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1042 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1043 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1044 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1045 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1046 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1047 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1048 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1049 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1050 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1051 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1052 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1053 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1054 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1055 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1056 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1057 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1058 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1059 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1060 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1061 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1062 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1063 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1064 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1065 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1066 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1067 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1068 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1069 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1070 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1071 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1072 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1073 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1074 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1075 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1076 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1077 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1078 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1079 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1080 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1081 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1082 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1083 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1084 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1085 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1086 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1087 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1088 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1089 /* */ 1090 1091 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1092 { #_string, _size, _reg, _type } 1093 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1094 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1095 }; 1096 1097 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1098 MV88E6XXX_HW_STAT_ID_ ## _string 1099 enum mv88e6xxx_hw_stat_id { 1100 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1101 }; 1102 1103 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1104 const struct mv88e6xxx_hw_stat *s, 1105 int port, u16 bank1_select, 1106 u16 histogram) 1107 { 1108 u32 low; 1109 u32 high = 0; 1110 u16 reg = 0; 1111 int err; 1112 u64 value; 1113 1114 switch (s->type) { 1115 case STATS_TYPE_PORT: 1116 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1117 if (err) 1118 return U64_MAX; 1119 1120 low = reg; 1121 if (s->size == 4) { 1122 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1123 if (err) 1124 return U64_MAX; 1125 low |= ((u32)reg) << 16; 1126 } 1127 break; 1128 case STATS_TYPE_BANK1: 1129 reg = bank1_select; 1130 fallthrough; 1131 case STATS_TYPE_BANK0: 1132 reg |= s->reg | histogram; 1133 mv88e6xxx_g1_stats_read(chip, reg, &low); 1134 if (s->size == 8) 1135 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1136 break; 1137 default: 1138 return U64_MAX; 1139 } 1140 value = (((u64)high) << 32) | low; 1141 return value; 1142 } 1143 1144 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1145 uint8_t *data, int types) 1146 { 1147 const struct mv88e6xxx_hw_stat *stat; 1148 int i, j; 1149 1150 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1151 stat = &mv88e6xxx_hw_stats[i]; 1152 if (stat->type & types) { 1153 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1154 ETH_GSTRING_LEN); 1155 j++; 1156 } 1157 } 1158 1159 return j; 1160 } 1161 1162 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1163 uint8_t *data) 1164 { 1165 return mv88e6xxx_stats_get_strings(chip, data, 1166 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1167 } 1168 1169 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t *data) 1171 { 1172 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1173 } 1174 1175 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1176 uint8_t *data) 1177 { 1178 return mv88e6xxx_stats_get_strings(chip, data, 1179 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1180 } 1181 1182 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1183 "atu_member_violation", 1184 "atu_miss_violation", 1185 "atu_full_violation", 1186 "vtu_member_violation", 1187 "vtu_miss_violation", 1188 }; 1189 1190 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1191 { 1192 unsigned int i; 1193 1194 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1195 strscpy(data + i * ETH_GSTRING_LEN, 1196 mv88e6xxx_atu_vtu_stats_strings[i], 1197 ETH_GSTRING_LEN); 1198 } 1199 1200 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1201 u32 stringset, uint8_t *data) 1202 { 1203 struct mv88e6xxx_chip *chip = ds->priv; 1204 int count = 0; 1205 1206 if (stringset != ETH_SS_STATS) 1207 return; 1208 1209 mv88e6xxx_reg_lock(chip); 1210 1211 if (chip->info->ops->stats_get_strings) 1212 count = chip->info->ops->stats_get_strings(chip, data); 1213 1214 if (chip->info->ops->serdes_get_strings) { 1215 data += count * ETH_GSTRING_LEN; 1216 count = chip->info->ops->serdes_get_strings(chip, port, data); 1217 } 1218 1219 data += count * ETH_GSTRING_LEN; 1220 mv88e6xxx_atu_vtu_get_strings(data); 1221 1222 mv88e6xxx_reg_unlock(chip); 1223 } 1224 1225 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1226 int types) 1227 { 1228 const struct mv88e6xxx_hw_stat *stat; 1229 int i, j; 1230 1231 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1232 stat = &mv88e6xxx_hw_stats[i]; 1233 if (stat->type & types) 1234 j++; 1235 } 1236 return j; 1237 } 1238 1239 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1240 { 1241 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1242 STATS_TYPE_PORT); 1243 } 1244 1245 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1246 { 1247 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1248 } 1249 1250 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1251 { 1252 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1253 STATS_TYPE_BANK1); 1254 } 1255 1256 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1257 { 1258 struct mv88e6xxx_chip *chip = ds->priv; 1259 int serdes_count = 0; 1260 int count = 0; 1261 1262 if (sset != ETH_SS_STATS) 1263 return 0; 1264 1265 mv88e6xxx_reg_lock(chip); 1266 if (chip->info->ops->stats_get_sset_count) 1267 count = chip->info->ops->stats_get_sset_count(chip); 1268 if (count < 0) 1269 goto out; 1270 1271 if (chip->info->ops->serdes_get_sset_count) 1272 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1273 port); 1274 if (serdes_count < 0) { 1275 count = serdes_count; 1276 goto out; 1277 } 1278 count += serdes_count; 1279 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1280 1281 out: 1282 mv88e6xxx_reg_unlock(chip); 1283 1284 return count; 1285 } 1286 1287 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1288 const struct mv88e6xxx_hw_stat *stat, 1289 uint64_t *data) 1290 { 1291 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT))) 1292 return 0; 1293 1294 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1295 MV88E6XXX_G1_STATS_OP_HIST_RX); 1296 return 1; 1297 } 1298 1299 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1300 const struct mv88e6xxx_hw_stat *stat, 1301 uint64_t *data) 1302 { 1303 if (!(stat->type & STATS_TYPE_BANK0)) 1304 return 0; 1305 1306 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1307 MV88E6XXX_G1_STATS_OP_HIST_RX); 1308 return 1; 1309 } 1310 1311 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1312 const struct mv88e6xxx_hw_stat *stat, 1313 uint64_t *data) 1314 { 1315 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1316 return 0; 1317 1318 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1319 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1320 MV88E6XXX_G1_STATS_OP_HIST_RX); 1321 return 1; 1322 } 1323 1324 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1325 const struct mv88e6xxx_hw_stat *stat, 1326 uint64_t *data) 1327 { 1328 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1329 return 0; 1330 1331 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1332 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1333 0); 1334 return 1; 1335 } 1336 1337 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1338 const struct mv88e6xxx_hw_stat *stat, 1339 uint64_t *data) 1340 { 1341 int ret = 0; 1342 1343 if (chip->info->ops->stats_get_stat) { 1344 mv88e6xxx_reg_lock(chip); 1345 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1346 mv88e6xxx_reg_unlock(chip); 1347 } 1348 1349 return ret; 1350 } 1351 1352 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1353 uint64_t *data) 1354 { 1355 const struct mv88e6xxx_hw_stat *stat; 1356 size_t i, j; 1357 1358 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1359 stat = &mv88e6xxx_hw_stats[i]; 1360 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1361 } 1362 return j; 1363 } 1364 1365 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1366 uint64_t *data) 1367 { 1368 *data++ = chip->ports[port].atu_member_violation; 1369 *data++ = chip->ports[port].atu_miss_violation; 1370 *data++ = chip->ports[port].atu_full_violation; 1371 *data++ = chip->ports[port].vtu_member_violation; 1372 *data++ = chip->ports[port].vtu_miss_violation; 1373 } 1374 1375 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1376 uint64_t *data) 1377 { 1378 size_t count; 1379 1380 count = mv88e6xxx_stats_get_stats(chip, port, data); 1381 1382 mv88e6xxx_reg_lock(chip); 1383 if (chip->info->ops->serdes_get_stats) { 1384 data += count; 1385 count = chip->info->ops->serdes_get_stats(chip, port, data); 1386 } 1387 data += count; 1388 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1389 mv88e6xxx_reg_unlock(chip); 1390 } 1391 1392 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1393 uint64_t *data) 1394 { 1395 struct mv88e6xxx_chip *chip = ds->priv; 1396 int ret; 1397 1398 ret = mv88e6xxx_stats_snapshot(chip, port); 1399 if (ret < 0) 1400 return; 1401 1402 mv88e6xxx_get_stats(chip, port, data); 1403 } 1404 1405 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1406 struct ethtool_eth_mac_stats *mac_stats) 1407 { 1408 struct mv88e6xxx_chip *chip = ds->priv; 1409 int ret; 1410 1411 ret = mv88e6xxx_stats_snapshot(chip, port); 1412 if (ret < 0) 1413 return; 1414 1415 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1416 mv88e6xxx_stats_get_stat(chip, port, \ 1417 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1418 &mac_stats->stats._member) 1419 1420 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1426 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1427 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1428 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1429 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1430 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1431 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1432 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1433 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1434 1435 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1436 1437 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1438 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1439 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1440 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1441 } 1442 1443 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1444 struct ethtool_rmon_stats *rmon_stats, 1445 const struct ethtool_rmon_hist_range **ranges) 1446 { 1447 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1448 { 64, 64 }, 1449 { 65, 127 }, 1450 { 128, 255 }, 1451 { 256, 511 }, 1452 { 512, 1023 }, 1453 { 1024, 65535 }, 1454 {} 1455 }; 1456 struct mv88e6xxx_chip *chip = ds->priv; 1457 int ret; 1458 1459 ret = mv88e6xxx_stats_snapshot(chip, port); 1460 if (ret < 0) 1461 return; 1462 1463 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1464 mv88e6xxx_stats_get_stat(chip, port, \ 1465 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1466 &rmon_stats->stats._member) 1467 1468 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1469 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1470 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1471 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1472 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1473 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1474 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1475 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1476 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1477 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1478 1479 #undef MV88E6XXX_RMON_STAT_MAP 1480 1481 *ranges = rmon_ranges; 1482 } 1483 1484 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1485 { 1486 struct mv88e6xxx_chip *chip = ds->priv; 1487 int len; 1488 1489 len = 32 * sizeof(u16); 1490 if (chip->info->ops->serdes_get_regs_len) 1491 len += chip->info->ops->serdes_get_regs_len(chip, port); 1492 1493 return len; 1494 } 1495 1496 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1497 struct ethtool_regs *regs, void *_p) 1498 { 1499 struct mv88e6xxx_chip *chip = ds->priv; 1500 int err; 1501 u16 reg; 1502 u16 *p = _p; 1503 int i; 1504 1505 regs->version = chip->info->prod_num; 1506 1507 memset(p, 0xff, 32 * sizeof(u16)); 1508 1509 mv88e6xxx_reg_lock(chip); 1510 1511 for (i = 0; i < 32; i++) { 1512 1513 err = mv88e6xxx_port_read(chip, port, i, ®); 1514 if (!err) 1515 p[i] = reg; 1516 } 1517 1518 if (chip->info->ops->serdes_get_regs) 1519 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1520 1521 mv88e6xxx_reg_unlock(chip); 1522 } 1523 1524 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1525 struct ethtool_keee *e) 1526 { 1527 /* Nothing to do on the port's MAC */ 1528 return 0; 1529 } 1530 1531 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1532 struct ethtool_keee *e) 1533 { 1534 /* Nothing to do on the port's MAC */ 1535 return 0; 1536 } 1537 1538 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1539 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1540 { 1541 struct dsa_switch *ds = chip->ds; 1542 struct dsa_switch_tree *dst = ds->dst; 1543 struct dsa_port *dp, *other_dp; 1544 bool found = false; 1545 u16 pvlan; 1546 1547 /* dev is a physical switch */ 1548 if (dev <= dst->last_switch) { 1549 list_for_each_entry(dp, &dst->ports, list) { 1550 if (dp->ds->index == dev && dp->index == port) { 1551 /* dp might be a DSA link or a user port, so it 1552 * might or might not have a bridge. 1553 * Use the "found" variable for both cases. 1554 */ 1555 found = true; 1556 break; 1557 } 1558 } 1559 /* dev is a virtual bridge */ 1560 } else { 1561 list_for_each_entry(dp, &dst->ports, list) { 1562 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1563 1564 if (!bridge_num) 1565 continue; 1566 1567 if (bridge_num + dst->last_switch != dev) 1568 continue; 1569 1570 found = true; 1571 break; 1572 } 1573 } 1574 1575 /* Prevent frames from unknown switch or virtual bridge */ 1576 if (!found) 1577 return 0; 1578 1579 /* Frames from DSA links and CPU ports can egress any local port */ 1580 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1581 return mv88e6xxx_port_mask(chip); 1582 1583 pvlan = 0; 1584 1585 /* Frames from standalone user ports can only egress on the 1586 * upstream port. 1587 */ 1588 if (!dsa_port_bridge_dev_get(dp)) 1589 return BIT(dsa_switch_upstream_port(ds)); 1590 1591 /* Frames from bridged user ports can egress any local DSA 1592 * links and CPU ports, as well as any local member of their 1593 * bridge group. 1594 */ 1595 dsa_switch_for_each_port(other_dp, ds) 1596 if (other_dp->type == DSA_PORT_TYPE_CPU || 1597 other_dp->type == DSA_PORT_TYPE_DSA || 1598 dsa_port_bridge_same(dp, other_dp)) 1599 pvlan |= BIT(other_dp->index); 1600 1601 return pvlan; 1602 } 1603 1604 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1605 { 1606 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1607 1608 /* prevent frames from going back out of the port they came in on */ 1609 output_ports &= ~BIT(port); 1610 1611 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1612 } 1613 1614 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1615 u8 state) 1616 { 1617 struct mv88e6xxx_chip *chip = ds->priv; 1618 int err; 1619 1620 mv88e6xxx_reg_lock(chip); 1621 err = mv88e6xxx_port_set_state(chip, port, state); 1622 mv88e6xxx_reg_unlock(chip); 1623 1624 if (err) 1625 dev_err(ds->dev, "p%d: failed to update state\n", port); 1626 } 1627 1628 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1629 { 1630 int err; 1631 1632 if (chip->info->ops->ieee_pri_map) { 1633 err = chip->info->ops->ieee_pri_map(chip); 1634 if (err) 1635 return err; 1636 } 1637 1638 if (chip->info->ops->ip_pri_map) { 1639 err = chip->info->ops->ip_pri_map(chip); 1640 if (err) 1641 return err; 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1648 { 1649 struct dsa_switch *ds = chip->ds; 1650 int target, port; 1651 int err; 1652 1653 if (!chip->info->global2_addr) 1654 return 0; 1655 1656 /* Initialize the routing port to the 32 possible target devices */ 1657 for (target = 0; target < 32; target++) { 1658 port = dsa_routing_port(ds, target); 1659 if (port == ds->num_ports) 1660 port = 0x1f; 1661 1662 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1663 if (err) 1664 return err; 1665 } 1666 1667 if (chip->info->ops->set_cascade_port) { 1668 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1669 err = chip->info->ops->set_cascade_port(chip, port); 1670 if (err) 1671 return err; 1672 } 1673 1674 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1675 if (err) 1676 return err; 1677 1678 return 0; 1679 } 1680 1681 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1682 { 1683 /* Clear all trunk masks and mapping */ 1684 if (chip->info->global2_addr) 1685 return mv88e6xxx_g2_trunk_clear(chip); 1686 1687 return 0; 1688 } 1689 1690 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1691 { 1692 if (chip->info->ops->rmu_disable) 1693 return chip->info->ops->rmu_disable(chip); 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1699 { 1700 if (chip->info->ops->pot_clear) 1701 return chip->info->ops->pot_clear(chip); 1702 1703 return 0; 1704 } 1705 1706 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1707 { 1708 if (chip->info->ops->mgmt_rsvd2cpu) 1709 return chip->info->ops->mgmt_rsvd2cpu(chip); 1710 1711 return 0; 1712 } 1713 1714 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1715 { 1716 int err; 1717 1718 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1719 if (err) 1720 return err; 1721 1722 /* The chips that have a "learn2all" bit in Global1, ATU 1723 * Control are precisely those whose port registers have a 1724 * Message Port bit in Port Control 1 and hence implement 1725 * ->port_setup_message_port. 1726 */ 1727 if (chip->info->ops->port_setup_message_port) { 1728 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1729 if (err) 1730 return err; 1731 } 1732 1733 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1734 } 1735 1736 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1737 { 1738 int port; 1739 int err; 1740 1741 if (!chip->info->ops->irl_init_all) 1742 return 0; 1743 1744 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1745 /* Disable ingress rate limiting by resetting all per port 1746 * ingress rate limit resources to their initial state. 1747 */ 1748 err = chip->info->ops->irl_init_all(chip, port); 1749 if (err) 1750 return err; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1757 { 1758 if (chip->info->ops->set_switch_mac) { 1759 u8 addr[ETH_ALEN]; 1760 1761 eth_random_addr(addr); 1762 1763 return chip->info->ops->set_switch_mac(chip, addr); 1764 } 1765 1766 return 0; 1767 } 1768 1769 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1770 { 1771 struct dsa_switch_tree *dst = chip->ds->dst; 1772 struct dsa_switch *ds; 1773 struct dsa_port *dp; 1774 u16 pvlan = 0; 1775 1776 if (!mv88e6xxx_has_pvt(chip)) 1777 return 0; 1778 1779 /* Skip the local source device, which uses in-chip port VLAN */ 1780 if (dev != chip->ds->index) { 1781 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1782 1783 ds = dsa_switch_find(dst->index, dev); 1784 dp = ds ? dsa_to_port(ds, port) : NULL; 1785 if (dp && dp->lag) { 1786 /* As the PVT is used to limit flooding of 1787 * FORWARD frames, which use the LAG ID as the 1788 * source port, we must translate dev/port to 1789 * the special "LAG device" in the PVT, using 1790 * the LAG ID (one-based) as the port number 1791 * (zero-based). 1792 */ 1793 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1794 port = dsa_port_lag_id_get(dp) - 1; 1795 } 1796 } 1797 1798 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1799 } 1800 1801 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1802 { 1803 int dev, port; 1804 int err; 1805 1806 if (!mv88e6xxx_has_pvt(chip)) 1807 return 0; 1808 1809 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1810 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1811 */ 1812 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1813 if (err) 1814 return err; 1815 1816 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1817 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1818 err = mv88e6xxx_pvt_map(chip, dev, port); 1819 if (err) 1820 return err; 1821 } 1822 } 1823 1824 return 0; 1825 } 1826 1827 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1828 u16 fid) 1829 { 1830 if (dsa_to_port(chip->ds, port)->lag) 1831 /* Hardware is incapable of fast-aging a LAG through a 1832 * regular ATU move operation. Until we have something 1833 * more fancy in place this is a no-op. 1834 */ 1835 return -EOPNOTSUPP; 1836 1837 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1838 } 1839 1840 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1841 { 1842 struct mv88e6xxx_chip *chip = ds->priv; 1843 int err; 1844 1845 mv88e6xxx_reg_lock(chip); 1846 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1847 mv88e6xxx_reg_unlock(chip); 1848 1849 if (err) 1850 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1851 port, err); 1852 } 1853 1854 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1855 { 1856 if (!mv88e6xxx_max_vid(chip)) 1857 return 0; 1858 1859 return mv88e6xxx_g1_vtu_flush(chip); 1860 } 1861 1862 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1863 struct mv88e6xxx_vtu_entry *entry) 1864 { 1865 int err; 1866 1867 if (!chip->info->ops->vtu_getnext) 1868 return -EOPNOTSUPP; 1869 1870 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1871 entry->valid = false; 1872 1873 err = chip->info->ops->vtu_getnext(chip, entry); 1874 1875 if (entry->vid != vid) 1876 entry->valid = false; 1877 1878 return err; 1879 } 1880 1881 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1882 int (*cb)(struct mv88e6xxx_chip *chip, 1883 const struct mv88e6xxx_vtu_entry *entry, 1884 void *priv), 1885 void *priv) 1886 { 1887 struct mv88e6xxx_vtu_entry entry = { 1888 .vid = mv88e6xxx_max_vid(chip), 1889 .valid = false, 1890 }; 1891 int err; 1892 1893 if (!chip->info->ops->vtu_getnext) 1894 return -EOPNOTSUPP; 1895 1896 do { 1897 err = chip->info->ops->vtu_getnext(chip, &entry); 1898 if (err) 1899 return err; 1900 1901 if (!entry.valid) 1902 break; 1903 1904 err = cb(chip, &entry, priv); 1905 if (err) 1906 return err; 1907 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1908 1909 return 0; 1910 } 1911 1912 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1913 struct mv88e6xxx_vtu_entry *entry) 1914 { 1915 if (!chip->info->ops->vtu_loadpurge) 1916 return -EOPNOTSUPP; 1917 1918 return chip->info->ops->vtu_loadpurge(chip, entry); 1919 } 1920 1921 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1922 const struct mv88e6xxx_vtu_entry *entry, 1923 void *_fid_bitmap) 1924 { 1925 unsigned long *fid_bitmap = _fid_bitmap; 1926 1927 set_bit(entry->fid, fid_bitmap); 1928 return 0; 1929 } 1930 1931 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1932 { 1933 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1934 1935 /* Every FID has an associated VID, so walking the VTU 1936 * will discover the full set of FIDs in use. 1937 */ 1938 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1939 } 1940 1941 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1942 { 1943 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1944 int err; 1945 1946 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1947 if (err) 1948 return err; 1949 1950 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1951 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1952 return -ENOSPC; 1953 1954 /* Clear the database */ 1955 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1956 } 1957 1958 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1959 struct mv88e6xxx_stu_entry *entry) 1960 { 1961 if (!chip->info->ops->stu_loadpurge) 1962 return -EOPNOTSUPP; 1963 1964 return chip->info->ops->stu_loadpurge(chip, entry); 1965 } 1966 1967 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1968 { 1969 struct mv88e6xxx_stu_entry stu = { 1970 .valid = true, 1971 .sid = 0 1972 }; 1973 1974 if (!mv88e6xxx_has_stu(chip)) 1975 return 0; 1976 1977 /* Make sure that SID 0 is always valid. This is used by VTU 1978 * entries that do not make use of the STU, e.g. when creating 1979 * a VLAN upper on a port that is also part of a VLAN 1980 * filtering bridge. 1981 */ 1982 return mv88e6xxx_stu_loadpurge(chip, &stu); 1983 } 1984 1985 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1986 { 1987 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1988 struct mv88e6xxx_mst *mst; 1989 1990 __set_bit(0, busy); 1991 1992 list_for_each_entry(mst, &chip->msts, node) 1993 __set_bit(mst->stu.sid, busy); 1994 1995 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1996 1997 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1998 } 1999 2000 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 2001 { 2002 struct mv88e6xxx_mst *mst, *tmp; 2003 int err; 2004 2005 if (!sid) 2006 return 0; 2007 2008 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 2009 if (mst->stu.sid != sid) 2010 continue; 2011 2012 if (!refcount_dec_and_test(&mst->refcnt)) 2013 return 0; 2014 2015 mst->stu.valid = false; 2016 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2017 if (err) { 2018 refcount_set(&mst->refcnt, 1); 2019 return err; 2020 } 2021 2022 list_del(&mst->node); 2023 kfree(mst); 2024 return 0; 2025 } 2026 2027 return -ENOENT; 2028 } 2029 2030 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 2031 u16 msti, u8 *sid) 2032 { 2033 struct mv88e6xxx_mst *mst; 2034 int err, i; 2035 2036 if (!mv88e6xxx_has_stu(chip)) { 2037 err = -EOPNOTSUPP; 2038 goto err; 2039 } 2040 2041 if (!msti) { 2042 *sid = 0; 2043 return 0; 2044 } 2045 2046 list_for_each_entry(mst, &chip->msts, node) { 2047 if (mst->br == br && mst->msti == msti) { 2048 refcount_inc(&mst->refcnt); 2049 *sid = mst->stu.sid; 2050 return 0; 2051 } 2052 } 2053 2054 err = mv88e6xxx_sid_get(chip, sid); 2055 if (err) 2056 goto err; 2057 2058 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2059 if (!mst) { 2060 err = -ENOMEM; 2061 goto err; 2062 } 2063 2064 INIT_LIST_HEAD(&mst->node); 2065 refcount_set(&mst->refcnt, 1); 2066 mst->br = br; 2067 mst->msti = msti; 2068 mst->stu.valid = true; 2069 mst->stu.sid = *sid; 2070 2071 /* The bridge starts out all ports in the disabled state. But 2072 * a STU state of disabled means to go by the port-global 2073 * state. So we set all user port's initial state to blocking, 2074 * to match the bridge's behavior. 2075 */ 2076 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2077 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2078 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2079 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2080 2081 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2082 if (err) 2083 goto err_free; 2084 2085 list_add_tail(&mst->node, &chip->msts); 2086 return 0; 2087 2088 err_free: 2089 kfree(mst); 2090 err: 2091 return err; 2092 } 2093 2094 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2095 const struct switchdev_mst_state *st) 2096 { 2097 struct dsa_port *dp = dsa_to_port(ds, port); 2098 struct mv88e6xxx_chip *chip = ds->priv; 2099 struct mv88e6xxx_mst *mst; 2100 u8 state; 2101 int err; 2102 2103 if (!mv88e6xxx_has_stu(chip)) 2104 return -EOPNOTSUPP; 2105 2106 switch (st->state) { 2107 case BR_STATE_DISABLED: 2108 case BR_STATE_BLOCKING: 2109 case BR_STATE_LISTENING: 2110 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2111 break; 2112 case BR_STATE_LEARNING: 2113 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2114 break; 2115 case BR_STATE_FORWARDING: 2116 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2117 break; 2118 default: 2119 return -EINVAL; 2120 } 2121 2122 list_for_each_entry(mst, &chip->msts, node) { 2123 if (mst->br == dsa_port_bridge_dev_get(dp) && 2124 mst->msti == st->msti) { 2125 if (mst->stu.state[port] == state) 2126 return 0; 2127 2128 mst->stu.state[port] = state; 2129 mv88e6xxx_reg_lock(chip); 2130 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2131 mv88e6xxx_reg_unlock(chip); 2132 return err; 2133 } 2134 } 2135 2136 return -ENOENT; 2137 } 2138 2139 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2140 u16 vid) 2141 { 2142 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2143 struct mv88e6xxx_chip *chip = ds->priv; 2144 struct mv88e6xxx_vtu_entry vlan; 2145 int err; 2146 2147 /* DSA and CPU ports have to be members of multiple vlans */ 2148 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2149 return 0; 2150 2151 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2152 if (err) 2153 return err; 2154 2155 if (!vlan.valid) 2156 return 0; 2157 2158 dsa_switch_for_each_user_port(other_dp, ds) { 2159 struct net_device *other_br; 2160 2161 if (vlan.member[other_dp->index] == 2162 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2163 continue; 2164 2165 if (dsa_port_bridge_same(dp, other_dp)) 2166 break; /* same bridge, check next VLAN */ 2167 2168 other_br = dsa_port_bridge_dev_get(other_dp); 2169 if (!other_br) 2170 continue; 2171 2172 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2173 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2174 return -EOPNOTSUPP; 2175 } 2176 2177 return 0; 2178 } 2179 2180 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2181 { 2182 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2183 struct net_device *br = dsa_port_bridge_dev_get(dp); 2184 struct mv88e6xxx_port *p = &chip->ports[port]; 2185 u16 pvid = MV88E6XXX_VID_STANDALONE; 2186 bool drop_untagged = false; 2187 int err; 2188 2189 if (br) { 2190 if (br_vlan_enabled(br)) { 2191 pvid = p->bridge_pvid.vid; 2192 drop_untagged = !p->bridge_pvid.valid; 2193 } else { 2194 pvid = MV88E6XXX_VID_BRIDGED; 2195 } 2196 } 2197 2198 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2199 if (err) 2200 return err; 2201 2202 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2203 } 2204 2205 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2206 bool vlan_filtering, 2207 struct netlink_ext_ack *extack) 2208 { 2209 struct mv88e6xxx_chip *chip = ds->priv; 2210 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2211 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2212 int err; 2213 2214 if (!mv88e6xxx_max_vid(chip)) 2215 return -EOPNOTSUPP; 2216 2217 mv88e6xxx_reg_lock(chip); 2218 2219 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2220 if (err) 2221 goto unlock; 2222 2223 err = mv88e6xxx_port_commit_pvid(chip, port); 2224 if (err) 2225 goto unlock; 2226 2227 unlock: 2228 mv88e6xxx_reg_unlock(chip); 2229 2230 return err; 2231 } 2232 2233 static int 2234 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2235 const struct switchdev_obj_port_vlan *vlan) 2236 { 2237 struct mv88e6xxx_chip *chip = ds->priv; 2238 int err; 2239 2240 if (!mv88e6xxx_max_vid(chip)) 2241 return -EOPNOTSUPP; 2242 2243 /* If the requested port doesn't belong to the same bridge as the VLAN 2244 * members, do not support it (yet) and fallback to software VLAN. 2245 */ 2246 mv88e6xxx_reg_lock(chip); 2247 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2248 mv88e6xxx_reg_unlock(chip); 2249 2250 return err; 2251 } 2252 2253 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2254 const unsigned char *addr, u16 vid, 2255 u8 state) 2256 { 2257 struct mv88e6xxx_atu_entry entry; 2258 struct mv88e6xxx_vtu_entry vlan; 2259 u16 fid; 2260 int err; 2261 2262 /* Ports have two private address databases: one for when the port is 2263 * standalone and one for when the port is under a bridge and the 2264 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2265 * address database to remain 100% empty, so we never load an ATU entry 2266 * into a standalone port's database. Therefore, translate the null 2267 * VLAN ID into the port's database used for VLAN-unaware bridging. 2268 */ 2269 if (vid == 0) { 2270 fid = MV88E6XXX_FID_BRIDGED; 2271 } else { 2272 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2273 if (err) 2274 return err; 2275 2276 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2277 if (!vlan.valid) 2278 return -EOPNOTSUPP; 2279 2280 fid = vlan.fid; 2281 } 2282 2283 entry.state = 0; 2284 ether_addr_copy(entry.mac, addr); 2285 eth_addr_dec(entry.mac); 2286 2287 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2288 if (err) 2289 return err; 2290 2291 /* Initialize a fresh ATU entry if it isn't found */ 2292 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2293 memset(&entry, 0, sizeof(entry)); 2294 ether_addr_copy(entry.mac, addr); 2295 } 2296 2297 /* Purge the ATU entry only if no port is using it anymore */ 2298 if (!state) { 2299 entry.portvec &= ~BIT(port); 2300 if (!entry.portvec) 2301 entry.state = 0; 2302 } else { 2303 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2304 entry.portvec = BIT(port); 2305 else 2306 entry.portvec |= BIT(port); 2307 2308 entry.state = state; 2309 } 2310 2311 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2312 } 2313 2314 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2315 const struct mv88e6xxx_policy *policy) 2316 { 2317 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2318 enum mv88e6xxx_policy_action action = policy->action; 2319 const u8 *addr = policy->addr; 2320 u16 vid = policy->vid; 2321 u8 state; 2322 int err; 2323 int id; 2324 2325 if (!chip->info->ops->port_set_policy) 2326 return -EOPNOTSUPP; 2327 2328 switch (mapping) { 2329 case MV88E6XXX_POLICY_MAPPING_DA: 2330 case MV88E6XXX_POLICY_MAPPING_SA: 2331 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2332 state = 0; /* Dissociate the port and address */ 2333 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2334 is_multicast_ether_addr(addr)) 2335 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2336 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2337 is_unicast_ether_addr(addr)) 2338 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2339 else 2340 return -EOPNOTSUPP; 2341 2342 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2343 state); 2344 if (err) 2345 return err; 2346 break; 2347 default: 2348 return -EOPNOTSUPP; 2349 } 2350 2351 /* Skip the port's policy clearing if the mapping is still in use */ 2352 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2353 idr_for_each_entry(&chip->policies, policy, id) 2354 if (policy->port == port && 2355 policy->mapping == mapping && 2356 policy->action != action) 2357 return 0; 2358 2359 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2360 } 2361 2362 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2363 struct ethtool_rx_flow_spec *fs) 2364 { 2365 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2366 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2367 enum mv88e6xxx_policy_mapping mapping; 2368 enum mv88e6xxx_policy_action action; 2369 struct mv88e6xxx_policy *policy; 2370 u16 vid = 0; 2371 u8 *addr; 2372 int err; 2373 int id; 2374 2375 if (fs->location != RX_CLS_LOC_ANY) 2376 return -EINVAL; 2377 2378 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2379 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2380 else 2381 return -EOPNOTSUPP; 2382 2383 switch (fs->flow_type & ~FLOW_EXT) { 2384 case ETHER_FLOW: 2385 if (!is_zero_ether_addr(mac_mask->h_dest) && 2386 is_zero_ether_addr(mac_mask->h_source)) { 2387 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2388 addr = mac_entry->h_dest; 2389 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2390 !is_zero_ether_addr(mac_mask->h_source)) { 2391 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2392 addr = mac_entry->h_source; 2393 } else { 2394 /* Cannot support DA and SA mapping in the same rule */ 2395 return -EOPNOTSUPP; 2396 } 2397 break; 2398 default: 2399 return -EOPNOTSUPP; 2400 } 2401 2402 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2403 if (fs->m_ext.vlan_tci != htons(0xffff)) 2404 return -EOPNOTSUPP; 2405 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2406 } 2407 2408 idr_for_each_entry(&chip->policies, policy, id) { 2409 if (policy->port == port && policy->mapping == mapping && 2410 policy->action == action && policy->vid == vid && 2411 ether_addr_equal(policy->addr, addr)) 2412 return -EEXIST; 2413 } 2414 2415 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2416 if (!policy) 2417 return -ENOMEM; 2418 2419 fs->location = 0; 2420 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2421 GFP_KERNEL); 2422 if (err) { 2423 devm_kfree(chip->dev, policy); 2424 return err; 2425 } 2426 2427 memcpy(&policy->fs, fs, sizeof(*fs)); 2428 ether_addr_copy(policy->addr, addr); 2429 policy->mapping = mapping; 2430 policy->action = action; 2431 policy->port = port; 2432 policy->vid = vid; 2433 2434 err = mv88e6xxx_policy_apply(chip, port, policy); 2435 if (err) { 2436 idr_remove(&chip->policies, fs->location); 2437 devm_kfree(chip->dev, policy); 2438 return err; 2439 } 2440 2441 return 0; 2442 } 2443 2444 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2445 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2446 { 2447 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2448 struct mv88e6xxx_chip *chip = ds->priv; 2449 struct mv88e6xxx_policy *policy; 2450 int err; 2451 int id; 2452 2453 mv88e6xxx_reg_lock(chip); 2454 2455 switch (rxnfc->cmd) { 2456 case ETHTOOL_GRXCLSRLCNT: 2457 rxnfc->data = 0; 2458 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2459 rxnfc->rule_cnt = 0; 2460 idr_for_each_entry(&chip->policies, policy, id) 2461 if (policy->port == port) 2462 rxnfc->rule_cnt++; 2463 err = 0; 2464 break; 2465 case ETHTOOL_GRXCLSRULE: 2466 err = -ENOENT; 2467 policy = idr_find(&chip->policies, fs->location); 2468 if (policy) { 2469 memcpy(fs, &policy->fs, sizeof(*fs)); 2470 err = 0; 2471 } 2472 break; 2473 case ETHTOOL_GRXCLSRLALL: 2474 rxnfc->data = 0; 2475 rxnfc->rule_cnt = 0; 2476 idr_for_each_entry(&chip->policies, policy, id) 2477 if (policy->port == port) 2478 rule_locs[rxnfc->rule_cnt++] = id; 2479 err = 0; 2480 break; 2481 default: 2482 err = -EOPNOTSUPP; 2483 break; 2484 } 2485 2486 mv88e6xxx_reg_unlock(chip); 2487 2488 return err; 2489 } 2490 2491 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2492 struct ethtool_rxnfc *rxnfc) 2493 { 2494 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2495 struct mv88e6xxx_chip *chip = ds->priv; 2496 struct mv88e6xxx_policy *policy; 2497 int err; 2498 2499 mv88e6xxx_reg_lock(chip); 2500 2501 switch (rxnfc->cmd) { 2502 case ETHTOOL_SRXCLSRLINS: 2503 err = mv88e6xxx_policy_insert(chip, port, fs); 2504 break; 2505 case ETHTOOL_SRXCLSRLDEL: 2506 err = -ENOENT; 2507 policy = idr_remove(&chip->policies, fs->location); 2508 if (policy) { 2509 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2510 err = mv88e6xxx_policy_apply(chip, port, policy); 2511 devm_kfree(chip->dev, policy); 2512 } 2513 break; 2514 default: 2515 err = -EOPNOTSUPP; 2516 break; 2517 } 2518 2519 mv88e6xxx_reg_unlock(chip); 2520 2521 return err; 2522 } 2523 2524 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2525 u16 vid) 2526 { 2527 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2528 u8 broadcast[ETH_ALEN]; 2529 2530 eth_broadcast_addr(broadcast); 2531 2532 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2533 } 2534 2535 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2536 { 2537 int port; 2538 int err; 2539 2540 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2541 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2542 struct net_device *brport; 2543 2544 if (dsa_is_unused_port(chip->ds, port)) 2545 continue; 2546 2547 brport = dsa_port_to_bridge_port(dp); 2548 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2549 /* Skip bridged user ports where broadcast 2550 * flooding is disabled. 2551 */ 2552 continue; 2553 2554 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2555 if (err) 2556 return err; 2557 } 2558 2559 return 0; 2560 } 2561 2562 struct mv88e6xxx_port_broadcast_sync_ctx { 2563 int port; 2564 bool flood; 2565 }; 2566 2567 static int 2568 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2569 const struct mv88e6xxx_vtu_entry *vlan, 2570 void *_ctx) 2571 { 2572 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2573 u8 broadcast[ETH_ALEN]; 2574 u8 state; 2575 2576 if (ctx->flood) 2577 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2578 else 2579 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2580 2581 eth_broadcast_addr(broadcast); 2582 2583 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2584 vlan->vid, state); 2585 } 2586 2587 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2588 bool flood) 2589 { 2590 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2591 .port = port, 2592 .flood = flood, 2593 }; 2594 struct mv88e6xxx_vtu_entry vid0 = { 2595 .vid = 0, 2596 }; 2597 int err; 2598 2599 /* Update the port's private database... */ 2600 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2601 if (err) 2602 return err; 2603 2604 /* ...and the database for all VLANs. */ 2605 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2606 &ctx); 2607 } 2608 2609 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2610 u16 vid, u8 member, bool warn) 2611 { 2612 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2613 struct mv88e6xxx_vtu_entry vlan; 2614 int i, err; 2615 2616 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2617 if (err) 2618 return err; 2619 2620 if (!vlan.valid) { 2621 memset(&vlan, 0, sizeof(vlan)); 2622 2623 if (vid == MV88E6XXX_VID_STANDALONE) 2624 vlan.policy = true; 2625 2626 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2627 if (err) 2628 return err; 2629 2630 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2631 if (i == port) 2632 vlan.member[i] = member; 2633 else 2634 vlan.member[i] = non_member; 2635 2636 vlan.vid = vid; 2637 vlan.valid = true; 2638 2639 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2640 if (err) 2641 return err; 2642 2643 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2644 if (err) 2645 return err; 2646 } else if (vlan.member[port] != member) { 2647 vlan.member[port] = member; 2648 2649 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2650 if (err) 2651 return err; 2652 } else if (warn) { 2653 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2654 port, vid); 2655 } 2656 2657 return 0; 2658 } 2659 2660 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2661 const struct switchdev_obj_port_vlan *vlan, 2662 struct netlink_ext_ack *extack) 2663 { 2664 struct mv88e6xxx_chip *chip = ds->priv; 2665 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2666 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2667 struct mv88e6xxx_port *p = &chip->ports[port]; 2668 bool warn; 2669 u8 member; 2670 int err; 2671 2672 if (!vlan->vid) 2673 return 0; 2674 2675 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2676 if (err) 2677 return err; 2678 2679 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2680 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2681 else if (untagged) 2682 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2683 else 2684 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2685 2686 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2687 * and then the CPU port. Do not warn for duplicates for the CPU port. 2688 */ 2689 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2690 2691 mv88e6xxx_reg_lock(chip); 2692 2693 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2694 if (err) { 2695 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2696 vlan->vid, untagged ? 'u' : 't'); 2697 goto out; 2698 } 2699 2700 if (pvid) { 2701 p->bridge_pvid.vid = vlan->vid; 2702 p->bridge_pvid.valid = true; 2703 2704 err = mv88e6xxx_port_commit_pvid(chip, port); 2705 if (err) 2706 goto out; 2707 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2708 /* The old pvid was reinstalled as a non-pvid VLAN */ 2709 p->bridge_pvid.valid = false; 2710 2711 err = mv88e6xxx_port_commit_pvid(chip, port); 2712 if (err) 2713 goto out; 2714 } 2715 2716 out: 2717 mv88e6xxx_reg_unlock(chip); 2718 2719 return err; 2720 } 2721 2722 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2723 int port, u16 vid) 2724 { 2725 struct mv88e6xxx_vtu_entry vlan; 2726 int i, err; 2727 2728 if (!vid) 2729 return 0; 2730 2731 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2732 if (err) 2733 return err; 2734 2735 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2736 * tell switchdev that this VLAN is likely handled in software. 2737 */ 2738 if (!vlan.valid || 2739 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2740 return -EOPNOTSUPP; 2741 2742 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2743 2744 /* keep the VLAN unless all ports are excluded */ 2745 vlan.valid = false; 2746 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2747 if (vlan.member[i] != 2748 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2749 vlan.valid = true; 2750 break; 2751 } 2752 } 2753 2754 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2755 if (err) 2756 return err; 2757 2758 if (!vlan.valid) { 2759 err = mv88e6xxx_mst_put(chip, vlan.sid); 2760 if (err) 2761 return err; 2762 } 2763 2764 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2765 } 2766 2767 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2768 const struct switchdev_obj_port_vlan *vlan) 2769 { 2770 struct mv88e6xxx_chip *chip = ds->priv; 2771 struct mv88e6xxx_port *p = &chip->ports[port]; 2772 int err = 0; 2773 u16 pvid; 2774 2775 if (!mv88e6xxx_max_vid(chip)) 2776 return -EOPNOTSUPP; 2777 2778 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2779 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2780 * switchdev workqueue to ensure that all FDB entries are deleted 2781 * before we remove the VLAN. 2782 */ 2783 dsa_flush_workqueue(); 2784 2785 mv88e6xxx_reg_lock(chip); 2786 2787 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2788 if (err) 2789 goto unlock; 2790 2791 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2792 if (err) 2793 goto unlock; 2794 2795 if (vlan->vid == pvid) { 2796 p->bridge_pvid.valid = false; 2797 2798 err = mv88e6xxx_port_commit_pvid(chip, port); 2799 if (err) 2800 goto unlock; 2801 } 2802 2803 unlock: 2804 mv88e6xxx_reg_unlock(chip); 2805 2806 return err; 2807 } 2808 2809 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2810 { 2811 struct mv88e6xxx_chip *chip = ds->priv; 2812 struct mv88e6xxx_vtu_entry vlan; 2813 int err; 2814 2815 mv88e6xxx_reg_lock(chip); 2816 2817 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2818 if (err) 2819 goto unlock; 2820 2821 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2822 2823 unlock: 2824 mv88e6xxx_reg_unlock(chip); 2825 2826 return err; 2827 } 2828 2829 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2830 struct dsa_bridge bridge, 2831 const struct switchdev_vlan_msti *msti) 2832 { 2833 struct mv88e6xxx_chip *chip = ds->priv; 2834 struct mv88e6xxx_vtu_entry vlan; 2835 u8 old_sid, new_sid; 2836 int err; 2837 2838 if (!mv88e6xxx_has_stu(chip)) 2839 return -EOPNOTSUPP; 2840 2841 mv88e6xxx_reg_lock(chip); 2842 2843 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2844 if (err) 2845 goto unlock; 2846 2847 if (!vlan.valid) { 2848 err = -EINVAL; 2849 goto unlock; 2850 } 2851 2852 old_sid = vlan.sid; 2853 2854 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2855 if (err) 2856 goto unlock; 2857 2858 if (new_sid != old_sid) { 2859 vlan.sid = new_sid; 2860 2861 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2862 if (err) { 2863 mv88e6xxx_mst_put(chip, new_sid); 2864 goto unlock; 2865 } 2866 } 2867 2868 err = mv88e6xxx_mst_put(chip, old_sid); 2869 2870 unlock: 2871 mv88e6xxx_reg_unlock(chip); 2872 return err; 2873 } 2874 2875 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2876 const unsigned char *addr, u16 vid, 2877 struct dsa_db db) 2878 { 2879 struct mv88e6xxx_chip *chip = ds->priv; 2880 int err; 2881 2882 mv88e6xxx_reg_lock(chip); 2883 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2884 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2885 mv88e6xxx_reg_unlock(chip); 2886 2887 return err; 2888 } 2889 2890 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2891 const unsigned char *addr, u16 vid, 2892 struct dsa_db db) 2893 { 2894 struct mv88e6xxx_chip *chip = ds->priv; 2895 int err; 2896 2897 mv88e6xxx_reg_lock(chip); 2898 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2899 mv88e6xxx_reg_unlock(chip); 2900 2901 return err; 2902 } 2903 2904 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2905 u16 fid, u16 vid, int port, 2906 dsa_fdb_dump_cb_t *cb, void *data) 2907 { 2908 struct mv88e6xxx_atu_entry addr; 2909 bool is_static; 2910 int err; 2911 2912 addr.state = 0; 2913 eth_broadcast_addr(addr.mac); 2914 2915 do { 2916 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2917 if (err) 2918 return err; 2919 2920 if (!addr.state) 2921 break; 2922 2923 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2924 continue; 2925 2926 if (!is_unicast_ether_addr(addr.mac)) 2927 continue; 2928 2929 is_static = (addr.state == 2930 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2931 err = cb(addr.mac, vid, is_static, data); 2932 if (err) 2933 return err; 2934 } while (!is_broadcast_ether_addr(addr.mac)); 2935 2936 return err; 2937 } 2938 2939 struct mv88e6xxx_port_db_dump_vlan_ctx { 2940 int port; 2941 dsa_fdb_dump_cb_t *cb; 2942 void *data; 2943 }; 2944 2945 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2946 const struct mv88e6xxx_vtu_entry *entry, 2947 void *_data) 2948 { 2949 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2950 2951 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2952 ctx->port, ctx->cb, ctx->data); 2953 } 2954 2955 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2956 dsa_fdb_dump_cb_t *cb, void *data) 2957 { 2958 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2959 .port = port, 2960 .cb = cb, 2961 .data = data, 2962 }; 2963 u16 fid; 2964 int err; 2965 2966 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2967 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2968 if (err) 2969 return err; 2970 2971 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2972 if (err) 2973 return err; 2974 2975 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2976 } 2977 2978 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2979 dsa_fdb_dump_cb_t *cb, void *data) 2980 { 2981 struct mv88e6xxx_chip *chip = ds->priv; 2982 int err; 2983 2984 mv88e6xxx_reg_lock(chip); 2985 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2986 mv88e6xxx_reg_unlock(chip); 2987 2988 return err; 2989 } 2990 2991 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2992 struct dsa_bridge bridge) 2993 { 2994 struct dsa_switch *ds = chip->ds; 2995 struct dsa_switch_tree *dst = ds->dst; 2996 struct dsa_port *dp; 2997 int err; 2998 2999 list_for_each_entry(dp, &dst->ports, list) { 3000 if (dsa_port_offloads_bridge(dp, &bridge)) { 3001 if (dp->ds == ds) { 3002 /* This is a local bridge group member, 3003 * remap its Port VLAN Map. 3004 */ 3005 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3006 if (err) 3007 return err; 3008 } else { 3009 /* This is an external bridge group member, 3010 * remap its cross-chip Port VLAN Table entry. 3011 */ 3012 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3013 dp->index); 3014 if (err) 3015 return err; 3016 } 3017 } 3018 } 3019 3020 return 0; 3021 } 3022 3023 /* Treat the software bridge as a virtual single-port switch behind the 3024 * CPU and map in the PVT. First dst->last_switch elements are taken by 3025 * physical switches, so start from beyond that range. 3026 */ 3027 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3028 unsigned int bridge_num) 3029 { 3030 u8 dev = bridge_num + ds->dst->last_switch; 3031 struct mv88e6xxx_chip *chip = ds->priv; 3032 3033 return mv88e6xxx_pvt_map(chip, dev, 0); 3034 } 3035 3036 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3037 struct dsa_bridge bridge, 3038 bool *tx_fwd_offload, 3039 struct netlink_ext_ack *extack) 3040 { 3041 struct mv88e6xxx_chip *chip = ds->priv; 3042 int err; 3043 3044 mv88e6xxx_reg_lock(chip); 3045 3046 err = mv88e6xxx_bridge_map(chip, bridge); 3047 if (err) 3048 goto unlock; 3049 3050 err = mv88e6xxx_port_set_map_da(chip, port, true); 3051 if (err) 3052 goto unlock; 3053 3054 err = mv88e6xxx_port_commit_pvid(chip, port); 3055 if (err) 3056 goto unlock; 3057 3058 if (mv88e6xxx_has_pvt(chip)) { 3059 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3060 if (err) 3061 goto unlock; 3062 3063 *tx_fwd_offload = true; 3064 } 3065 3066 unlock: 3067 mv88e6xxx_reg_unlock(chip); 3068 3069 return err; 3070 } 3071 3072 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3073 struct dsa_bridge bridge) 3074 { 3075 struct mv88e6xxx_chip *chip = ds->priv; 3076 int err; 3077 3078 mv88e6xxx_reg_lock(chip); 3079 3080 if (bridge.tx_fwd_offload && 3081 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3082 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3083 3084 if (mv88e6xxx_bridge_map(chip, bridge) || 3085 mv88e6xxx_port_vlan_map(chip, port)) 3086 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3087 3088 err = mv88e6xxx_port_set_map_da(chip, port, false); 3089 if (err) 3090 dev_err(ds->dev, 3091 "port %d failed to restore map-DA: %pe\n", 3092 port, ERR_PTR(err)); 3093 3094 err = mv88e6xxx_port_commit_pvid(chip, port); 3095 if (err) 3096 dev_err(ds->dev, 3097 "port %d failed to restore standalone pvid: %pe\n", 3098 port, ERR_PTR(err)); 3099 3100 mv88e6xxx_reg_unlock(chip); 3101 } 3102 3103 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3104 int tree_index, int sw_index, 3105 int port, struct dsa_bridge bridge, 3106 struct netlink_ext_ack *extack) 3107 { 3108 struct mv88e6xxx_chip *chip = ds->priv; 3109 int err; 3110 3111 if (tree_index != ds->dst->index) 3112 return 0; 3113 3114 mv88e6xxx_reg_lock(chip); 3115 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3116 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3117 mv88e6xxx_reg_unlock(chip); 3118 3119 return err; 3120 } 3121 3122 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3123 int tree_index, int sw_index, 3124 int port, struct dsa_bridge bridge) 3125 { 3126 struct mv88e6xxx_chip *chip = ds->priv; 3127 3128 if (tree_index != ds->dst->index) 3129 return; 3130 3131 mv88e6xxx_reg_lock(chip); 3132 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3133 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3134 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3135 mv88e6xxx_reg_unlock(chip); 3136 } 3137 3138 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3139 { 3140 if (chip->info->ops->reset) 3141 return chip->info->ops->reset(chip); 3142 3143 return 0; 3144 } 3145 3146 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3147 { 3148 struct gpio_desc *gpiod = chip->reset; 3149 3150 /* If there is a GPIO connected to the reset pin, toggle it */ 3151 if (gpiod) { 3152 /* If the switch has just been reset and not yet completed 3153 * loading EEPROM, the reset may interrupt the I2C transaction 3154 * mid-byte, causing the first EEPROM read after the reset 3155 * from the wrong location resulting in the switch booting 3156 * to wrong mode and inoperable. 3157 */ 3158 if (chip->info->ops->get_eeprom) 3159 mv88e6xxx_g2_eeprom_wait(chip); 3160 3161 gpiod_set_value_cansleep(gpiod, 1); 3162 usleep_range(10000, 20000); 3163 gpiod_set_value_cansleep(gpiod, 0); 3164 usleep_range(10000, 20000); 3165 3166 if (chip->info->ops->get_eeprom) 3167 mv88e6xxx_g2_eeprom_wait(chip); 3168 } 3169 } 3170 3171 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3172 { 3173 int i, err; 3174 3175 /* Set all ports to the Disabled state */ 3176 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3177 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3178 if (err) 3179 return err; 3180 } 3181 3182 /* Wait for transmit queues to drain, 3183 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3184 */ 3185 usleep_range(2000, 4000); 3186 3187 return 0; 3188 } 3189 3190 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3191 { 3192 int err; 3193 3194 err = mv88e6xxx_disable_ports(chip); 3195 if (err) 3196 return err; 3197 3198 mv88e6xxx_hardware_reset(chip); 3199 3200 return mv88e6xxx_software_reset(chip); 3201 } 3202 3203 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3204 enum mv88e6xxx_frame_mode frame, 3205 enum mv88e6xxx_egress_mode egress, u16 etype) 3206 { 3207 int err; 3208 3209 if (!chip->info->ops->port_set_frame_mode) 3210 return -EOPNOTSUPP; 3211 3212 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3213 if (err) 3214 return err; 3215 3216 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3217 if (err) 3218 return err; 3219 3220 if (chip->info->ops->port_set_ether_type) 3221 return chip->info->ops->port_set_ether_type(chip, port, etype); 3222 3223 return 0; 3224 } 3225 3226 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3227 { 3228 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3229 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3230 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3231 } 3232 3233 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3234 { 3235 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3236 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3237 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3238 } 3239 3240 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3241 { 3242 return mv88e6xxx_set_port_mode(chip, port, 3243 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3244 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3245 ETH_P_EDSA); 3246 } 3247 3248 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3249 { 3250 if (dsa_is_dsa_port(chip->ds, port)) 3251 return mv88e6xxx_set_port_mode_dsa(chip, port); 3252 3253 if (dsa_is_user_port(chip->ds, port)) 3254 return mv88e6xxx_set_port_mode_normal(chip, port); 3255 3256 /* Setup CPU port mode depending on its supported tag format */ 3257 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3258 return mv88e6xxx_set_port_mode_dsa(chip, port); 3259 3260 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3261 return mv88e6xxx_set_port_mode_edsa(chip, port); 3262 3263 return -EINVAL; 3264 } 3265 3266 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3267 { 3268 bool message = dsa_is_dsa_port(chip->ds, port); 3269 3270 return mv88e6xxx_port_set_message_port(chip, port, message); 3271 } 3272 3273 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3274 { 3275 int err; 3276 3277 if (chip->info->ops->port_set_ucast_flood) { 3278 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3279 if (err) 3280 return err; 3281 } 3282 if (chip->info->ops->port_set_mcast_flood) { 3283 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3284 if (err) 3285 return err; 3286 } 3287 3288 return 0; 3289 } 3290 3291 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3292 enum mv88e6xxx_egress_direction direction, 3293 int port) 3294 { 3295 int err; 3296 3297 if (!chip->info->ops->set_egress_port) 3298 return -EOPNOTSUPP; 3299 3300 err = chip->info->ops->set_egress_port(chip, direction, port); 3301 if (err) 3302 return err; 3303 3304 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3305 chip->ingress_dest_port = port; 3306 else 3307 chip->egress_dest_port = port; 3308 3309 return 0; 3310 } 3311 3312 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3313 { 3314 struct dsa_switch *ds = chip->ds; 3315 int upstream_port; 3316 int err; 3317 3318 upstream_port = dsa_upstream_port(ds, port); 3319 if (chip->info->ops->port_set_upstream_port) { 3320 err = chip->info->ops->port_set_upstream_port(chip, port, 3321 upstream_port); 3322 if (err) 3323 return err; 3324 } 3325 3326 if (port == upstream_port) { 3327 if (chip->info->ops->set_cpu_port) { 3328 err = chip->info->ops->set_cpu_port(chip, 3329 upstream_port); 3330 if (err) 3331 return err; 3332 } 3333 3334 err = mv88e6xxx_set_egress_port(chip, 3335 MV88E6XXX_EGRESS_DIR_INGRESS, 3336 upstream_port); 3337 if (err && err != -EOPNOTSUPP) 3338 return err; 3339 3340 err = mv88e6xxx_set_egress_port(chip, 3341 MV88E6XXX_EGRESS_DIR_EGRESS, 3342 upstream_port); 3343 if (err && err != -EOPNOTSUPP) 3344 return err; 3345 } 3346 3347 return 0; 3348 } 3349 3350 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3351 { 3352 struct device_node *phy_handle = NULL; 3353 struct dsa_switch *ds = chip->ds; 3354 struct dsa_port *dp; 3355 int tx_amp; 3356 int err; 3357 u16 reg; 3358 3359 chip->ports[port].chip = chip; 3360 chip->ports[port].port = port; 3361 3362 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3363 SPEED_UNFORCED, DUPLEX_UNFORCED, 3364 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3365 if (err) 3366 return err; 3367 3368 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3369 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3370 * tunneling, determine priority by looking at 802.1p and IP 3371 * priority fields (IP prio has precedence), and set STP state 3372 * to Forwarding. 3373 * 3374 * If this is the CPU link, use DSA or EDSA tagging depending 3375 * on which tagging mode was configured. 3376 * 3377 * If this is a link to another switch, use DSA tagging mode. 3378 * 3379 * If this is the upstream port for this switch, enable 3380 * forwarding of unknown unicasts and multicasts. 3381 */ 3382 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3383 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3384 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3385 * by a USER port to the CPU port to allow snooping. 3386 */ 3387 if (dsa_is_user_port(ds, port)) 3388 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3389 3390 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3391 if (err) 3392 return err; 3393 3394 err = mv88e6xxx_setup_port_mode(chip, port); 3395 if (err) 3396 return err; 3397 3398 err = mv88e6xxx_setup_egress_floods(chip, port); 3399 if (err) 3400 return err; 3401 3402 /* Port Control 2: don't force a good FCS, set the MTU size to 3403 * 10222 bytes, disable 802.1q tags checking, don't discard 3404 * tagged or untagged frames on this port, skip destination 3405 * address lookup on user ports, disable ARP mirroring and don't 3406 * send a copy of all transmitted/received frames on this port 3407 * to the CPU. 3408 */ 3409 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3410 if (err) 3411 return err; 3412 3413 err = mv88e6xxx_setup_upstream_port(chip, port); 3414 if (err) 3415 return err; 3416 3417 /* On chips that support it, set all downstream DSA ports' 3418 * VLAN policy to TRAP. In combination with loading 3419 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3420 * provides a better isolation barrier between standalone 3421 * ports, as the ATU is bypassed on any intermediate switches 3422 * between the incoming port and the CPU. 3423 */ 3424 if (dsa_is_downstream_port(ds, port) && 3425 chip->info->ops->port_set_policy) { 3426 err = chip->info->ops->port_set_policy(chip, port, 3427 MV88E6XXX_POLICY_MAPPING_VTU, 3428 MV88E6XXX_POLICY_ACTION_TRAP); 3429 if (err) 3430 return err; 3431 } 3432 3433 /* User ports start out in standalone mode and 802.1Q is 3434 * therefore disabled. On DSA ports, all valid VIDs are always 3435 * loaded in the VTU - therefore, enable 802.1Q in order to take 3436 * advantage of VLAN policy on chips that supports it. 3437 */ 3438 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3439 dsa_is_user_port(ds, port) ? 3440 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3441 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3442 if (err) 3443 return err; 3444 3445 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3446 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3447 * the first free FID. This will be used as the private PVID for 3448 * unbridged ports. Shared (DSA and CPU) ports must also be 3449 * members of this VID, in order to trap all frames assigned to 3450 * it to the CPU. 3451 */ 3452 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3453 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3454 false); 3455 if (err) 3456 return err; 3457 3458 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3459 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3460 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3461 * as the private PVID on ports under a VLAN-unaware bridge. 3462 * Shared (DSA and CPU) ports must also be members of it, to translate 3463 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3464 * relying on their port default FID. 3465 */ 3466 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3467 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3468 false); 3469 if (err) 3470 return err; 3471 3472 if (chip->info->ops->port_set_jumbo_size) { 3473 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3474 if (err) 3475 return err; 3476 } 3477 3478 /* Port Association Vector: disable automatic address learning 3479 * on all user ports since they start out in standalone 3480 * mode. When joining a bridge, learning will be configured to 3481 * match the bridge port settings. Enable learning on all 3482 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3483 * learning process. 3484 * 3485 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3486 * and RefreshLocked. I.e. setup standard automatic learning. 3487 */ 3488 if (dsa_is_user_port(ds, port)) 3489 reg = 0; 3490 else 3491 reg = 1 << port; 3492 3493 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3494 reg); 3495 if (err) 3496 return err; 3497 3498 /* Egress rate control 2: disable egress rate control. */ 3499 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3500 0x0000); 3501 if (err) 3502 return err; 3503 3504 if (chip->info->ops->port_pause_limit) { 3505 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3506 if (err) 3507 return err; 3508 } 3509 3510 if (chip->info->ops->port_disable_learn_limit) { 3511 err = chip->info->ops->port_disable_learn_limit(chip, port); 3512 if (err) 3513 return err; 3514 } 3515 3516 if (chip->info->ops->port_disable_pri_override) { 3517 err = chip->info->ops->port_disable_pri_override(chip, port); 3518 if (err) 3519 return err; 3520 } 3521 3522 if (chip->info->ops->port_tag_remap) { 3523 err = chip->info->ops->port_tag_remap(chip, port); 3524 if (err) 3525 return err; 3526 } 3527 3528 if (chip->info->ops->port_egress_rate_limiting) { 3529 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3530 if (err) 3531 return err; 3532 } 3533 3534 if (chip->info->ops->port_setup_message_port) { 3535 err = chip->info->ops->port_setup_message_port(chip, port); 3536 if (err) 3537 return err; 3538 } 3539 3540 if (chip->info->ops->serdes_set_tx_amplitude) { 3541 dp = dsa_to_port(ds, port); 3542 if (dp) 3543 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3544 3545 if (phy_handle && !of_property_read_u32(phy_handle, 3546 "tx-p2p-microvolt", 3547 &tx_amp)) 3548 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3549 port, tx_amp); 3550 if (phy_handle) { 3551 of_node_put(phy_handle); 3552 if (err) 3553 return err; 3554 } 3555 } 3556 3557 /* Port based VLAN map: give each port the same default address 3558 * database, and allow bidirectional communication between the 3559 * CPU and DSA port(s), and the other ports. 3560 */ 3561 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3562 if (err) 3563 return err; 3564 3565 err = mv88e6xxx_port_vlan_map(chip, port); 3566 if (err) 3567 return err; 3568 3569 /* Default VLAN ID and priority: don't set a default VLAN 3570 * ID, and set the default packet priority to zero. 3571 */ 3572 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3573 } 3574 3575 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3576 { 3577 struct mv88e6xxx_chip *chip = ds->priv; 3578 3579 if (chip->info->ops->port_set_jumbo_size) 3580 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3581 else if (chip->info->ops->set_max_frame_size) 3582 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3583 return ETH_DATA_LEN; 3584 } 3585 3586 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3587 { 3588 struct mv88e6xxx_chip *chip = ds->priv; 3589 int ret = 0; 3590 3591 /* For families where we don't know how to alter the MTU, 3592 * just accept any value up to ETH_DATA_LEN 3593 */ 3594 if (!chip->info->ops->port_set_jumbo_size && 3595 !chip->info->ops->set_max_frame_size) { 3596 if (new_mtu > ETH_DATA_LEN) 3597 return -EINVAL; 3598 3599 return 0; 3600 } 3601 3602 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3603 new_mtu += EDSA_HLEN; 3604 3605 mv88e6xxx_reg_lock(chip); 3606 if (chip->info->ops->port_set_jumbo_size) 3607 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3608 else if (chip->info->ops->set_max_frame_size) 3609 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3610 mv88e6xxx_reg_unlock(chip); 3611 3612 return ret; 3613 } 3614 3615 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3616 unsigned int ageing_time) 3617 { 3618 struct mv88e6xxx_chip *chip = ds->priv; 3619 int err; 3620 3621 mv88e6xxx_reg_lock(chip); 3622 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3623 mv88e6xxx_reg_unlock(chip); 3624 3625 return err; 3626 } 3627 3628 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3629 { 3630 int err; 3631 3632 /* Initialize the statistics unit */ 3633 if (chip->info->ops->stats_set_histogram) { 3634 err = chip->info->ops->stats_set_histogram(chip); 3635 if (err) 3636 return err; 3637 } 3638 3639 return mv88e6xxx_g1_stats_clear(chip); 3640 } 3641 3642 /* Check if the errata has already been applied. */ 3643 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3644 { 3645 int port; 3646 int err; 3647 u16 val; 3648 3649 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3650 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3651 if (err) { 3652 dev_err(chip->dev, 3653 "Error reading hidden register: %d\n", err); 3654 return false; 3655 } 3656 if (val != 0x01c0) 3657 return false; 3658 } 3659 3660 return true; 3661 } 3662 3663 /* The 6390 copper ports have an errata which require poking magic 3664 * values into undocumented hidden registers and then performing a 3665 * software reset. 3666 */ 3667 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3668 { 3669 int port; 3670 int err; 3671 3672 if (mv88e6390_setup_errata_applied(chip)) 3673 return 0; 3674 3675 /* Set the ports into blocking mode */ 3676 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3677 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3678 if (err) 3679 return err; 3680 } 3681 3682 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3683 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3684 if (err) 3685 return err; 3686 } 3687 3688 return mv88e6xxx_software_reset(chip); 3689 } 3690 3691 /* prod_id for switch families which do not have a PHY model number */ 3692 static const u16 family_prod_id_table[] = { 3693 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3694 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3695 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3696 }; 3697 3698 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3699 { 3700 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3701 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3702 u16 prod_id; 3703 u16 val; 3704 int err; 3705 3706 if (!chip->info->ops->phy_read) 3707 return -EOPNOTSUPP; 3708 3709 mv88e6xxx_reg_lock(chip); 3710 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3711 mv88e6xxx_reg_unlock(chip); 3712 3713 /* Some internal PHYs don't have a model number. */ 3714 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3715 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3716 prod_id = family_prod_id_table[chip->info->family]; 3717 if (prod_id) 3718 val |= prod_id >> 4; 3719 } 3720 3721 return err ? err : val; 3722 } 3723 3724 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3725 int reg) 3726 { 3727 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3728 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3729 u16 val; 3730 int err; 3731 3732 if (!chip->info->ops->phy_read_c45) 3733 return -ENODEV; 3734 3735 mv88e6xxx_reg_lock(chip); 3736 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3737 mv88e6xxx_reg_unlock(chip); 3738 3739 return err ? err : val; 3740 } 3741 3742 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3743 { 3744 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3745 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3746 int err; 3747 3748 if (!chip->info->ops->phy_write) 3749 return -EOPNOTSUPP; 3750 3751 mv88e6xxx_reg_lock(chip); 3752 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3753 mv88e6xxx_reg_unlock(chip); 3754 3755 return err; 3756 } 3757 3758 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3759 int reg, u16 val) 3760 { 3761 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3762 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3763 int err; 3764 3765 if (!chip->info->ops->phy_write_c45) 3766 return -EOPNOTSUPP; 3767 3768 mv88e6xxx_reg_lock(chip); 3769 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3770 mv88e6xxx_reg_unlock(chip); 3771 3772 return err; 3773 } 3774 3775 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3776 struct device_node *np, 3777 bool external) 3778 { 3779 static int index; 3780 struct mv88e6xxx_mdio_bus *mdio_bus; 3781 struct mii_bus *bus; 3782 int err; 3783 3784 if (external) { 3785 mv88e6xxx_reg_lock(chip); 3786 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3787 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3788 else 3789 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3790 mv88e6xxx_reg_unlock(chip); 3791 3792 if (err) 3793 return err; 3794 } 3795 3796 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3797 if (!bus) 3798 return -ENOMEM; 3799 3800 mdio_bus = bus->priv; 3801 mdio_bus->bus = bus; 3802 mdio_bus->chip = chip; 3803 INIT_LIST_HEAD(&mdio_bus->list); 3804 mdio_bus->external = external; 3805 3806 if (np) { 3807 bus->name = np->full_name; 3808 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3809 } else { 3810 bus->name = "mv88e6xxx SMI"; 3811 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3812 } 3813 3814 bus->read = mv88e6xxx_mdio_read; 3815 bus->write = mv88e6xxx_mdio_write; 3816 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3817 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3818 bus->parent = chip->dev; 3819 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3820 mv88e6xxx_num_ports(chip) - 1, 3821 chip->info->phy_base_addr); 3822 3823 if (!external) { 3824 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3825 if (err) 3826 goto out; 3827 } 3828 3829 err = of_mdiobus_register(bus, np); 3830 if (err) { 3831 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3832 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3833 goto out; 3834 } 3835 3836 if (external) 3837 list_add_tail(&mdio_bus->list, &chip->mdios); 3838 else 3839 list_add(&mdio_bus->list, &chip->mdios); 3840 3841 return 0; 3842 3843 out: 3844 mdiobus_free(bus); 3845 return err; 3846 } 3847 3848 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3849 3850 { 3851 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3852 struct mii_bus *bus; 3853 3854 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3855 bus = mdio_bus->bus; 3856 3857 if (!mdio_bus->external) 3858 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3859 3860 mdiobus_unregister(bus); 3861 mdiobus_free(bus); 3862 } 3863 } 3864 3865 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3866 { 3867 struct device_node *np = chip->dev->of_node; 3868 struct device_node *child; 3869 int err; 3870 3871 /* Always register one mdio bus for the internal/default mdio 3872 * bus. This maybe represented in the device tree, but is 3873 * optional. 3874 */ 3875 child = of_get_child_by_name(np, "mdio"); 3876 err = mv88e6xxx_mdio_register(chip, child, false); 3877 of_node_put(child); 3878 if (err) 3879 return err; 3880 3881 /* Walk the device tree, and see if there are any other nodes 3882 * which say they are compatible with the external mdio 3883 * bus. 3884 */ 3885 for_each_available_child_of_node(np, child) { 3886 if (of_device_is_compatible( 3887 child, "marvell,mv88e6xxx-mdio-external")) { 3888 err = mv88e6xxx_mdio_register(chip, child, true); 3889 if (err) { 3890 mv88e6xxx_mdios_unregister(chip); 3891 of_node_put(child); 3892 return err; 3893 } 3894 } 3895 } 3896 3897 return 0; 3898 } 3899 3900 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3901 { 3902 struct mv88e6xxx_chip *chip = ds->priv; 3903 3904 mv88e6xxx_teardown_devlink_params(ds); 3905 dsa_devlink_resources_unregister(ds); 3906 mv88e6xxx_teardown_devlink_regions_global(ds); 3907 mv88e6xxx_mdios_unregister(chip); 3908 } 3909 3910 static int mv88e6xxx_setup(struct dsa_switch *ds) 3911 { 3912 struct mv88e6xxx_chip *chip = ds->priv; 3913 u8 cmode; 3914 int err; 3915 int i; 3916 3917 err = mv88e6xxx_mdios_register(chip); 3918 if (err) 3919 return err; 3920 3921 chip->ds = ds; 3922 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3923 3924 /* Since virtual bridges are mapped in the PVT, the number we support 3925 * depends on the physical switch topology. We need to let DSA figure 3926 * that out and therefore we cannot set this at dsa_register_switch() 3927 * time. 3928 */ 3929 if (mv88e6xxx_has_pvt(chip)) 3930 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3931 ds->dst->last_switch - 1; 3932 3933 mv88e6xxx_reg_lock(chip); 3934 3935 if (chip->info->ops->setup_errata) { 3936 err = chip->info->ops->setup_errata(chip); 3937 if (err) 3938 goto unlock; 3939 } 3940 3941 /* Cache the cmode of each port. */ 3942 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3943 if (chip->info->ops->port_get_cmode) { 3944 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3945 if (err) 3946 goto unlock; 3947 3948 chip->ports[i].cmode = cmode; 3949 } 3950 } 3951 3952 err = mv88e6xxx_vtu_setup(chip); 3953 if (err) 3954 goto unlock; 3955 3956 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3957 * VTU, thereby also flushing the STU). 3958 */ 3959 err = mv88e6xxx_stu_setup(chip); 3960 if (err) 3961 goto unlock; 3962 3963 /* Setup Switch Port Registers */ 3964 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3965 if (dsa_is_unused_port(ds, i)) 3966 continue; 3967 3968 /* Prevent the use of an invalid port. */ 3969 if (mv88e6xxx_is_invalid_port(chip, i)) { 3970 dev_err(chip->dev, "port %d is invalid\n", i); 3971 err = -EINVAL; 3972 goto unlock; 3973 } 3974 3975 err = mv88e6xxx_setup_port(chip, i); 3976 if (err) 3977 goto unlock; 3978 } 3979 3980 err = mv88e6xxx_irl_setup(chip); 3981 if (err) 3982 goto unlock; 3983 3984 err = mv88e6xxx_mac_setup(chip); 3985 if (err) 3986 goto unlock; 3987 3988 err = mv88e6xxx_phy_setup(chip); 3989 if (err) 3990 goto unlock; 3991 3992 err = mv88e6xxx_pvt_setup(chip); 3993 if (err) 3994 goto unlock; 3995 3996 err = mv88e6xxx_atu_setup(chip); 3997 if (err) 3998 goto unlock; 3999 4000 err = mv88e6xxx_broadcast_setup(chip, 0); 4001 if (err) 4002 goto unlock; 4003 4004 err = mv88e6xxx_pot_setup(chip); 4005 if (err) 4006 goto unlock; 4007 4008 err = mv88e6xxx_rmu_setup(chip); 4009 if (err) 4010 goto unlock; 4011 4012 err = mv88e6xxx_rsvd2cpu_setup(chip); 4013 if (err) 4014 goto unlock; 4015 4016 err = mv88e6xxx_trunk_setup(chip); 4017 if (err) 4018 goto unlock; 4019 4020 err = mv88e6xxx_devmap_setup(chip); 4021 if (err) 4022 goto unlock; 4023 4024 err = mv88e6xxx_pri_setup(chip); 4025 if (err) 4026 goto unlock; 4027 4028 /* Setup PTP Hardware Clock and timestamping */ 4029 if (chip->info->ptp_support) { 4030 err = mv88e6xxx_ptp_setup(chip); 4031 if (err) 4032 goto unlock; 4033 4034 err = mv88e6xxx_hwtstamp_setup(chip); 4035 if (err) 4036 goto unlock; 4037 } 4038 4039 err = mv88e6xxx_stats_setup(chip); 4040 if (err) 4041 goto unlock; 4042 4043 unlock: 4044 mv88e6xxx_reg_unlock(chip); 4045 4046 if (err) 4047 goto out_mdios; 4048 4049 /* Have to be called without holding the register lock, since 4050 * they take the devlink lock, and we later take the locks in 4051 * the reverse order when getting/setting parameters or 4052 * resource occupancy. 4053 */ 4054 err = mv88e6xxx_setup_devlink_resources(ds); 4055 if (err) 4056 goto out_mdios; 4057 4058 err = mv88e6xxx_setup_devlink_params(ds); 4059 if (err) 4060 goto out_resources; 4061 4062 err = mv88e6xxx_setup_devlink_regions_global(ds); 4063 if (err) 4064 goto out_params; 4065 4066 return 0; 4067 4068 out_params: 4069 mv88e6xxx_teardown_devlink_params(ds); 4070 out_resources: 4071 dsa_devlink_resources_unregister(ds); 4072 out_mdios: 4073 mv88e6xxx_mdios_unregister(chip); 4074 4075 return err; 4076 } 4077 4078 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4079 { 4080 struct mv88e6xxx_chip *chip = ds->priv; 4081 int err; 4082 4083 if (chip->info->ops->pcs_ops && 4084 chip->info->ops->pcs_ops->pcs_init) { 4085 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4086 if (err) 4087 return err; 4088 } 4089 4090 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4091 } 4092 4093 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4094 { 4095 struct mv88e6xxx_chip *chip = ds->priv; 4096 4097 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4098 4099 if (chip->info->ops->pcs_ops && 4100 chip->info->ops->pcs_ops->pcs_teardown) 4101 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4102 } 4103 4104 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4105 { 4106 struct mv88e6xxx_chip *chip = ds->priv; 4107 4108 return chip->eeprom_len; 4109 } 4110 4111 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4112 struct ethtool_eeprom *eeprom, u8 *data) 4113 { 4114 struct mv88e6xxx_chip *chip = ds->priv; 4115 int err; 4116 4117 if (!chip->info->ops->get_eeprom) 4118 return -EOPNOTSUPP; 4119 4120 mv88e6xxx_reg_lock(chip); 4121 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4122 mv88e6xxx_reg_unlock(chip); 4123 4124 if (err) 4125 return err; 4126 4127 eeprom->magic = 0xc3ec4951; 4128 4129 return 0; 4130 } 4131 4132 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4133 struct ethtool_eeprom *eeprom, u8 *data) 4134 { 4135 struct mv88e6xxx_chip *chip = ds->priv; 4136 int err; 4137 4138 if (!chip->info->ops->set_eeprom) 4139 return -EOPNOTSUPP; 4140 4141 if (eeprom->magic != 0xc3ec4951) 4142 return -EINVAL; 4143 4144 mv88e6xxx_reg_lock(chip); 4145 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4146 mv88e6xxx_reg_unlock(chip); 4147 4148 return err; 4149 } 4150 4151 static const struct mv88e6xxx_ops mv88e6085_ops = { 4152 /* MV88E6XXX_FAMILY_6097 */ 4153 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4154 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4155 .irl_init_all = mv88e6352_g2_irl_init_all, 4156 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4157 .phy_read = mv88e6185_phy_ppu_read, 4158 .phy_write = mv88e6185_phy_ppu_write, 4159 .port_set_link = mv88e6xxx_port_set_link, 4160 .port_sync_link = mv88e6xxx_port_sync_link, 4161 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4162 .port_tag_remap = mv88e6095_port_tag_remap, 4163 .port_set_policy = mv88e6352_port_set_policy, 4164 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4165 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4166 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4167 .port_set_ether_type = mv88e6351_port_set_ether_type, 4168 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4169 .port_pause_limit = mv88e6097_port_pause_limit, 4170 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4171 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4172 .port_get_cmode = mv88e6185_port_get_cmode, 4173 .port_setup_message_port = mv88e6xxx_setup_message_port, 4174 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4175 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4176 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4177 .stats_get_strings = mv88e6095_stats_get_strings, 4178 .stats_get_stat = mv88e6095_stats_get_stat, 4179 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4180 .set_egress_port = mv88e6095_g1_set_egress_port, 4181 .watchdog_ops = &mv88e6097_watchdog_ops, 4182 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4183 .pot_clear = mv88e6xxx_g2_pot_clear, 4184 .ppu_enable = mv88e6185_g1_ppu_enable, 4185 .ppu_disable = mv88e6185_g1_ppu_disable, 4186 .reset = mv88e6185_g1_reset, 4187 .rmu_disable = mv88e6085_g1_rmu_disable, 4188 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4189 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4190 .stu_getnext = mv88e6352_g1_stu_getnext, 4191 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4192 .phylink_get_caps = mv88e6185_phylink_get_caps, 4193 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4194 }; 4195 4196 static const struct mv88e6xxx_ops mv88e6095_ops = { 4197 /* MV88E6XXX_FAMILY_6095 */ 4198 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4199 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4200 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4201 .phy_read = mv88e6185_phy_ppu_read, 4202 .phy_write = mv88e6185_phy_ppu_write, 4203 .port_set_link = mv88e6xxx_port_set_link, 4204 .port_sync_link = mv88e6185_port_sync_link, 4205 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4206 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4207 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4208 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4209 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4210 .port_get_cmode = mv88e6185_port_get_cmode, 4211 .port_setup_message_port = mv88e6xxx_setup_message_port, 4212 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4213 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4214 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4215 .stats_get_strings = mv88e6095_stats_get_strings, 4216 .stats_get_stat = mv88e6095_stats_get_stat, 4217 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4218 .ppu_enable = mv88e6185_g1_ppu_enable, 4219 .ppu_disable = mv88e6185_g1_ppu_disable, 4220 .reset = mv88e6185_g1_reset, 4221 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4222 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4223 .phylink_get_caps = mv88e6095_phylink_get_caps, 4224 .pcs_ops = &mv88e6185_pcs_ops, 4225 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4226 }; 4227 4228 static const struct mv88e6xxx_ops mv88e6097_ops = { 4229 /* MV88E6XXX_FAMILY_6097 */ 4230 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4231 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4232 .irl_init_all = mv88e6352_g2_irl_init_all, 4233 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4234 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4235 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4236 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4237 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4238 .port_set_link = mv88e6xxx_port_set_link, 4239 .port_sync_link = mv88e6185_port_sync_link, 4240 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4241 .port_tag_remap = mv88e6095_port_tag_remap, 4242 .port_set_policy = mv88e6352_port_set_policy, 4243 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4244 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4245 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4246 .port_set_ether_type = mv88e6351_port_set_ether_type, 4247 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4248 .port_pause_limit = mv88e6097_port_pause_limit, 4249 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4250 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4251 .port_get_cmode = mv88e6185_port_get_cmode, 4252 .port_setup_message_port = mv88e6xxx_setup_message_port, 4253 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4254 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4255 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4256 .stats_get_strings = mv88e6095_stats_get_strings, 4257 .stats_get_stat = mv88e6095_stats_get_stat, 4258 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4259 .set_egress_port = mv88e6095_g1_set_egress_port, 4260 .watchdog_ops = &mv88e6097_watchdog_ops, 4261 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4262 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4263 .pot_clear = mv88e6xxx_g2_pot_clear, 4264 .reset = mv88e6352_g1_reset, 4265 .rmu_disable = mv88e6085_g1_rmu_disable, 4266 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4267 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4268 .phylink_get_caps = mv88e6095_phylink_get_caps, 4269 .pcs_ops = &mv88e6185_pcs_ops, 4270 .stu_getnext = mv88e6352_g1_stu_getnext, 4271 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4272 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4273 }; 4274 4275 static const struct mv88e6xxx_ops mv88e6123_ops = { 4276 /* MV88E6XXX_FAMILY_6165 */ 4277 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4278 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4279 .irl_init_all = mv88e6352_g2_irl_init_all, 4280 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4281 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4282 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4283 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4284 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4285 .port_set_link = mv88e6xxx_port_set_link, 4286 .port_sync_link = mv88e6xxx_port_sync_link, 4287 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4288 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4289 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4290 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4291 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4292 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4293 .port_get_cmode = mv88e6185_port_get_cmode, 4294 .port_setup_message_port = mv88e6xxx_setup_message_port, 4295 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4296 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4297 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4298 .stats_get_strings = mv88e6095_stats_get_strings, 4299 .stats_get_stat = mv88e6095_stats_get_stat, 4300 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4301 .set_egress_port = mv88e6095_g1_set_egress_port, 4302 .watchdog_ops = &mv88e6097_watchdog_ops, 4303 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4304 .pot_clear = mv88e6xxx_g2_pot_clear, 4305 .reset = mv88e6352_g1_reset, 4306 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4307 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4308 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4309 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4310 .stu_getnext = mv88e6352_g1_stu_getnext, 4311 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4312 .phylink_get_caps = mv88e6185_phylink_get_caps, 4313 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4314 }; 4315 4316 static const struct mv88e6xxx_ops mv88e6131_ops = { 4317 /* MV88E6XXX_FAMILY_6185 */ 4318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4319 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4320 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4321 .phy_read = mv88e6185_phy_ppu_read, 4322 .phy_write = mv88e6185_phy_ppu_write, 4323 .port_set_link = mv88e6xxx_port_set_link, 4324 .port_sync_link = mv88e6xxx_port_sync_link, 4325 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4326 .port_tag_remap = mv88e6095_port_tag_remap, 4327 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4328 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4329 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4330 .port_set_ether_type = mv88e6351_port_set_ether_type, 4331 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4332 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4334 .port_pause_limit = mv88e6097_port_pause_limit, 4335 .port_set_pause = mv88e6185_port_set_pause, 4336 .port_get_cmode = mv88e6185_port_get_cmode, 4337 .port_setup_message_port = mv88e6xxx_setup_message_port, 4338 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4339 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4340 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4341 .stats_get_strings = mv88e6095_stats_get_strings, 4342 .stats_get_stat = mv88e6095_stats_get_stat, 4343 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4344 .set_egress_port = mv88e6095_g1_set_egress_port, 4345 .watchdog_ops = &mv88e6097_watchdog_ops, 4346 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4347 .ppu_enable = mv88e6185_g1_ppu_enable, 4348 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4349 .ppu_disable = mv88e6185_g1_ppu_disable, 4350 .reset = mv88e6185_g1_reset, 4351 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4352 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4353 .phylink_get_caps = mv88e6185_phylink_get_caps, 4354 }; 4355 4356 static const struct mv88e6xxx_ops mv88e6141_ops = { 4357 /* MV88E6XXX_FAMILY_6341 */ 4358 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4359 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4360 .irl_init_all = mv88e6352_g2_irl_init_all, 4361 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4362 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4364 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4365 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4366 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4367 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4368 .port_set_link = mv88e6xxx_port_set_link, 4369 .port_sync_link = mv88e6xxx_port_sync_link, 4370 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4371 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4372 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4373 .port_tag_remap = mv88e6095_port_tag_remap, 4374 .port_set_policy = mv88e6352_port_set_policy, 4375 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4376 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4377 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4378 .port_set_ether_type = mv88e6351_port_set_ether_type, 4379 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4380 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4381 .port_pause_limit = mv88e6097_port_pause_limit, 4382 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4383 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4384 .port_get_cmode = mv88e6352_port_get_cmode, 4385 .port_set_cmode = mv88e6341_port_set_cmode, 4386 .port_setup_message_port = mv88e6xxx_setup_message_port, 4387 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4388 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4389 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4390 .stats_get_strings = mv88e6320_stats_get_strings, 4391 .stats_get_stat = mv88e6390_stats_get_stat, 4392 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4393 .set_egress_port = mv88e6390_g1_set_egress_port, 4394 .watchdog_ops = &mv88e6390_watchdog_ops, 4395 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4396 .pot_clear = mv88e6xxx_g2_pot_clear, 4397 .reset = mv88e6352_g1_reset, 4398 .rmu_disable = mv88e6390_g1_rmu_disable, 4399 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4400 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4401 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4402 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4403 .stu_getnext = mv88e6352_g1_stu_getnext, 4404 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4405 .serdes_get_lane = mv88e6341_serdes_get_lane, 4406 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4407 .gpio_ops = &mv88e6352_gpio_ops, 4408 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4409 .serdes_get_strings = mv88e6390_serdes_get_strings, 4410 .serdes_get_stats = mv88e6390_serdes_get_stats, 4411 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4412 .serdes_get_regs = mv88e6390_serdes_get_regs, 4413 .phylink_get_caps = mv88e6341_phylink_get_caps, 4414 .pcs_ops = &mv88e6390_pcs_ops, 4415 }; 4416 4417 static const struct mv88e6xxx_ops mv88e6161_ops = { 4418 /* MV88E6XXX_FAMILY_6165 */ 4419 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4420 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4421 .irl_init_all = mv88e6352_g2_irl_init_all, 4422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4423 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4424 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4425 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4426 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4427 .port_set_link = mv88e6xxx_port_set_link, 4428 .port_sync_link = mv88e6xxx_port_sync_link, 4429 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4430 .port_tag_remap = mv88e6095_port_tag_remap, 4431 .port_set_policy = mv88e6352_port_set_policy, 4432 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4433 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4434 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4435 .port_set_ether_type = mv88e6351_port_set_ether_type, 4436 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4437 .port_pause_limit = mv88e6097_port_pause_limit, 4438 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4439 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4440 .port_get_cmode = mv88e6185_port_get_cmode, 4441 .port_setup_message_port = mv88e6xxx_setup_message_port, 4442 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4443 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4444 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4445 .stats_get_strings = mv88e6095_stats_get_strings, 4446 .stats_get_stat = mv88e6095_stats_get_stat, 4447 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4448 .set_egress_port = mv88e6095_g1_set_egress_port, 4449 .watchdog_ops = &mv88e6097_watchdog_ops, 4450 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4451 .pot_clear = mv88e6xxx_g2_pot_clear, 4452 .reset = mv88e6352_g1_reset, 4453 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4454 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4455 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4456 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4457 .stu_getnext = mv88e6352_g1_stu_getnext, 4458 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4459 .avb_ops = &mv88e6165_avb_ops, 4460 .ptp_ops = &mv88e6165_ptp_ops, 4461 .phylink_get_caps = mv88e6185_phylink_get_caps, 4462 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4463 }; 4464 4465 static const struct mv88e6xxx_ops mv88e6165_ops = { 4466 /* MV88E6XXX_FAMILY_6165 */ 4467 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4468 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4469 .irl_init_all = mv88e6352_g2_irl_init_all, 4470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4471 .phy_read = mv88e6165_phy_read, 4472 .phy_write = mv88e6165_phy_write, 4473 .port_set_link = mv88e6xxx_port_set_link, 4474 .port_sync_link = mv88e6xxx_port_sync_link, 4475 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4476 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4477 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4478 .port_get_cmode = mv88e6185_port_get_cmode, 4479 .port_setup_message_port = mv88e6xxx_setup_message_port, 4480 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4481 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4482 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4483 .stats_get_strings = mv88e6095_stats_get_strings, 4484 .stats_get_stat = mv88e6095_stats_get_stat, 4485 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4486 .set_egress_port = mv88e6095_g1_set_egress_port, 4487 .watchdog_ops = &mv88e6097_watchdog_ops, 4488 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4489 .pot_clear = mv88e6xxx_g2_pot_clear, 4490 .reset = mv88e6352_g1_reset, 4491 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4492 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4493 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4494 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4495 .stu_getnext = mv88e6352_g1_stu_getnext, 4496 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4497 .avb_ops = &mv88e6165_avb_ops, 4498 .ptp_ops = &mv88e6165_ptp_ops, 4499 .phylink_get_caps = mv88e6185_phylink_get_caps, 4500 }; 4501 4502 static const struct mv88e6xxx_ops mv88e6171_ops = { 4503 /* MV88E6XXX_FAMILY_6351 */ 4504 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4505 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4506 .irl_init_all = mv88e6352_g2_irl_init_all, 4507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4508 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4509 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4510 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4511 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4512 .port_set_link = mv88e6xxx_port_set_link, 4513 .port_sync_link = mv88e6xxx_port_sync_link, 4514 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4515 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4516 .port_tag_remap = mv88e6095_port_tag_remap, 4517 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4518 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4519 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4520 .port_set_ether_type = mv88e6351_port_set_ether_type, 4521 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4522 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4523 .port_pause_limit = mv88e6097_port_pause_limit, 4524 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4525 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4526 .port_get_cmode = mv88e6352_port_get_cmode, 4527 .port_setup_message_port = mv88e6xxx_setup_message_port, 4528 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4529 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4530 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4531 .stats_get_strings = mv88e6095_stats_get_strings, 4532 .stats_get_stat = mv88e6095_stats_get_stat, 4533 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4534 .set_egress_port = mv88e6095_g1_set_egress_port, 4535 .watchdog_ops = &mv88e6097_watchdog_ops, 4536 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4537 .pot_clear = mv88e6xxx_g2_pot_clear, 4538 .reset = mv88e6352_g1_reset, 4539 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4540 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4541 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4542 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4543 .stu_getnext = mv88e6352_g1_stu_getnext, 4544 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4545 .phylink_get_caps = mv88e6351_phylink_get_caps, 4546 }; 4547 4548 static const struct mv88e6xxx_ops mv88e6172_ops = { 4549 /* MV88E6XXX_FAMILY_6352 */ 4550 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4551 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4552 .irl_init_all = mv88e6352_g2_irl_init_all, 4553 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4554 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4555 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4556 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4557 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4558 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4559 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4560 .port_set_link = mv88e6xxx_port_set_link, 4561 .port_sync_link = mv88e6xxx_port_sync_link, 4562 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4563 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4564 .port_tag_remap = mv88e6095_port_tag_remap, 4565 .port_set_policy = mv88e6352_port_set_policy, 4566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4567 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4568 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4569 .port_set_ether_type = mv88e6351_port_set_ether_type, 4570 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4571 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4572 .port_pause_limit = mv88e6097_port_pause_limit, 4573 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4574 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4575 .port_get_cmode = mv88e6352_port_get_cmode, 4576 .port_setup_message_port = mv88e6xxx_setup_message_port, 4577 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4578 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4579 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4580 .stats_get_strings = mv88e6095_stats_get_strings, 4581 .stats_get_stat = mv88e6095_stats_get_stat, 4582 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4583 .set_egress_port = mv88e6095_g1_set_egress_port, 4584 .watchdog_ops = &mv88e6097_watchdog_ops, 4585 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4586 .pot_clear = mv88e6xxx_g2_pot_clear, 4587 .reset = mv88e6352_g1_reset, 4588 .rmu_disable = mv88e6352_g1_rmu_disable, 4589 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4590 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4591 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4592 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4593 .stu_getnext = mv88e6352_g1_stu_getnext, 4594 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4595 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4596 .serdes_get_regs = mv88e6352_serdes_get_regs, 4597 .gpio_ops = &mv88e6352_gpio_ops, 4598 .phylink_get_caps = mv88e6352_phylink_get_caps, 4599 .pcs_ops = &mv88e6352_pcs_ops, 4600 }; 4601 4602 static const struct mv88e6xxx_ops mv88e6175_ops = { 4603 /* MV88E6XXX_FAMILY_6351 */ 4604 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4605 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4606 .irl_init_all = mv88e6352_g2_irl_init_all, 4607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4608 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4609 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4610 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4611 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4612 .port_set_link = mv88e6xxx_port_set_link, 4613 .port_sync_link = mv88e6xxx_port_sync_link, 4614 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4615 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4616 .port_tag_remap = mv88e6095_port_tag_remap, 4617 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4618 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4619 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4620 .port_set_ether_type = mv88e6351_port_set_ether_type, 4621 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4622 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4623 .port_pause_limit = mv88e6097_port_pause_limit, 4624 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4625 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4626 .port_get_cmode = mv88e6352_port_get_cmode, 4627 .port_setup_message_port = mv88e6xxx_setup_message_port, 4628 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4629 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4630 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4631 .stats_get_strings = mv88e6095_stats_get_strings, 4632 .stats_get_stat = mv88e6095_stats_get_stat, 4633 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4634 .set_egress_port = mv88e6095_g1_set_egress_port, 4635 .watchdog_ops = &mv88e6097_watchdog_ops, 4636 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4637 .pot_clear = mv88e6xxx_g2_pot_clear, 4638 .reset = mv88e6352_g1_reset, 4639 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4640 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4641 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4642 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4643 .stu_getnext = mv88e6352_g1_stu_getnext, 4644 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4645 .phylink_get_caps = mv88e6351_phylink_get_caps, 4646 }; 4647 4648 static const struct mv88e6xxx_ops mv88e6176_ops = { 4649 /* MV88E6XXX_FAMILY_6352 */ 4650 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4651 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4652 .irl_init_all = mv88e6352_g2_irl_init_all, 4653 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4654 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4655 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4656 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4657 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4658 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4659 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4660 .port_set_link = mv88e6xxx_port_set_link, 4661 .port_sync_link = mv88e6xxx_port_sync_link, 4662 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4663 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4664 .port_tag_remap = mv88e6095_port_tag_remap, 4665 .port_set_policy = mv88e6352_port_set_policy, 4666 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4667 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4668 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4669 .port_set_ether_type = mv88e6351_port_set_ether_type, 4670 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4671 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4672 .port_pause_limit = mv88e6097_port_pause_limit, 4673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4675 .port_get_cmode = mv88e6352_port_get_cmode, 4676 .port_setup_message_port = mv88e6xxx_setup_message_port, 4677 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4679 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4680 .stats_get_strings = mv88e6095_stats_get_strings, 4681 .stats_get_stat = mv88e6095_stats_get_stat, 4682 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4683 .set_egress_port = mv88e6095_g1_set_egress_port, 4684 .watchdog_ops = &mv88e6097_watchdog_ops, 4685 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4686 .pot_clear = mv88e6xxx_g2_pot_clear, 4687 .reset = mv88e6352_g1_reset, 4688 .rmu_disable = mv88e6352_g1_rmu_disable, 4689 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4690 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4691 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4693 .stu_getnext = mv88e6352_g1_stu_getnext, 4694 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4695 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4696 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4697 .serdes_get_regs = mv88e6352_serdes_get_regs, 4698 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4699 .gpio_ops = &mv88e6352_gpio_ops, 4700 .phylink_get_caps = mv88e6352_phylink_get_caps, 4701 .pcs_ops = &mv88e6352_pcs_ops, 4702 }; 4703 4704 static const struct mv88e6xxx_ops mv88e6185_ops = { 4705 /* MV88E6XXX_FAMILY_6185 */ 4706 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4707 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4708 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4709 .phy_read = mv88e6185_phy_ppu_read, 4710 .phy_write = mv88e6185_phy_ppu_write, 4711 .port_set_link = mv88e6xxx_port_set_link, 4712 .port_sync_link = mv88e6185_port_sync_link, 4713 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4714 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4715 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4716 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4717 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4718 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4719 .port_set_pause = mv88e6185_port_set_pause, 4720 .port_get_cmode = mv88e6185_port_get_cmode, 4721 .port_setup_message_port = mv88e6xxx_setup_message_port, 4722 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4723 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4724 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4725 .stats_get_strings = mv88e6095_stats_get_strings, 4726 .stats_get_stat = mv88e6095_stats_get_stat, 4727 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4728 .set_egress_port = mv88e6095_g1_set_egress_port, 4729 .watchdog_ops = &mv88e6097_watchdog_ops, 4730 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4731 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4732 .ppu_enable = mv88e6185_g1_ppu_enable, 4733 .ppu_disable = mv88e6185_g1_ppu_disable, 4734 .reset = mv88e6185_g1_reset, 4735 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4736 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4737 .phylink_get_caps = mv88e6185_phylink_get_caps, 4738 .pcs_ops = &mv88e6185_pcs_ops, 4739 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4740 }; 4741 4742 static const struct mv88e6xxx_ops mv88e6190_ops = { 4743 /* MV88E6XXX_FAMILY_6390 */ 4744 .setup_errata = mv88e6390_setup_errata, 4745 .irl_init_all = mv88e6390_g2_irl_init_all, 4746 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4747 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4749 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4750 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4751 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4752 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4753 .port_set_link = mv88e6xxx_port_set_link, 4754 .port_sync_link = mv88e6xxx_port_sync_link, 4755 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4756 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4757 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4758 .port_tag_remap = mv88e6390_port_tag_remap, 4759 .port_set_policy = mv88e6352_port_set_policy, 4760 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4761 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4762 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4763 .port_set_ether_type = mv88e6351_port_set_ether_type, 4764 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4765 .port_pause_limit = mv88e6390_port_pause_limit, 4766 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4767 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4768 .port_get_cmode = mv88e6352_port_get_cmode, 4769 .port_set_cmode = mv88e6390_port_set_cmode, 4770 .port_setup_message_port = mv88e6xxx_setup_message_port, 4771 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4772 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4773 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4774 .stats_get_strings = mv88e6320_stats_get_strings, 4775 .stats_get_stat = mv88e6390_stats_get_stat, 4776 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4777 .set_egress_port = mv88e6390_g1_set_egress_port, 4778 .watchdog_ops = &mv88e6390_watchdog_ops, 4779 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4780 .pot_clear = mv88e6xxx_g2_pot_clear, 4781 .reset = mv88e6352_g1_reset, 4782 .rmu_disable = mv88e6390_g1_rmu_disable, 4783 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4784 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4785 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4786 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4787 .stu_getnext = mv88e6390_g1_stu_getnext, 4788 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4789 .serdes_get_lane = mv88e6390_serdes_get_lane, 4790 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4791 .serdes_get_strings = mv88e6390_serdes_get_strings, 4792 .serdes_get_stats = mv88e6390_serdes_get_stats, 4793 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4794 .serdes_get_regs = mv88e6390_serdes_get_regs, 4795 .gpio_ops = &mv88e6352_gpio_ops, 4796 .phylink_get_caps = mv88e6390_phylink_get_caps, 4797 .pcs_ops = &mv88e6390_pcs_ops, 4798 }; 4799 4800 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4801 /* MV88E6XXX_FAMILY_6390 */ 4802 .setup_errata = mv88e6390_setup_errata, 4803 .irl_init_all = mv88e6390_g2_irl_init_all, 4804 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4805 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4807 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4808 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4809 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4810 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4811 .port_set_link = mv88e6xxx_port_set_link, 4812 .port_sync_link = mv88e6xxx_port_sync_link, 4813 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4814 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4815 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4816 .port_tag_remap = mv88e6390_port_tag_remap, 4817 .port_set_policy = mv88e6352_port_set_policy, 4818 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4819 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4820 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4821 .port_set_ether_type = mv88e6351_port_set_ether_type, 4822 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4823 .port_pause_limit = mv88e6390_port_pause_limit, 4824 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4825 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4826 .port_get_cmode = mv88e6352_port_get_cmode, 4827 .port_set_cmode = mv88e6390x_port_set_cmode, 4828 .port_setup_message_port = mv88e6xxx_setup_message_port, 4829 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4830 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4831 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4832 .stats_get_strings = mv88e6320_stats_get_strings, 4833 .stats_get_stat = mv88e6390_stats_get_stat, 4834 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4835 .set_egress_port = mv88e6390_g1_set_egress_port, 4836 .watchdog_ops = &mv88e6390_watchdog_ops, 4837 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4838 .pot_clear = mv88e6xxx_g2_pot_clear, 4839 .reset = mv88e6352_g1_reset, 4840 .rmu_disable = mv88e6390_g1_rmu_disable, 4841 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4842 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4843 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4844 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4845 .stu_getnext = mv88e6390_g1_stu_getnext, 4846 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4847 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4848 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4849 .serdes_get_strings = mv88e6390_serdes_get_strings, 4850 .serdes_get_stats = mv88e6390_serdes_get_stats, 4851 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4852 .serdes_get_regs = mv88e6390_serdes_get_regs, 4853 .gpio_ops = &mv88e6352_gpio_ops, 4854 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4855 .pcs_ops = &mv88e6390_pcs_ops, 4856 }; 4857 4858 static const struct mv88e6xxx_ops mv88e6191_ops = { 4859 /* MV88E6XXX_FAMILY_6390 */ 4860 .setup_errata = mv88e6390_setup_errata, 4861 .irl_init_all = mv88e6390_g2_irl_init_all, 4862 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4863 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4865 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4866 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4867 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4868 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4869 .port_set_link = mv88e6xxx_port_set_link, 4870 .port_sync_link = mv88e6xxx_port_sync_link, 4871 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4872 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4873 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4874 .port_tag_remap = mv88e6390_port_tag_remap, 4875 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4876 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4877 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4878 .port_set_ether_type = mv88e6351_port_set_ether_type, 4879 .port_pause_limit = mv88e6390_port_pause_limit, 4880 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4881 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4882 .port_get_cmode = mv88e6352_port_get_cmode, 4883 .port_set_cmode = mv88e6390_port_set_cmode, 4884 .port_setup_message_port = mv88e6xxx_setup_message_port, 4885 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4886 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4887 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4888 .stats_get_strings = mv88e6320_stats_get_strings, 4889 .stats_get_stat = mv88e6390_stats_get_stat, 4890 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4891 .set_egress_port = mv88e6390_g1_set_egress_port, 4892 .watchdog_ops = &mv88e6390_watchdog_ops, 4893 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4894 .pot_clear = mv88e6xxx_g2_pot_clear, 4895 .reset = mv88e6352_g1_reset, 4896 .rmu_disable = mv88e6390_g1_rmu_disable, 4897 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4898 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4899 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4900 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4901 .stu_getnext = mv88e6390_g1_stu_getnext, 4902 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4903 .serdes_get_lane = mv88e6390_serdes_get_lane, 4904 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4905 .serdes_get_strings = mv88e6390_serdes_get_strings, 4906 .serdes_get_stats = mv88e6390_serdes_get_stats, 4907 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4908 .serdes_get_regs = mv88e6390_serdes_get_regs, 4909 .avb_ops = &mv88e6390_avb_ops, 4910 .ptp_ops = &mv88e6352_ptp_ops, 4911 .phylink_get_caps = mv88e6390_phylink_get_caps, 4912 .pcs_ops = &mv88e6390_pcs_ops, 4913 }; 4914 4915 static const struct mv88e6xxx_ops mv88e6240_ops = { 4916 /* MV88E6XXX_FAMILY_6352 */ 4917 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4918 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4919 .irl_init_all = mv88e6352_g2_irl_init_all, 4920 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4921 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4922 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4923 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4924 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4925 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4926 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4927 .port_set_link = mv88e6xxx_port_set_link, 4928 .port_sync_link = mv88e6xxx_port_sync_link, 4929 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4930 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4931 .port_tag_remap = mv88e6095_port_tag_remap, 4932 .port_set_policy = mv88e6352_port_set_policy, 4933 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4934 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4935 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4936 .port_set_ether_type = mv88e6351_port_set_ether_type, 4937 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4938 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4939 .port_pause_limit = mv88e6097_port_pause_limit, 4940 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4941 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4942 .port_get_cmode = mv88e6352_port_get_cmode, 4943 .port_setup_message_port = mv88e6xxx_setup_message_port, 4944 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4945 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4946 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4947 .stats_get_strings = mv88e6095_stats_get_strings, 4948 .stats_get_stat = mv88e6095_stats_get_stat, 4949 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4950 .set_egress_port = mv88e6095_g1_set_egress_port, 4951 .watchdog_ops = &mv88e6097_watchdog_ops, 4952 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4953 .pot_clear = mv88e6xxx_g2_pot_clear, 4954 .reset = mv88e6352_g1_reset, 4955 .rmu_disable = mv88e6352_g1_rmu_disable, 4956 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4957 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4958 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4959 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4960 .stu_getnext = mv88e6352_g1_stu_getnext, 4961 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4962 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4963 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4964 .serdes_get_regs = mv88e6352_serdes_get_regs, 4965 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4966 .gpio_ops = &mv88e6352_gpio_ops, 4967 .avb_ops = &mv88e6352_avb_ops, 4968 .ptp_ops = &mv88e6352_ptp_ops, 4969 .phylink_get_caps = mv88e6352_phylink_get_caps, 4970 .pcs_ops = &mv88e6352_pcs_ops, 4971 }; 4972 4973 static const struct mv88e6xxx_ops mv88e6250_ops = { 4974 /* MV88E6XXX_FAMILY_6250 */ 4975 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4976 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4977 .irl_init_all = mv88e6352_g2_irl_init_all, 4978 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4979 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4980 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4981 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4982 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4983 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4984 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4985 .port_set_link = mv88e6xxx_port_set_link, 4986 .port_sync_link = mv88e6xxx_port_sync_link, 4987 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4988 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4989 .port_tag_remap = mv88e6095_port_tag_remap, 4990 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4991 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4992 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4993 .port_set_ether_type = mv88e6351_port_set_ether_type, 4994 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4995 .port_pause_limit = mv88e6097_port_pause_limit, 4996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4997 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4998 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4999 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5000 .stats_get_strings = mv88e6250_stats_get_strings, 5001 .stats_get_stat = mv88e6250_stats_get_stat, 5002 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5003 .set_egress_port = mv88e6095_g1_set_egress_port, 5004 .watchdog_ops = &mv88e6250_watchdog_ops, 5005 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5006 .pot_clear = mv88e6xxx_g2_pot_clear, 5007 .reset = mv88e6250_g1_reset, 5008 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5009 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5010 .avb_ops = &mv88e6352_avb_ops, 5011 .ptp_ops = &mv88e6250_ptp_ops, 5012 .phylink_get_caps = mv88e6250_phylink_get_caps, 5013 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5014 }; 5015 5016 static const struct mv88e6xxx_ops mv88e6290_ops = { 5017 /* MV88E6XXX_FAMILY_6390 */ 5018 .setup_errata = mv88e6390_setup_errata, 5019 .irl_init_all = mv88e6390_g2_irl_init_all, 5020 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5021 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5022 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5023 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5024 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5025 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5026 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5027 .port_set_link = mv88e6xxx_port_set_link, 5028 .port_sync_link = mv88e6xxx_port_sync_link, 5029 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5030 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5031 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5032 .port_tag_remap = mv88e6390_port_tag_remap, 5033 .port_set_policy = mv88e6352_port_set_policy, 5034 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5035 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5036 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5037 .port_set_ether_type = mv88e6351_port_set_ether_type, 5038 .port_pause_limit = mv88e6390_port_pause_limit, 5039 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5040 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5041 .port_get_cmode = mv88e6352_port_get_cmode, 5042 .port_set_cmode = mv88e6390_port_set_cmode, 5043 .port_setup_message_port = mv88e6xxx_setup_message_port, 5044 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5045 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5046 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5047 .stats_get_strings = mv88e6320_stats_get_strings, 5048 .stats_get_stat = mv88e6390_stats_get_stat, 5049 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5050 .set_egress_port = mv88e6390_g1_set_egress_port, 5051 .watchdog_ops = &mv88e6390_watchdog_ops, 5052 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5053 .pot_clear = mv88e6xxx_g2_pot_clear, 5054 .reset = mv88e6352_g1_reset, 5055 .rmu_disable = mv88e6390_g1_rmu_disable, 5056 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5057 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5058 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5059 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5060 .stu_getnext = mv88e6390_g1_stu_getnext, 5061 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5062 .serdes_get_lane = mv88e6390_serdes_get_lane, 5063 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5064 .serdes_get_strings = mv88e6390_serdes_get_strings, 5065 .serdes_get_stats = mv88e6390_serdes_get_stats, 5066 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5067 .serdes_get_regs = mv88e6390_serdes_get_regs, 5068 .gpio_ops = &mv88e6352_gpio_ops, 5069 .avb_ops = &mv88e6390_avb_ops, 5070 .ptp_ops = &mv88e6390_ptp_ops, 5071 .phylink_get_caps = mv88e6390_phylink_get_caps, 5072 .pcs_ops = &mv88e6390_pcs_ops, 5073 }; 5074 5075 static const struct mv88e6xxx_ops mv88e6320_ops = { 5076 /* MV88E6XXX_FAMILY_6320 */ 5077 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5078 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5079 .irl_init_all = mv88e6352_g2_irl_init_all, 5080 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5081 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5082 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5083 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5084 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5085 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5086 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5087 .port_set_link = mv88e6xxx_port_set_link, 5088 .port_sync_link = mv88e6xxx_port_sync_link, 5089 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5090 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5091 .port_tag_remap = mv88e6095_port_tag_remap, 5092 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5093 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5094 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5095 .port_set_ether_type = mv88e6351_port_set_ether_type, 5096 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5097 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5098 .port_pause_limit = mv88e6097_port_pause_limit, 5099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5101 .port_get_cmode = mv88e6352_port_get_cmode, 5102 .port_setup_message_port = mv88e6xxx_setup_message_port, 5103 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5104 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5105 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5106 .stats_get_strings = mv88e6320_stats_get_strings, 5107 .stats_get_stat = mv88e6320_stats_get_stat, 5108 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5109 .set_egress_port = mv88e6095_g1_set_egress_port, 5110 .watchdog_ops = &mv88e6390_watchdog_ops, 5111 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5112 .pot_clear = mv88e6xxx_g2_pot_clear, 5113 .reset = mv88e6352_g1_reset, 5114 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5115 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5116 .gpio_ops = &mv88e6352_gpio_ops, 5117 .avb_ops = &mv88e6352_avb_ops, 5118 .ptp_ops = &mv88e6352_ptp_ops, 5119 .phylink_get_caps = mv88e632x_phylink_get_caps, 5120 }; 5121 5122 static const struct mv88e6xxx_ops mv88e6321_ops = { 5123 /* MV88E6XXX_FAMILY_6320 */ 5124 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5125 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5126 .irl_init_all = mv88e6352_g2_irl_init_all, 5127 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5128 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5129 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5130 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5131 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5132 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5133 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5134 .port_set_link = mv88e6xxx_port_set_link, 5135 .port_sync_link = mv88e6xxx_port_sync_link, 5136 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5137 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5138 .port_tag_remap = mv88e6095_port_tag_remap, 5139 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5140 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5141 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5142 .port_set_ether_type = mv88e6351_port_set_ether_type, 5143 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5144 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5145 .port_pause_limit = mv88e6097_port_pause_limit, 5146 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5147 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5148 .port_get_cmode = mv88e6352_port_get_cmode, 5149 .port_setup_message_port = mv88e6xxx_setup_message_port, 5150 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5151 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5152 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5153 .stats_get_strings = mv88e6320_stats_get_strings, 5154 .stats_get_stat = mv88e6320_stats_get_stat, 5155 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5156 .set_egress_port = mv88e6095_g1_set_egress_port, 5157 .watchdog_ops = &mv88e6390_watchdog_ops, 5158 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5159 .reset = mv88e6352_g1_reset, 5160 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5161 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5162 .gpio_ops = &mv88e6352_gpio_ops, 5163 .avb_ops = &mv88e6352_avb_ops, 5164 .ptp_ops = &mv88e6352_ptp_ops, 5165 .phylink_get_caps = mv88e632x_phylink_get_caps, 5166 }; 5167 5168 static const struct mv88e6xxx_ops mv88e6341_ops = { 5169 /* MV88E6XXX_FAMILY_6341 */ 5170 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5171 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5172 .irl_init_all = mv88e6352_g2_irl_init_all, 5173 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5174 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5175 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5176 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5177 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5178 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5179 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5180 .port_set_link = mv88e6xxx_port_set_link, 5181 .port_sync_link = mv88e6xxx_port_sync_link, 5182 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5183 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5184 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5185 .port_tag_remap = mv88e6095_port_tag_remap, 5186 .port_set_policy = mv88e6352_port_set_policy, 5187 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5188 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5189 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5190 .port_set_ether_type = mv88e6351_port_set_ether_type, 5191 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5192 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5193 .port_pause_limit = mv88e6097_port_pause_limit, 5194 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5196 .port_get_cmode = mv88e6352_port_get_cmode, 5197 .port_set_cmode = mv88e6341_port_set_cmode, 5198 .port_setup_message_port = mv88e6xxx_setup_message_port, 5199 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5200 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5201 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5202 .stats_get_strings = mv88e6320_stats_get_strings, 5203 .stats_get_stat = mv88e6390_stats_get_stat, 5204 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5205 .set_egress_port = mv88e6390_g1_set_egress_port, 5206 .watchdog_ops = &mv88e6390_watchdog_ops, 5207 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5208 .pot_clear = mv88e6xxx_g2_pot_clear, 5209 .reset = mv88e6352_g1_reset, 5210 .rmu_disable = mv88e6390_g1_rmu_disable, 5211 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5212 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5213 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5214 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5215 .stu_getnext = mv88e6352_g1_stu_getnext, 5216 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5217 .serdes_get_lane = mv88e6341_serdes_get_lane, 5218 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5219 .gpio_ops = &mv88e6352_gpio_ops, 5220 .avb_ops = &mv88e6390_avb_ops, 5221 .ptp_ops = &mv88e6352_ptp_ops, 5222 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5223 .serdes_get_strings = mv88e6390_serdes_get_strings, 5224 .serdes_get_stats = mv88e6390_serdes_get_stats, 5225 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5226 .serdes_get_regs = mv88e6390_serdes_get_regs, 5227 .phylink_get_caps = mv88e6341_phylink_get_caps, 5228 .pcs_ops = &mv88e6390_pcs_ops, 5229 }; 5230 5231 static const struct mv88e6xxx_ops mv88e6350_ops = { 5232 /* MV88E6XXX_FAMILY_6351 */ 5233 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5234 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5235 .irl_init_all = mv88e6352_g2_irl_init_all, 5236 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5237 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5238 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5239 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5240 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5241 .port_set_link = mv88e6xxx_port_set_link, 5242 .port_sync_link = mv88e6xxx_port_sync_link, 5243 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5244 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5245 .port_tag_remap = mv88e6095_port_tag_remap, 5246 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5247 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5248 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5249 .port_set_ether_type = mv88e6351_port_set_ether_type, 5250 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5251 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5252 .port_pause_limit = mv88e6097_port_pause_limit, 5253 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5254 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5255 .port_get_cmode = mv88e6352_port_get_cmode, 5256 .port_setup_message_port = mv88e6xxx_setup_message_port, 5257 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5258 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5259 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5260 .stats_get_strings = mv88e6095_stats_get_strings, 5261 .stats_get_stat = mv88e6095_stats_get_stat, 5262 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5263 .set_egress_port = mv88e6095_g1_set_egress_port, 5264 .watchdog_ops = &mv88e6097_watchdog_ops, 5265 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5266 .pot_clear = mv88e6xxx_g2_pot_clear, 5267 .reset = mv88e6352_g1_reset, 5268 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5269 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5270 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5271 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5272 .stu_getnext = mv88e6352_g1_stu_getnext, 5273 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5274 .phylink_get_caps = mv88e6351_phylink_get_caps, 5275 }; 5276 5277 static const struct mv88e6xxx_ops mv88e6351_ops = { 5278 /* MV88E6XXX_FAMILY_6351 */ 5279 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5280 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5281 .irl_init_all = mv88e6352_g2_irl_init_all, 5282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5283 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5284 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5285 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5286 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5287 .port_set_link = mv88e6xxx_port_set_link, 5288 .port_sync_link = mv88e6xxx_port_sync_link, 5289 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5291 .port_tag_remap = mv88e6095_port_tag_remap, 5292 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5293 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5294 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5295 .port_set_ether_type = mv88e6351_port_set_ether_type, 5296 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5297 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5298 .port_pause_limit = mv88e6097_port_pause_limit, 5299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5301 .port_get_cmode = mv88e6352_port_get_cmode, 5302 .port_setup_message_port = mv88e6xxx_setup_message_port, 5303 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5304 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5305 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5306 .stats_get_strings = mv88e6095_stats_get_strings, 5307 .stats_get_stat = mv88e6095_stats_get_stat, 5308 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5309 .set_egress_port = mv88e6095_g1_set_egress_port, 5310 .watchdog_ops = &mv88e6097_watchdog_ops, 5311 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5312 .pot_clear = mv88e6xxx_g2_pot_clear, 5313 .reset = mv88e6352_g1_reset, 5314 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5315 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5316 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5317 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5318 .stu_getnext = mv88e6352_g1_stu_getnext, 5319 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5320 .avb_ops = &mv88e6352_avb_ops, 5321 .ptp_ops = &mv88e6352_ptp_ops, 5322 .phylink_get_caps = mv88e6351_phylink_get_caps, 5323 }; 5324 5325 static const struct mv88e6xxx_ops mv88e6352_ops = { 5326 /* MV88E6XXX_FAMILY_6352 */ 5327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5328 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5329 .irl_init_all = mv88e6352_g2_irl_init_all, 5330 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5331 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5332 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5333 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5334 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5335 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5336 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5337 .port_set_link = mv88e6xxx_port_set_link, 5338 .port_sync_link = mv88e6xxx_port_sync_link, 5339 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5340 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5341 .port_tag_remap = mv88e6095_port_tag_remap, 5342 .port_set_policy = mv88e6352_port_set_policy, 5343 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5344 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5345 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5346 .port_set_ether_type = mv88e6351_port_set_ether_type, 5347 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5348 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5349 .port_pause_limit = mv88e6097_port_pause_limit, 5350 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5351 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5352 .port_get_cmode = mv88e6352_port_get_cmode, 5353 .port_setup_message_port = mv88e6xxx_setup_message_port, 5354 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5355 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5356 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5357 .stats_get_strings = mv88e6095_stats_get_strings, 5358 .stats_get_stat = mv88e6095_stats_get_stat, 5359 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5360 .set_egress_port = mv88e6095_g1_set_egress_port, 5361 .watchdog_ops = &mv88e6097_watchdog_ops, 5362 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5363 .pot_clear = mv88e6xxx_g2_pot_clear, 5364 .reset = mv88e6352_g1_reset, 5365 .rmu_disable = mv88e6352_g1_rmu_disable, 5366 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5367 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5368 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5369 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5370 .stu_getnext = mv88e6352_g1_stu_getnext, 5371 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5372 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5373 .gpio_ops = &mv88e6352_gpio_ops, 5374 .avb_ops = &mv88e6352_avb_ops, 5375 .ptp_ops = &mv88e6352_ptp_ops, 5376 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5377 .serdes_get_strings = mv88e6352_serdes_get_strings, 5378 .serdes_get_stats = mv88e6352_serdes_get_stats, 5379 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5380 .serdes_get_regs = mv88e6352_serdes_get_regs, 5381 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5382 .phylink_get_caps = mv88e6352_phylink_get_caps, 5383 .pcs_ops = &mv88e6352_pcs_ops, 5384 }; 5385 5386 static const struct mv88e6xxx_ops mv88e6390_ops = { 5387 /* MV88E6XXX_FAMILY_6390 */ 5388 .setup_errata = mv88e6390_setup_errata, 5389 .irl_init_all = mv88e6390_g2_irl_init_all, 5390 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5391 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5392 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5393 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5394 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5395 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5396 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5397 .port_set_link = mv88e6xxx_port_set_link, 5398 .port_sync_link = mv88e6xxx_port_sync_link, 5399 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5400 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5401 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5402 .port_tag_remap = mv88e6390_port_tag_remap, 5403 .port_set_policy = mv88e6352_port_set_policy, 5404 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5405 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5406 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5407 .port_set_ether_type = mv88e6351_port_set_ether_type, 5408 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5409 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5410 .port_pause_limit = mv88e6390_port_pause_limit, 5411 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5412 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5413 .port_get_cmode = mv88e6352_port_get_cmode, 5414 .port_set_cmode = mv88e6390_port_set_cmode, 5415 .port_setup_message_port = mv88e6xxx_setup_message_port, 5416 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5417 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5418 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5419 .stats_get_strings = mv88e6320_stats_get_strings, 5420 .stats_get_stat = mv88e6390_stats_get_stat, 5421 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5422 .set_egress_port = mv88e6390_g1_set_egress_port, 5423 .watchdog_ops = &mv88e6390_watchdog_ops, 5424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5425 .pot_clear = mv88e6xxx_g2_pot_clear, 5426 .reset = mv88e6352_g1_reset, 5427 .rmu_disable = mv88e6390_g1_rmu_disable, 5428 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5429 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5430 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5431 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5432 .stu_getnext = mv88e6390_g1_stu_getnext, 5433 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5434 .serdes_get_lane = mv88e6390_serdes_get_lane, 5435 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5436 .gpio_ops = &mv88e6352_gpio_ops, 5437 .avb_ops = &mv88e6390_avb_ops, 5438 .ptp_ops = &mv88e6390_ptp_ops, 5439 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5440 .serdes_get_strings = mv88e6390_serdes_get_strings, 5441 .serdes_get_stats = mv88e6390_serdes_get_stats, 5442 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5443 .serdes_get_regs = mv88e6390_serdes_get_regs, 5444 .phylink_get_caps = mv88e6390_phylink_get_caps, 5445 .pcs_ops = &mv88e6390_pcs_ops, 5446 }; 5447 5448 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5449 /* MV88E6XXX_FAMILY_6390 */ 5450 .setup_errata = mv88e6390_setup_errata, 5451 .irl_init_all = mv88e6390_g2_irl_init_all, 5452 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5453 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5454 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5455 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5456 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5457 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5458 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5459 .port_set_link = mv88e6xxx_port_set_link, 5460 .port_sync_link = mv88e6xxx_port_sync_link, 5461 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5462 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5463 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5464 .port_tag_remap = mv88e6390_port_tag_remap, 5465 .port_set_policy = mv88e6352_port_set_policy, 5466 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5467 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5468 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5469 .port_set_ether_type = mv88e6351_port_set_ether_type, 5470 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5471 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5472 .port_pause_limit = mv88e6390_port_pause_limit, 5473 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5474 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5475 .port_get_cmode = mv88e6352_port_get_cmode, 5476 .port_set_cmode = mv88e6390x_port_set_cmode, 5477 .port_setup_message_port = mv88e6xxx_setup_message_port, 5478 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5479 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5480 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5481 .stats_get_strings = mv88e6320_stats_get_strings, 5482 .stats_get_stat = mv88e6390_stats_get_stat, 5483 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5484 .set_egress_port = mv88e6390_g1_set_egress_port, 5485 .watchdog_ops = &mv88e6390_watchdog_ops, 5486 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5487 .pot_clear = mv88e6xxx_g2_pot_clear, 5488 .reset = mv88e6352_g1_reset, 5489 .rmu_disable = mv88e6390_g1_rmu_disable, 5490 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5491 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5492 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5493 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5494 .stu_getnext = mv88e6390_g1_stu_getnext, 5495 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5496 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5497 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5498 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5499 .serdes_get_strings = mv88e6390_serdes_get_strings, 5500 .serdes_get_stats = mv88e6390_serdes_get_stats, 5501 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5502 .serdes_get_regs = mv88e6390_serdes_get_regs, 5503 .gpio_ops = &mv88e6352_gpio_ops, 5504 .avb_ops = &mv88e6390_avb_ops, 5505 .ptp_ops = &mv88e6390_ptp_ops, 5506 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5507 .pcs_ops = &mv88e6390_pcs_ops, 5508 }; 5509 5510 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5511 /* MV88E6XXX_FAMILY_6393 */ 5512 .irl_init_all = mv88e6390_g2_irl_init_all, 5513 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5514 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5516 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5517 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5518 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5519 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5520 .port_set_link = mv88e6xxx_port_set_link, 5521 .port_sync_link = mv88e6xxx_port_sync_link, 5522 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5523 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5524 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5525 .port_tag_remap = mv88e6390_port_tag_remap, 5526 .port_set_policy = mv88e6393x_port_set_policy, 5527 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5528 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5529 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5530 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5531 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5532 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5533 .port_pause_limit = mv88e6390_port_pause_limit, 5534 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5535 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5536 .port_get_cmode = mv88e6352_port_get_cmode, 5537 .port_set_cmode = mv88e6393x_port_set_cmode, 5538 .port_setup_message_port = mv88e6xxx_setup_message_port, 5539 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5540 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5541 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5542 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5543 .stats_get_strings = mv88e6320_stats_get_strings, 5544 .stats_get_stat = mv88e6390_stats_get_stat, 5545 /* .set_cpu_port is missing because this family does not support a global 5546 * CPU port, only per port CPU port which is set via 5547 * .port_set_upstream_port method. 5548 */ 5549 .set_egress_port = mv88e6393x_set_egress_port, 5550 .watchdog_ops = &mv88e6393x_watchdog_ops, 5551 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5552 .pot_clear = mv88e6xxx_g2_pot_clear, 5553 .reset = mv88e6352_g1_reset, 5554 .rmu_disable = mv88e6390_g1_rmu_disable, 5555 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5556 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5557 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5558 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5559 .stu_getnext = mv88e6390_g1_stu_getnext, 5560 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5561 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5562 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5563 /* TODO: serdes stats */ 5564 .gpio_ops = &mv88e6352_gpio_ops, 5565 .avb_ops = &mv88e6390_avb_ops, 5566 .ptp_ops = &mv88e6352_ptp_ops, 5567 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5568 .pcs_ops = &mv88e6393x_pcs_ops, 5569 }; 5570 5571 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5572 [MV88E6020] = { 5573 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5574 .family = MV88E6XXX_FAMILY_6250, 5575 .name = "Marvell 88E6020", 5576 .num_databases = 64, 5577 /* Ports 2-4 are not routed to pins 5578 * => usable ports 0, 1, 5, 6 5579 */ 5580 .num_ports = 7, 5581 .num_internal_phys = 2, 5582 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5583 .max_vid = 4095, 5584 .port_base_addr = 0x8, 5585 .phy_base_addr = 0x0, 5586 .global1_addr = 0xf, 5587 .global2_addr = 0x7, 5588 .age_time_coeff = 15000, 5589 .g1_irqs = 9, 5590 .g2_irqs = 5, 5591 .atu_move_port_mask = 0xf, 5592 .dual_chip = true, 5593 .ops = &mv88e6250_ops, 5594 }, 5595 5596 [MV88E6071] = { 5597 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5598 .family = MV88E6XXX_FAMILY_6250, 5599 .name = "Marvell 88E6071", 5600 .num_databases = 64, 5601 .num_ports = 7, 5602 .num_internal_phys = 5, 5603 .max_vid = 4095, 5604 .port_base_addr = 0x08, 5605 .phy_base_addr = 0x00, 5606 .global1_addr = 0x0f, 5607 .global2_addr = 0x07, 5608 .age_time_coeff = 15000, 5609 .g1_irqs = 9, 5610 .g2_irqs = 5, 5611 .atu_move_port_mask = 0xf, 5612 .dual_chip = true, 5613 .ops = &mv88e6250_ops, 5614 }, 5615 5616 [MV88E6085] = { 5617 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5618 .family = MV88E6XXX_FAMILY_6097, 5619 .name = "Marvell 88E6085", 5620 .num_databases = 4096, 5621 .num_macs = 8192, 5622 .num_ports = 10, 5623 .num_internal_phys = 5, 5624 .max_vid = 4095, 5625 .max_sid = 63, 5626 .port_base_addr = 0x10, 5627 .phy_base_addr = 0x0, 5628 .global1_addr = 0x1b, 5629 .global2_addr = 0x1c, 5630 .age_time_coeff = 15000, 5631 .g1_irqs = 8, 5632 .g2_irqs = 10, 5633 .atu_move_port_mask = 0xf, 5634 .pvt = true, 5635 .multi_chip = true, 5636 .ops = &mv88e6085_ops, 5637 }, 5638 5639 [MV88E6095] = { 5640 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5641 .family = MV88E6XXX_FAMILY_6095, 5642 .name = "Marvell 88E6095/88E6095F", 5643 .num_databases = 256, 5644 .num_macs = 8192, 5645 .num_ports = 11, 5646 .num_internal_phys = 0, 5647 .max_vid = 4095, 5648 .port_base_addr = 0x10, 5649 .phy_base_addr = 0x0, 5650 .global1_addr = 0x1b, 5651 .global2_addr = 0x1c, 5652 .age_time_coeff = 15000, 5653 .g1_irqs = 8, 5654 .atu_move_port_mask = 0xf, 5655 .multi_chip = true, 5656 .ops = &mv88e6095_ops, 5657 }, 5658 5659 [MV88E6097] = { 5660 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5661 .family = MV88E6XXX_FAMILY_6097, 5662 .name = "Marvell 88E6097/88E6097F", 5663 .num_databases = 4096, 5664 .num_macs = 8192, 5665 .num_ports = 11, 5666 .num_internal_phys = 8, 5667 .max_vid = 4095, 5668 .max_sid = 63, 5669 .port_base_addr = 0x10, 5670 .phy_base_addr = 0x0, 5671 .global1_addr = 0x1b, 5672 .global2_addr = 0x1c, 5673 .age_time_coeff = 15000, 5674 .g1_irqs = 8, 5675 .g2_irqs = 10, 5676 .atu_move_port_mask = 0xf, 5677 .pvt = true, 5678 .multi_chip = true, 5679 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5680 .ops = &mv88e6097_ops, 5681 }, 5682 5683 [MV88E6123] = { 5684 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5685 .family = MV88E6XXX_FAMILY_6165, 5686 .name = "Marvell 88E6123", 5687 .num_databases = 4096, 5688 .num_macs = 1024, 5689 .num_ports = 3, 5690 .num_internal_phys = 5, 5691 .max_vid = 4095, 5692 .max_sid = 63, 5693 .port_base_addr = 0x10, 5694 .phy_base_addr = 0x0, 5695 .global1_addr = 0x1b, 5696 .global2_addr = 0x1c, 5697 .age_time_coeff = 15000, 5698 .g1_irqs = 9, 5699 .g2_irqs = 10, 5700 .atu_move_port_mask = 0xf, 5701 .pvt = true, 5702 .multi_chip = true, 5703 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5704 .ops = &mv88e6123_ops, 5705 }, 5706 5707 [MV88E6131] = { 5708 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5709 .family = MV88E6XXX_FAMILY_6185, 5710 .name = "Marvell 88E6131", 5711 .num_databases = 256, 5712 .num_macs = 8192, 5713 .num_ports = 8, 5714 .num_internal_phys = 0, 5715 .max_vid = 4095, 5716 .port_base_addr = 0x10, 5717 .phy_base_addr = 0x0, 5718 .global1_addr = 0x1b, 5719 .global2_addr = 0x1c, 5720 .age_time_coeff = 15000, 5721 .g1_irqs = 9, 5722 .atu_move_port_mask = 0xf, 5723 .multi_chip = true, 5724 .ops = &mv88e6131_ops, 5725 }, 5726 5727 [MV88E6141] = { 5728 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5729 .family = MV88E6XXX_FAMILY_6341, 5730 .name = "Marvell 88E6141", 5731 .num_databases = 256, 5732 .num_macs = 2048, 5733 .num_ports = 6, 5734 .num_internal_phys = 5, 5735 .num_gpio = 11, 5736 .max_vid = 4095, 5737 .max_sid = 63, 5738 .port_base_addr = 0x10, 5739 .phy_base_addr = 0x10, 5740 .global1_addr = 0x1b, 5741 .global2_addr = 0x1c, 5742 .age_time_coeff = 3750, 5743 .atu_move_port_mask = 0x1f, 5744 .g1_irqs = 9, 5745 .g2_irqs = 10, 5746 .pvt = true, 5747 .multi_chip = true, 5748 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5749 .ops = &mv88e6141_ops, 5750 }, 5751 5752 [MV88E6161] = { 5753 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5754 .family = MV88E6XXX_FAMILY_6165, 5755 .name = "Marvell 88E6161", 5756 .num_databases = 4096, 5757 .num_macs = 1024, 5758 .num_ports = 6, 5759 .num_internal_phys = 5, 5760 .max_vid = 4095, 5761 .max_sid = 63, 5762 .port_base_addr = 0x10, 5763 .phy_base_addr = 0x0, 5764 .global1_addr = 0x1b, 5765 .global2_addr = 0x1c, 5766 .age_time_coeff = 15000, 5767 .g1_irqs = 9, 5768 .g2_irqs = 10, 5769 .atu_move_port_mask = 0xf, 5770 .pvt = true, 5771 .multi_chip = true, 5772 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5773 .ptp_support = true, 5774 .ops = &mv88e6161_ops, 5775 }, 5776 5777 [MV88E6165] = { 5778 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5779 .family = MV88E6XXX_FAMILY_6165, 5780 .name = "Marvell 88E6165", 5781 .num_databases = 4096, 5782 .num_macs = 8192, 5783 .num_ports = 6, 5784 .num_internal_phys = 0, 5785 .max_vid = 4095, 5786 .max_sid = 63, 5787 .port_base_addr = 0x10, 5788 .phy_base_addr = 0x0, 5789 .global1_addr = 0x1b, 5790 .global2_addr = 0x1c, 5791 .age_time_coeff = 15000, 5792 .g1_irqs = 9, 5793 .g2_irqs = 10, 5794 .atu_move_port_mask = 0xf, 5795 .pvt = true, 5796 .multi_chip = true, 5797 .ptp_support = true, 5798 .ops = &mv88e6165_ops, 5799 }, 5800 5801 [MV88E6171] = { 5802 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5803 .family = MV88E6XXX_FAMILY_6351, 5804 .name = "Marvell 88E6171", 5805 .num_databases = 4096, 5806 .num_macs = 8192, 5807 .num_ports = 7, 5808 .num_internal_phys = 5, 5809 .max_vid = 4095, 5810 .max_sid = 63, 5811 .port_base_addr = 0x10, 5812 .phy_base_addr = 0x0, 5813 .global1_addr = 0x1b, 5814 .global2_addr = 0x1c, 5815 .age_time_coeff = 15000, 5816 .g1_irqs = 9, 5817 .g2_irqs = 10, 5818 .atu_move_port_mask = 0xf, 5819 .pvt = true, 5820 .multi_chip = true, 5821 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5822 .ops = &mv88e6171_ops, 5823 }, 5824 5825 [MV88E6172] = { 5826 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5827 .family = MV88E6XXX_FAMILY_6352, 5828 .name = "Marvell 88E6172", 5829 .num_databases = 4096, 5830 .num_macs = 8192, 5831 .num_ports = 7, 5832 .num_internal_phys = 5, 5833 .num_gpio = 15, 5834 .max_vid = 4095, 5835 .max_sid = 63, 5836 .port_base_addr = 0x10, 5837 .phy_base_addr = 0x0, 5838 .global1_addr = 0x1b, 5839 .global2_addr = 0x1c, 5840 .age_time_coeff = 15000, 5841 .g1_irqs = 9, 5842 .g2_irqs = 10, 5843 .atu_move_port_mask = 0xf, 5844 .pvt = true, 5845 .multi_chip = true, 5846 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5847 .ops = &mv88e6172_ops, 5848 }, 5849 5850 [MV88E6175] = { 5851 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5852 .family = MV88E6XXX_FAMILY_6351, 5853 .name = "Marvell 88E6175", 5854 .num_databases = 4096, 5855 .num_macs = 8192, 5856 .num_ports = 7, 5857 .num_internal_phys = 5, 5858 .max_vid = 4095, 5859 .max_sid = 63, 5860 .port_base_addr = 0x10, 5861 .phy_base_addr = 0x0, 5862 .global1_addr = 0x1b, 5863 .global2_addr = 0x1c, 5864 .age_time_coeff = 15000, 5865 .g1_irqs = 9, 5866 .g2_irqs = 10, 5867 .atu_move_port_mask = 0xf, 5868 .pvt = true, 5869 .multi_chip = true, 5870 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5871 .ops = &mv88e6175_ops, 5872 }, 5873 5874 [MV88E6176] = { 5875 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5876 .family = MV88E6XXX_FAMILY_6352, 5877 .name = "Marvell 88E6176", 5878 .num_databases = 4096, 5879 .num_macs = 8192, 5880 .num_ports = 7, 5881 .num_internal_phys = 5, 5882 .num_gpio = 15, 5883 .max_vid = 4095, 5884 .max_sid = 63, 5885 .port_base_addr = 0x10, 5886 .phy_base_addr = 0x0, 5887 .global1_addr = 0x1b, 5888 .global2_addr = 0x1c, 5889 .age_time_coeff = 15000, 5890 .g1_irqs = 9, 5891 .g2_irqs = 10, 5892 .atu_move_port_mask = 0xf, 5893 .pvt = true, 5894 .multi_chip = true, 5895 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5896 .ops = &mv88e6176_ops, 5897 }, 5898 5899 [MV88E6185] = { 5900 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5901 .family = MV88E6XXX_FAMILY_6185, 5902 .name = "Marvell 88E6185", 5903 .num_databases = 256, 5904 .num_macs = 8192, 5905 .num_ports = 10, 5906 .num_internal_phys = 0, 5907 .max_vid = 4095, 5908 .port_base_addr = 0x10, 5909 .phy_base_addr = 0x0, 5910 .global1_addr = 0x1b, 5911 .global2_addr = 0x1c, 5912 .age_time_coeff = 15000, 5913 .g1_irqs = 8, 5914 .atu_move_port_mask = 0xf, 5915 .multi_chip = true, 5916 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5917 .ops = &mv88e6185_ops, 5918 }, 5919 5920 [MV88E6190] = { 5921 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5922 .family = MV88E6XXX_FAMILY_6390, 5923 .name = "Marvell 88E6190", 5924 .num_databases = 4096, 5925 .num_macs = 16384, 5926 .num_ports = 11, /* 10 + Z80 */ 5927 .num_internal_phys = 9, 5928 .num_gpio = 16, 5929 .max_vid = 8191, 5930 .max_sid = 63, 5931 .port_base_addr = 0x0, 5932 .phy_base_addr = 0x0, 5933 .global1_addr = 0x1b, 5934 .global2_addr = 0x1c, 5935 .age_time_coeff = 3750, 5936 .g1_irqs = 9, 5937 .g2_irqs = 14, 5938 .pvt = true, 5939 .multi_chip = true, 5940 .atu_move_port_mask = 0x1f, 5941 .ops = &mv88e6190_ops, 5942 }, 5943 5944 [MV88E6190X] = { 5945 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5946 .family = MV88E6XXX_FAMILY_6390, 5947 .name = "Marvell 88E6190X", 5948 .num_databases = 4096, 5949 .num_macs = 16384, 5950 .num_ports = 11, /* 10 + Z80 */ 5951 .num_internal_phys = 9, 5952 .num_gpio = 16, 5953 .max_vid = 8191, 5954 .max_sid = 63, 5955 .port_base_addr = 0x0, 5956 .phy_base_addr = 0x0, 5957 .global1_addr = 0x1b, 5958 .global2_addr = 0x1c, 5959 .age_time_coeff = 3750, 5960 .g1_irqs = 9, 5961 .g2_irqs = 14, 5962 .atu_move_port_mask = 0x1f, 5963 .pvt = true, 5964 .multi_chip = true, 5965 .ops = &mv88e6190x_ops, 5966 }, 5967 5968 [MV88E6191] = { 5969 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5970 .family = MV88E6XXX_FAMILY_6390, 5971 .name = "Marvell 88E6191", 5972 .num_databases = 4096, 5973 .num_macs = 16384, 5974 .num_ports = 11, /* 10 + Z80 */ 5975 .num_internal_phys = 9, 5976 .max_vid = 8191, 5977 .max_sid = 63, 5978 .port_base_addr = 0x0, 5979 .phy_base_addr = 0x0, 5980 .global1_addr = 0x1b, 5981 .global2_addr = 0x1c, 5982 .age_time_coeff = 3750, 5983 .g1_irqs = 9, 5984 .g2_irqs = 14, 5985 .atu_move_port_mask = 0x1f, 5986 .pvt = true, 5987 .multi_chip = true, 5988 .ptp_support = true, 5989 .ops = &mv88e6191_ops, 5990 }, 5991 5992 [MV88E6191X] = { 5993 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5994 .family = MV88E6XXX_FAMILY_6393, 5995 .name = "Marvell 88E6191X", 5996 .num_databases = 4096, 5997 .num_ports = 11, /* 10 + Z80 */ 5998 .num_internal_phys = 8, 5999 .internal_phys_offset = 1, 6000 .max_vid = 8191, 6001 .max_sid = 63, 6002 .port_base_addr = 0x0, 6003 .phy_base_addr = 0x0, 6004 .global1_addr = 0x1b, 6005 .global2_addr = 0x1c, 6006 .age_time_coeff = 3750, 6007 .g1_irqs = 10, 6008 .g2_irqs = 14, 6009 .atu_move_port_mask = 0x1f, 6010 .pvt = true, 6011 .multi_chip = true, 6012 .ptp_support = true, 6013 .ops = &mv88e6393x_ops, 6014 }, 6015 6016 [MV88E6193X] = { 6017 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6018 .family = MV88E6XXX_FAMILY_6393, 6019 .name = "Marvell 88E6193X", 6020 .num_databases = 4096, 6021 .num_ports = 11, /* 10 + Z80 */ 6022 .num_internal_phys = 8, 6023 .internal_phys_offset = 1, 6024 .max_vid = 8191, 6025 .max_sid = 63, 6026 .port_base_addr = 0x0, 6027 .phy_base_addr = 0x0, 6028 .global1_addr = 0x1b, 6029 .global2_addr = 0x1c, 6030 .age_time_coeff = 3750, 6031 .g1_irqs = 10, 6032 .g2_irqs = 14, 6033 .atu_move_port_mask = 0x1f, 6034 .pvt = true, 6035 .multi_chip = true, 6036 .ptp_support = true, 6037 .ops = &mv88e6393x_ops, 6038 }, 6039 6040 [MV88E6220] = { 6041 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6042 .family = MV88E6XXX_FAMILY_6250, 6043 .name = "Marvell 88E6220", 6044 .num_databases = 64, 6045 6046 /* Ports 2-4 are not routed to pins 6047 * => usable ports 0, 1, 5, 6 6048 */ 6049 .num_ports = 7, 6050 .num_internal_phys = 2, 6051 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6052 .max_vid = 4095, 6053 .port_base_addr = 0x08, 6054 .phy_base_addr = 0x00, 6055 .global1_addr = 0x0f, 6056 .global2_addr = 0x07, 6057 .age_time_coeff = 15000, 6058 .g1_irqs = 9, 6059 .g2_irqs = 10, 6060 .atu_move_port_mask = 0xf, 6061 .dual_chip = true, 6062 .ptp_support = true, 6063 .ops = &mv88e6250_ops, 6064 }, 6065 6066 [MV88E6240] = { 6067 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6068 .family = MV88E6XXX_FAMILY_6352, 6069 .name = "Marvell 88E6240", 6070 .num_databases = 4096, 6071 .num_macs = 8192, 6072 .num_ports = 7, 6073 .num_internal_phys = 5, 6074 .num_gpio = 15, 6075 .max_vid = 4095, 6076 .max_sid = 63, 6077 .port_base_addr = 0x10, 6078 .phy_base_addr = 0x0, 6079 .global1_addr = 0x1b, 6080 .global2_addr = 0x1c, 6081 .age_time_coeff = 15000, 6082 .g1_irqs = 9, 6083 .g2_irqs = 10, 6084 .atu_move_port_mask = 0xf, 6085 .pvt = true, 6086 .multi_chip = true, 6087 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6088 .ptp_support = true, 6089 .ops = &mv88e6240_ops, 6090 }, 6091 6092 [MV88E6250] = { 6093 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6094 .family = MV88E6XXX_FAMILY_6250, 6095 .name = "Marvell 88E6250", 6096 .num_databases = 64, 6097 .num_ports = 7, 6098 .num_internal_phys = 5, 6099 .max_vid = 4095, 6100 .port_base_addr = 0x08, 6101 .phy_base_addr = 0x00, 6102 .global1_addr = 0x0f, 6103 .global2_addr = 0x07, 6104 .age_time_coeff = 15000, 6105 .g1_irqs = 9, 6106 .g2_irqs = 10, 6107 .atu_move_port_mask = 0xf, 6108 .dual_chip = true, 6109 .ptp_support = true, 6110 .ops = &mv88e6250_ops, 6111 }, 6112 6113 [MV88E6290] = { 6114 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6115 .family = MV88E6XXX_FAMILY_6390, 6116 .name = "Marvell 88E6290", 6117 .num_databases = 4096, 6118 .num_ports = 11, /* 10 + Z80 */ 6119 .num_internal_phys = 9, 6120 .num_gpio = 16, 6121 .max_vid = 8191, 6122 .max_sid = 63, 6123 .port_base_addr = 0x0, 6124 .phy_base_addr = 0x0, 6125 .global1_addr = 0x1b, 6126 .global2_addr = 0x1c, 6127 .age_time_coeff = 3750, 6128 .g1_irqs = 9, 6129 .g2_irqs = 14, 6130 .atu_move_port_mask = 0x1f, 6131 .pvt = true, 6132 .multi_chip = true, 6133 .ptp_support = true, 6134 .ops = &mv88e6290_ops, 6135 }, 6136 6137 [MV88E6320] = { 6138 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6139 .family = MV88E6XXX_FAMILY_6320, 6140 .name = "Marvell 88E6320", 6141 .num_databases = 4096, 6142 .num_macs = 8192, 6143 .num_ports = 7, 6144 .num_internal_phys = 5, 6145 .num_gpio = 15, 6146 .max_vid = 4095, 6147 .port_base_addr = 0x10, 6148 .phy_base_addr = 0x0, 6149 .global1_addr = 0x1b, 6150 .global2_addr = 0x1c, 6151 .age_time_coeff = 15000, 6152 .g1_irqs = 8, 6153 .g2_irqs = 10, 6154 .atu_move_port_mask = 0xf, 6155 .pvt = true, 6156 .multi_chip = true, 6157 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6158 .ptp_support = true, 6159 .ops = &mv88e6320_ops, 6160 }, 6161 6162 [MV88E6321] = { 6163 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6164 .family = MV88E6XXX_FAMILY_6320, 6165 .name = "Marvell 88E6321", 6166 .num_databases = 4096, 6167 .num_macs = 8192, 6168 .num_ports = 7, 6169 .num_internal_phys = 5, 6170 .num_gpio = 15, 6171 .max_vid = 4095, 6172 .port_base_addr = 0x10, 6173 .phy_base_addr = 0x0, 6174 .global1_addr = 0x1b, 6175 .global2_addr = 0x1c, 6176 .age_time_coeff = 15000, 6177 .g1_irqs = 8, 6178 .g2_irqs = 10, 6179 .atu_move_port_mask = 0xf, 6180 .multi_chip = true, 6181 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6182 .ptp_support = true, 6183 .ops = &mv88e6321_ops, 6184 }, 6185 6186 [MV88E6341] = { 6187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6188 .family = MV88E6XXX_FAMILY_6341, 6189 .name = "Marvell 88E6341", 6190 .num_databases = 256, 6191 .num_macs = 2048, 6192 .num_internal_phys = 5, 6193 .num_ports = 6, 6194 .num_gpio = 11, 6195 .max_vid = 4095, 6196 .max_sid = 63, 6197 .port_base_addr = 0x10, 6198 .phy_base_addr = 0x10, 6199 .global1_addr = 0x1b, 6200 .global2_addr = 0x1c, 6201 .age_time_coeff = 3750, 6202 .atu_move_port_mask = 0x1f, 6203 .g1_irqs = 9, 6204 .g2_irqs = 10, 6205 .pvt = true, 6206 .multi_chip = true, 6207 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6208 .ptp_support = true, 6209 .ops = &mv88e6341_ops, 6210 }, 6211 6212 [MV88E6350] = { 6213 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6214 .family = MV88E6XXX_FAMILY_6351, 6215 .name = "Marvell 88E6350", 6216 .num_databases = 4096, 6217 .num_macs = 8192, 6218 .num_ports = 7, 6219 .num_internal_phys = 5, 6220 .max_vid = 4095, 6221 .max_sid = 63, 6222 .port_base_addr = 0x10, 6223 .phy_base_addr = 0x0, 6224 .global1_addr = 0x1b, 6225 .global2_addr = 0x1c, 6226 .age_time_coeff = 15000, 6227 .g1_irqs = 9, 6228 .g2_irqs = 10, 6229 .atu_move_port_mask = 0xf, 6230 .pvt = true, 6231 .multi_chip = true, 6232 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6233 .ops = &mv88e6350_ops, 6234 }, 6235 6236 [MV88E6351] = { 6237 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6238 .family = MV88E6XXX_FAMILY_6351, 6239 .name = "Marvell 88E6351", 6240 .num_databases = 4096, 6241 .num_macs = 8192, 6242 .num_ports = 7, 6243 .num_internal_phys = 5, 6244 .max_vid = 4095, 6245 .max_sid = 63, 6246 .port_base_addr = 0x10, 6247 .phy_base_addr = 0x0, 6248 .global1_addr = 0x1b, 6249 .global2_addr = 0x1c, 6250 .age_time_coeff = 15000, 6251 .g1_irqs = 9, 6252 .g2_irqs = 10, 6253 .atu_move_port_mask = 0xf, 6254 .pvt = true, 6255 .multi_chip = true, 6256 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6257 .ops = &mv88e6351_ops, 6258 }, 6259 6260 [MV88E6352] = { 6261 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6262 .family = MV88E6XXX_FAMILY_6352, 6263 .name = "Marvell 88E6352", 6264 .num_databases = 4096, 6265 .num_macs = 8192, 6266 .num_ports = 7, 6267 .num_internal_phys = 5, 6268 .num_gpio = 15, 6269 .max_vid = 4095, 6270 .max_sid = 63, 6271 .port_base_addr = 0x10, 6272 .phy_base_addr = 0x0, 6273 .global1_addr = 0x1b, 6274 .global2_addr = 0x1c, 6275 .age_time_coeff = 15000, 6276 .g1_irqs = 9, 6277 .g2_irqs = 10, 6278 .atu_move_port_mask = 0xf, 6279 .pvt = true, 6280 .multi_chip = true, 6281 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6282 .ptp_support = true, 6283 .ops = &mv88e6352_ops, 6284 }, 6285 [MV88E6361] = { 6286 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6287 .family = MV88E6XXX_FAMILY_6393, 6288 .name = "Marvell 88E6361", 6289 .num_databases = 4096, 6290 .num_macs = 16384, 6291 .num_ports = 11, 6292 /* Ports 1, 2 and 8 are not routed */ 6293 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6294 .num_internal_phys = 5, 6295 .internal_phys_offset = 3, 6296 .max_vid = 4095, 6297 .max_sid = 63, 6298 .port_base_addr = 0x0, 6299 .phy_base_addr = 0x0, 6300 .global1_addr = 0x1b, 6301 .global2_addr = 0x1c, 6302 .age_time_coeff = 3750, 6303 .g1_irqs = 10, 6304 .g2_irqs = 14, 6305 .atu_move_port_mask = 0x1f, 6306 .pvt = true, 6307 .multi_chip = true, 6308 .ptp_support = true, 6309 .ops = &mv88e6393x_ops, 6310 }, 6311 [MV88E6390] = { 6312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6313 .family = MV88E6XXX_FAMILY_6390, 6314 .name = "Marvell 88E6390", 6315 .num_databases = 4096, 6316 .num_macs = 16384, 6317 .num_ports = 11, /* 10 + Z80 */ 6318 .num_internal_phys = 9, 6319 .num_gpio = 16, 6320 .max_vid = 8191, 6321 .max_sid = 63, 6322 .port_base_addr = 0x0, 6323 .phy_base_addr = 0x0, 6324 .global1_addr = 0x1b, 6325 .global2_addr = 0x1c, 6326 .age_time_coeff = 3750, 6327 .g1_irqs = 9, 6328 .g2_irqs = 14, 6329 .atu_move_port_mask = 0x1f, 6330 .pvt = true, 6331 .multi_chip = true, 6332 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6333 .ptp_support = true, 6334 .ops = &mv88e6390_ops, 6335 }, 6336 [MV88E6390X] = { 6337 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6338 .family = MV88E6XXX_FAMILY_6390, 6339 .name = "Marvell 88E6390X", 6340 .num_databases = 4096, 6341 .num_macs = 16384, 6342 .num_ports = 11, /* 10 + Z80 */ 6343 .num_internal_phys = 9, 6344 .num_gpio = 16, 6345 .max_vid = 8191, 6346 .max_sid = 63, 6347 .port_base_addr = 0x0, 6348 .phy_base_addr = 0x0, 6349 .global1_addr = 0x1b, 6350 .global2_addr = 0x1c, 6351 .age_time_coeff = 3750, 6352 .g1_irqs = 9, 6353 .g2_irqs = 14, 6354 .atu_move_port_mask = 0x1f, 6355 .pvt = true, 6356 .multi_chip = true, 6357 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6358 .ptp_support = true, 6359 .ops = &mv88e6390x_ops, 6360 }, 6361 6362 [MV88E6393X] = { 6363 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6364 .family = MV88E6XXX_FAMILY_6393, 6365 .name = "Marvell 88E6393X", 6366 .num_databases = 4096, 6367 .num_ports = 11, /* 10 + Z80 */ 6368 .num_internal_phys = 8, 6369 .internal_phys_offset = 1, 6370 .max_vid = 8191, 6371 .max_sid = 63, 6372 .port_base_addr = 0x0, 6373 .phy_base_addr = 0x0, 6374 .global1_addr = 0x1b, 6375 .global2_addr = 0x1c, 6376 .age_time_coeff = 3750, 6377 .g1_irqs = 10, 6378 .g2_irqs = 14, 6379 .atu_move_port_mask = 0x1f, 6380 .pvt = true, 6381 .multi_chip = true, 6382 .ptp_support = true, 6383 .ops = &mv88e6393x_ops, 6384 }, 6385 }; 6386 6387 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6388 { 6389 int i; 6390 6391 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6392 if (mv88e6xxx_table[i].prod_num == prod_num) 6393 return &mv88e6xxx_table[i]; 6394 6395 return NULL; 6396 } 6397 6398 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6399 { 6400 const struct mv88e6xxx_info *info; 6401 unsigned int prod_num, rev; 6402 u16 id; 6403 int err; 6404 6405 mv88e6xxx_reg_lock(chip); 6406 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6407 mv88e6xxx_reg_unlock(chip); 6408 if (err) 6409 return err; 6410 6411 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6412 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6413 6414 info = mv88e6xxx_lookup_info(prod_num); 6415 if (!info) 6416 return -ENODEV; 6417 6418 /* Update the compatible info with the probed one */ 6419 chip->info = info; 6420 6421 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6422 chip->info->prod_num, chip->info->name, rev); 6423 6424 return 0; 6425 } 6426 6427 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6428 struct mdio_device *mdiodev) 6429 { 6430 int err; 6431 6432 /* dual_chip takes precedence over single/multi-chip modes */ 6433 if (chip->info->dual_chip) 6434 return -EINVAL; 6435 6436 /* If the mdio addr is 16 indicating the first port address of a switch 6437 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6438 * configured in single chip addressing mode. Setup the smi access as 6439 * single chip addressing mode and attempt to detect the model of the 6440 * switch, if this fails the device is not configured in single chip 6441 * addressing mode. 6442 */ 6443 if (mdiodev->addr != 16) 6444 return -EINVAL; 6445 6446 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6447 if (err) 6448 return err; 6449 6450 return mv88e6xxx_detect(chip); 6451 } 6452 6453 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6454 { 6455 struct mv88e6xxx_chip *chip; 6456 6457 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6458 if (!chip) 6459 return NULL; 6460 6461 chip->dev = dev; 6462 6463 mutex_init(&chip->reg_lock); 6464 INIT_LIST_HEAD(&chip->mdios); 6465 idr_init(&chip->policies); 6466 INIT_LIST_HEAD(&chip->msts); 6467 6468 return chip; 6469 } 6470 6471 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6472 int port, 6473 enum dsa_tag_protocol m) 6474 { 6475 struct mv88e6xxx_chip *chip = ds->priv; 6476 6477 return chip->tag_protocol; 6478 } 6479 6480 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6481 enum dsa_tag_protocol proto) 6482 { 6483 struct mv88e6xxx_chip *chip = ds->priv; 6484 enum dsa_tag_protocol old_protocol; 6485 struct dsa_port *cpu_dp; 6486 int err; 6487 6488 switch (proto) { 6489 case DSA_TAG_PROTO_EDSA: 6490 switch (chip->info->edsa_support) { 6491 case MV88E6XXX_EDSA_UNSUPPORTED: 6492 return -EPROTONOSUPPORT; 6493 case MV88E6XXX_EDSA_UNDOCUMENTED: 6494 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6495 fallthrough; 6496 case MV88E6XXX_EDSA_SUPPORTED: 6497 break; 6498 } 6499 break; 6500 case DSA_TAG_PROTO_DSA: 6501 break; 6502 default: 6503 return -EPROTONOSUPPORT; 6504 } 6505 6506 old_protocol = chip->tag_protocol; 6507 chip->tag_protocol = proto; 6508 6509 mv88e6xxx_reg_lock(chip); 6510 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6511 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6512 if (err) { 6513 mv88e6xxx_reg_unlock(chip); 6514 goto unwind; 6515 } 6516 } 6517 mv88e6xxx_reg_unlock(chip); 6518 6519 return 0; 6520 6521 unwind: 6522 chip->tag_protocol = old_protocol; 6523 6524 mv88e6xxx_reg_lock(chip); 6525 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6526 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6527 mv88e6xxx_reg_unlock(chip); 6528 6529 return err; 6530 } 6531 6532 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6533 const struct switchdev_obj_port_mdb *mdb, 6534 struct dsa_db db) 6535 { 6536 struct mv88e6xxx_chip *chip = ds->priv; 6537 int err; 6538 6539 mv88e6xxx_reg_lock(chip); 6540 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6541 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6542 mv88e6xxx_reg_unlock(chip); 6543 6544 return err; 6545 } 6546 6547 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6548 const struct switchdev_obj_port_mdb *mdb, 6549 struct dsa_db db) 6550 { 6551 struct mv88e6xxx_chip *chip = ds->priv; 6552 int err; 6553 6554 mv88e6xxx_reg_lock(chip); 6555 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6556 mv88e6xxx_reg_unlock(chip); 6557 6558 return err; 6559 } 6560 6561 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6562 struct dsa_mall_mirror_tc_entry *mirror, 6563 bool ingress, 6564 struct netlink_ext_ack *extack) 6565 { 6566 enum mv88e6xxx_egress_direction direction = ingress ? 6567 MV88E6XXX_EGRESS_DIR_INGRESS : 6568 MV88E6XXX_EGRESS_DIR_EGRESS; 6569 struct mv88e6xxx_chip *chip = ds->priv; 6570 bool other_mirrors = false; 6571 int i; 6572 int err; 6573 6574 mutex_lock(&chip->reg_lock); 6575 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6576 mirror->to_local_port) { 6577 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6578 other_mirrors |= ingress ? 6579 chip->ports[i].mirror_ingress : 6580 chip->ports[i].mirror_egress; 6581 6582 /* Can't change egress port when other mirror is active */ 6583 if (other_mirrors) { 6584 err = -EBUSY; 6585 goto out; 6586 } 6587 6588 err = mv88e6xxx_set_egress_port(chip, direction, 6589 mirror->to_local_port); 6590 if (err) 6591 goto out; 6592 } 6593 6594 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6595 out: 6596 mutex_unlock(&chip->reg_lock); 6597 6598 return err; 6599 } 6600 6601 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6602 struct dsa_mall_mirror_tc_entry *mirror) 6603 { 6604 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6605 MV88E6XXX_EGRESS_DIR_INGRESS : 6606 MV88E6XXX_EGRESS_DIR_EGRESS; 6607 struct mv88e6xxx_chip *chip = ds->priv; 6608 bool other_mirrors = false; 6609 int i; 6610 6611 mutex_lock(&chip->reg_lock); 6612 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6613 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6614 6615 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6616 other_mirrors |= mirror->ingress ? 6617 chip->ports[i].mirror_ingress : 6618 chip->ports[i].mirror_egress; 6619 6620 /* Reset egress port when no other mirror is active */ 6621 if (!other_mirrors) { 6622 if (mv88e6xxx_set_egress_port(chip, direction, 6623 dsa_upstream_port(ds, port))) 6624 dev_err(ds->dev, "failed to set egress port\n"); 6625 } 6626 6627 mutex_unlock(&chip->reg_lock); 6628 } 6629 6630 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6631 struct switchdev_brport_flags flags, 6632 struct netlink_ext_ack *extack) 6633 { 6634 struct mv88e6xxx_chip *chip = ds->priv; 6635 const struct mv88e6xxx_ops *ops; 6636 6637 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6638 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6639 return -EINVAL; 6640 6641 ops = chip->info->ops; 6642 6643 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6644 return -EINVAL; 6645 6646 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6647 return -EINVAL; 6648 6649 return 0; 6650 } 6651 6652 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6653 struct switchdev_brport_flags flags, 6654 struct netlink_ext_ack *extack) 6655 { 6656 struct mv88e6xxx_chip *chip = ds->priv; 6657 int err = 0; 6658 6659 mv88e6xxx_reg_lock(chip); 6660 6661 if (flags.mask & BR_LEARNING) { 6662 bool learning = !!(flags.val & BR_LEARNING); 6663 u16 pav = learning ? (1 << port) : 0; 6664 6665 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6666 if (err) 6667 goto out; 6668 } 6669 6670 if (flags.mask & BR_FLOOD) { 6671 bool unicast = !!(flags.val & BR_FLOOD); 6672 6673 err = chip->info->ops->port_set_ucast_flood(chip, port, 6674 unicast); 6675 if (err) 6676 goto out; 6677 } 6678 6679 if (flags.mask & BR_MCAST_FLOOD) { 6680 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6681 6682 err = chip->info->ops->port_set_mcast_flood(chip, port, 6683 multicast); 6684 if (err) 6685 goto out; 6686 } 6687 6688 if (flags.mask & BR_BCAST_FLOOD) { 6689 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6690 6691 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6692 if (err) 6693 goto out; 6694 } 6695 6696 if (flags.mask & BR_PORT_MAB) { 6697 bool mab = !!(flags.val & BR_PORT_MAB); 6698 6699 mv88e6xxx_port_set_mab(chip, port, mab); 6700 } 6701 6702 if (flags.mask & BR_PORT_LOCKED) { 6703 bool locked = !!(flags.val & BR_PORT_LOCKED); 6704 6705 err = mv88e6xxx_port_set_lock(chip, port, locked); 6706 if (err) 6707 goto out; 6708 } 6709 out: 6710 mv88e6xxx_reg_unlock(chip); 6711 6712 return err; 6713 } 6714 6715 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6716 struct dsa_lag lag, 6717 struct netdev_lag_upper_info *info, 6718 struct netlink_ext_ack *extack) 6719 { 6720 struct mv88e6xxx_chip *chip = ds->priv; 6721 struct dsa_port *dp; 6722 int members = 0; 6723 6724 if (!mv88e6xxx_has_lag(chip)) { 6725 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6726 return false; 6727 } 6728 6729 if (!lag.id) 6730 return false; 6731 6732 dsa_lag_foreach_port(dp, ds->dst, &lag) 6733 /* Includes the port joining the LAG */ 6734 members++; 6735 6736 if (members > 8) { 6737 NL_SET_ERR_MSG_MOD(extack, 6738 "Cannot offload more than 8 LAG ports"); 6739 return false; 6740 } 6741 6742 /* We could potentially relax this to include active 6743 * backup in the future. 6744 */ 6745 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6746 NL_SET_ERR_MSG_MOD(extack, 6747 "Can only offload LAG using hash TX type"); 6748 return false; 6749 } 6750 6751 /* Ideally we would also validate that the hash type matches 6752 * the hardware. Alas, this is always set to unknown on team 6753 * interfaces. 6754 */ 6755 return true; 6756 } 6757 6758 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6759 { 6760 struct mv88e6xxx_chip *chip = ds->priv; 6761 struct dsa_port *dp; 6762 u16 map = 0; 6763 int id; 6764 6765 /* DSA LAG IDs are one-based, hardware is zero-based */ 6766 id = lag.id - 1; 6767 6768 /* Build the map of all ports to distribute flows destined for 6769 * this LAG. This can be either a local user port, or a DSA 6770 * port if the LAG port is on a remote chip. 6771 */ 6772 dsa_lag_foreach_port(dp, ds->dst, &lag) 6773 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6774 6775 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6776 } 6777 6778 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6779 /* Row number corresponds to the number of active members in a 6780 * LAG. Each column states which of the eight hash buckets are 6781 * mapped to the column:th port in the LAG. 6782 * 6783 * Example: In a LAG with three active ports, the second port 6784 * ([2][1]) would be selected for traffic mapped to buckets 6785 * 3,4,5 (0x38). 6786 */ 6787 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6788 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6789 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6790 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6791 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6792 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6793 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6794 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6795 }; 6796 6797 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6798 int num_tx, int nth) 6799 { 6800 u8 active = 0; 6801 int i; 6802 6803 num_tx = num_tx <= 8 ? num_tx : 8; 6804 if (nth < num_tx) 6805 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6806 6807 for (i = 0; i < 8; i++) { 6808 if (BIT(i) & active) 6809 mask[i] |= BIT(port); 6810 } 6811 } 6812 6813 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6814 { 6815 struct mv88e6xxx_chip *chip = ds->priv; 6816 unsigned int id, num_tx; 6817 struct dsa_port *dp; 6818 struct dsa_lag *lag; 6819 int i, err, nth; 6820 u16 mask[8]; 6821 u16 ivec; 6822 6823 /* Assume no port is a member of any LAG. */ 6824 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6825 6826 /* Disable all masks for ports that _are_ members of a LAG. */ 6827 dsa_switch_for_each_port(dp, ds) { 6828 if (!dp->lag) 6829 continue; 6830 6831 ivec &= ~BIT(dp->index); 6832 } 6833 6834 for (i = 0; i < 8; i++) 6835 mask[i] = ivec; 6836 6837 /* Enable the correct subset of masks for all LAG ports that 6838 * are in the Tx set. 6839 */ 6840 dsa_lags_foreach_id(id, ds->dst) { 6841 lag = dsa_lag_by_id(ds->dst, id); 6842 if (!lag) 6843 continue; 6844 6845 num_tx = 0; 6846 dsa_lag_foreach_port(dp, ds->dst, lag) { 6847 if (dp->lag_tx_enabled) 6848 num_tx++; 6849 } 6850 6851 if (!num_tx) 6852 continue; 6853 6854 nth = 0; 6855 dsa_lag_foreach_port(dp, ds->dst, lag) { 6856 if (!dp->lag_tx_enabled) 6857 continue; 6858 6859 if (dp->ds == ds) 6860 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6861 num_tx, nth); 6862 6863 nth++; 6864 } 6865 } 6866 6867 for (i = 0; i < 8; i++) { 6868 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6869 if (err) 6870 return err; 6871 } 6872 6873 return 0; 6874 } 6875 6876 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6877 struct dsa_lag lag) 6878 { 6879 int err; 6880 6881 err = mv88e6xxx_lag_sync_masks(ds); 6882 6883 if (!err) 6884 err = mv88e6xxx_lag_sync_map(ds, lag); 6885 6886 return err; 6887 } 6888 6889 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6890 { 6891 struct mv88e6xxx_chip *chip = ds->priv; 6892 int err; 6893 6894 mv88e6xxx_reg_lock(chip); 6895 err = mv88e6xxx_lag_sync_masks(ds); 6896 mv88e6xxx_reg_unlock(chip); 6897 return err; 6898 } 6899 6900 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6901 struct dsa_lag lag, 6902 struct netdev_lag_upper_info *info, 6903 struct netlink_ext_ack *extack) 6904 { 6905 struct mv88e6xxx_chip *chip = ds->priv; 6906 int err, id; 6907 6908 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6909 return -EOPNOTSUPP; 6910 6911 /* DSA LAG IDs are one-based */ 6912 id = lag.id - 1; 6913 6914 mv88e6xxx_reg_lock(chip); 6915 6916 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6917 if (err) 6918 goto err_unlock; 6919 6920 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6921 if (err) 6922 goto err_clear_trunk; 6923 6924 mv88e6xxx_reg_unlock(chip); 6925 return 0; 6926 6927 err_clear_trunk: 6928 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6929 err_unlock: 6930 mv88e6xxx_reg_unlock(chip); 6931 return err; 6932 } 6933 6934 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6935 struct dsa_lag lag) 6936 { 6937 struct mv88e6xxx_chip *chip = ds->priv; 6938 int err_sync, err_trunk; 6939 6940 mv88e6xxx_reg_lock(chip); 6941 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6942 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6943 mv88e6xxx_reg_unlock(chip); 6944 return err_sync ? : err_trunk; 6945 } 6946 6947 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6948 int port) 6949 { 6950 struct mv88e6xxx_chip *chip = ds->priv; 6951 int err; 6952 6953 mv88e6xxx_reg_lock(chip); 6954 err = mv88e6xxx_lag_sync_masks(ds); 6955 mv88e6xxx_reg_unlock(chip); 6956 return err; 6957 } 6958 6959 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6960 int port, struct dsa_lag lag, 6961 struct netdev_lag_upper_info *info, 6962 struct netlink_ext_ack *extack) 6963 { 6964 struct mv88e6xxx_chip *chip = ds->priv; 6965 int err; 6966 6967 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6968 return -EOPNOTSUPP; 6969 6970 mv88e6xxx_reg_lock(chip); 6971 6972 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6973 if (err) 6974 goto unlock; 6975 6976 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6977 6978 unlock: 6979 mv88e6xxx_reg_unlock(chip); 6980 return err; 6981 } 6982 6983 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6984 int port, struct dsa_lag lag) 6985 { 6986 struct mv88e6xxx_chip *chip = ds->priv; 6987 int err_sync, err_pvt; 6988 6989 mv88e6xxx_reg_lock(chip); 6990 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6991 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6992 mv88e6xxx_reg_unlock(chip); 6993 return err_sync ? : err_pvt; 6994 } 6995 6996 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6997 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6998 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6999 .setup = mv88e6xxx_setup, 7000 .teardown = mv88e6xxx_teardown, 7001 .port_setup = mv88e6xxx_port_setup, 7002 .port_teardown = mv88e6xxx_port_teardown, 7003 .phylink_get_caps = mv88e6xxx_get_caps, 7004 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, 7005 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 7006 .phylink_mac_config = mv88e6xxx_mac_config, 7007 .phylink_mac_finish = mv88e6xxx_mac_finish, 7008 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7009 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7010 .get_strings = mv88e6xxx_get_strings, 7011 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7012 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7013 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7014 .get_sset_count = mv88e6xxx_get_sset_count, 7015 .port_max_mtu = mv88e6xxx_get_max_mtu, 7016 .port_change_mtu = mv88e6xxx_change_mtu, 7017 .get_mac_eee = mv88e6xxx_get_mac_eee, 7018 .set_mac_eee = mv88e6xxx_set_mac_eee, 7019 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7020 .get_eeprom = mv88e6xxx_get_eeprom, 7021 .set_eeprom = mv88e6xxx_set_eeprom, 7022 .get_regs_len = mv88e6xxx_get_regs_len, 7023 .get_regs = mv88e6xxx_get_regs, 7024 .get_rxnfc = mv88e6xxx_get_rxnfc, 7025 .set_rxnfc = mv88e6xxx_set_rxnfc, 7026 .set_ageing_time = mv88e6xxx_set_ageing_time, 7027 .port_bridge_join = mv88e6xxx_port_bridge_join, 7028 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7029 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7030 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7031 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7032 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7033 .port_fast_age = mv88e6xxx_port_fast_age, 7034 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7035 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7036 .port_vlan_add = mv88e6xxx_port_vlan_add, 7037 .port_vlan_del = mv88e6xxx_port_vlan_del, 7038 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7039 .port_fdb_add = mv88e6xxx_port_fdb_add, 7040 .port_fdb_del = mv88e6xxx_port_fdb_del, 7041 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7042 .port_mdb_add = mv88e6xxx_port_mdb_add, 7043 .port_mdb_del = mv88e6xxx_port_mdb_del, 7044 .port_mirror_add = mv88e6xxx_port_mirror_add, 7045 .port_mirror_del = mv88e6xxx_port_mirror_del, 7046 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7047 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7048 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7049 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7050 .port_txtstamp = mv88e6xxx_port_txtstamp, 7051 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7052 .get_ts_info = mv88e6xxx_get_ts_info, 7053 .devlink_param_get = mv88e6xxx_devlink_param_get, 7054 .devlink_param_set = mv88e6xxx_devlink_param_set, 7055 .devlink_info_get = mv88e6xxx_devlink_info_get, 7056 .port_lag_change = mv88e6xxx_port_lag_change, 7057 .port_lag_join = mv88e6xxx_port_lag_join, 7058 .port_lag_leave = mv88e6xxx_port_lag_leave, 7059 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7060 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7061 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7062 }; 7063 7064 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7065 { 7066 struct device *dev = chip->dev; 7067 struct dsa_switch *ds; 7068 7069 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7070 if (!ds) 7071 return -ENOMEM; 7072 7073 ds->dev = dev; 7074 ds->num_ports = mv88e6xxx_num_ports(chip); 7075 ds->priv = chip; 7076 ds->dev = dev; 7077 ds->ops = &mv88e6xxx_switch_ops; 7078 ds->ageing_time_min = chip->info->age_time_coeff; 7079 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7080 7081 /* Some chips support up to 32, but that requires enabling the 7082 * 5-bit port mode, which we do not support. 640k^W16 ought to 7083 * be enough for anyone. 7084 */ 7085 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7086 7087 dev_set_drvdata(dev, ds); 7088 7089 return dsa_register_switch(ds); 7090 } 7091 7092 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7093 { 7094 dsa_unregister_switch(chip->ds); 7095 } 7096 7097 static const void *pdata_device_get_match_data(struct device *dev) 7098 { 7099 const struct of_device_id *matches = dev->driver->of_match_table; 7100 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7101 7102 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7103 matches++) { 7104 if (!strcmp(pdata->compatible, matches->compatible)) 7105 return matches->data; 7106 } 7107 return NULL; 7108 } 7109 7110 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7111 * would be lost after a power cycle so prevent it to be suspended. 7112 */ 7113 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7114 { 7115 return -EOPNOTSUPP; 7116 } 7117 7118 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7119 { 7120 return 0; 7121 } 7122 7123 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7124 7125 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7126 { 7127 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7128 const struct mv88e6xxx_info *compat_info = NULL; 7129 struct device *dev = &mdiodev->dev; 7130 struct device_node *np = dev->of_node; 7131 struct mv88e6xxx_chip *chip; 7132 int port; 7133 int err; 7134 7135 if (!np && !pdata) 7136 return -EINVAL; 7137 7138 if (np) 7139 compat_info = of_device_get_match_data(dev); 7140 7141 if (pdata) { 7142 compat_info = pdata_device_get_match_data(dev); 7143 7144 if (!pdata->netdev) 7145 return -EINVAL; 7146 7147 for (port = 0; port < DSA_MAX_PORTS; port++) { 7148 if (!(pdata->enabled_ports & (1 << port))) 7149 continue; 7150 if (strcmp(pdata->cd.port_names[port], "cpu")) 7151 continue; 7152 pdata->cd.netdev[port] = &pdata->netdev->dev; 7153 break; 7154 } 7155 } 7156 7157 if (!compat_info) 7158 return -EINVAL; 7159 7160 chip = mv88e6xxx_alloc_chip(dev); 7161 if (!chip) { 7162 err = -ENOMEM; 7163 goto out; 7164 } 7165 7166 chip->info = compat_info; 7167 7168 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7169 if (IS_ERR(chip->reset)) { 7170 err = PTR_ERR(chip->reset); 7171 goto out; 7172 } 7173 if (chip->reset) 7174 usleep_range(10000, 20000); 7175 7176 /* Detect if the device is configured in single chip addressing mode, 7177 * otherwise continue with address specific smi init/detection. 7178 */ 7179 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7180 if (err) { 7181 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7182 if (err) 7183 goto out; 7184 7185 err = mv88e6xxx_detect(chip); 7186 if (err) 7187 goto out; 7188 } 7189 7190 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7191 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7192 else 7193 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7194 7195 mv88e6xxx_phy_init(chip); 7196 7197 if (chip->info->ops->get_eeprom) { 7198 if (np) 7199 of_property_read_u32(np, "eeprom-length", 7200 &chip->eeprom_len); 7201 else 7202 chip->eeprom_len = pdata->eeprom_len; 7203 } 7204 7205 mv88e6xxx_reg_lock(chip); 7206 err = mv88e6xxx_switch_reset(chip); 7207 mv88e6xxx_reg_unlock(chip); 7208 if (err) 7209 goto out; 7210 7211 if (np) { 7212 chip->irq = of_irq_get(np, 0); 7213 if (chip->irq == -EPROBE_DEFER) { 7214 err = chip->irq; 7215 goto out; 7216 } 7217 } 7218 7219 if (pdata) 7220 chip->irq = pdata->irq; 7221 7222 /* Has to be performed before the MDIO bus is created, because 7223 * the PHYs will link their interrupts to these interrupt 7224 * controllers 7225 */ 7226 mv88e6xxx_reg_lock(chip); 7227 if (chip->irq > 0) 7228 err = mv88e6xxx_g1_irq_setup(chip); 7229 else 7230 err = mv88e6xxx_irq_poll_setup(chip); 7231 mv88e6xxx_reg_unlock(chip); 7232 7233 if (err) 7234 goto out; 7235 7236 if (chip->info->g2_irqs > 0) { 7237 err = mv88e6xxx_g2_irq_setup(chip); 7238 if (err) 7239 goto out_g1_irq; 7240 } 7241 7242 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7243 if (err) 7244 goto out_g2_irq; 7245 7246 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7247 if (err) 7248 goto out_g1_atu_prob_irq; 7249 7250 err = mv88e6xxx_register_switch(chip); 7251 if (err) 7252 goto out_g1_vtu_prob_irq; 7253 7254 return 0; 7255 7256 out_g1_vtu_prob_irq: 7257 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7258 out_g1_atu_prob_irq: 7259 mv88e6xxx_g1_atu_prob_irq_free(chip); 7260 out_g2_irq: 7261 if (chip->info->g2_irqs > 0) 7262 mv88e6xxx_g2_irq_free(chip); 7263 out_g1_irq: 7264 if (chip->irq > 0) 7265 mv88e6xxx_g1_irq_free(chip); 7266 else 7267 mv88e6xxx_irq_poll_free(chip); 7268 out: 7269 if (pdata) 7270 dev_put(pdata->netdev); 7271 7272 return err; 7273 } 7274 7275 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7276 { 7277 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7278 struct mv88e6xxx_chip *chip; 7279 7280 if (!ds) 7281 return; 7282 7283 chip = ds->priv; 7284 7285 if (chip->info->ptp_support) { 7286 mv88e6xxx_hwtstamp_free(chip); 7287 mv88e6xxx_ptp_free(chip); 7288 } 7289 7290 mv88e6xxx_phy_destroy(chip); 7291 mv88e6xxx_unregister_switch(chip); 7292 7293 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7294 mv88e6xxx_g1_atu_prob_irq_free(chip); 7295 7296 if (chip->info->g2_irqs > 0) 7297 mv88e6xxx_g2_irq_free(chip); 7298 7299 if (chip->irq > 0) 7300 mv88e6xxx_g1_irq_free(chip); 7301 else 7302 mv88e6xxx_irq_poll_free(chip); 7303 } 7304 7305 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7306 { 7307 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7308 7309 if (!ds) 7310 return; 7311 7312 dsa_switch_shutdown(ds); 7313 7314 dev_set_drvdata(&mdiodev->dev, NULL); 7315 } 7316 7317 static const struct of_device_id mv88e6xxx_of_match[] = { 7318 { 7319 .compatible = "marvell,mv88e6085", 7320 .data = &mv88e6xxx_table[MV88E6085], 7321 }, 7322 { 7323 .compatible = "marvell,mv88e6190", 7324 .data = &mv88e6xxx_table[MV88E6190], 7325 }, 7326 { 7327 .compatible = "marvell,mv88e6250", 7328 .data = &mv88e6xxx_table[MV88E6250], 7329 }, 7330 { /* sentinel */ }, 7331 }; 7332 7333 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7334 7335 static struct mdio_driver mv88e6xxx_driver = { 7336 .probe = mv88e6xxx_probe, 7337 .remove = mv88e6xxx_remove, 7338 .shutdown = mv88e6xxx_shutdown, 7339 .mdiodrv.driver = { 7340 .name = "mv88e6085", 7341 .of_match_table = mv88e6xxx_of_match, 7342 .pm = &mv88e6xxx_pm_ops, 7343 }, 7344 }; 7345 7346 mdio_module_driver(mv88e6xxx_driver); 7347 7348 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7349 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7350 MODULE_LICENSE("GPL"); 7351