1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_create_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t **data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i; 1161 1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) 1165 ethtool_puts(data, stat->string); 1166 } 1167 } 1168 1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t **data) 1171 { 1172 mv88e6xxx_stats_get_strings(chip, data, 1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1174 } 1175 1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1177 uint8_t **data) 1178 { 1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1180 } 1181 1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1183 uint8_t **data) 1184 { 1185 mv88e6xxx_stats_get_strings(chip, data, 1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1187 } 1188 1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1190 "atu_member_violation", 1191 "atu_miss_violation", 1192 "atu_full_violation", 1193 "vtu_member_violation", 1194 "vtu_miss_violation", 1195 }; 1196 1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1203 } 1204 1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1206 u32 stringset, uint8_t *data) 1207 { 1208 struct mv88e6xxx_chip *chip = ds->priv; 1209 1210 if (stringset != ETH_SS_STATS) 1211 return; 1212 1213 mv88e6xxx_reg_lock(chip); 1214 1215 if (chip->info->ops->stats_get_strings) 1216 chip->info->ops->stats_get_strings(chip, &data); 1217 1218 if (chip->info->ops->serdes_get_strings) 1219 chip->info->ops->serdes_get_strings(chip, port, &data); 1220 1221 mv88e6xxx_atu_vtu_get_strings(&data); 1222 1223 mv88e6xxx_reg_unlock(chip); 1224 } 1225 1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1227 int types) 1228 { 1229 const struct mv88e6xxx_hw_stat *stat; 1230 int i, j; 1231 1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1233 stat = &mv88e6xxx_hw_stats[i]; 1234 if (stat->type & types) 1235 j++; 1236 } 1237 return j; 1238 } 1239 1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1241 { 1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1243 STATS_TYPE_PORT); 1244 } 1245 1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1247 { 1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1249 } 1250 1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_BANK1); 1255 } 1256 1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1258 { 1259 struct mv88e6xxx_chip *chip = ds->priv; 1260 int serdes_count = 0; 1261 int count = 0; 1262 1263 if (sset != ETH_SS_STATS) 1264 return 0; 1265 1266 mv88e6xxx_reg_lock(chip); 1267 if (chip->info->ops->stats_get_sset_count) 1268 count = chip->info->ops->stats_get_sset_count(chip); 1269 if (count < 0) 1270 goto out; 1271 1272 if (chip->info->ops->serdes_get_sset_count) 1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1274 port); 1275 if (serdes_count < 0) { 1276 count = serdes_count; 1277 goto out; 1278 } 1279 count += serdes_count; 1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1281 1282 out: 1283 mv88e6xxx_reg_unlock(chip); 1284 1285 return count; 1286 } 1287 1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1289 const struct mv88e6xxx_hw_stat *stat, 1290 uint64_t *data) 1291 { 1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1293 MV88E6XXX_G1_STATS_OP_HIST_RX); 1294 return 1; 1295 } 1296 1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1298 const struct mv88e6xxx_hw_stat *stat, 1299 uint64_t *data) 1300 { 1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1302 MV88E6XXX_G1_STATS_OP_HIST_RX); 1303 return 1; 1304 } 1305 1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1307 const struct mv88e6xxx_hw_stat *stat, 1308 uint64_t *data) 1309 { 1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1312 MV88E6XXX_G1_STATS_OP_HIST_RX); 1313 return 1; 1314 } 1315 1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1317 const struct mv88e6xxx_hw_stat *stat, 1318 uint64_t *data) 1319 { 1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1322 0); 1323 return 1; 1324 } 1325 1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1327 const struct mv88e6xxx_hw_stat *stat, 1328 uint64_t *data) 1329 { 1330 int ret = 0; 1331 1332 if (!(stat->type & chip->info->stats_type)) 1333 return 0; 1334 1335 if (chip->info->ops->stats_get_stat) { 1336 mv88e6xxx_reg_lock(chip); 1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 return ret; 1342 } 1343 1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1345 uint64_t *data) 1346 { 1347 const struct mv88e6xxx_hw_stat *stat; 1348 size_t i, j; 1349 1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1351 stat = &mv88e6xxx_hw_stats[i]; 1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1353 } 1354 return j; 1355 } 1356 1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1358 uint64_t *data) 1359 { 1360 *data++ = chip->ports[port].atu_member_violation; 1361 *data++ = chip->ports[port].atu_miss_violation; 1362 *data++ = chip->ports[port].atu_full_violation; 1363 *data++ = chip->ports[port].vtu_member_violation; 1364 *data++ = chip->ports[port].vtu_miss_violation; 1365 } 1366 1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1368 uint64_t *data) 1369 { 1370 size_t count; 1371 1372 count = mv88e6xxx_stats_get_stats(chip, port, data); 1373 1374 mv88e6xxx_reg_lock(chip); 1375 if (chip->info->ops->serdes_get_stats) { 1376 data += count; 1377 count = chip->info->ops->serdes_get_stats(chip, port, data); 1378 } 1379 data += count; 1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1381 mv88e6xxx_reg_unlock(chip); 1382 } 1383 1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1385 uint64_t *data) 1386 { 1387 struct mv88e6xxx_chip *chip = ds->priv; 1388 int ret; 1389 1390 ret = mv88e6xxx_stats_snapshot(chip, port); 1391 if (ret < 0) 1392 return; 1393 1394 mv88e6xxx_get_stats(chip, port, data); 1395 } 1396 1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1398 struct ethtool_eth_mac_stats *mac_stats) 1399 { 1400 struct mv88e6xxx_chip *chip = ds->priv; 1401 int ret; 1402 1403 ret = mv88e6xxx_stats_snapshot(chip, port); 1404 if (ret < 0) 1405 return; 1406 1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1408 mv88e6xxx_stats_get_stat(chip, port, \ 1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1410 &mac_stats->stats._member) 1411 1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1426 1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1428 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1433 } 1434 1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1436 struct ethtool_rmon_stats *rmon_stats, 1437 const struct ethtool_rmon_hist_range **ranges) 1438 { 1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1440 { 64, 64 }, 1441 { 65, 127 }, 1442 { 128, 255 }, 1443 { 256, 511 }, 1444 { 512, 1023 }, 1445 { 1024, 65535 }, 1446 {} 1447 }; 1448 struct mv88e6xxx_chip *chip = ds->priv; 1449 int ret; 1450 1451 ret = mv88e6xxx_stats_snapshot(chip, port); 1452 if (ret < 0) 1453 return; 1454 1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1456 mv88e6xxx_stats_get_stat(chip, port, \ 1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1458 &rmon_stats->stats._member) 1459 1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1470 1471 #undef MV88E6XXX_RMON_STAT_MAP 1472 1473 *ranges = rmon_ranges; 1474 } 1475 1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int len; 1480 1481 len = 32 * sizeof(u16); 1482 if (chip->info->ops->serdes_get_regs_len) 1483 len += chip->info->ops->serdes_get_regs_len(chip, port); 1484 1485 return len; 1486 } 1487 1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1489 struct ethtool_regs *regs, void *_p) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 int err; 1493 u16 reg; 1494 u16 *p = _p; 1495 int i; 1496 1497 regs->version = chip->info->prod_num; 1498 1499 memset(p, 0xff, 32 * sizeof(u16)); 1500 1501 mv88e6xxx_reg_lock(chip); 1502 1503 for (i = 0; i < 32; i++) { 1504 1505 err = mv88e6xxx_port_read(chip, port, i, ®); 1506 if (!err) 1507 p[i] = reg; 1508 } 1509 1510 if (chip->info->ops->serdes_get_regs) 1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1512 1513 mv88e6xxx_reg_unlock(chip); 1514 } 1515 1516 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1517 struct ethtool_keee *e) 1518 { 1519 /* Nothing to do on the port's MAC */ 1520 return 0; 1521 } 1522 1523 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1525 { 1526 struct dsa_switch *ds = chip->ds; 1527 struct dsa_switch_tree *dst = ds->dst; 1528 struct dsa_port *dp, *other_dp; 1529 bool found = false; 1530 u16 pvlan; 1531 1532 /* dev is a physical switch */ 1533 if (dev <= dst->last_switch) { 1534 list_for_each_entry(dp, &dst->ports, list) { 1535 if (dp->ds->index == dev && dp->index == port) { 1536 /* dp might be a DSA link or a user port, so it 1537 * might or might not have a bridge. 1538 * Use the "found" variable for both cases. 1539 */ 1540 found = true; 1541 break; 1542 } 1543 } 1544 /* dev is a virtual bridge */ 1545 } else { 1546 list_for_each_entry(dp, &dst->ports, list) { 1547 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1548 1549 if (!bridge_num) 1550 continue; 1551 1552 if (bridge_num + dst->last_switch != dev) 1553 continue; 1554 1555 found = true; 1556 break; 1557 } 1558 } 1559 1560 /* Prevent frames from unknown switch or virtual bridge */ 1561 if (!found) 1562 return 0; 1563 1564 /* Frames from DSA links and CPU ports can egress any local port */ 1565 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1566 return mv88e6xxx_port_mask(chip); 1567 1568 pvlan = 0; 1569 1570 /* Frames from standalone user ports can only egress on the 1571 * upstream port. 1572 */ 1573 if (!dsa_port_bridge_dev_get(dp)) 1574 return BIT(dsa_switch_upstream_port(ds)); 1575 1576 /* Frames from bridged user ports can egress any local DSA 1577 * links and CPU ports, as well as any local member of their 1578 * bridge group. 1579 */ 1580 dsa_switch_for_each_port(other_dp, ds) 1581 if (other_dp->type == DSA_PORT_TYPE_CPU || 1582 other_dp->type == DSA_PORT_TYPE_DSA || 1583 dsa_port_bridge_same(dp, other_dp)) 1584 pvlan |= BIT(other_dp->index); 1585 1586 return pvlan; 1587 } 1588 1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1590 { 1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1592 1593 /* prevent frames from going back out of the port they came in on */ 1594 output_ports &= ~BIT(port); 1595 1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1597 } 1598 1599 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1600 u8 state) 1601 { 1602 struct mv88e6xxx_chip *chip = ds->priv; 1603 int err; 1604 1605 mv88e6xxx_reg_lock(chip); 1606 err = mv88e6xxx_port_set_state(chip, port, state); 1607 mv88e6xxx_reg_unlock(chip); 1608 1609 if (err) 1610 dev_err(ds->dev, "p%d: failed to update state\n", port); 1611 } 1612 1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1614 { 1615 int err; 1616 1617 if (chip->info->ops->ieee_pri_map) { 1618 err = chip->info->ops->ieee_pri_map(chip); 1619 if (err) 1620 return err; 1621 } 1622 1623 if (chip->info->ops->ip_pri_map) { 1624 err = chip->info->ops->ip_pri_map(chip); 1625 if (err) 1626 return err; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1633 { 1634 struct dsa_switch *ds = chip->ds; 1635 int target, port; 1636 int err; 1637 1638 if (!chip->info->global2_addr) 1639 return 0; 1640 1641 /* Initialize the routing port to the 32 possible target devices */ 1642 for (target = 0; target < 32; target++) { 1643 port = dsa_routing_port(ds, target); 1644 if (port == ds->num_ports) 1645 port = 0x1f; 1646 1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1648 if (err) 1649 return err; 1650 } 1651 1652 if (chip->info->ops->set_cascade_port) { 1653 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1654 err = chip->info->ops->set_cascade_port(chip, port); 1655 if (err) 1656 return err; 1657 } 1658 1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1660 if (err) 1661 return err; 1662 1663 return 0; 1664 } 1665 1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1667 { 1668 /* Clear all trunk masks and mapping */ 1669 if (chip->info->global2_addr) 1670 return mv88e6xxx_g2_trunk_clear(chip); 1671 1672 return 0; 1673 } 1674 1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1676 { 1677 if (chip->info->ops->rmu_disable) 1678 return chip->info->ops->rmu_disable(chip); 1679 1680 return 0; 1681 } 1682 1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1684 { 1685 if (chip->info->ops->pot_clear) 1686 return chip->info->ops->pot_clear(chip); 1687 1688 return 0; 1689 } 1690 1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1692 { 1693 if (chip->info->ops->mgmt_rsvd2cpu) 1694 return chip->info->ops->mgmt_rsvd2cpu(chip); 1695 1696 return 0; 1697 } 1698 1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1700 { 1701 int err; 1702 1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1704 if (err) 1705 return err; 1706 1707 /* The chips that have a "learn2all" bit in Global1, ATU 1708 * Control are precisely those whose port registers have a 1709 * Message Port bit in Port Control 1 and hence implement 1710 * ->port_setup_message_port. 1711 */ 1712 if (chip->info->ops->port_setup_message_port) { 1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1714 if (err) 1715 return err; 1716 } 1717 1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1719 } 1720 1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1722 { 1723 int port; 1724 int err; 1725 1726 if (!chip->info->ops->irl_init_all) 1727 return 0; 1728 1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1730 /* Disable ingress rate limiting by resetting all per port 1731 * ingress rate limit resources to their initial state. 1732 */ 1733 err = chip->info->ops->irl_init_all(chip, port); 1734 if (err) 1735 return err; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1742 { 1743 if (chip->info->ops->set_switch_mac) { 1744 u8 addr[ETH_ALEN]; 1745 1746 eth_random_addr(addr); 1747 1748 return chip->info->ops->set_switch_mac(chip, addr); 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1755 { 1756 struct dsa_switch_tree *dst = chip->ds->dst; 1757 struct dsa_switch *ds; 1758 struct dsa_port *dp; 1759 u16 pvlan = 0; 1760 1761 if (!mv88e6xxx_has_pvt(chip)) 1762 return 0; 1763 1764 /* Skip the local source device, which uses in-chip port VLAN */ 1765 if (dev != chip->ds->index) { 1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1767 1768 ds = dsa_switch_find(dst->index, dev); 1769 dp = ds ? dsa_to_port(ds, port) : NULL; 1770 if (dp && dp->lag) { 1771 /* As the PVT is used to limit flooding of 1772 * FORWARD frames, which use the LAG ID as the 1773 * source port, we must translate dev/port to 1774 * the special "LAG device" in the PVT, using 1775 * the LAG ID (one-based) as the port number 1776 * (zero-based). 1777 */ 1778 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1779 port = dsa_port_lag_id_get(dp) - 1; 1780 } 1781 } 1782 1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1784 } 1785 1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1787 { 1788 int dev, port; 1789 int err; 1790 1791 if (!mv88e6xxx_has_pvt(chip)) 1792 return 0; 1793 1794 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1795 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1796 */ 1797 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1798 if (err) 1799 return err; 1800 1801 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1802 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1803 err = mv88e6xxx_pvt_map(chip, dev, port); 1804 if (err) 1805 return err; 1806 } 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1813 u16 fid) 1814 { 1815 if (dsa_to_port(chip->ds, port)->lag) 1816 /* Hardware is incapable of fast-aging a LAG through a 1817 * regular ATU move operation. Until we have something 1818 * more fancy in place this is a no-op. 1819 */ 1820 return -EOPNOTSUPP; 1821 1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1823 } 1824 1825 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1826 { 1827 struct mv88e6xxx_chip *chip = ds->priv; 1828 int err; 1829 1830 mv88e6xxx_reg_lock(chip); 1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1832 mv88e6xxx_reg_unlock(chip); 1833 1834 if (err) 1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1836 port, err); 1837 } 1838 1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1840 { 1841 if (!mv88e6xxx_max_vid(chip)) 1842 return 0; 1843 1844 return mv88e6xxx_g1_vtu_flush(chip); 1845 } 1846 1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1848 struct mv88e6xxx_vtu_entry *entry) 1849 { 1850 int err; 1851 1852 if (!chip->info->ops->vtu_getnext) 1853 return -EOPNOTSUPP; 1854 1855 memset(entry, 0, sizeof(*entry)); 1856 1857 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1858 entry->valid = false; 1859 1860 err = chip->info->ops->vtu_getnext(chip, entry); 1861 1862 if (entry->vid != vid) 1863 entry->valid = false; 1864 1865 return err; 1866 } 1867 1868 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1869 int (*cb)(struct mv88e6xxx_chip *chip, 1870 const struct mv88e6xxx_vtu_entry *entry, 1871 void *priv), 1872 void *priv) 1873 { 1874 struct mv88e6xxx_vtu_entry entry = { 1875 .vid = mv88e6xxx_max_vid(chip), 1876 .valid = false, 1877 }; 1878 int err; 1879 1880 if (!chip->info->ops->vtu_getnext) 1881 return -EOPNOTSUPP; 1882 1883 do { 1884 err = chip->info->ops->vtu_getnext(chip, &entry); 1885 if (err) 1886 return err; 1887 1888 if (!entry.valid) 1889 break; 1890 1891 err = cb(chip, &entry, priv); 1892 if (err) 1893 return err; 1894 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1895 1896 return 0; 1897 } 1898 1899 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1900 struct mv88e6xxx_vtu_entry *entry) 1901 { 1902 if (!chip->info->ops->vtu_loadpurge) 1903 return -EOPNOTSUPP; 1904 1905 return chip->info->ops->vtu_loadpurge(chip, entry); 1906 } 1907 1908 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1909 { 1910 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1911 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1912 return -ENOSPC; 1913 1914 /* Clear the database */ 1915 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1916 } 1917 1918 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1919 struct mv88e6xxx_stu_entry *entry) 1920 { 1921 if (!chip->info->ops->stu_loadpurge) 1922 return -EOPNOTSUPP; 1923 1924 return chip->info->ops->stu_loadpurge(chip, entry); 1925 } 1926 1927 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1928 { 1929 struct mv88e6xxx_stu_entry stu = { 1930 .valid = true, 1931 .sid = 0 1932 }; 1933 1934 if (!mv88e6xxx_has_stu(chip)) 1935 return 0; 1936 1937 /* Make sure that SID 0 is always valid. This is used by VTU 1938 * entries that do not make use of the STU, e.g. when creating 1939 * a VLAN upper on a port that is also part of a VLAN 1940 * filtering bridge. 1941 */ 1942 return mv88e6xxx_stu_loadpurge(chip, &stu); 1943 } 1944 1945 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1946 { 1947 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1948 struct mv88e6xxx_mst *mst; 1949 1950 __set_bit(0, busy); 1951 1952 list_for_each_entry(mst, &chip->msts, node) 1953 __set_bit(mst->stu.sid, busy); 1954 1955 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1956 1957 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1958 } 1959 1960 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1961 { 1962 struct mv88e6xxx_mst *mst, *tmp; 1963 int err; 1964 1965 /* If the SID is zero, it is for a VLAN mapped to the default MSTI, 1966 * and mv88e6xxx_stu_setup() made sure it is always present, and thus, 1967 * should not be removed here. 1968 * 1969 * If the chip lacks STU support, numerically the "sid" variable will 1970 * happen to also be zero, but we don't want to rely on that fact, so 1971 * we explicitly test that first. In that case, there is also nothing 1972 * to do here. 1973 */ 1974 if (!mv88e6xxx_has_stu(chip) || !sid) 1975 return 0; 1976 1977 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1978 if (mst->stu.sid != sid) 1979 continue; 1980 1981 if (!refcount_dec_and_test(&mst->refcnt)) 1982 return 0; 1983 1984 mst->stu.valid = false; 1985 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1986 if (err) { 1987 refcount_set(&mst->refcnt, 1); 1988 return err; 1989 } 1990 1991 list_del(&mst->node); 1992 kfree(mst); 1993 return 0; 1994 } 1995 1996 return -ENOENT; 1997 } 1998 1999 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 2000 u16 msti, u8 *sid) 2001 { 2002 struct mv88e6xxx_mst *mst; 2003 int err, i; 2004 2005 if (!mv88e6xxx_has_stu(chip)) { 2006 err = -EOPNOTSUPP; 2007 goto err; 2008 } 2009 2010 if (!msti) { 2011 *sid = 0; 2012 return 0; 2013 } 2014 2015 list_for_each_entry(mst, &chip->msts, node) { 2016 if (mst->br == br && mst->msti == msti) { 2017 refcount_inc(&mst->refcnt); 2018 *sid = mst->stu.sid; 2019 return 0; 2020 } 2021 } 2022 2023 err = mv88e6xxx_sid_get(chip, sid); 2024 if (err) 2025 goto err; 2026 2027 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2028 if (!mst) { 2029 err = -ENOMEM; 2030 goto err; 2031 } 2032 2033 INIT_LIST_HEAD(&mst->node); 2034 refcount_set(&mst->refcnt, 1); 2035 mst->br = br; 2036 mst->msti = msti; 2037 mst->stu.valid = true; 2038 mst->stu.sid = *sid; 2039 2040 /* The bridge starts out all ports in the disabled state. But 2041 * a STU state of disabled means to go by the port-global 2042 * state. So we set all user port's initial state to blocking, 2043 * to match the bridge's behavior. 2044 */ 2045 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2046 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2047 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2048 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2049 2050 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2051 if (err) 2052 goto err_free; 2053 2054 list_add_tail(&mst->node, &chip->msts); 2055 return 0; 2056 2057 err_free: 2058 kfree(mst); 2059 err: 2060 return err; 2061 } 2062 2063 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2064 const struct switchdev_mst_state *st) 2065 { 2066 struct dsa_port *dp = dsa_to_port(ds, port); 2067 struct mv88e6xxx_chip *chip = ds->priv; 2068 struct mv88e6xxx_mst *mst; 2069 u8 state; 2070 int err; 2071 2072 if (!mv88e6xxx_has_stu(chip)) 2073 return -EOPNOTSUPP; 2074 2075 switch (st->state) { 2076 case BR_STATE_DISABLED: 2077 case BR_STATE_BLOCKING: 2078 case BR_STATE_LISTENING: 2079 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2080 break; 2081 case BR_STATE_LEARNING: 2082 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2083 break; 2084 case BR_STATE_FORWARDING: 2085 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2086 break; 2087 default: 2088 return -EINVAL; 2089 } 2090 2091 list_for_each_entry(mst, &chip->msts, node) { 2092 if (mst->br == dsa_port_bridge_dev_get(dp) && 2093 mst->msti == st->msti) { 2094 if (mst->stu.state[port] == state) 2095 return 0; 2096 2097 mst->stu.state[port] = state; 2098 mv88e6xxx_reg_lock(chip); 2099 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2100 mv88e6xxx_reg_unlock(chip); 2101 return err; 2102 } 2103 } 2104 2105 return -ENOENT; 2106 } 2107 2108 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2109 u16 vid) 2110 { 2111 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2112 struct mv88e6xxx_chip *chip = ds->priv; 2113 struct mv88e6xxx_vtu_entry vlan; 2114 int err; 2115 2116 /* DSA and CPU ports have to be members of multiple vlans */ 2117 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2118 return 0; 2119 2120 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2121 if (err) 2122 return err; 2123 2124 if (!vlan.valid) 2125 return 0; 2126 2127 dsa_switch_for_each_user_port(other_dp, ds) { 2128 struct net_device *other_br; 2129 2130 if (vlan.member[other_dp->index] == 2131 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2132 continue; 2133 2134 if (dsa_port_bridge_same(dp, other_dp)) 2135 break; /* same bridge, check next VLAN */ 2136 2137 other_br = dsa_port_bridge_dev_get(other_dp); 2138 if (!other_br) 2139 continue; 2140 2141 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2142 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2143 return -EOPNOTSUPP; 2144 } 2145 2146 return 0; 2147 } 2148 2149 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2150 { 2151 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2152 struct net_device *br = dsa_port_bridge_dev_get(dp); 2153 struct mv88e6xxx_port *p = &chip->ports[port]; 2154 u16 pvid = MV88E6XXX_VID_STANDALONE; 2155 bool drop_untagged = false; 2156 int err; 2157 2158 if (br) { 2159 if (br_vlan_enabled(br)) { 2160 pvid = p->bridge_pvid.vid; 2161 drop_untagged = !p->bridge_pvid.valid; 2162 } else { 2163 pvid = MV88E6XXX_VID_BRIDGED; 2164 } 2165 } 2166 2167 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2168 if (err) 2169 return err; 2170 2171 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2172 } 2173 2174 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2175 bool vlan_filtering, 2176 struct netlink_ext_ack *extack) 2177 { 2178 struct mv88e6xxx_chip *chip = ds->priv; 2179 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2180 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2181 int err; 2182 2183 if (!mv88e6xxx_max_vid(chip)) 2184 return -EOPNOTSUPP; 2185 2186 mv88e6xxx_reg_lock(chip); 2187 2188 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2189 if (err) 2190 goto unlock; 2191 2192 err = mv88e6xxx_port_commit_pvid(chip, port); 2193 if (err) 2194 goto unlock; 2195 2196 unlock: 2197 mv88e6xxx_reg_unlock(chip); 2198 2199 return err; 2200 } 2201 2202 static int 2203 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2204 const struct switchdev_obj_port_vlan *vlan) 2205 { 2206 struct mv88e6xxx_chip *chip = ds->priv; 2207 int err; 2208 2209 if (!mv88e6xxx_max_vid(chip)) 2210 return -EOPNOTSUPP; 2211 2212 /* If the requested port doesn't belong to the same bridge as the VLAN 2213 * members, do not support it (yet) and fallback to software VLAN. 2214 */ 2215 mv88e6xxx_reg_lock(chip); 2216 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2217 mv88e6xxx_reg_unlock(chip); 2218 2219 return err; 2220 } 2221 2222 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip, 2223 const unsigned char *addr, u16 vid, 2224 u16 *fid, struct mv88e6xxx_atu_entry *entry) 2225 { 2226 struct mv88e6xxx_vtu_entry vlan; 2227 int err; 2228 2229 /* Ports have two private address databases: one for when the port is 2230 * standalone and one for when the port is under a bridge and the 2231 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2232 * address database to remain 100% empty, so we never load an ATU entry 2233 * into a standalone port's database. Therefore, translate the null 2234 * VLAN ID into the port's database used for VLAN-unaware bridging. 2235 */ 2236 if (vid == 0) { 2237 *fid = MV88E6XXX_FID_BRIDGED; 2238 } else { 2239 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2240 if (err) 2241 return err; 2242 2243 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2244 if (!vlan.valid) 2245 return -EOPNOTSUPP; 2246 2247 *fid = vlan.fid; 2248 } 2249 2250 entry->state = 0; 2251 ether_addr_copy(entry->mac, addr); 2252 eth_addr_dec(entry->mac); 2253 2254 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry); 2255 } 2256 2257 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip, 2258 const unsigned char *addr, u16 vid) 2259 { 2260 struct mv88e6xxx_atu_entry entry; 2261 u16 fid; 2262 int err; 2263 2264 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2265 if (err) 2266 return false; 2267 2268 return entry.state && ether_addr_equal(entry.mac, addr); 2269 } 2270 2271 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2272 const unsigned char *addr, u16 vid, 2273 u8 state) 2274 { 2275 struct mv88e6xxx_atu_entry entry; 2276 u16 fid; 2277 int err; 2278 2279 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2280 if (err) 2281 return err; 2282 2283 /* Initialize a fresh ATU entry if it isn't found */ 2284 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2285 memset(&entry, 0, sizeof(entry)); 2286 ether_addr_copy(entry.mac, addr); 2287 } 2288 2289 /* Purge the ATU entry only if no port is using it anymore */ 2290 if (!state) { 2291 entry.portvec &= ~BIT(port); 2292 if (!entry.portvec) 2293 entry.state = 0; 2294 } else { 2295 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2296 entry.portvec = BIT(port); 2297 else 2298 entry.portvec |= BIT(port); 2299 2300 entry.state = state; 2301 } 2302 2303 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2304 } 2305 2306 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2307 const struct mv88e6xxx_policy *policy) 2308 { 2309 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2310 enum mv88e6xxx_policy_action action = policy->action; 2311 const u8 *addr = policy->addr; 2312 u16 vid = policy->vid; 2313 u8 state; 2314 int err; 2315 int id; 2316 2317 if (!chip->info->ops->port_set_policy) 2318 return -EOPNOTSUPP; 2319 2320 switch (mapping) { 2321 case MV88E6XXX_POLICY_MAPPING_DA: 2322 case MV88E6XXX_POLICY_MAPPING_SA: 2323 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2324 state = 0; /* Dissociate the port and address */ 2325 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2326 is_multicast_ether_addr(addr)) 2327 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2328 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2329 is_unicast_ether_addr(addr)) 2330 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2331 else 2332 return -EOPNOTSUPP; 2333 2334 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2335 state); 2336 if (err) 2337 return err; 2338 break; 2339 default: 2340 return -EOPNOTSUPP; 2341 } 2342 2343 /* Skip the port's policy clearing if the mapping is still in use */ 2344 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2345 idr_for_each_entry(&chip->policies, policy, id) 2346 if (policy->port == port && 2347 policy->mapping == mapping && 2348 policy->action != action) 2349 return 0; 2350 2351 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2352 } 2353 2354 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2355 struct ethtool_rx_flow_spec *fs) 2356 { 2357 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2358 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2359 enum mv88e6xxx_policy_mapping mapping; 2360 enum mv88e6xxx_policy_action action; 2361 struct mv88e6xxx_policy *policy; 2362 u16 vid = 0; 2363 u8 *addr; 2364 int err; 2365 int id; 2366 2367 if (fs->location != RX_CLS_LOC_ANY) 2368 return -EINVAL; 2369 2370 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2371 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2372 else 2373 return -EOPNOTSUPP; 2374 2375 switch (fs->flow_type & ~FLOW_EXT) { 2376 case ETHER_FLOW: 2377 if (!is_zero_ether_addr(mac_mask->h_dest) && 2378 is_zero_ether_addr(mac_mask->h_source)) { 2379 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2380 addr = mac_entry->h_dest; 2381 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2382 !is_zero_ether_addr(mac_mask->h_source)) { 2383 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2384 addr = mac_entry->h_source; 2385 } else { 2386 /* Cannot support DA and SA mapping in the same rule */ 2387 return -EOPNOTSUPP; 2388 } 2389 break; 2390 default: 2391 return -EOPNOTSUPP; 2392 } 2393 2394 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2395 if (fs->m_ext.vlan_tci != htons(0xffff)) 2396 return -EOPNOTSUPP; 2397 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2398 } 2399 2400 idr_for_each_entry(&chip->policies, policy, id) { 2401 if (policy->port == port && policy->mapping == mapping && 2402 policy->action == action && policy->vid == vid && 2403 ether_addr_equal(policy->addr, addr)) 2404 return -EEXIST; 2405 } 2406 2407 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2408 if (!policy) 2409 return -ENOMEM; 2410 2411 fs->location = 0; 2412 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2413 GFP_KERNEL); 2414 if (err) { 2415 devm_kfree(chip->dev, policy); 2416 return err; 2417 } 2418 2419 memcpy(&policy->fs, fs, sizeof(*fs)); 2420 ether_addr_copy(policy->addr, addr); 2421 policy->mapping = mapping; 2422 policy->action = action; 2423 policy->port = port; 2424 policy->vid = vid; 2425 2426 err = mv88e6xxx_policy_apply(chip, port, policy); 2427 if (err) { 2428 idr_remove(&chip->policies, fs->location); 2429 devm_kfree(chip->dev, policy); 2430 return err; 2431 } 2432 2433 return 0; 2434 } 2435 2436 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2437 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2438 { 2439 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2440 struct mv88e6xxx_chip *chip = ds->priv; 2441 struct mv88e6xxx_policy *policy; 2442 int err; 2443 int id; 2444 2445 mv88e6xxx_reg_lock(chip); 2446 2447 switch (rxnfc->cmd) { 2448 case ETHTOOL_GRXCLSRLCNT: 2449 rxnfc->data = 0; 2450 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2451 rxnfc->rule_cnt = 0; 2452 idr_for_each_entry(&chip->policies, policy, id) 2453 if (policy->port == port) 2454 rxnfc->rule_cnt++; 2455 err = 0; 2456 break; 2457 case ETHTOOL_GRXCLSRULE: 2458 err = -ENOENT; 2459 policy = idr_find(&chip->policies, fs->location); 2460 if (policy) { 2461 memcpy(fs, &policy->fs, sizeof(*fs)); 2462 err = 0; 2463 } 2464 break; 2465 case ETHTOOL_GRXCLSRLALL: 2466 rxnfc->data = 0; 2467 rxnfc->rule_cnt = 0; 2468 idr_for_each_entry(&chip->policies, policy, id) 2469 if (policy->port == port) 2470 rule_locs[rxnfc->rule_cnt++] = id; 2471 err = 0; 2472 break; 2473 default: 2474 err = -EOPNOTSUPP; 2475 break; 2476 } 2477 2478 mv88e6xxx_reg_unlock(chip); 2479 2480 return err; 2481 } 2482 2483 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2484 struct ethtool_rxnfc *rxnfc) 2485 { 2486 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2487 struct mv88e6xxx_chip *chip = ds->priv; 2488 struct mv88e6xxx_policy *policy; 2489 int err; 2490 2491 mv88e6xxx_reg_lock(chip); 2492 2493 switch (rxnfc->cmd) { 2494 case ETHTOOL_SRXCLSRLINS: 2495 err = mv88e6xxx_policy_insert(chip, port, fs); 2496 break; 2497 case ETHTOOL_SRXCLSRLDEL: 2498 err = -ENOENT; 2499 policy = idr_remove(&chip->policies, fs->location); 2500 if (policy) { 2501 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2502 err = mv88e6xxx_policy_apply(chip, port, policy); 2503 devm_kfree(chip->dev, policy); 2504 } 2505 break; 2506 default: 2507 err = -EOPNOTSUPP; 2508 break; 2509 } 2510 2511 mv88e6xxx_reg_unlock(chip); 2512 2513 return err; 2514 } 2515 2516 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2517 u16 vid) 2518 { 2519 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2520 u8 broadcast[ETH_ALEN]; 2521 2522 eth_broadcast_addr(broadcast); 2523 2524 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2525 } 2526 2527 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2528 { 2529 int port; 2530 int err; 2531 2532 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2533 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2534 struct net_device *brport; 2535 2536 if (dsa_is_unused_port(chip->ds, port)) 2537 continue; 2538 2539 brport = dsa_port_to_bridge_port(dp); 2540 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2541 /* Skip bridged user ports where broadcast 2542 * flooding is disabled. 2543 */ 2544 continue; 2545 2546 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2547 if (err) 2548 return err; 2549 } 2550 2551 return 0; 2552 } 2553 2554 struct mv88e6xxx_port_broadcast_sync_ctx { 2555 int port; 2556 bool flood; 2557 }; 2558 2559 static int 2560 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2561 const struct mv88e6xxx_vtu_entry *vlan, 2562 void *_ctx) 2563 { 2564 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2565 u8 broadcast[ETH_ALEN]; 2566 u8 state; 2567 2568 if (ctx->flood) 2569 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2570 else 2571 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2572 2573 eth_broadcast_addr(broadcast); 2574 2575 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2576 vlan->vid, state); 2577 } 2578 2579 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2580 bool flood) 2581 { 2582 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2583 .port = port, 2584 .flood = flood, 2585 }; 2586 struct mv88e6xxx_vtu_entry vid0 = { 2587 .vid = 0, 2588 }; 2589 int err; 2590 2591 /* Update the port's private database... */ 2592 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2593 if (err) 2594 return err; 2595 2596 /* ...and the database for all VLANs. */ 2597 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2598 &ctx); 2599 } 2600 2601 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2602 u16 vid, u8 member, bool warn) 2603 { 2604 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2605 struct mv88e6xxx_vtu_entry vlan; 2606 int i, err; 2607 2608 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2609 if (err) 2610 return err; 2611 2612 if (!vlan.valid) { 2613 memset(&vlan, 0, sizeof(vlan)); 2614 2615 if (vid == MV88E6XXX_VID_STANDALONE) 2616 vlan.policy = true; 2617 2618 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2619 if (err) 2620 return err; 2621 2622 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2623 if (i == port) 2624 vlan.member[i] = member; 2625 else 2626 vlan.member[i] = non_member; 2627 2628 vlan.vid = vid; 2629 vlan.valid = true; 2630 2631 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2632 if (err) 2633 return err; 2634 2635 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2636 if (err) 2637 return err; 2638 } else if (vlan.member[port] != member) { 2639 vlan.member[port] = member; 2640 2641 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2642 if (err) 2643 return err; 2644 } else if (warn) { 2645 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2646 port, vid); 2647 } 2648 2649 /* Record FID used in SW FID map */ 2650 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2651 2652 return 0; 2653 } 2654 2655 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2656 const struct switchdev_obj_port_vlan *vlan, 2657 struct netlink_ext_ack *extack) 2658 { 2659 struct mv88e6xxx_chip *chip = ds->priv; 2660 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2661 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2662 struct mv88e6xxx_port *p = &chip->ports[port]; 2663 bool warn; 2664 u8 member; 2665 int err; 2666 2667 if (!vlan->vid) 2668 return 0; 2669 2670 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2671 if (err) 2672 return err; 2673 2674 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2675 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2676 else if (untagged) 2677 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2678 else 2679 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2680 2681 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2682 * and then the CPU port. Do not warn for duplicates for the CPU port. 2683 */ 2684 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2685 2686 mv88e6xxx_reg_lock(chip); 2687 2688 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2689 if (err) { 2690 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2691 vlan->vid, untagged ? 'u' : 't'); 2692 goto out; 2693 } 2694 2695 if (pvid) { 2696 p->bridge_pvid.vid = vlan->vid; 2697 p->bridge_pvid.valid = true; 2698 2699 err = mv88e6xxx_port_commit_pvid(chip, port); 2700 if (err) 2701 goto out; 2702 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2703 /* The old pvid was reinstalled as a non-pvid VLAN */ 2704 p->bridge_pvid.valid = false; 2705 2706 err = mv88e6xxx_port_commit_pvid(chip, port); 2707 if (err) 2708 goto out; 2709 } 2710 2711 out: 2712 mv88e6xxx_reg_unlock(chip); 2713 2714 return err; 2715 } 2716 2717 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2718 int port, u16 vid) 2719 { 2720 struct mv88e6xxx_vtu_entry vlan; 2721 int i, err; 2722 2723 if (!vid) 2724 return 0; 2725 2726 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2727 if (err) 2728 return err; 2729 2730 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2731 * tell switchdev that this VLAN is likely handled in software. 2732 */ 2733 if (!vlan.valid || 2734 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2735 return -EOPNOTSUPP; 2736 2737 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2738 2739 /* keep the VLAN unless all ports are excluded */ 2740 vlan.valid = false; 2741 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2742 if (vlan.member[i] != 2743 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2744 vlan.valid = true; 2745 break; 2746 } 2747 } 2748 2749 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2750 if (err) 2751 return err; 2752 2753 if (!vlan.valid) { 2754 err = mv88e6xxx_mst_put(chip, vlan.sid); 2755 if (err) 2756 return err; 2757 2758 /* Record FID freed in SW FID map */ 2759 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2760 } 2761 2762 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2763 } 2764 2765 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2766 const struct switchdev_obj_port_vlan *vlan) 2767 { 2768 struct mv88e6xxx_chip *chip = ds->priv; 2769 struct mv88e6xxx_port *p = &chip->ports[port]; 2770 int err = 0; 2771 u16 pvid; 2772 2773 if (!mv88e6xxx_max_vid(chip)) 2774 return -EOPNOTSUPP; 2775 2776 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2777 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2778 * switchdev workqueue to ensure that all FDB entries are deleted 2779 * before we remove the VLAN. 2780 */ 2781 dsa_flush_workqueue(); 2782 2783 mv88e6xxx_reg_lock(chip); 2784 2785 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2786 if (err) 2787 goto unlock; 2788 2789 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2790 if (err) 2791 goto unlock; 2792 2793 if (vlan->vid == pvid) { 2794 p->bridge_pvid.valid = false; 2795 2796 err = mv88e6xxx_port_commit_pvid(chip, port); 2797 if (err) 2798 goto unlock; 2799 } 2800 2801 unlock: 2802 mv88e6xxx_reg_unlock(chip); 2803 2804 return err; 2805 } 2806 2807 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2808 { 2809 struct mv88e6xxx_chip *chip = ds->priv; 2810 struct mv88e6xxx_vtu_entry vlan; 2811 int err; 2812 2813 mv88e6xxx_reg_lock(chip); 2814 2815 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2816 if (err) 2817 goto unlock; 2818 2819 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2820 2821 unlock: 2822 mv88e6xxx_reg_unlock(chip); 2823 2824 return err; 2825 } 2826 2827 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2828 struct dsa_bridge bridge, 2829 const struct switchdev_vlan_msti *msti) 2830 { 2831 struct mv88e6xxx_chip *chip = ds->priv; 2832 struct mv88e6xxx_vtu_entry vlan; 2833 u8 old_sid, new_sid; 2834 int err; 2835 2836 if (!mv88e6xxx_has_stu(chip)) 2837 return -EOPNOTSUPP; 2838 2839 mv88e6xxx_reg_lock(chip); 2840 2841 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2842 if (err) 2843 goto unlock; 2844 2845 if (!vlan.valid) { 2846 err = -EINVAL; 2847 goto unlock; 2848 } 2849 2850 old_sid = vlan.sid; 2851 2852 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2853 if (err) 2854 goto unlock; 2855 2856 if (new_sid != old_sid) { 2857 vlan.sid = new_sid; 2858 2859 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2860 if (err) { 2861 mv88e6xxx_mst_put(chip, new_sid); 2862 goto unlock; 2863 } 2864 } 2865 2866 err = mv88e6xxx_mst_put(chip, old_sid); 2867 2868 unlock: 2869 mv88e6xxx_reg_unlock(chip); 2870 return err; 2871 } 2872 2873 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2874 const unsigned char *addr, u16 vid, 2875 struct dsa_db db) 2876 { 2877 struct mv88e6xxx_chip *chip = ds->priv; 2878 int err; 2879 2880 mv88e6xxx_reg_lock(chip); 2881 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2882 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2883 if (err) 2884 goto out; 2885 2886 if (!mv88e6xxx_port_db_find(chip, addr, vid)) 2887 err = -ENOSPC; 2888 2889 out: 2890 mv88e6xxx_reg_unlock(chip); 2891 2892 return err; 2893 } 2894 2895 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2896 const unsigned char *addr, u16 vid, 2897 struct dsa_db db) 2898 { 2899 struct mv88e6xxx_chip *chip = ds->priv; 2900 int err; 2901 2902 mv88e6xxx_reg_lock(chip); 2903 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2904 mv88e6xxx_reg_unlock(chip); 2905 2906 return err; 2907 } 2908 2909 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2910 u16 fid, u16 vid, int port, 2911 dsa_fdb_dump_cb_t *cb, void *data) 2912 { 2913 struct mv88e6xxx_atu_entry addr; 2914 bool is_static; 2915 int err; 2916 2917 addr.state = 0; 2918 eth_broadcast_addr(addr.mac); 2919 2920 do { 2921 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2922 if (err) 2923 return err; 2924 2925 if (!addr.state) 2926 break; 2927 2928 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2929 continue; 2930 2931 if (!is_unicast_ether_addr(addr.mac)) 2932 continue; 2933 2934 is_static = (addr.state == 2935 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2936 err = cb(addr.mac, vid, is_static, data); 2937 if (err) 2938 return err; 2939 } while (!is_broadcast_ether_addr(addr.mac)); 2940 2941 return err; 2942 } 2943 2944 struct mv88e6xxx_port_db_dump_vlan_ctx { 2945 int port; 2946 dsa_fdb_dump_cb_t *cb; 2947 void *data; 2948 }; 2949 2950 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2951 const struct mv88e6xxx_vtu_entry *entry, 2952 void *_data) 2953 { 2954 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2955 2956 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2957 ctx->port, ctx->cb, ctx->data); 2958 } 2959 2960 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2961 dsa_fdb_dump_cb_t *cb, void *data) 2962 { 2963 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2964 .port = port, 2965 .cb = cb, 2966 .data = data, 2967 }; 2968 u16 fid; 2969 int err; 2970 2971 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2972 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2973 if (err) 2974 return err; 2975 2976 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2977 if (err) 2978 return err; 2979 2980 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2981 } 2982 2983 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2984 dsa_fdb_dump_cb_t *cb, void *data) 2985 { 2986 struct mv88e6xxx_chip *chip = ds->priv; 2987 int err; 2988 2989 mv88e6xxx_reg_lock(chip); 2990 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2991 mv88e6xxx_reg_unlock(chip); 2992 2993 return err; 2994 } 2995 2996 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2997 struct dsa_bridge bridge) 2998 { 2999 struct dsa_switch *ds = chip->ds; 3000 struct dsa_switch_tree *dst = ds->dst; 3001 struct dsa_port *dp; 3002 int err; 3003 3004 list_for_each_entry(dp, &dst->ports, list) { 3005 if (dsa_port_offloads_bridge(dp, &bridge)) { 3006 if (dp->ds == ds) { 3007 /* This is a local bridge group member, 3008 * remap its Port VLAN Map. 3009 */ 3010 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3011 if (err) 3012 return err; 3013 } else { 3014 /* This is an external bridge group member, 3015 * remap its cross-chip Port VLAN Table entry. 3016 */ 3017 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3018 dp->index); 3019 if (err) 3020 return err; 3021 } 3022 } 3023 } 3024 3025 return 0; 3026 } 3027 3028 /* Treat the software bridge as a virtual single-port switch behind the 3029 * CPU and map in the PVT. First dst->last_switch elements are taken by 3030 * physical switches, so start from beyond that range. 3031 */ 3032 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3033 unsigned int bridge_num) 3034 { 3035 u8 dev = bridge_num + ds->dst->last_switch; 3036 struct mv88e6xxx_chip *chip = ds->priv; 3037 3038 return mv88e6xxx_pvt_map(chip, dev, 0); 3039 } 3040 3041 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3042 struct dsa_bridge bridge, 3043 bool *tx_fwd_offload, 3044 struct netlink_ext_ack *extack) 3045 { 3046 struct mv88e6xxx_chip *chip = ds->priv; 3047 int err; 3048 3049 mv88e6xxx_reg_lock(chip); 3050 3051 err = mv88e6xxx_bridge_map(chip, bridge); 3052 if (err) 3053 goto unlock; 3054 3055 err = mv88e6xxx_port_set_map_da(chip, port, true); 3056 if (err) 3057 goto unlock; 3058 3059 err = mv88e6xxx_port_commit_pvid(chip, port); 3060 if (err) 3061 goto unlock; 3062 3063 if (mv88e6xxx_has_pvt(chip)) { 3064 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3065 if (err) 3066 goto unlock; 3067 3068 *tx_fwd_offload = true; 3069 } 3070 3071 unlock: 3072 mv88e6xxx_reg_unlock(chip); 3073 3074 return err; 3075 } 3076 3077 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3078 struct dsa_bridge bridge) 3079 { 3080 struct mv88e6xxx_chip *chip = ds->priv; 3081 int err; 3082 3083 mv88e6xxx_reg_lock(chip); 3084 3085 if (bridge.tx_fwd_offload && 3086 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3087 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3088 3089 if (mv88e6xxx_bridge_map(chip, bridge) || 3090 mv88e6xxx_port_vlan_map(chip, port)) 3091 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3092 3093 err = mv88e6xxx_port_set_map_da(chip, port, false); 3094 if (err) 3095 dev_err(ds->dev, 3096 "port %d failed to restore map-DA: %pe\n", 3097 port, ERR_PTR(err)); 3098 3099 err = mv88e6xxx_port_commit_pvid(chip, port); 3100 if (err) 3101 dev_err(ds->dev, 3102 "port %d failed to restore standalone pvid: %pe\n", 3103 port, ERR_PTR(err)); 3104 3105 mv88e6xxx_reg_unlock(chip); 3106 } 3107 3108 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3109 int tree_index, int sw_index, 3110 int port, struct dsa_bridge bridge, 3111 struct netlink_ext_ack *extack) 3112 { 3113 struct mv88e6xxx_chip *chip = ds->priv; 3114 int err; 3115 3116 if (tree_index != ds->dst->index) 3117 return 0; 3118 3119 mv88e6xxx_reg_lock(chip); 3120 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3121 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3122 mv88e6xxx_reg_unlock(chip); 3123 3124 return err; 3125 } 3126 3127 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3128 int tree_index, int sw_index, 3129 int port, struct dsa_bridge bridge) 3130 { 3131 struct mv88e6xxx_chip *chip = ds->priv; 3132 3133 if (tree_index != ds->dst->index) 3134 return; 3135 3136 mv88e6xxx_reg_lock(chip); 3137 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3138 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3139 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3140 mv88e6xxx_reg_unlock(chip); 3141 } 3142 3143 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3144 { 3145 if (chip->info->ops->reset) 3146 return chip->info->ops->reset(chip); 3147 3148 return 0; 3149 } 3150 3151 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3152 { 3153 struct gpio_desc *gpiod = chip->reset; 3154 int err; 3155 3156 /* If there is a GPIO connected to the reset pin, toggle it */ 3157 if (gpiod) { 3158 /* If the switch has just been reset and not yet completed 3159 * loading EEPROM, the reset may interrupt the I2C transaction 3160 * mid-byte, causing the first EEPROM read after the reset 3161 * from the wrong location resulting in the switch booting 3162 * to wrong mode and inoperable. 3163 * For this reason, switch families with EEPROM support 3164 * generally wait for EEPROM loads to complete as their pre- 3165 * and post-reset handlers. 3166 */ 3167 if (chip->info->ops->hardware_reset_pre) { 3168 err = chip->info->ops->hardware_reset_pre(chip); 3169 if (err) 3170 dev_err(chip->dev, "pre-reset error: %d\n", err); 3171 } 3172 3173 gpiod_set_value_cansleep(gpiod, 1); 3174 usleep_range(10000, 20000); 3175 gpiod_set_value_cansleep(gpiod, 0); 3176 usleep_range(10000, 20000); 3177 3178 if (chip->info->ops->hardware_reset_post) { 3179 err = chip->info->ops->hardware_reset_post(chip); 3180 if (err) 3181 dev_err(chip->dev, "post-reset error: %d\n", err); 3182 } 3183 } 3184 } 3185 3186 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3187 { 3188 int i, err; 3189 3190 /* Set all ports to the Disabled state */ 3191 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3192 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3193 if (err) 3194 return err; 3195 } 3196 3197 /* Wait for transmit queues to drain, 3198 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3199 */ 3200 usleep_range(2000, 4000); 3201 3202 return 0; 3203 } 3204 3205 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3206 { 3207 int err; 3208 3209 err = mv88e6xxx_disable_ports(chip); 3210 if (err) 3211 return err; 3212 3213 mv88e6xxx_hardware_reset(chip); 3214 3215 return mv88e6xxx_software_reset(chip); 3216 } 3217 3218 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3219 enum mv88e6xxx_frame_mode frame, 3220 enum mv88e6xxx_egress_mode egress, u16 etype) 3221 { 3222 int err; 3223 3224 if (!chip->info->ops->port_set_frame_mode) 3225 return -EOPNOTSUPP; 3226 3227 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3228 if (err) 3229 return err; 3230 3231 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3232 if (err) 3233 return err; 3234 3235 if (chip->info->ops->port_set_ether_type) 3236 return chip->info->ops->port_set_ether_type(chip, port, etype); 3237 3238 return 0; 3239 } 3240 3241 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3242 { 3243 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3244 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3245 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3246 } 3247 3248 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3249 { 3250 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3251 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3252 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3253 } 3254 3255 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3256 { 3257 return mv88e6xxx_set_port_mode(chip, port, 3258 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3259 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3260 ETH_P_EDSA); 3261 } 3262 3263 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3264 { 3265 if (dsa_is_dsa_port(chip->ds, port)) 3266 return mv88e6xxx_set_port_mode_dsa(chip, port); 3267 3268 if (dsa_is_user_port(chip->ds, port)) 3269 return mv88e6xxx_set_port_mode_normal(chip, port); 3270 3271 /* Setup CPU port mode depending on its supported tag format */ 3272 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3273 return mv88e6xxx_set_port_mode_dsa(chip, port); 3274 3275 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3276 return mv88e6xxx_set_port_mode_edsa(chip, port); 3277 3278 return -EINVAL; 3279 } 3280 3281 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3282 { 3283 bool message = dsa_is_dsa_port(chip->ds, port); 3284 3285 return mv88e6xxx_port_set_message_port(chip, port, message); 3286 } 3287 3288 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3289 { 3290 int err; 3291 3292 if (chip->info->ops->port_set_ucast_flood) { 3293 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3294 if (err) 3295 return err; 3296 } 3297 if (chip->info->ops->port_set_mcast_flood) { 3298 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3299 if (err) 3300 return err; 3301 } 3302 3303 return 0; 3304 } 3305 3306 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3307 enum mv88e6xxx_egress_direction direction, 3308 int port) 3309 { 3310 int err; 3311 3312 if (!chip->info->ops->set_egress_port) 3313 return -EOPNOTSUPP; 3314 3315 err = chip->info->ops->set_egress_port(chip, direction, port); 3316 if (err) 3317 return err; 3318 3319 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3320 chip->ingress_dest_port = port; 3321 else 3322 chip->egress_dest_port = port; 3323 3324 return 0; 3325 } 3326 3327 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3328 { 3329 struct dsa_switch *ds = chip->ds; 3330 int upstream_port; 3331 int err; 3332 3333 upstream_port = dsa_upstream_port(ds, port); 3334 if (chip->info->ops->port_set_upstream_port) { 3335 err = chip->info->ops->port_set_upstream_port(chip, port, 3336 upstream_port); 3337 if (err) 3338 return err; 3339 } 3340 3341 if (port == upstream_port) { 3342 if (chip->info->ops->set_cpu_port) { 3343 err = chip->info->ops->set_cpu_port(chip, 3344 upstream_port); 3345 if (err) 3346 return err; 3347 } 3348 3349 err = mv88e6xxx_set_egress_port(chip, 3350 MV88E6XXX_EGRESS_DIR_INGRESS, 3351 upstream_port); 3352 if (err && err != -EOPNOTSUPP) 3353 return err; 3354 3355 err = mv88e6xxx_set_egress_port(chip, 3356 MV88E6XXX_EGRESS_DIR_EGRESS, 3357 upstream_port); 3358 if (err && err != -EOPNOTSUPP) 3359 return err; 3360 } 3361 3362 return 0; 3363 } 3364 3365 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3366 { 3367 struct device_node *phy_handle = NULL; 3368 struct fwnode_handle *ports_fwnode; 3369 struct fwnode_handle *port_fwnode; 3370 struct dsa_switch *ds = chip->ds; 3371 struct mv88e6xxx_port *p; 3372 struct dsa_port *dp; 3373 int tx_amp; 3374 int err; 3375 u16 reg; 3376 u32 val; 3377 3378 p = &chip->ports[port]; 3379 p->chip = chip; 3380 p->port = port; 3381 3382 /* Look up corresponding fwnode if any */ 3383 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3384 if (!ports_fwnode) 3385 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3386 if (ports_fwnode) { 3387 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3388 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3389 continue; 3390 if (val == port) { 3391 p->fwnode = port_fwnode; 3392 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3393 break; 3394 } 3395 } 3396 fwnode_handle_put(ports_fwnode); 3397 } else { 3398 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3399 } 3400 3401 if (chip->info->ops->port_setup_leds) { 3402 err = chip->info->ops->port_setup_leds(chip, port); 3403 if (err && err != -EOPNOTSUPP) 3404 return err; 3405 } 3406 3407 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3408 SPEED_UNFORCED, DUPLEX_UNFORCED, 3409 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3410 if (err) 3411 return err; 3412 3413 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3414 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3415 * tunneling, determine priority by looking at 802.1p and IP 3416 * priority fields (IP prio has precedence), and set STP state 3417 * to Forwarding. 3418 * 3419 * If this is the CPU link, use DSA or EDSA tagging depending 3420 * on which tagging mode was configured. 3421 * 3422 * If this is a link to another switch, use DSA tagging mode. 3423 * 3424 * If this is the upstream port for this switch, enable 3425 * forwarding of unknown unicasts and multicasts. 3426 */ 3427 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3428 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3429 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3430 * by a USER port to the CPU port to allow snooping. 3431 */ 3432 if (dsa_is_user_port(ds, port)) 3433 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3434 3435 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3436 if (err) 3437 return err; 3438 3439 err = mv88e6xxx_setup_port_mode(chip, port); 3440 if (err) 3441 return err; 3442 3443 err = mv88e6xxx_setup_egress_floods(chip, port); 3444 if (err) 3445 return err; 3446 3447 /* Port Control 2: don't force a good FCS, set the MTU size to 3448 * 10222 bytes, disable 802.1q tags checking, don't discard 3449 * tagged or untagged frames on this port, skip destination 3450 * address lookup on user ports, disable ARP mirroring and don't 3451 * send a copy of all transmitted/received frames on this port 3452 * to the CPU. 3453 */ 3454 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3455 if (err) 3456 return err; 3457 3458 err = mv88e6xxx_setup_upstream_port(chip, port); 3459 if (err) 3460 return err; 3461 3462 /* On chips that support it, set all downstream DSA ports' 3463 * VLAN policy to TRAP. In combination with loading 3464 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3465 * provides a better isolation barrier between standalone 3466 * ports, as the ATU is bypassed on any intermediate switches 3467 * between the incoming port and the CPU. 3468 */ 3469 if (dsa_is_downstream_port(ds, port) && 3470 chip->info->ops->port_set_policy) { 3471 err = chip->info->ops->port_set_policy(chip, port, 3472 MV88E6XXX_POLICY_MAPPING_VTU, 3473 MV88E6XXX_POLICY_ACTION_TRAP); 3474 if (err) 3475 return err; 3476 } 3477 3478 /* User ports start out in standalone mode and 802.1Q is 3479 * therefore disabled. On DSA ports, all valid VIDs are always 3480 * loaded in the VTU - therefore, enable 802.1Q in order to take 3481 * advantage of VLAN policy on chips that supports it. 3482 */ 3483 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3484 dsa_is_user_port(ds, port) ? 3485 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3486 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3487 if (err) 3488 return err; 3489 3490 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3491 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3492 * the first free FID. This will be used as the private PVID for 3493 * unbridged ports. Shared (DSA and CPU) ports must also be 3494 * members of this VID, in order to trap all frames assigned to 3495 * it to the CPU. 3496 */ 3497 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3498 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3499 false); 3500 if (err) 3501 return err; 3502 3503 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3504 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3505 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3506 * as the private PVID on ports under a VLAN-unaware bridge. 3507 * Shared (DSA and CPU) ports must also be members of it, to translate 3508 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3509 * relying on their port default FID. 3510 */ 3511 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3512 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3513 false); 3514 if (err) 3515 return err; 3516 3517 if (chip->info->ops->port_set_jumbo_size) { 3518 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3519 if (err) 3520 return err; 3521 } 3522 3523 /* Port Association Vector: disable automatic address learning 3524 * on all user ports since they start out in standalone 3525 * mode. When joining a bridge, learning will be configured to 3526 * match the bridge port settings. Enable learning on all 3527 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3528 * learning process. 3529 * 3530 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3531 * and RefreshLocked. I.e. setup standard automatic learning. 3532 */ 3533 if (dsa_is_user_port(ds, port)) 3534 reg = 0; 3535 else 3536 reg = 1 << port; 3537 3538 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3539 reg); 3540 if (err) 3541 return err; 3542 3543 /* Egress rate control 2: disable egress rate control. */ 3544 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3545 0x0000); 3546 if (err) 3547 return err; 3548 3549 if (chip->info->ops->port_pause_limit) { 3550 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3551 if (err) 3552 return err; 3553 } 3554 3555 if (chip->info->ops->port_disable_learn_limit) { 3556 err = chip->info->ops->port_disable_learn_limit(chip, port); 3557 if (err) 3558 return err; 3559 } 3560 3561 if (chip->info->ops->port_disable_pri_override) { 3562 err = chip->info->ops->port_disable_pri_override(chip, port); 3563 if (err) 3564 return err; 3565 } 3566 3567 if (chip->info->ops->port_tag_remap) { 3568 err = chip->info->ops->port_tag_remap(chip, port); 3569 if (err) 3570 return err; 3571 } 3572 3573 if (chip->info->ops->port_egress_rate_limiting) { 3574 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3575 if (err) 3576 return err; 3577 } 3578 3579 if (chip->info->ops->port_setup_message_port) { 3580 err = chip->info->ops->port_setup_message_port(chip, port); 3581 if (err) 3582 return err; 3583 } 3584 3585 if (chip->info->ops->serdes_set_tx_amplitude) { 3586 dp = dsa_to_port(ds, port); 3587 if (dp) 3588 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3589 3590 if (phy_handle && !of_property_read_u32(phy_handle, 3591 "tx-p2p-microvolt", 3592 &tx_amp)) 3593 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3594 port, tx_amp); 3595 if (phy_handle) { 3596 of_node_put(phy_handle); 3597 if (err) 3598 return err; 3599 } 3600 } 3601 3602 /* Port based VLAN map: give each port the same default address 3603 * database, and allow bidirectional communication between the 3604 * CPU and DSA port(s), and the other ports. 3605 */ 3606 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3607 if (err) 3608 return err; 3609 3610 err = mv88e6xxx_port_vlan_map(chip, port); 3611 if (err) 3612 return err; 3613 3614 /* Default VLAN ID and priority: don't set a default VLAN 3615 * ID, and set the default packet priority to zero. 3616 */ 3617 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3618 } 3619 3620 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3621 { 3622 struct mv88e6xxx_chip *chip = ds->priv; 3623 3624 if (chip->info->ops->port_set_jumbo_size) 3625 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3626 else if (chip->info->ops->set_max_frame_size) 3627 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3628 return ETH_DATA_LEN; 3629 } 3630 3631 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3632 { 3633 struct mv88e6xxx_chip *chip = ds->priv; 3634 int ret = 0; 3635 3636 /* For families where we don't know how to alter the MTU, 3637 * just accept any value up to ETH_DATA_LEN 3638 */ 3639 if (!chip->info->ops->port_set_jumbo_size && 3640 !chip->info->ops->set_max_frame_size) { 3641 if (new_mtu > ETH_DATA_LEN) 3642 return -EINVAL; 3643 3644 return 0; 3645 } 3646 3647 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3648 new_mtu += EDSA_HLEN; 3649 3650 mv88e6xxx_reg_lock(chip); 3651 if (chip->info->ops->port_set_jumbo_size) 3652 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3653 else if (chip->info->ops->set_max_frame_size && 3654 dsa_is_cpu_port(ds, port)) 3655 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3656 mv88e6xxx_reg_unlock(chip); 3657 3658 return ret; 3659 } 3660 3661 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3662 unsigned int ageing_time) 3663 { 3664 struct mv88e6xxx_chip *chip = ds->priv; 3665 int err; 3666 3667 mv88e6xxx_reg_lock(chip); 3668 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3669 mv88e6xxx_reg_unlock(chip); 3670 3671 return err; 3672 } 3673 3674 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3675 { 3676 int err; 3677 3678 /* Initialize the statistics unit */ 3679 if (chip->info->ops->stats_set_histogram) { 3680 err = chip->info->ops->stats_set_histogram(chip); 3681 if (err) 3682 return err; 3683 } 3684 3685 return mv88e6xxx_g1_stats_clear(chip); 3686 } 3687 3688 static int mv88e6320_setup_errata(struct mv88e6xxx_chip *chip) 3689 { 3690 u16 dummy; 3691 int err; 3692 3693 /* Workaround for erratum 3694 * 3.3 RGMII timing may be out of spec when transmit delay is enabled 3695 */ 3696 err = mv88e6xxx_port_hidden_write(chip, 0, 0xf, 0x7, 0xe000); 3697 if (err) 3698 return err; 3699 3700 return mv88e6xxx_port_hidden_read(chip, 0, 0xf, 0x7, &dummy); 3701 } 3702 3703 /* Check if the errata has already been applied. */ 3704 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3705 { 3706 int port; 3707 int err; 3708 u16 val; 3709 3710 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3711 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3712 if (err) { 3713 dev_err(chip->dev, 3714 "Error reading hidden register: %d\n", err); 3715 return false; 3716 } 3717 if (val != 0x01c0) 3718 return false; 3719 } 3720 3721 return true; 3722 } 3723 3724 /* The 6390 copper ports have an errata which require poking magic 3725 * values into undocumented hidden registers and then performing a 3726 * software reset. 3727 */ 3728 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3729 { 3730 int port; 3731 int err; 3732 3733 if (mv88e6390_setup_errata_applied(chip)) 3734 return 0; 3735 3736 /* Set the ports into blocking mode */ 3737 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3738 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3739 if (err) 3740 return err; 3741 } 3742 3743 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3744 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3745 if (err) 3746 return err; 3747 } 3748 3749 return mv88e6xxx_software_reset(chip); 3750 } 3751 3752 /* prod_id for switch families which do not have a PHY model number */ 3753 static const u16 family_prod_id_table[] = { 3754 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3755 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3756 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3757 }; 3758 3759 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3760 { 3761 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3762 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3763 u16 prod_id; 3764 u16 val; 3765 int err; 3766 3767 if (!chip->info->ops->phy_read) 3768 return -EOPNOTSUPP; 3769 3770 mv88e6xxx_reg_lock(chip); 3771 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3772 mv88e6xxx_reg_unlock(chip); 3773 3774 /* Some internal PHYs don't have a model number. */ 3775 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3776 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3777 prod_id = family_prod_id_table[chip->info->family]; 3778 if (prod_id) 3779 val |= prod_id >> 4; 3780 } 3781 3782 return err ? err : val; 3783 } 3784 3785 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3786 int reg) 3787 { 3788 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3789 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3790 u16 val; 3791 int err; 3792 3793 if (!chip->info->ops->phy_read_c45) 3794 return -ENODEV; 3795 3796 mv88e6xxx_reg_lock(chip); 3797 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3798 mv88e6xxx_reg_unlock(chip); 3799 3800 return err ? err : val; 3801 } 3802 3803 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3804 { 3805 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3806 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3807 int err; 3808 3809 if (!chip->info->ops->phy_write) 3810 return -EOPNOTSUPP; 3811 3812 mv88e6xxx_reg_lock(chip); 3813 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3814 mv88e6xxx_reg_unlock(chip); 3815 3816 return err; 3817 } 3818 3819 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3820 int reg, u16 val) 3821 { 3822 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3823 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3824 int err; 3825 3826 if (!chip->info->ops->phy_write_c45) 3827 return -EOPNOTSUPP; 3828 3829 mv88e6xxx_reg_lock(chip); 3830 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3831 mv88e6xxx_reg_unlock(chip); 3832 3833 return err; 3834 } 3835 3836 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3837 struct device_node *np, 3838 bool external) 3839 { 3840 static int index; 3841 struct mv88e6xxx_mdio_bus *mdio_bus; 3842 struct mii_bus *bus; 3843 int err; 3844 3845 if (external) { 3846 mv88e6xxx_reg_lock(chip); 3847 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3848 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3849 else 3850 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3851 mv88e6xxx_reg_unlock(chip); 3852 3853 if (err) 3854 return err; 3855 } 3856 3857 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3858 if (!bus) 3859 return -ENOMEM; 3860 3861 mdio_bus = bus->priv; 3862 mdio_bus->bus = bus; 3863 mdio_bus->chip = chip; 3864 INIT_LIST_HEAD(&mdio_bus->list); 3865 mdio_bus->external = external; 3866 3867 if (np) { 3868 bus->name = np->full_name; 3869 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3870 } else { 3871 bus->name = "mv88e6xxx SMI"; 3872 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3873 } 3874 3875 bus->read = mv88e6xxx_mdio_read; 3876 bus->write = mv88e6xxx_mdio_write; 3877 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3878 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3879 bus->parent = chip->dev; 3880 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3881 mv88e6xxx_num_ports(chip) - 1, 3882 chip->info->phy_base_addr); 3883 3884 if (!external) { 3885 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3886 if (err) 3887 goto out; 3888 } 3889 3890 err = of_mdiobus_register(bus, np); 3891 if (err) { 3892 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3893 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3894 goto out; 3895 } 3896 3897 if (external) 3898 list_add_tail(&mdio_bus->list, &chip->mdios); 3899 else 3900 list_add(&mdio_bus->list, &chip->mdios); 3901 3902 return 0; 3903 3904 out: 3905 mdiobus_free(bus); 3906 return err; 3907 } 3908 3909 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3910 3911 { 3912 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3913 struct mii_bus *bus; 3914 3915 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3916 bus = mdio_bus->bus; 3917 3918 if (!mdio_bus->external) 3919 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3920 3921 mdiobus_unregister(bus); 3922 mdiobus_free(bus); 3923 } 3924 } 3925 3926 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3927 { 3928 struct device_node *np = chip->dev->of_node; 3929 struct device_node *child; 3930 int err; 3931 3932 /* Always register one mdio bus for the internal/default mdio 3933 * bus. This maybe represented in the device tree, but is 3934 * optional. 3935 */ 3936 child = of_get_child_by_name(np, "mdio"); 3937 err = mv88e6xxx_mdio_register(chip, child, false); 3938 of_node_put(child); 3939 if (err) 3940 return err; 3941 3942 /* Walk the device tree, and see if there are any other nodes 3943 * which say they are compatible with the external mdio 3944 * bus. 3945 */ 3946 for_each_available_child_of_node(np, child) { 3947 if (of_device_is_compatible( 3948 child, "marvell,mv88e6xxx-mdio-external")) { 3949 err = mv88e6xxx_mdio_register(chip, child, true); 3950 if (err) { 3951 mv88e6xxx_mdios_unregister(chip); 3952 of_node_put(child); 3953 return err; 3954 } 3955 } 3956 } 3957 3958 return 0; 3959 } 3960 3961 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3962 { 3963 struct mv88e6xxx_chip *chip = ds->priv; 3964 3965 mv88e6xxx_teardown_devlink_params(ds); 3966 dsa_devlink_resources_unregister(ds); 3967 mv88e6xxx_teardown_devlink_regions_global(ds); 3968 mv88e6xxx_hwtstamp_free(chip); 3969 mv88e6xxx_ptp_free(chip); 3970 mv88e6xxx_mdios_unregister(chip); 3971 } 3972 3973 static int mv88e6xxx_setup(struct dsa_switch *ds) 3974 { 3975 struct mv88e6xxx_chip *chip = ds->priv; 3976 u8 cmode; 3977 int err; 3978 int i; 3979 3980 err = mv88e6xxx_mdios_register(chip); 3981 if (err) 3982 return err; 3983 3984 chip->ds = ds; 3985 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3986 3987 /* Since virtual bridges are mapped in the PVT, the number we support 3988 * depends on the physical switch topology. We need to let DSA figure 3989 * that out and therefore we cannot set this at dsa_register_switch() 3990 * time. 3991 */ 3992 if (mv88e6xxx_has_pvt(chip)) 3993 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3994 ds->dst->last_switch - 1; 3995 3996 mv88e6xxx_reg_lock(chip); 3997 3998 if (chip->info->ops->setup_errata) { 3999 err = chip->info->ops->setup_errata(chip); 4000 if (err) 4001 goto unlock; 4002 } 4003 4004 /* Cache the cmode of each port. */ 4005 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4006 if (chip->info->ops->port_get_cmode) { 4007 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 4008 if (err) 4009 goto unlock; 4010 4011 chip->ports[i].cmode = cmode; 4012 } 4013 } 4014 4015 err = mv88e6xxx_vtu_setup(chip); 4016 if (err) 4017 goto unlock; 4018 4019 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 4020 * VTU, thereby also flushing the STU). 4021 */ 4022 err = mv88e6xxx_stu_setup(chip); 4023 if (err) 4024 goto unlock; 4025 4026 /* Setup Switch Port Registers */ 4027 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4028 if (dsa_is_unused_port(ds, i)) 4029 continue; 4030 4031 /* Prevent the use of an invalid port. */ 4032 if (mv88e6xxx_is_invalid_port(chip, i)) { 4033 dev_err(chip->dev, "port %d is invalid\n", i); 4034 err = -EINVAL; 4035 goto unlock; 4036 } 4037 4038 err = mv88e6xxx_setup_port(chip, i); 4039 if (err) 4040 goto unlock; 4041 } 4042 4043 err = mv88e6xxx_irl_setup(chip); 4044 if (err) 4045 goto unlock; 4046 4047 err = mv88e6xxx_mac_setup(chip); 4048 if (err) 4049 goto unlock; 4050 4051 err = mv88e6xxx_phy_setup(chip); 4052 if (err) 4053 goto unlock; 4054 4055 err = mv88e6xxx_pvt_setup(chip); 4056 if (err) 4057 goto unlock; 4058 4059 err = mv88e6xxx_atu_setup(chip); 4060 if (err) 4061 goto unlock; 4062 4063 err = mv88e6xxx_broadcast_setup(chip, 0); 4064 if (err) 4065 goto unlock; 4066 4067 err = mv88e6xxx_pot_setup(chip); 4068 if (err) 4069 goto unlock; 4070 4071 err = mv88e6xxx_rmu_setup(chip); 4072 if (err) 4073 goto unlock; 4074 4075 err = mv88e6xxx_rsvd2cpu_setup(chip); 4076 if (err) 4077 goto unlock; 4078 4079 err = mv88e6xxx_trunk_setup(chip); 4080 if (err) 4081 goto unlock; 4082 4083 err = mv88e6xxx_devmap_setup(chip); 4084 if (err) 4085 goto unlock; 4086 4087 err = mv88e6xxx_pri_setup(chip); 4088 if (err) 4089 goto unlock; 4090 4091 /* Setup PTP Hardware Clock and timestamping */ 4092 if (chip->info->ptp_support) { 4093 err = mv88e6xxx_ptp_setup(chip); 4094 if (err) 4095 goto unlock; 4096 4097 err = mv88e6xxx_hwtstamp_setup(chip); 4098 if (err) 4099 goto unlock; 4100 } 4101 4102 err = mv88e6xxx_stats_setup(chip); 4103 if (err) 4104 goto unlock; 4105 4106 unlock: 4107 mv88e6xxx_reg_unlock(chip); 4108 4109 if (err) 4110 goto out_hwtstamp; 4111 4112 /* Have to be called without holding the register lock, since 4113 * they take the devlink lock, and we later take the locks in 4114 * the reverse order when getting/setting parameters or 4115 * resource occupancy. 4116 */ 4117 err = mv88e6xxx_setup_devlink_resources(ds); 4118 if (err) 4119 goto out_hwtstamp; 4120 4121 err = mv88e6xxx_setup_devlink_params(ds); 4122 if (err) 4123 goto out_resources; 4124 4125 err = mv88e6xxx_setup_devlink_regions_global(ds); 4126 if (err) 4127 goto out_params; 4128 4129 return 0; 4130 4131 out_params: 4132 mv88e6xxx_teardown_devlink_params(ds); 4133 out_resources: 4134 dsa_devlink_resources_unregister(ds); 4135 out_hwtstamp: 4136 mv88e6xxx_hwtstamp_free(chip); 4137 mv88e6xxx_ptp_free(chip); 4138 mv88e6xxx_mdios_unregister(chip); 4139 4140 return err; 4141 } 4142 4143 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4144 { 4145 struct mv88e6xxx_chip *chip = ds->priv; 4146 int err; 4147 4148 if (chip->info->ops->pcs_ops && 4149 chip->info->ops->pcs_ops->pcs_init) { 4150 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4151 if (err) 4152 return err; 4153 } 4154 4155 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4156 } 4157 4158 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4159 { 4160 struct mv88e6xxx_chip *chip = ds->priv; 4161 4162 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4163 4164 if (chip->info->ops->pcs_ops && 4165 chip->info->ops->pcs_ops->pcs_teardown) 4166 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4167 } 4168 4169 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4170 { 4171 struct mv88e6xxx_chip *chip = ds->priv; 4172 4173 return chip->eeprom_len; 4174 } 4175 4176 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4177 struct ethtool_eeprom *eeprom, u8 *data) 4178 { 4179 struct mv88e6xxx_chip *chip = ds->priv; 4180 int err; 4181 4182 if (!chip->info->ops->get_eeprom) 4183 return -EOPNOTSUPP; 4184 4185 mv88e6xxx_reg_lock(chip); 4186 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4187 mv88e6xxx_reg_unlock(chip); 4188 4189 if (err) 4190 return err; 4191 4192 eeprom->magic = 0xc3ec4951; 4193 4194 return 0; 4195 } 4196 4197 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4198 struct ethtool_eeprom *eeprom, u8 *data) 4199 { 4200 struct mv88e6xxx_chip *chip = ds->priv; 4201 int err; 4202 4203 if (!chip->info->ops->set_eeprom) 4204 return -EOPNOTSUPP; 4205 4206 if (eeprom->magic != 0xc3ec4951) 4207 return -EINVAL; 4208 4209 mv88e6xxx_reg_lock(chip); 4210 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4211 mv88e6xxx_reg_unlock(chip); 4212 4213 return err; 4214 } 4215 4216 static const struct mv88e6xxx_ops mv88e6085_ops = { 4217 /* MV88E6XXX_FAMILY_6097 */ 4218 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4219 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4220 .irl_init_all = mv88e6352_g2_irl_init_all, 4221 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4222 .phy_read = mv88e6185_phy_ppu_read, 4223 .phy_write = mv88e6185_phy_ppu_write, 4224 .port_set_link = mv88e6xxx_port_set_link, 4225 .port_sync_link = mv88e6xxx_port_sync_link, 4226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4227 .port_tag_remap = mv88e6095_port_tag_remap, 4228 .port_set_policy = mv88e6352_port_set_policy, 4229 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4230 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4231 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4232 .port_set_ether_type = mv88e6351_port_set_ether_type, 4233 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4234 .port_pause_limit = mv88e6097_port_pause_limit, 4235 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4236 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4237 .port_get_cmode = mv88e6185_port_get_cmode, 4238 .port_setup_message_port = mv88e6xxx_setup_message_port, 4239 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4240 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4241 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4242 .stats_get_strings = mv88e6095_stats_get_strings, 4243 .stats_get_stat = mv88e6095_stats_get_stat, 4244 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4245 .set_egress_port = mv88e6095_g1_set_egress_port, 4246 .watchdog_ops = &mv88e6097_watchdog_ops, 4247 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4248 .pot_clear = mv88e6xxx_g2_pot_clear, 4249 .ppu_enable = mv88e6185_g1_ppu_enable, 4250 .ppu_disable = mv88e6185_g1_ppu_disable, 4251 .reset = mv88e6185_g1_reset, 4252 .rmu_disable = mv88e6085_g1_rmu_disable, 4253 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4254 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4255 .stu_getnext = mv88e6352_g1_stu_getnext, 4256 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4257 .phylink_get_caps = mv88e6185_phylink_get_caps, 4258 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4259 }; 4260 4261 static const struct mv88e6xxx_ops mv88e6095_ops = { 4262 /* MV88E6XXX_FAMILY_6095 */ 4263 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4264 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4265 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4266 .phy_read = mv88e6185_phy_ppu_read, 4267 .phy_write = mv88e6185_phy_ppu_write, 4268 .port_set_link = mv88e6xxx_port_set_link, 4269 .port_sync_link = mv88e6185_port_sync_link, 4270 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4271 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4272 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4273 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4274 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4275 .port_get_cmode = mv88e6185_port_get_cmode, 4276 .port_setup_message_port = mv88e6xxx_setup_message_port, 4277 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4278 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4279 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4280 .stats_get_strings = mv88e6095_stats_get_strings, 4281 .stats_get_stat = mv88e6095_stats_get_stat, 4282 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4283 .ppu_enable = mv88e6185_g1_ppu_enable, 4284 .ppu_disable = mv88e6185_g1_ppu_disable, 4285 .reset = mv88e6185_g1_reset, 4286 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4287 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4288 .phylink_get_caps = mv88e6095_phylink_get_caps, 4289 .pcs_ops = &mv88e6185_pcs_ops, 4290 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4291 }; 4292 4293 static const struct mv88e6xxx_ops mv88e6097_ops = { 4294 /* MV88E6XXX_FAMILY_6097 */ 4295 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4296 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4297 .irl_init_all = mv88e6352_g2_irl_init_all, 4298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4299 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4300 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4301 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4302 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4303 .port_set_link = mv88e6xxx_port_set_link, 4304 .port_sync_link = mv88e6185_port_sync_link, 4305 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4306 .port_tag_remap = mv88e6095_port_tag_remap, 4307 .port_set_policy = mv88e6352_port_set_policy, 4308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4309 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4310 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4311 .port_set_ether_type = mv88e6351_port_set_ether_type, 4312 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4313 .port_pause_limit = mv88e6097_port_pause_limit, 4314 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4315 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4316 .port_get_cmode = mv88e6185_port_get_cmode, 4317 .port_setup_message_port = mv88e6xxx_setup_message_port, 4318 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4319 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4320 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4321 .stats_get_strings = mv88e6095_stats_get_strings, 4322 .stats_get_stat = mv88e6095_stats_get_stat, 4323 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4324 .set_egress_port = mv88e6095_g1_set_egress_port, 4325 .watchdog_ops = &mv88e6097_watchdog_ops, 4326 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4327 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4328 .pot_clear = mv88e6xxx_g2_pot_clear, 4329 .reset = mv88e6352_g1_reset, 4330 .rmu_disable = mv88e6085_g1_rmu_disable, 4331 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4332 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4333 .phylink_get_caps = mv88e6095_phylink_get_caps, 4334 .pcs_ops = &mv88e6185_pcs_ops, 4335 .stu_getnext = mv88e6352_g1_stu_getnext, 4336 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4337 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4338 }; 4339 4340 static const struct mv88e6xxx_ops mv88e6123_ops = { 4341 /* MV88E6XXX_FAMILY_6165 */ 4342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4343 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4344 .irl_init_all = mv88e6352_g2_irl_init_all, 4345 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4346 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4347 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4348 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4349 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4350 .port_set_link = mv88e6xxx_port_set_link, 4351 .port_sync_link = mv88e6xxx_port_sync_link, 4352 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4353 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4354 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4355 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4356 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4357 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4358 .port_get_cmode = mv88e6185_port_get_cmode, 4359 .port_setup_message_port = mv88e6xxx_setup_message_port, 4360 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4361 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4362 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4363 .stats_get_strings = mv88e6095_stats_get_strings, 4364 .stats_get_stat = mv88e6095_stats_get_stat, 4365 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4366 .set_egress_port = mv88e6095_g1_set_egress_port, 4367 .watchdog_ops = &mv88e6097_watchdog_ops, 4368 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4369 .pot_clear = mv88e6xxx_g2_pot_clear, 4370 .reset = mv88e6352_g1_reset, 4371 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4372 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4373 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4374 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4375 .stu_getnext = mv88e6352_g1_stu_getnext, 4376 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4377 .phylink_get_caps = mv88e6185_phylink_get_caps, 4378 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4379 }; 4380 4381 static const struct mv88e6xxx_ops mv88e6131_ops = { 4382 /* MV88E6XXX_FAMILY_6185 */ 4383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4384 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4385 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4386 .phy_read = mv88e6185_phy_ppu_read, 4387 .phy_write = mv88e6185_phy_ppu_write, 4388 .port_set_link = mv88e6xxx_port_set_link, 4389 .port_sync_link = mv88e6xxx_port_sync_link, 4390 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4391 .port_tag_remap = mv88e6095_port_tag_remap, 4392 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4393 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4394 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4395 .port_set_ether_type = mv88e6351_port_set_ether_type, 4396 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4397 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4398 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4399 .port_pause_limit = mv88e6097_port_pause_limit, 4400 .port_set_pause = mv88e6185_port_set_pause, 4401 .port_get_cmode = mv88e6185_port_get_cmode, 4402 .port_setup_message_port = mv88e6xxx_setup_message_port, 4403 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4405 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4406 .stats_get_strings = mv88e6095_stats_get_strings, 4407 .stats_get_stat = mv88e6095_stats_get_stat, 4408 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4409 .set_egress_port = mv88e6095_g1_set_egress_port, 4410 .watchdog_ops = &mv88e6097_watchdog_ops, 4411 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4412 .ppu_enable = mv88e6185_g1_ppu_enable, 4413 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4414 .ppu_disable = mv88e6185_g1_ppu_disable, 4415 .reset = mv88e6185_g1_reset, 4416 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4417 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4418 .phylink_get_caps = mv88e6185_phylink_get_caps, 4419 }; 4420 4421 static const struct mv88e6xxx_ops mv88e6141_ops = { 4422 /* MV88E6XXX_FAMILY_6341 */ 4423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4424 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4425 .irl_init_all = mv88e6352_g2_irl_init_all, 4426 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4427 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4429 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4430 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4431 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4432 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4433 .port_set_link = mv88e6xxx_port_set_link, 4434 .port_sync_link = mv88e6xxx_port_sync_link, 4435 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4436 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4437 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4438 .port_tag_remap = mv88e6095_port_tag_remap, 4439 .port_set_policy = mv88e6352_port_set_policy, 4440 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4441 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4442 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4443 .port_set_ether_type = mv88e6351_port_set_ether_type, 4444 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4445 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4446 .port_pause_limit = mv88e6097_port_pause_limit, 4447 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4448 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4449 .port_get_cmode = mv88e6352_port_get_cmode, 4450 .port_set_cmode = mv88e6341_port_set_cmode, 4451 .port_setup_message_port = mv88e6xxx_setup_message_port, 4452 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4453 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4454 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4455 .stats_get_strings = mv88e6320_stats_get_strings, 4456 .stats_get_stat = mv88e6390_stats_get_stat, 4457 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4458 .set_egress_port = mv88e6390_g1_set_egress_port, 4459 .watchdog_ops = &mv88e6390_watchdog_ops, 4460 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4461 .pot_clear = mv88e6xxx_g2_pot_clear, 4462 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4463 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4464 .reset = mv88e6352_g1_reset, 4465 .rmu_disable = mv88e6390_g1_rmu_disable, 4466 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4467 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4468 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4469 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4470 .stu_getnext = mv88e6352_g1_stu_getnext, 4471 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4472 .serdes_get_lane = mv88e6341_serdes_get_lane, 4473 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4474 .gpio_ops = &mv88e6352_gpio_ops, 4475 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4476 .serdes_get_strings = mv88e6390_serdes_get_strings, 4477 .serdes_get_stats = mv88e6390_serdes_get_stats, 4478 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4479 .serdes_get_regs = mv88e6390_serdes_get_regs, 4480 .phylink_get_caps = mv88e6341_phylink_get_caps, 4481 .pcs_ops = &mv88e6390_pcs_ops, 4482 }; 4483 4484 static const struct mv88e6xxx_ops mv88e6161_ops = { 4485 /* MV88E6XXX_FAMILY_6165 */ 4486 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4487 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4488 .irl_init_all = mv88e6352_g2_irl_init_all, 4489 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4490 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4491 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4492 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4493 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4494 .port_set_link = mv88e6xxx_port_set_link, 4495 .port_sync_link = mv88e6xxx_port_sync_link, 4496 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4497 .port_tag_remap = mv88e6095_port_tag_remap, 4498 .port_set_policy = mv88e6352_port_set_policy, 4499 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4500 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4501 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4502 .port_set_ether_type = mv88e6351_port_set_ether_type, 4503 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4504 .port_pause_limit = mv88e6097_port_pause_limit, 4505 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4506 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4507 .port_get_cmode = mv88e6185_port_get_cmode, 4508 .port_setup_message_port = mv88e6xxx_setup_message_port, 4509 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4510 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4511 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4512 .stats_get_strings = mv88e6095_stats_get_strings, 4513 .stats_get_stat = mv88e6095_stats_get_stat, 4514 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4515 .set_egress_port = mv88e6095_g1_set_egress_port, 4516 .watchdog_ops = &mv88e6097_watchdog_ops, 4517 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4518 .pot_clear = mv88e6xxx_g2_pot_clear, 4519 .reset = mv88e6352_g1_reset, 4520 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4521 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4522 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4523 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4524 .stu_getnext = mv88e6352_g1_stu_getnext, 4525 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4526 .avb_ops = &mv88e6165_avb_ops, 4527 .ptp_ops = &mv88e6165_ptp_ops, 4528 .phylink_get_caps = mv88e6185_phylink_get_caps, 4529 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4530 }; 4531 4532 static const struct mv88e6xxx_ops mv88e6165_ops = { 4533 /* MV88E6XXX_FAMILY_6165 */ 4534 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4535 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4536 .irl_init_all = mv88e6352_g2_irl_init_all, 4537 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4538 .phy_read = mv88e6165_phy_read, 4539 .phy_write = mv88e6165_phy_write, 4540 .port_set_link = mv88e6xxx_port_set_link, 4541 .port_sync_link = mv88e6xxx_port_sync_link, 4542 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4545 .port_get_cmode = mv88e6185_port_get_cmode, 4546 .port_setup_message_port = mv88e6xxx_setup_message_port, 4547 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4548 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4549 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4550 .stats_get_strings = mv88e6095_stats_get_strings, 4551 .stats_get_stat = mv88e6095_stats_get_stat, 4552 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4553 .set_egress_port = mv88e6095_g1_set_egress_port, 4554 .watchdog_ops = &mv88e6097_watchdog_ops, 4555 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4556 .pot_clear = mv88e6xxx_g2_pot_clear, 4557 .reset = mv88e6352_g1_reset, 4558 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4559 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4560 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4561 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4562 .stu_getnext = mv88e6352_g1_stu_getnext, 4563 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4564 .avb_ops = &mv88e6165_avb_ops, 4565 .ptp_ops = &mv88e6165_ptp_ops, 4566 .phylink_get_caps = mv88e6185_phylink_get_caps, 4567 }; 4568 4569 static const struct mv88e6xxx_ops mv88e6171_ops = { 4570 /* MV88E6XXX_FAMILY_6351 */ 4571 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4572 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4573 .irl_init_all = mv88e6352_g2_irl_init_all, 4574 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4575 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4576 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4577 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4578 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4579 .port_set_link = mv88e6xxx_port_set_link, 4580 .port_sync_link = mv88e6xxx_port_sync_link, 4581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4582 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4583 .port_tag_remap = mv88e6095_port_tag_remap, 4584 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4585 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4586 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4587 .port_set_ether_type = mv88e6351_port_set_ether_type, 4588 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4589 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4590 .port_pause_limit = mv88e6097_port_pause_limit, 4591 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4592 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4593 .port_get_cmode = mv88e6352_port_get_cmode, 4594 .port_setup_message_port = mv88e6xxx_setup_message_port, 4595 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4597 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4598 .stats_get_strings = mv88e6095_stats_get_strings, 4599 .stats_get_stat = mv88e6095_stats_get_stat, 4600 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4601 .set_egress_port = mv88e6095_g1_set_egress_port, 4602 .watchdog_ops = &mv88e6097_watchdog_ops, 4603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4604 .pot_clear = mv88e6xxx_g2_pot_clear, 4605 .reset = mv88e6352_g1_reset, 4606 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4607 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4608 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4609 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4610 .stu_getnext = mv88e6352_g1_stu_getnext, 4611 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4612 .phylink_get_caps = mv88e6351_phylink_get_caps, 4613 }; 4614 4615 static const struct mv88e6xxx_ops mv88e6172_ops = { 4616 /* MV88E6XXX_FAMILY_6352 */ 4617 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4618 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4619 .irl_init_all = mv88e6352_g2_irl_init_all, 4620 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4621 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4623 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4624 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4625 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4626 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4627 .port_set_link = mv88e6xxx_port_set_link, 4628 .port_sync_link = mv88e6xxx_port_sync_link, 4629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4630 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4631 .port_tag_remap = mv88e6095_port_tag_remap, 4632 .port_set_policy = mv88e6352_port_set_policy, 4633 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4634 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4635 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4636 .port_set_ether_type = mv88e6351_port_set_ether_type, 4637 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4638 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4639 .port_pause_limit = mv88e6097_port_pause_limit, 4640 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4641 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4642 .port_get_cmode = mv88e6352_port_get_cmode, 4643 .port_setup_leds = mv88e6xxx_port_setup_leds, 4644 .port_setup_message_port = mv88e6xxx_setup_message_port, 4645 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4646 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4647 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4648 .stats_get_strings = mv88e6095_stats_get_strings, 4649 .stats_get_stat = mv88e6095_stats_get_stat, 4650 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4651 .set_egress_port = mv88e6095_g1_set_egress_port, 4652 .watchdog_ops = &mv88e6097_watchdog_ops, 4653 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4654 .pot_clear = mv88e6xxx_g2_pot_clear, 4655 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4656 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4657 .reset = mv88e6352_g1_reset, 4658 .rmu_disable = mv88e6352_g1_rmu_disable, 4659 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4660 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4661 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4662 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4663 .stu_getnext = mv88e6352_g1_stu_getnext, 4664 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4665 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4666 .serdes_get_regs = mv88e6352_serdes_get_regs, 4667 .gpio_ops = &mv88e6352_gpio_ops, 4668 .phylink_get_caps = mv88e6352_phylink_get_caps, 4669 .pcs_ops = &mv88e6352_pcs_ops, 4670 }; 4671 4672 static const struct mv88e6xxx_ops mv88e6175_ops = { 4673 /* MV88E6XXX_FAMILY_6351 */ 4674 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4675 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4676 .irl_init_all = mv88e6352_g2_irl_init_all, 4677 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4678 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4679 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4680 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4681 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4682 .port_set_link = mv88e6xxx_port_set_link, 4683 .port_sync_link = mv88e6xxx_port_sync_link, 4684 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4685 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4686 .port_tag_remap = mv88e6095_port_tag_remap, 4687 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4688 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4689 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4690 .port_set_ether_type = mv88e6351_port_set_ether_type, 4691 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4692 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4693 .port_pause_limit = mv88e6097_port_pause_limit, 4694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4696 .port_get_cmode = mv88e6352_port_get_cmode, 4697 .port_setup_message_port = mv88e6xxx_setup_message_port, 4698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4700 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4701 .stats_get_strings = mv88e6095_stats_get_strings, 4702 .stats_get_stat = mv88e6095_stats_get_stat, 4703 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4704 .set_egress_port = mv88e6095_g1_set_egress_port, 4705 .watchdog_ops = &mv88e6097_watchdog_ops, 4706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4707 .pot_clear = mv88e6xxx_g2_pot_clear, 4708 .reset = mv88e6352_g1_reset, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4713 .stu_getnext = mv88e6352_g1_stu_getnext, 4714 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4715 .phylink_get_caps = mv88e6351_phylink_get_caps, 4716 }; 4717 4718 static const struct mv88e6xxx_ops mv88e6176_ops = { 4719 /* MV88E6XXX_FAMILY_6352 */ 4720 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4721 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4722 .irl_init_all = mv88e6352_g2_irl_init_all, 4723 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4724 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4726 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4727 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4728 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4729 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4730 .port_set_link = mv88e6xxx_port_set_link, 4731 .port_sync_link = mv88e6xxx_port_sync_link, 4732 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4733 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4734 .port_tag_remap = mv88e6095_port_tag_remap, 4735 .port_set_policy = mv88e6352_port_set_policy, 4736 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4737 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4738 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4739 .port_set_ether_type = mv88e6351_port_set_ether_type, 4740 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4741 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4742 .port_pause_limit = mv88e6097_port_pause_limit, 4743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4745 .port_get_cmode = mv88e6352_port_get_cmode, 4746 .port_setup_leds = mv88e6xxx_port_setup_leds, 4747 .port_setup_message_port = mv88e6xxx_setup_message_port, 4748 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4749 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4750 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4751 .stats_get_strings = mv88e6095_stats_get_strings, 4752 .stats_get_stat = mv88e6095_stats_get_stat, 4753 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4754 .set_egress_port = mv88e6095_g1_set_egress_port, 4755 .watchdog_ops = &mv88e6097_watchdog_ops, 4756 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4757 .pot_clear = mv88e6xxx_g2_pot_clear, 4758 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4759 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4760 .reset = mv88e6352_g1_reset, 4761 .rmu_disable = mv88e6352_g1_rmu_disable, 4762 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4763 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4764 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4765 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4766 .stu_getnext = mv88e6352_g1_stu_getnext, 4767 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4768 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4769 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4770 .serdes_get_regs = mv88e6352_serdes_get_regs, 4771 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4772 .gpio_ops = &mv88e6352_gpio_ops, 4773 .phylink_get_caps = mv88e6352_phylink_get_caps, 4774 .pcs_ops = &mv88e6352_pcs_ops, 4775 }; 4776 4777 static const struct mv88e6xxx_ops mv88e6185_ops = { 4778 /* MV88E6XXX_FAMILY_6185 */ 4779 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4780 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4781 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4782 .phy_read = mv88e6185_phy_ppu_read, 4783 .phy_write = mv88e6185_phy_ppu_write, 4784 .port_set_link = mv88e6xxx_port_set_link, 4785 .port_sync_link = mv88e6185_port_sync_link, 4786 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4787 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4788 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4789 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4790 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4791 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4792 .port_set_pause = mv88e6185_port_set_pause, 4793 .port_get_cmode = mv88e6185_port_get_cmode, 4794 .port_setup_message_port = mv88e6xxx_setup_message_port, 4795 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4796 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4797 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4798 .stats_get_strings = mv88e6095_stats_get_strings, 4799 .stats_get_stat = mv88e6095_stats_get_stat, 4800 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4801 .set_egress_port = mv88e6095_g1_set_egress_port, 4802 .watchdog_ops = &mv88e6097_watchdog_ops, 4803 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4804 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4805 .ppu_enable = mv88e6185_g1_ppu_enable, 4806 .ppu_disable = mv88e6185_g1_ppu_disable, 4807 .reset = mv88e6185_g1_reset, 4808 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4809 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4810 .phylink_get_caps = mv88e6185_phylink_get_caps, 4811 .pcs_ops = &mv88e6185_pcs_ops, 4812 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4813 }; 4814 4815 static const struct mv88e6xxx_ops mv88e6190_ops = { 4816 /* MV88E6XXX_FAMILY_6390 */ 4817 .setup_errata = mv88e6390_setup_errata, 4818 .irl_init_all = mv88e6390_g2_irl_init_all, 4819 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4820 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4822 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4823 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4824 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4825 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4826 .port_set_link = mv88e6xxx_port_set_link, 4827 .port_sync_link = mv88e6xxx_port_sync_link, 4828 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4829 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4830 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4831 .port_tag_remap = mv88e6390_port_tag_remap, 4832 .port_set_policy = mv88e6352_port_set_policy, 4833 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4834 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4835 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4836 .port_set_ether_type = mv88e6351_port_set_ether_type, 4837 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4838 .port_pause_limit = mv88e6390_port_pause_limit, 4839 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4840 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4841 .port_get_cmode = mv88e6352_port_get_cmode, 4842 .port_set_cmode = mv88e6390_port_set_cmode, 4843 .port_setup_message_port = mv88e6xxx_setup_message_port, 4844 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4845 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4846 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4847 .stats_get_strings = mv88e6320_stats_get_strings, 4848 .stats_get_stat = mv88e6390_stats_get_stat, 4849 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4850 .set_egress_port = mv88e6390_g1_set_egress_port, 4851 .watchdog_ops = &mv88e6390_watchdog_ops, 4852 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4853 .pot_clear = mv88e6xxx_g2_pot_clear, 4854 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4855 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4856 .reset = mv88e6352_g1_reset, 4857 .rmu_disable = mv88e6390_g1_rmu_disable, 4858 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4859 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4860 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4861 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4862 .stu_getnext = mv88e6390_g1_stu_getnext, 4863 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4864 .serdes_get_lane = mv88e6390_serdes_get_lane, 4865 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4866 .serdes_get_strings = mv88e6390_serdes_get_strings, 4867 .serdes_get_stats = mv88e6390_serdes_get_stats, 4868 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4869 .serdes_get_regs = mv88e6390_serdes_get_regs, 4870 .gpio_ops = &mv88e6352_gpio_ops, 4871 .phylink_get_caps = mv88e6390_phylink_get_caps, 4872 .pcs_ops = &mv88e6390_pcs_ops, 4873 }; 4874 4875 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4876 /* MV88E6XXX_FAMILY_6390 */ 4877 .setup_errata = mv88e6390_setup_errata, 4878 .irl_init_all = mv88e6390_g2_irl_init_all, 4879 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4880 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4881 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4882 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4883 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4884 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4885 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4886 .port_set_link = mv88e6xxx_port_set_link, 4887 .port_sync_link = mv88e6xxx_port_sync_link, 4888 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4889 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4890 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4891 .port_tag_remap = mv88e6390_port_tag_remap, 4892 .port_set_policy = mv88e6352_port_set_policy, 4893 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4894 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4895 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4896 .port_set_ether_type = mv88e6351_port_set_ether_type, 4897 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4898 .port_pause_limit = mv88e6390_port_pause_limit, 4899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4901 .port_get_cmode = mv88e6352_port_get_cmode, 4902 .port_set_cmode = mv88e6390x_port_set_cmode, 4903 .port_setup_message_port = mv88e6xxx_setup_message_port, 4904 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4905 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4906 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4907 .stats_get_strings = mv88e6320_stats_get_strings, 4908 .stats_get_stat = mv88e6390_stats_get_stat, 4909 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4910 .set_egress_port = mv88e6390_g1_set_egress_port, 4911 .watchdog_ops = &mv88e6390_watchdog_ops, 4912 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4913 .pot_clear = mv88e6xxx_g2_pot_clear, 4914 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4915 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4916 .reset = mv88e6352_g1_reset, 4917 .rmu_disable = mv88e6390_g1_rmu_disable, 4918 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4919 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4920 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4921 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4922 .stu_getnext = mv88e6390_g1_stu_getnext, 4923 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4924 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4925 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4926 .serdes_get_strings = mv88e6390_serdes_get_strings, 4927 .serdes_get_stats = mv88e6390_serdes_get_stats, 4928 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4929 .serdes_get_regs = mv88e6390_serdes_get_regs, 4930 .gpio_ops = &mv88e6352_gpio_ops, 4931 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4932 .pcs_ops = &mv88e6390_pcs_ops, 4933 }; 4934 4935 static const struct mv88e6xxx_ops mv88e6191_ops = { 4936 /* MV88E6XXX_FAMILY_6390 */ 4937 .setup_errata = mv88e6390_setup_errata, 4938 .irl_init_all = mv88e6390_g2_irl_init_all, 4939 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4940 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4941 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4942 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4943 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4944 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4945 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4946 .port_set_link = mv88e6xxx_port_set_link, 4947 .port_sync_link = mv88e6xxx_port_sync_link, 4948 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4949 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4950 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4951 .port_tag_remap = mv88e6390_port_tag_remap, 4952 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4953 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4954 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4955 .port_set_ether_type = mv88e6351_port_set_ether_type, 4956 .port_pause_limit = mv88e6390_port_pause_limit, 4957 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4958 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4959 .port_get_cmode = mv88e6352_port_get_cmode, 4960 .port_set_cmode = mv88e6390_port_set_cmode, 4961 .port_setup_message_port = mv88e6xxx_setup_message_port, 4962 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4963 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4964 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4965 .stats_get_strings = mv88e6320_stats_get_strings, 4966 .stats_get_stat = mv88e6390_stats_get_stat, 4967 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4968 .set_egress_port = mv88e6390_g1_set_egress_port, 4969 .watchdog_ops = &mv88e6390_watchdog_ops, 4970 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4971 .pot_clear = mv88e6xxx_g2_pot_clear, 4972 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4973 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4974 .reset = mv88e6352_g1_reset, 4975 .rmu_disable = mv88e6390_g1_rmu_disable, 4976 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4977 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4978 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4979 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4980 .stu_getnext = mv88e6390_g1_stu_getnext, 4981 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4982 .serdes_get_lane = mv88e6390_serdes_get_lane, 4983 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4984 .serdes_get_strings = mv88e6390_serdes_get_strings, 4985 .serdes_get_stats = mv88e6390_serdes_get_stats, 4986 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4987 .serdes_get_regs = mv88e6390_serdes_get_regs, 4988 .avb_ops = &mv88e6390_avb_ops, 4989 .ptp_ops = &mv88e6352_ptp_ops, 4990 .phylink_get_caps = mv88e6390_phylink_get_caps, 4991 .pcs_ops = &mv88e6390_pcs_ops, 4992 }; 4993 4994 static const struct mv88e6xxx_ops mv88e6240_ops = { 4995 /* MV88E6XXX_FAMILY_6352 */ 4996 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4997 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4998 .irl_init_all = mv88e6352_g2_irl_init_all, 4999 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5000 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5001 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5002 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5003 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5004 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5005 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5006 .port_set_link = mv88e6xxx_port_set_link, 5007 .port_sync_link = mv88e6xxx_port_sync_link, 5008 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5009 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5010 .port_tag_remap = mv88e6095_port_tag_remap, 5011 .port_set_policy = mv88e6352_port_set_policy, 5012 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5013 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5014 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5015 .port_set_ether_type = mv88e6351_port_set_ether_type, 5016 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5017 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5018 .port_pause_limit = mv88e6097_port_pause_limit, 5019 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5020 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5021 .port_get_cmode = mv88e6352_port_get_cmode, 5022 .port_setup_leds = mv88e6xxx_port_setup_leds, 5023 .port_setup_message_port = mv88e6xxx_setup_message_port, 5024 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5025 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5026 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5027 .stats_get_strings = mv88e6095_stats_get_strings, 5028 .stats_get_stat = mv88e6095_stats_get_stat, 5029 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5030 .set_egress_port = mv88e6095_g1_set_egress_port, 5031 .watchdog_ops = &mv88e6097_watchdog_ops, 5032 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5033 .pot_clear = mv88e6xxx_g2_pot_clear, 5034 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5035 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5036 .reset = mv88e6352_g1_reset, 5037 .rmu_disable = mv88e6352_g1_rmu_disable, 5038 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5039 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5040 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5041 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5042 .stu_getnext = mv88e6352_g1_stu_getnext, 5043 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5044 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5045 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5046 .serdes_get_regs = mv88e6352_serdes_get_regs, 5047 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5048 .gpio_ops = &mv88e6352_gpio_ops, 5049 .avb_ops = &mv88e6352_avb_ops, 5050 .ptp_ops = &mv88e6352_ptp_ops, 5051 .phylink_get_caps = mv88e6352_phylink_get_caps, 5052 .pcs_ops = &mv88e6352_pcs_ops, 5053 }; 5054 5055 static const struct mv88e6xxx_ops mv88e6250_ops = { 5056 /* MV88E6XXX_FAMILY_6250 */ 5057 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5058 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5059 .irl_init_all = mv88e6352_g2_irl_init_all, 5060 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5061 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5062 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5063 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5064 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5065 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5066 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5067 .port_set_link = mv88e6xxx_port_set_link, 5068 .port_sync_link = mv88e6xxx_port_sync_link, 5069 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5070 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5071 .port_tag_remap = mv88e6095_port_tag_remap, 5072 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5073 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5074 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5075 .port_set_ether_type = mv88e6351_port_set_ether_type, 5076 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5077 .port_pause_limit = mv88e6097_port_pause_limit, 5078 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5079 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5080 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5081 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5082 .stats_get_strings = mv88e6250_stats_get_strings, 5083 .stats_get_stat = mv88e6250_stats_get_stat, 5084 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5085 .set_egress_port = mv88e6095_g1_set_egress_port, 5086 .watchdog_ops = &mv88e6250_watchdog_ops, 5087 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5088 .pot_clear = mv88e6xxx_g2_pot_clear, 5089 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5090 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5091 .reset = mv88e6250_g1_reset, 5092 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5093 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5094 .avb_ops = &mv88e6352_avb_ops, 5095 .ptp_ops = &mv88e6352_ptp_ops, 5096 .phylink_get_caps = mv88e6250_phylink_get_caps, 5097 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5098 }; 5099 5100 static const struct mv88e6xxx_ops mv88e6290_ops = { 5101 /* MV88E6XXX_FAMILY_6390 */ 5102 .setup_errata = mv88e6390_setup_errata, 5103 .irl_init_all = mv88e6390_g2_irl_init_all, 5104 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5105 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5106 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5107 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5108 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5109 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5110 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5111 .port_set_link = mv88e6xxx_port_set_link, 5112 .port_sync_link = mv88e6xxx_port_sync_link, 5113 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5114 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5115 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5116 .port_tag_remap = mv88e6390_port_tag_remap, 5117 .port_set_policy = mv88e6352_port_set_policy, 5118 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5119 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5120 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5121 .port_set_ether_type = mv88e6351_port_set_ether_type, 5122 .port_pause_limit = mv88e6390_port_pause_limit, 5123 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5124 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5125 .port_get_cmode = mv88e6352_port_get_cmode, 5126 .port_set_cmode = mv88e6390_port_set_cmode, 5127 .port_setup_message_port = mv88e6xxx_setup_message_port, 5128 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5129 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5130 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5131 .stats_get_strings = mv88e6320_stats_get_strings, 5132 .stats_get_stat = mv88e6390_stats_get_stat, 5133 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5134 .set_egress_port = mv88e6390_g1_set_egress_port, 5135 .watchdog_ops = &mv88e6390_watchdog_ops, 5136 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5137 .pot_clear = mv88e6xxx_g2_pot_clear, 5138 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5139 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5140 .reset = mv88e6352_g1_reset, 5141 .rmu_disable = mv88e6390_g1_rmu_disable, 5142 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5143 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5144 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5145 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5146 .stu_getnext = mv88e6390_g1_stu_getnext, 5147 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5148 .serdes_get_lane = mv88e6390_serdes_get_lane, 5149 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5150 .serdes_get_strings = mv88e6390_serdes_get_strings, 5151 .serdes_get_stats = mv88e6390_serdes_get_stats, 5152 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5153 .serdes_get_regs = mv88e6390_serdes_get_regs, 5154 .gpio_ops = &mv88e6352_gpio_ops, 5155 .avb_ops = &mv88e6390_avb_ops, 5156 .ptp_ops = &mv88e6390_ptp_ops, 5157 .phylink_get_caps = mv88e6390_phylink_get_caps, 5158 .pcs_ops = &mv88e6390_pcs_ops, 5159 }; 5160 5161 static const struct mv88e6xxx_ops mv88e6320_ops = { 5162 /* MV88E6XXX_FAMILY_6320 */ 5163 .setup_errata = mv88e6320_setup_errata, 5164 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5165 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5166 .irl_init_all = mv88e6352_g2_irl_init_all, 5167 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5168 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5169 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5170 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5171 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5172 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5173 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5174 .port_set_link = mv88e6xxx_port_set_link, 5175 .port_sync_link = mv88e6xxx_port_sync_link, 5176 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5177 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5178 .port_tag_remap = mv88e6095_port_tag_remap, 5179 .port_set_policy = mv88e6352_port_set_policy, 5180 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5181 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5182 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5183 .port_set_ether_type = mv88e6351_port_set_ether_type, 5184 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5185 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5186 .port_pause_limit = mv88e6097_port_pause_limit, 5187 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5188 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5189 .port_get_cmode = mv88e6352_port_get_cmode, 5190 .port_setup_message_port = mv88e6xxx_setup_message_port, 5191 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5192 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5193 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5194 .stats_get_strings = mv88e6320_stats_get_strings, 5195 .stats_get_stat = mv88e6320_stats_get_stat, 5196 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5197 .set_egress_port = mv88e6095_g1_set_egress_port, 5198 .watchdog_ops = &mv88e6390_watchdog_ops, 5199 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5200 .pot_clear = mv88e6xxx_g2_pot_clear, 5201 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5202 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5203 .reset = mv88e6352_g1_reset, 5204 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5205 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5206 .stu_getnext = mv88e6352_g1_stu_getnext, 5207 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5208 .gpio_ops = &mv88e6352_gpio_ops, 5209 .avb_ops = &mv88e6352_avb_ops, 5210 .ptp_ops = &mv88e6352_ptp_ops, 5211 .phylink_get_caps = mv88e632x_phylink_get_caps, 5212 }; 5213 5214 static const struct mv88e6xxx_ops mv88e6321_ops = { 5215 /* MV88E6XXX_FAMILY_6320 */ 5216 .setup_errata = mv88e6320_setup_errata, 5217 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5218 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5219 .irl_init_all = mv88e6352_g2_irl_init_all, 5220 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5221 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5223 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5224 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5225 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5226 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5227 .port_set_link = mv88e6xxx_port_set_link, 5228 .port_sync_link = mv88e6xxx_port_sync_link, 5229 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5230 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5231 .port_tag_remap = mv88e6095_port_tag_remap, 5232 .port_set_policy = mv88e6352_port_set_policy, 5233 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5234 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5235 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5236 .port_set_ether_type = mv88e6351_port_set_ether_type, 5237 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5238 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5239 .port_pause_limit = mv88e6097_port_pause_limit, 5240 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5241 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5242 .port_get_cmode = mv88e6352_port_get_cmode, 5243 .port_setup_message_port = mv88e6xxx_setup_message_port, 5244 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5245 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5246 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5247 .stats_get_strings = mv88e6320_stats_get_strings, 5248 .stats_get_stat = mv88e6320_stats_get_stat, 5249 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5250 .set_egress_port = mv88e6095_g1_set_egress_port, 5251 .watchdog_ops = &mv88e6390_watchdog_ops, 5252 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5253 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5254 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5255 .reset = mv88e6352_g1_reset, 5256 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5257 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5258 .stu_getnext = mv88e6352_g1_stu_getnext, 5259 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5260 .gpio_ops = &mv88e6352_gpio_ops, 5261 .avb_ops = &mv88e6352_avb_ops, 5262 .ptp_ops = &mv88e6352_ptp_ops, 5263 .phylink_get_caps = mv88e632x_phylink_get_caps, 5264 }; 5265 5266 static const struct mv88e6xxx_ops mv88e6341_ops = { 5267 /* MV88E6XXX_FAMILY_6341 */ 5268 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5269 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5270 .irl_init_all = mv88e6352_g2_irl_init_all, 5271 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5272 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5273 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5274 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5275 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5276 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5277 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5278 .port_set_link = mv88e6xxx_port_set_link, 5279 .port_sync_link = mv88e6xxx_port_sync_link, 5280 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5281 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5282 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5283 .port_tag_remap = mv88e6095_port_tag_remap, 5284 .port_set_policy = mv88e6352_port_set_policy, 5285 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5286 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5287 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5288 .port_set_ether_type = mv88e6351_port_set_ether_type, 5289 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5290 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5291 .port_pause_limit = mv88e6097_port_pause_limit, 5292 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5293 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5294 .port_get_cmode = mv88e6352_port_get_cmode, 5295 .port_set_cmode = mv88e6341_port_set_cmode, 5296 .port_setup_message_port = mv88e6xxx_setup_message_port, 5297 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5298 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5299 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5300 .stats_get_strings = mv88e6320_stats_get_strings, 5301 .stats_get_stat = mv88e6390_stats_get_stat, 5302 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5303 .set_egress_port = mv88e6390_g1_set_egress_port, 5304 .watchdog_ops = &mv88e6390_watchdog_ops, 5305 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5306 .pot_clear = mv88e6xxx_g2_pot_clear, 5307 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5308 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5309 .reset = mv88e6352_g1_reset, 5310 .rmu_disable = mv88e6390_g1_rmu_disable, 5311 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5312 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5313 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5314 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5315 .stu_getnext = mv88e6352_g1_stu_getnext, 5316 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5317 .serdes_get_lane = mv88e6341_serdes_get_lane, 5318 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5319 .gpio_ops = &mv88e6352_gpio_ops, 5320 .avb_ops = &mv88e6390_avb_ops, 5321 .ptp_ops = &mv88e6352_ptp_ops, 5322 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5323 .serdes_get_strings = mv88e6390_serdes_get_strings, 5324 .serdes_get_stats = mv88e6390_serdes_get_stats, 5325 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5326 .serdes_get_regs = mv88e6390_serdes_get_regs, 5327 .phylink_get_caps = mv88e6341_phylink_get_caps, 5328 .pcs_ops = &mv88e6390_pcs_ops, 5329 }; 5330 5331 static const struct mv88e6xxx_ops mv88e6350_ops = { 5332 /* MV88E6XXX_FAMILY_6351 */ 5333 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5334 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5335 .irl_init_all = mv88e6352_g2_irl_init_all, 5336 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5337 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5338 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5339 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5340 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5341 .port_set_link = mv88e6xxx_port_set_link, 5342 .port_sync_link = mv88e6xxx_port_sync_link, 5343 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5344 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5345 .port_tag_remap = mv88e6095_port_tag_remap, 5346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5347 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5348 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5349 .port_set_ether_type = mv88e6351_port_set_ether_type, 5350 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5351 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5352 .port_pause_limit = mv88e6097_port_pause_limit, 5353 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5354 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5355 .port_get_cmode = mv88e6352_port_get_cmode, 5356 .port_setup_message_port = mv88e6xxx_setup_message_port, 5357 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5358 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5359 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5360 .stats_get_strings = mv88e6095_stats_get_strings, 5361 .stats_get_stat = mv88e6095_stats_get_stat, 5362 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5363 .set_egress_port = mv88e6095_g1_set_egress_port, 5364 .watchdog_ops = &mv88e6097_watchdog_ops, 5365 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5366 .pot_clear = mv88e6xxx_g2_pot_clear, 5367 .reset = mv88e6352_g1_reset, 5368 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5369 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5370 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5371 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5372 .stu_getnext = mv88e6352_g1_stu_getnext, 5373 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5374 .phylink_get_caps = mv88e6351_phylink_get_caps, 5375 }; 5376 5377 static const struct mv88e6xxx_ops mv88e6351_ops = { 5378 /* MV88E6XXX_FAMILY_6351 */ 5379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5380 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5381 .irl_init_all = mv88e6352_g2_irl_init_all, 5382 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5383 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5384 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5385 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5386 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5387 .port_set_link = mv88e6xxx_port_set_link, 5388 .port_sync_link = mv88e6xxx_port_sync_link, 5389 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5390 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5391 .port_tag_remap = mv88e6095_port_tag_remap, 5392 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5393 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5394 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5395 .port_set_ether_type = mv88e6351_port_set_ether_type, 5396 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5398 .port_pause_limit = mv88e6097_port_pause_limit, 5399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5401 .port_get_cmode = mv88e6352_port_get_cmode, 5402 .port_setup_message_port = mv88e6xxx_setup_message_port, 5403 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5405 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5406 .stats_get_strings = mv88e6095_stats_get_strings, 5407 .stats_get_stat = mv88e6095_stats_get_stat, 5408 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5409 .set_egress_port = mv88e6095_g1_set_egress_port, 5410 .watchdog_ops = &mv88e6097_watchdog_ops, 5411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5412 .pot_clear = mv88e6xxx_g2_pot_clear, 5413 .reset = mv88e6352_g1_reset, 5414 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5415 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5416 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5417 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5418 .stu_getnext = mv88e6352_g1_stu_getnext, 5419 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5420 .avb_ops = &mv88e6352_avb_ops, 5421 .ptp_ops = &mv88e6352_ptp_ops, 5422 .phylink_get_caps = mv88e6351_phylink_get_caps, 5423 }; 5424 5425 static const struct mv88e6xxx_ops mv88e6352_ops = { 5426 /* MV88E6XXX_FAMILY_6352 */ 5427 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5428 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5429 .irl_init_all = mv88e6352_g2_irl_init_all, 5430 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5431 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5433 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5434 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5435 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5436 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5437 .port_set_link = mv88e6xxx_port_set_link, 5438 .port_sync_link = mv88e6xxx_port_sync_link, 5439 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5440 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5441 .port_tag_remap = mv88e6095_port_tag_remap, 5442 .port_set_policy = mv88e6352_port_set_policy, 5443 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5444 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5445 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5446 .port_set_ether_type = mv88e6351_port_set_ether_type, 5447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5449 .port_pause_limit = mv88e6097_port_pause_limit, 5450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5452 .port_get_cmode = mv88e6352_port_get_cmode, 5453 .port_setup_leds = mv88e6xxx_port_setup_leds, 5454 .port_setup_message_port = mv88e6xxx_setup_message_port, 5455 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5456 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5457 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5458 .stats_get_strings = mv88e6095_stats_get_strings, 5459 .stats_get_stat = mv88e6095_stats_get_stat, 5460 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5461 .set_egress_port = mv88e6095_g1_set_egress_port, 5462 .watchdog_ops = &mv88e6097_watchdog_ops, 5463 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5464 .pot_clear = mv88e6xxx_g2_pot_clear, 5465 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5466 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5467 .reset = mv88e6352_g1_reset, 5468 .rmu_disable = mv88e6352_g1_rmu_disable, 5469 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5470 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5471 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5472 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5473 .stu_getnext = mv88e6352_g1_stu_getnext, 5474 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5475 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5476 .gpio_ops = &mv88e6352_gpio_ops, 5477 .avb_ops = &mv88e6352_avb_ops, 5478 .ptp_ops = &mv88e6352_ptp_ops, 5479 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5480 .serdes_get_strings = mv88e6352_serdes_get_strings, 5481 .serdes_get_stats = mv88e6352_serdes_get_stats, 5482 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5483 .serdes_get_regs = mv88e6352_serdes_get_regs, 5484 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5485 .phylink_get_caps = mv88e6352_phylink_get_caps, 5486 .pcs_ops = &mv88e6352_pcs_ops, 5487 }; 5488 5489 static const struct mv88e6xxx_ops mv88e6390_ops = { 5490 /* MV88E6XXX_FAMILY_6390 */ 5491 .setup_errata = mv88e6390_setup_errata, 5492 .irl_init_all = mv88e6390_g2_irl_init_all, 5493 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5494 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5495 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5496 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5497 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5498 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5499 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5500 .port_set_link = mv88e6xxx_port_set_link, 5501 .port_sync_link = mv88e6xxx_port_sync_link, 5502 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5503 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5504 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5505 .port_tag_remap = mv88e6390_port_tag_remap, 5506 .port_set_policy = mv88e6352_port_set_policy, 5507 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5508 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5509 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5510 .port_set_ether_type = mv88e6351_port_set_ether_type, 5511 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5512 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5513 .port_pause_limit = mv88e6390_port_pause_limit, 5514 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5515 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5516 .port_get_cmode = mv88e6352_port_get_cmode, 5517 .port_set_cmode = mv88e6390_port_set_cmode, 5518 .port_setup_message_port = mv88e6xxx_setup_message_port, 5519 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5520 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5521 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5522 .stats_get_strings = mv88e6320_stats_get_strings, 5523 .stats_get_stat = mv88e6390_stats_get_stat, 5524 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5525 .set_egress_port = mv88e6390_g1_set_egress_port, 5526 .watchdog_ops = &mv88e6390_watchdog_ops, 5527 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5528 .pot_clear = mv88e6xxx_g2_pot_clear, 5529 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5530 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5531 .reset = mv88e6352_g1_reset, 5532 .rmu_disable = mv88e6390_g1_rmu_disable, 5533 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5534 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5535 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5536 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5537 .stu_getnext = mv88e6390_g1_stu_getnext, 5538 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5539 .serdes_get_lane = mv88e6390_serdes_get_lane, 5540 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5541 .gpio_ops = &mv88e6352_gpio_ops, 5542 .avb_ops = &mv88e6390_avb_ops, 5543 .ptp_ops = &mv88e6390_ptp_ops, 5544 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5545 .serdes_get_strings = mv88e6390_serdes_get_strings, 5546 .serdes_get_stats = mv88e6390_serdes_get_stats, 5547 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5548 .serdes_get_regs = mv88e6390_serdes_get_regs, 5549 .phylink_get_caps = mv88e6390_phylink_get_caps, 5550 .pcs_ops = &mv88e6390_pcs_ops, 5551 }; 5552 5553 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5554 /* MV88E6XXX_FAMILY_6390 */ 5555 .setup_errata = mv88e6390_setup_errata, 5556 .irl_init_all = mv88e6390_g2_irl_init_all, 5557 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5558 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5560 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5561 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5562 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5563 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5564 .port_set_link = mv88e6xxx_port_set_link, 5565 .port_sync_link = mv88e6xxx_port_sync_link, 5566 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5567 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5568 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5569 .port_tag_remap = mv88e6390_port_tag_remap, 5570 .port_set_policy = mv88e6352_port_set_policy, 5571 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5572 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5573 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5574 .port_set_ether_type = mv88e6351_port_set_ether_type, 5575 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5576 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5577 .port_pause_limit = mv88e6390_port_pause_limit, 5578 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5579 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5580 .port_get_cmode = mv88e6352_port_get_cmode, 5581 .port_set_cmode = mv88e6390x_port_set_cmode, 5582 .port_setup_message_port = mv88e6xxx_setup_message_port, 5583 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5584 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5585 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5586 .stats_get_strings = mv88e6320_stats_get_strings, 5587 .stats_get_stat = mv88e6390_stats_get_stat, 5588 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5589 .set_egress_port = mv88e6390_g1_set_egress_port, 5590 .watchdog_ops = &mv88e6390_watchdog_ops, 5591 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5592 .pot_clear = mv88e6xxx_g2_pot_clear, 5593 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5594 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5595 .reset = mv88e6352_g1_reset, 5596 .rmu_disable = mv88e6390_g1_rmu_disable, 5597 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5598 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5599 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5600 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5601 .stu_getnext = mv88e6390_g1_stu_getnext, 5602 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5603 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5604 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5605 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5606 .serdes_get_strings = mv88e6390_serdes_get_strings, 5607 .serdes_get_stats = mv88e6390_serdes_get_stats, 5608 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5609 .serdes_get_regs = mv88e6390_serdes_get_regs, 5610 .gpio_ops = &mv88e6352_gpio_ops, 5611 .avb_ops = &mv88e6390_avb_ops, 5612 .ptp_ops = &mv88e6390_ptp_ops, 5613 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5614 .pcs_ops = &mv88e6390_pcs_ops, 5615 }; 5616 5617 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5618 /* MV88E6XXX_FAMILY_6393 */ 5619 .irl_init_all = mv88e6390_g2_irl_init_all, 5620 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5621 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5623 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5624 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5625 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5626 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5627 .port_set_link = mv88e6xxx_port_set_link, 5628 .port_sync_link = mv88e6xxx_port_sync_link, 5629 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5630 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5631 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5632 .port_tag_remap = mv88e6390_port_tag_remap, 5633 .port_set_policy = mv88e6393x_port_set_policy, 5634 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5635 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5636 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5637 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5638 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5639 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5640 .port_pause_limit = mv88e6390_port_pause_limit, 5641 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5642 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5643 .port_get_cmode = mv88e6352_port_get_cmode, 5644 .port_set_cmode = mv88e6393x_port_set_cmode, 5645 .port_setup_message_port = mv88e6xxx_setup_message_port, 5646 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5647 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5648 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5649 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5650 .stats_get_strings = mv88e6320_stats_get_strings, 5651 .stats_get_stat = mv88e6390_stats_get_stat, 5652 /* .set_cpu_port is missing because this family does not support a global 5653 * CPU port, only per port CPU port which is set via 5654 * .port_set_upstream_port method. 5655 */ 5656 .set_egress_port = mv88e6393x_set_egress_port, 5657 .watchdog_ops = &mv88e6393x_watchdog_ops, 5658 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5659 .pot_clear = mv88e6xxx_g2_pot_clear, 5660 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5661 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5662 .reset = mv88e6352_g1_reset, 5663 .rmu_disable = mv88e6390_g1_rmu_disable, 5664 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5665 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5666 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5667 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5668 .stu_getnext = mv88e6390_g1_stu_getnext, 5669 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5670 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5671 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5672 /* TODO: serdes stats */ 5673 .gpio_ops = &mv88e6352_gpio_ops, 5674 .avb_ops = &mv88e6390_avb_ops, 5675 .ptp_ops = &mv88e6352_ptp_ops, 5676 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5677 .pcs_ops = &mv88e6393x_pcs_ops, 5678 }; 5679 5680 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5681 [MV88E6020] = { 5682 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5683 .family = MV88E6XXX_FAMILY_6250, 5684 .name = "Marvell 88E6020", 5685 .num_databases = 64, 5686 /* Ports 2-4 are not routed to pins 5687 * => usable ports 0, 1, 5, 6 5688 */ 5689 .num_ports = 7, 5690 .num_internal_phys = 2, 5691 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5692 .max_vid = 4095, 5693 .port_base_addr = 0x8, 5694 .phy_base_addr = 0x0, 5695 .global1_addr = 0xf, 5696 .global2_addr = 0x7, 5697 .age_time_coeff = 15000, 5698 .g1_irqs = 9, 5699 .g2_irqs = 5, 5700 .stats_type = STATS_TYPE_BANK0, 5701 .atu_move_port_mask = 0xf, 5702 .dual_chip = true, 5703 .ops = &mv88e6250_ops, 5704 }, 5705 5706 [MV88E6071] = { 5707 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5708 .family = MV88E6XXX_FAMILY_6250, 5709 .name = "Marvell 88E6071", 5710 .num_databases = 64, 5711 .num_ports = 7, 5712 .num_internal_phys = 5, 5713 .max_vid = 4095, 5714 .port_base_addr = 0x08, 5715 .phy_base_addr = 0x00, 5716 .global1_addr = 0x0f, 5717 .global2_addr = 0x07, 5718 .age_time_coeff = 15000, 5719 .g1_irqs = 9, 5720 .g2_irqs = 5, 5721 .stats_type = STATS_TYPE_BANK0, 5722 .atu_move_port_mask = 0xf, 5723 .dual_chip = true, 5724 .ops = &mv88e6250_ops, 5725 }, 5726 5727 [MV88E6085] = { 5728 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5729 .family = MV88E6XXX_FAMILY_6097, 5730 .name = "Marvell 88E6085", 5731 .num_databases = 4096, 5732 .num_macs = 8192, 5733 .num_ports = 10, 5734 .num_internal_phys = 5, 5735 .max_vid = 4095, 5736 .max_sid = 63, 5737 .port_base_addr = 0x10, 5738 .phy_base_addr = 0x0, 5739 .global1_addr = 0x1b, 5740 .global2_addr = 0x1c, 5741 .age_time_coeff = 15000, 5742 .g1_irqs = 8, 5743 .g2_irqs = 10, 5744 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5745 .atu_move_port_mask = 0xf, 5746 .pvt = true, 5747 .multi_chip = true, 5748 .ops = &mv88e6085_ops, 5749 }, 5750 5751 [MV88E6095] = { 5752 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5753 .family = MV88E6XXX_FAMILY_6095, 5754 .name = "Marvell 88E6095/88E6095F", 5755 .num_databases = 256, 5756 .num_macs = 8192, 5757 .num_ports = 11, 5758 .num_internal_phys = 0, 5759 .max_vid = 4095, 5760 .port_base_addr = 0x10, 5761 .phy_base_addr = 0x0, 5762 .global1_addr = 0x1b, 5763 .global2_addr = 0x1c, 5764 .age_time_coeff = 15000, 5765 .g1_irqs = 8, 5766 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5767 .atu_move_port_mask = 0xf, 5768 .multi_chip = true, 5769 .ops = &mv88e6095_ops, 5770 }, 5771 5772 [MV88E6097] = { 5773 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5774 .family = MV88E6XXX_FAMILY_6097, 5775 .name = "Marvell 88E6097/88E6097F", 5776 .num_databases = 4096, 5777 .num_macs = 8192, 5778 .num_ports = 11, 5779 .num_internal_phys = 8, 5780 .max_vid = 4095, 5781 .max_sid = 63, 5782 .port_base_addr = 0x10, 5783 .phy_base_addr = 0x0, 5784 .global1_addr = 0x1b, 5785 .global2_addr = 0x1c, 5786 .age_time_coeff = 15000, 5787 .g1_irqs = 8, 5788 .g2_irqs = 10, 5789 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5790 .atu_move_port_mask = 0xf, 5791 .pvt = true, 5792 .multi_chip = true, 5793 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5794 .ops = &mv88e6097_ops, 5795 }, 5796 5797 [MV88E6123] = { 5798 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5799 .family = MV88E6XXX_FAMILY_6165, 5800 .name = "Marvell 88E6123", 5801 .num_databases = 4096, 5802 .num_macs = 1024, 5803 .num_ports = 3, 5804 .num_internal_phys = 5, 5805 .max_vid = 4095, 5806 .max_sid = 63, 5807 .port_base_addr = 0x10, 5808 .phy_base_addr = 0x0, 5809 .global1_addr = 0x1b, 5810 .global2_addr = 0x1c, 5811 .age_time_coeff = 15000, 5812 .g1_irqs = 9, 5813 .g2_irqs = 10, 5814 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5815 .atu_move_port_mask = 0xf, 5816 .pvt = true, 5817 .multi_chip = true, 5818 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5819 .ops = &mv88e6123_ops, 5820 }, 5821 5822 [MV88E6131] = { 5823 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5824 .family = MV88E6XXX_FAMILY_6185, 5825 .name = "Marvell 88E6131", 5826 .num_databases = 256, 5827 .num_macs = 8192, 5828 .num_ports = 8, 5829 .num_internal_phys = 0, 5830 .max_vid = 4095, 5831 .port_base_addr = 0x10, 5832 .phy_base_addr = 0x0, 5833 .global1_addr = 0x1b, 5834 .global2_addr = 0x1c, 5835 .age_time_coeff = 15000, 5836 .g1_irqs = 9, 5837 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5838 .atu_move_port_mask = 0xf, 5839 .multi_chip = true, 5840 .ops = &mv88e6131_ops, 5841 }, 5842 5843 [MV88E6141] = { 5844 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5845 .family = MV88E6XXX_FAMILY_6341, 5846 .name = "Marvell 88E6141", 5847 .num_databases = 256, 5848 .num_macs = 2048, 5849 .num_ports = 6, 5850 .num_internal_phys = 5, 5851 .num_gpio = 11, 5852 .max_vid = 4095, 5853 .max_sid = 63, 5854 .port_base_addr = 0x10, 5855 .phy_base_addr = 0x10, 5856 .global1_addr = 0x1b, 5857 .global2_addr = 0x1c, 5858 .age_time_coeff = 3750, 5859 .atu_move_port_mask = 0xf, 5860 .g1_irqs = 9, 5861 .g2_irqs = 10, 5862 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5863 .pvt = true, 5864 .multi_chip = true, 5865 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5866 .ops = &mv88e6141_ops, 5867 }, 5868 5869 [MV88E6161] = { 5870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5871 .family = MV88E6XXX_FAMILY_6165, 5872 .name = "Marvell 88E6161", 5873 .num_databases = 4096, 5874 .num_macs = 1024, 5875 .num_ports = 6, 5876 .num_internal_phys = 5, 5877 .max_vid = 4095, 5878 .max_sid = 63, 5879 .port_base_addr = 0x10, 5880 .phy_base_addr = 0x0, 5881 .global1_addr = 0x1b, 5882 .global2_addr = 0x1c, 5883 .age_time_coeff = 15000, 5884 .g1_irqs = 9, 5885 .g2_irqs = 10, 5886 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5887 .atu_move_port_mask = 0xf, 5888 .pvt = true, 5889 .multi_chip = true, 5890 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5891 .ptp_support = true, 5892 .ops = &mv88e6161_ops, 5893 }, 5894 5895 [MV88E6165] = { 5896 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5897 .family = MV88E6XXX_FAMILY_6165, 5898 .name = "Marvell 88E6165", 5899 .num_databases = 4096, 5900 .num_macs = 8192, 5901 .num_ports = 6, 5902 .num_internal_phys = 0, 5903 .max_vid = 4095, 5904 .max_sid = 63, 5905 .port_base_addr = 0x10, 5906 .phy_base_addr = 0x0, 5907 .global1_addr = 0x1b, 5908 .global2_addr = 0x1c, 5909 .age_time_coeff = 15000, 5910 .g1_irqs = 9, 5911 .g2_irqs = 10, 5912 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5913 .atu_move_port_mask = 0xf, 5914 .pvt = true, 5915 .multi_chip = true, 5916 .ptp_support = true, 5917 .ops = &mv88e6165_ops, 5918 }, 5919 5920 [MV88E6171] = { 5921 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5922 .family = MV88E6XXX_FAMILY_6351, 5923 .name = "Marvell 88E6171", 5924 .num_databases = 4096, 5925 .num_macs = 8192, 5926 .num_ports = 7, 5927 .num_internal_phys = 5, 5928 .max_vid = 4095, 5929 .max_sid = 63, 5930 .port_base_addr = 0x10, 5931 .phy_base_addr = 0x0, 5932 .global1_addr = 0x1b, 5933 .global2_addr = 0x1c, 5934 .age_time_coeff = 15000, 5935 .g1_irqs = 9, 5936 .g2_irqs = 10, 5937 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5938 .atu_move_port_mask = 0xf, 5939 .pvt = true, 5940 .multi_chip = true, 5941 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5942 .ops = &mv88e6171_ops, 5943 }, 5944 5945 [MV88E6172] = { 5946 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5947 .family = MV88E6XXX_FAMILY_6352, 5948 .name = "Marvell 88E6172", 5949 .num_databases = 4096, 5950 .num_macs = 8192, 5951 .num_ports = 7, 5952 .num_internal_phys = 5, 5953 .num_gpio = 15, 5954 .max_vid = 4095, 5955 .max_sid = 63, 5956 .port_base_addr = 0x10, 5957 .phy_base_addr = 0x0, 5958 .global1_addr = 0x1b, 5959 .global2_addr = 0x1c, 5960 .age_time_coeff = 15000, 5961 .g1_irqs = 9, 5962 .g2_irqs = 10, 5963 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5964 .atu_move_port_mask = 0xf, 5965 .pvt = true, 5966 .multi_chip = true, 5967 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5968 .ops = &mv88e6172_ops, 5969 }, 5970 5971 [MV88E6175] = { 5972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5973 .family = MV88E6XXX_FAMILY_6351, 5974 .name = "Marvell 88E6175", 5975 .num_databases = 4096, 5976 .num_macs = 8192, 5977 .num_ports = 7, 5978 .num_internal_phys = 5, 5979 .max_vid = 4095, 5980 .max_sid = 63, 5981 .port_base_addr = 0x10, 5982 .phy_base_addr = 0x0, 5983 .global1_addr = 0x1b, 5984 .global2_addr = 0x1c, 5985 .age_time_coeff = 15000, 5986 .g1_irqs = 9, 5987 .g2_irqs = 10, 5988 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5989 .atu_move_port_mask = 0xf, 5990 .pvt = true, 5991 .multi_chip = true, 5992 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5993 .ops = &mv88e6175_ops, 5994 }, 5995 5996 [MV88E6176] = { 5997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5998 .family = MV88E6XXX_FAMILY_6352, 5999 .name = "Marvell 88E6176", 6000 .num_databases = 4096, 6001 .num_macs = 8192, 6002 .num_ports = 7, 6003 .num_internal_phys = 5, 6004 .num_gpio = 15, 6005 .max_vid = 4095, 6006 .max_sid = 63, 6007 .port_base_addr = 0x10, 6008 .phy_base_addr = 0x0, 6009 .global1_addr = 0x1b, 6010 .global2_addr = 0x1c, 6011 .age_time_coeff = 15000, 6012 .g1_irqs = 9, 6013 .g2_irqs = 10, 6014 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6015 .atu_move_port_mask = 0xf, 6016 .pvt = true, 6017 .multi_chip = true, 6018 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6019 .ops = &mv88e6176_ops, 6020 }, 6021 6022 [MV88E6185] = { 6023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 6024 .family = MV88E6XXX_FAMILY_6185, 6025 .name = "Marvell 88E6185", 6026 .num_databases = 256, 6027 .num_macs = 8192, 6028 .num_ports = 10, 6029 .num_internal_phys = 0, 6030 .max_vid = 4095, 6031 .port_base_addr = 0x10, 6032 .phy_base_addr = 0x0, 6033 .global1_addr = 0x1b, 6034 .global2_addr = 0x1c, 6035 .age_time_coeff = 15000, 6036 .g1_irqs = 8, 6037 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6038 .atu_move_port_mask = 0xf, 6039 .multi_chip = true, 6040 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6041 .ops = &mv88e6185_ops, 6042 }, 6043 6044 [MV88E6190] = { 6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6046 .family = MV88E6XXX_FAMILY_6390, 6047 .name = "Marvell 88E6190", 6048 .num_databases = 4096, 6049 .num_macs = 16384, 6050 .num_ports = 11, /* 10 + Z80 */ 6051 .num_internal_phys = 9, 6052 .num_gpio = 16, 6053 .max_vid = 8191, 6054 .max_sid = 63, 6055 .port_base_addr = 0x0, 6056 .phy_base_addr = 0x0, 6057 .global1_addr = 0x1b, 6058 .global2_addr = 0x1c, 6059 .age_time_coeff = 3750, 6060 .g1_irqs = 9, 6061 .g2_irqs = 14, 6062 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6063 .pvt = true, 6064 .multi_chip = true, 6065 .atu_move_port_mask = 0x1f, 6066 .ops = &mv88e6190_ops, 6067 }, 6068 6069 [MV88E6190X] = { 6070 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6071 .family = MV88E6XXX_FAMILY_6390, 6072 .name = "Marvell 88E6190X", 6073 .num_databases = 4096, 6074 .num_macs = 16384, 6075 .num_ports = 11, /* 10 + Z80 */ 6076 .num_internal_phys = 9, 6077 .num_gpio = 16, 6078 .max_vid = 8191, 6079 .max_sid = 63, 6080 .port_base_addr = 0x0, 6081 .phy_base_addr = 0x0, 6082 .global1_addr = 0x1b, 6083 .global2_addr = 0x1c, 6084 .age_time_coeff = 3750, 6085 .g1_irqs = 9, 6086 .g2_irqs = 14, 6087 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6088 .atu_move_port_mask = 0x1f, 6089 .pvt = true, 6090 .multi_chip = true, 6091 .ops = &mv88e6190x_ops, 6092 }, 6093 6094 [MV88E6191] = { 6095 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6096 .family = MV88E6XXX_FAMILY_6390, 6097 .name = "Marvell 88E6191", 6098 .num_databases = 4096, 6099 .num_macs = 16384, 6100 .num_ports = 11, /* 10 + Z80 */ 6101 .num_internal_phys = 9, 6102 .max_vid = 8191, 6103 .max_sid = 63, 6104 .port_base_addr = 0x0, 6105 .phy_base_addr = 0x0, 6106 .global1_addr = 0x1b, 6107 .global2_addr = 0x1c, 6108 .age_time_coeff = 3750, 6109 .g1_irqs = 9, 6110 .g2_irqs = 14, 6111 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6112 .atu_move_port_mask = 0x1f, 6113 .pvt = true, 6114 .multi_chip = true, 6115 .ptp_support = true, 6116 .ops = &mv88e6191_ops, 6117 }, 6118 6119 [MV88E6191X] = { 6120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6121 .family = MV88E6XXX_FAMILY_6393, 6122 .name = "Marvell 88E6191X", 6123 .num_databases = 4096, 6124 .num_ports = 11, /* 10 + Z80 */ 6125 .num_internal_phys = 8, 6126 .internal_phys_offset = 1, 6127 .max_vid = 8191, 6128 .max_sid = 63, 6129 .port_base_addr = 0x0, 6130 .phy_base_addr = 0x0, 6131 .global1_addr = 0x1b, 6132 .global2_addr = 0x1c, 6133 .age_time_coeff = 3750, 6134 .g1_irqs = 10, 6135 .g2_irqs = 14, 6136 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6137 .atu_move_port_mask = 0x1f, 6138 .pvt = true, 6139 .multi_chip = true, 6140 .ptp_support = true, 6141 .ops = &mv88e6393x_ops, 6142 }, 6143 6144 [MV88E6193X] = { 6145 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6146 .family = MV88E6XXX_FAMILY_6393, 6147 .name = "Marvell 88E6193X", 6148 .num_databases = 4096, 6149 .num_ports = 11, /* 10 + Z80 */ 6150 .num_internal_phys = 8, 6151 .internal_phys_offset = 1, 6152 .max_vid = 8191, 6153 .max_sid = 63, 6154 .port_base_addr = 0x0, 6155 .phy_base_addr = 0x0, 6156 .global1_addr = 0x1b, 6157 .global2_addr = 0x1c, 6158 .age_time_coeff = 3750, 6159 .g1_irqs = 10, 6160 .g2_irqs = 14, 6161 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6162 .atu_move_port_mask = 0x1f, 6163 .pvt = true, 6164 .multi_chip = true, 6165 .ptp_support = true, 6166 .ops = &mv88e6393x_ops, 6167 }, 6168 6169 [MV88E6220] = { 6170 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6171 .family = MV88E6XXX_FAMILY_6250, 6172 .name = "Marvell 88E6220", 6173 .num_databases = 64, 6174 6175 /* Ports 2-4 are not routed to pins 6176 * => usable ports 0, 1, 5, 6 6177 */ 6178 .num_ports = 7, 6179 .num_internal_phys = 2, 6180 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6181 .max_vid = 4095, 6182 .port_base_addr = 0x08, 6183 .phy_base_addr = 0x00, 6184 .global1_addr = 0x0f, 6185 .global2_addr = 0x07, 6186 .age_time_coeff = 15000, 6187 .g1_irqs = 9, 6188 .g2_irqs = 10, 6189 .stats_type = STATS_TYPE_BANK0, 6190 .atu_move_port_mask = 0xf, 6191 .dual_chip = true, 6192 .ptp_support = true, 6193 .ops = &mv88e6250_ops, 6194 }, 6195 6196 [MV88E6240] = { 6197 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6198 .family = MV88E6XXX_FAMILY_6352, 6199 .name = "Marvell 88E6240", 6200 .num_databases = 4096, 6201 .num_macs = 8192, 6202 .num_ports = 7, 6203 .num_internal_phys = 5, 6204 .num_gpio = 15, 6205 .max_vid = 4095, 6206 .max_sid = 63, 6207 .port_base_addr = 0x10, 6208 .phy_base_addr = 0x0, 6209 .global1_addr = 0x1b, 6210 .global2_addr = 0x1c, 6211 .age_time_coeff = 15000, 6212 .g1_irqs = 9, 6213 .g2_irqs = 10, 6214 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6215 .atu_move_port_mask = 0xf, 6216 .pvt = true, 6217 .multi_chip = true, 6218 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6219 .ptp_support = true, 6220 .ops = &mv88e6240_ops, 6221 }, 6222 6223 [MV88E6250] = { 6224 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6225 .family = MV88E6XXX_FAMILY_6250, 6226 .name = "Marvell 88E6250", 6227 .num_databases = 64, 6228 .num_ports = 7, 6229 .num_internal_phys = 5, 6230 .max_vid = 4095, 6231 .port_base_addr = 0x08, 6232 .phy_base_addr = 0x00, 6233 .global1_addr = 0x0f, 6234 .global2_addr = 0x07, 6235 .age_time_coeff = 15000, 6236 .g1_irqs = 9, 6237 .g2_irqs = 10, 6238 .stats_type = STATS_TYPE_BANK0, 6239 .atu_move_port_mask = 0xf, 6240 .dual_chip = true, 6241 .ptp_support = true, 6242 .ops = &mv88e6250_ops, 6243 }, 6244 6245 [MV88E6290] = { 6246 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6247 .family = MV88E6XXX_FAMILY_6390, 6248 .name = "Marvell 88E6290", 6249 .num_databases = 4096, 6250 .num_ports = 11, /* 10 + Z80 */ 6251 .num_internal_phys = 9, 6252 .num_gpio = 16, 6253 .max_vid = 8191, 6254 .max_sid = 63, 6255 .port_base_addr = 0x0, 6256 .phy_base_addr = 0x0, 6257 .global1_addr = 0x1b, 6258 .global2_addr = 0x1c, 6259 .age_time_coeff = 3750, 6260 .g1_irqs = 9, 6261 .g2_irqs = 14, 6262 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6263 .atu_move_port_mask = 0x1f, 6264 .pvt = true, 6265 .multi_chip = true, 6266 .ptp_support = true, 6267 .ops = &mv88e6290_ops, 6268 }, 6269 6270 [MV88E6320] = { 6271 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6272 .family = MV88E6XXX_FAMILY_6320, 6273 .name = "Marvell 88E6320", 6274 .num_databases = 4096, 6275 .num_macs = 8192, 6276 .num_ports = 7, 6277 .num_internal_phys = 2, 6278 .internal_phys_offset = 3, 6279 .num_gpio = 15, 6280 .max_vid = 4095, 6281 .max_sid = 63, 6282 .port_base_addr = 0x10, 6283 .phy_base_addr = 0x0, 6284 .global1_addr = 0x1b, 6285 .global2_addr = 0x1c, 6286 .age_time_coeff = 15000, 6287 .g1_irqs = 8, 6288 .g2_irqs = 10, 6289 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6290 .atu_move_port_mask = 0xf, 6291 .pvt = true, 6292 .multi_chip = true, 6293 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6294 .ptp_support = true, 6295 .ops = &mv88e6320_ops, 6296 }, 6297 6298 [MV88E6321] = { 6299 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6300 .family = MV88E6XXX_FAMILY_6320, 6301 .name = "Marvell 88E6321", 6302 .num_databases = 4096, 6303 .num_macs = 8192, 6304 .num_ports = 7, 6305 .num_internal_phys = 2, 6306 .internal_phys_offset = 3, 6307 .num_gpio = 15, 6308 .max_vid = 4095, 6309 .max_sid = 63, 6310 .port_base_addr = 0x10, 6311 .phy_base_addr = 0x0, 6312 .global1_addr = 0x1b, 6313 .global2_addr = 0x1c, 6314 .age_time_coeff = 15000, 6315 .g1_irqs = 8, 6316 .g2_irqs = 10, 6317 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6318 .atu_move_port_mask = 0xf, 6319 .pvt = true, 6320 .multi_chip = true, 6321 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6322 .ptp_support = true, 6323 .ops = &mv88e6321_ops, 6324 }, 6325 6326 [MV88E6341] = { 6327 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6328 .family = MV88E6XXX_FAMILY_6341, 6329 .name = "Marvell 88E6341", 6330 .num_databases = 256, 6331 .num_macs = 2048, 6332 .num_internal_phys = 5, 6333 .num_ports = 6, 6334 .num_gpio = 11, 6335 .max_vid = 4095, 6336 .max_sid = 63, 6337 .port_base_addr = 0x10, 6338 .phy_base_addr = 0x10, 6339 .global1_addr = 0x1b, 6340 .global2_addr = 0x1c, 6341 .age_time_coeff = 3750, 6342 .atu_move_port_mask = 0xf, 6343 .g1_irqs = 9, 6344 .g2_irqs = 10, 6345 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6346 .pvt = true, 6347 .multi_chip = true, 6348 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6349 .ptp_support = true, 6350 .ops = &mv88e6341_ops, 6351 }, 6352 6353 [MV88E6350] = { 6354 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6355 .family = MV88E6XXX_FAMILY_6351, 6356 .name = "Marvell 88E6350", 6357 .num_databases = 4096, 6358 .num_macs = 8192, 6359 .num_ports = 7, 6360 .num_internal_phys = 5, 6361 .max_vid = 4095, 6362 .max_sid = 63, 6363 .port_base_addr = 0x10, 6364 .phy_base_addr = 0x0, 6365 .global1_addr = 0x1b, 6366 .global2_addr = 0x1c, 6367 .age_time_coeff = 15000, 6368 .g1_irqs = 9, 6369 .g2_irqs = 10, 6370 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6371 .atu_move_port_mask = 0xf, 6372 .pvt = true, 6373 .multi_chip = true, 6374 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6375 .ops = &mv88e6350_ops, 6376 }, 6377 6378 [MV88E6351] = { 6379 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6380 .family = MV88E6XXX_FAMILY_6351, 6381 .name = "Marvell 88E6351", 6382 .num_databases = 4096, 6383 .num_macs = 8192, 6384 .num_ports = 7, 6385 .num_internal_phys = 5, 6386 .max_vid = 4095, 6387 .max_sid = 63, 6388 .port_base_addr = 0x10, 6389 .phy_base_addr = 0x0, 6390 .global1_addr = 0x1b, 6391 .global2_addr = 0x1c, 6392 .age_time_coeff = 15000, 6393 .g1_irqs = 9, 6394 .g2_irqs = 10, 6395 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6396 .atu_move_port_mask = 0xf, 6397 .pvt = true, 6398 .multi_chip = true, 6399 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6400 .ops = &mv88e6351_ops, 6401 }, 6402 6403 [MV88E6352] = { 6404 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6405 .family = MV88E6XXX_FAMILY_6352, 6406 .name = "Marvell 88E6352", 6407 .num_databases = 4096, 6408 .num_macs = 8192, 6409 .num_ports = 7, 6410 .num_internal_phys = 5, 6411 .num_gpio = 15, 6412 .max_vid = 4095, 6413 .max_sid = 63, 6414 .port_base_addr = 0x10, 6415 .phy_base_addr = 0x0, 6416 .global1_addr = 0x1b, 6417 .global2_addr = 0x1c, 6418 .age_time_coeff = 15000, 6419 .g1_irqs = 9, 6420 .g2_irqs = 10, 6421 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6422 .atu_move_port_mask = 0xf, 6423 .pvt = true, 6424 .multi_chip = true, 6425 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6426 .ptp_support = true, 6427 .ops = &mv88e6352_ops, 6428 }, 6429 [MV88E6361] = { 6430 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6431 .family = MV88E6XXX_FAMILY_6393, 6432 .name = "Marvell 88E6361", 6433 .num_databases = 4096, 6434 .num_macs = 16384, 6435 .num_ports = 11, 6436 /* Ports 1, 2 and 8 are not routed */ 6437 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6438 .num_internal_phys = 5, 6439 .internal_phys_offset = 3, 6440 .max_vid = 8191, 6441 .max_sid = 63, 6442 .port_base_addr = 0x0, 6443 .phy_base_addr = 0x0, 6444 .global1_addr = 0x1b, 6445 .global2_addr = 0x1c, 6446 .age_time_coeff = 3750, 6447 .g1_irqs = 10, 6448 .g2_irqs = 14, 6449 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6450 .atu_move_port_mask = 0x1f, 6451 .pvt = true, 6452 .multi_chip = true, 6453 .ptp_support = true, 6454 .ops = &mv88e6393x_ops, 6455 }, 6456 [MV88E6390] = { 6457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6458 .family = MV88E6XXX_FAMILY_6390, 6459 .name = "Marvell 88E6390", 6460 .num_databases = 4096, 6461 .num_macs = 16384, 6462 .num_ports = 11, /* 10 + Z80 */ 6463 .num_internal_phys = 9, 6464 .num_gpio = 16, 6465 .max_vid = 8191, 6466 .max_sid = 63, 6467 .port_base_addr = 0x0, 6468 .phy_base_addr = 0x0, 6469 .global1_addr = 0x1b, 6470 .global2_addr = 0x1c, 6471 .age_time_coeff = 3750, 6472 .g1_irqs = 9, 6473 .g2_irqs = 14, 6474 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6475 .atu_move_port_mask = 0x1f, 6476 .pvt = true, 6477 .multi_chip = true, 6478 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6479 .ptp_support = true, 6480 .ops = &mv88e6390_ops, 6481 }, 6482 [MV88E6390X] = { 6483 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6484 .family = MV88E6XXX_FAMILY_6390, 6485 .name = "Marvell 88E6390X", 6486 .num_databases = 4096, 6487 .num_macs = 16384, 6488 .num_ports = 11, /* 10 + Z80 */ 6489 .num_internal_phys = 9, 6490 .num_gpio = 16, 6491 .max_vid = 8191, 6492 .max_sid = 63, 6493 .port_base_addr = 0x0, 6494 .phy_base_addr = 0x0, 6495 .global1_addr = 0x1b, 6496 .global2_addr = 0x1c, 6497 .age_time_coeff = 3750, 6498 .g1_irqs = 9, 6499 .g2_irqs = 14, 6500 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6501 .atu_move_port_mask = 0x1f, 6502 .pvt = true, 6503 .multi_chip = true, 6504 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6505 .ptp_support = true, 6506 .ops = &mv88e6390x_ops, 6507 }, 6508 6509 [MV88E6393X] = { 6510 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6511 .family = MV88E6XXX_FAMILY_6393, 6512 .name = "Marvell 88E6393X", 6513 .num_databases = 4096, 6514 .num_ports = 11, /* 10 + Z80 */ 6515 .num_internal_phys = 8, 6516 .internal_phys_offset = 1, 6517 .max_vid = 8191, 6518 .max_sid = 63, 6519 .port_base_addr = 0x0, 6520 .phy_base_addr = 0x0, 6521 .global1_addr = 0x1b, 6522 .global2_addr = 0x1c, 6523 .age_time_coeff = 3750, 6524 .g1_irqs = 10, 6525 .g2_irqs = 14, 6526 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6527 .atu_move_port_mask = 0x1f, 6528 .pvt = true, 6529 .multi_chip = true, 6530 .ptp_support = true, 6531 .ops = &mv88e6393x_ops, 6532 }, 6533 }; 6534 6535 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6536 { 6537 int i; 6538 6539 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6540 if (mv88e6xxx_table[i].prod_num == prod_num) 6541 return &mv88e6xxx_table[i]; 6542 6543 return NULL; 6544 } 6545 6546 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6547 { 6548 const struct mv88e6xxx_info *info; 6549 unsigned int prod_num, rev; 6550 u16 id; 6551 int err; 6552 6553 mv88e6xxx_reg_lock(chip); 6554 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6555 mv88e6xxx_reg_unlock(chip); 6556 if (err) 6557 return err; 6558 6559 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6560 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6561 6562 info = mv88e6xxx_lookup_info(prod_num); 6563 if (!info) 6564 return -ENODEV; 6565 6566 /* Update the compatible info with the probed one */ 6567 chip->info = info; 6568 6569 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6570 chip->info->prod_num, chip->info->name, rev); 6571 6572 return 0; 6573 } 6574 6575 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6576 struct mdio_device *mdiodev) 6577 { 6578 int err; 6579 6580 /* dual_chip takes precedence over single/multi-chip modes */ 6581 if (chip->info->dual_chip) 6582 return -EINVAL; 6583 6584 /* If the mdio addr is 16 indicating the first port address of a switch 6585 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6586 * configured in single chip addressing mode. Setup the smi access as 6587 * single chip addressing mode and attempt to detect the model of the 6588 * switch, if this fails the device is not configured in single chip 6589 * addressing mode. 6590 */ 6591 if (mdiodev->addr != 16) 6592 return -EINVAL; 6593 6594 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6595 if (err) 6596 return err; 6597 6598 return mv88e6xxx_detect(chip); 6599 } 6600 6601 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6602 { 6603 struct mv88e6xxx_chip *chip; 6604 6605 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6606 if (!chip) 6607 return NULL; 6608 6609 chip->dev = dev; 6610 6611 mutex_init(&chip->reg_lock); 6612 INIT_LIST_HEAD(&chip->mdios); 6613 idr_init(&chip->policies); 6614 INIT_LIST_HEAD(&chip->msts); 6615 6616 return chip; 6617 } 6618 6619 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6620 int port, 6621 enum dsa_tag_protocol m) 6622 { 6623 struct mv88e6xxx_chip *chip = ds->priv; 6624 6625 return chip->tag_protocol; 6626 } 6627 6628 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6629 enum dsa_tag_protocol proto) 6630 { 6631 struct mv88e6xxx_chip *chip = ds->priv; 6632 enum dsa_tag_protocol old_protocol; 6633 struct dsa_port *cpu_dp; 6634 int err; 6635 6636 switch (proto) { 6637 case DSA_TAG_PROTO_EDSA: 6638 switch (chip->info->edsa_support) { 6639 case MV88E6XXX_EDSA_UNSUPPORTED: 6640 return -EPROTONOSUPPORT; 6641 case MV88E6XXX_EDSA_UNDOCUMENTED: 6642 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6643 fallthrough; 6644 case MV88E6XXX_EDSA_SUPPORTED: 6645 break; 6646 } 6647 break; 6648 case DSA_TAG_PROTO_DSA: 6649 break; 6650 default: 6651 return -EPROTONOSUPPORT; 6652 } 6653 6654 old_protocol = chip->tag_protocol; 6655 chip->tag_protocol = proto; 6656 6657 mv88e6xxx_reg_lock(chip); 6658 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6659 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6660 if (err) { 6661 mv88e6xxx_reg_unlock(chip); 6662 goto unwind; 6663 } 6664 } 6665 mv88e6xxx_reg_unlock(chip); 6666 6667 return 0; 6668 6669 unwind: 6670 chip->tag_protocol = old_protocol; 6671 6672 mv88e6xxx_reg_lock(chip); 6673 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6674 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6675 mv88e6xxx_reg_unlock(chip); 6676 6677 return err; 6678 } 6679 6680 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6681 const struct switchdev_obj_port_mdb *mdb, 6682 struct dsa_db db) 6683 { 6684 struct mv88e6xxx_chip *chip = ds->priv; 6685 int err; 6686 6687 mv88e6xxx_reg_lock(chip); 6688 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6689 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6690 if (err) 6691 goto out; 6692 6693 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid)) 6694 err = -ENOSPC; 6695 6696 out: 6697 mv88e6xxx_reg_unlock(chip); 6698 6699 return err; 6700 } 6701 6702 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6703 const struct switchdev_obj_port_mdb *mdb, 6704 struct dsa_db db) 6705 { 6706 struct mv88e6xxx_chip *chip = ds->priv; 6707 int err; 6708 6709 mv88e6xxx_reg_lock(chip); 6710 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6711 mv88e6xxx_reg_unlock(chip); 6712 6713 return err; 6714 } 6715 6716 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6717 struct dsa_mall_mirror_tc_entry *mirror, 6718 bool ingress, 6719 struct netlink_ext_ack *extack) 6720 { 6721 enum mv88e6xxx_egress_direction direction = ingress ? 6722 MV88E6XXX_EGRESS_DIR_INGRESS : 6723 MV88E6XXX_EGRESS_DIR_EGRESS; 6724 struct mv88e6xxx_chip *chip = ds->priv; 6725 bool other_mirrors = false; 6726 int i; 6727 int err; 6728 6729 mutex_lock(&chip->reg_lock); 6730 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6731 mirror->to_local_port) { 6732 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6733 other_mirrors |= ingress ? 6734 chip->ports[i].mirror_ingress : 6735 chip->ports[i].mirror_egress; 6736 6737 /* Can't change egress port when other mirror is active */ 6738 if (other_mirrors) { 6739 err = -EBUSY; 6740 goto out; 6741 } 6742 6743 err = mv88e6xxx_set_egress_port(chip, direction, 6744 mirror->to_local_port); 6745 if (err) 6746 goto out; 6747 } 6748 6749 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6750 out: 6751 mutex_unlock(&chip->reg_lock); 6752 6753 return err; 6754 } 6755 6756 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6757 struct dsa_mall_mirror_tc_entry *mirror) 6758 { 6759 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6760 MV88E6XXX_EGRESS_DIR_INGRESS : 6761 MV88E6XXX_EGRESS_DIR_EGRESS; 6762 struct mv88e6xxx_chip *chip = ds->priv; 6763 bool other_mirrors = false; 6764 int i; 6765 6766 mutex_lock(&chip->reg_lock); 6767 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6768 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6769 6770 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6771 other_mirrors |= mirror->ingress ? 6772 chip->ports[i].mirror_ingress : 6773 chip->ports[i].mirror_egress; 6774 6775 /* Reset egress port when no other mirror is active */ 6776 if (!other_mirrors) { 6777 if (mv88e6xxx_set_egress_port(chip, direction, 6778 dsa_upstream_port(ds, port))) 6779 dev_err(ds->dev, "failed to set egress port\n"); 6780 } 6781 6782 mutex_unlock(&chip->reg_lock); 6783 } 6784 6785 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6786 struct switchdev_brport_flags flags, 6787 struct netlink_ext_ack *extack) 6788 { 6789 struct mv88e6xxx_chip *chip = ds->priv; 6790 const struct mv88e6xxx_ops *ops; 6791 6792 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6793 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6794 return -EINVAL; 6795 6796 ops = chip->info->ops; 6797 6798 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6799 return -EINVAL; 6800 6801 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6802 return -EINVAL; 6803 6804 return 0; 6805 } 6806 6807 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6808 struct switchdev_brport_flags flags, 6809 struct netlink_ext_ack *extack) 6810 { 6811 struct mv88e6xxx_chip *chip = ds->priv; 6812 int err = 0; 6813 6814 mv88e6xxx_reg_lock(chip); 6815 6816 if (flags.mask & BR_LEARNING) { 6817 bool learning = !!(flags.val & BR_LEARNING); 6818 u16 pav = learning ? (1 << port) : 0; 6819 6820 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6821 if (err) 6822 goto out; 6823 } 6824 6825 if (flags.mask & BR_FLOOD) { 6826 bool unicast = !!(flags.val & BR_FLOOD); 6827 6828 err = chip->info->ops->port_set_ucast_flood(chip, port, 6829 unicast); 6830 if (err) 6831 goto out; 6832 } 6833 6834 if (flags.mask & BR_MCAST_FLOOD) { 6835 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6836 6837 err = chip->info->ops->port_set_mcast_flood(chip, port, 6838 multicast); 6839 if (err) 6840 goto out; 6841 } 6842 6843 if (flags.mask & BR_BCAST_FLOOD) { 6844 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6845 6846 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6847 if (err) 6848 goto out; 6849 } 6850 6851 if (flags.mask & BR_PORT_MAB) { 6852 bool mab = !!(flags.val & BR_PORT_MAB); 6853 6854 mv88e6xxx_port_set_mab(chip, port, mab); 6855 } 6856 6857 if (flags.mask & BR_PORT_LOCKED) { 6858 bool locked = !!(flags.val & BR_PORT_LOCKED); 6859 6860 err = mv88e6xxx_port_set_lock(chip, port, locked); 6861 if (err) 6862 goto out; 6863 } 6864 out: 6865 mv88e6xxx_reg_unlock(chip); 6866 6867 return err; 6868 } 6869 6870 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6871 struct dsa_lag lag, 6872 struct netdev_lag_upper_info *info, 6873 struct netlink_ext_ack *extack) 6874 { 6875 struct mv88e6xxx_chip *chip = ds->priv; 6876 struct dsa_port *dp; 6877 int members = 0; 6878 6879 if (!mv88e6xxx_has_lag(chip)) { 6880 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6881 return false; 6882 } 6883 6884 if (!lag.id) 6885 return false; 6886 6887 dsa_lag_foreach_port(dp, ds->dst, &lag) 6888 /* Includes the port joining the LAG */ 6889 members++; 6890 6891 if (members > 8) { 6892 NL_SET_ERR_MSG_MOD(extack, 6893 "Cannot offload more than 8 LAG ports"); 6894 return false; 6895 } 6896 6897 /* We could potentially relax this to include active 6898 * backup in the future. 6899 */ 6900 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6901 NL_SET_ERR_MSG_MOD(extack, 6902 "Can only offload LAG using hash TX type"); 6903 return false; 6904 } 6905 6906 /* Ideally we would also validate that the hash type matches 6907 * the hardware. Alas, this is always set to unknown on team 6908 * interfaces. 6909 */ 6910 return true; 6911 } 6912 6913 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6914 { 6915 struct mv88e6xxx_chip *chip = ds->priv; 6916 struct dsa_port *dp; 6917 u16 map = 0; 6918 int id; 6919 6920 /* DSA LAG IDs are one-based, hardware is zero-based */ 6921 id = lag.id - 1; 6922 6923 /* Build the map of all ports to distribute flows destined for 6924 * this LAG. This can be either a local user port, or a DSA 6925 * port if the LAG port is on a remote chip. 6926 */ 6927 dsa_lag_foreach_port(dp, ds->dst, &lag) 6928 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6929 6930 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6931 } 6932 6933 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6934 /* Row number corresponds to the number of active members in a 6935 * LAG. Each column states which of the eight hash buckets are 6936 * mapped to the column:th port in the LAG. 6937 * 6938 * Example: In a LAG with three active ports, the second port 6939 * ([2][1]) would be selected for traffic mapped to buckets 6940 * 3,4,5 (0x38). 6941 */ 6942 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6943 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6944 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6945 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6946 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6947 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6948 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6949 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6950 }; 6951 6952 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6953 int num_tx, int nth) 6954 { 6955 u8 active = 0; 6956 int i; 6957 6958 num_tx = num_tx <= 8 ? num_tx : 8; 6959 if (nth < num_tx) 6960 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6961 6962 for (i = 0; i < 8; i++) { 6963 if (BIT(i) & active) 6964 mask[i] |= BIT(port); 6965 } 6966 } 6967 6968 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6969 { 6970 struct mv88e6xxx_chip *chip = ds->priv; 6971 unsigned int id, num_tx; 6972 struct dsa_port *dp; 6973 struct dsa_lag *lag; 6974 int i, err, nth; 6975 u16 mask[8]; 6976 u16 ivec; 6977 6978 /* Assume no port is a member of any LAG. */ 6979 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6980 6981 /* Disable all masks for ports that _are_ members of a LAG. */ 6982 dsa_switch_for_each_port(dp, ds) { 6983 if (!dp->lag) 6984 continue; 6985 6986 ivec &= ~BIT(dp->index); 6987 } 6988 6989 for (i = 0; i < 8; i++) 6990 mask[i] = ivec; 6991 6992 /* Enable the correct subset of masks for all LAG ports that 6993 * are in the Tx set. 6994 */ 6995 dsa_lags_foreach_id(id, ds->dst) { 6996 lag = dsa_lag_by_id(ds->dst, id); 6997 if (!lag) 6998 continue; 6999 7000 num_tx = 0; 7001 dsa_lag_foreach_port(dp, ds->dst, lag) { 7002 if (dp->lag_tx_enabled) 7003 num_tx++; 7004 } 7005 7006 if (!num_tx) 7007 continue; 7008 7009 nth = 0; 7010 dsa_lag_foreach_port(dp, ds->dst, lag) { 7011 if (!dp->lag_tx_enabled) 7012 continue; 7013 7014 if (dp->ds == ds) 7015 mv88e6xxx_lag_set_port_mask(mask, dp->index, 7016 num_tx, nth); 7017 7018 nth++; 7019 } 7020 } 7021 7022 for (i = 0; i < 8; i++) { 7023 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 7024 if (err) 7025 return err; 7026 } 7027 7028 return 0; 7029 } 7030 7031 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 7032 struct dsa_lag lag) 7033 { 7034 int err; 7035 7036 err = mv88e6xxx_lag_sync_masks(ds); 7037 7038 if (!err) 7039 err = mv88e6xxx_lag_sync_map(ds, lag); 7040 7041 return err; 7042 } 7043 7044 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 7045 { 7046 struct mv88e6xxx_chip *chip = ds->priv; 7047 int err; 7048 7049 mv88e6xxx_reg_lock(chip); 7050 err = mv88e6xxx_lag_sync_masks(ds); 7051 mv88e6xxx_reg_unlock(chip); 7052 return err; 7053 } 7054 7055 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7056 struct dsa_lag lag, 7057 struct netdev_lag_upper_info *info, 7058 struct netlink_ext_ack *extack) 7059 { 7060 struct mv88e6xxx_chip *chip = ds->priv; 7061 int err, id; 7062 7063 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7064 return -EOPNOTSUPP; 7065 7066 /* DSA LAG IDs are one-based */ 7067 id = lag.id - 1; 7068 7069 mv88e6xxx_reg_lock(chip); 7070 7071 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7072 if (err) 7073 goto err_unlock; 7074 7075 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7076 if (err) 7077 goto err_clear_trunk; 7078 7079 mv88e6xxx_reg_unlock(chip); 7080 return 0; 7081 7082 err_clear_trunk: 7083 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7084 err_unlock: 7085 mv88e6xxx_reg_unlock(chip); 7086 return err; 7087 } 7088 7089 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7090 struct dsa_lag lag) 7091 { 7092 struct mv88e6xxx_chip *chip = ds->priv; 7093 int err_sync, err_trunk; 7094 7095 mv88e6xxx_reg_lock(chip); 7096 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7097 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7098 mv88e6xxx_reg_unlock(chip); 7099 return err_sync ? : err_trunk; 7100 } 7101 7102 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7103 int port) 7104 { 7105 struct mv88e6xxx_chip *chip = ds->priv; 7106 int err; 7107 7108 mv88e6xxx_reg_lock(chip); 7109 err = mv88e6xxx_lag_sync_masks(ds); 7110 mv88e6xxx_reg_unlock(chip); 7111 return err; 7112 } 7113 7114 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7115 int port, struct dsa_lag lag, 7116 struct netdev_lag_upper_info *info, 7117 struct netlink_ext_ack *extack) 7118 { 7119 struct mv88e6xxx_chip *chip = ds->priv; 7120 int err; 7121 7122 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7123 return -EOPNOTSUPP; 7124 7125 mv88e6xxx_reg_lock(chip); 7126 7127 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7128 if (err) 7129 goto unlock; 7130 7131 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7132 7133 unlock: 7134 mv88e6xxx_reg_unlock(chip); 7135 return err; 7136 } 7137 7138 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7139 int port, struct dsa_lag lag) 7140 { 7141 struct mv88e6xxx_chip *chip = ds->priv; 7142 int err_sync, err_pvt; 7143 7144 mv88e6xxx_reg_lock(chip); 7145 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7146 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7147 mv88e6xxx_reg_unlock(chip); 7148 return err_sync ? : err_pvt; 7149 } 7150 7151 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7152 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7153 .mac_prepare = mv88e6xxx_mac_prepare, 7154 .mac_config = mv88e6xxx_mac_config, 7155 .mac_finish = mv88e6xxx_mac_finish, 7156 .mac_link_down = mv88e6xxx_mac_link_down, 7157 .mac_link_up = mv88e6xxx_mac_link_up, 7158 }; 7159 7160 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7161 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7162 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7163 .setup = mv88e6xxx_setup, 7164 .teardown = mv88e6xxx_teardown, 7165 .port_setup = mv88e6xxx_port_setup, 7166 .port_teardown = mv88e6xxx_port_teardown, 7167 .phylink_get_caps = mv88e6xxx_get_caps, 7168 .get_strings = mv88e6xxx_get_strings, 7169 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7170 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7171 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7172 .get_sset_count = mv88e6xxx_get_sset_count, 7173 .port_max_mtu = mv88e6xxx_get_max_mtu, 7174 .port_change_mtu = mv88e6xxx_change_mtu, 7175 .support_eee = dsa_supports_eee, 7176 .set_mac_eee = mv88e6xxx_set_mac_eee, 7177 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7178 .get_eeprom = mv88e6xxx_get_eeprom, 7179 .set_eeprom = mv88e6xxx_set_eeprom, 7180 .get_regs_len = mv88e6xxx_get_regs_len, 7181 .get_regs = mv88e6xxx_get_regs, 7182 .get_rxnfc = mv88e6xxx_get_rxnfc, 7183 .set_rxnfc = mv88e6xxx_set_rxnfc, 7184 .set_ageing_time = mv88e6xxx_set_ageing_time, 7185 .port_bridge_join = mv88e6xxx_port_bridge_join, 7186 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7187 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7188 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7189 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7190 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7191 .port_fast_age = mv88e6xxx_port_fast_age, 7192 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7193 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7194 .port_vlan_add = mv88e6xxx_port_vlan_add, 7195 .port_vlan_del = mv88e6xxx_port_vlan_del, 7196 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7197 .port_fdb_add = mv88e6xxx_port_fdb_add, 7198 .port_fdb_del = mv88e6xxx_port_fdb_del, 7199 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7200 .port_mdb_add = mv88e6xxx_port_mdb_add, 7201 .port_mdb_del = mv88e6xxx_port_mdb_del, 7202 .port_mirror_add = mv88e6xxx_port_mirror_add, 7203 .port_mirror_del = mv88e6xxx_port_mirror_del, 7204 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7205 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7206 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7207 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7208 .port_txtstamp = mv88e6xxx_port_txtstamp, 7209 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7210 .get_ts_info = mv88e6xxx_get_ts_info, 7211 .devlink_param_get = mv88e6xxx_devlink_param_get, 7212 .devlink_param_set = mv88e6xxx_devlink_param_set, 7213 .devlink_info_get = mv88e6xxx_devlink_info_get, 7214 .port_lag_change = mv88e6xxx_port_lag_change, 7215 .port_lag_join = mv88e6xxx_port_lag_join, 7216 .port_lag_leave = mv88e6xxx_port_lag_leave, 7217 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7218 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7219 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7220 }; 7221 7222 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7223 { 7224 struct device *dev = chip->dev; 7225 struct dsa_switch *ds; 7226 7227 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7228 if (!ds) 7229 return -ENOMEM; 7230 7231 ds->dev = dev; 7232 ds->num_ports = mv88e6xxx_num_ports(chip); 7233 ds->priv = chip; 7234 ds->dev = dev; 7235 ds->ops = &mv88e6xxx_switch_ops; 7236 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7237 ds->ageing_time_min = chip->info->age_time_coeff; 7238 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7239 7240 /* Some chips support up to 32, but that requires enabling the 7241 * 5-bit port mode, which we do not support. 640k^W16 ought to 7242 * be enough for anyone. 7243 */ 7244 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7245 7246 dev_set_drvdata(dev, ds); 7247 7248 return dsa_register_switch(ds); 7249 } 7250 7251 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7252 { 7253 dsa_unregister_switch(chip->ds); 7254 } 7255 7256 static const void *pdata_device_get_match_data(struct device *dev) 7257 { 7258 const struct of_device_id *matches = dev->driver->of_match_table; 7259 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7260 7261 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7262 matches++) { 7263 if (!strcmp(pdata->compatible, matches->compatible)) 7264 return matches->data; 7265 } 7266 return NULL; 7267 } 7268 7269 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7270 * would be lost after a power cycle so prevent it to be suspended. 7271 */ 7272 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7273 { 7274 return -EOPNOTSUPP; 7275 } 7276 7277 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7278 { 7279 return 0; 7280 } 7281 7282 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7283 7284 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7285 { 7286 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7287 const struct mv88e6xxx_info *compat_info = NULL; 7288 struct device *dev = &mdiodev->dev; 7289 struct device_node *np = dev->of_node; 7290 struct mv88e6xxx_chip *chip; 7291 int port; 7292 int err; 7293 7294 if (!np && !pdata) 7295 return -EINVAL; 7296 7297 if (np) 7298 compat_info = of_device_get_match_data(dev); 7299 7300 if (pdata) { 7301 compat_info = pdata_device_get_match_data(dev); 7302 7303 if (!pdata->netdev) 7304 return -EINVAL; 7305 7306 for (port = 0; port < DSA_MAX_PORTS; port++) { 7307 if (!(pdata->enabled_ports & (1 << port))) 7308 continue; 7309 if (strcmp(pdata->cd.port_names[port], "cpu")) 7310 continue; 7311 pdata->cd.netdev[port] = &pdata->netdev->dev; 7312 break; 7313 } 7314 } 7315 7316 if (!compat_info) 7317 return -EINVAL; 7318 7319 chip = mv88e6xxx_alloc_chip(dev); 7320 if (!chip) { 7321 err = -ENOMEM; 7322 goto out; 7323 } 7324 7325 chip->info = compat_info; 7326 7327 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7328 if (IS_ERR(chip->reset)) { 7329 err = PTR_ERR(chip->reset); 7330 goto out; 7331 } 7332 if (chip->reset) 7333 usleep_range(10000, 20000); 7334 7335 /* Detect if the device is configured in single chip addressing mode, 7336 * otherwise continue with address specific smi init/detection. 7337 */ 7338 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7339 if (err) { 7340 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7341 if (err) 7342 goto out; 7343 7344 err = mv88e6xxx_detect(chip); 7345 if (err) 7346 goto out; 7347 } 7348 7349 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7350 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7351 else 7352 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7353 7354 mv88e6xxx_phy_init(chip); 7355 7356 if (chip->info->ops->get_eeprom) { 7357 if (np) 7358 of_property_read_u32(np, "eeprom-length", 7359 &chip->eeprom_len); 7360 else 7361 chip->eeprom_len = pdata->eeprom_len; 7362 } 7363 7364 mv88e6xxx_reg_lock(chip); 7365 err = mv88e6xxx_switch_reset(chip); 7366 mv88e6xxx_reg_unlock(chip); 7367 if (err) 7368 goto out_phy; 7369 7370 if (np) { 7371 chip->irq = of_irq_get(np, 0); 7372 if (chip->irq == -EPROBE_DEFER) { 7373 err = chip->irq; 7374 goto out_phy; 7375 } 7376 } 7377 7378 if (pdata) 7379 chip->irq = pdata->irq; 7380 7381 /* Has to be performed before the MDIO bus is created, because 7382 * the PHYs will link their interrupts to these interrupt 7383 * controllers 7384 */ 7385 mv88e6xxx_reg_lock(chip); 7386 if (chip->irq > 0) 7387 err = mv88e6xxx_g1_irq_setup(chip); 7388 else 7389 err = mv88e6xxx_irq_poll_setup(chip); 7390 mv88e6xxx_reg_unlock(chip); 7391 7392 if (err) 7393 goto out_phy; 7394 7395 if (chip->info->g2_irqs > 0) { 7396 err = mv88e6xxx_g2_irq_setup(chip); 7397 if (err) 7398 goto out_g1_irq; 7399 } 7400 7401 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7402 if (err) 7403 goto out_g2_irq; 7404 7405 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7406 if (err) 7407 goto out_g1_atu_prob_irq; 7408 7409 err = mv88e6xxx_register_switch(chip); 7410 if (err) 7411 goto out_g1_vtu_prob_irq; 7412 7413 return 0; 7414 7415 out_g1_vtu_prob_irq: 7416 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7417 out_g1_atu_prob_irq: 7418 mv88e6xxx_g1_atu_prob_irq_free(chip); 7419 out_g2_irq: 7420 if (chip->info->g2_irqs > 0) 7421 mv88e6xxx_g2_irq_free(chip); 7422 out_g1_irq: 7423 if (chip->irq > 0) 7424 mv88e6xxx_g1_irq_free(chip); 7425 else 7426 mv88e6xxx_irq_poll_free(chip); 7427 out_phy: 7428 mv88e6xxx_phy_destroy(chip); 7429 out: 7430 if (pdata) 7431 dev_put(pdata->netdev); 7432 7433 return err; 7434 } 7435 7436 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7437 { 7438 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7439 struct mv88e6xxx_chip *chip; 7440 7441 if (!ds) 7442 return; 7443 7444 chip = ds->priv; 7445 7446 mv88e6xxx_unregister_switch(chip); 7447 7448 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7449 mv88e6xxx_g1_atu_prob_irq_free(chip); 7450 7451 if (chip->info->g2_irqs > 0) 7452 mv88e6xxx_g2_irq_free(chip); 7453 7454 if (chip->irq > 0) 7455 mv88e6xxx_g1_irq_free(chip); 7456 else 7457 mv88e6xxx_irq_poll_free(chip); 7458 7459 mv88e6xxx_phy_destroy(chip); 7460 } 7461 7462 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7463 { 7464 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7465 7466 if (!ds) 7467 return; 7468 7469 dsa_switch_shutdown(ds); 7470 7471 dev_set_drvdata(&mdiodev->dev, NULL); 7472 } 7473 7474 static const struct of_device_id mv88e6xxx_of_match[] = { 7475 { 7476 .compatible = "marvell,mv88e6085", 7477 .data = &mv88e6xxx_table[MV88E6085], 7478 }, 7479 { 7480 .compatible = "marvell,mv88e6190", 7481 .data = &mv88e6xxx_table[MV88E6190], 7482 }, 7483 { 7484 .compatible = "marvell,mv88e6250", 7485 .data = &mv88e6xxx_table[MV88E6250], 7486 }, 7487 { /* sentinel */ }, 7488 }; 7489 7490 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7491 7492 static struct mdio_driver mv88e6xxx_driver = { 7493 .probe = mv88e6xxx_probe, 7494 .remove = mv88e6xxx_remove, 7495 .shutdown = mv88e6xxx_shutdown, 7496 .mdiodrv.driver = { 7497 .name = "mv88e6085", 7498 .of_match_table = mv88e6xxx_of_match, 7499 .pm = &mv88e6xxx_pm_ops, 7500 }, 7501 }; 7502 7503 mdio_module_driver(mv88e6xxx_driver); 7504 7505 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7506 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7507 MODULE_LICENSE("GPL"); 7508