1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 570 struct phylink_config *config) 571 { 572 unsigned long *supported = config->supported_interfaces; 573 574 /* Translate the default cmode */ 575 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 576 577 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 578 } 579 580 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 unsigned long *supported = config->supported_interfaces; 584 585 /* Translate the default cmode */ 586 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 587 588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 589 MAC_1000FD; 590 } 591 592 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 593 { 594 u16 reg, val; 595 int err; 596 597 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 598 if (err) 599 return err; 600 601 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 602 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 603 return 0xf; 604 605 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 606 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 607 if (err) 608 return err; 609 610 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 611 if (err) 612 return err; 613 614 /* Restore PHY_DETECT value */ 615 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 616 if (err) 617 return err; 618 619 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 620 } 621 622 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 623 struct phylink_config *config) 624 { 625 unsigned long *supported = config->supported_interfaces; 626 int err, cmode; 627 628 /* Translate the default cmode */ 629 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 630 631 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 632 MAC_1000FD; 633 634 /* Port 4 supports automedia if the serdes is associated with it. */ 635 if (port == 4) { 636 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 637 if (err < 0) 638 dev_err(chip->dev, "p%d: failed to read scratch\n", 639 port); 640 if (err <= 0) 641 return; 642 643 cmode = mv88e6352_get_port4_serdes_cmode(chip); 644 if (cmode < 0) 645 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 646 port); 647 else 648 mv88e6xxx_translate_cmode(cmode, supported); 649 } 650 } 651 652 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 653 struct phylink_config *config) 654 { 655 unsigned long *supported = config->supported_interfaces; 656 657 /* Translate the default cmode */ 658 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 659 660 /* No ethtool bits for 200Mbps */ 661 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 662 MAC_1000FD; 663 664 /* The C_Mode field is programmable on port 5 */ 665 if (port == 5) { 666 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 667 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 668 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 669 670 config->mac_capabilities |= MAC_2500FD; 671 } 672 } 673 674 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 675 struct phylink_config *config) 676 { 677 unsigned long *supported = config->supported_interfaces; 678 679 /* Translate the default cmode */ 680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 681 682 /* No ethtool bits for 200Mbps */ 683 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 684 MAC_1000FD; 685 686 /* The C_Mode field is programmable on ports 9 and 10 */ 687 if (port == 9 || port == 10) { 688 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 689 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 690 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 691 692 config->mac_capabilities |= MAC_2500FD; 693 } 694 } 695 696 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 697 struct phylink_config *config) 698 { 699 unsigned long *supported = config->supported_interfaces; 700 701 mv88e6390_phylink_get_caps(chip, port, config); 702 703 /* For the 6x90X, ports 2-7 can be in automedia mode. 704 * (Note that 6x90 doesn't support RXAUI nor XAUI). 705 * 706 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 707 * configured for 1000BASE-X, SGMII or 2500BASE-X. 708 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 709 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 710 * 711 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 712 * configured for 1000BASE-X, SGMII or 2500BASE-X. 713 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 714 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 715 * 716 * For now, be permissive (as the old code was) and allow 1000BASE-X 717 * on ports 2..7. 718 */ 719 if (port >= 2 && port <= 7) 720 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 721 722 /* The C_Mode field can also be programmed for 10G speeds */ 723 if (port == 9 || port == 10) { 724 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 725 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 726 727 config->mac_capabilities |= MAC_10000FD; 728 } 729 } 730 731 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 732 struct phylink_config *config) 733 { 734 unsigned long *supported = config->supported_interfaces; 735 bool is_6191x = 736 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 737 bool is_6361 = 738 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 739 740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 741 742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 743 MAC_1000FD; 744 745 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 746 if (port == 0 || port == 9 || port == 10) { 747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 749 750 /* 6191X supports >1G modes only on port 10 */ 751 if (!is_6191x || port == 10) { 752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 753 config->mac_capabilities |= MAC_2500FD; 754 755 /* 6361 only supports up to 2500BaseX */ 756 if (!is_6361) { 757 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 758 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 759 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 760 config->mac_capabilities |= MAC_5000FD | 761 MAC_10000FD; 762 } 763 } 764 } 765 766 if (port == 0) { 767 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 768 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 769 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 770 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 771 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 772 } 773 } 774 775 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 776 struct phylink_config *config) 777 { 778 struct mv88e6xxx_chip *chip = ds->priv; 779 780 mv88e6xxx_reg_lock(chip); 781 chip->info->ops->phylink_get_caps(chip, port, config); 782 mv88e6xxx_reg_unlock(chip); 783 784 if (mv88e6xxx_phy_is_internal(chip, port)) { 785 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 786 config->supported_interfaces); 787 /* Internal ports with no phy-mode need GMII for PHYLIB */ 788 __set_bit(PHY_INTERFACE_MODE_GMII, 789 config->supported_interfaces); 790 } 791 } 792 793 static struct phylink_pcs * 794 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 795 phy_interface_t interface) 796 { 797 struct dsa_port *dp = dsa_phylink_to_port(config); 798 struct mv88e6xxx_chip *chip = dp->ds->priv; 799 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 800 801 if (chip->info->ops->pcs_ops) 802 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 803 interface); 804 805 return pcs; 806 } 807 808 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 809 unsigned int mode, phy_interface_t interface) 810 { 811 struct dsa_port *dp = dsa_phylink_to_port(config); 812 struct mv88e6xxx_chip *chip = dp->ds->priv; 813 int port = dp->index; 814 int err = 0; 815 816 /* In inband mode, the link may come up at any time while the link 817 * is not forced down. Force the link down while we reconfigure the 818 * interface mode. 819 */ 820 if (mode == MLO_AN_INBAND && 821 chip->ports[port].interface != interface && 822 chip->info->ops->port_set_link) { 823 mv88e6xxx_reg_lock(chip); 824 err = chip->info->ops->port_set_link(chip, port, 825 LINK_FORCED_DOWN); 826 mv88e6xxx_reg_unlock(chip); 827 } 828 829 return err; 830 } 831 832 static void mv88e6xxx_mac_config(struct phylink_config *config, 833 unsigned int mode, 834 const struct phylink_link_state *state) 835 { 836 struct dsa_port *dp = dsa_phylink_to_port(config); 837 struct mv88e6xxx_chip *chip = dp->ds->priv; 838 int port = dp->index; 839 int err = 0; 840 841 mv88e6xxx_reg_lock(chip); 842 843 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 844 err = mv88e6xxx_port_config_interface(chip, port, 845 state->interface); 846 if (err && err != -EOPNOTSUPP) 847 goto err_unlock; 848 } 849 850 err_unlock: 851 mv88e6xxx_reg_unlock(chip); 852 853 if (err && err != -EOPNOTSUPP) 854 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 855 } 856 857 static int mv88e6xxx_mac_finish(struct phylink_config *config, 858 unsigned int mode, phy_interface_t interface) 859 { 860 struct dsa_port *dp = dsa_phylink_to_port(config); 861 struct mv88e6xxx_chip *chip = dp->ds->priv; 862 int port = dp->index; 863 int err = 0; 864 865 /* Undo the forced down state above after completing configuration 866 * irrespective of its state on entry, which allows the link to come 867 * up in the in-band case where there is no separate SERDES. Also 868 * ensure that the link can come up if the PPU is in use and we are 869 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 870 */ 871 mv88e6xxx_reg_lock(chip); 872 873 if (chip->info->ops->port_set_link && 874 ((mode == MLO_AN_INBAND && 875 chip->ports[port].interface != interface) || 876 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 877 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 878 879 mv88e6xxx_reg_unlock(chip); 880 881 chip->ports[port].interface = interface; 882 883 return err; 884 } 885 886 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 887 unsigned int mode, 888 phy_interface_t interface) 889 { 890 struct dsa_port *dp = dsa_phylink_to_port(config); 891 struct mv88e6xxx_chip *chip = dp->ds->priv; 892 const struct mv88e6xxx_ops *ops; 893 int port = dp->index; 894 int err = 0; 895 896 ops = chip->info->ops; 897 898 mv88e6xxx_reg_lock(chip); 899 /* Force the link down if we know the port may not be automatically 900 * updated by the switch or if we are using fixed-link mode. 901 */ 902 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 903 mode == MLO_AN_FIXED) && ops->port_sync_link) 904 err = ops->port_sync_link(chip, port, mode, false); 905 906 if (!err && ops->port_set_speed_duplex) 907 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 908 DUPLEX_UNFORCED); 909 mv88e6xxx_reg_unlock(chip); 910 911 if (err) 912 dev_err(chip->dev, 913 "p%d: failed to force MAC link down\n", port); 914 } 915 916 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 917 struct phy_device *phydev, 918 unsigned int mode, phy_interface_t interface, 919 int speed, int duplex, 920 bool tx_pause, bool rx_pause) 921 { 922 struct dsa_port *dp = dsa_phylink_to_port(config); 923 struct mv88e6xxx_chip *chip = dp->ds->priv; 924 const struct mv88e6xxx_ops *ops; 925 int port = dp->index; 926 int err = 0; 927 928 ops = chip->info->ops; 929 930 mv88e6xxx_reg_lock(chip); 931 /* Configure and force the link up if we know that the port may not 932 * automatically updated by the switch or if we are using fixed-link 933 * mode. 934 */ 935 if (!mv88e6xxx_port_ppu_updates(chip, port) || 936 mode == MLO_AN_FIXED) { 937 if (ops->port_set_speed_duplex) { 938 err = ops->port_set_speed_duplex(chip, port, 939 speed, duplex); 940 if (err && err != -EOPNOTSUPP) 941 goto error; 942 } 943 944 if (ops->port_sync_link) 945 err = ops->port_sync_link(chip, port, mode, true); 946 } 947 error: 948 mv88e6xxx_reg_unlock(chip); 949 950 if (err && err != -EOPNOTSUPP) 951 dev_err(chip->dev, 952 "p%d: failed to configure MAC link up\n", port); 953 } 954 955 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 956 { 957 int err; 958 959 if (!chip->info->ops->stats_snapshot) 960 return -EOPNOTSUPP; 961 962 mv88e6xxx_reg_lock(chip); 963 err = chip->info->ops->stats_snapshot(chip, port); 964 mv88e6xxx_reg_unlock(chip); 965 966 return err; 967 } 968 969 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 970 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 971 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 972 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 973 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 974 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 975 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 976 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 977 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 978 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 979 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 980 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 981 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 982 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 983 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 984 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 985 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 986 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 987 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 988 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 989 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 990 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 991 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 992 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 993 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 994 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 995 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 996 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 997 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 998 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 999 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1000 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1001 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1002 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1003 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1004 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1005 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1006 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1007 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1008 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1009 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1010 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1011 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1012 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1013 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1014 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1015 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1016 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1017 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1018 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1019 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1020 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1021 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1022 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1023 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1024 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1025 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1026 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1027 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1028 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1029 /* */ 1030 1031 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1032 { #_string, _size, _reg, _type } 1033 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1034 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1035 }; 1036 1037 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1038 MV88E6XXX_HW_STAT_ID_ ## _string 1039 enum mv88e6xxx_hw_stat_id { 1040 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1041 }; 1042 1043 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1044 const struct mv88e6xxx_hw_stat *s, 1045 int port, u16 bank1_select, 1046 u16 histogram) 1047 { 1048 u32 low; 1049 u32 high = 0; 1050 u16 reg = 0; 1051 int err; 1052 u64 value; 1053 1054 switch (s->type) { 1055 case STATS_TYPE_PORT: 1056 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1057 if (err) 1058 return U64_MAX; 1059 1060 low = reg; 1061 if (s->size == 4) { 1062 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1063 if (err) 1064 return U64_MAX; 1065 low |= ((u32)reg) << 16; 1066 } 1067 break; 1068 case STATS_TYPE_BANK1: 1069 reg = bank1_select; 1070 fallthrough; 1071 case STATS_TYPE_BANK0: 1072 reg |= s->reg | histogram; 1073 mv88e6xxx_g1_stats_read(chip, reg, &low); 1074 if (s->size == 8) 1075 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1076 break; 1077 default: 1078 return U64_MAX; 1079 } 1080 value = (((u64)high) << 32) | low; 1081 return value; 1082 } 1083 1084 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1085 uint8_t *data, int types) 1086 { 1087 const struct mv88e6xxx_hw_stat *stat; 1088 int i, j; 1089 1090 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1091 stat = &mv88e6xxx_hw_stats[i]; 1092 if (stat->type & types) { 1093 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1094 ETH_GSTRING_LEN); 1095 j++; 1096 } 1097 } 1098 1099 return j; 1100 } 1101 1102 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1103 uint8_t *data) 1104 { 1105 return mv88e6xxx_stats_get_strings(chip, data, 1106 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1107 } 1108 1109 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1110 uint8_t *data) 1111 { 1112 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1113 } 1114 1115 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1116 uint8_t *data) 1117 { 1118 return mv88e6xxx_stats_get_strings(chip, data, 1119 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1120 } 1121 1122 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1123 "atu_member_violation", 1124 "atu_miss_violation", 1125 "atu_full_violation", 1126 "vtu_member_violation", 1127 "vtu_miss_violation", 1128 }; 1129 1130 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1131 { 1132 unsigned int i; 1133 1134 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1135 strscpy(data + i * ETH_GSTRING_LEN, 1136 mv88e6xxx_atu_vtu_stats_strings[i], 1137 ETH_GSTRING_LEN); 1138 } 1139 1140 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1141 u32 stringset, uint8_t *data) 1142 { 1143 struct mv88e6xxx_chip *chip = ds->priv; 1144 int count = 0; 1145 1146 if (stringset != ETH_SS_STATS) 1147 return; 1148 1149 mv88e6xxx_reg_lock(chip); 1150 1151 if (chip->info->ops->stats_get_strings) 1152 count = chip->info->ops->stats_get_strings(chip, data); 1153 1154 if (chip->info->ops->serdes_get_strings) { 1155 data += count * ETH_GSTRING_LEN; 1156 count = chip->info->ops->serdes_get_strings(chip, port, data); 1157 } 1158 1159 data += count * ETH_GSTRING_LEN; 1160 mv88e6xxx_atu_vtu_get_strings(data); 1161 1162 mv88e6xxx_reg_unlock(chip); 1163 } 1164 1165 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1166 int types) 1167 { 1168 const struct mv88e6xxx_hw_stat *stat; 1169 int i, j; 1170 1171 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1172 stat = &mv88e6xxx_hw_stats[i]; 1173 if (stat->type & types) 1174 j++; 1175 } 1176 return j; 1177 } 1178 1179 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1180 { 1181 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1182 STATS_TYPE_PORT); 1183 } 1184 1185 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1186 { 1187 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1188 } 1189 1190 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1191 { 1192 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1193 STATS_TYPE_BANK1); 1194 } 1195 1196 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1197 { 1198 struct mv88e6xxx_chip *chip = ds->priv; 1199 int serdes_count = 0; 1200 int count = 0; 1201 1202 if (sset != ETH_SS_STATS) 1203 return 0; 1204 1205 mv88e6xxx_reg_lock(chip); 1206 if (chip->info->ops->stats_get_sset_count) 1207 count = chip->info->ops->stats_get_sset_count(chip); 1208 if (count < 0) 1209 goto out; 1210 1211 if (chip->info->ops->serdes_get_sset_count) 1212 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1213 port); 1214 if (serdes_count < 0) { 1215 count = serdes_count; 1216 goto out; 1217 } 1218 count += serdes_count; 1219 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1220 1221 out: 1222 mv88e6xxx_reg_unlock(chip); 1223 1224 return count; 1225 } 1226 1227 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1228 const struct mv88e6xxx_hw_stat *stat, 1229 uint64_t *data) 1230 { 1231 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT))) 1232 return 0; 1233 1234 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1235 MV88E6XXX_G1_STATS_OP_HIST_RX); 1236 return 1; 1237 } 1238 1239 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1240 const struct mv88e6xxx_hw_stat *stat, 1241 uint64_t *data) 1242 { 1243 if (!(stat->type & STATS_TYPE_BANK0)) 1244 return 0; 1245 1246 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1247 MV88E6XXX_G1_STATS_OP_HIST_RX); 1248 return 1; 1249 } 1250 1251 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1252 const struct mv88e6xxx_hw_stat *stat, 1253 uint64_t *data) 1254 { 1255 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1256 return 0; 1257 1258 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1259 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1260 MV88E6XXX_G1_STATS_OP_HIST_RX); 1261 return 1; 1262 } 1263 1264 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1265 const struct mv88e6xxx_hw_stat *stat, 1266 uint64_t *data) 1267 { 1268 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1269 return 0; 1270 1271 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1272 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1273 0); 1274 return 1; 1275 } 1276 1277 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1278 const struct mv88e6xxx_hw_stat *stat, 1279 uint64_t *data) 1280 { 1281 int ret = 0; 1282 1283 if (chip->info->ops->stats_get_stat) { 1284 mv88e6xxx_reg_lock(chip); 1285 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1286 mv88e6xxx_reg_unlock(chip); 1287 } 1288 1289 return ret; 1290 } 1291 1292 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1293 uint64_t *data) 1294 { 1295 const struct mv88e6xxx_hw_stat *stat; 1296 size_t i, j; 1297 1298 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1299 stat = &mv88e6xxx_hw_stats[i]; 1300 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1301 } 1302 return j; 1303 } 1304 1305 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1306 uint64_t *data) 1307 { 1308 *data++ = chip->ports[port].atu_member_violation; 1309 *data++ = chip->ports[port].atu_miss_violation; 1310 *data++ = chip->ports[port].atu_full_violation; 1311 *data++ = chip->ports[port].vtu_member_violation; 1312 *data++ = chip->ports[port].vtu_miss_violation; 1313 } 1314 1315 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1316 uint64_t *data) 1317 { 1318 size_t count; 1319 1320 count = mv88e6xxx_stats_get_stats(chip, port, data); 1321 1322 mv88e6xxx_reg_lock(chip); 1323 if (chip->info->ops->serdes_get_stats) { 1324 data += count; 1325 count = chip->info->ops->serdes_get_stats(chip, port, data); 1326 } 1327 data += count; 1328 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1329 mv88e6xxx_reg_unlock(chip); 1330 } 1331 1332 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1333 uint64_t *data) 1334 { 1335 struct mv88e6xxx_chip *chip = ds->priv; 1336 int ret; 1337 1338 ret = mv88e6xxx_stats_snapshot(chip, port); 1339 if (ret < 0) 1340 return; 1341 1342 mv88e6xxx_get_stats(chip, port, data); 1343 } 1344 1345 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1346 struct ethtool_eth_mac_stats *mac_stats) 1347 { 1348 struct mv88e6xxx_chip *chip = ds->priv; 1349 int ret; 1350 1351 ret = mv88e6xxx_stats_snapshot(chip, port); 1352 if (ret < 0) 1353 return; 1354 1355 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1356 mv88e6xxx_stats_get_stat(chip, port, \ 1357 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1358 &mac_stats->stats._member) 1359 1360 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1361 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1362 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1363 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1364 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1365 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1366 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1367 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1368 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1369 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1370 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1371 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1372 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1373 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1374 1375 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1376 1377 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1378 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1379 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1380 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1381 } 1382 1383 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1384 struct ethtool_rmon_stats *rmon_stats, 1385 const struct ethtool_rmon_hist_range **ranges) 1386 { 1387 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1388 { 64, 64 }, 1389 { 65, 127 }, 1390 { 128, 255 }, 1391 { 256, 511 }, 1392 { 512, 1023 }, 1393 { 1024, 65535 }, 1394 {} 1395 }; 1396 struct mv88e6xxx_chip *chip = ds->priv; 1397 int ret; 1398 1399 ret = mv88e6xxx_stats_snapshot(chip, port); 1400 if (ret < 0) 1401 return; 1402 1403 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1404 mv88e6xxx_stats_get_stat(chip, port, \ 1405 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1406 &rmon_stats->stats._member) 1407 1408 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1409 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1410 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1411 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1412 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1413 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1414 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1415 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1416 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1417 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1418 1419 #undef MV88E6XXX_RMON_STAT_MAP 1420 1421 *ranges = rmon_ranges; 1422 } 1423 1424 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1425 { 1426 struct mv88e6xxx_chip *chip = ds->priv; 1427 int len; 1428 1429 len = 32 * sizeof(u16); 1430 if (chip->info->ops->serdes_get_regs_len) 1431 len += chip->info->ops->serdes_get_regs_len(chip, port); 1432 1433 return len; 1434 } 1435 1436 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1437 struct ethtool_regs *regs, void *_p) 1438 { 1439 struct mv88e6xxx_chip *chip = ds->priv; 1440 int err; 1441 u16 reg; 1442 u16 *p = _p; 1443 int i; 1444 1445 regs->version = chip->info->prod_num; 1446 1447 memset(p, 0xff, 32 * sizeof(u16)); 1448 1449 mv88e6xxx_reg_lock(chip); 1450 1451 for (i = 0; i < 32; i++) { 1452 1453 err = mv88e6xxx_port_read(chip, port, i, ®); 1454 if (!err) 1455 p[i] = reg; 1456 } 1457 1458 if (chip->info->ops->serdes_get_regs) 1459 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1460 1461 mv88e6xxx_reg_unlock(chip); 1462 } 1463 1464 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1465 struct ethtool_keee *e) 1466 { 1467 /* Nothing to do on the port's MAC */ 1468 return 0; 1469 } 1470 1471 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1472 struct ethtool_keee *e) 1473 { 1474 /* Nothing to do on the port's MAC */ 1475 return 0; 1476 } 1477 1478 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1479 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1480 { 1481 struct dsa_switch *ds = chip->ds; 1482 struct dsa_switch_tree *dst = ds->dst; 1483 struct dsa_port *dp, *other_dp; 1484 bool found = false; 1485 u16 pvlan; 1486 1487 /* dev is a physical switch */ 1488 if (dev <= dst->last_switch) { 1489 list_for_each_entry(dp, &dst->ports, list) { 1490 if (dp->ds->index == dev && dp->index == port) { 1491 /* dp might be a DSA link or a user port, so it 1492 * might or might not have a bridge. 1493 * Use the "found" variable for both cases. 1494 */ 1495 found = true; 1496 break; 1497 } 1498 } 1499 /* dev is a virtual bridge */ 1500 } else { 1501 list_for_each_entry(dp, &dst->ports, list) { 1502 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1503 1504 if (!bridge_num) 1505 continue; 1506 1507 if (bridge_num + dst->last_switch != dev) 1508 continue; 1509 1510 found = true; 1511 break; 1512 } 1513 } 1514 1515 /* Prevent frames from unknown switch or virtual bridge */ 1516 if (!found) 1517 return 0; 1518 1519 /* Frames from DSA links and CPU ports can egress any local port */ 1520 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1521 return mv88e6xxx_port_mask(chip); 1522 1523 pvlan = 0; 1524 1525 /* Frames from standalone user ports can only egress on the 1526 * upstream port. 1527 */ 1528 if (!dsa_port_bridge_dev_get(dp)) 1529 return BIT(dsa_switch_upstream_port(ds)); 1530 1531 /* Frames from bridged user ports can egress any local DSA 1532 * links and CPU ports, as well as any local member of their 1533 * bridge group. 1534 */ 1535 dsa_switch_for_each_port(other_dp, ds) 1536 if (other_dp->type == DSA_PORT_TYPE_CPU || 1537 other_dp->type == DSA_PORT_TYPE_DSA || 1538 dsa_port_bridge_same(dp, other_dp)) 1539 pvlan |= BIT(other_dp->index); 1540 1541 return pvlan; 1542 } 1543 1544 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1545 { 1546 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1547 1548 /* prevent frames from going back out of the port they came in on */ 1549 output_ports &= ~BIT(port); 1550 1551 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1552 } 1553 1554 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1555 u8 state) 1556 { 1557 struct mv88e6xxx_chip *chip = ds->priv; 1558 int err; 1559 1560 mv88e6xxx_reg_lock(chip); 1561 err = mv88e6xxx_port_set_state(chip, port, state); 1562 mv88e6xxx_reg_unlock(chip); 1563 1564 if (err) 1565 dev_err(ds->dev, "p%d: failed to update state\n", port); 1566 } 1567 1568 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1569 { 1570 int err; 1571 1572 if (chip->info->ops->ieee_pri_map) { 1573 err = chip->info->ops->ieee_pri_map(chip); 1574 if (err) 1575 return err; 1576 } 1577 1578 if (chip->info->ops->ip_pri_map) { 1579 err = chip->info->ops->ip_pri_map(chip); 1580 if (err) 1581 return err; 1582 } 1583 1584 return 0; 1585 } 1586 1587 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1588 { 1589 struct dsa_switch *ds = chip->ds; 1590 int target, port; 1591 int err; 1592 1593 if (!chip->info->global2_addr) 1594 return 0; 1595 1596 /* Initialize the routing port to the 32 possible target devices */ 1597 for (target = 0; target < 32; target++) { 1598 port = dsa_routing_port(ds, target); 1599 if (port == ds->num_ports) 1600 port = 0x1f; 1601 1602 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1603 if (err) 1604 return err; 1605 } 1606 1607 if (chip->info->ops->set_cascade_port) { 1608 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1609 err = chip->info->ops->set_cascade_port(chip, port); 1610 if (err) 1611 return err; 1612 } 1613 1614 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1615 if (err) 1616 return err; 1617 1618 return 0; 1619 } 1620 1621 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1622 { 1623 /* Clear all trunk masks and mapping */ 1624 if (chip->info->global2_addr) 1625 return mv88e6xxx_g2_trunk_clear(chip); 1626 1627 return 0; 1628 } 1629 1630 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1631 { 1632 if (chip->info->ops->rmu_disable) 1633 return chip->info->ops->rmu_disable(chip); 1634 1635 return 0; 1636 } 1637 1638 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1639 { 1640 if (chip->info->ops->pot_clear) 1641 return chip->info->ops->pot_clear(chip); 1642 1643 return 0; 1644 } 1645 1646 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1647 { 1648 if (chip->info->ops->mgmt_rsvd2cpu) 1649 return chip->info->ops->mgmt_rsvd2cpu(chip); 1650 1651 return 0; 1652 } 1653 1654 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1655 { 1656 int err; 1657 1658 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1659 if (err) 1660 return err; 1661 1662 /* The chips that have a "learn2all" bit in Global1, ATU 1663 * Control are precisely those whose port registers have a 1664 * Message Port bit in Port Control 1 and hence implement 1665 * ->port_setup_message_port. 1666 */ 1667 if (chip->info->ops->port_setup_message_port) { 1668 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1669 if (err) 1670 return err; 1671 } 1672 1673 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1674 } 1675 1676 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1677 { 1678 int port; 1679 int err; 1680 1681 if (!chip->info->ops->irl_init_all) 1682 return 0; 1683 1684 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1685 /* Disable ingress rate limiting by resetting all per port 1686 * ingress rate limit resources to their initial state. 1687 */ 1688 err = chip->info->ops->irl_init_all(chip, port); 1689 if (err) 1690 return err; 1691 } 1692 1693 return 0; 1694 } 1695 1696 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1697 { 1698 if (chip->info->ops->set_switch_mac) { 1699 u8 addr[ETH_ALEN]; 1700 1701 eth_random_addr(addr); 1702 1703 return chip->info->ops->set_switch_mac(chip, addr); 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1710 { 1711 struct dsa_switch_tree *dst = chip->ds->dst; 1712 struct dsa_switch *ds; 1713 struct dsa_port *dp; 1714 u16 pvlan = 0; 1715 1716 if (!mv88e6xxx_has_pvt(chip)) 1717 return 0; 1718 1719 /* Skip the local source device, which uses in-chip port VLAN */ 1720 if (dev != chip->ds->index) { 1721 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1722 1723 ds = dsa_switch_find(dst->index, dev); 1724 dp = ds ? dsa_to_port(ds, port) : NULL; 1725 if (dp && dp->lag) { 1726 /* As the PVT is used to limit flooding of 1727 * FORWARD frames, which use the LAG ID as the 1728 * source port, we must translate dev/port to 1729 * the special "LAG device" in the PVT, using 1730 * the LAG ID (one-based) as the port number 1731 * (zero-based). 1732 */ 1733 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1734 port = dsa_port_lag_id_get(dp) - 1; 1735 } 1736 } 1737 1738 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1739 } 1740 1741 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1742 { 1743 int dev, port; 1744 int err; 1745 1746 if (!mv88e6xxx_has_pvt(chip)) 1747 return 0; 1748 1749 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1750 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1751 */ 1752 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1753 if (err) 1754 return err; 1755 1756 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1757 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1758 err = mv88e6xxx_pvt_map(chip, dev, port); 1759 if (err) 1760 return err; 1761 } 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1768 u16 fid) 1769 { 1770 if (dsa_to_port(chip->ds, port)->lag) 1771 /* Hardware is incapable of fast-aging a LAG through a 1772 * regular ATU move operation. Until we have something 1773 * more fancy in place this is a no-op. 1774 */ 1775 return -EOPNOTSUPP; 1776 1777 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1778 } 1779 1780 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1781 { 1782 struct mv88e6xxx_chip *chip = ds->priv; 1783 int err; 1784 1785 mv88e6xxx_reg_lock(chip); 1786 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1787 mv88e6xxx_reg_unlock(chip); 1788 1789 if (err) 1790 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1791 port, err); 1792 } 1793 1794 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1795 { 1796 if (!mv88e6xxx_max_vid(chip)) 1797 return 0; 1798 1799 return mv88e6xxx_g1_vtu_flush(chip); 1800 } 1801 1802 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1803 struct mv88e6xxx_vtu_entry *entry) 1804 { 1805 int err; 1806 1807 if (!chip->info->ops->vtu_getnext) 1808 return -EOPNOTSUPP; 1809 1810 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1811 entry->valid = false; 1812 1813 err = chip->info->ops->vtu_getnext(chip, entry); 1814 1815 if (entry->vid != vid) 1816 entry->valid = false; 1817 1818 return err; 1819 } 1820 1821 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1822 int (*cb)(struct mv88e6xxx_chip *chip, 1823 const struct mv88e6xxx_vtu_entry *entry, 1824 void *priv), 1825 void *priv) 1826 { 1827 struct mv88e6xxx_vtu_entry entry = { 1828 .vid = mv88e6xxx_max_vid(chip), 1829 .valid = false, 1830 }; 1831 int err; 1832 1833 if (!chip->info->ops->vtu_getnext) 1834 return -EOPNOTSUPP; 1835 1836 do { 1837 err = chip->info->ops->vtu_getnext(chip, &entry); 1838 if (err) 1839 return err; 1840 1841 if (!entry.valid) 1842 break; 1843 1844 err = cb(chip, &entry, priv); 1845 if (err) 1846 return err; 1847 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1848 1849 return 0; 1850 } 1851 1852 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1853 struct mv88e6xxx_vtu_entry *entry) 1854 { 1855 if (!chip->info->ops->vtu_loadpurge) 1856 return -EOPNOTSUPP; 1857 1858 return chip->info->ops->vtu_loadpurge(chip, entry); 1859 } 1860 1861 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1862 const struct mv88e6xxx_vtu_entry *entry, 1863 void *_fid_bitmap) 1864 { 1865 unsigned long *fid_bitmap = _fid_bitmap; 1866 1867 set_bit(entry->fid, fid_bitmap); 1868 return 0; 1869 } 1870 1871 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1872 { 1873 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1874 1875 /* Every FID has an associated VID, so walking the VTU 1876 * will discover the full set of FIDs in use. 1877 */ 1878 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1879 } 1880 1881 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1882 { 1883 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1884 int err; 1885 1886 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1887 if (err) 1888 return err; 1889 1890 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1891 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1892 return -ENOSPC; 1893 1894 /* Clear the database */ 1895 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1896 } 1897 1898 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1899 struct mv88e6xxx_stu_entry *entry) 1900 { 1901 if (!chip->info->ops->stu_loadpurge) 1902 return -EOPNOTSUPP; 1903 1904 return chip->info->ops->stu_loadpurge(chip, entry); 1905 } 1906 1907 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1908 { 1909 struct mv88e6xxx_stu_entry stu = { 1910 .valid = true, 1911 .sid = 0 1912 }; 1913 1914 if (!mv88e6xxx_has_stu(chip)) 1915 return 0; 1916 1917 /* Make sure that SID 0 is always valid. This is used by VTU 1918 * entries that do not make use of the STU, e.g. when creating 1919 * a VLAN upper on a port that is also part of a VLAN 1920 * filtering bridge. 1921 */ 1922 return mv88e6xxx_stu_loadpurge(chip, &stu); 1923 } 1924 1925 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1926 { 1927 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1928 struct mv88e6xxx_mst *mst; 1929 1930 __set_bit(0, busy); 1931 1932 list_for_each_entry(mst, &chip->msts, node) 1933 __set_bit(mst->stu.sid, busy); 1934 1935 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1936 1937 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1938 } 1939 1940 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1941 { 1942 struct mv88e6xxx_mst *mst, *tmp; 1943 int err; 1944 1945 if (!sid) 1946 return 0; 1947 1948 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1949 if (mst->stu.sid != sid) 1950 continue; 1951 1952 if (!refcount_dec_and_test(&mst->refcnt)) 1953 return 0; 1954 1955 mst->stu.valid = false; 1956 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1957 if (err) { 1958 refcount_set(&mst->refcnt, 1); 1959 return err; 1960 } 1961 1962 list_del(&mst->node); 1963 kfree(mst); 1964 return 0; 1965 } 1966 1967 return -ENOENT; 1968 } 1969 1970 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1971 u16 msti, u8 *sid) 1972 { 1973 struct mv88e6xxx_mst *mst; 1974 int err, i; 1975 1976 if (!mv88e6xxx_has_stu(chip)) { 1977 err = -EOPNOTSUPP; 1978 goto err; 1979 } 1980 1981 if (!msti) { 1982 *sid = 0; 1983 return 0; 1984 } 1985 1986 list_for_each_entry(mst, &chip->msts, node) { 1987 if (mst->br == br && mst->msti == msti) { 1988 refcount_inc(&mst->refcnt); 1989 *sid = mst->stu.sid; 1990 return 0; 1991 } 1992 } 1993 1994 err = mv88e6xxx_sid_get(chip, sid); 1995 if (err) 1996 goto err; 1997 1998 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1999 if (!mst) { 2000 err = -ENOMEM; 2001 goto err; 2002 } 2003 2004 INIT_LIST_HEAD(&mst->node); 2005 refcount_set(&mst->refcnt, 1); 2006 mst->br = br; 2007 mst->msti = msti; 2008 mst->stu.valid = true; 2009 mst->stu.sid = *sid; 2010 2011 /* The bridge starts out all ports in the disabled state. But 2012 * a STU state of disabled means to go by the port-global 2013 * state. So we set all user port's initial state to blocking, 2014 * to match the bridge's behavior. 2015 */ 2016 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2017 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2018 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2019 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2020 2021 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2022 if (err) 2023 goto err_free; 2024 2025 list_add_tail(&mst->node, &chip->msts); 2026 return 0; 2027 2028 err_free: 2029 kfree(mst); 2030 err: 2031 return err; 2032 } 2033 2034 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2035 const struct switchdev_mst_state *st) 2036 { 2037 struct dsa_port *dp = dsa_to_port(ds, port); 2038 struct mv88e6xxx_chip *chip = ds->priv; 2039 struct mv88e6xxx_mst *mst; 2040 u8 state; 2041 int err; 2042 2043 if (!mv88e6xxx_has_stu(chip)) 2044 return -EOPNOTSUPP; 2045 2046 switch (st->state) { 2047 case BR_STATE_DISABLED: 2048 case BR_STATE_BLOCKING: 2049 case BR_STATE_LISTENING: 2050 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2051 break; 2052 case BR_STATE_LEARNING: 2053 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2054 break; 2055 case BR_STATE_FORWARDING: 2056 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2057 break; 2058 default: 2059 return -EINVAL; 2060 } 2061 2062 list_for_each_entry(mst, &chip->msts, node) { 2063 if (mst->br == dsa_port_bridge_dev_get(dp) && 2064 mst->msti == st->msti) { 2065 if (mst->stu.state[port] == state) 2066 return 0; 2067 2068 mst->stu.state[port] = state; 2069 mv88e6xxx_reg_lock(chip); 2070 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2071 mv88e6xxx_reg_unlock(chip); 2072 return err; 2073 } 2074 } 2075 2076 return -ENOENT; 2077 } 2078 2079 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2080 u16 vid) 2081 { 2082 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2083 struct mv88e6xxx_chip *chip = ds->priv; 2084 struct mv88e6xxx_vtu_entry vlan; 2085 int err; 2086 2087 /* DSA and CPU ports have to be members of multiple vlans */ 2088 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2089 return 0; 2090 2091 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2092 if (err) 2093 return err; 2094 2095 if (!vlan.valid) 2096 return 0; 2097 2098 dsa_switch_for_each_user_port(other_dp, ds) { 2099 struct net_device *other_br; 2100 2101 if (vlan.member[other_dp->index] == 2102 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2103 continue; 2104 2105 if (dsa_port_bridge_same(dp, other_dp)) 2106 break; /* same bridge, check next VLAN */ 2107 2108 other_br = dsa_port_bridge_dev_get(other_dp); 2109 if (!other_br) 2110 continue; 2111 2112 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2113 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2114 return -EOPNOTSUPP; 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2121 { 2122 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2123 struct net_device *br = dsa_port_bridge_dev_get(dp); 2124 struct mv88e6xxx_port *p = &chip->ports[port]; 2125 u16 pvid = MV88E6XXX_VID_STANDALONE; 2126 bool drop_untagged = false; 2127 int err; 2128 2129 if (br) { 2130 if (br_vlan_enabled(br)) { 2131 pvid = p->bridge_pvid.vid; 2132 drop_untagged = !p->bridge_pvid.valid; 2133 } else { 2134 pvid = MV88E6XXX_VID_BRIDGED; 2135 } 2136 } 2137 2138 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2139 if (err) 2140 return err; 2141 2142 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2143 } 2144 2145 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2146 bool vlan_filtering, 2147 struct netlink_ext_ack *extack) 2148 { 2149 struct mv88e6xxx_chip *chip = ds->priv; 2150 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2151 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2152 int err; 2153 2154 if (!mv88e6xxx_max_vid(chip)) 2155 return -EOPNOTSUPP; 2156 2157 mv88e6xxx_reg_lock(chip); 2158 2159 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2160 if (err) 2161 goto unlock; 2162 2163 err = mv88e6xxx_port_commit_pvid(chip, port); 2164 if (err) 2165 goto unlock; 2166 2167 unlock: 2168 mv88e6xxx_reg_unlock(chip); 2169 2170 return err; 2171 } 2172 2173 static int 2174 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2175 const struct switchdev_obj_port_vlan *vlan) 2176 { 2177 struct mv88e6xxx_chip *chip = ds->priv; 2178 int err; 2179 2180 if (!mv88e6xxx_max_vid(chip)) 2181 return -EOPNOTSUPP; 2182 2183 /* If the requested port doesn't belong to the same bridge as the VLAN 2184 * members, do not support it (yet) and fallback to software VLAN. 2185 */ 2186 mv88e6xxx_reg_lock(chip); 2187 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2188 mv88e6xxx_reg_unlock(chip); 2189 2190 return err; 2191 } 2192 2193 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2194 const unsigned char *addr, u16 vid, 2195 u8 state) 2196 { 2197 struct mv88e6xxx_atu_entry entry; 2198 struct mv88e6xxx_vtu_entry vlan; 2199 u16 fid; 2200 int err; 2201 2202 /* Ports have two private address databases: one for when the port is 2203 * standalone and one for when the port is under a bridge and the 2204 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2205 * address database to remain 100% empty, so we never load an ATU entry 2206 * into a standalone port's database. Therefore, translate the null 2207 * VLAN ID into the port's database used for VLAN-unaware bridging. 2208 */ 2209 if (vid == 0) { 2210 fid = MV88E6XXX_FID_BRIDGED; 2211 } else { 2212 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2213 if (err) 2214 return err; 2215 2216 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2217 if (!vlan.valid) 2218 return -EOPNOTSUPP; 2219 2220 fid = vlan.fid; 2221 } 2222 2223 entry.state = 0; 2224 ether_addr_copy(entry.mac, addr); 2225 eth_addr_dec(entry.mac); 2226 2227 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2228 if (err) 2229 return err; 2230 2231 /* Initialize a fresh ATU entry if it isn't found */ 2232 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2233 memset(&entry, 0, sizeof(entry)); 2234 ether_addr_copy(entry.mac, addr); 2235 } 2236 2237 /* Purge the ATU entry only if no port is using it anymore */ 2238 if (!state) { 2239 entry.portvec &= ~BIT(port); 2240 if (!entry.portvec) 2241 entry.state = 0; 2242 } else { 2243 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2244 entry.portvec = BIT(port); 2245 else 2246 entry.portvec |= BIT(port); 2247 2248 entry.state = state; 2249 } 2250 2251 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2252 } 2253 2254 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2255 const struct mv88e6xxx_policy *policy) 2256 { 2257 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2258 enum mv88e6xxx_policy_action action = policy->action; 2259 const u8 *addr = policy->addr; 2260 u16 vid = policy->vid; 2261 u8 state; 2262 int err; 2263 int id; 2264 2265 if (!chip->info->ops->port_set_policy) 2266 return -EOPNOTSUPP; 2267 2268 switch (mapping) { 2269 case MV88E6XXX_POLICY_MAPPING_DA: 2270 case MV88E6XXX_POLICY_MAPPING_SA: 2271 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2272 state = 0; /* Dissociate the port and address */ 2273 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2274 is_multicast_ether_addr(addr)) 2275 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2276 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2277 is_unicast_ether_addr(addr)) 2278 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2279 else 2280 return -EOPNOTSUPP; 2281 2282 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2283 state); 2284 if (err) 2285 return err; 2286 break; 2287 default: 2288 return -EOPNOTSUPP; 2289 } 2290 2291 /* Skip the port's policy clearing if the mapping is still in use */ 2292 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2293 idr_for_each_entry(&chip->policies, policy, id) 2294 if (policy->port == port && 2295 policy->mapping == mapping && 2296 policy->action != action) 2297 return 0; 2298 2299 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2300 } 2301 2302 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2303 struct ethtool_rx_flow_spec *fs) 2304 { 2305 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2306 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2307 enum mv88e6xxx_policy_mapping mapping; 2308 enum mv88e6xxx_policy_action action; 2309 struct mv88e6xxx_policy *policy; 2310 u16 vid = 0; 2311 u8 *addr; 2312 int err; 2313 int id; 2314 2315 if (fs->location != RX_CLS_LOC_ANY) 2316 return -EINVAL; 2317 2318 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2319 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2320 else 2321 return -EOPNOTSUPP; 2322 2323 switch (fs->flow_type & ~FLOW_EXT) { 2324 case ETHER_FLOW: 2325 if (!is_zero_ether_addr(mac_mask->h_dest) && 2326 is_zero_ether_addr(mac_mask->h_source)) { 2327 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2328 addr = mac_entry->h_dest; 2329 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2330 !is_zero_ether_addr(mac_mask->h_source)) { 2331 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2332 addr = mac_entry->h_source; 2333 } else { 2334 /* Cannot support DA and SA mapping in the same rule */ 2335 return -EOPNOTSUPP; 2336 } 2337 break; 2338 default: 2339 return -EOPNOTSUPP; 2340 } 2341 2342 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2343 if (fs->m_ext.vlan_tci != htons(0xffff)) 2344 return -EOPNOTSUPP; 2345 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2346 } 2347 2348 idr_for_each_entry(&chip->policies, policy, id) { 2349 if (policy->port == port && policy->mapping == mapping && 2350 policy->action == action && policy->vid == vid && 2351 ether_addr_equal(policy->addr, addr)) 2352 return -EEXIST; 2353 } 2354 2355 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2356 if (!policy) 2357 return -ENOMEM; 2358 2359 fs->location = 0; 2360 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2361 GFP_KERNEL); 2362 if (err) { 2363 devm_kfree(chip->dev, policy); 2364 return err; 2365 } 2366 2367 memcpy(&policy->fs, fs, sizeof(*fs)); 2368 ether_addr_copy(policy->addr, addr); 2369 policy->mapping = mapping; 2370 policy->action = action; 2371 policy->port = port; 2372 policy->vid = vid; 2373 2374 err = mv88e6xxx_policy_apply(chip, port, policy); 2375 if (err) { 2376 idr_remove(&chip->policies, fs->location); 2377 devm_kfree(chip->dev, policy); 2378 return err; 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2385 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2386 { 2387 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2388 struct mv88e6xxx_chip *chip = ds->priv; 2389 struct mv88e6xxx_policy *policy; 2390 int err; 2391 int id; 2392 2393 mv88e6xxx_reg_lock(chip); 2394 2395 switch (rxnfc->cmd) { 2396 case ETHTOOL_GRXCLSRLCNT: 2397 rxnfc->data = 0; 2398 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2399 rxnfc->rule_cnt = 0; 2400 idr_for_each_entry(&chip->policies, policy, id) 2401 if (policy->port == port) 2402 rxnfc->rule_cnt++; 2403 err = 0; 2404 break; 2405 case ETHTOOL_GRXCLSRULE: 2406 err = -ENOENT; 2407 policy = idr_find(&chip->policies, fs->location); 2408 if (policy) { 2409 memcpy(fs, &policy->fs, sizeof(*fs)); 2410 err = 0; 2411 } 2412 break; 2413 case ETHTOOL_GRXCLSRLALL: 2414 rxnfc->data = 0; 2415 rxnfc->rule_cnt = 0; 2416 idr_for_each_entry(&chip->policies, policy, id) 2417 if (policy->port == port) 2418 rule_locs[rxnfc->rule_cnt++] = id; 2419 err = 0; 2420 break; 2421 default: 2422 err = -EOPNOTSUPP; 2423 break; 2424 } 2425 2426 mv88e6xxx_reg_unlock(chip); 2427 2428 return err; 2429 } 2430 2431 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2432 struct ethtool_rxnfc *rxnfc) 2433 { 2434 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2435 struct mv88e6xxx_chip *chip = ds->priv; 2436 struct mv88e6xxx_policy *policy; 2437 int err; 2438 2439 mv88e6xxx_reg_lock(chip); 2440 2441 switch (rxnfc->cmd) { 2442 case ETHTOOL_SRXCLSRLINS: 2443 err = mv88e6xxx_policy_insert(chip, port, fs); 2444 break; 2445 case ETHTOOL_SRXCLSRLDEL: 2446 err = -ENOENT; 2447 policy = idr_remove(&chip->policies, fs->location); 2448 if (policy) { 2449 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2450 err = mv88e6xxx_policy_apply(chip, port, policy); 2451 devm_kfree(chip->dev, policy); 2452 } 2453 break; 2454 default: 2455 err = -EOPNOTSUPP; 2456 break; 2457 } 2458 2459 mv88e6xxx_reg_unlock(chip); 2460 2461 return err; 2462 } 2463 2464 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2465 u16 vid) 2466 { 2467 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2468 u8 broadcast[ETH_ALEN]; 2469 2470 eth_broadcast_addr(broadcast); 2471 2472 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2473 } 2474 2475 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2476 { 2477 int port; 2478 int err; 2479 2480 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2481 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2482 struct net_device *brport; 2483 2484 if (dsa_is_unused_port(chip->ds, port)) 2485 continue; 2486 2487 brport = dsa_port_to_bridge_port(dp); 2488 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2489 /* Skip bridged user ports where broadcast 2490 * flooding is disabled. 2491 */ 2492 continue; 2493 2494 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2495 if (err) 2496 return err; 2497 } 2498 2499 return 0; 2500 } 2501 2502 struct mv88e6xxx_port_broadcast_sync_ctx { 2503 int port; 2504 bool flood; 2505 }; 2506 2507 static int 2508 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2509 const struct mv88e6xxx_vtu_entry *vlan, 2510 void *_ctx) 2511 { 2512 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2513 u8 broadcast[ETH_ALEN]; 2514 u8 state; 2515 2516 if (ctx->flood) 2517 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2518 else 2519 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2520 2521 eth_broadcast_addr(broadcast); 2522 2523 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2524 vlan->vid, state); 2525 } 2526 2527 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2528 bool flood) 2529 { 2530 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2531 .port = port, 2532 .flood = flood, 2533 }; 2534 struct mv88e6xxx_vtu_entry vid0 = { 2535 .vid = 0, 2536 }; 2537 int err; 2538 2539 /* Update the port's private database... */ 2540 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2541 if (err) 2542 return err; 2543 2544 /* ...and the database for all VLANs. */ 2545 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2546 &ctx); 2547 } 2548 2549 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2550 u16 vid, u8 member, bool warn) 2551 { 2552 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2553 struct mv88e6xxx_vtu_entry vlan; 2554 int i, err; 2555 2556 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2557 if (err) 2558 return err; 2559 2560 if (!vlan.valid) { 2561 memset(&vlan, 0, sizeof(vlan)); 2562 2563 if (vid == MV88E6XXX_VID_STANDALONE) 2564 vlan.policy = true; 2565 2566 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2567 if (err) 2568 return err; 2569 2570 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2571 if (i == port) 2572 vlan.member[i] = member; 2573 else 2574 vlan.member[i] = non_member; 2575 2576 vlan.vid = vid; 2577 vlan.valid = true; 2578 2579 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2580 if (err) 2581 return err; 2582 2583 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2584 if (err) 2585 return err; 2586 } else if (vlan.member[port] != member) { 2587 vlan.member[port] = member; 2588 2589 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2590 if (err) 2591 return err; 2592 } else if (warn) { 2593 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2594 port, vid); 2595 } 2596 2597 return 0; 2598 } 2599 2600 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2601 const struct switchdev_obj_port_vlan *vlan, 2602 struct netlink_ext_ack *extack) 2603 { 2604 struct mv88e6xxx_chip *chip = ds->priv; 2605 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2606 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2607 struct mv88e6xxx_port *p = &chip->ports[port]; 2608 bool warn; 2609 u8 member; 2610 int err; 2611 2612 if (!vlan->vid) 2613 return 0; 2614 2615 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2616 if (err) 2617 return err; 2618 2619 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2620 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2621 else if (untagged) 2622 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2623 else 2624 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2625 2626 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2627 * and then the CPU port. Do not warn for duplicates for the CPU port. 2628 */ 2629 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2630 2631 mv88e6xxx_reg_lock(chip); 2632 2633 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2634 if (err) { 2635 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2636 vlan->vid, untagged ? 'u' : 't'); 2637 goto out; 2638 } 2639 2640 if (pvid) { 2641 p->bridge_pvid.vid = vlan->vid; 2642 p->bridge_pvid.valid = true; 2643 2644 err = mv88e6xxx_port_commit_pvid(chip, port); 2645 if (err) 2646 goto out; 2647 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2648 /* The old pvid was reinstalled as a non-pvid VLAN */ 2649 p->bridge_pvid.valid = false; 2650 2651 err = mv88e6xxx_port_commit_pvid(chip, port); 2652 if (err) 2653 goto out; 2654 } 2655 2656 out: 2657 mv88e6xxx_reg_unlock(chip); 2658 2659 return err; 2660 } 2661 2662 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2663 int port, u16 vid) 2664 { 2665 struct mv88e6xxx_vtu_entry vlan; 2666 int i, err; 2667 2668 if (!vid) 2669 return 0; 2670 2671 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2672 if (err) 2673 return err; 2674 2675 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2676 * tell switchdev that this VLAN is likely handled in software. 2677 */ 2678 if (!vlan.valid || 2679 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2680 return -EOPNOTSUPP; 2681 2682 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2683 2684 /* keep the VLAN unless all ports are excluded */ 2685 vlan.valid = false; 2686 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2687 if (vlan.member[i] != 2688 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2689 vlan.valid = true; 2690 break; 2691 } 2692 } 2693 2694 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2695 if (err) 2696 return err; 2697 2698 if (!vlan.valid) { 2699 err = mv88e6xxx_mst_put(chip, vlan.sid); 2700 if (err) 2701 return err; 2702 } 2703 2704 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2705 } 2706 2707 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2708 const struct switchdev_obj_port_vlan *vlan) 2709 { 2710 struct mv88e6xxx_chip *chip = ds->priv; 2711 struct mv88e6xxx_port *p = &chip->ports[port]; 2712 int err = 0; 2713 u16 pvid; 2714 2715 if (!mv88e6xxx_max_vid(chip)) 2716 return -EOPNOTSUPP; 2717 2718 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2719 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2720 * switchdev workqueue to ensure that all FDB entries are deleted 2721 * before we remove the VLAN. 2722 */ 2723 dsa_flush_workqueue(); 2724 2725 mv88e6xxx_reg_lock(chip); 2726 2727 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2728 if (err) 2729 goto unlock; 2730 2731 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2732 if (err) 2733 goto unlock; 2734 2735 if (vlan->vid == pvid) { 2736 p->bridge_pvid.valid = false; 2737 2738 err = mv88e6xxx_port_commit_pvid(chip, port); 2739 if (err) 2740 goto unlock; 2741 } 2742 2743 unlock: 2744 mv88e6xxx_reg_unlock(chip); 2745 2746 return err; 2747 } 2748 2749 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2750 { 2751 struct mv88e6xxx_chip *chip = ds->priv; 2752 struct mv88e6xxx_vtu_entry vlan; 2753 int err; 2754 2755 mv88e6xxx_reg_lock(chip); 2756 2757 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2758 if (err) 2759 goto unlock; 2760 2761 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2762 2763 unlock: 2764 mv88e6xxx_reg_unlock(chip); 2765 2766 return err; 2767 } 2768 2769 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2770 struct dsa_bridge bridge, 2771 const struct switchdev_vlan_msti *msti) 2772 { 2773 struct mv88e6xxx_chip *chip = ds->priv; 2774 struct mv88e6xxx_vtu_entry vlan; 2775 u8 old_sid, new_sid; 2776 int err; 2777 2778 if (!mv88e6xxx_has_stu(chip)) 2779 return -EOPNOTSUPP; 2780 2781 mv88e6xxx_reg_lock(chip); 2782 2783 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2784 if (err) 2785 goto unlock; 2786 2787 if (!vlan.valid) { 2788 err = -EINVAL; 2789 goto unlock; 2790 } 2791 2792 old_sid = vlan.sid; 2793 2794 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2795 if (err) 2796 goto unlock; 2797 2798 if (new_sid != old_sid) { 2799 vlan.sid = new_sid; 2800 2801 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2802 if (err) { 2803 mv88e6xxx_mst_put(chip, new_sid); 2804 goto unlock; 2805 } 2806 } 2807 2808 err = mv88e6xxx_mst_put(chip, old_sid); 2809 2810 unlock: 2811 mv88e6xxx_reg_unlock(chip); 2812 return err; 2813 } 2814 2815 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2816 const unsigned char *addr, u16 vid, 2817 struct dsa_db db) 2818 { 2819 struct mv88e6xxx_chip *chip = ds->priv; 2820 int err; 2821 2822 mv88e6xxx_reg_lock(chip); 2823 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2824 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2825 mv88e6xxx_reg_unlock(chip); 2826 2827 return err; 2828 } 2829 2830 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2831 const unsigned char *addr, u16 vid, 2832 struct dsa_db db) 2833 { 2834 struct mv88e6xxx_chip *chip = ds->priv; 2835 int err; 2836 2837 mv88e6xxx_reg_lock(chip); 2838 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2839 mv88e6xxx_reg_unlock(chip); 2840 2841 return err; 2842 } 2843 2844 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2845 u16 fid, u16 vid, int port, 2846 dsa_fdb_dump_cb_t *cb, void *data) 2847 { 2848 struct mv88e6xxx_atu_entry addr; 2849 bool is_static; 2850 int err; 2851 2852 addr.state = 0; 2853 eth_broadcast_addr(addr.mac); 2854 2855 do { 2856 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2857 if (err) 2858 return err; 2859 2860 if (!addr.state) 2861 break; 2862 2863 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2864 continue; 2865 2866 if (!is_unicast_ether_addr(addr.mac)) 2867 continue; 2868 2869 is_static = (addr.state == 2870 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2871 err = cb(addr.mac, vid, is_static, data); 2872 if (err) 2873 return err; 2874 } while (!is_broadcast_ether_addr(addr.mac)); 2875 2876 return err; 2877 } 2878 2879 struct mv88e6xxx_port_db_dump_vlan_ctx { 2880 int port; 2881 dsa_fdb_dump_cb_t *cb; 2882 void *data; 2883 }; 2884 2885 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2886 const struct mv88e6xxx_vtu_entry *entry, 2887 void *_data) 2888 { 2889 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2890 2891 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2892 ctx->port, ctx->cb, ctx->data); 2893 } 2894 2895 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2896 dsa_fdb_dump_cb_t *cb, void *data) 2897 { 2898 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2899 .port = port, 2900 .cb = cb, 2901 .data = data, 2902 }; 2903 u16 fid; 2904 int err; 2905 2906 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2907 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2908 if (err) 2909 return err; 2910 2911 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2912 if (err) 2913 return err; 2914 2915 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2916 } 2917 2918 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2919 dsa_fdb_dump_cb_t *cb, void *data) 2920 { 2921 struct mv88e6xxx_chip *chip = ds->priv; 2922 int err; 2923 2924 mv88e6xxx_reg_lock(chip); 2925 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2926 mv88e6xxx_reg_unlock(chip); 2927 2928 return err; 2929 } 2930 2931 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2932 struct dsa_bridge bridge) 2933 { 2934 struct dsa_switch *ds = chip->ds; 2935 struct dsa_switch_tree *dst = ds->dst; 2936 struct dsa_port *dp; 2937 int err; 2938 2939 list_for_each_entry(dp, &dst->ports, list) { 2940 if (dsa_port_offloads_bridge(dp, &bridge)) { 2941 if (dp->ds == ds) { 2942 /* This is a local bridge group member, 2943 * remap its Port VLAN Map. 2944 */ 2945 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2946 if (err) 2947 return err; 2948 } else { 2949 /* This is an external bridge group member, 2950 * remap its cross-chip Port VLAN Table entry. 2951 */ 2952 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2953 dp->index); 2954 if (err) 2955 return err; 2956 } 2957 } 2958 } 2959 2960 return 0; 2961 } 2962 2963 /* Treat the software bridge as a virtual single-port switch behind the 2964 * CPU and map in the PVT. First dst->last_switch elements are taken by 2965 * physical switches, so start from beyond that range. 2966 */ 2967 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2968 unsigned int bridge_num) 2969 { 2970 u8 dev = bridge_num + ds->dst->last_switch; 2971 struct mv88e6xxx_chip *chip = ds->priv; 2972 2973 return mv88e6xxx_pvt_map(chip, dev, 0); 2974 } 2975 2976 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2977 struct dsa_bridge bridge, 2978 bool *tx_fwd_offload, 2979 struct netlink_ext_ack *extack) 2980 { 2981 struct mv88e6xxx_chip *chip = ds->priv; 2982 int err; 2983 2984 mv88e6xxx_reg_lock(chip); 2985 2986 err = mv88e6xxx_bridge_map(chip, bridge); 2987 if (err) 2988 goto unlock; 2989 2990 err = mv88e6xxx_port_set_map_da(chip, port, true); 2991 if (err) 2992 goto unlock; 2993 2994 err = mv88e6xxx_port_commit_pvid(chip, port); 2995 if (err) 2996 goto unlock; 2997 2998 if (mv88e6xxx_has_pvt(chip)) { 2999 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3000 if (err) 3001 goto unlock; 3002 3003 *tx_fwd_offload = true; 3004 } 3005 3006 unlock: 3007 mv88e6xxx_reg_unlock(chip); 3008 3009 return err; 3010 } 3011 3012 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3013 struct dsa_bridge bridge) 3014 { 3015 struct mv88e6xxx_chip *chip = ds->priv; 3016 int err; 3017 3018 mv88e6xxx_reg_lock(chip); 3019 3020 if (bridge.tx_fwd_offload && 3021 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3022 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3023 3024 if (mv88e6xxx_bridge_map(chip, bridge) || 3025 mv88e6xxx_port_vlan_map(chip, port)) 3026 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3027 3028 err = mv88e6xxx_port_set_map_da(chip, port, false); 3029 if (err) 3030 dev_err(ds->dev, 3031 "port %d failed to restore map-DA: %pe\n", 3032 port, ERR_PTR(err)); 3033 3034 err = mv88e6xxx_port_commit_pvid(chip, port); 3035 if (err) 3036 dev_err(ds->dev, 3037 "port %d failed to restore standalone pvid: %pe\n", 3038 port, ERR_PTR(err)); 3039 3040 mv88e6xxx_reg_unlock(chip); 3041 } 3042 3043 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3044 int tree_index, int sw_index, 3045 int port, struct dsa_bridge bridge, 3046 struct netlink_ext_ack *extack) 3047 { 3048 struct mv88e6xxx_chip *chip = ds->priv; 3049 int err; 3050 3051 if (tree_index != ds->dst->index) 3052 return 0; 3053 3054 mv88e6xxx_reg_lock(chip); 3055 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3056 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3057 mv88e6xxx_reg_unlock(chip); 3058 3059 return err; 3060 } 3061 3062 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3063 int tree_index, int sw_index, 3064 int port, struct dsa_bridge bridge) 3065 { 3066 struct mv88e6xxx_chip *chip = ds->priv; 3067 3068 if (tree_index != ds->dst->index) 3069 return; 3070 3071 mv88e6xxx_reg_lock(chip); 3072 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3073 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3074 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3075 mv88e6xxx_reg_unlock(chip); 3076 } 3077 3078 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3079 { 3080 if (chip->info->ops->reset) 3081 return chip->info->ops->reset(chip); 3082 3083 return 0; 3084 } 3085 3086 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3087 { 3088 struct gpio_desc *gpiod = chip->reset; 3089 3090 /* If there is a GPIO connected to the reset pin, toggle it */ 3091 if (gpiod) { 3092 /* If the switch has just been reset and not yet completed 3093 * loading EEPROM, the reset may interrupt the I2C transaction 3094 * mid-byte, causing the first EEPROM read after the reset 3095 * from the wrong location resulting in the switch booting 3096 * to wrong mode and inoperable. 3097 */ 3098 if (chip->info->ops->get_eeprom) 3099 mv88e6xxx_g2_eeprom_wait(chip); 3100 3101 gpiod_set_value_cansleep(gpiod, 1); 3102 usleep_range(10000, 20000); 3103 gpiod_set_value_cansleep(gpiod, 0); 3104 usleep_range(10000, 20000); 3105 3106 if (chip->info->ops->get_eeprom) 3107 mv88e6xxx_g2_eeprom_wait(chip); 3108 } 3109 } 3110 3111 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3112 { 3113 int i, err; 3114 3115 /* Set all ports to the Disabled state */ 3116 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3117 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3118 if (err) 3119 return err; 3120 } 3121 3122 /* Wait for transmit queues to drain, 3123 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3124 */ 3125 usleep_range(2000, 4000); 3126 3127 return 0; 3128 } 3129 3130 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3131 { 3132 int err; 3133 3134 err = mv88e6xxx_disable_ports(chip); 3135 if (err) 3136 return err; 3137 3138 mv88e6xxx_hardware_reset(chip); 3139 3140 return mv88e6xxx_software_reset(chip); 3141 } 3142 3143 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3144 enum mv88e6xxx_frame_mode frame, 3145 enum mv88e6xxx_egress_mode egress, u16 etype) 3146 { 3147 int err; 3148 3149 if (!chip->info->ops->port_set_frame_mode) 3150 return -EOPNOTSUPP; 3151 3152 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3153 if (err) 3154 return err; 3155 3156 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3157 if (err) 3158 return err; 3159 3160 if (chip->info->ops->port_set_ether_type) 3161 return chip->info->ops->port_set_ether_type(chip, port, etype); 3162 3163 return 0; 3164 } 3165 3166 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3167 { 3168 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3169 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3170 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3171 } 3172 3173 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3174 { 3175 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3176 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3177 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3178 } 3179 3180 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3181 { 3182 return mv88e6xxx_set_port_mode(chip, port, 3183 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3184 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3185 ETH_P_EDSA); 3186 } 3187 3188 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3189 { 3190 if (dsa_is_dsa_port(chip->ds, port)) 3191 return mv88e6xxx_set_port_mode_dsa(chip, port); 3192 3193 if (dsa_is_user_port(chip->ds, port)) 3194 return mv88e6xxx_set_port_mode_normal(chip, port); 3195 3196 /* Setup CPU port mode depending on its supported tag format */ 3197 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3198 return mv88e6xxx_set_port_mode_dsa(chip, port); 3199 3200 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3201 return mv88e6xxx_set_port_mode_edsa(chip, port); 3202 3203 return -EINVAL; 3204 } 3205 3206 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3207 { 3208 bool message = dsa_is_dsa_port(chip->ds, port); 3209 3210 return mv88e6xxx_port_set_message_port(chip, port, message); 3211 } 3212 3213 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3214 { 3215 int err; 3216 3217 if (chip->info->ops->port_set_ucast_flood) { 3218 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3219 if (err) 3220 return err; 3221 } 3222 if (chip->info->ops->port_set_mcast_flood) { 3223 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3224 if (err) 3225 return err; 3226 } 3227 3228 return 0; 3229 } 3230 3231 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3232 enum mv88e6xxx_egress_direction direction, 3233 int port) 3234 { 3235 int err; 3236 3237 if (!chip->info->ops->set_egress_port) 3238 return -EOPNOTSUPP; 3239 3240 err = chip->info->ops->set_egress_port(chip, direction, port); 3241 if (err) 3242 return err; 3243 3244 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3245 chip->ingress_dest_port = port; 3246 else 3247 chip->egress_dest_port = port; 3248 3249 return 0; 3250 } 3251 3252 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3253 { 3254 struct dsa_switch *ds = chip->ds; 3255 int upstream_port; 3256 int err; 3257 3258 upstream_port = dsa_upstream_port(ds, port); 3259 if (chip->info->ops->port_set_upstream_port) { 3260 err = chip->info->ops->port_set_upstream_port(chip, port, 3261 upstream_port); 3262 if (err) 3263 return err; 3264 } 3265 3266 if (port == upstream_port) { 3267 if (chip->info->ops->set_cpu_port) { 3268 err = chip->info->ops->set_cpu_port(chip, 3269 upstream_port); 3270 if (err) 3271 return err; 3272 } 3273 3274 err = mv88e6xxx_set_egress_port(chip, 3275 MV88E6XXX_EGRESS_DIR_INGRESS, 3276 upstream_port); 3277 if (err && err != -EOPNOTSUPP) 3278 return err; 3279 3280 err = mv88e6xxx_set_egress_port(chip, 3281 MV88E6XXX_EGRESS_DIR_EGRESS, 3282 upstream_port); 3283 if (err && err != -EOPNOTSUPP) 3284 return err; 3285 } 3286 3287 return 0; 3288 } 3289 3290 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3291 { 3292 struct device_node *phy_handle = NULL; 3293 struct dsa_switch *ds = chip->ds; 3294 struct dsa_port *dp; 3295 int tx_amp; 3296 int err; 3297 u16 reg; 3298 3299 chip->ports[port].chip = chip; 3300 chip->ports[port].port = port; 3301 3302 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3303 SPEED_UNFORCED, DUPLEX_UNFORCED, 3304 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3305 if (err) 3306 return err; 3307 3308 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3309 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3310 * tunneling, determine priority by looking at 802.1p and IP 3311 * priority fields (IP prio has precedence), and set STP state 3312 * to Forwarding. 3313 * 3314 * If this is the CPU link, use DSA or EDSA tagging depending 3315 * on which tagging mode was configured. 3316 * 3317 * If this is a link to another switch, use DSA tagging mode. 3318 * 3319 * If this is the upstream port for this switch, enable 3320 * forwarding of unknown unicasts and multicasts. 3321 */ 3322 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3323 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3324 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3325 * by a USER port to the CPU port to allow snooping. 3326 */ 3327 if (dsa_is_user_port(ds, port)) 3328 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3329 3330 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3331 if (err) 3332 return err; 3333 3334 err = mv88e6xxx_setup_port_mode(chip, port); 3335 if (err) 3336 return err; 3337 3338 err = mv88e6xxx_setup_egress_floods(chip, port); 3339 if (err) 3340 return err; 3341 3342 /* Port Control 2: don't force a good FCS, set the MTU size to 3343 * 10222 bytes, disable 802.1q tags checking, don't discard 3344 * tagged or untagged frames on this port, skip destination 3345 * address lookup on user ports, disable ARP mirroring and don't 3346 * send a copy of all transmitted/received frames on this port 3347 * to the CPU. 3348 */ 3349 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3350 if (err) 3351 return err; 3352 3353 err = mv88e6xxx_setup_upstream_port(chip, port); 3354 if (err) 3355 return err; 3356 3357 /* On chips that support it, set all downstream DSA ports' 3358 * VLAN policy to TRAP. In combination with loading 3359 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3360 * provides a better isolation barrier between standalone 3361 * ports, as the ATU is bypassed on any intermediate switches 3362 * between the incoming port and the CPU. 3363 */ 3364 if (dsa_is_downstream_port(ds, port) && 3365 chip->info->ops->port_set_policy) { 3366 err = chip->info->ops->port_set_policy(chip, port, 3367 MV88E6XXX_POLICY_MAPPING_VTU, 3368 MV88E6XXX_POLICY_ACTION_TRAP); 3369 if (err) 3370 return err; 3371 } 3372 3373 /* User ports start out in standalone mode and 802.1Q is 3374 * therefore disabled. On DSA ports, all valid VIDs are always 3375 * loaded in the VTU - therefore, enable 802.1Q in order to take 3376 * advantage of VLAN policy on chips that supports it. 3377 */ 3378 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3379 dsa_is_user_port(ds, port) ? 3380 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3381 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3382 if (err) 3383 return err; 3384 3385 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3386 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3387 * the first free FID. This will be used as the private PVID for 3388 * unbridged ports. Shared (DSA and CPU) ports must also be 3389 * members of this VID, in order to trap all frames assigned to 3390 * it to the CPU. 3391 */ 3392 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3393 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3394 false); 3395 if (err) 3396 return err; 3397 3398 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3399 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3400 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3401 * as the private PVID on ports under a VLAN-unaware bridge. 3402 * Shared (DSA and CPU) ports must also be members of it, to translate 3403 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3404 * relying on their port default FID. 3405 */ 3406 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3407 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3408 false); 3409 if (err) 3410 return err; 3411 3412 if (chip->info->ops->port_set_jumbo_size) { 3413 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3414 if (err) 3415 return err; 3416 } 3417 3418 /* Port Association Vector: disable automatic address learning 3419 * on all user ports since they start out in standalone 3420 * mode. When joining a bridge, learning will be configured to 3421 * match the bridge port settings. Enable learning on all 3422 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3423 * learning process. 3424 * 3425 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3426 * and RefreshLocked. I.e. setup standard automatic learning. 3427 */ 3428 if (dsa_is_user_port(ds, port)) 3429 reg = 0; 3430 else 3431 reg = 1 << port; 3432 3433 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3434 reg); 3435 if (err) 3436 return err; 3437 3438 /* Egress rate control 2: disable egress rate control. */ 3439 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3440 0x0000); 3441 if (err) 3442 return err; 3443 3444 if (chip->info->ops->port_pause_limit) { 3445 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3446 if (err) 3447 return err; 3448 } 3449 3450 if (chip->info->ops->port_disable_learn_limit) { 3451 err = chip->info->ops->port_disable_learn_limit(chip, port); 3452 if (err) 3453 return err; 3454 } 3455 3456 if (chip->info->ops->port_disable_pri_override) { 3457 err = chip->info->ops->port_disable_pri_override(chip, port); 3458 if (err) 3459 return err; 3460 } 3461 3462 if (chip->info->ops->port_tag_remap) { 3463 err = chip->info->ops->port_tag_remap(chip, port); 3464 if (err) 3465 return err; 3466 } 3467 3468 if (chip->info->ops->port_egress_rate_limiting) { 3469 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3470 if (err) 3471 return err; 3472 } 3473 3474 if (chip->info->ops->port_setup_message_port) { 3475 err = chip->info->ops->port_setup_message_port(chip, port); 3476 if (err) 3477 return err; 3478 } 3479 3480 if (chip->info->ops->serdes_set_tx_amplitude) { 3481 dp = dsa_to_port(ds, port); 3482 if (dp) 3483 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3484 3485 if (phy_handle && !of_property_read_u32(phy_handle, 3486 "tx-p2p-microvolt", 3487 &tx_amp)) 3488 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3489 port, tx_amp); 3490 if (phy_handle) { 3491 of_node_put(phy_handle); 3492 if (err) 3493 return err; 3494 } 3495 } 3496 3497 /* Port based VLAN map: give each port the same default address 3498 * database, and allow bidirectional communication between the 3499 * CPU and DSA port(s), and the other ports. 3500 */ 3501 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3502 if (err) 3503 return err; 3504 3505 err = mv88e6xxx_port_vlan_map(chip, port); 3506 if (err) 3507 return err; 3508 3509 /* Default VLAN ID and priority: don't set a default VLAN 3510 * ID, and set the default packet priority to zero. 3511 */ 3512 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3513 } 3514 3515 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3516 { 3517 struct mv88e6xxx_chip *chip = ds->priv; 3518 3519 if (chip->info->ops->port_set_jumbo_size) 3520 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3521 else if (chip->info->ops->set_max_frame_size) 3522 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3523 return ETH_DATA_LEN; 3524 } 3525 3526 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3527 { 3528 struct mv88e6xxx_chip *chip = ds->priv; 3529 int ret = 0; 3530 3531 /* For families where we don't know how to alter the MTU, 3532 * just accept any value up to ETH_DATA_LEN 3533 */ 3534 if (!chip->info->ops->port_set_jumbo_size && 3535 !chip->info->ops->set_max_frame_size) { 3536 if (new_mtu > ETH_DATA_LEN) 3537 return -EINVAL; 3538 3539 return 0; 3540 } 3541 3542 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3543 new_mtu += EDSA_HLEN; 3544 3545 mv88e6xxx_reg_lock(chip); 3546 if (chip->info->ops->port_set_jumbo_size) 3547 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3548 else if (chip->info->ops->set_max_frame_size) 3549 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3550 mv88e6xxx_reg_unlock(chip); 3551 3552 return ret; 3553 } 3554 3555 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3556 unsigned int ageing_time) 3557 { 3558 struct mv88e6xxx_chip *chip = ds->priv; 3559 int err; 3560 3561 mv88e6xxx_reg_lock(chip); 3562 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3563 mv88e6xxx_reg_unlock(chip); 3564 3565 return err; 3566 } 3567 3568 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3569 { 3570 int err; 3571 3572 /* Initialize the statistics unit */ 3573 if (chip->info->ops->stats_set_histogram) { 3574 err = chip->info->ops->stats_set_histogram(chip); 3575 if (err) 3576 return err; 3577 } 3578 3579 return mv88e6xxx_g1_stats_clear(chip); 3580 } 3581 3582 /* Check if the errata has already been applied. */ 3583 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3584 { 3585 int port; 3586 int err; 3587 u16 val; 3588 3589 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3590 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3591 if (err) { 3592 dev_err(chip->dev, 3593 "Error reading hidden register: %d\n", err); 3594 return false; 3595 } 3596 if (val != 0x01c0) 3597 return false; 3598 } 3599 3600 return true; 3601 } 3602 3603 /* The 6390 copper ports have an errata which require poking magic 3604 * values into undocumented hidden registers and then performing a 3605 * software reset. 3606 */ 3607 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3608 { 3609 int port; 3610 int err; 3611 3612 if (mv88e6390_setup_errata_applied(chip)) 3613 return 0; 3614 3615 /* Set the ports into blocking mode */ 3616 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3617 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3618 if (err) 3619 return err; 3620 } 3621 3622 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3623 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3624 if (err) 3625 return err; 3626 } 3627 3628 return mv88e6xxx_software_reset(chip); 3629 } 3630 3631 /* prod_id for switch families which do not have a PHY model number */ 3632 static const u16 family_prod_id_table[] = { 3633 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3634 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3635 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3636 }; 3637 3638 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3639 { 3640 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3641 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3642 u16 prod_id; 3643 u16 val; 3644 int err; 3645 3646 if (!chip->info->ops->phy_read) 3647 return -EOPNOTSUPP; 3648 3649 mv88e6xxx_reg_lock(chip); 3650 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3651 mv88e6xxx_reg_unlock(chip); 3652 3653 /* Some internal PHYs don't have a model number. */ 3654 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3655 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3656 prod_id = family_prod_id_table[chip->info->family]; 3657 if (prod_id) 3658 val |= prod_id >> 4; 3659 } 3660 3661 return err ? err : val; 3662 } 3663 3664 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3665 int reg) 3666 { 3667 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3668 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3669 u16 val; 3670 int err; 3671 3672 if (!chip->info->ops->phy_read_c45) 3673 return -ENODEV; 3674 3675 mv88e6xxx_reg_lock(chip); 3676 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3677 mv88e6xxx_reg_unlock(chip); 3678 3679 return err ? err : val; 3680 } 3681 3682 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3683 { 3684 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3685 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3686 int err; 3687 3688 if (!chip->info->ops->phy_write) 3689 return -EOPNOTSUPP; 3690 3691 mv88e6xxx_reg_lock(chip); 3692 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3693 mv88e6xxx_reg_unlock(chip); 3694 3695 return err; 3696 } 3697 3698 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3699 int reg, u16 val) 3700 { 3701 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3702 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3703 int err; 3704 3705 if (!chip->info->ops->phy_write_c45) 3706 return -EOPNOTSUPP; 3707 3708 mv88e6xxx_reg_lock(chip); 3709 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3710 mv88e6xxx_reg_unlock(chip); 3711 3712 return err; 3713 } 3714 3715 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3716 struct device_node *np, 3717 bool external) 3718 { 3719 static int index; 3720 struct mv88e6xxx_mdio_bus *mdio_bus; 3721 struct mii_bus *bus; 3722 int err; 3723 3724 if (external) { 3725 mv88e6xxx_reg_lock(chip); 3726 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3727 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3728 else 3729 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3730 mv88e6xxx_reg_unlock(chip); 3731 3732 if (err) 3733 return err; 3734 } 3735 3736 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3737 if (!bus) 3738 return -ENOMEM; 3739 3740 mdio_bus = bus->priv; 3741 mdio_bus->bus = bus; 3742 mdio_bus->chip = chip; 3743 INIT_LIST_HEAD(&mdio_bus->list); 3744 mdio_bus->external = external; 3745 3746 if (np) { 3747 bus->name = np->full_name; 3748 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3749 } else { 3750 bus->name = "mv88e6xxx SMI"; 3751 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3752 } 3753 3754 bus->read = mv88e6xxx_mdio_read; 3755 bus->write = mv88e6xxx_mdio_write; 3756 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3757 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3758 bus->parent = chip->dev; 3759 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3760 mv88e6xxx_num_ports(chip) - 1, 3761 chip->info->phy_base_addr); 3762 3763 if (!external) { 3764 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3765 if (err) 3766 goto out; 3767 } 3768 3769 err = of_mdiobus_register(bus, np); 3770 if (err) { 3771 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3772 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3773 goto out; 3774 } 3775 3776 if (external) 3777 list_add_tail(&mdio_bus->list, &chip->mdios); 3778 else 3779 list_add(&mdio_bus->list, &chip->mdios); 3780 3781 return 0; 3782 3783 out: 3784 mdiobus_free(bus); 3785 return err; 3786 } 3787 3788 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3789 3790 { 3791 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3792 struct mii_bus *bus; 3793 3794 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3795 bus = mdio_bus->bus; 3796 3797 if (!mdio_bus->external) 3798 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3799 3800 mdiobus_unregister(bus); 3801 mdiobus_free(bus); 3802 } 3803 } 3804 3805 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3806 { 3807 struct device_node *np = chip->dev->of_node; 3808 struct device_node *child; 3809 int err; 3810 3811 /* Always register one mdio bus for the internal/default mdio 3812 * bus. This maybe represented in the device tree, but is 3813 * optional. 3814 */ 3815 child = of_get_child_by_name(np, "mdio"); 3816 err = mv88e6xxx_mdio_register(chip, child, false); 3817 of_node_put(child); 3818 if (err) 3819 return err; 3820 3821 /* Walk the device tree, and see if there are any other nodes 3822 * which say they are compatible with the external mdio 3823 * bus. 3824 */ 3825 for_each_available_child_of_node(np, child) { 3826 if (of_device_is_compatible( 3827 child, "marvell,mv88e6xxx-mdio-external")) { 3828 err = mv88e6xxx_mdio_register(chip, child, true); 3829 if (err) { 3830 mv88e6xxx_mdios_unregister(chip); 3831 of_node_put(child); 3832 return err; 3833 } 3834 } 3835 } 3836 3837 return 0; 3838 } 3839 3840 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3841 { 3842 struct mv88e6xxx_chip *chip = ds->priv; 3843 3844 mv88e6xxx_teardown_devlink_params(ds); 3845 dsa_devlink_resources_unregister(ds); 3846 mv88e6xxx_teardown_devlink_regions_global(ds); 3847 mv88e6xxx_mdios_unregister(chip); 3848 } 3849 3850 static int mv88e6xxx_setup(struct dsa_switch *ds) 3851 { 3852 struct mv88e6xxx_chip *chip = ds->priv; 3853 u8 cmode; 3854 int err; 3855 int i; 3856 3857 err = mv88e6xxx_mdios_register(chip); 3858 if (err) 3859 return err; 3860 3861 chip->ds = ds; 3862 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3863 3864 /* Since virtual bridges are mapped in the PVT, the number we support 3865 * depends on the physical switch topology. We need to let DSA figure 3866 * that out and therefore we cannot set this at dsa_register_switch() 3867 * time. 3868 */ 3869 if (mv88e6xxx_has_pvt(chip)) 3870 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3871 ds->dst->last_switch - 1; 3872 3873 mv88e6xxx_reg_lock(chip); 3874 3875 if (chip->info->ops->setup_errata) { 3876 err = chip->info->ops->setup_errata(chip); 3877 if (err) 3878 goto unlock; 3879 } 3880 3881 /* Cache the cmode of each port. */ 3882 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3883 if (chip->info->ops->port_get_cmode) { 3884 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3885 if (err) 3886 goto unlock; 3887 3888 chip->ports[i].cmode = cmode; 3889 } 3890 } 3891 3892 err = mv88e6xxx_vtu_setup(chip); 3893 if (err) 3894 goto unlock; 3895 3896 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3897 * VTU, thereby also flushing the STU). 3898 */ 3899 err = mv88e6xxx_stu_setup(chip); 3900 if (err) 3901 goto unlock; 3902 3903 /* Setup Switch Port Registers */ 3904 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3905 if (dsa_is_unused_port(ds, i)) 3906 continue; 3907 3908 /* Prevent the use of an invalid port. */ 3909 if (mv88e6xxx_is_invalid_port(chip, i)) { 3910 dev_err(chip->dev, "port %d is invalid\n", i); 3911 err = -EINVAL; 3912 goto unlock; 3913 } 3914 3915 err = mv88e6xxx_setup_port(chip, i); 3916 if (err) 3917 goto unlock; 3918 } 3919 3920 err = mv88e6xxx_irl_setup(chip); 3921 if (err) 3922 goto unlock; 3923 3924 err = mv88e6xxx_mac_setup(chip); 3925 if (err) 3926 goto unlock; 3927 3928 err = mv88e6xxx_phy_setup(chip); 3929 if (err) 3930 goto unlock; 3931 3932 err = mv88e6xxx_pvt_setup(chip); 3933 if (err) 3934 goto unlock; 3935 3936 err = mv88e6xxx_atu_setup(chip); 3937 if (err) 3938 goto unlock; 3939 3940 err = mv88e6xxx_broadcast_setup(chip, 0); 3941 if (err) 3942 goto unlock; 3943 3944 err = mv88e6xxx_pot_setup(chip); 3945 if (err) 3946 goto unlock; 3947 3948 err = mv88e6xxx_rmu_setup(chip); 3949 if (err) 3950 goto unlock; 3951 3952 err = mv88e6xxx_rsvd2cpu_setup(chip); 3953 if (err) 3954 goto unlock; 3955 3956 err = mv88e6xxx_trunk_setup(chip); 3957 if (err) 3958 goto unlock; 3959 3960 err = mv88e6xxx_devmap_setup(chip); 3961 if (err) 3962 goto unlock; 3963 3964 err = mv88e6xxx_pri_setup(chip); 3965 if (err) 3966 goto unlock; 3967 3968 /* Setup PTP Hardware Clock and timestamping */ 3969 if (chip->info->ptp_support) { 3970 err = mv88e6xxx_ptp_setup(chip); 3971 if (err) 3972 goto unlock; 3973 3974 err = mv88e6xxx_hwtstamp_setup(chip); 3975 if (err) 3976 goto unlock; 3977 } 3978 3979 err = mv88e6xxx_stats_setup(chip); 3980 if (err) 3981 goto unlock; 3982 3983 unlock: 3984 mv88e6xxx_reg_unlock(chip); 3985 3986 if (err) 3987 goto out_mdios; 3988 3989 /* Have to be called without holding the register lock, since 3990 * they take the devlink lock, and we later take the locks in 3991 * the reverse order when getting/setting parameters or 3992 * resource occupancy. 3993 */ 3994 err = mv88e6xxx_setup_devlink_resources(ds); 3995 if (err) 3996 goto out_mdios; 3997 3998 err = mv88e6xxx_setup_devlink_params(ds); 3999 if (err) 4000 goto out_resources; 4001 4002 err = mv88e6xxx_setup_devlink_regions_global(ds); 4003 if (err) 4004 goto out_params; 4005 4006 return 0; 4007 4008 out_params: 4009 mv88e6xxx_teardown_devlink_params(ds); 4010 out_resources: 4011 dsa_devlink_resources_unregister(ds); 4012 out_mdios: 4013 mv88e6xxx_mdios_unregister(chip); 4014 4015 return err; 4016 } 4017 4018 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4019 { 4020 struct mv88e6xxx_chip *chip = ds->priv; 4021 int err; 4022 4023 if (chip->info->ops->pcs_ops && 4024 chip->info->ops->pcs_ops->pcs_init) { 4025 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4026 if (err) 4027 return err; 4028 } 4029 4030 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4031 } 4032 4033 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4034 { 4035 struct mv88e6xxx_chip *chip = ds->priv; 4036 4037 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4038 4039 if (chip->info->ops->pcs_ops && 4040 chip->info->ops->pcs_ops->pcs_teardown) 4041 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4042 } 4043 4044 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4045 { 4046 struct mv88e6xxx_chip *chip = ds->priv; 4047 4048 return chip->eeprom_len; 4049 } 4050 4051 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4052 struct ethtool_eeprom *eeprom, u8 *data) 4053 { 4054 struct mv88e6xxx_chip *chip = ds->priv; 4055 int err; 4056 4057 if (!chip->info->ops->get_eeprom) 4058 return -EOPNOTSUPP; 4059 4060 mv88e6xxx_reg_lock(chip); 4061 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4062 mv88e6xxx_reg_unlock(chip); 4063 4064 if (err) 4065 return err; 4066 4067 eeprom->magic = 0xc3ec4951; 4068 4069 return 0; 4070 } 4071 4072 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4073 struct ethtool_eeprom *eeprom, u8 *data) 4074 { 4075 struct mv88e6xxx_chip *chip = ds->priv; 4076 int err; 4077 4078 if (!chip->info->ops->set_eeprom) 4079 return -EOPNOTSUPP; 4080 4081 if (eeprom->magic != 0xc3ec4951) 4082 return -EINVAL; 4083 4084 mv88e6xxx_reg_lock(chip); 4085 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4086 mv88e6xxx_reg_unlock(chip); 4087 4088 return err; 4089 } 4090 4091 static const struct mv88e6xxx_ops mv88e6085_ops = { 4092 /* MV88E6XXX_FAMILY_6097 */ 4093 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4094 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4095 .irl_init_all = mv88e6352_g2_irl_init_all, 4096 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4097 .phy_read = mv88e6185_phy_ppu_read, 4098 .phy_write = mv88e6185_phy_ppu_write, 4099 .port_set_link = mv88e6xxx_port_set_link, 4100 .port_sync_link = mv88e6xxx_port_sync_link, 4101 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4102 .port_tag_remap = mv88e6095_port_tag_remap, 4103 .port_set_policy = mv88e6352_port_set_policy, 4104 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4105 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4106 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4107 .port_set_ether_type = mv88e6351_port_set_ether_type, 4108 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4109 .port_pause_limit = mv88e6097_port_pause_limit, 4110 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4111 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4112 .port_get_cmode = mv88e6185_port_get_cmode, 4113 .port_setup_message_port = mv88e6xxx_setup_message_port, 4114 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4115 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4116 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4117 .stats_get_strings = mv88e6095_stats_get_strings, 4118 .stats_get_stat = mv88e6095_stats_get_stat, 4119 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4120 .set_egress_port = mv88e6095_g1_set_egress_port, 4121 .watchdog_ops = &mv88e6097_watchdog_ops, 4122 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4123 .pot_clear = mv88e6xxx_g2_pot_clear, 4124 .ppu_enable = mv88e6185_g1_ppu_enable, 4125 .ppu_disable = mv88e6185_g1_ppu_disable, 4126 .reset = mv88e6185_g1_reset, 4127 .rmu_disable = mv88e6085_g1_rmu_disable, 4128 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4129 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4130 .stu_getnext = mv88e6352_g1_stu_getnext, 4131 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4132 .phylink_get_caps = mv88e6185_phylink_get_caps, 4133 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4134 }; 4135 4136 static const struct mv88e6xxx_ops mv88e6095_ops = { 4137 /* MV88E6XXX_FAMILY_6095 */ 4138 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4139 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4140 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4141 .phy_read = mv88e6185_phy_ppu_read, 4142 .phy_write = mv88e6185_phy_ppu_write, 4143 .port_set_link = mv88e6xxx_port_set_link, 4144 .port_sync_link = mv88e6185_port_sync_link, 4145 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4146 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4147 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4148 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4149 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4150 .port_get_cmode = mv88e6185_port_get_cmode, 4151 .port_setup_message_port = mv88e6xxx_setup_message_port, 4152 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4153 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4154 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4155 .stats_get_strings = mv88e6095_stats_get_strings, 4156 .stats_get_stat = mv88e6095_stats_get_stat, 4157 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4158 .ppu_enable = mv88e6185_g1_ppu_enable, 4159 .ppu_disable = mv88e6185_g1_ppu_disable, 4160 .reset = mv88e6185_g1_reset, 4161 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4162 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4163 .phylink_get_caps = mv88e6095_phylink_get_caps, 4164 .pcs_ops = &mv88e6185_pcs_ops, 4165 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4166 }; 4167 4168 static const struct mv88e6xxx_ops mv88e6097_ops = { 4169 /* MV88E6XXX_FAMILY_6097 */ 4170 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4171 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4172 .irl_init_all = mv88e6352_g2_irl_init_all, 4173 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4174 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4175 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4176 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4177 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4178 .port_set_link = mv88e6xxx_port_set_link, 4179 .port_sync_link = mv88e6185_port_sync_link, 4180 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4181 .port_tag_remap = mv88e6095_port_tag_remap, 4182 .port_set_policy = mv88e6352_port_set_policy, 4183 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4184 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4185 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4186 .port_set_ether_type = mv88e6351_port_set_ether_type, 4187 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4188 .port_pause_limit = mv88e6097_port_pause_limit, 4189 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4190 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4191 .port_get_cmode = mv88e6185_port_get_cmode, 4192 .port_setup_message_port = mv88e6xxx_setup_message_port, 4193 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4194 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4195 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4196 .stats_get_strings = mv88e6095_stats_get_strings, 4197 .stats_get_stat = mv88e6095_stats_get_stat, 4198 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4199 .set_egress_port = mv88e6095_g1_set_egress_port, 4200 .watchdog_ops = &mv88e6097_watchdog_ops, 4201 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4202 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4203 .pot_clear = mv88e6xxx_g2_pot_clear, 4204 .reset = mv88e6352_g1_reset, 4205 .rmu_disable = mv88e6085_g1_rmu_disable, 4206 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4207 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4208 .phylink_get_caps = mv88e6095_phylink_get_caps, 4209 .pcs_ops = &mv88e6185_pcs_ops, 4210 .stu_getnext = mv88e6352_g1_stu_getnext, 4211 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4212 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4213 }; 4214 4215 static const struct mv88e6xxx_ops mv88e6123_ops = { 4216 /* MV88E6XXX_FAMILY_6165 */ 4217 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4218 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4219 .irl_init_all = mv88e6352_g2_irl_init_all, 4220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4221 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4222 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4223 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4224 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4225 .port_set_link = mv88e6xxx_port_set_link, 4226 .port_sync_link = mv88e6xxx_port_sync_link, 4227 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4228 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4229 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4230 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4231 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4232 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4233 .port_get_cmode = mv88e6185_port_get_cmode, 4234 .port_setup_message_port = mv88e6xxx_setup_message_port, 4235 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4236 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4237 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4238 .stats_get_strings = mv88e6095_stats_get_strings, 4239 .stats_get_stat = mv88e6095_stats_get_stat, 4240 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4241 .set_egress_port = mv88e6095_g1_set_egress_port, 4242 .watchdog_ops = &mv88e6097_watchdog_ops, 4243 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4244 .pot_clear = mv88e6xxx_g2_pot_clear, 4245 .reset = mv88e6352_g1_reset, 4246 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4247 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4248 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4249 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4250 .stu_getnext = mv88e6352_g1_stu_getnext, 4251 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4252 .phylink_get_caps = mv88e6185_phylink_get_caps, 4253 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4254 }; 4255 4256 static const struct mv88e6xxx_ops mv88e6131_ops = { 4257 /* MV88E6XXX_FAMILY_6185 */ 4258 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4259 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4260 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4261 .phy_read = mv88e6185_phy_ppu_read, 4262 .phy_write = mv88e6185_phy_ppu_write, 4263 .port_set_link = mv88e6xxx_port_set_link, 4264 .port_sync_link = mv88e6xxx_port_sync_link, 4265 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4266 .port_tag_remap = mv88e6095_port_tag_remap, 4267 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4268 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4269 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4270 .port_set_ether_type = mv88e6351_port_set_ether_type, 4271 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4272 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4273 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4274 .port_pause_limit = mv88e6097_port_pause_limit, 4275 .port_set_pause = mv88e6185_port_set_pause, 4276 .port_get_cmode = mv88e6185_port_get_cmode, 4277 .port_setup_message_port = mv88e6xxx_setup_message_port, 4278 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4279 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4280 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4281 .stats_get_strings = mv88e6095_stats_get_strings, 4282 .stats_get_stat = mv88e6095_stats_get_stat, 4283 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4284 .set_egress_port = mv88e6095_g1_set_egress_port, 4285 .watchdog_ops = &mv88e6097_watchdog_ops, 4286 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4287 .ppu_enable = mv88e6185_g1_ppu_enable, 4288 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4289 .ppu_disable = mv88e6185_g1_ppu_disable, 4290 .reset = mv88e6185_g1_reset, 4291 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4292 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4293 .phylink_get_caps = mv88e6185_phylink_get_caps, 4294 }; 4295 4296 static const struct mv88e6xxx_ops mv88e6141_ops = { 4297 /* MV88E6XXX_FAMILY_6341 */ 4298 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4299 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4300 .irl_init_all = mv88e6352_g2_irl_init_all, 4301 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4302 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4304 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4305 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4306 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4307 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4308 .port_set_link = mv88e6xxx_port_set_link, 4309 .port_sync_link = mv88e6xxx_port_sync_link, 4310 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4311 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4312 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4313 .port_tag_remap = mv88e6095_port_tag_remap, 4314 .port_set_policy = mv88e6352_port_set_policy, 4315 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4316 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4317 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4318 .port_set_ether_type = mv88e6351_port_set_ether_type, 4319 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4320 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4321 .port_pause_limit = mv88e6097_port_pause_limit, 4322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4324 .port_get_cmode = mv88e6352_port_get_cmode, 4325 .port_set_cmode = mv88e6341_port_set_cmode, 4326 .port_setup_message_port = mv88e6xxx_setup_message_port, 4327 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4328 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4329 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4330 .stats_get_strings = mv88e6320_stats_get_strings, 4331 .stats_get_stat = mv88e6390_stats_get_stat, 4332 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4333 .set_egress_port = mv88e6390_g1_set_egress_port, 4334 .watchdog_ops = &mv88e6390_watchdog_ops, 4335 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4336 .pot_clear = mv88e6xxx_g2_pot_clear, 4337 .reset = mv88e6352_g1_reset, 4338 .rmu_disable = mv88e6390_g1_rmu_disable, 4339 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4340 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4341 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4342 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4343 .stu_getnext = mv88e6352_g1_stu_getnext, 4344 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4345 .serdes_get_lane = mv88e6341_serdes_get_lane, 4346 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4347 .gpio_ops = &mv88e6352_gpio_ops, 4348 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4349 .serdes_get_strings = mv88e6390_serdes_get_strings, 4350 .serdes_get_stats = mv88e6390_serdes_get_stats, 4351 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4352 .serdes_get_regs = mv88e6390_serdes_get_regs, 4353 .phylink_get_caps = mv88e6341_phylink_get_caps, 4354 .pcs_ops = &mv88e6390_pcs_ops, 4355 }; 4356 4357 static const struct mv88e6xxx_ops mv88e6161_ops = { 4358 /* MV88E6XXX_FAMILY_6165 */ 4359 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4360 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4361 .irl_init_all = mv88e6352_g2_irl_init_all, 4362 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4363 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4364 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4365 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4366 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4367 .port_set_link = mv88e6xxx_port_set_link, 4368 .port_sync_link = mv88e6xxx_port_sync_link, 4369 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4370 .port_tag_remap = mv88e6095_port_tag_remap, 4371 .port_set_policy = mv88e6352_port_set_policy, 4372 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4373 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4374 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4375 .port_set_ether_type = mv88e6351_port_set_ether_type, 4376 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4377 .port_pause_limit = mv88e6097_port_pause_limit, 4378 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4379 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4380 .port_get_cmode = mv88e6185_port_get_cmode, 4381 .port_setup_message_port = mv88e6xxx_setup_message_port, 4382 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4383 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4384 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4385 .stats_get_strings = mv88e6095_stats_get_strings, 4386 .stats_get_stat = mv88e6095_stats_get_stat, 4387 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4388 .set_egress_port = mv88e6095_g1_set_egress_port, 4389 .watchdog_ops = &mv88e6097_watchdog_ops, 4390 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4391 .pot_clear = mv88e6xxx_g2_pot_clear, 4392 .reset = mv88e6352_g1_reset, 4393 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4394 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4395 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4396 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4397 .stu_getnext = mv88e6352_g1_stu_getnext, 4398 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4399 .avb_ops = &mv88e6165_avb_ops, 4400 .ptp_ops = &mv88e6165_ptp_ops, 4401 .phylink_get_caps = mv88e6185_phylink_get_caps, 4402 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4403 }; 4404 4405 static const struct mv88e6xxx_ops mv88e6165_ops = { 4406 /* MV88E6XXX_FAMILY_6165 */ 4407 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4408 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4409 .irl_init_all = mv88e6352_g2_irl_init_all, 4410 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4411 .phy_read = mv88e6165_phy_read, 4412 .phy_write = mv88e6165_phy_write, 4413 .port_set_link = mv88e6xxx_port_set_link, 4414 .port_sync_link = mv88e6xxx_port_sync_link, 4415 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4416 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4417 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4418 .port_get_cmode = mv88e6185_port_get_cmode, 4419 .port_setup_message_port = mv88e6xxx_setup_message_port, 4420 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4421 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4422 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4423 .stats_get_strings = mv88e6095_stats_get_strings, 4424 .stats_get_stat = mv88e6095_stats_get_stat, 4425 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4426 .set_egress_port = mv88e6095_g1_set_egress_port, 4427 .watchdog_ops = &mv88e6097_watchdog_ops, 4428 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4429 .pot_clear = mv88e6xxx_g2_pot_clear, 4430 .reset = mv88e6352_g1_reset, 4431 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4432 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4433 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4434 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4435 .stu_getnext = mv88e6352_g1_stu_getnext, 4436 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4437 .avb_ops = &mv88e6165_avb_ops, 4438 .ptp_ops = &mv88e6165_ptp_ops, 4439 .phylink_get_caps = mv88e6185_phylink_get_caps, 4440 }; 4441 4442 static const struct mv88e6xxx_ops mv88e6171_ops = { 4443 /* MV88E6XXX_FAMILY_6351 */ 4444 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4445 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4446 .irl_init_all = mv88e6352_g2_irl_init_all, 4447 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4448 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4449 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4450 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4451 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4452 .port_set_link = mv88e6xxx_port_set_link, 4453 .port_sync_link = mv88e6xxx_port_sync_link, 4454 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4455 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4456 .port_tag_remap = mv88e6095_port_tag_remap, 4457 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4458 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4459 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4460 .port_set_ether_type = mv88e6351_port_set_ether_type, 4461 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4462 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4463 .port_pause_limit = mv88e6097_port_pause_limit, 4464 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4465 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4466 .port_get_cmode = mv88e6352_port_get_cmode, 4467 .port_setup_message_port = mv88e6xxx_setup_message_port, 4468 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4469 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4470 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4471 .stats_get_strings = mv88e6095_stats_get_strings, 4472 .stats_get_stat = mv88e6095_stats_get_stat, 4473 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4474 .set_egress_port = mv88e6095_g1_set_egress_port, 4475 .watchdog_ops = &mv88e6097_watchdog_ops, 4476 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4477 .pot_clear = mv88e6xxx_g2_pot_clear, 4478 .reset = mv88e6352_g1_reset, 4479 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4480 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4481 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4482 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4483 .stu_getnext = mv88e6352_g1_stu_getnext, 4484 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4485 .phylink_get_caps = mv88e6351_phylink_get_caps, 4486 }; 4487 4488 static const struct mv88e6xxx_ops mv88e6172_ops = { 4489 /* MV88E6XXX_FAMILY_6352 */ 4490 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4491 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4492 .irl_init_all = mv88e6352_g2_irl_init_all, 4493 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4494 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4495 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4496 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4497 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4498 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4499 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4500 .port_set_link = mv88e6xxx_port_set_link, 4501 .port_sync_link = mv88e6xxx_port_sync_link, 4502 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4503 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4504 .port_tag_remap = mv88e6095_port_tag_remap, 4505 .port_set_policy = mv88e6352_port_set_policy, 4506 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4507 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4508 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4509 .port_set_ether_type = mv88e6351_port_set_ether_type, 4510 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4511 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4512 .port_pause_limit = mv88e6097_port_pause_limit, 4513 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4514 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4515 .port_get_cmode = mv88e6352_port_get_cmode, 4516 .port_setup_message_port = mv88e6xxx_setup_message_port, 4517 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4518 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4519 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4520 .stats_get_strings = mv88e6095_stats_get_strings, 4521 .stats_get_stat = mv88e6095_stats_get_stat, 4522 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4523 .set_egress_port = mv88e6095_g1_set_egress_port, 4524 .watchdog_ops = &mv88e6097_watchdog_ops, 4525 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4526 .pot_clear = mv88e6xxx_g2_pot_clear, 4527 .reset = mv88e6352_g1_reset, 4528 .rmu_disable = mv88e6352_g1_rmu_disable, 4529 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4530 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4531 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4532 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4533 .stu_getnext = mv88e6352_g1_stu_getnext, 4534 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4535 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4536 .serdes_get_regs = mv88e6352_serdes_get_regs, 4537 .gpio_ops = &mv88e6352_gpio_ops, 4538 .phylink_get_caps = mv88e6352_phylink_get_caps, 4539 .pcs_ops = &mv88e6352_pcs_ops, 4540 }; 4541 4542 static const struct mv88e6xxx_ops mv88e6175_ops = { 4543 /* MV88E6XXX_FAMILY_6351 */ 4544 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4545 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4546 .irl_init_all = mv88e6352_g2_irl_init_all, 4547 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4548 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4549 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4550 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4551 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4552 .port_set_link = mv88e6xxx_port_set_link, 4553 .port_sync_link = mv88e6xxx_port_sync_link, 4554 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4555 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4556 .port_tag_remap = mv88e6095_port_tag_remap, 4557 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4558 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4559 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4560 .port_set_ether_type = mv88e6351_port_set_ether_type, 4561 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4562 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4563 .port_pause_limit = mv88e6097_port_pause_limit, 4564 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4565 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4566 .port_get_cmode = mv88e6352_port_get_cmode, 4567 .port_setup_message_port = mv88e6xxx_setup_message_port, 4568 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4569 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4570 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4571 .stats_get_strings = mv88e6095_stats_get_strings, 4572 .stats_get_stat = mv88e6095_stats_get_stat, 4573 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4574 .set_egress_port = mv88e6095_g1_set_egress_port, 4575 .watchdog_ops = &mv88e6097_watchdog_ops, 4576 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4577 .pot_clear = mv88e6xxx_g2_pot_clear, 4578 .reset = mv88e6352_g1_reset, 4579 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4580 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4581 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4582 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4583 .stu_getnext = mv88e6352_g1_stu_getnext, 4584 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4585 .phylink_get_caps = mv88e6351_phylink_get_caps, 4586 }; 4587 4588 static const struct mv88e6xxx_ops mv88e6176_ops = { 4589 /* MV88E6XXX_FAMILY_6352 */ 4590 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4591 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4592 .irl_init_all = mv88e6352_g2_irl_init_all, 4593 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4594 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4595 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4596 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4597 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4598 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4599 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4600 .port_set_link = mv88e6xxx_port_set_link, 4601 .port_sync_link = mv88e6xxx_port_sync_link, 4602 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4603 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4604 .port_tag_remap = mv88e6095_port_tag_remap, 4605 .port_set_policy = mv88e6352_port_set_policy, 4606 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4607 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4608 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4609 .port_set_ether_type = mv88e6351_port_set_ether_type, 4610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4611 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4612 .port_pause_limit = mv88e6097_port_pause_limit, 4613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4615 .port_get_cmode = mv88e6352_port_get_cmode, 4616 .port_setup_message_port = mv88e6xxx_setup_message_port, 4617 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4618 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4619 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4620 .stats_get_strings = mv88e6095_stats_get_strings, 4621 .stats_get_stat = mv88e6095_stats_get_stat, 4622 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4623 .set_egress_port = mv88e6095_g1_set_egress_port, 4624 .watchdog_ops = &mv88e6097_watchdog_ops, 4625 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4626 .pot_clear = mv88e6xxx_g2_pot_clear, 4627 .reset = mv88e6352_g1_reset, 4628 .rmu_disable = mv88e6352_g1_rmu_disable, 4629 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4630 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4631 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4632 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4633 .stu_getnext = mv88e6352_g1_stu_getnext, 4634 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4635 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4636 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4637 .serdes_get_regs = mv88e6352_serdes_get_regs, 4638 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4639 .gpio_ops = &mv88e6352_gpio_ops, 4640 .phylink_get_caps = mv88e6352_phylink_get_caps, 4641 .pcs_ops = &mv88e6352_pcs_ops, 4642 }; 4643 4644 static const struct mv88e6xxx_ops mv88e6185_ops = { 4645 /* MV88E6XXX_FAMILY_6185 */ 4646 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4647 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4648 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4649 .phy_read = mv88e6185_phy_ppu_read, 4650 .phy_write = mv88e6185_phy_ppu_write, 4651 .port_set_link = mv88e6xxx_port_set_link, 4652 .port_sync_link = mv88e6185_port_sync_link, 4653 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4654 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4655 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4656 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4657 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4658 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4659 .port_set_pause = mv88e6185_port_set_pause, 4660 .port_get_cmode = mv88e6185_port_get_cmode, 4661 .port_setup_message_port = mv88e6xxx_setup_message_port, 4662 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4663 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4664 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4665 .stats_get_strings = mv88e6095_stats_get_strings, 4666 .stats_get_stat = mv88e6095_stats_get_stat, 4667 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4668 .set_egress_port = mv88e6095_g1_set_egress_port, 4669 .watchdog_ops = &mv88e6097_watchdog_ops, 4670 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4671 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4672 .ppu_enable = mv88e6185_g1_ppu_enable, 4673 .ppu_disable = mv88e6185_g1_ppu_disable, 4674 .reset = mv88e6185_g1_reset, 4675 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4676 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4677 .phylink_get_caps = mv88e6185_phylink_get_caps, 4678 .pcs_ops = &mv88e6185_pcs_ops, 4679 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4680 }; 4681 4682 static const struct mv88e6xxx_ops mv88e6190_ops = { 4683 /* MV88E6XXX_FAMILY_6390 */ 4684 .setup_errata = mv88e6390_setup_errata, 4685 .irl_init_all = mv88e6390_g2_irl_init_all, 4686 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4687 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4688 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4689 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4690 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4691 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4692 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4693 .port_set_link = mv88e6xxx_port_set_link, 4694 .port_sync_link = mv88e6xxx_port_sync_link, 4695 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4696 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4697 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4698 .port_tag_remap = mv88e6390_port_tag_remap, 4699 .port_set_policy = mv88e6352_port_set_policy, 4700 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4701 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4702 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4703 .port_set_ether_type = mv88e6351_port_set_ether_type, 4704 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4705 .port_pause_limit = mv88e6390_port_pause_limit, 4706 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4707 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4708 .port_get_cmode = mv88e6352_port_get_cmode, 4709 .port_set_cmode = mv88e6390_port_set_cmode, 4710 .port_setup_message_port = mv88e6xxx_setup_message_port, 4711 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4712 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4713 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4714 .stats_get_strings = mv88e6320_stats_get_strings, 4715 .stats_get_stat = mv88e6390_stats_get_stat, 4716 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4717 .set_egress_port = mv88e6390_g1_set_egress_port, 4718 .watchdog_ops = &mv88e6390_watchdog_ops, 4719 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4720 .pot_clear = mv88e6xxx_g2_pot_clear, 4721 .reset = mv88e6352_g1_reset, 4722 .rmu_disable = mv88e6390_g1_rmu_disable, 4723 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4724 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4725 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4726 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4727 .stu_getnext = mv88e6390_g1_stu_getnext, 4728 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4729 .serdes_get_lane = mv88e6390_serdes_get_lane, 4730 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4731 .serdes_get_strings = mv88e6390_serdes_get_strings, 4732 .serdes_get_stats = mv88e6390_serdes_get_stats, 4733 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4734 .serdes_get_regs = mv88e6390_serdes_get_regs, 4735 .gpio_ops = &mv88e6352_gpio_ops, 4736 .phylink_get_caps = mv88e6390_phylink_get_caps, 4737 .pcs_ops = &mv88e6390_pcs_ops, 4738 }; 4739 4740 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4741 /* MV88E6XXX_FAMILY_6390 */ 4742 .setup_errata = mv88e6390_setup_errata, 4743 .irl_init_all = mv88e6390_g2_irl_init_all, 4744 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4745 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4746 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4747 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4748 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4749 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4750 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4751 .port_set_link = mv88e6xxx_port_set_link, 4752 .port_sync_link = mv88e6xxx_port_sync_link, 4753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4754 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4755 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4756 .port_tag_remap = mv88e6390_port_tag_remap, 4757 .port_set_policy = mv88e6352_port_set_policy, 4758 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4759 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4760 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4761 .port_set_ether_type = mv88e6351_port_set_ether_type, 4762 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4763 .port_pause_limit = mv88e6390_port_pause_limit, 4764 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4765 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4766 .port_get_cmode = mv88e6352_port_get_cmode, 4767 .port_set_cmode = mv88e6390x_port_set_cmode, 4768 .port_setup_message_port = mv88e6xxx_setup_message_port, 4769 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4770 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4771 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4772 .stats_get_strings = mv88e6320_stats_get_strings, 4773 .stats_get_stat = mv88e6390_stats_get_stat, 4774 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4775 .set_egress_port = mv88e6390_g1_set_egress_port, 4776 .watchdog_ops = &mv88e6390_watchdog_ops, 4777 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4778 .pot_clear = mv88e6xxx_g2_pot_clear, 4779 .reset = mv88e6352_g1_reset, 4780 .rmu_disable = mv88e6390_g1_rmu_disable, 4781 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4782 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4783 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4784 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4785 .stu_getnext = mv88e6390_g1_stu_getnext, 4786 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4787 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4788 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4789 .serdes_get_strings = mv88e6390_serdes_get_strings, 4790 .serdes_get_stats = mv88e6390_serdes_get_stats, 4791 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4792 .serdes_get_regs = mv88e6390_serdes_get_regs, 4793 .gpio_ops = &mv88e6352_gpio_ops, 4794 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4795 .pcs_ops = &mv88e6390_pcs_ops, 4796 }; 4797 4798 static const struct mv88e6xxx_ops mv88e6191_ops = { 4799 /* MV88E6XXX_FAMILY_6390 */ 4800 .setup_errata = mv88e6390_setup_errata, 4801 .irl_init_all = mv88e6390_g2_irl_init_all, 4802 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4803 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4804 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4805 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4806 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4807 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4808 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4809 .port_set_link = mv88e6xxx_port_set_link, 4810 .port_sync_link = mv88e6xxx_port_sync_link, 4811 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4812 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4813 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4814 .port_tag_remap = mv88e6390_port_tag_remap, 4815 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4816 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4817 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4818 .port_set_ether_type = mv88e6351_port_set_ether_type, 4819 .port_pause_limit = mv88e6390_port_pause_limit, 4820 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4821 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4822 .port_get_cmode = mv88e6352_port_get_cmode, 4823 .port_set_cmode = mv88e6390_port_set_cmode, 4824 .port_setup_message_port = mv88e6xxx_setup_message_port, 4825 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4826 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4827 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4828 .stats_get_strings = mv88e6320_stats_get_strings, 4829 .stats_get_stat = mv88e6390_stats_get_stat, 4830 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4831 .set_egress_port = mv88e6390_g1_set_egress_port, 4832 .watchdog_ops = &mv88e6390_watchdog_ops, 4833 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4834 .pot_clear = mv88e6xxx_g2_pot_clear, 4835 .reset = mv88e6352_g1_reset, 4836 .rmu_disable = mv88e6390_g1_rmu_disable, 4837 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4838 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4839 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4840 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4841 .stu_getnext = mv88e6390_g1_stu_getnext, 4842 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4843 .serdes_get_lane = mv88e6390_serdes_get_lane, 4844 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4845 .serdes_get_strings = mv88e6390_serdes_get_strings, 4846 .serdes_get_stats = mv88e6390_serdes_get_stats, 4847 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4848 .serdes_get_regs = mv88e6390_serdes_get_regs, 4849 .avb_ops = &mv88e6390_avb_ops, 4850 .ptp_ops = &mv88e6352_ptp_ops, 4851 .phylink_get_caps = mv88e6390_phylink_get_caps, 4852 .pcs_ops = &mv88e6390_pcs_ops, 4853 }; 4854 4855 static const struct mv88e6xxx_ops mv88e6240_ops = { 4856 /* MV88E6XXX_FAMILY_6352 */ 4857 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4858 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4859 .irl_init_all = mv88e6352_g2_irl_init_all, 4860 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4861 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4862 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4863 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4864 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4865 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4866 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4867 .port_set_link = mv88e6xxx_port_set_link, 4868 .port_sync_link = mv88e6xxx_port_sync_link, 4869 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4870 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4871 .port_tag_remap = mv88e6095_port_tag_remap, 4872 .port_set_policy = mv88e6352_port_set_policy, 4873 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4874 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4875 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4876 .port_set_ether_type = mv88e6351_port_set_ether_type, 4877 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4878 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4879 .port_pause_limit = mv88e6097_port_pause_limit, 4880 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4881 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4882 .port_get_cmode = mv88e6352_port_get_cmode, 4883 .port_setup_message_port = mv88e6xxx_setup_message_port, 4884 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4885 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4886 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4887 .stats_get_strings = mv88e6095_stats_get_strings, 4888 .stats_get_stat = mv88e6095_stats_get_stat, 4889 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4890 .set_egress_port = mv88e6095_g1_set_egress_port, 4891 .watchdog_ops = &mv88e6097_watchdog_ops, 4892 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4893 .pot_clear = mv88e6xxx_g2_pot_clear, 4894 .reset = mv88e6352_g1_reset, 4895 .rmu_disable = mv88e6352_g1_rmu_disable, 4896 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4897 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4898 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4899 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4900 .stu_getnext = mv88e6352_g1_stu_getnext, 4901 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4902 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4903 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4904 .serdes_get_regs = mv88e6352_serdes_get_regs, 4905 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4906 .gpio_ops = &mv88e6352_gpio_ops, 4907 .avb_ops = &mv88e6352_avb_ops, 4908 .ptp_ops = &mv88e6352_ptp_ops, 4909 .phylink_get_caps = mv88e6352_phylink_get_caps, 4910 .pcs_ops = &mv88e6352_pcs_ops, 4911 }; 4912 4913 static const struct mv88e6xxx_ops mv88e6250_ops = { 4914 /* MV88E6XXX_FAMILY_6250 */ 4915 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4916 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4917 .irl_init_all = mv88e6352_g2_irl_init_all, 4918 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4919 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4920 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4921 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4922 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4923 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4924 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4925 .port_set_link = mv88e6xxx_port_set_link, 4926 .port_sync_link = mv88e6xxx_port_sync_link, 4927 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4928 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4929 .port_tag_remap = mv88e6095_port_tag_remap, 4930 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4931 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4932 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4933 .port_set_ether_type = mv88e6351_port_set_ether_type, 4934 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4935 .port_pause_limit = mv88e6097_port_pause_limit, 4936 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4937 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4938 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4939 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4940 .stats_get_strings = mv88e6250_stats_get_strings, 4941 .stats_get_stat = mv88e6250_stats_get_stat, 4942 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4943 .set_egress_port = mv88e6095_g1_set_egress_port, 4944 .watchdog_ops = &mv88e6250_watchdog_ops, 4945 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4946 .pot_clear = mv88e6xxx_g2_pot_clear, 4947 .reset = mv88e6250_g1_reset, 4948 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4949 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4950 .avb_ops = &mv88e6352_avb_ops, 4951 .ptp_ops = &mv88e6250_ptp_ops, 4952 .phylink_get_caps = mv88e6250_phylink_get_caps, 4953 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4954 }; 4955 4956 static const struct mv88e6xxx_ops mv88e6290_ops = { 4957 /* MV88E6XXX_FAMILY_6390 */ 4958 .setup_errata = mv88e6390_setup_errata, 4959 .irl_init_all = mv88e6390_g2_irl_init_all, 4960 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4961 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4962 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4963 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4964 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4965 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4966 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4967 .port_set_link = mv88e6xxx_port_set_link, 4968 .port_sync_link = mv88e6xxx_port_sync_link, 4969 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4970 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4971 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4972 .port_tag_remap = mv88e6390_port_tag_remap, 4973 .port_set_policy = mv88e6352_port_set_policy, 4974 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4975 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4976 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4977 .port_set_ether_type = mv88e6351_port_set_ether_type, 4978 .port_pause_limit = mv88e6390_port_pause_limit, 4979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4981 .port_get_cmode = mv88e6352_port_get_cmode, 4982 .port_set_cmode = mv88e6390_port_set_cmode, 4983 .port_setup_message_port = mv88e6xxx_setup_message_port, 4984 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4985 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4986 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4987 .stats_get_strings = mv88e6320_stats_get_strings, 4988 .stats_get_stat = mv88e6390_stats_get_stat, 4989 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4990 .set_egress_port = mv88e6390_g1_set_egress_port, 4991 .watchdog_ops = &mv88e6390_watchdog_ops, 4992 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4993 .pot_clear = mv88e6xxx_g2_pot_clear, 4994 .reset = mv88e6352_g1_reset, 4995 .rmu_disable = mv88e6390_g1_rmu_disable, 4996 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4997 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4998 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4999 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5000 .stu_getnext = mv88e6390_g1_stu_getnext, 5001 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5002 .serdes_get_lane = mv88e6390_serdes_get_lane, 5003 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5004 .serdes_get_strings = mv88e6390_serdes_get_strings, 5005 .serdes_get_stats = mv88e6390_serdes_get_stats, 5006 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5007 .serdes_get_regs = mv88e6390_serdes_get_regs, 5008 .gpio_ops = &mv88e6352_gpio_ops, 5009 .avb_ops = &mv88e6390_avb_ops, 5010 .ptp_ops = &mv88e6390_ptp_ops, 5011 .phylink_get_caps = mv88e6390_phylink_get_caps, 5012 .pcs_ops = &mv88e6390_pcs_ops, 5013 }; 5014 5015 static const struct mv88e6xxx_ops mv88e6320_ops = { 5016 /* MV88E6XXX_FAMILY_6320 */ 5017 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5018 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5019 .irl_init_all = mv88e6352_g2_irl_init_all, 5020 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5021 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5022 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5023 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5024 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5025 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5026 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5027 .port_set_link = mv88e6xxx_port_set_link, 5028 .port_sync_link = mv88e6xxx_port_sync_link, 5029 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5030 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5031 .port_tag_remap = mv88e6095_port_tag_remap, 5032 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5033 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5034 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5035 .port_set_ether_type = mv88e6351_port_set_ether_type, 5036 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5037 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5038 .port_pause_limit = mv88e6097_port_pause_limit, 5039 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5040 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5041 .port_get_cmode = mv88e6352_port_get_cmode, 5042 .port_setup_message_port = mv88e6xxx_setup_message_port, 5043 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5044 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5045 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5046 .stats_get_strings = mv88e6320_stats_get_strings, 5047 .stats_get_stat = mv88e6320_stats_get_stat, 5048 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5049 .set_egress_port = mv88e6095_g1_set_egress_port, 5050 .watchdog_ops = &mv88e6390_watchdog_ops, 5051 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5052 .pot_clear = mv88e6xxx_g2_pot_clear, 5053 .reset = mv88e6352_g1_reset, 5054 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5055 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5056 .gpio_ops = &mv88e6352_gpio_ops, 5057 .avb_ops = &mv88e6352_avb_ops, 5058 .ptp_ops = &mv88e6352_ptp_ops, 5059 .phylink_get_caps = mv88e6185_phylink_get_caps, 5060 }; 5061 5062 static const struct mv88e6xxx_ops mv88e6321_ops = { 5063 /* MV88E6XXX_FAMILY_6320 */ 5064 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5065 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5066 .irl_init_all = mv88e6352_g2_irl_init_all, 5067 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5068 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5069 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5070 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5071 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5072 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5073 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5074 .port_set_link = mv88e6xxx_port_set_link, 5075 .port_sync_link = mv88e6xxx_port_sync_link, 5076 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5077 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5078 .port_tag_remap = mv88e6095_port_tag_remap, 5079 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5080 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5081 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5082 .port_set_ether_type = mv88e6351_port_set_ether_type, 5083 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5084 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5085 .port_pause_limit = mv88e6097_port_pause_limit, 5086 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5087 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5088 .port_get_cmode = mv88e6352_port_get_cmode, 5089 .port_setup_message_port = mv88e6xxx_setup_message_port, 5090 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5091 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5092 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5093 .stats_get_strings = mv88e6320_stats_get_strings, 5094 .stats_get_stat = mv88e6320_stats_get_stat, 5095 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5096 .set_egress_port = mv88e6095_g1_set_egress_port, 5097 .watchdog_ops = &mv88e6390_watchdog_ops, 5098 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5099 .reset = mv88e6352_g1_reset, 5100 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5101 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5102 .gpio_ops = &mv88e6352_gpio_ops, 5103 .avb_ops = &mv88e6352_avb_ops, 5104 .ptp_ops = &mv88e6352_ptp_ops, 5105 .phylink_get_caps = mv88e6185_phylink_get_caps, 5106 }; 5107 5108 static const struct mv88e6xxx_ops mv88e6341_ops = { 5109 /* MV88E6XXX_FAMILY_6341 */ 5110 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5111 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5112 .irl_init_all = mv88e6352_g2_irl_init_all, 5113 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5114 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5115 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5116 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5117 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5118 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5119 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5120 .port_set_link = mv88e6xxx_port_set_link, 5121 .port_sync_link = mv88e6xxx_port_sync_link, 5122 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5123 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5124 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5125 .port_tag_remap = mv88e6095_port_tag_remap, 5126 .port_set_policy = mv88e6352_port_set_policy, 5127 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5128 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5129 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5130 .port_set_ether_type = mv88e6351_port_set_ether_type, 5131 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5132 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5133 .port_pause_limit = mv88e6097_port_pause_limit, 5134 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5135 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5136 .port_get_cmode = mv88e6352_port_get_cmode, 5137 .port_set_cmode = mv88e6341_port_set_cmode, 5138 .port_setup_message_port = mv88e6xxx_setup_message_port, 5139 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5140 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5141 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5142 .stats_get_strings = mv88e6320_stats_get_strings, 5143 .stats_get_stat = mv88e6390_stats_get_stat, 5144 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5145 .set_egress_port = mv88e6390_g1_set_egress_port, 5146 .watchdog_ops = &mv88e6390_watchdog_ops, 5147 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5148 .pot_clear = mv88e6xxx_g2_pot_clear, 5149 .reset = mv88e6352_g1_reset, 5150 .rmu_disable = mv88e6390_g1_rmu_disable, 5151 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5152 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5153 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5154 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5155 .stu_getnext = mv88e6352_g1_stu_getnext, 5156 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5157 .serdes_get_lane = mv88e6341_serdes_get_lane, 5158 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5159 .gpio_ops = &mv88e6352_gpio_ops, 5160 .avb_ops = &mv88e6390_avb_ops, 5161 .ptp_ops = &mv88e6352_ptp_ops, 5162 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5163 .serdes_get_strings = mv88e6390_serdes_get_strings, 5164 .serdes_get_stats = mv88e6390_serdes_get_stats, 5165 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5166 .serdes_get_regs = mv88e6390_serdes_get_regs, 5167 .phylink_get_caps = mv88e6341_phylink_get_caps, 5168 .pcs_ops = &mv88e6390_pcs_ops, 5169 }; 5170 5171 static const struct mv88e6xxx_ops mv88e6350_ops = { 5172 /* MV88E6XXX_FAMILY_6351 */ 5173 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5174 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5175 .irl_init_all = mv88e6352_g2_irl_init_all, 5176 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5177 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5178 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5179 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5180 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5181 .port_set_link = mv88e6xxx_port_set_link, 5182 .port_sync_link = mv88e6xxx_port_sync_link, 5183 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5184 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5185 .port_tag_remap = mv88e6095_port_tag_remap, 5186 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5187 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5188 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5189 .port_set_ether_type = mv88e6351_port_set_ether_type, 5190 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5191 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5192 .port_pause_limit = mv88e6097_port_pause_limit, 5193 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5194 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5195 .port_get_cmode = mv88e6352_port_get_cmode, 5196 .port_setup_message_port = mv88e6xxx_setup_message_port, 5197 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5198 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5199 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5200 .stats_get_strings = mv88e6095_stats_get_strings, 5201 .stats_get_stat = mv88e6095_stats_get_stat, 5202 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5203 .set_egress_port = mv88e6095_g1_set_egress_port, 5204 .watchdog_ops = &mv88e6097_watchdog_ops, 5205 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5206 .pot_clear = mv88e6xxx_g2_pot_clear, 5207 .reset = mv88e6352_g1_reset, 5208 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5209 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5210 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5211 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5212 .stu_getnext = mv88e6352_g1_stu_getnext, 5213 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5214 .phylink_get_caps = mv88e6351_phylink_get_caps, 5215 }; 5216 5217 static const struct mv88e6xxx_ops mv88e6351_ops = { 5218 /* MV88E6XXX_FAMILY_6351 */ 5219 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5220 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5221 .irl_init_all = mv88e6352_g2_irl_init_all, 5222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5223 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5224 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5225 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5226 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5227 .port_set_link = mv88e6xxx_port_set_link, 5228 .port_sync_link = mv88e6xxx_port_sync_link, 5229 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5230 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5231 .port_tag_remap = mv88e6095_port_tag_remap, 5232 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5233 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5234 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5235 .port_set_ether_type = mv88e6351_port_set_ether_type, 5236 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5237 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5238 .port_pause_limit = mv88e6097_port_pause_limit, 5239 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5240 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5241 .port_get_cmode = mv88e6352_port_get_cmode, 5242 .port_setup_message_port = mv88e6xxx_setup_message_port, 5243 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5244 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5245 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5246 .stats_get_strings = mv88e6095_stats_get_strings, 5247 .stats_get_stat = mv88e6095_stats_get_stat, 5248 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5249 .set_egress_port = mv88e6095_g1_set_egress_port, 5250 .watchdog_ops = &mv88e6097_watchdog_ops, 5251 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5252 .pot_clear = mv88e6xxx_g2_pot_clear, 5253 .reset = mv88e6352_g1_reset, 5254 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5255 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5256 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5257 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5258 .stu_getnext = mv88e6352_g1_stu_getnext, 5259 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5260 .avb_ops = &mv88e6352_avb_ops, 5261 .ptp_ops = &mv88e6352_ptp_ops, 5262 .phylink_get_caps = mv88e6351_phylink_get_caps, 5263 }; 5264 5265 static const struct mv88e6xxx_ops mv88e6352_ops = { 5266 /* MV88E6XXX_FAMILY_6352 */ 5267 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5268 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5269 .irl_init_all = mv88e6352_g2_irl_init_all, 5270 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5271 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5272 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5273 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5274 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5275 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5276 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5277 .port_set_link = mv88e6xxx_port_set_link, 5278 .port_sync_link = mv88e6xxx_port_sync_link, 5279 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5280 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5281 .port_tag_remap = mv88e6095_port_tag_remap, 5282 .port_set_policy = mv88e6352_port_set_policy, 5283 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5284 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5285 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5286 .port_set_ether_type = mv88e6351_port_set_ether_type, 5287 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5288 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5289 .port_pause_limit = mv88e6097_port_pause_limit, 5290 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5291 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5292 .port_get_cmode = mv88e6352_port_get_cmode, 5293 .port_setup_message_port = mv88e6xxx_setup_message_port, 5294 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5295 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5296 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5297 .stats_get_strings = mv88e6095_stats_get_strings, 5298 .stats_get_stat = mv88e6095_stats_get_stat, 5299 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5300 .set_egress_port = mv88e6095_g1_set_egress_port, 5301 .watchdog_ops = &mv88e6097_watchdog_ops, 5302 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5303 .pot_clear = mv88e6xxx_g2_pot_clear, 5304 .reset = mv88e6352_g1_reset, 5305 .rmu_disable = mv88e6352_g1_rmu_disable, 5306 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5307 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5308 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5309 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5310 .stu_getnext = mv88e6352_g1_stu_getnext, 5311 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5312 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5313 .gpio_ops = &mv88e6352_gpio_ops, 5314 .avb_ops = &mv88e6352_avb_ops, 5315 .ptp_ops = &mv88e6352_ptp_ops, 5316 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5317 .serdes_get_strings = mv88e6352_serdes_get_strings, 5318 .serdes_get_stats = mv88e6352_serdes_get_stats, 5319 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5320 .serdes_get_regs = mv88e6352_serdes_get_regs, 5321 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5322 .phylink_get_caps = mv88e6352_phylink_get_caps, 5323 .pcs_ops = &mv88e6352_pcs_ops, 5324 }; 5325 5326 static const struct mv88e6xxx_ops mv88e6390_ops = { 5327 /* MV88E6XXX_FAMILY_6390 */ 5328 .setup_errata = mv88e6390_setup_errata, 5329 .irl_init_all = mv88e6390_g2_irl_init_all, 5330 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5331 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5332 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5333 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5334 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5335 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5336 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5337 .port_set_link = mv88e6xxx_port_set_link, 5338 .port_sync_link = mv88e6xxx_port_sync_link, 5339 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5340 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5341 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5342 .port_tag_remap = mv88e6390_port_tag_remap, 5343 .port_set_policy = mv88e6352_port_set_policy, 5344 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5345 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5346 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5347 .port_set_ether_type = mv88e6351_port_set_ether_type, 5348 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5349 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5350 .port_pause_limit = mv88e6390_port_pause_limit, 5351 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5352 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5353 .port_get_cmode = mv88e6352_port_get_cmode, 5354 .port_set_cmode = mv88e6390_port_set_cmode, 5355 .port_setup_message_port = mv88e6xxx_setup_message_port, 5356 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5357 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5358 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5359 .stats_get_strings = mv88e6320_stats_get_strings, 5360 .stats_get_stat = mv88e6390_stats_get_stat, 5361 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5362 .set_egress_port = mv88e6390_g1_set_egress_port, 5363 .watchdog_ops = &mv88e6390_watchdog_ops, 5364 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5365 .pot_clear = mv88e6xxx_g2_pot_clear, 5366 .reset = mv88e6352_g1_reset, 5367 .rmu_disable = mv88e6390_g1_rmu_disable, 5368 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5369 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5370 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5371 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5372 .stu_getnext = mv88e6390_g1_stu_getnext, 5373 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5374 .serdes_get_lane = mv88e6390_serdes_get_lane, 5375 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5376 .gpio_ops = &mv88e6352_gpio_ops, 5377 .avb_ops = &mv88e6390_avb_ops, 5378 .ptp_ops = &mv88e6390_ptp_ops, 5379 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5380 .serdes_get_strings = mv88e6390_serdes_get_strings, 5381 .serdes_get_stats = mv88e6390_serdes_get_stats, 5382 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5383 .serdes_get_regs = mv88e6390_serdes_get_regs, 5384 .phylink_get_caps = mv88e6390_phylink_get_caps, 5385 .pcs_ops = &mv88e6390_pcs_ops, 5386 }; 5387 5388 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5389 /* MV88E6XXX_FAMILY_6390 */ 5390 .setup_errata = mv88e6390_setup_errata, 5391 .irl_init_all = mv88e6390_g2_irl_init_all, 5392 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5393 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5394 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5395 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5396 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5397 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5398 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5399 .port_set_link = mv88e6xxx_port_set_link, 5400 .port_sync_link = mv88e6xxx_port_sync_link, 5401 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5402 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5403 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5404 .port_tag_remap = mv88e6390_port_tag_remap, 5405 .port_set_policy = mv88e6352_port_set_policy, 5406 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5407 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5408 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5409 .port_set_ether_type = mv88e6351_port_set_ether_type, 5410 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5411 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5412 .port_pause_limit = mv88e6390_port_pause_limit, 5413 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5414 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5415 .port_get_cmode = mv88e6352_port_get_cmode, 5416 .port_set_cmode = mv88e6390x_port_set_cmode, 5417 .port_setup_message_port = mv88e6xxx_setup_message_port, 5418 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5419 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5420 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5421 .stats_get_strings = mv88e6320_stats_get_strings, 5422 .stats_get_stat = mv88e6390_stats_get_stat, 5423 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5424 .set_egress_port = mv88e6390_g1_set_egress_port, 5425 .watchdog_ops = &mv88e6390_watchdog_ops, 5426 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5427 .pot_clear = mv88e6xxx_g2_pot_clear, 5428 .reset = mv88e6352_g1_reset, 5429 .rmu_disable = mv88e6390_g1_rmu_disable, 5430 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5431 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5432 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5433 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5434 .stu_getnext = mv88e6390_g1_stu_getnext, 5435 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5436 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5437 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5438 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5439 .serdes_get_strings = mv88e6390_serdes_get_strings, 5440 .serdes_get_stats = mv88e6390_serdes_get_stats, 5441 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5442 .serdes_get_regs = mv88e6390_serdes_get_regs, 5443 .gpio_ops = &mv88e6352_gpio_ops, 5444 .avb_ops = &mv88e6390_avb_ops, 5445 .ptp_ops = &mv88e6390_ptp_ops, 5446 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5447 .pcs_ops = &mv88e6390_pcs_ops, 5448 }; 5449 5450 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5451 /* MV88E6XXX_FAMILY_6393 */ 5452 .irl_init_all = mv88e6390_g2_irl_init_all, 5453 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5454 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5455 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5456 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5457 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5458 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5459 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5460 .port_set_link = mv88e6xxx_port_set_link, 5461 .port_sync_link = mv88e6xxx_port_sync_link, 5462 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5463 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5464 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5465 .port_tag_remap = mv88e6390_port_tag_remap, 5466 .port_set_policy = mv88e6393x_port_set_policy, 5467 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5468 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5469 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5470 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5471 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5472 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5473 .port_pause_limit = mv88e6390_port_pause_limit, 5474 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5475 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5476 .port_get_cmode = mv88e6352_port_get_cmode, 5477 .port_set_cmode = mv88e6393x_port_set_cmode, 5478 .port_setup_message_port = mv88e6xxx_setup_message_port, 5479 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5480 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5481 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5482 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5483 .stats_get_strings = mv88e6320_stats_get_strings, 5484 .stats_get_stat = mv88e6390_stats_get_stat, 5485 /* .set_cpu_port is missing because this family does not support a global 5486 * CPU port, only per port CPU port which is set via 5487 * .port_set_upstream_port method. 5488 */ 5489 .set_egress_port = mv88e6393x_set_egress_port, 5490 .watchdog_ops = &mv88e6393x_watchdog_ops, 5491 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5492 .pot_clear = mv88e6xxx_g2_pot_clear, 5493 .reset = mv88e6352_g1_reset, 5494 .rmu_disable = mv88e6390_g1_rmu_disable, 5495 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5496 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5497 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5498 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5499 .stu_getnext = mv88e6390_g1_stu_getnext, 5500 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5501 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5502 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5503 /* TODO: serdes stats */ 5504 .gpio_ops = &mv88e6352_gpio_ops, 5505 .avb_ops = &mv88e6390_avb_ops, 5506 .ptp_ops = &mv88e6352_ptp_ops, 5507 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5508 .pcs_ops = &mv88e6393x_pcs_ops, 5509 }; 5510 5511 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5512 [MV88E6020] = { 5513 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5514 .family = MV88E6XXX_FAMILY_6250, 5515 .name = "Marvell 88E6020", 5516 .num_databases = 64, 5517 /* Ports 2-4 are not routed to pins 5518 * => usable ports 0, 1, 5, 6 5519 */ 5520 .num_ports = 7, 5521 .num_internal_phys = 2, 5522 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5523 .max_vid = 4095, 5524 .port_base_addr = 0x8, 5525 .phy_base_addr = 0x0, 5526 .global1_addr = 0xf, 5527 .global2_addr = 0x7, 5528 .age_time_coeff = 15000, 5529 .g1_irqs = 9, 5530 .g2_irqs = 5, 5531 .atu_move_port_mask = 0xf, 5532 .dual_chip = true, 5533 .ops = &mv88e6250_ops, 5534 }, 5535 5536 [MV88E6071] = { 5537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5538 .family = MV88E6XXX_FAMILY_6250, 5539 .name = "Marvell 88E6071", 5540 .num_databases = 64, 5541 .num_ports = 7, 5542 .num_internal_phys = 5, 5543 .max_vid = 4095, 5544 .port_base_addr = 0x08, 5545 .phy_base_addr = 0x00, 5546 .global1_addr = 0x0f, 5547 .global2_addr = 0x07, 5548 .age_time_coeff = 15000, 5549 .g1_irqs = 9, 5550 .g2_irqs = 5, 5551 .atu_move_port_mask = 0xf, 5552 .dual_chip = true, 5553 .ops = &mv88e6250_ops, 5554 }, 5555 5556 [MV88E6085] = { 5557 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5558 .family = MV88E6XXX_FAMILY_6097, 5559 .name = "Marvell 88E6085", 5560 .num_databases = 4096, 5561 .num_macs = 8192, 5562 .num_ports = 10, 5563 .num_internal_phys = 5, 5564 .max_vid = 4095, 5565 .max_sid = 63, 5566 .port_base_addr = 0x10, 5567 .phy_base_addr = 0x0, 5568 .global1_addr = 0x1b, 5569 .global2_addr = 0x1c, 5570 .age_time_coeff = 15000, 5571 .g1_irqs = 8, 5572 .g2_irqs = 10, 5573 .atu_move_port_mask = 0xf, 5574 .pvt = true, 5575 .multi_chip = true, 5576 .ops = &mv88e6085_ops, 5577 }, 5578 5579 [MV88E6095] = { 5580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5581 .family = MV88E6XXX_FAMILY_6095, 5582 .name = "Marvell 88E6095/88E6095F", 5583 .num_databases = 256, 5584 .num_macs = 8192, 5585 .num_ports = 11, 5586 .num_internal_phys = 0, 5587 .max_vid = 4095, 5588 .port_base_addr = 0x10, 5589 .phy_base_addr = 0x0, 5590 .global1_addr = 0x1b, 5591 .global2_addr = 0x1c, 5592 .age_time_coeff = 15000, 5593 .g1_irqs = 8, 5594 .atu_move_port_mask = 0xf, 5595 .multi_chip = true, 5596 .ops = &mv88e6095_ops, 5597 }, 5598 5599 [MV88E6097] = { 5600 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5601 .family = MV88E6XXX_FAMILY_6097, 5602 .name = "Marvell 88E6097/88E6097F", 5603 .num_databases = 4096, 5604 .num_macs = 8192, 5605 .num_ports = 11, 5606 .num_internal_phys = 8, 5607 .max_vid = 4095, 5608 .max_sid = 63, 5609 .port_base_addr = 0x10, 5610 .phy_base_addr = 0x0, 5611 .global1_addr = 0x1b, 5612 .global2_addr = 0x1c, 5613 .age_time_coeff = 15000, 5614 .g1_irqs = 8, 5615 .g2_irqs = 10, 5616 .atu_move_port_mask = 0xf, 5617 .pvt = true, 5618 .multi_chip = true, 5619 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5620 .ops = &mv88e6097_ops, 5621 }, 5622 5623 [MV88E6123] = { 5624 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5625 .family = MV88E6XXX_FAMILY_6165, 5626 .name = "Marvell 88E6123", 5627 .num_databases = 4096, 5628 .num_macs = 1024, 5629 .num_ports = 3, 5630 .num_internal_phys = 5, 5631 .max_vid = 4095, 5632 .max_sid = 63, 5633 .port_base_addr = 0x10, 5634 .phy_base_addr = 0x0, 5635 .global1_addr = 0x1b, 5636 .global2_addr = 0x1c, 5637 .age_time_coeff = 15000, 5638 .g1_irqs = 9, 5639 .g2_irqs = 10, 5640 .atu_move_port_mask = 0xf, 5641 .pvt = true, 5642 .multi_chip = true, 5643 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5644 .ops = &mv88e6123_ops, 5645 }, 5646 5647 [MV88E6131] = { 5648 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5649 .family = MV88E6XXX_FAMILY_6185, 5650 .name = "Marvell 88E6131", 5651 .num_databases = 256, 5652 .num_macs = 8192, 5653 .num_ports = 8, 5654 .num_internal_phys = 0, 5655 .max_vid = 4095, 5656 .port_base_addr = 0x10, 5657 .phy_base_addr = 0x0, 5658 .global1_addr = 0x1b, 5659 .global2_addr = 0x1c, 5660 .age_time_coeff = 15000, 5661 .g1_irqs = 9, 5662 .atu_move_port_mask = 0xf, 5663 .multi_chip = true, 5664 .ops = &mv88e6131_ops, 5665 }, 5666 5667 [MV88E6141] = { 5668 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5669 .family = MV88E6XXX_FAMILY_6341, 5670 .name = "Marvell 88E6141", 5671 .num_databases = 4096, 5672 .num_macs = 2048, 5673 .num_ports = 6, 5674 .num_internal_phys = 5, 5675 .num_gpio = 11, 5676 .max_vid = 4095, 5677 .max_sid = 63, 5678 .port_base_addr = 0x10, 5679 .phy_base_addr = 0x10, 5680 .global1_addr = 0x1b, 5681 .global2_addr = 0x1c, 5682 .age_time_coeff = 3750, 5683 .atu_move_port_mask = 0x1f, 5684 .g1_irqs = 9, 5685 .g2_irqs = 10, 5686 .pvt = true, 5687 .multi_chip = true, 5688 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5689 .ops = &mv88e6141_ops, 5690 }, 5691 5692 [MV88E6161] = { 5693 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5694 .family = MV88E6XXX_FAMILY_6165, 5695 .name = "Marvell 88E6161", 5696 .num_databases = 4096, 5697 .num_macs = 1024, 5698 .num_ports = 6, 5699 .num_internal_phys = 5, 5700 .max_vid = 4095, 5701 .max_sid = 63, 5702 .port_base_addr = 0x10, 5703 .phy_base_addr = 0x0, 5704 .global1_addr = 0x1b, 5705 .global2_addr = 0x1c, 5706 .age_time_coeff = 15000, 5707 .g1_irqs = 9, 5708 .g2_irqs = 10, 5709 .atu_move_port_mask = 0xf, 5710 .pvt = true, 5711 .multi_chip = true, 5712 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5713 .ptp_support = true, 5714 .ops = &mv88e6161_ops, 5715 }, 5716 5717 [MV88E6165] = { 5718 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5719 .family = MV88E6XXX_FAMILY_6165, 5720 .name = "Marvell 88E6165", 5721 .num_databases = 4096, 5722 .num_macs = 8192, 5723 .num_ports = 6, 5724 .num_internal_phys = 0, 5725 .max_vid = 4095, 5726 .max_sid = 63, 5727 .port_base_addr = 0x10, 5728 .phy_base_addr = 0x0, 5729 .global1_addr = 0x1b, 5730 .global2_addr = 0x1c, 5731 .age_time_coeff = 15000, 5732 .g1_irqs = 9, 5733 .g2_irqs = 10, 5734 .atu_move_port_mask = 0xf, 5735 .pvt = true, 5736 .multi_chip = true, 5737 .ptp_support = true, 5738 .ops = &mv88e6165_ops, 5739 }, 5740 5741 [MV88E6171] = { 5742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5743 .family = MV88E6XXX_FAMILY_6351, 5744 .name = "Marvell 88E6171", 5745 .num_databases = 4096, 5746 .num_macs = 8192, 5747 .num_ports = 7, 5748 .num_internal_phys = 5, 5749 .max_vid = 4095, 5750 .max_sid = 63, 5751 .port_base_addr = 0x10, 5752 .phy_base_addr = 0x0, 5753 .global1_addr = 0x1b, 5754 .global2_addr = 0x1c, 5755 .age_time_coeff = 15000, 5756 .g1_irqs = 9, 5757 .g2_irqs = 10, 5758 .atu_move_port_mask = 0xf, 5759 .pvt = true, 5760 .multi_chip = true, 5761 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5762 .ops = &mv88e6171_ops, 5763 }, 5764 5765 [MV88E6172] = { 5766 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5767 .family = MV88E6XXX_FAMILY_6352, 5768 .name = "Marvell 88E6172", 5769 .num_databases = 4096, 5770 .num_macs = 8192, 5771 .num_ports = 7, 5772 .num_internal_phys = 5, 5773 .num_gpio = 15, 5774 .max_vid = 4095, 5775 .max_sid = 63, 5776 .port_base_addr = 0x10, 5777 .phy_base_addr = 0x0, 5778 .global1_addr = 0x1b, 5779 .global2_addr = 0x1c, 5780 .age_time_coeff = 15000, 5781 .g1_irqs = 9, 5782 .g2_irqs = 10, 5783 .atu_move_port_mask = 0xf, 5784 .pvt = true, 5785 .multi_chip = true, 5786 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5787 .ops = &mv88e6172_ops, 5788 }, 5789 5790 [MV88E6175] = { 5791 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5792 .family = MV88E6XXX_FAMILY_6351, 5793 .name = "Marvell 88E6175", 5794 .num_databases = 4096, 5795 .num_macs = 8192, 5796 .num_ports = 7, 5797 .num_internal_phys = 5, 5798 .max_vid = 4095, 5799 .max_sid = 63, 5800 .port_base_addr = 0x10, 5801 .phy_base_addr = 0x0, 5802 .global1_addr = 0x1b, 5803 .global2_addr = 0x1c, 5804 .age_time_coeff = 15000, 5805 .g1_irqs = 9, 5806 .g2_irqs = 10, 5807 .atu_move_port_mask = 0xf, 5808 .pvt = true, 5809 .multi_chip = true, 5810 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5811 .ops = &mv88e6175_ops, 5812 }, 5813 5814 [MV88E6176] = { 5815 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5816 .family = MV88E6XXX_FAMILY_6352, 5817 .name = "Marvell 88E6176", 5818 .num_databases = 4096, 5819 .num_macs = 8192, 5820 .num_ports = 7, 5821 .num_internal_phys = 5, 5822 .num_gpio = 15, 5823 .max_vid = 4095, 5824 .max_sid = 63, 5825 .port_base_addr = 0x10, 5826 .phy_base_addr = 0x0, 5827 .global1_addr = 0x1b, 5828 .global2_addr = 0x1c, 5829 .age_time_coeff = 15000, 5830 .g1_irqs = 9, 5831 .g2_irqs = 10, 5832 .atu_move_port_mask = 0xf, 5833 .pvt = true, 5834 .multi_chip = true, 5835 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5836 .ops = &mv88e6176_ops, 5837 }, 5838 5839 [MV88E6185] = { 5840 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5841 .family = MV88E6XXX_FAMILY_6185, 5842 .name = "Marvell 88E6185", 5843 .num_databases = 256, 5844 .num_macs = 8192, 5845 .num_ports = 10, 5846 .num_internal_phys = 0, 5847 .max_vid = 4095, 5848 .port_base_addr = 0x10, 5849 .phy_base_addr = 0x0, 5850 .global1_addr = 0x1b, 5851 .global2_addr = 0x1c, 5852 .age_time_coeff = 15000, 5853 .g1_irqs = 8, 5854 .atu_move_port_mask = 0xf, 5855 .multi_chip = true, 5856 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5857 .ops = &mv88e6185_ops, 5858 }, 5859 5860 [MV88E6190] = { 5861 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5862 .family = MV88E6XXX_FAMILY_6390, 5863 .name = "Marvell 88E6190", 5864 .num_databases = 4096, 5865 .num_macs = 16384, 5866 .num_ports = 11, /* 10 + Z80 */ 5867 .num_internal_phys = 9, 5868 .num_gpio = 16, 5869 .max_vid = 8191, 5870 .max_sid = 63, 5871 .port_base_addr = 0x0, 5872 .phy_base_addr = 0x0, 5873 .global1_addr = 0x1b, 5874 .global2_addr = 0x1c, 5875 .age_time_coeff = 3750, 5876 .g1_irqs = 9, 5877 .g2_irqs = 14, 5878 .pvt = true, 5879 .multi_chip = true, 5880 .atu_move_port_mask = 0x1f, 5881 .ops = &mv88e6190_ops, 5882 }, 5883 5884 [MV88E6190X] = { 5885 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5886 .family = MV88E6XXX_FAMILY_6390, 5887 .name = "Marvell 88E6190X", 5888 .num_databases = 4096, 5889 .num_macs = 16384, 5890 .num_ports = 11, /* 10 + Z80 */ 5891 .num_internal_phys = 9, 5892 .num_gpio = 16, 5893 .max_vid = 8191, 5894 .max_sid = 63, 5895 .port_base_addr = 0x0, 5896 .phy_base_addr = 0x0, 5897 .global1_addr = 0x1b, 5898 .global2_addr = 0x1c, 5899 .age_time_coeff = 3750, 5900 .g1_irqs = 9, 5901 .g2_irqs = 14, 5902 .atu_move_port_mask = 0x1f, 5903 .pvt = true, 5904 .multi_chip = true, 5905 .ops = &mv88e6190x_ops, 5906 }, 5907 5908 [MV88E6191] = { 5909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5910 .family = MV88E6XXX_FAMILY_6390, 5911 .name = "Marvell 88E6191", 5912 .num_databases = 4096, 5913 .num_macs = 16384, 5914 .num_ports = 11, /* 10 + Z80 */ 5915 .num_internal_phys = 9, 5916 .max_vid = 8191, 5917 .max_sid = 63, 5918 .port_base_addr = 0x0, 5919 .phy_base_addr = 0x0, 5920 .global1_addr = 0x1b, 5921 .global2_addr = 0x1c, 5922 .age_time_coeff = 3750, 5923 .g1_irqs = 9, 5924 .g2_irqs = 14, 5925 .atu_move_port_mask = 0x1f, 5926 .pvt = true, 5927 .multi_chip = true, 5928 .ptp_support = true, 5929 .ops = &mv88e6191_ops, 5930 }, 5931 5932 [MV88E6191X] = { 5933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5934 .family = MV88E6XXX_FAMILY_6393, 5935 .name = "Marvell 88E6191X", 5936 .num_databases = 4096, 5937 .num_ports = 11, /* 10 + Z80 */ 5938 .num_internal_phys = 8, 5939 .internal_phys_offset = 1, 5940 .max_vid = 8191, 5941 .max_sid = 63, 5942 .port_base_addr = 0x0, 5943 .phy_base_addr = 0x0, 5944 .global1_addr = 0x1b, 5945 .global2_addr = 0x1c, 5946 .age_time_coeff = 3750, 5947 .g1_irqs = 10, 5948 .g2_irqs = 14, 5949 .atu_move_port_mask = 0x1f, 5950 .pvt = true, 5951 .multi_chip = true, 5952 .ptp_support = true, 5953 .ops = &mv88e6393x_ops, 5954 }, 5955 5956 [MV88E6193X] = { 5957 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5958 .family = MV88E6XXX_FAMILY_6393, 5959 .name = "Marvell 88E6193X", 5960 .num_databases = 4096, 5961 .num_ports = 11, /* 10 + Z80 */ 5962 .num_internal_phys = 8, 5963 .internal_phys_offset = 1, 5964 .max_vid = 8191, 5965 .max_sid = 63, 5966 .port_base_addr = 0x0, 5967 .phy_base_addr = 0x0, 5968 .global1_addr = 0x1b, 5969 .global2_addr = 0x1c, 5970 .age_time_coeff = 3750, 5971 .g1_irqs = 10, 5972 .g2_irqs = 14, 5973 .atu_move_port_mask = 0x1f, 5974 .pvt = true, 5975 .multi_chip = true, 5976 .ptp_support = true, 5977 .ops = &mv88e6393x_ops, 5978 }, 5979 5980 [MV88E6220] = { 5981 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5982 .family = MV88E6XXX_FAMILY_6250, 5983 .name = "Marvell 88E6220", 5984 .num_databases = 64, 5985 5986 /* Ports 2-4 are not routed to pins 5987 * => usable ports 0, 1, 5, 6 5988 */ 5989 .num_ports = 7, 5990 .num_internal_phys = 2, 5991 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5992 .max_vid = 4095, 5993 .port_base_addr = 0x08, 5994 .phy_base_addr = 0x00, 5995 .global1_addr = 0x0f, 5996 .global2_addr = 0x07, 5997 .age_time_coeff = 15000, 5998 .g1_irqs = 9, 5999 .g2_irqs = 10, 6000 .atu_move_port_mask = 0xf, 6001 .dual_chip = true, 6002 .ptp_support = true, 6003 .ops = &mv88e6250_ops, 6004 }, 6005 6006 [MV88E6240] = { 6007 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6008 .family = MV88E6XXX_FAMILY_6352, 6009 .name = "Marvell 88E6240", 6010 .num_databases = 4096, 6011 .num_macs = 8192, 6012 .num_ports = 7, 6013 .num_internal_phys = 5, 6014 .num_gpio = 15, 6015 .max_vid = 4095, 6016 .max_sid = 63, 6017 .port_base_addr = 0x10, 6018 .phy_base_addr = 0x0, 6019 .global1_addr = 0x1b, 6020 .global2_addr = 0x1c, 6021 .age_time_coeff = 15000, 6022 .g1_irqs = 9, 6023 .g2_irqs = 10, 6024 .atu_move_port_mask = 0xf, 6025 .pvt = true, 6026 .multi_chip = true, 6027 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6028 .ptp_support = true, 6029 .ops = &mv88e6240_ops, 6030 }, 6031 6032 [MV88E6250] = { 6033 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6034 .family = MV88E6XXX_FAMILY_6250, 6035 .name = "Marvell 88E6250", 6036 .num_databases = 64, 6037 .num_ports = 7, 6038 .num_internal_phys = 5, 6039 .max_vid = 4095, 6040 .port_base_addr = 0x08, 6041 .phy_base_addr = 0x00, 6042 .global1_addr = 0x0f, 6043 .global2_addr = 0x07, 6044 .age_time_coeff = 15000, 6045 .g1_irqs = 9, 6046 .g2_irqs = 10, 6047 .atu_move_port_mask = 0xf, 6048 .dual_chip = true, 6049 .ptp_support = true, 6050 .ops = &mv88e6250_ops, 6051 }, 6052 6053 [MV88E6290] = { 6054 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6055 .family = MV88E6XXX_FAMILY_6390, 6056 .name = "Marvell 88E6290", 6057 .num_databases = 4096, 6058 .num_ports = 11, /* 10 + Z80 */ 6059 .num_internal_phys = 9, 6060 .num_gpio = 16, 6061 .max_vid = 8191, 6062 .max_sid = 63, 6063 .port_base_addr = 0x0, 6064 .phy_base_addr = 0x0, 6065 .global1_addr = 0x1b, 6066 .global2_addr = 0x1c, 6067 .age_time_coeff = 3750, 6068 .g1_irqs = 9, 6069 .g2_irqs = 14, 6070 .atu_move_port_mask = 0x1f, 6071 .pvt = true, 6072 .multi_chip = true, 6073 .ptp_support = true, 6074 .ops = &mv88e6290_ops, 6075 }, 6076 6077 [MV88E6320] = { 6078 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6079 .family = MV88E6XXX_FAMILY_6320, 6080 .name = "Marvell 88E6320", 6081 .num_databases = 4096, 6082 .num_macs = 8192, 6083 .num_ports = 7, 6084 .num_internal_phys = 5, 6085 .num_gpio = 15, 6086 .max_vid = 4095, 6087 .port_base_addr = 0x10, 6088 .phy_base_addr = 0x0, 6089 .global1_addr = 0x1b, 6090 .global2_addr = 0x1c, 6091 .age_time_coeff = 15000, 6092 .g1_irqs = 8, 6093 .g2_irqs = 10, 6094 .atu_move_port_mask = 0xf, 6095 .pvt = true, 6096 .multi_chip = true, 6097 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6098 .ptp_support = true, 6099 .ops = &mv88e6320_ops, 6100 }, 6101 6102 [MV88E6321] = { 6103 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6104 .family = MV88E6XXX_FAMILY_6320, 6105 .name = "Marvell 88E6321", 6106 .num_databases = 4096, 6107 .num_macs = 8192, 6108 .num_ports = 7, 6109 .num_internal_phys = 5, 6110 .num_gpio = 15, 6111 .max_vid = 4095, 6112 .port_base_addr = 0x10, 6113 .phy_base_addr = 0x0, 6114 .global1_addr = 0x1b, 6115 .global2_addr = 0x1c, 6116 .age_time_coeff = 15000, 6117 .g1_irqs = 8, 6118 .g2_irqs = 10, 6119 .atu_move_port_mask = 0xf, 6120 .multi_chip = true, 6121 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6122 .ptp_support = true, 6123 .ops = &mv88e6321_ops, 6124 }, 6125 6126 [MV88E6341] = { 6127 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6128 .family = MV88E6XXX_FAMILY_6341, 6129 .name = "Marvell 88E6341", 6130 .num_databases = 4096, 6131 .num_macs = 2048, 6132 .num_internal_phys = 5, 6133 .num_ports = 6, 6134 .num_gpio = 11, 6135 .max_vid = 4095, 6136 .max_sid = 63, 6137 .port_base_addr = 0x10, 6138 .phy_base_addr = 0x10, 6139 .global1_addr = 0x1b, 6140 .global2_addr = 0x1c, 6141 .age_time_coeff = 3750, 6142 .atu_move_port_mask = 0x1f, 6143 .g1_irqs = 9, 6144 .g2_irqs = 10, 6145 .pvt = true, 6146 .multi_chip = true, 6147 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6148 .ptp_support = true, 6149 .ops = &mv88e6341_ops, 6150 }, 6151 6152 [MV88E6350] = { 6153 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6154 .family = MV88E6XXX_FAMILY_6351, 6155 .name = "Marvell 88E6350", 6156 .num_databases = 4096, 6157 .num_macs = 8192, 6158 .num_ports = 7, 6159 .num_internal_phys = 5, 6160 .max_vid = 4095, 6161 .max_sid = 63, 6162 .port_base_addr = 0x10, 6163 .phy_base_addr = 0x0, 6164 .global1_addr = 0x1b, 6165 .global2_addr = 0x1c, 6166 .age_time_coeff = 15000, 6167 .g1_irqs = 9, 6168 .g2_irqs = 10, 6169 .atu_move_port_mask = 0xf, 6170 .pvt = true, 6171 .multi_chip = true, 6172 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6173 .ops = &mv88e6350_ops, 6174 }, 6175 6176 [MV88E6351] = { 6177 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6178 .family = MV88E6XXX_FAMILY_6351, 6179 .name = "Marvell 88E6351", 6180 .num_databases = 4096, 6181 .num_macs = 8192, 6182 .num_ports = 7, 6183 .num_internal_phys = 5, 6184 .max_vid = 4095, 6185 .max_sid = 63, 6186 .port_base_addr = 0x10, 6187 .phy_base_addr = 0x0, 6188 .global1_addr = 0x1b, 6189 .global2_addr = 0x1c, 6190 .age_time_coeff = 15000, 6191 .g1_irqs = 9, 6192 .g2_irqs = 10, 6193 .atu_move_port_mask = 0xf, 6194 .pvt = true, 6195 .multi_chip = true, 6196 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6197 .ops = &mv88e6351_ops, 6198 }, 6199 6200 [MV88E6352] = { 6201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6202 .family = MV88E6XXX_FAMILY_6352, 6203 .name = "Marvell 88E6352", 6204 .num_databases = 4096, 6205 .num_macs = 8192, 6206 .num_ports = 7, 6207 .num_internal_phys = 5, 6208 .num_gpio = 15, 6209 .max_vid = 4095, 6210 .max_sid = 63, 6211 .port_base_addr = 0x10, 6212 .phy_base_addr = 0x0, 6213 .global1_addr = 0x1b, 6214 .global2_addr = 0x1c, 6215 .age_time_coeff = 15000, 6216 .g1_irqs = 9, 6217 .g2_irqs = 10, 6218 .atu_move_port_mask = 0xf, 6219 .pvt = true, 6220 .multi_chip = true, 6221 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6222 .ptp_support = true, 6223 .ops = &mv88e6352_ops, 6224 }, 6225 [MV88E6361] = { 6226 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6227 .family = MV88E6XXX_FAMILY_6393, 6228 .name = "Marvell 88E6361", 6229 .num_databases = 4096, 6230 .num_macs = 16384, 6231 .num_ports = 11, 6232 /* Ports 1, 2 and 8 are not routed */ 6233 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6234 .num_internal_phys = 5, 6235 .internal_phys_offset = 3, 6236 .max_vid = 4095, 6237 .max_sid = 63, 6238 .port_base_addr = 0x0, 6239 .phy_base_addr = 0x0, 6240 .global1_addr = 0x1b, 6241 .global2_addr = 0x1c, 6242 .age_time_coeff = 3750, 6243 .g1_irqs = 10, 6244 .g2_irqs = 14, 6245 .atu_move_port_mask = 0x1f, 6246 .pvt = true, 6247 .multi_chip = true, 6248 .ptp_support = true, 6249 .ops = &mv88e6393x_ops, 6250 }, 6251 [MV88E6390] = { 6252 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6253 .family = MV88E6XXX_FAMILY_6390, 6254 .name = "Marvell 88E6390", 6255 .num_databases = 4096, 6256 .num_macs = 16384, 6257 .num_ports = 11, /* 10 + Z80 */ 6258 .num_internal_phys = 9, 6259 .num_gpio = 16, 6260 .max_vid = 8191, 6261 .max_sid = 63, 6262 .port_base_addr = 0x0, 6263 .phy_base_addr = 0x0, 6264 .global1_addr = 0x1b, 6265 .global2_addr = 0x1c, 6266 .age_time_coeff = 3750, 6267 .g1_irqs = 9, 6268 .g2_irqs = 14, 6269 .atu_move_port_mask = 0x1f, 6270 .pvt = true, 6271 .multi_chip = true, 6272 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6273 .ptp_support = true, 6274 .ops = &mv88e6390_ops, 6275 }, 6276 [MV88E6390X] = { 6277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6278 .family = MV88E6XXX_FAMILY_6390, 6279 .name = "Marvell 88E6390X", 6280 .num_databases = 4096, 6281 .num_macs = 16384, 6282 .num_ports = 11, /* 10 + Z80 */ 6283 .num_internal_phys = 9, 6284 .num_gpio = 16, 6285 .max_vid = 8191, 6286 .max_sid = 63, 6287 .port_base_addr = 0x0, 6288 .phy_base_addr = 0x0, 6289 .global1_addr = 0x1b, 6290 .global2_addr = 0x1c, 6291 .age_time_coeff = 3750, 6292 .g1_irqs = 9, 6293 .g2_irqs = 14, 6294 .atu_move_port_mask = 0x1f, 6295 .pvt = true, 6296 .multi_chip = true, 6297 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6298 .ptp_support = true, 6299 .ops = &mv88e6390x_ops, 6300 }, 6301 6302 [MV88E6393X] = { 6303 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6304 .family = MV88E6XXX_FAMILY_6393, 6305 .name = "Marvell 88E6393X", 6306 .num_databases = 4096, 6307 .num_ports = 11, /* 10 + Z80 */ 6308 .num_internal_phys = 8, 6309 .internal_phys_offset = 1, 6310 .max_vid = 8191, 6311 .max_sid = 63, 6312 .port_base_addr = 0x0, 6313 .phy_base_addr = 0x0, 6314 .global1_addr = 0x1b, 6315 .global2_addr = 0x1c, 6316 .age_time_coeff = 3750, 6317 .g1_irqs = 10, 6318 .g2_irqs = 14, 6319 .atu_move_port_mask = 0x1f, 6320 .pvt = true, 6321 .multi_chip = true, 6322 .ptp_support = true, 6323 .ops = &mv88e6393x_ops, 6324 }, 6325 }; 6326 6327 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6328 { 6329 int i; 6330 6331 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6332 if (mv88e6xxx_table[i].prod_num == prod_num) 6333 return &mv88e6xxx_table[i]; 6334 6335 return NULL; 6336 } 6337 6338 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6339 { 6340 const struct mv88e6xxx_info *info; 6341 unsigned int prod_num, rev; 6342 u16 id; 6343 int err; 6344 6345 mv88e6xxx_reg_lock(chip); 6346 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6347 mv88e6xxx_reg_unlock(chip); 6348 if (err) 6349 return err; 6350 6351 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6352 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6353 6354 info = mv88e6xxx_lookup_info(prod_num); 6355 if (!info) 6356 return -ENODEV; 6357 6358 /* Update the compatible info with the probed one */ 6359 chip->info = info; 6360 6361 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6362 chip->info->prod_num, chip->info->name, rev); 6363 6364 return 0; 6365 } 6366 6367 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6368 struct mdio_device *mdiodev) 6369 { 6370 int err; 6371 6372 /* dual_chip takes precedence over single/multi-chip modes */ 6373 if (chip->info->dual_chip) 6374 return -EINVAL; 6375 6376 /* If the mdio addr is 16 indicating the first port address of a switch 6377 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6378 * configured in single chip addressing mode. Setup the smi access as 6379 * single chip addressing mode and attempt to detect the model of the 6380 * switch, if this fails the device is not configured in single chip 6381 * addressing mode. 6382 */ 6383 if (mdiodev->addr != 16) 6384 return -EINVAL; 6385 6386 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6387 if (err) 6388 return err; 6389 6390 return mv88e6xxx_detect(chip); 6391 } 6392 6393 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6394 { 6395 struct mv88e6xxx_chip *chip; 6396 6397 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6398 if (!chip) 6399 return NULL; 6400 6401 chip->dev = dev; 6402 6403 mutex_init(&chip->reg_lock); 6404 INIT_LIST_HEAD(&chip->mdios); 6405 idr_init(&chip->policies); 6406 INIT_LIST_HEAD(&chip->msts); 6407 6408 return chip; 6409 } 6410 6411 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6412 int port, 6413 enum dsa_tag_protocol m) 6414 { 6415 struct mv88e6xxx_chip *chip = ds->priv; 6416 6417 return chip->tag_protocol; 6418 } 6419 6420 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6421 enum dsa_tag_protocol proto) 6422 { 6423 struct mv88e6xxx_chip *chip = ds->priv; 6424 enum dsa_tag_protocol old_protocol; 6425 struct dsa_port *cpu_dp; 6426 int err; 6427 6428 switch (proto) { 6429 case DSA_TAG_PROTO_EDSA: 6430 switch (chip->info->edsa_support) { 6431 case MV88E6XXX_EDSA_UNSUPPORTED: 6432 return -EPROTONOSUPPORT; 6433 case MV88E6XXX_EDSA_UNDOCUMENTED: 6434 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6435 fallthrough; 6436 case MV88E6XXX_EDSA_SUPPORTED: 6437 break; 6438 } 6439 break; 6440 case DSA_TAG_PROTO_DSA: 6441 break; 6442 default: 6443 return -EPROTONOSUPPORT; 6444 } 6445 6446 old_protocol = chip->tag_protocol; 6447 chip->tag_protocol = proto; 6448 6449 mv88e6xxx_reg_lock(chip); 6450 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6451 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6452 if (err) { 6453 mv88e6xxx_reg_unlock(chip); 6454 goto unwind; 6455 } 6456 } 6457 mv88e6xxx_reg_unlock(chip); 6458 6459 return 0; 6460 6461 unwind: 6462 chip->tag_protocol = old_protocol; 6463 6464 mv88e6xxx_reg_lock(chip); 6465 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6466 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6467 mv88e6xxx_reg_unlock(chip); 6468 6469 return err; 6470 } 6471 6472 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6473 const struct switchdev_obj_port_mdb *mdb, 6474 struct dsa_db db) 6475 { 6476 struct mv88e6xxx_chip *chip = ds->priv; 6477 int err; 6478 6479 mv88e6xxx_reg_lock(chip); 6480 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6481 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6482 mv88e6xxx_reg_unlock(chip); 6483 6484 return err; 6485 } 6486 6487 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6488 const struct switchdev_obj_port_mdb *mdb, 6489 struct dsa_db db) 6490 { 6491 struct mv88e6xxx_chip *chip = ds->priv; 6492 int err; 6493 6494 mv88e6xxx_reg_lock(chip); 6495 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6496 mv88e6xxx_reg_unlock(chip); 6497 6498 return err; 6499 } 6500 6501 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6502 struct dsa_mall_mirror_tc_entry *mirror, 6503 bool ingress, 6504 struct netlink_ext_ack *extack) 6505 { 6506 enum mv88e6xxx_egress_direction direction = ingress ? 6507 MV88E6XXX_EGRESS_DIR_INGRESS : 6508 MV88E6XXX_EGRESS_DIR_EGRESS; 6509 struct mv88e6xxx_chip *chip = ds->priv; 6510 bool other_mirrors = false; 6511 int i; 6512 int err; 6513 6514 mutex_lock(&chip->reg_lock); 6515 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6516 mirror->to_local_port) { 6517 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6518 other_mirrors |= ingress ? 6519 chip->ports[i].mirror_ingress : 6520 chip->ports[i].mirror_egress; 6521 6522 /* Can't change egress port when other mirror is active */ 6523 if (other_mirrors) { 6524 err = -EBUSY; 6525 goto out; 6526 } 6527 6528 err = mv88e6xxx_set_egress_port(chip, direction, 6529 mirror->to_local_port); 6530 if (err) 6531 goto out; 6532 } 6533 6534 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6535 out: 6536 mutex_unlock(&chip->reg_lock); 6537 6538 return err; 6539 } 6540 6541 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6542 struct dsa_mall_mirror_tc_entry *mirror) 6543 { 6544 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6545 MV88E6XXX_EGRESS_DIR_INGRESS : 6546 MV88E6XXX_EGRESS_DIR_EGRESS; 6547 struct mv88e6xxx_chip *chip = ds->priv; 6548 bool other_mirrors = false; 6549 int i; 6550 6551 mutex_lock(&chip->reg_lock); 6552 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6553 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6554 6555 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6556 other_mirrors |= mirror->ingress ? 6557 chip->ports[i].mirror_ingress : 6558 chip->ports[i].mirror_egress; 6559 6560 /* Reset egress port when no other mirror is active */ 6561 if (!other_mirrors) { 6562 if (mv88e6xxx_set_egress_port(chip, direction, 6563 dsa_upstream_port(ds, port))) 6564 dev_err(ds->dev, "failed to set egress port\n"); 6565 } 6566 6567 mutex_unlock(&chip->reg_lock); 6568 } 6569 6570 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6571 struct switchdev_brport_flags flags, 6572 struct netlink_ext_ack *extack) 6573 { 6574 struct mv88e6xxx_chip *chip = ds->priv; 6575 const struct mv88e6xxx_ops *ops; 6576 6577 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6578 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6579 return -EINVAL; 6580 6581 ops = chip->info->ops; 6582 6583 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6584 return -EINVAL; 6585 6586 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6587 return -EINVAL; 6588 6589 return 0; 6590 } 6591 6592 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6593 struct switchdev_brport_flags flags, 6594 struct netlink_ext_ack *extack) 6595 { 6596 struct mv88e6xxx_chip *chip = ds->priv; 6597 int err = 0; 6598 6599 mv88e6xxx_reg_lock(chip); 6600 6601 if (flags.mask & BR_LEARNING) { 6602 bool learning = !!(flags.val & BR_LEARNING); 6603 u16 pav = learning ? (1 << port) : 0; 6604 6605 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6606 if (err) 6607 goto out; 6608 } 6609 6610 if (flags.mask & BR_FLOOD) { 6611 bool unicast = !!(flags.val & BR_FLOOD); 6612 6613 err = chip->info->ops->port_set_ucast_flood(chip, port, 6614 unicast); 6615 if (err) 6616 goto out; 6617 } 6618 6619 if (flags.mask & BR_MCAST_FLOOD) { 6620 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6621 6622 err = chip->info->ops->port_set_mcast_flood(chip, port, 6623 multicast); 6624 if (err) 6625 goto out; 6626 } 6627 6628 if (flags.mask & BR_BCAST_FLOOD) { 6629 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6630 6631 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6632 if (err) 6633 goto out; 6634 } 6635 6636 if (flags.mask & BR_PORT_MAB) { 6637 bool mab = !!(flags.val & BR_PORT_MAB); 6638 6639 mv88e6xxx_port_set_mab(chip, port, mab); 6640 } 6641 6642 if (flags.mask & BR_PORT_LOCKED) { 6643 bool locked = !!(flags.val & BR_PORT_LOCKED); 6644 6645 err = mv88e6xxx_port_set_lock(chip, port, locked); 6646 if (err) 6647 goto out; 6648 } 6649 out: 6650 mv88e6xxx_reg_unlock(chip); 6651 6652 return err; 6653 } 6654 6655 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6656 struct dsa_lag lag, 6657 struct netdev_lag_upper_info *info, 6658 struct netlink_ext_ack *extack) 6659 { 6660 struct mv88e6xxx_chip *chip = ds->priv; 6661 struct dsa_port *dp; 6662 int members = 0; 6663 6664 if (!mv88e6xxx_has_lag(chip)) { 6665 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6666 return false; 6667 } 6668 6669 if (!lag.id) 6670 return false; 6671 6672 dsa_lag_foreach_port(dp, ds->dst, &lag) 6673 /* Includes the port joining the LAG */ 6674 members++; 6675 6676 if (members > 8) { 6677 NL_SET_ERR_MSG_MOD(extack, 6678 "Cannot offload more than 8 LAG ports"); 6679 return false; 6680 } 6681 6682 /* We could potentially relax this to include active 6683 * backup in the future. 6684 */ 6685 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6686 NL_SET_ERR_MSG_MOD(extack, 6687 "Can only offload LAG using hash TX type"); 6688 return false; 6689 } 6690 6691 /* Ideally we would also validate that the hash type matches 6692 * the hardware. Alas, this is always set to unknown on team 6693 * interfaces. 6694 */ 6695 return true; 6696 } 6697 6698 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6699 { 6700 struct mv88e6xxx_chip *chip = ds->priv; 6701 struct dsa_port *dp; 6702 u16 map = 0; 6703 int id; 6704 6705 /* DSA LAG IDs are one-based, hardware is zero-based */ 6706 id = lag.id - 1; 6707 6708 /* Build the map of all ports to distribute flows destined for 6709 * this LAG. This can be either a local user port, or a DSA 6710 * port if the LAG port is on a remote chip. 6711 */ 6712 dsa_lag_foreach_port(dp, ds->dst, &lag) 6713 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6714 6715 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6716 } 6717 6718 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6719 /* Row number corresponds to the number of active members in a 6720 * LAG. Each column states which of the eight hash buckets are 6721 * mapped to the column:th port in the LAG. 6722 * 6723 * Example: In a LAG with three active ports, the second port 6724 * ([2][1]) would be selected for traffic mapped to buckets 6725 * 3,4,5 (0x38). 6726 */ 6727 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6728 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6729 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6730 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6731 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6732 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6733 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6734 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6735 }; 6736 6737 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6738 int num_tx, int nth) 6739 { 6740 u8 active = 0; 6741 int i; 6742 6743 num_tx = num_tx <= 8 ? num_tx : 8; 6744 if (nth < num_tx) 6745 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6746 6747 for (i = 0; i < 8; i++) { 6748 if (BIT(i) & active) 6749 mask[i] |= BIT(port); 6750 } 6751 } 6752 6753 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6754 { 6755 struct mv88e6xxx_chip *chip = ds->priv; 6756 unsigned int id, num_tx; 6757 struct dsa_port *dp; 6758 struct dsa_lag *lag; 6759 int i, err, nth; 6760 u16 mask[8]; 6761 u16 ivec; 6762 6763 /* Assume no port is a member of any LAG. */ 6764 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6765 6766 /* Disable all masks for ports that _are_ members of a LAG. */ 6767 dsa_switch_for_each_port(dp, ds) { 6768 if (!dp->lag) 6769 continue; 6770 6771 ivec &= ~BIT(dp->index); 6772 } 6773 6774 for (i = 0; i < 8; i++) 6775 mask[i] = ivec; 6776 6777 /* Enable the correct subset of masks for all LAG ports that 6778 * are in the Tx set. 6779 */ 6780 dsa_lags_foreach_id(id, ds->dst) { 6781 lag = dsa_lag_by_id(ds->dst, id); 6782 if (!lag) 6783 continue; 6784 6785 num_tx = 0; 6786 dsa_lag_foreach_port(dp, ds->dst, lag) { 6787 if (dp->lag_tx_enabled) 6788 num_tx++; 6789 } 6790 6791 if (!num_tx) 6792 continue; 6793 6794 nth = 0; 6795 dsa_lag_foreach_port(dp, ds->dst, lag) { 6796 if (!dp->lag_tx_enabled) 6797 continue; 6798 6799 if (dp->ds == ds) 6800 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6801 num_tx, nth); 6802 6803 nth++; 6804 } 6805 } 6806 6807 for (i = 0; i < 8; i++) { 6808 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6809 if (err) 6810 return err; 6811 } 6812 6813 return 0; 6814 } 6815 6816 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6817 struct dsa_lag lag) 6818 { 6819 int err; 6820 6821 err = mv88e6xxx_lag_sync_masks(ds); 6822 6823 if (!err) 6824 err = mv88e6xxx_lag_sync_map(ds, lag); 6825 6826 return err; 6827 } 6828 6829 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6830 { 6831 struct mv88e6xxx_chip *chip = ds->priv; 6832 int err; 6833 6834 mv88e6xxx_reg_lock(chip); 6835 err = mv88e6xxx_lag_sync_masks(ds); 6836 mv88e6xxx_reg_unlock(chip); 6837 return err; 6838 } 6839 6840 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6841 struct dsa_lag lag, 6842 struct netdev_lag_upper_info *info, 6843 struct netlink_ext_ack *extack) 6844 { 6845 struct mv88e6xxx_chip *chip = ds->priv; 6846 int err, id; 6847 6848 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6849 return -EOPNOTSUPP; 6850 6851 /* DSA LAG IDs are one-based */ 6852 id = lag.id - 1; 6853 6854 mv88e6xxx_reg_lock(chip); 6855 6856 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6857 if (err) 6858 goto err_unlock; 6859 6860 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6861 if (err) 6862 goto err_clear_trunk; 6863 6864 mv88e6xxx_reg_unlock(chip); 6865 return 0; 6866 6867 err_clear_trunk: 6868 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6869 err_unlock: 6870 mv88e6xxx_reg_unlock(chip); 6871 return err; 6872 } 6873 6874 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6875 struct dsa_lag lag) 6876 { 6877 struct mv88e6xxx_chip *chip = ds->priv; 6878 int err_sync, err_trunk; 6879 6880 mv88e6xxx_reg_lock(chip); 6881 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6882 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6883 mv88e6xxx_reg_unlock(chip); 6884 return err_sync ? : err_trunk; 6885 } 6886 6887 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6888 int port) 6889 { 6890 struct mv88e6xxx_chip *chip = ds->priv; 6891 int err; 6892 6893 mv88e6xxx_reg_lock(chip); 6894 err = mv88e6xxx_lag_sync_masks(ds); 6895 mv88e6xxx_reg_unlock(chip); 6896 return err; 6897 } 6898 6899 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6900 int port, struct dsa_lag lag, 6901 struct netdev_lag_upper_info *info, 6902 struct netlink_ext_ack *extack) 6903 { 6904 struct mv88e6xxx_chip *chip = ds->priv; 6905 int err; 6906 6907 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6908 return -EOPNOTSUPP; 6909 6910 mv88e6xxx_reg_lock(chip); 6911 6912 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6913 if (err) 6914 goto unlock; 6915 6916 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6917 6918 unlock: 6919 mv88e6xxx_reg_unlock(chip); 6920 return err; 6921 } 6922 6923 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6924 int port, struct dsa_lag lag) 6925 { 6926 struct mv88e6xxx_chip *chip = ds->priv; 6927 int err_sync, err_pvt; 6928 6929 mv88e6xxx_reg_lock(chip); 6930 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6931 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6932 mv88e6xxx_reg_unlock(chip); 6933 return err_sync ? : err_pvt; 6934 } 6935 6936 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 6937 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 6938 .mac_prepare = mv88e6xxx_mac_prepare, 6939 .mac_config = mv88e6xxx_mac_config, 6940 .mac_finish = mv88e6xxx_mac_finish, 6941 .mac_link_down = mv88e6xxx_mac_link_down, 6942 .mac_link_up = mv88e6xxx_mac_link_up, 6943 }; 6944 6945 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6946 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6947 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6948 .setup = mv88e6xxx_setup, 6949 .teardown = mv88e6xxx_teardown, 6950 .port_setup = mv88e6xxx_port_setup, 6951 .port_teardown = mv88e6xxx_port_teardown, 6952 .phylink_get_caps = mv88e6xxx_get_caps, 6953 .get_strings = mv88e6xxx_get_strings, 6954 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6955 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 6956 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 6957 .get_sset_count = mv88e6xxx_get_sset_count, 6958 .port_max_mtu = mv88e6xxx_get_max_mtu, 6959 .port_change_mtu = mv88e6xxx_change_mtu, 6960 .get_mac_eee = mv88e6xxx_get_mac_eee, 6961 .set_mac_eee = mv88e6xxx_set_mac_eee, 6962 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6963 .get_eeprom = mv88e6xxx_get_eeprom, 6964 .set_eeprom = mv88e6xxx_set_eeprom, 6965 .get_regs_len = mv88e6xxx_get_regs_len, 6966 .get_regs = mv88e6xxx_get_regs, 6967 .get_rxnfc = mv88e6xxx_get_rxnfc, 6968 .set_rxnfc = mv88e6xxx_set_rxnfc, 6969 .set_ageing_time = mv88e6xxx_set_ageing_time, 6970 .port_bridge_join = mv88e6xxx_port_bridge_join, 6971 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6972 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6973 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6974 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6975 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6976 .port_fast_age = mv88e6xxx_port_fast_age, 6977 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6978 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6979 .port_vlan_add = mv88e6xxx_port_vlan_add, 6980 .port_vlan_del = mv88e6xxx_port_vlan_del, 6981 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6982 .port_fdb_add = mv88e6xxx_port_fdb_add, 6983 .port_fdb_del = mv88e6xxx_port_fdb_del, 6984 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6985 .port_mdb_add = mv88e6xxx_port_mdb_add, 6986 .port_mdb_del = mv88e6xxx_port_mdb_del, 6987 .port_mirror_add = mv88e6xxx_port_mirror_add, 6988 .port_mirror_del = mv88e6xxx_port_mirror_del, 6989 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6990 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6991 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6992 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6993 .port_txtstamp = mv88e6xxx_port_txtstamp, 6994 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6995 .get_ts_info = mv88e6xxx_get_ts_info, 6996 .devlink_param_get = mv88e6xxx_devlink_param_get, 6997 .devlink_param_set = mv88e6xxx_devlink_param_set, 6998 .devlink_info_get = mv88e6xxx_devlink_info_get, 6999 .port_lag_change = mv88e6xxx_port_lag_change, 7000 .port_lag_join = mv88e6xxx_port_lag_join, 7001 .port_lag_leave = mv88e6xxx_port_lag_leave, 7002 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7003 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7004 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7005 }; 7006 7007 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7008 { 7009 struct device *dev = chip->dev; 7010 struct dsa_switch *ds; 7011 7012 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7013 if (!ds) 7014 return -ENOMEM; 7015 7016 ds->dev = dev; 7017 ds->num_ports = mv88e6xxx_num_ports(chip); 7018 ds->priv = chip; 7019 ds->dev = dev; 7020 ds->ops = &mv88e6xxx_switch_ops; 7021 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7022 ds->ageing_time_min = chip->info->age_time_coeff; 7023 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7024 7025 /* Some chips support up to 32, but that requires enabling the 7026 * 5-bit port mode, which we do not support. 640k^W16 ought to 7027 * be enough for anyone. 7028 */ 7029 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7030 7031 dev_set_drvdata(dev, ds); 7032 7033 return dsa_register_switch(ds); 7034 } 7035 7036 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7037 { 7038 dsa_unregister_switch(chip->ds); 7039 } 7040 7041 static const void *pdata_device_get_match_data(struct device *dev) 7042 { 7043 const struct of_device_id *matches = dev->driver->of_match_table; 7044 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7045 7046 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7047 matches++) { 7048 if (!strcmp(pdata->compatible, matches->compatible)) 7049 return matches->data; 7050 } 7051 return NULL; 7052 } 7053 7054 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7055 * would be lost after a power cycle so prevent it to be suspended. 7056 */ 7057 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7058 { 7059 return -EOPNOTSUPP; 7060 } 7061 7062 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7063 { 7064 return 0; 7065 } 7066 7067 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7068 7069 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7070 { 7071 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7072 const struct mv88e6xxx_info *compat_info = NULL; 7073 struct device *dev = &mdiodev->dev; 7074 struct device_node *np = dev->of_node; 7075 struct mv88e6xxx_chip *chip; 7076 int port; 7077 int err; 7078 7079 if (!np && !pdata) 7080 return -EINVAL; 7081 7082 if (np) 7083 compat_info = of_device_get_match_data(dev); 7084 7085 if (pdata) { 7086 compat_info = pdata_device_get_match_data(dev); 7087 7088 if (!pdata->netdev) 7089 return -EINVAL; 7090 7091 for (port = 0; port < DSA_MAX_PORTS; port++) { 7092 if (!(pdata->enabled_ports & (1 << port))) 7093 continue; 7094 if (strcmp(pdata->cd.port_names[port], "cpu")) 7095 continue; 7096 pdata->cd.netdev[port] = &pdata->netdev->dev; 7097 break; 7098 } 7099 } 7100 7101 if (!compat_info) 7102 return -EINVAL; 7103 7104 chip = mv88e6xxx_alloc_chip(dev); 7105 if (!chip) { 7106 err = -ENOMEM; 7107 goto out; 7108 } 7109 7110 chip->info = compat_info; 7111 7112 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7113 if (IS_ERR(chip->reset)) { 7114 err = PTR_ERR(chip->reset); 7115 goto out; 7116 } 7117 if (chip->reset) 7118 usleep_range(10000, 20000); 7119 7120 /* Detect if the device is configured in single chip addressing mode, 7121 * otherwise continue with address specific smi init/detection. 7122 */ 7123 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7124 if (err) { 7125 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7126 if (err) 7127 goto out; 7128 7129 err = mv88e6xxx_detect(chip); 7130 if (err) 7131 goto out; 7132 } 7133 7134 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7135 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7136 else 7137 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7138 7139 mv88e6xxx_phy_init(chip); 7140 7141 if (chip->info->ops->get_eeprom) { 7142 if (np) 7143 of_property_read_u32(np, "eeprom-length", 7144 &chip->eeprom_len); 7145 else 7146 chip->eeprom_len = pdata->eeprom_len; 7147 } 7148 7149 mv88e6xxx_reg_lock(chip); 7150 err = mv88e6xxx_switch_reset(chip); 7151 mv88e6xxx_reg_unlock(chip); 7152 if (err) 7153 goto out; 7154 7155 if (np) { 7156 chip->irq = of_irq_get(np, 0); 7157 if (chip->irq == -EPROBE_DEFER) { 7158 err = chip->irq; 7159 goto out; 7160 } 7161 } 7162 7163 if (pdata) 7164 chip->irq = pdata->irq; 7165 7166 /* Has to be performed before the MDIO bus is created, because 7167 * the PHYs will link their interrupts to these interrupt 7168 * controllers 7169 */ 7170 mv88e6xxx_reg_lock(chip); 7171 if (chip->irq > 0) 7172 err = mv88e6xxx_g1_irq_setup(chip); 7173 else 7174 err = mv88e6xxx_irq_poll_setup(chip); 7175 mv88e6xxx_reg_unlock(chip); 7176 7177 if (err) 7178 goto out; 7179 7180 if (chip->info->g2_irqs > 0) { 7181 err = mv88e6xxx_g2_irq_setup(chip); 7182 if (err) 7183 goto out_g1_irq; 7184 } 7185 7186 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7187 if (err) 7188 goto out_g2_irq; 7189 7190 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7191 if (err) 7192 goto out_g1_atu_prob_irq; 7193 7194 err = mv88e6xxx_register_switch(chip); 7195 if (err) 7196 goto out_g1_vtu_prob_irq; 7197 7198 return 0; 7199 7200 out_g1_vtu_prob_irq: 7201 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7202 out_g1_atu_prob_irq: 7203 mv88e6xxx_g1_atu_prob_irq_free(chip); 7204 out_g2_irq: 7205 if (chip->info->g2_irqs > 0) 7206 mv88e6xxx_g2_irq_free(chip); 7207 out_g1_irq: 7208 if (chip->irq > 0) 7209 mv88e6xxx_g1_irq_free(chip); 7210 else 7211 mv88e6xxx_irq_poll_free(chip); 7212 out: 7213 if (pdata) 7214 dev_put(pdata->netdev); 7215 7216 return err; 7217 } 7218 7219 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7220 { 7221 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7222 struct mv88e6xxx_chip *chip; 7223 7224 if (!ds) 7225 return; 7226 7227 chip = ds->priv; 7228 7229 if (chip->info->ptp_support) { 7230 mv88e6xxx_hwtstamp_free(chip); 7231 mv88e6xxx_ptp_free(chip); 7232 } 7233 7234 mv88e6xxx_phy_destroy(chip); 7235 mv88e6xxx_unregister_switch(chip); 7236 7237 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7238 mv88e6xxx_g1_atu_prob_irq_free(chip); 7239 7240 if (chip->info->g2_irqs > 0) 7241 mv88e6xxx_g2_irq_free(chip); 7242 7243 if (chip->irq > 0) 7244 mv88e6xxx_g1_irq_free(chip); 7245 else 7246 mv88e6xxx_irq_poll_free(chip); 7247 } 7248 7249 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7250 { 7251 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7252 7253 if (!ds) 7254 return; 7255 7256 dsa_switch_shutdown(ds); 7257 7258 dev_set_drvdata(&mdiodev->dev, NULL); 7259 } 7260 7261 static const struct of_device_id mv88e6xxx_of_match[] = { 7262 { 7263 .compatible = "marvell,mv88e6085", 7264 .data = &mv88e6xxx_table[MV88E6085], 7265 }, 7266 { 7267 .compatible = "marvell,mv88e6190", 7268 .data = &mv88e6xxx_table[MV88E6190], 7269 }, 7270 { 7271 .compatible = "marvell,mv88e6250", 7272 .data = &mv88e6xxx_table[MV88E6250], 7273 }, 7274 { /* sentinel */ }, 7275 }; 7276 7277 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7278 7279 static struct mdio_driver mv88e6xxx_driver = { 7280 .probe = mv88e6xxx_probe, 7281 .remove = mv88e6xxx_remove, 7282 .shutdown = mv88e6xxx_shutdown, 7283 .mdiodrv.driver = { 7284 .name = "mv88e6085", 7285 .of_match_table = mv88e6xxx_of_match, 7286 .pm = &mv88e6xxx_pm_ops, 7287 }, 7288 }; 7289 7290 mdio_module_driver(mv88e6xxx_driver); 7291 7292 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7293 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7294 MODULE_LICENSE("GPL"); 7295