1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 936 { 937 if (chip->info->ops->set_switch_mac) { 938 u8 addr[ETH_ALEN]; 939 940 eth_random_addr(addr); 941 942 return chip->info->ops->set_switch_mac(chip, addr); 943 } 944 945 return 0; 946 } 947 948 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 949 { 950 u16 pvlan = 0; 951 952 if (!mv88e6xxx_has_pvt(chip)) 953 return -EOPNOTSUPP; 954 955 /* Skip the local source device, which uses in-chip port VLAN */ 956 if (dev != chip->ds->index) 957 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 958 959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 960 } 961 962 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 963 { 964 int dev, port; 965 int err; 966 967 if (!mv88e6xxx_has_pvt(chip)) 968 return 0; 969 970 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 972 */ 973 err = mv88e6xxx_g2_misc_4_bit_port(chip); 974 if (err) 975 return err; 976 977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 979 err = mv88e6xxx_pvt_map(chip, dev, port); 980 if (err) 981 return err; 982 } 983 } 984 985 return 0; 986 } 987 988 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int err; 992 993 mutex_lock(&chip->reg_lock); 994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 995 mutex_unlock(&chip->reg_lock); 996 997 if (err) 998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 999 } 1000 1001 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1002 { 1003 if (!chip->info->max_vid) 1004 return 0; 1005 1006 return mv88e6xxx_g1_vtu_flush(chip); 1007 } 1008 1009 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1010 struct mv88e6xxx_vtu_entry *entry) 1011 { 1012 if (!chip->info->ops->vtu_getnext) 1013 return -EOPNOTSUPP; 1014 1015 return chip->info->ops->vtu_getnext(chip, entry); 1016 } 1017 1018 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1019 struct mv88e6xxx_vtu_entry *entry) 1020 { 1021 if (!chip->info->ops->vtu_loadpurge) 1022 return -EOPNOTSUPP; 1023 1024 return chip->info->ops->vtu_loadpurge(chip, entry); 1025 } 1026 1027 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1028 { 1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1030 struct mv88e6xxx_vtu_entry vlan = { 1031 .vid = chip->info->max_vid, 1032 }; 1033 int i, err; 1034 1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1036 1037 /* Set every FID bit used by the (un)bridged ports */ 1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1039 err = mv88e6xxx_port_get_fid(chip, i, fid); 1040 if (err) 1041 return err; 1042 1043 set_bit(*fid, fid_bitmap); 1044 } 1045 1046 /* Set every FID bit used by the VLAN entries */ 1047 do { 1048 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1049 if (err) 1050 return err; 1051 1052 if (!vlan.valid) 1053 break; 1054 1055 set_bit(vlan.fid, fid_bitmap); 1056 } while (vlan.vid < chip->info->max_vid); 1057 1058 /* The reset value 0x000 is used to indicate that multiple address 1059 * databases are not needed. Return the next positive available. 1060 */ 1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1063 return -ENOSPC; 1064 1065 /* Clear the database */ 1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1067 } 1068 1069 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1070 struct mv88e6xxx_vtu_entry *entry, bool new) 1071 { 1072 int err; 1073 1074 if (!vid) 1075 return -EINVAL; 1076 1077 entry->vid = vid - 1; 1078 entry->valid = false; 1079 1080 err = mv88e6xxx_vtu_getnext(chip, entry); 1081 if (err) 1082 return err; 1083 1084 if (entry->vid == vid && entry->valid) 1085 return 0; 1086 1087 if (new) { 1088 int i; 1089 1090 /* Initialize a fresh VLAN entry */ 1091 memset(entry, 0, sizeof(*entry)); 1092 entry->valid = true; 1093 entry->vid = vid; 1094 1095 /* Exclude all ports */ 1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1097 entry->member[i] = 1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1099 1100 return mv88e6xxx_atu_new(chip, &entry->fid); 1101 } 1102 1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1104 return -EOPNOTSUPP; 1105 } 1106 1107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1108 u16 vid_begin, u16 vid_end) 1109 { 1110 struct mv88e6xxx_chip *chip = ds->priv; 1111 struct mv88e6xxx_vtu_entry vlan = { 1112 .vid = vid_begin - 1, 1113 }; 1114 int i, err; 1115 1116 /* DSA and CPU ports have to be members of multiple vlans */ 1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1118 return 0; 1119 1120 if (!vid_begin) 1121 return -EOPNOTSUPP; 1122 1123 mutex_lock(&chip->reg_lock); 1124 1125 do { 1126 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1127 if (err) 1128 goto unlock; 1129 1130 if (!vlan.valid) 1131 break; 1132 1133 if (vlan.vid > vid_end) 1134 break; 1135 1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1138 continue; 1139 1140 if (!ds->ports[port].slave) 1141 continue; 1142 1143 if (vlan.member[i] == 1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1145 continue; 1146 1147 if (dsa_to_port(ds, i)->bridge_dev == 1148 ds->ports[port].bridge_dev) 1149 break; /* same bridge, check next VLAN */ 1150 1151 if (!dsa_to_port(ds, i)->bridge_dev) 1152 continue; 1153 1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", 1155 port, vlan.vid, 1156 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1157 err = -EOPNOTSUPP; 1158 goto unlock; 1159 } 1160 } while (vlan.vid < vid_end); 1161 1162 unlock: 1163 mutex_unlock(&chip->reg_lock); 1164 1165 return err; 1166 } 1167 1168 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1169 bool vlan_filtering) 1170 { 1171 struct mv88e6xxx_chip *chip = ds->priv; 1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1174 int err; 1175 1176 if (!chip->info->max_vid) 1177 return -EOPNOTSUPP; 1178 1179 mutex_lock(&chip->reg_lock); 1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1181 mutex_unlock(&chip->reg_lock); 1182 1183 return err; 1184 } 1185 1186 static int 1187 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1188 const struct switchdev_obj_port_vlan *vlan, 1189 struct switchdev_trans *trans) 1190 { 1191 struct mv88e6xxx_chip *chip = ds->priv; 1192 int err; 1193 1194 if (!chip->info->max_vid) 1195 return -EOPNOTSUPP; 1196 1197 /* If the requested port doesn't belong to the same bridge as the VLAN 1198 * members, do not support it (yet) and fallback to software VLAN. 1199 */ 1200 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1201 vlan->vid_end); 1202 if (err) 1203 return err; 1204 1205 /* We don't need any dynamic resource from the kernel (yet), 1206 * so skip the prepare phase. 1207 */ 1208 return 0; 1209 } 1210 1211 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1212 u16 vid, u8 member) 1213 { 1214 struct mv88e6xxx_vtu_entry vlan; 1215 int err; 1216 1217 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1218 if (err) 1219 return err; 1220 1221 vlan.member[port] = member; 1222 1223 return mv88e6xxx_vtu_loadpurge(chip, &vlan); 1224 } 1225 1226 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1227 const struct switchdev_obj_port_vlan *vlan, 1228 struct switchdev_trans *trans) 1229 { 1230 struct mv88e6xxx_chip *chip = ds->priv; 1231 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1232 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1233 u8 member; 1234 u16 vid; 1235 1236 if (!chip->info->max_vid) 1237 return; 1238 1239 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1240 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1241 else if (untagged) 1242 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1243 else 1244 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1245 1246 mutex_lock(&chip->reg_lock); 1247 1248 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1249 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1250 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1251 vid, untagged ? 'u' : 't'); 1252 1253 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1254 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1255 vlan->vid_end); 1256 1257 mutex_unlock(&chip->reg_lock); 1258 } 1259 1260 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1261 int port, u16 vid) 1262 { 1263 struct mv88e6xxx_vtu_entry vlan; 1264 int i, err; 1265 1266 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1267 if (err) 1268 return err; 1269 1270 /* Tell switchdev if this VLAN is handled in software */ 1271 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1272 return -EOPNOTSUPP; 1273 1274 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1275 1276 /* keep the VLAN unless all ports are excluded */ 1277 vlan.valid = false; 1278 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1279 if (vlan.member[i] != 1280 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1281 vlan.valid = true; 1282 break; 1283 } 1284 } 1285 1286 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1287 if (err) 1288 return err; 1289 1290 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1291 } 1292 1293 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1294 const struct switchdev_obj_port_vlan *vlan) 1295 { 1296 struct mv88e6xxx_chip *chip = ds->priv; 1297 u16 pvid, vid; 1298 int err = 0; 1299 1300 if (!chip->info->max_vid) 1301 return -EOPNOTSUPP; 1302 1303 mutex_lock(&chip->reg_lock); 1304 1305 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1306 if (err) 1307 goto unlock; 1308 1309 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1310 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1311 if (err) 1312 goto unlock; 1313 1314 if (vid == pvid) { 1315 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1316 if (err) 1317 goto unlock; 1318 } 1319 } 1320 1321 unlock: 1322 mutex_unlock(&chip->reg_lock); 1323 1324 return err; 1325 } 1326 1327 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1328 const unsigned char *addr, u16 vid, 1329 u8 state) 1330 { 1331 struct mv88e6xxx_vtu_entry vlan; 1332 struct mv88e6xxx_atu_entry entry; 1333 int err; 1334 1335 /* Null VLAN ID corresponds to the port private database */ 1336 if (vid == 0) 1337 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1338 else 1339 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1340 if (err) 1341 return err; 1342 1343 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1344 ether_addr_copy(entry.mac, addr); 1345 eth_addr_dec(entry.mac); 1346 1347 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1348 if (err) 1349 return err; 1350 1351 /* Initialize a fresh ATU entry if it isn't found */ 1352 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1353 !ether_addr_equal(entry.mac, addr)) { 1354 memset(&entry, 0, sizeof(entry)); 1355 ether_addr_copy(entry.mac, addr); 1356 } 1357 1358 /* Purge the ATU entry only if no port is using it anymore */ 1359 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1360 entry.portvec &= ~BIT(port); 1361 if (!entry.portvec) 1362 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1363 } else { 1364 entry.portvec |= BIT(port); 1365 entry.state = state; 1366 } 1367 1368 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1369 } 1370 1371 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1372 const unsigned char *addr, u16 vid) 1373 { 1374 struct mv88e6xxx_chip *chip = ds->priv; 1375 int err; 1376 1377 mutex_lock(&chip->reg_lock); 1378 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1379 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1380 mutex_unlock(&chip->reg_lock); 1381 1382 return err; 1383 } 1384 1385 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1386 const unsigned char *addr, u16 vid) 1387 { 1388 struct mv88e6xxx_chip *chip = ds->priv; 1389 int err; 1390 1391 mutex_lock(&chip->reg_lock); 1392 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1393 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1394 mutex_unlock(&chip->reg_lock); 1395 1396 return err; 1397 } 1398 1399 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1400 u16 fid, u16 vid, int port, 1401 dsa_fdb_dump_cb_t *cb, void *data) 1402 { 1403 struct mv88e6xxx_atu_entry addr; 1404 bool is_static; 1405 int err; 1406 1407 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1408 eth_broadcast_addr(addr.mac); 1409 1410 do { 1411 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1412 if (err) 1413 return err; 1414 1415 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1416 break; 1417 1418 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1419 continue; 1420 1421 if (!is_unicast_ether_addr(addr.mac)) 1422 continue; 1423 1424 is_static = (addr.state == 1425 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1426 err = cb(addr.mac, vid, is_static, data); 1427 if (err) 1428 return err; 1429 } while (!is_broadcast_ether_addr(addr.mac)); 1430 1431 return err; 1432 } 1433 1434 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1435 dsa_fdb_dump_cb_t *cb, void *data) 1436 { 1437 struct mv88e6xxx_vtu_entry vlan = { 1438 .vid = chip->info->max_vid, 1439 }; 1440 u16 fid; 1441 int err; 1442 1443 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1444 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1445 if (err) 1446 return err; 1447 1448 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1449 if (err) 1450 return err; 1451 1452 /* Dump VLANs' Filtering Information Databases */ 1453 do { 1454 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1455 if (err) 1456 return err; 1457 1458 if (!vlan.valid) 1459 break; 1460 1461 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1462 cb, data); 1463 if (err) 1464 return err; 1465 } while (vlan.vid < chip->info->max_vid); 1466 1467 return err; 1468 } 1469 1470 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1471 dsa_fdb_dump_cb_t *cb, void *data) 1472 { 1473 struct mv88e6xxx_chip *chip = ds->priv; 1474 int err; 1475 1476 mutex_lock(&chip->reg_lock); 1477 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1478 mutex_unlock(&chip->reg_lock); 1479 1480 return err; 1481 } 1482 1483 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1484 struct net_device *br) 1485 { 1486 struct dsa_switch *ds; 1487 int port; 1488 int dev; 1489 int err; 1490 1491 /* Remap the Port VLAN of each local bridge group member */ 1492 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1493 if (chip->ds->ports[port].bridge_dev == br) { 1494 err = mv88e6xxx_port_vlan_map(chip, port); 1495 if (err) 1496 return err; 1497 } 1498 } 1499 1500 if (!mv88e6xxx_has_pvt(chip)) 1501 return 0; 1502 1503 /* Remap the Port VLAN of each cross-chip bridge group member */ 1504 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1505 ds = chip->ds->dst->ds[dev]; 1506 if (!ds) 1507 break; 1508 1509 for (port = 0; port < ds->num_ports; ++port) { 1510 if (ds->ports[port].bridge_dev == br) { 1511 err = mv88e6xxx_pvt_map(chip, dev, port); 1512 if (err) 1513 return err; 1514 } 1515 } 1516 } 1517 1518 return 0; 1519 } 1520 1521 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1522 struct net_device *br) 1523 { 1524 struct mv88e6xxx_chip *chip = ds->priv; 1525 int err; 1526 1527 mutex_lock(&chip->reg_lock); 1528 err = mv88e6xxx_bridge_map(chip, br); 1529 mutex_unlock(&chip->reg_lock); 1530 1531 return err; 1532 } 1533 1534 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1535 struct net_device *br) 1536 { 1537 struct mv88e6xxx_chip *chip = ds->priv; 1538 1539 mutex_lock(&chip->reg_lock); 1540 if (mv88e6xxx_bridge_map(chip, br) || 1541 mv88e6xxx_port_vlan_map(chip, port)) 1542 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1543 mutex_unlock(&chip->reg_lock); 1544 } 1545 1546 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1547 int port, struct net_device *br) 1548 { 1549 struct mv88e6xxx_chip *chip = ds->priv; 1550 int err; 1551 1552 if (!mv88e6xxx_has_pvt(chip)) 1553 return 0; 1554 1555 mutex_lock(&chip->reg_lock); 1556 err = mv88e6xxx_pvt_map(chip, dev, port); 1557 mutex_unlock(&chip->reg_lock); 1558 1559 return err; 1560 } 1561 1562 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1563 int port, struct net_device *br) 1564 { 1565 struct mv88e6xxx_chip *chip = ds->priv; 1566 1567 if (!mv88e6xxx_has_pvt(chip)) 1568 return; 1569 1570 mutex_lock(&chip->reg_lock); 1571 if (mv88e6xxx_pvt_map(chip, dev, port)) 1572 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1573 mutex_unlock(&chip->reg_lock); 1574 } 1575 1576 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1577 { 1578 if (chip->info->ops->reset) 1579 return chip->info->ops->reset(chip); 1580 1581 return 0; 1582 } 1583 1584 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1585 { 1586 struct gpio_desc *gpiod = chip->reset; 1587 1588 /* If there is a GPIO connected to the reset pin, toggle it */ 1589 if (gpiod) { 1590 gpiod_set_value_cansleep(gpiod, 1); 1591 usleep_range(10000, 20000); 1592 gpiod_set_value_cansleep(gpiod, 0); 1593 usleep_range(10000, 20000); 1594 } 1595 } 1596 1597 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1598 { 1599 int i, err; 1600 1601 /* Set all ports to the Disabled state */ 1602 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1603 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1604 if (err) 1605 return err; 1606 } 1607 1608 /* Wait for transmit queues to drain, 1609 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1610 */ 1611 usleep_range(2000, 4000); 1612 1613 return 0; 1614 } 1615 1616 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1617 { 1618 int err; 1619 1620 err = mv88e6xxx_disable_ports(chip); 1621 if (err) 1622 return err; 1623 1624 mv88e6xxx_hardware_reset(chip); 1625 1626 return mv88e6xxx_software_reset(chip); 1627 } 1628 1629 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1630 enum mv88e6xxx_frame_mode frame, 1631 enum mv88e6xxx_egress_mode egress, u16 etype) 1632 { 1633 int err; 1634 1635 if (!chip->info->ops->port_set_frame_mode) 1636 return -EOPNOTSUPP; 1637 1638 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1639 if (err) 1640 return err; 1641 1642 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1643 if (err) 1644 return err; 1645 1646 if (chip->info->ops->port_set_ether_type) 1647 return chip->info->ops->port_set_ether_type(chip, port, etype); 1648 1649 return 0; 1650 } 1651 1652 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1653 { 1654 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1655 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1656 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1657 } 1658 1659 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1660 { 1661 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1662 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1663 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1664 } 1665 1666 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1667 { 1668 return mv88e6xxx_set_port_mode(chip, port, 1669 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1670 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1671 ETH_P_EDSA); 1672 } 1673 1674 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1675 { 1676 if (dsa_is_dsa_port(chip->ds, port)) 1677 return mv88e6xxx_set_port_mode_dsa(chip, port); 1678 1679 if (dsa_is_normal_port(chip->ds, port)) 1680 return mv88e6xxx_set_port_mode_normal(chip, port); 1681 1682 /* Setup CPU port mode depending on its supported tag format */ 1683 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1684 return mv88e6xxx_set_port_mode_dsa(chip, port); 1685 1686 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1687 return mv88e6xxx_set_port_mode_edsa(chip, port); 1688 1689 return -EINVAL; 1690 } 1691 1692 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1693 { 1694 bool message = dsa_is_dsa_port(chip->ds, port); 1695 1696 return mv88e6xxx_port_set_message_port(chip, port, message); 1697 } 1698 1699 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1700 { 1701 bool flood = port == dsa_upstream_port(chip->ds); 1702 1703 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1704 if (chip->info->ops->port_set_egress_floods) 1705 return chip->info->ops->port_set_egress_floods(chip, port, 1706 flood, flood); 1707 1708 return 0; 1709 } 1710 1711 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1712 bool on) 1713 { 1714 if (chip->info->ops->serdes_power) 1715 return chip->info->ops->serdes_power(chip, port, on); 1716 1717 return 0; 1718 } 1719 1720 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1721 { 1722 struct dsa_switch *ds = chip->ds; 1723 int err; 1724 u16 reg; 1725 1726 /* MAC Forcing register: don't force link, speed, duplex or flow control 1727 * state to any particular values on physical ports, but force the CPU 1728 * port and all DSA ports to their maximum bandwidth and full duplex. 1729 */ 1730 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1731 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1732 SPEED_MAX, DUPLEX_FULL, 1733 PHY_INTERFACE_MODE_NA); 1734 else 1735 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1736 SPEED_UNFORCED, DUPLEX_UNFORCED, 1737 PHY_INTERFACE_MODE_NA); 1738 if (err) 1739 return err; 1740 1741 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1742 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1743 * tunneling, determine priority by looking at 802.1p and IP 1744 * priority fields (IP prio has precedence), and set STP state 1745 * to Forwarding. 1746 * 1747 * If this is the CPU link, use DSA or EDSA tagging depending 1748 * on which tagging mode was configured. 1749 * 1750 * If this is a link to another switch, use DSA tagging mode. 1751 * 1752 * If this is the upstream port for this switch, enable 1753 * forwarding of unknown unicasts and multicasts. 1754 */ 1755 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1756 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1757 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1758 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1759 if (err) 1760 return err; 1761 1762 err = mv88e6xxx_setup_port_mode(chip, port); 1763 if (err) 1764 return err; 1765 1766 err = mv88e6xxx_setup_egress_floods(chip, port); 1767 if (err) 1768 return err; 1769 1770 /* Enable the SERDES interface for DSA and CPU ports. Normal 1771 * ports SERDES are enabled when the port is enabled, thus 1772 * saving a bit of power. 1773 */ 1774 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1775 err = mv88e6xxx_serdes_power(chip, port, true); 1776 if (err) 1777 return err; 1778 } 1779 1780 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1781 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1782 * untagged frames on this port, do a destination address lookup on all 1783 * received packets as usual, disable ARP mirroring and don't send a 1784 * copy of all transmitted/received frames on this port to the CPU. 1785 */ 1786 err = mv88e6xxx_port_set_map_da(chip, port); 1787 if (err) 1788 return err; 1789 1790 reg = 0; 1791 if (chip->info->ops->port_set_upstream_port) { 1792 err = chip->info->ops->port_set_upstream_port( 1793 chip, port, dsa_upstream_port(ds)); 1794 if (err) 1795 return err; 1796 } 1797 1798 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1799 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1800 if (err) 1801 return err; 1802 1803 if (chip->info->ops->port_set_jumbo_size) { 1804 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1805 if (err) 1806 return err; 1807 } 1808 1809 /* Port Association Vector: when learning source addresses 1810 * of packets, add the address to the address database using 1811 * a port bitmap that has only the bit for this port set and 1812 * the other bits clear. 1813 */ 1814 reg = 1 << port; 1815 /* Disable learning for CPU port */ 1816 if (dsa_is_cpu_port(ds, port)) 1817 reg = 0; 1818 1819 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1820 reg); 1821 if (err) 1822 return err; 1823 1824 /* Egress rate control 2: disable egress rate control. */ 1825 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1826 0x0000); 1827 if (err) 1828 return err; 1829 1830 if (chip->info->ops->port_pause_limit) { 1831 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1832 if (err) 1833 return err; 1834 } 1835 1836 if (chip->info->ops->port_disable_learn_limit) { 1837 err = chip->info->ops->port_disable_learn_limit(chip, port); 1838 if (err) 1839 return err; 1840 } 1841 1842 if (chip->info->ops->port_disable_pri_override) { 1843 err = chip->info->ops->port_disable_pri_override(chip, port); 1844 if (err) 1845 return err; 1846 } 1847 1848 if (chip->info->ops->port_tag_remap) { 1849 err = chip->info->ops->port_tag_remap(chip, port); 1850 if (err) 1851 return err; 1852 } 1853 1854 if (chip->info->ops->port_egress_rate_limiting) { 1855 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1856 if (err) 1857 return err; 1858 } 1859 1860 err = mv88e6xxx_setup_message_port(chip, port); 1861 if (err) 1862 return err; 1863 1864 /* Port based VLAN map: give each port the same default address 1865 * database, and allow bidirectional communication between the 1866 * CPU and DSA port(s), and the other ports. 1867 */ 1868 err = mv88e6xxx_port_set_fid(chip, port, 0); 1869 if (err) 1870 return err; 1871 1872 err = mv88e6xxx_port_vlan_map(chip, port); 1873 if (err) 1874 return err; 1875 1876 /* Default VLAN ID and priority: don't set a default VLAN 1877 * ID, and set the default packet priority to zero. 1878 */ 1879 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1880 } 1881 1882 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1883 struct phy_device *phydev) 1884 { 1885 struct mv88e6xxx_chip *chip = ds->priv; 1886 int err; 1887 1888 mutex_lock(&chip->reg_lock); 1889 err = mv88e6xxx_serdes_power(chip, port, true); 1890 mutex_unlock(&chip->reg_lock); 1891 1892 return err; 1893 } 1894 1895 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1896 struct phy_device *phydev) 1897 { 1898 struct mv88e6xxx_chip *chip = ds->priv; 1899 1900 mutex_lock(&chip->reg_lock); 1901 if (mv88e6xxx_serdes_power(chip, port, false)) 1902 dev_err(chip->dev, "failed to power off SERDES\n"); 1903 mutex_unlock(&chip->reg_lock); 1904 } 1905 1906 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1907 unsigned int ageing_time) 1908 { 1909 struct mv88e6xxx_chip *chip = ds->priv; 1910 int err; 1911 1912 mutex_lock(&chip->reg_lock); 1913 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1914 mutex_unlock(&chip->reg_lock); 1915 1916 return err; 1917 } 1918 1919 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1920 { 1921 struct dsa_switch *ds = chip->ds; 1922 u32 upstream_port = dsa_upstream_port(ds); 1923 int err; 1924 1925 if (chip->info->ops->set_cpu_port) { 1926 err = chip->info->ops->set_cpu_port(chip, upstream_port); 1927 if (err) 1928 return err; 1929 } 1930 1931 if (chip->info->ops->set_egress_port) { 1932 err = chip->info->ops->set_egress_port(chip, upstream_port); 1933 if (err) 1934 return err; 1935 } 1936 1937 /* Disable remote management, and set the switch's DSA device number. */ 1938 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1939 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1940 (ds->index & 0x1f)); 1941 if (err) 1942 return err; 1943 1944 /* Configure the IP ToS mapping registers. */ 1945 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1946 if (err) 1947 return err; 1948 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1949 if (err) 1950 return err; 1951 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1952 if (err) 1953 return err; 1954 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1955 if (err) 1956 return err; 1957 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 1958 if (err) 1959 return err; 1960 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 1961 if (err) 1962 return err; 1963 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 1964 if (err) 1965 return err; 1966 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 1967 if (err) 1968 return err; 1969 1970 /* Configure the IEEE 802.1p priority mapping register. */ 1971 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 1972 if (err) 1973 return err; 1974 1975 /* Initialize the statistics unit */ 1976 err = mv88e6xxx_stats_set_histogram(chip); 1977 if (err) 1978 return err; 1979 1980 /* Clear the statistics counters for all ports */ 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 1982 MV88E6XXX_G1_STATS_OP_BUSY | 1983 MV88E6XXX_G1_STATS_OP_FLUSH_ALL); 1984 if (err) 1985 return err; 1986 1987 /* Wait for the flush to complete. */ 1988 err = mv88e6xxx_g1_stats_wait(chip); 1989 if (err) 1990 return err; 1991 1992 return 0; 1993 } 1994 1995 static int mv88e6xxx_setup(struct dsa_switch *ds) 1996 { 1997 struct mv88e6xxx_chip *chip = ds->priv; 1998 int err; 1999 int i; 2000 2001 chip->ds = ds; 2002 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2003 2004 mutex_lock(&chip->reg_lock); 2005 2006 /* Setup Switch Port Registers */ 2007 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2008 err = mv88e6xxx_setup_port(chip, i); 2009 if (err) 2010 goto unlock; 2011 } 2012 2013 /* Setup Switch Global 1 Registers */ 2014 err = mv88e6xxx_g1_setup(chip); 2015 if (err) 2016 goto unlock; 2017 2018 /* Setup Switch Global 2 Registers */ 2019 if (chip->info->global2_addr) { 2020 err = mv88e6xxx_g2_setup(chip); 2021 if (err) 2022 goto unlock; 2023 } 2024 2025 err = mv88e6xxx_irl_setup(chip); 2026 if (err) 2027 goto unlock; 2028 2029 err = mv88e6xxx_mac_setup(chip); 2030 if (err) 2031 goto unlock; 2032 2033 err = mv88e6xxx_phy_setup(chip); 2034 if (err) 2035 goto unlock; 2036 2037 err = mv88e6xxx_vtu_setup(chip); 2038 if (err) 2039 goto unlock; 2040 2041 err = mv88e6xxx_pvt_setup(chip); 2042 if (err) 2043 goto unlock; 2044 2045 err = mv88e6xxx_atu_setup(chip); 2046 if (err) 2047 goto unlock; 2048 2049 err = mv88e6xxx_pot_setup(chip); 2050 if (err) 2051 goto unlock; 2052 2053 err = mv88e6xxx_rsvd2cpu_setup(chip); 2054 if (err) 2055 goto unlock; 2056 2057 unlock: 2058 mutex_unlock(&chip->reg_lock); 2059 2060 return err; 2061 } 2062 2063 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2064 { 2065 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2066 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2067 u16 val; 2068 int err; 2069 2070 if (!chip->info->ops->phy_read) 2071 return -EOPNOTSUPP; 2072 2073 mutex_lock(&chip->reg_lock); 2074 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2075 mutex_unlock(&chip->reg_lock); 2076 2077 if (reg == MII_PHYSID2) { 2078 /* Some internal PHYS don't have a model number. Use 2079 * the mv88e6390 family model number instead. 2080 */ 2081 if (!(val & 0x3f0)) 2082 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2083 } 2084 2085 return err ? err : val; 2086 } 2087 2088 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2089 { 2090 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2091 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2092 int err; 2093 2094 if (!chip->info->ops->phy_write) 2095 return -EOPNOTSUPP; 2096 2097 mutex_lock(&chip->reg_lock); 2098 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2099 mutex_unlock(&chip->reg_lock); 2100 2101 return err; 2102 } 2103 2104 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2105 struct device_node *np, 2106 bool external) 2107 { 2108 static int index; 2109 struct mv88e6xxx_mdio_bus *mdio_bus; 2110 struct mii_bus *bus; 2111 int err; 2112 2113 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2114 if (!bus) 2115 return -ENOMEM; 2116 2117 mdio_bus = bus->priv; 2118 mdio_bus->bus = bus; 2119 mdio_bus->chip = chip; 2120 INIT_LIST_HEAD(&mdio_bus->list); 2121 mdio_bus->external = external; 2122 2123 if (np) { 2124 bus->name = np->full_name; 2125 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2126 } else { 2127 bus->name = "mv88e6xxx SMI"; 2128 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2129 } 2130 2131 bus->read = mv88e6xxx_mdio_read; 2132 bus->write = mv88e6xxx_mdio_write; 2133 bus->parent = chip->dev; 2134 2135 if (np) 2136 err = of_mdiobus_register(bus, np); 2137 else 2138 err = mdiobus_register(bus); 2139 if (err) { 2140 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2141 return err; 2142 } 2143 2144 if (external) 2145 list_add_tail(&mdio_bus->list, &chip->mdios); 2146 else 2147 list_add(&mdio_bus->list, &chip->mdios); 2148 2149 return 0; 2150 } 2151 2152 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2153 { .compatible = "marvell,mv88e6xxx-mdio-external", 2154 .data = (void *)true }, 2155 { }, 2156 }; 2157 2158 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2159 struct device_node *np) 2160 { 2161 const struct of_device_id *match; 2162 struct device_node *child; 2163 int err; 2164 2165 /* Always register one mdio bus for the internal/default mdio 2166 * bus. This maybe represented in the device tree, but is 2167 * optional. 2168 */ 2169 child = of_get_child_by_name(np, "mdio"); 2170 err = mv88e6xxx_mdio_register(chip, child, false); 2171 if (err) 2172 return err; 2173 2174 /* Walk the device tree, and see if there are any other nodes 2175 * which say they are compatible with the external mdio 2176 * bus. 2177 */ 2178 for_each_available_child_of_node(np, child) { 2179 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2180 if (match) { 2181 err = mv88e6xxx_mdio_register(chip, child, true); 2182 if (err) 2183 return err; 2184 } 2185 } 2186 2187 return 0; 2188 } 2189 2190 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2191 2192 { 2193 struct mv88e6xxx_mdio_bus *mdio_bus; 2194 struct mii_bus *bus; 2195 2196 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2197 bus = mdio_bus->bus; 2198 2199 mdiobus_unregister(bus); 2200 } 2201 } 2202 2203 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2204 { 2205 struct mv88e6xxx_chip *chip = ds->priv; 2206 2207 return chip->eeprom_len; 2208 } 2209 2210 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2211 struct ethtool_eeprom *eeprom, u8 *data) 2212 { 2213 struct mv88e6xxx_chip *chip = ds->priv; 2214 int err; 2215 2216 if (!chip->info->ops->get_eeprom) 2217 return -EOPNOTSUPP; 2218 2219 mutex_lock(&chip->reg_lock); 2220 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2221 mutex_unlock(&chip->reg_lock); 2222 2223 if (err) 2224 return err; 2225 2226 eeprom->magic = 0xc3ec4951; 2227 2228 return 0; 2229 } 2230 2231 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2232 struct ethtool_eeprom *eeprom, u8 *data) 2233 { 2234 struct mv88e6xxx_chip *chip = ds->priv; 2235 int err; 2236 2237 if (!chip->info->ops->set_eeprom) 2238 return -EOPNOTSUPP; 2239 2240 if (eeprom->magic != 0xc3ec4951) 2241 return -EINVAL; 2242 2243 mutex_lock(&chip->reg_lock); 2244 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2245 mutex_unlock(&chip->reg_lock); 2246 2247 return err; 2248 } 2249 2250 static const struct mv88e6xxx_ops mv88e6085_ops = { 2251 /* MV88E6XXX_FAMILY_6097 */ 2252 .irl_init_all = mv88e6352_g2_irl_init_all, 2253 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2254 .phy_read = mv88e6185_phy_ppu_read, 2255 .phy_write = mv88e6185_phy_ppu_write, 2256 .port_set_link = mv88e6xxx_port_set_link, 2257 .port_set_duplex = mv88e6xxx_port_set_duplex, 2258 .port_set_speed = mv88e6185_port_set_speed, 2259 .port_tag_remap = mv88e6095_port_tag_remap, 2260 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2261 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2262 .port_set_ether_type = mv88e6351_port_set_ether_type, 2263 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2264 .port_pause_limit = mv88e6097_port_pause_limit, 2265 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2266 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2267 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2268 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2269 .stats_get_strings = mv88e6095_stats_get_strings, 2270 .stats_get_stats = mv88e6095_stats_get_stats, 2271 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2272 .set_egress_port = mv88e6095_g1_set_egress_port, 2273 .watchdog_ops = &mv88e6097_watchdog_ops, 2274 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2275 .pot_clear = mv88e6xxx_g2_pot_clear, 2276 .ppu_enable = mv88e6185_g1_ppu_enable, 2277 .ppu_disable = mv88e6185_g1_ppu_disable, 2278 .reset = mv88e6185_g1_reset, 2279 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2280 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2281 }; 2282 2283 static const struct mv88e6xxx_ops mv88e6095_ops = { 2284 /* MV88E6XXX_FAMILY_6095 */ 2285 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2286 .phy_read = mv88e6185_phy_ppu_read, 2287 .phy_write = mv88e6185_phy_ppu_write, 2288 .port_set_link = mv88e6xxx_port_set_link, 2289 .port_set_duplex = mv88e6xxx_port_set_duplex, 2290 .port_set_speed = mv88e6185_port_set_speed, 2291 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2292 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2293 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2294 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2295 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2296 .stats_get_strings = mv88e6095_stats_get_strings, 2297 .stats_get_stats = mv88e6095_stats_get_stats, 2298 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2299 .ppu_enable = mv88e6185_g1_ppu_enable, 2300 .ppu_disable = mv88e6185_g1_ppu_disable, 2301 .reset = mv88e6185_g1_reset, 2302 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2303 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2304 }; 2305 2306 static const struct mv88e6xxx_ops mv88e6097_ops = { 2307 /* MV88E6XXX_FAMILY_6097 */ 2308 .irl_init_all = mv88e6352_g2_irl_init_all, 2309 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2310 .phy_read = mv88e6xxx_g2_smi_phy_read, 2311 .phy_write = mv88e6xxx_g2_smi_phy_write, 2312 .port_set_link = mv88e6xxx_port_set_link, 2313 .port_set_duplex = mv88e6xxx_port_set_duplex, 2314 .port_set_speed = mv88e6185_port_set_speed, 2315 .port_tag_remap = mv88e6095_port_tag_remap, 2316 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2317 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2318 .port_set_ether_type = mv88e6351_port_set_ether_type, 2319 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2320 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2321 .port_pause_limit = mv88e6097_port_pause_limit, 2322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2324 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2325 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2326 .stats_get_strings = mv88e6095_stats_get_strings, 2327 .stats_get_stats = mv88e6095_stats_get_stats, 2328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2329 .set_egress_port = mv88e6095_g1_set_egress_port, 2330 .watchdog_ops = &mv88e6097_watchdog_ops, 2331 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2332 .pot_clear = mv88e6xxx_g2_pot_clear, 2333 .reset = mv88e6352_g1_reset, 2334 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2335 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2336 }; 2337 2338 static const struct mv88e6xxx_ops mv88e6123_ops = { 2339 /* MV88E6XXX_FAMILY_6165 */ 2340 .irl_init_all = mv88e6352_g2_irl_init_all, 2341 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2342 .phy_read = mv88e6xxx_g2_smi_phy_read, 2343 .phy_write = mv88e6xxx_g2_smi_phy_write, 2344 .port_set_link = mv88e6xxx_port_set_link, 2345 .port_set_duplex = mv88e6xxx_port_set_duplex, 2346 .port_set_speed = mv88e6185_port_set_speed, 2347 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2348 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2351 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2352 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2353 .stats_get_strings = mv88e6095_stats_get_strings, 2354 .stats_get_stats = mv88e6095_stats_get_stats, 2355 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2356 .set_egress_port = mv88e6095_g1_set_egress_port, 2357 .watchdog_ops = &mv88e6097_watchdog_ops, 2358 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2359 .pot_clear = mv88e6xxx_g2_pot_clear, 2360 .reset = mv88e6352_g1_reset, 2361 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2362 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2363 }; 2364 2365 static const struct mv88e6xxx_ops mv88e6131_ops = { 2366 /* MV88E6XXX_FAMILY_6185 */ 2367 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2368 .phy_read = mv88e6185_phy_ppu_read, 2369 .phy_write = mv88e6185_phy_ppu_write, 2370 .port_set_link = mv88e6xxx_port_set_link, 2371 .port_set_duplex = mv88e6xxx_port_set_duplex, 2372 .port_set_speed = mv88e6185_port_set_speed, 2373 .port_tag_remap = mv88e6095_port_tag_remap, 2374 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2375 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2376 .port_set_ether_type = mv88e6351_port_set_ether_type, 2377 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2378 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2379 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2380 .port_pause_limit = mv88e6097_port_pause_limit, 2381 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2382 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2383 .stats_get_strings = mv88e6095_stats_get_strings, 2384 .stats_get_stats = mv88e6095_stats_get_stats, 2385 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2386 .set_egress_port = mv88e6095_g1_set_egress_port, 2387 .watchdog_ops = &mv88e6097_watchdog_ops, 2388 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2389 .ppu_enable = mv88e6185_g1_ppu_enable, 2390 .ppu_disable = mv88e6185_g1_ppu_disable, 2391 .reset = mv88e6185_g1_reset, 2392 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2393 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2394 }; 2395 2396 static const struct mv88e6xxx_ops mv88e6141_ops = { 2397 /* MV88E6XXX_FAMILY_6341 */ 2398 .irl_init_all = mv88e6352_g2_irl_init_all, 2399 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2400 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2401 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2402 .phy_read = mv88e6xxx_g2_smi_phy_read, 2403 .phy_write = mv88e6xxx_g2_smi_phy_write, 2404 .port_set_link = mv88e6xxx_port_set_link, 2405 .port_set_duplex = mv88e6xxx_port_set_duplex, 2406 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2407 .port_set_speed = mv88e6390_port_set_speed, 2408 .port_tag_remap = mv88e6095_port_tag_remap, 2409 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2410 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2411 .port_set_ether_type = mv88e6351_port_set_ether_type, 2412 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2413 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2414 .port_pause_limit = mv88e6097_port_pause_limit, 2415 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2416 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2417 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2418 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2419 .stats_get_strings = mv88e6320_stats_get_strings, 2420 .stats_get_stats = mv88e6390_stats_get_stats, 2421 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2422 .set_egress_port = mv88e6390_g1_set_egress_port, 2423 .watchdog_ops = &mv88e6390_watchdog_ops, 2424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2425 .pot_clear = mv88e6xxx_g2_pot_clear, 2426 .reset = mv88e6352_g1_reset, 2427 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2428 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2429 }; 2430 2431 static const struct mv88e6xxx_ops mv88e6161_ops = { 2432 /* MV88E6XXX_FAMILY_6165 */ 2433 .irl_init_all = mv88e6352_g2_irl_init_all, 2434 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2435 .phy_read = mv88e6xxx_g2_smi_phy_read, 2436 .phy_write = mv88e6xxx_g2_smi_phy_write, 2437 .port_set_link = mv88e6xxx_port_set_link, 2438 .port_set_duplex = mv88e6xxx_port_set_duplex, 2439 .port_set_speed = mv88e6185_port_set_speed, 2440 .port_tag_remap = mv88e6095_port_tag_remap, 2441 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2442 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2443 .port_set_ether_type = mv88e6351_port_set_ether_type, 2444 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2445 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2446 .port_pause_limit = mv88e6097_port_pause_limit, 2447 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2448 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2449 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2450 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2451 .stats_get_strings = mv88e6095_stats_get_strings, 2452 .stats_get_stats = mv88e6095_stats_get_stats, 2453 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2454 .set_egress_port = mv88e6095_g1_set_egress_port, 2455 .watchdog_ops = &mv88e6097_watchdog_ops, 2456 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2457 .pot_clear = mv88e6xxx_g2_pot_clear, 2458 .reset = mv88e6352_g1_reset, 2459 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2460 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2461 }; 2462 2463 static const struct mv88e6xxx_ops mv88e6165_ops = { 2464 /* MV88E6XXX_FAMILY_6165 */ 2465 .irl_init_all = mv88e6352_g2_irl_init_all, 2466 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2467 .phy_read = mv88e6165_phy_read, 2468 .phy_write = mv88e6165_phy_write, 2469 .port_set_link = mv88e6xxx_port_set_link, 2470 .port_set_duplex = mv88e6xxx_port_set_duplex, 2471 .port_set_speed = mv88e6185_port_set_speed, 2472 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2473 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2474 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2475 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2476 .stats_get_strings = mv88e6095_stats_get_strings, 2477 .stats_get_stats = mv88e6095_stats_get_stats, 2478 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2479 .set_egress_port = mv88e6095_g1_set_egress_port, 2480 .watchdog_ops = &mv88e6097_watchdog_ops, 2481 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2482 .pot_clear = mv88e6xxx_g2_pot_clear, 2483 .reset = mv88e6352_g1_reset, 2484 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2485 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2486 }; 2487 2488 static const struct mv88e6xxx_ops mv88e6171_ops = { 2489 /* MV88E6XXX_FAMILY_6351 */ 2490 .irl_init_all = mv88e6352_g2_irl_init_all, 2491 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2492 .phy_read = mv88e6xxx_g2_smi_phy_read, 2493 .phy_write = mv88e6xxx_g2_smi_phy_write, 2494 .port_set_link = mv88e6xxx_port_set_link, 2495 .port_set_duplex = mv88e6xxx_port_set_duplex, 2496 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2497 .port_set_speed = mv88e6185_port_set_speed, 2498 .port_tag_remap = mv88e6095_port_tag_remap, 2499 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2500 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2501 .port_set_ether_type = mv88e6351_port_set_ether_type, 2502 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2503 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2504 .port_pause_limit = mv88e6097_port_pause_limit, 2505 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2506 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2507 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2508 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2509 .stats_get_strings = mv88e6095_stats_get_strings, 2510 .stats_get_stats = mv88e6095_stats_get_stats, 2511 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2512 .set_egress_port = mv88e6095_g1_set_egress_port, 2513 .watchdog_ops = &mv88e6097_watchdog_ops, 2514 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2515 .pot_clear = mv88e6xxx_g2_pot_clear, 2516 .reset = mv88e6352_g1_reset, 2517 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2518 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2519 }; 2520 2521 static const struct mv88e6xxx_ops mv88e6172_ops = { 2522 /* MV88E6XXX_FAMILY_6352 */ 2523 .irl_init_all = mv88e6352_g2_irl_init_all, 2524 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2525 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2526 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2527 .phy_read = mv88e6xxx_g2_smi_phy_read, 2528 .phy_write = mv88e6xxx_g2_smi_phy_write, 2529 .port_set_link = mv88e6xxx_port_set_link, 2530 .port_set_duplex = mv88e6xxx_port_set_duplex, 2531 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2532 .port_set_speed = mv88e6352_port_set_speed, 2533 .port_tag_remap = mv88e6095_port_tag_remap, 2534 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2535 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2536 .port_set_ether_type = mv88e6351_port_set_ether_type, 2537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2539 .port_pause_limit = mv88e6097_port_pause_limit, 2540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2542 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2543 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2544 .stats_get_strings = mv88e6095_stats_get_strings, 2545 .stats_get_stats = mv88e6095_stats_get_stats, 2546 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2547 .set_egress_port = mv88e6095_g1_set_egress_port, 2548 .watchdog_ops = &mv88e6097_watchdog_ops, 2549 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2550 .pot_clear = mv88e6xxx_g2_pot_clear, 2551 .reset = mv88e6352_g1_reset, 2552 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2553 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2554 .serdes_power = mv88e6352_serdes_power, 2555 }; 2556 2557 static const struct mv88e6xxx_ops mv88e6175_ops = { 2558 /* MV88E6XXX_FAMILY_6351 */ 2559 .irl_init_all = mv88e6352_g2_irl_init_all, 2560 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2561 .phy_read = mv88e6xxx_g2_smi_phy_read, 2562 .phy_write = mv88e6xxx_g2_smi_phy_write, 2563 .port_set_link = mv88e6xxx_port_set_link, 2564 .port_set_duplex = mv88e6xxx_port_set_duplex, 2565 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2566 .port_set_speed = mv88e6185_port_set_speed, 2567 .port_tag_remap = mv88e6095_port_tag_remap, 2568 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2569 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2570 .port_set_ether_type = mv88e6351_port_set_ether_type, 2571 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2573 .port_pause_limit = mv88e6097_port_pause_limit, 2574 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2575 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2576 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2577 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2578 .stats_get_strings = mv88e6095_stats_get_strings, 2579 .stats_get_stats = mv88e6095_stats_get_stats, 2580 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2581 .set_egress_port = mv88e6095_g1_set_egress_port, 2582 .watchdog_ops = &mv88e6097_watchdog_ops, 2583 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2584 .pot_clear = mv88e6xxx_g2_pot_clear, 2585 .reset = mv88e6352_g1_reset, 2586 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2587 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2588 }; 2589 2590 static const struct mv88e6xxx_ops mv88e6176_ops = { 2591 /* MV88E6XXX_FAMILY_6352 */ 2592 .irl_init_all = mv88e6352_g2_irl_init_all, 2593 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2594 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2595 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2596 .phy_read = mv88e6xxx_g2_smi_phy_read, 2597 .phy_write = mv88e6xxx_g2_smi_phy_write, 2598 .port_set_link = mv88e6xxx_port_set_link, 2599 .port_set_duplex = mv88e6xxx_port_set_duplex, 2600 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2601 .port_set_speed = mv88e6352_port_set_speed, 2602 .port_tag_remap = mv88e6095_port_tag_remap, 2603 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2604 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2605 .port_set_ether_type = mv88e6351_port_set_ether_type, 2606 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2607 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2608 .port_pause_limit = mv88e6097_port_pause_limit, 2609 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2610 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2611 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2612 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2613 .stats_get_strings = mv88e6095_stats_get_strings, 2614 .stats_get_stats = mv88e6095_stats_get_stats, 2615 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2616 .set_egress_port = mv88e6095_g1_set_egress_port, 2617 .watchdog_ops = &mv88e6097_watchdog_ops, 2618 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2619 .pot_clear = mv88e6xxx_g2_pot_clear, 2620 .reset = mv88e6352_g1_reset, 2621 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2622 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2623 .serdes_power = mv88e6352_serdes_power, 2624 }; 2625 2626 static const struct mv88e6xxx_ops mv88e6185_ops = { 2627 /* MV88E6XXX_FAMILY_6185 */ 2628 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2629 .phy_read = mv88e6185_phy_ppu_read, 2630 .phy_write = mv88e6185_phy_ppu_write, 2631 .port_set_link = mv88e6xxx_port_set_link, 2632 .port_set_duplex = mv88e6xxx_port_set_duplex, 2633 .port_set_speed = mv88e6185_port_set_speed, 2634 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2635 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2636 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2637 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2638 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2639 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2640 .stats_get_strings = mv88e6095_stats_get_strings, 2641 .stats_get_stats = mv88e6095_stats_get_stats, 2642 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2643 .set_egress_port = mv88e6095_g1_set_egress_port, 2644 .watchdog_ops = &mv88e6097_watchdog_ops, 2645 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2646 .ppu_enable = mv88e6185_g1_ppu_enable, 2647 .ppu_disable = mv88e6185_g1_ppu_disable, 2648 .reset = mv88e6185_g1_reset, 2649 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2650 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2651 }; 2652 2653 static const struct mv88e6xxx_ops mv88e6190_ops = { 2654 /* MV88E6XXX_FAMILY_6390 */ 2655 .irl_init_all = mv88e6390_g2_irl_init_all, 2656 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2657 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2658 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2659 .phy_read = mv88e6xxx_g2_smi_phy_read, 2660 .phy_write = mv88e6xxx_g2_smi_phy_write, 2661 .port_set_link = mv88e6xxx_port_set_link, 2662 .port_set_duplex = mv88e6xxx_port_set_duplex, 2663 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2664 .port_set_speed = mv88e6390_port_set_speed, 2665 .port_tag_remap = mv88e6390_port_tag_remap, 2666 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2667 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2668 .port_set_ether_type = mv88e6351_port_set_ether_type, 2669 .port_pause_limit = mv88e6390_port_pause_limit, 2670 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2671 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2672 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2673 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2674 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2675 .stats_get_strings = mv88e6320_stats_get_strings, 2676 .stats_get_stats = mv88e6390_stats_get_stats, 2677 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2678 .set_egress_port = mv88e6390_g1_set_egress_port, 2679 .watchdog_ops = &mv88e6390_watchdog_ops, 2680 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2681 .pot_clear = mv88e6xxx_g2_pot_clear, 2682 .reset = mv88e6352_g1_reset, 2683 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2684 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2685 .serdes_power = mv88e6390_serdes_power, 2686 }; 2687 2688 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2689 /* MV88E6XXX_FAMILY_6390 */ 2690 .irl_init_all = mv88e6390_g2_irl_init_all, 2691 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2692 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2694 .phy_read = mv88e6xxx_g2_smi_phy_read, 2695 .phy_write = mv88e6xxx_g2_smi_phy_write, 2696 .port_set_link = mv88e6xxx_port_set_link, 2697 .port_set_duplex = mv88e6xxx_port_set_duplex, 2698 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2699 .port_set_speed = mv88e6390x_port_set_speed, 2700 .port_tag_remap = mv88e6390_port_tag_remap, 2701 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2702 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2703 .port_set_ether_type = mv88e6351_port_set_ether_type, 2704 .port_pause_limit = mv88e6390_port_pause_limit, 2705 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2706 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2707 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2708 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2709 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2710 .stats_get_strings = mv88e6320_stats_get_strings, 2711 .stats_get_stats = mv88e6390_stats_get_stats, 2712 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2713 .set_egress_port = mv88e6390_g1_set_egress_port, 2714 .watchdog_ops = &mv88e6390_watchdog_ops, 2715 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2716 .pot_clear = mv88e6xxx_g2_pot_clear, 2717 .reset = mv88e6352_g1_reset, 2718 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2719 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2720 .serdes_power = mv88e6390_serdes_power, 2721 }; 2722 2723 static const struct mv88e6xxx_ops mv88e6191_ops = { 2724 /* MV88E6XXX_FAMILY_6390 */ 2725 .irl_init_all = mv88e6390_g2_irl_init_all, 2726 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2727 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2728 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2729 .phy_read = mv88e6xxx_g2_smi_phy_read, 2730 .phy_write = mv88e6xxx_g2_smi_phy_write, 2731 .port_set_link = mv88e6xxx_port_set_link, 2732 .port_set_duplex = mv88e6xxx_port_set_duplex, 2733 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2734 .port_set_speed = mv88e6390_port_set_speed, 2735 .port_tag_remap = mv88e6390_port_tag_remap, 2736 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2737 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2738 .port_set_ether_type = mv88e6351_port_set_ether_type, 2739 .port_pause_limit = mv88e6390_port_pause_limit, 2740 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2741 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2742 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2743 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2744 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2745 .stats_get_strings = mv88e6320_stats_get_strings, 2746 .stats_get_stats = mv88e6390_stats_get_stats, 2747 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2748 .set_egress_port = mv88e6390_g1_set_egress_port, 2749 .watchdog_ops = &mv88e6390_watchdog_ops, 2750 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2751 .pot_clear = mv88e6xxx_g2_pot_clear, 2752 .reset = mv88e6352_g1_reset, 2753 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2754 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2755 .serdes_power = mv88e6390_serdes_power, 2756 }; 2757 2758 static const struct mv88e6xxx_ops mv88e6240_ops = { 2759 /* MV88E6XXX_FAMILY_6352 */ 2760 .irl_init_all = mv88e6352_g2_irl_init_all, 2761 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2762 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2763 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2764 .phy_read = mv88e6xxx_g2_smi_phy_read, 2765 .phy_write = mv88e6xxx_g2_smi_phy_write, 2766 .port_set_link = mv88e6xxx_port_set_link, 2767 .port_set_duplex = mv88e6xxx_port_set_duplex, 2768 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2769 .port_set_speed = mv88e6352_port_set_speed, 2770 .port_tag_remap = mv88e6095_port_tag_remap, 2771 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2772 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2773 .port_set_ether_type = mv88e6351_port_set_ether_type, 2774 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2775 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2776 .port_pause_limit = mv88e6097_port_pause_limit, 2777 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2778 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2779 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2780 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2781 .stats_get_strings = mv88e6095_stats_get_strings, 2782 .stats_get_stats = mv88e6095_stats_get_stats, 2783 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2784 .set_egress_port = mv88e6095_g1_set_egress_port, 2785 .watchdog_ops = &mv88e6097_watchdog_ops, 2786 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2787 .pot_clear = mv88e6xxx_g2_pot_clear, 2788 .reset = mv88e6352_g1_reset, 2789 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2790 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2791 .serdes_power = mv88e6352_serdes_power, 2792 }; 2793 2794 static const struct mv88e6xxx_ops mv88e6290_ops = { 2795 /* MV88E6XXX_FAMILY_6390 */ 2796 .irl_init_all = mv88e6390_g2_irl_init_all, 2797 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2798 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2799 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2800 .phy_read = mv88e6xxx_g2_smi_phy_read, 2801 .phy_write = mv88e6xxx_g2_smi_phy_write, 2802 .port_set_link = mv88e6xxx_port_set_link, 2803 .port_set_duplex = mv88e6xxx_port_set_duplex, 2804 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2805 .port_set_speed = mv88e6390_port_set_speed, 2806 .port_tag_remap = mv88e6390_port_tag_remap, 2807 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2808 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2809 .port_set_ether_type = mv88e6351_port_set_ether_type, 2810 .port_pause_limit = mv88e6390_port_pause_limit, 2811 .port_set_cmode = mv88e6390x_port_set_cmode, 2812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2814 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2815 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2816 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2817 .stats_get_strings = mv88e6320_stats_get_strings, 2818 .stats_get_stats = mv88e6390_stats_get_stats, 2819 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2820 .set_egress_port = mv88e6390_g1_set_egress_port, 2821 .watchdog_ops = &mv88e6390_watchdog_ops, 2822 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2823 .pot_clear = mv88e6xxx_g2_pot_clear, 2824 .reset = mv88e6352_g1_reset, 2825 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2827 .serdes_power = mv88e6390_serdes_power, 2828 }; 2829 2830 static const struct mv88e6xxx_ops mv88e6320_ops = { 2831 /* MV88E6XXX_FAMILY_6320 */ 2832 .irl_init_all = mv88e6352_g2_irl_init_all, 2833 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2834 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2835 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2836 .phy_read = mv88e6xxx_g2_smi_phy_read, 2837 .phy_write = mv88e6xxx_g2_smi_phy_write, 2838 .port_set_link = mv88e6xxx_port_set_link, 2839 .port_set_duplex = mv88e6xxx_port_set_duplex, 2840 .port_set_speed = mv88e6185_port_set_speed, 2841 .port_tag_remap = mv88e6095_port_tag_remap, 2842 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2843 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2844 .port_set_ether_type = mv88e6351_port_set_ether_type, 2845 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2846 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2847 .port_pause_limit = mv88e6097_port_pause_limit, 2848 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2849 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2850 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2851 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2852 .stats_get_strings = mv88e6320_stats_get_strings, 2853 .stats_get_stats = mv88e6320_stats_get_stats, 2854 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2855 .set_egress_port = mv88e6095_g1_set_egress_port, 2856 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2857 .pot_clear = mv88e6xxx_g2_pot_clear, 2858 .reset = mv88e6352_g1_reset, 2859 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2860 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2861 }; 2862 2863 static const struct mv88e6xxx_ops mv88e6321_ops = { 2864 /* MV88E6XXX_FAMILY_6320 */ 2865 .irl_init_all = mv88e6352_g2_irl_init_all, 2866 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2867 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2868 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2869 .phy_read = mv88e6xxx_g2_smi_phy_read, 2870 .phy_write = mv88e6xxx_g2_smi_phy_write, 2871 .port_set_link = mv88e6xxx_port_set_link, 2872 .port_set_duplex = mv88e6xxx_port_set_duplex, 2873 .port_set_speed = mv88e6185_port_set_speed, 2874 .port_tag_remap = mv88e6095_port_tag_remap, 2875 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2876 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2877 .port_set_ether_type = mv88e6351_port_set_ether_type, 2878 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2879 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2880 .port_pause_limit = mv88e6097_port_pause_limit, 2881 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2882 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2883 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2884 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2885 .stats_get_strings = mv88e6320_stats_get_strings, 2886 .stats_get_stats = mv88e6320_stats_get_stats, 2887 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2888 .set_egress_port = mv88e6095_g1_set_egress_port, 2889 .reset = mv88e6352_g1_reset, 2890 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2891 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2892 }; 2893 2894 static const struct mv88e6xxx_ops mv88e6341_ops = { 2895 /* MV88E6XXX_FAMILY_6341 */ 2896 .irl_init_all = mv88e6352_g2_irl_init_all, 2897 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2898 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2899 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2900 .phy_read = mv88e6xxx_g2_smi_phy_read, 2901 .phy_write = mv88e6xxx_g2_smi_phy_write, 2902 .port_set_link = mv88e6xxx_port_set_link, 2903 .port_set_duplex = mv88e6xxx_port_set_duplex, 2904 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2905 .port_set_speed = mv88e6390_port_set_speed, 2906 .port_tag_remap = mv88e6095_port_tag_remap, 2907 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2908 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2909 .port_set_ether_type = mv88e6351_port_set_ether_type, 2910 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2911 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2912 .port_pause_limit = mv88e6097_port_pause_limit, 2913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2915 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2916 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2917 .stats_get_strings = mv88e6320_stats_get_strings, 2918 .stats_get_stats = mv88e6390_stats_get_stats, 2919 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2920 .set_egress_port = mv88e6390_g1_set_egress_port, 2921 .watchdog_ops = &mv88e6390_watchdog_ops, 2922 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2923 .pot_clear = mv88e6xxx_g2_pot_clear, 2924 .reset = mv88e6352_g1_reset, 2925 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2926 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2927 }; 2928 2929 static const struct mv88e6xxx_ops mv88e6350_ops = { 2930 /* MV88E6XXX_FAMILY_6351 */ 2931 .irl_init_all = mv88e6352_g2_irl_init_all, 2932 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2933 .phy_read = mv88e6xxx_g2_smi_phy_read, 2934 .phy_write = mv88e6xxx_g2_smi_phy_write, 2935 .port_set_link = mv88e6xxx_port_set_link, 2936 .port_set_duplex = mv88e6xxx_port_set_duplex, 2937 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2938 .port_set_speed = mv88e6185_port_set_speed, 2939 .port_tag_remap = mv88e6095_port_tag_remap, 2940 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2941 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2942 .port_set_ether_type = mv88e6351_port_set_ether_type, 2943 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2944 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2945 .port_pause_limit = mv88e6097_port_pause_limit, 2946 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2947 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2948 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2949 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2950 .stats_get_strings = mv88e6095_stats_get_strings, 2951 .stats_get_stats = mv88e6095_stats_get_stats, 2952 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2953 .set_egress_port = mv88e6095_g1_set_egress_port, 2954 .watchdog_ops = &mv88e6097_watchdog_ops, 2955 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2956 .pot_clear = mv88e6xxx_g2_pot_clear, 2957 .reset = mv88e6352_g1_reset, 2958 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2959 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2960 }; 2961 2962 static const struct mv88e6xxx_ops mv88e6351_ops = { 2963 /* MV88E6XXX_FAMILY_6351 */ 2964 .irl_init_all = mv88e6352_g2_irl_init_all, 2965 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2966 .phy_read = mv88e6xxx_g2_smi_phy_read, 2967 .phy_write = mv88e6xxx_g2_smi_phy_write, 2968 .port_set_link = mv88e6xxx_port_set_link, 2969 .port_set_duplex = mv88e6xxx_port_set_duplex, 2970 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2971 .port_set_speed = mv88e6185_port_set_speed, 2972 .port_tag_remap = mv88e6095_port_tag_remap, 2973 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2974 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2975 .port_set_ether_type = mv88e6351_port_set_ether_type, 2976 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2977 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2978 .port_pause_limit = mv88e6097_port_pause_limit, 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2981 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2982 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2983 .stats_get_strings = mv88e6095_stats_get_strings, 2984 .stats_get_stats = mv88e6095_stats_get_stats, 2985 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2986 .set_egress_port = mv88e6095_g1_set_egress_port, 2987 .watchdog_ops = &mv88e6097_watchdog_ops, 2988 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2989 .pot_clear = mv88e6xxx_g2_pot_clear, 2990 .reset = mv88e6352_g1_reset, 2991 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2992 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2993 }; 2994 2995 static const struct mv88e6xxx_ops mv88e6352_ops = { 2996 /* MV88E6XXX_FAMILY_6352 */ 2997 .irl_init_all = mv88e6352_g2_irl_init_all, 2998 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2999 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3000 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3001 .phy_read = mv88e6xxx_g2_smi_phy_read, 3002 .phy_write = mv88e6xxx_g2_smi_phy_write, 3003 .port_set_link = mv88e6xxx_port_set_link, 3004 .port_set_duplex = mv88e6xxx_port_set_duplex, 3005 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3006 .port_set_speed = mv88e6352_port_set_speed, 3007 .port_tag_remap = mv88e6095_port_tag_remap, 3008 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3009 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3010 .port_set_ether_type = mv88e6351_port_set_ether_type, 3011 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3012 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3013 .port_pause_limit = mv88e6097_port_pause_limit, 3014 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3015 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3016 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3017 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3018 .stats_get_strings = mv88e6095_stats_get_strings, 3019 .stats_get_stats = mv88e6095_stats_get_stats, 3020 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3021 .set_egress_port = mv88e6095_g1_set_egress_port, 3022 .watchdog_ops = &mv88e6097_watchdog_ops, 3023 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3024 .pot_clear = mv88e6xxx_g2_pot_clear, 3025 .reset = mv88e6352_g1_reset, 3026 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3027 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3028 .serdes_power = mv88e6352_serdes_power, 3029 }; 3030 3031 static const struct mv88e6xxx_ops mv88e6390_ops = { 3032 /* MV88E6XXX_FAMILY_6390 */ 3033 .irl_init_all = mv88e6390_g2_irl_init_all, 3034 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3035 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3037 .phy_read = mv88e6xxx_g2_smi_phy_read, 3038 .phy_write = mv88e6xxx_g2_smi_phy_write, 3039 .port_set_link = mv88e6xxx_port_set_link, 3040 .port_set_duplex = mv88e6xxx_port_set_duplex, 3041 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3042 .port_set_speed = mv88e6390_port_set_speed, 3043 .port_tag_remap = mv88e6390_port_tag_remap, 3044 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3045 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3046 .port_set_ether_type = mv88e6351_port_set_ether_type, 3047 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3048 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3049 .port_pause_limit = mv88e6390_port_pause_limit, 3050 .port_set_cmode = mv88e6390x_port_set_cmode, 3051 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3052 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3053 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3054 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3055 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3056 .stats_get_strings = mv88e6320_stats_get_strings, 3057 .stats_get_stats = mv88e6390_stats_get_stats, 3058 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3059 .set_egress_port = mv88e6390_g1_set_egress_port, 3060 .watchdog_ops = &mv88e6390_watchdog_ops, 3061 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3062 .pot_clear = mv88e6xxx_g2_pot_clear, 3063 .reset = mv88e6352_g1_reset, 3064 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3065 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3066 .serdes_power = mv88e6390_serdes_power, 3067 }; 3068 3069 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3070 /* MV88E6XXX_FAMILY_6390 */ 3071 .irl_init_all = mv88e6390_g2_irl_init_all, 3072 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3073 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3074 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3075 .phy_read = mv88e6xxx_g2_smi_phy_read, 3076 .phy_write = mv88e6xxx_g2_smi_phy_write, 3077 .port_set_link = mv88e6xxx_port_set_link, 3078 .port_set_duplex = mv88e6xxx_port_set_duplex, 3079 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3080 .port_set_speed = mv88e6390x_port_set_speed, 3081 .port_tag_remap = mv88e6390_port_tag_remap, 3082 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3083 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3084 .port_set_ether_type = mv88e6351_port_set_ether_type, 3085 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3086 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3087 .port_pause_limit = mv88e6390_port_pause_limit, 3088 .port_set_cmode = mv88e6390x_port_set_cmode, 3089 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3090 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3091 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3092 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3093 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3094 .stats_get_strings = mv88e6320_stats_get_strings, 3095 .stats_get_stats = mv88e6390_stats_get_stats, 3096 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3097 .set_egress_port = mv88e6390_g1_set_egress_port, 3098 .watchdog_ops = &mv88e6390_watchdog_ops, 3099 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3100 .pot_clear = mv88e6xxx_g2_pot_clear, 3101 .reset = mv88e6352_g1_reset, 3102 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3103 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3104 .serdes_power = mv88e6390_serdes_power, 3105 }; 3106 3107 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3108 [MV88E6085] = { 3109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3110 .family = MV88E6XXX_FAMILY_6097, 3111 .name = "Marvell 88E6085", 3112 .num_databases = 4096, 3113 .num_ports = 10, 3114 .max_vid = 4095, 3115 .port_base_addr = 0x10, 3116 .global1_addr = 0x1b, 3117 .global2_addr = 0x1c, 3118 .age_time_coeff = 15000, 3119 .g1_irqs = 8, 3120 .g2_irqs = 10, 3121 .atu_move_port_mask = 0xf, 3122 .pvt = true, 3123 .multi_chip = true, 3124 .tag_protocol = DSA_TAG_PROTO_DSA, 3125 .ops = &mv88e6085_ops, 3126 }, 3127 3128 [MV88E6095] = { 3129 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3130 .family = MV88E6XXX_FAMILY_6095, 3131 .name = "Marvell 88E6095/88E6095F", 3132 .num_databases = 256, 3133 .num_ports = 11, 3134 .max_vid = 4095, 3135 .port_base_addr = 0x10, 3136 .global1_addr = 0x1b, 3137 .global2_addr = 0x1c, 3138 .age_time_coeff = 15000, 3139 .g1_irqs = 8, 3140 .atu_move_port_mask = 0xf, 3141 .multi_chip = true, 3142 .tag_protocol = DSA_TAG_PROTO_DSA, 3143 .ops = &mv88e6095_ops, 3144 }, 3145 3146 [MV88E6097] = { 3147 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3148 .family = MV88E6XXX_FAMILY_6097, 3149 .name = "Marvell 88E6097/88E6097F", 3150 .num_databases = 4096, 3151 .num_ports = 11, 3152 .max_vid = 4095, 3153 .port_base_addr = 0x10, 3154 .global1_addr = 0x1b, 3155 .global2_addr = 0x1c, 3156 .age_time_coeff = 15000, 3157 .g1_irqs = 8, 3158 .g2_irqs = 10, 3159 .atu_move_port_mask = 0xf, 3160 .pvt = true, 3161 .multi_chip = true, 3162 .tag_protocol = DSA_TAG_PROTO_EDSA, 3163 .ops = &mv88e6097_ops, 3164 }, 3165 3166 [MV88E6123] = { 3167 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3168 .family = MV88E6XXX_FAMILY_6165, 3169 .name = "Marvell 88E6123", 3170 .num_databases = 4096, 3171 .num_ports = 3, 3172 .max_vid = 4095, 3173 .port_base_addr = 0x10, 3174 .global1_addr = 0x1b, 3175 .global2_addr = 0x1c, 3176 .age_time_coeff = 15000, 3177 .g1_irqs = 9, 3178 .g2_irqs = 10, 3179 .atu_move_port_mask = 0xf, 3180 .pvt = true, 3181 .multi_chip = true, 3182 .tag_protocol = DSA_TAG_PROTO_EDSA, 3183 .ops = &mv88e6123_ops, 3184 }, 3185 3186 [MV88E6131] = { 3187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3188 .family = MV88E6XXX_FAMILY_6185, 3189 .name = "Marvell 88E6131", 3190 .num_databases = 256, 3191 .num_ports = 8, 3192 .max_vid = 4095, 3193 .port_base_addr = 0x10, 3194 .global1_addr = 0x1b, 3195 .global2_addr = 0x1c, 3196 .age_time_coeff = 15000, 3197 .g1_irqs = 9, 3198 .atu_move_port_mask = 0xf, 3199 .multi_chip = true, 3200 .tag_protocol = DSA_TAG_PROTO_DSA, 3201 .ops = &mv88e6131_ops, 3202 }, 3203 3204 [MV88E6141] = { 3205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3206 .family = MV88E6XXX_FAMILY_6341, 3207 .name = "Marvell 88E6341", 3208 .num_databases = 4096, 3209 .num_ports = 6, 3210 .max_vid = 4095, 3211 .port_base_addr = 0x10, 3212 .global1_addr = 0x1b, 3213 .global2_addr = 0x1c, 3214 .age_time_coeff = 3750, 3215 .atu_move_port_mask = 0x1f, 3216 .g2_irqs = 10, 3217 .pvt = true, 3218 .multi_chip = true, 3219 .tag_protocol = DSA_TAG_PROTO_EDSA, 3220 .ops = &mv88e6141_ops, 3221 }, 3222 3223 [MV88E6161] = { 3224 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3225 .family = MV88E6XXX_FAMILY_6165, 3226 .name = "Marvell 88E6161", 3227 .num_databases = 4096, 3228 .num_ports = 6, 3229 .max_vid = 4095, 3230 .port_base_addr = 0x10, 3231 .global1_addr = 0x1b, 3232 .global2_addr = 0x1c, 3233 .age_time_coeff = 15000, 3234 .g1_irqs = 9, 3235 .g2_irqs = 10, 3236 .atu_move_port_mask = 0xf, 3237 .pvt = true, 3238 .multi_chip = true, 3239 .tag_protocol = DSA_TAG_PROTO_EDSA, 3240 .ops = &mv88e6161_ops, 3241 }, 3242 3243 [MV88E6165] = { 3244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3245 .family = MV88E6XXX_FAMILY_6165, 3246 .name = "Marvell 88E6165", 3247 .num_databases = 4096, 3248 .num_ports = 6, 3249 .max_vid = 4095, 3250 .port_base_addr = 0x10, 3251 .global1_addr = 0x1b, 3252 .global2_addr = 0x1c, 3253 .age_time_coeff = 15000, 3254 .g1_irqs = 9, 3255 .g2_irqs = 10, 3256 .atu_move_port_mask = 0xf, 3257 .pvt = true, 3258 .multi_chip = true, 3259 .tag_protocol = DSA_TAG_PROTO_DSA, 3260 .ops = &mv88e6165_ops, 3261 }, 3262 3263 [MV88E6171] = { 3264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3265 .family = MV88E6XXX_FAMILY_6351, 3266 .name = "Marvell 88E6171", 3267 .num_databases = 4096, 3268 .num_ports = 7, 3269 .max_vid = 4095, 3270 .port_base_addr = 0x10, 3271 .global1_addr = 0x1b, 3272 .global2_addr = 0x1c, 3273 .age_time_coeff = 15000, 3274 .g1_irqs = 9, 3275 .g2_irqs = 10, 3276 .atu_move_port_mask = 0xf, 3277 .pvt = true, 3278 .multi_chip = true, 3279 .tag_protocol = DSA_TAG_PROTO_EDSA, 3280 .ops = &mv88e6171_ops, 3281 }, 3282 3283 [MV88E6172] = { 3284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3285 .family = MV88E6XXX_FAMILY_6352, 3286 .name = "Marvell 88E6172", 3287 .num_databases = 4096, 3288 .num_ports = 7, 3289 .max_vid = 4095, 3290 .port_base_addr = 0x10, 3291 .global1_addr = 0x1b, 3292 .global2_addr = 0x1c, 3293 .age_time_coeff = 15000, 3294 .g1_irqs = 9, 3295 .g2_irqs = 10, 3296 .atu_move_port_mask = 0xf, 3297 .pvt = true, 3298 .multi_chip = true, 3299 .tag_protocol = DSA_TAG_PROTO_EDSA, 3300 .ops = &mv88e6172_ops, 3301 }, 3302 3303 [MV88E6175] = { 3304 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3305 .family = MV88E6XXX_FAMILY_6351, 3306 .name = "Marvell 88E6175", 3307 .num_databases = 4096, 3308 .num_ports = 7, 3309 .max_vid = 4095, 3310 .port_base_addr = 0x10, 3311 .global1_addr = 0x1b, 3312 .global2_addr = 0x1c, 3313 .age_time_coeff = 15000, 3314 .g1_irqs = 9, 3315 .g2_irqs = 10, 3316 .atu_move_port_mask = 0xf, 3317 .pvt = true, 3318 .multi_chip = true, 3319 .tag_protocol = DSA_TAG_PROTO_EDSA, 3320 .ops = &mv88e6175_ops, 3321 }, 3322 3323 [MV88E6176] = { 3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3325 .family = MV88E6XXX_FAMILY_6352, 3326 .name = "Marvell 88E6176", 3327 .num_databases = 4096, 3328 .num_ports = 7, 3329 .max_vid = 4095, 3330 .port_base_addr = 0x10, 3331 .global1_addr = 0x1b, 3332 .global2_addr = 0x1c, 3333 .age_time_coeff = 15000, 3334 .g1_irqs = 9, 3335 .g2_irqs = 10, 3336 .atu_move_port_mask = 0xf, 3337 .pvt = true, 3338 .multi_chip = true, 3339 .tag_protocol = DSA_TAG_PROTO_EDSA, 3340 .ops = &mv88e6176_ops, 3341 }, 3342 3343 [MV88E6185] = { 3344 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3345 .family = MV88E6XXX_FAMILY_6185, 3346 .name = "Marvell 88E6185", 3347 .num_databases = 256, 3348 .num_ports = 10, 3349 .max_vid = 4095, 3350 .port_base_addr = 0x10, 3351 .global1_addr = 0x1b, 3352 .global2_addr = 0x1c, 3353 .age_time_coeff = 15000, 3354 .g1_irqs = 8, 3355 .atu_move_port_mask = 0xf, 3356 .multi_chip = true, 3357 .tag_protocol = DSA_TAG_PROTO_EDSA, 3358 .ops = &mv88e6185_ops, 3359 }, 3360 3361 [MV88E6190] = { 3362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3363 .family = MV88E6XXX_FAMILY_6390, 3364 .name = "Marvell 88E6190", 3365 .num_databases = 4096, 3366 .num_ports = 11, /* 10 + Z80 */ 3367 .max_vid = 8191, 3368 .port_base_addr = 0x0, 3369 .global1_addr = 0x1b, 3370 .global2_addr = 0x1c, 3371 .tag_protocol = DSA_TAG_PROTO_DSA, 3372 .age_time_coeff = 3750, 3373 .g1_irqs = 9, 3374 .g2_irqs = 14, 3375 .pvt = true, 3376 .multi_chip = true, 3377 .atu_move_port_mask = 0x1f, 3378 .ops = &mv88e6190_ops, 3379 }, 3380 3381 [MV88E6190X] = { 3382 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3383 .family = MV88E6XXX_FAMILY_6390, 3384 .name = "Marvell 88E6190X", 3385 .num_databases = 4096, 3386 .num_ports = 11, /* 10 + Z80 */ 3387 .max_vid = 8191, 3388 .port_base_addr = 0x0, 3389 .global1_addr = 0x1b, 3390 .global2_addr = 0x1c, 3391 .age_time_coeff = 3750, 3392 .g1_irqs = 9, 3393 .g2_irqs = 14, 3394 .atu_move_port_mask = 0x1f, 3395 .pvt = true, 3396 .multi_chip = true, 3397 .tag_protocol = DSA_TAG_PROTO_DSA, 3398 .ops = &mv88e6190x_ops, 3399 }, 3400 3401 [MV88E6191] = { 3402 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3403 .family = MV88E6XXX_FAMILY_6390, 3404 .name = "Marvell 88E6191", 3405 .num_databases = 4096, 3406 .num_ports = 11, /* 10 + Z80 */ 3407 .max_vid = 8191, 3408 .port_base_addr = 0x0, 3409 .global1_addr = 0x1b, 3410 .global2_addr = 0x1c, 3411 .age_time_coeff = 3750, 3412 .g1_irqs = 9, 3413 .g2_irqs = 14, 3414 .atu_move_port_mask = 0x1f, 3415 .pvt = true, 3416 .multi_chip = true, 3417 .tag_protocol = DSA_TAG_PROTO_DSA, 3418 .ops = &mv88e6191_ops, 3419 }, 3420 3421 [MV88E6240] = { 3422 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3423 .family = MV88E6XXX_FAMILY_6352, 3424 .name = "Marvell 88E6240", 3425 .num_databases = 4096, 3426 .num_ports = 7, 3427 .max_vid = 4095, 3428 .port_base_addr = 0x10, 3429 .global1_addr = 0x1b, 3430 .global2_addr = 0x1c, 3431 .age_time_coeff = 15000, 3432 .g1_irqs = 9, 3433 .g2_irqs = 10, 3434 .atu_move_port_mask = 0xf, 3435 .pvt = true, 3436 .multi_chip = true, 3437 .tag_protocol = DSA_TAG_PROTO_EDSA, 3438 .ops = &mv88e6240_ops, 3439 }, 3440 3441 [MV88E6290] = { 3442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3443 .family = MV88E6XXX_FAMILY_6390, 3444 .name = "Marvell 88E6290", 3445 .num_databases = 4096, 3446 .num_ports = 11, /* 10 + Z80 */ 3447 .max_vid = 8191, 3448 .port_base_addr = 0x0, 3449 .global1_addr = 0x1b, 3450 .global2_addr = 0x1c, 3451 .age_time_coeff = 3750, 3452 .g1_irqs = 9, 3453 .g2_irqs = 14, 3454 .atu_move_port_mask = 0x1f, 3455 .pvt = true, 3456 .multi_chip = true, 3457 .tag_protocol = DSA_TAG_PROTO_DSA, 3458 .ops = &mv88e6290_ops, 3459 }, 3460 3461 [MV88E6320] = { 3462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3463 .family = MV88E6XXX_FAMILY_6320, 3464 .name = "Marvell 88E6320", 3465 .num_databases = 4096, 3466 .num_ports = 7, 3467 .max_vid = 4095, 3468 .port_base_addr = 0x10, 3469 .global1_addr = 0x1b, 3470 .global2_addr = 0x1c, 3471 .age_time_coeff = 15000, 3472 .g1_irqs = 8, 3473 .atu_move_port_mask = 0xf, 3474 .pvt = true, 3475 .multi_chip = true, 3476 .tag_protocol = DSA_TAG_PROTO_EDSA, 3477 .ops = &mv88e6320_ops, 3478 }, 3479 3480 [MV88E6321] = { 3481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3482 .family = MV88E6XXX_FAMILY_6320, 3483 .name = "Marvell 88E6321", 3484 .num_databases = 4096, 3485 .num_ports = 7, 3486 .max_vid = 4095, 3487 .port_base_addr = 0x10, 3488 .global1_addr = 0x1b, 3489 .global2_addr = 0x1c, 3490 .age_time_coeff = 15000, 3491 .g1_irqs = 8, 3492 .atu_move_port_mask = 0xf, 3493 .multi_chip = true, 3494 .tag_protocol = DSA_TAG_PROTO_EDSA, 3495 .ops = &mv88e6321_ops, 3496 }, 3497 3498 [MV88E6341] = { 3499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3500 .family = MV88E6XXX_FAMILY_6341, 3501 .name = "Marvell 88E6341", 3502 .num_databases = 4096, 3503 .num_ports = 6, 3504 .max_vid = 4095, 3505 .port_base_addr = 0x10, 3506 .global1_addr = 0x1b, 3507 .global2_addr = 0x1c, 3508 .age_time_coeff = 3750, 3509 .atu_move_port_mask = 0x1f, 3510 .g2_irqs = 10, 3511 .pvt = true, 3512 .multi_chip = true, 3513 .tag_protocol = DSA_TAG_PROTO_EDSA, 3514 .ops = &mv88e6341_ops, 3515 }, 3516 3517 [MV88E6350] = { 3518 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3519 .family = MV88E6XXX_FAMILY_6351, 3520 .name = "Marvell 88E6350", 3521 .num_databases = 4096, 3522 .num_ports = 7, 3523 .max_vid = 4095, 3524 .port_base_addr = 0x10, 3525 .global1_addr = 0x1b, 3526 .global2_addr = 0x1c, 3527 .age_time_coeff = 15000, 3528 .g1_irqs = 9, 3529 .g2_irqs = 10, 3530 .atu_move_port_mask = 0xf, 3531 .pvt = true, 3532 .multi_chip = true, 3533 .tag_protocol = DSA_TAG_PROTO_EDSA, 3534 .ops = &mv88e6350_ops, 3535 }, 3536 3537 [MV88E6351] = { 3538 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3539 .family = MV88E6XXX_FAMILY_6351, 3540 .name = "Marvell 88E6351", 3541 .num_databases = 4096, 3542 .num_ports = 7, 3543 .max_vid = 4095, 3544 .port_base_addr = 0x10, 3545 .global1_addr = 0x1b, 3546 .global2_addr = 0x1c, 3547 .age_time_coeff = 15000, 3548 .g1_irqs = 9, 3549 .g2_irqs = 10, 3550 .atu_move_port_mask = 0xf, 3551 .pvt = true, 3552 .multi_chip = true, 3553 .tag_protocol = DSA_TAG_PROTO_EDSA, 3554 .ops = &mv88e6351_ops, 3555 }, 3556 3557 [MV88E6352] = { 3558 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3559 .family = MV88E6XXX_FAMILY_6352, 3560 .name = "Marvell 88E6352", 3561 .num_databases = 4096, 3562 .num_ports = 7, 3563 .max_vid = 4095, 3564 .port_base_addr = 0x10, 3565 .global1_addr = 0x1b, 3566 .global2_addr = 0x1c, 3567 .age_time_coeff = 15000, 3568 .g1_irqs = 9, 3569 .g2_irqs = 10, 3570 .atu_move_port_mask = 0xf, 3571 .pvt = true, 3572 .multi_chip = true, 3573 .tag_protocol = DSA_TAG_PROTO_EDSA, 3574 .ops = &mv88e6352_ops, 3575 }, 3576 [MV88E6390] = { 3577 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3578 .family = MV88E6XXX_FAMILY_6390, 3579 .name = "Marvell 88E6390", 3580 .num_databases = 4096, 3581 .num_ports = 11, /* 10 + Z80 */ 3582 .max_vid = 8191, 3583 .port_base_addr = 0x0, 3584 .global1_addr = 0x1b, 3585 .global2_addr = 0x1c, 3586 .age_time_coeff = 3750, 3587 .g1_irqs = 9, 3588 .g2_irqs = 14, 3589 .atu_move_port_mask = 0x1f, 3590 .pvt = true, 3591 .multi_chip = true, 3592 .tag_protocol = DSA_TAG_PROTO_DSA, 3593 .ops = &mv88e6390_ops, 3594 }, 3595 [MV88E6390X] = { 3596 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3597 .family = MV88E6XXX_FAMILY_6390, 3598 .name = "Marvell 88E6390X", 3599 .num_databases = 4096, 3600 .num_ports = 11, /* 10 + Z80 */ 3601 .max_vid = 8191, 3602 .port_base_addr = 0x0, 3603 .global1_addr = 0x1b, 3604 .global2_addr = 0x1c, 3605 .age_time_coeff = 3750, 3606 .g1_irqs = 9, 3607 .g2_irqs = 14, 3608 .atu_move_port_mask = 0x1f, 3609 .pvt = true, 3610 .multi_chip = true, 3611 .tag_protocol = DSA_TAG_PROTO_DSA, 3612 .ops = &mv88e6390x_ops, 3613 }, 3614 }; 3615 3616 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3617 { 3618 int i; 3619 3620 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3621 if (mv88e6xxx_table[i].prod_num == prod_num) 3622 return &mv88e6xxx_table[i]; 3623 3624 return NULL; 3625 } 3626 3627 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3628 { 3629 const struct mv88e6xxx_info *info; 3630 unsigned int prod_num, rev; 3631 u16 id; 3632 int err; 3633 3634 mutex_lock(&chip->reg_lock); 3635 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3636 mutex_unlock(&chip->reg_lock); 3637 if (err) 3638 return err; 3639 3640 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3641 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3642 3643 info = mv88e6xxx_lookup_info(prod_num); 3644 if (!info) 3645 return -ENODEV; 3646 3647 /* Update the compatible info with the probed one */ 3648 chip->info = info; 3649 3650 err = mv88e6xxx_g2_require(chip); 3651 if (err) 3652 return err; 3653 3654 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3655 chip->info->prod_num, chip->info->name, rev); 3656 3657 return 0; 3658 } 3659 3660 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3661 { 3662 struct mv88e6xxx_chip *chip; 3663 3664 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3665 if (!chip) 3666 return NULL; 3667 3668 chip->dev = dev; 3669 3670 mutex_init(&chip->reg_lock); 3671 INIT_LIST_HEAD(&chip->mdios); 3672 3673 return chip; 3674 } 3675 3676 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3677 struct mii_bus *bus, int sw_addr) 3678 { 3679 if (sw_addr == 0) 3680 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3681 else if (chip->info->multi_chip) 3682 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3683 else 3684 return -EINVAL; 3685 3686 chip->bus = bus; 3687 chip->sw_addr = sw_addr; 3688 3689 return 0; 3690 } 3691 3692 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3693 { 3694 struct mv88e6xxx_chip *chip = ds->priv; 3695 3696 return chip->info->tag_protocol; 3697 } 3698 3699 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3700 struct device *host_dev, int sw_addr, 3701 void **priv) 3702 { 3703 struct mv88e6xxx_chip *chip; 3704 struct mii_bus *bus; 3705 int err; 3706 3707 bus = dsa_host_dev_to_mii_bus(host_dev); 3708 if (!bus) 3709 return NULL; 3710 3711 chip = mv88e6xxx_alloc_chip(dsa_dev); 3712 if (!chip) 3713 return NULL; 3714 3715 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3716 chip->info = &mv88e6xxx_table[MV88E6085]; 3717 3718 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3719 if (err) 3720 goto free; 3721 3722 err = mv88e6xxx_detect(chip); 3723 if (err) 3724 goto free; 3725 3726 mutex_lock(&chip->reg_lock); 3727 err = mv88e6xxx_switch_reset(chip); 3728 mutex_unlock(&chip->reg_lock); 3729 if (err) 3730 goto free; 3731 3732 mv88e6xxx_phy_init(chip); 3733 3734 err = mv88e6xxx_mdios_register(chip, NULL); 3735 if (err) 3736 goto free; 3737 3738 *priv = chip; 3739 3740 return chip->info->name; 3741 free: 3742 devm_kfree(dsa_dev, chip); 3743 3744 return NULL; 3745 } 3746 3747 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3748 const struct switchdev_obj_port_mdb *mdb, 3749 struct switchdev_trans *trans) 3750 { 3751 /* We don't need any dynamic resource from the kernel (yet), 3752 * so skip the prepare phase. 3753 */ 3754 3755 return 0; 3756 } 3757 3758 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3759 const struct switchdev_obj_port_mdb *mdb, 3760 struct switchdev_trans *trans) 3761 { 3762 struct mv88e6xxx_chip *chip = ds->priv; 3763 3764 mutex_lock(&chip->reg_lock); 3765 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3766 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3767 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3768 port); 3769 mutex_unlock(&chip->reg_lock); 3770 } 3771 3772 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3773 const struct switchdev_obj_port_mdb *mdb) 3774 { 3775 struct mv88e6xxx_chip *chip = ds->priv; 3776 int err; 3777 3778 mutex_lock(&chip->reg_lock); 3779 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3780 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3781 mutex_unlock(&chip->reg_lock); 3782 3783 return err; 3784 } 3785 3786 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3787 .probe = mv88e6xxx_drv_probe, 3788 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3789 .setup = mv88e6xxx_setup, 3790 .adjust_link = mv88e6xxx_adjust_link, 3791 .get_strings = mv88e6xxx_get_strings, 3792 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3793 .get_sset_count = mv88e6xxx_get_sset_count, 3794 .port_enable = mv88e6xxx_port_enable, 3795 .port_disable = mv88e6xxx_port_disable, 3796 .get_mac_eee = mv88e6xxx_get_mac_eee, 3797 .set_mac_eee = mv88e6xxx_set_mac_eee, 3798 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3799 .get_eeprom = mv88e6xxx_get_eeprom, 3800 .set_eeprom = mv88e6xxx_set_eeprom, 3801 .get_regs_len = mv88e6xxx_get_regs_len, 3802 .get_regs = mv88e6xxx_get_regs, 3803 .set_ageing_time = mv88e6xxx_set_ageing_time, 3804 .port_bridge_join = mv88e6xxx_port_bridge_join, 3805 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3806 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3807 .port_fast_age = mv88e6xxx_port_fast_age, 3808 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3809 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3810 .port_vlan_add = mv88e6xxx_port_vlan_add, 3811 .port_vlan_del = mv88e6xxx_port_vlan_del, 3812 .port_fdb_add = mv88e6xxx_port_fdb_add, 3813 .port_fdb_del = mv88e6xxx_port_fdb_del, 3814 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3815 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3816 .port_mdb_add = mv88e6xxx_port_mdb_add, 3817 .port_mdb_del = mv88e6xxx_port_mdb_del, 3818 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3819 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3820 }; 3821 3822 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3823 .ops = &mv88e6xxx_switch_ops, 3824 }; 3825 3826 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3827 { 3828 struct device *dev = chip->dev; 3829 struct dsa_switch *ds; 3830 3831 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3832 if (!ds) 3833 return -ENOMEM; 3834 3835 ds->priv = chip; 3836 ds->ops = &mv88e6xxx_switch_ops; 3837 ds->ageing_time_min = chip->info->age_time_coeff; 3838 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3839 3840 dev_set_drvdata(dev, ds); 3841 3842 return dsa_register_switch(ds); 3843 } 3844 3845 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3846 { 3847 dsa_unregister_switch(chip->ds); 3848 } 3849 3850 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3851 { 3852 struct device *dev = &mdiodev->dev; 3853 struct device_node *np = dev->of_node; 3854 const struct mv88e6xxx_info *compat_info; 3855 struct mv88e6xxx_chip *chip; 3856 u32 eeprom_len; 3857 int err; 3858 3859 compat_info = of_device_get_match_data(dev); 3860 if (!compat_info) 3861 return -EINVAL; 3862 3863 chip = mv88e6xxx_alloc_chip(dev); 3864 if (!chip) 3865 return -ENOMEM; 3866 3867 chip->info = compat_info; 3868 3869 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3870 if (err) 3871 return err; 3872 3873 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3874 if (IS_ERR(chip->reset)) 3875 return PTR_ERR(chip->reset); 3876 3877 err = mv88e6xxx_detect(chip); 3878 if (err) 3879 return err; 3880 3881 mv88e6xxx_phy_init(chip); 3882 3883 if (chip->info->ops->get_eeprom && 3884 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3885 chip->eeprom_len = eeprom_len; 3886 3887 mutex_lock(&chip->reg_lock); 3888 err = mv88e6xxx_switch_reset(chip); 3889 mutex_unlock(&chip->reg_lock); 3890 if (err) 3891 goto out; 3892 3893 chip->irq = of_irq_get(np, 0); 3894 if (chip->irq == -EPROBE_DEFER) { 3895 err = chip->irq; 3896 goto out; 3897 } 3898 3899 if (chip->irq > 0) { 3900 /* Has to be performed before the MDIO bus is created, 3901 * because the PHYs will link there interrupts to these 3902 * interrupt controllers 3903 */ 3904 mutex_lock(&chip->reg_lock); 3905 err = mv88e6xxx_g1_irq_setup(chip); 3906 mutex_unlock(&chip->reg_lock); 3907 3908 if (err) 3909 goto out; 3910 3911 if (chip->info->g2_irqs > 0) { 3912 err = mv88e6xxx_g2_irq_setup(chip); 3913 if (err) 3914 goto out_g1_irq; 3915 } 3916 } 3917 3918 err = mv88e6xxx_mdios_register(chip, np); 3919 if (err) 3920 goto out_g2_irq; 3921 3922 err = mv88e6xxx_register_switch(chip); 3923 if (err) 3924 goto out_mdio; 3925 3926 return 0; 3927 3928 out_mdio: 3929 mv88e6xxx_mdios_unregister(chip); 3930 out_g2_irq: 3931 if (chip->info->g2_irqs > 0 && chip->irq > 0) 3932 mv88e6xxx_g2_irq_free(chip); 3933 out_g1_irq: 3934 if (chip->irq > 0) { 3935 mutex_lock(&chip->reg_lock); 3936 mv88e6xxx_g1_irq_free(chip); 3937 mutex_unlock(&chip->reg_lock); 3938 } 3939 out: 3940 return err; 3941 } 3942 3943 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3944 { 3945 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3946 struct mv88e6xxx_chip *chip = ds->priv; 3947 3948 mv88e6xxx_phy_destroy(chip); 3949 mv88e6xxx_unregister_switch(chip); 3950 mv88e6xxx_mdios_unregister(chip); 3951 3952 if (chip->irq > 0) { 3953 if (chip->info->g2_irqs > 0) 3954 mv88e6xxx_g2_irq_free(chip); 3955 mutex_lock(&chip->reg_lock); 3956 mv88e6xxx_g1_irq_free(chip); 3957 mutex_unlock(&chip->reg_lock); 3958 } 3959 } 3960 3961 static const struct of_device_id mv88e6xxx_of_match[] = { 3962 { 3963 .compatible = "marvell,mv88e6085", 3964 .data = &mv88e6xxx_table[MV88E6085], 3965 }, 3966 { 3967 .compatible = "marvell,mv88e6190", 3968 .data = &mv88e6xxx_table[MV88E6190], 3969 }, 3970 { /* sentinel */ }, 3971 }; 3972 3973 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 3974 3975 static struct mdio_driver mv88e6xxx_driver = { 3976 .probe = mv88e6xxx_probe, 3977 .remove = mv88e6xxx_remove, 3978 .mdiodrv.driver = { 3979 .name = "mv88e6085", 3980 .of_match_table = mv88e6xxx_of_match, 3981 }, 3982 }; 3983 3984 static int __init mv88e6xxx_init(void) 3985 { 3986 register_switch_driver(&mv88e6xxx_switch_drv); 3987 return mdio_driver_register(&mv88e6xxx_driver); 3988 } 3989 module_init(mv88e6xxx_init); 3990 3991 static void __exit mv88e6xxx_cleanup(void) 3992 { 3993 mdio_driver_unregister(&mv88e6xxx_driver); 3994 unregister_switch_driver(&mv88e6xxx_switch_drv); 3995 } 3996 module_exit(mv88e6xxx_cleanup); 3997 3998 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 3999 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4000 MODULE_LICENSE("GPL"); 4001