1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_add_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t **data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i; 1161 1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) 1165 ethtool_puts(data, stat->string); 1166 } 1167 } 1168 1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t **data) 1171 { 1172 mv88e6xxx_stats_get_strings(chip, data, 1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1174 } 1175 1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1177 uint8_t **data) 1178 { 1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1180 } 1181 1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1183 uint8_t **data) 1184 { 1185 mv88e6xxx_stats_get_strings(chip, data, 1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1187 } 1188 1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1190 "atu_member_violation", 1191 "atu_miss_violation", 1192 "atu_full_violation", 1193 "vtu_member_violation", 1194 "vtu_miss_violation", 1195 }; 1196 1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1203 } 1204 1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1206 u32 stringset, uint8_t *data) 1207 { 1208 struct mv88e6xxx_chip *chip = ds->priv; 1209 1210 if (stringset != ETH_SS_STATS) 1211 return; 1212 1213 mv88e6xxx_reg_lock(chip); 1214 1215 if (chip->info->ops->stats_get_strings) 1216 chip->info->ops->stats_get_strings(chip, &data); 1217 1218 if (chip->info->ops->serdes_get_strings) 1219 chip->info->ops->serdes_get_strings(chip, port, &data); 1220 1221 mv88e6xxx_atu_vtu_get_strings(&data); 1222 1223 mv88e6xxx_reg_unlock(chip); 1224 } 1225 1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1227 int types) 1228 { 1229 const struct mv88e6xxx_hw_stat *stat; 1230 int i, j; 1231 1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1233 stat = &mv88e6xxx_hw_stats[i]; 1234 if (stat->type & types) 1235 j++; 1236 } 1237 return j; 1238 } 1239 1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1241 { 1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1243 STATS_TYPE_PORT); 1244 } 1245 1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1247 { 1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1249 } 1250 1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_BANK1); 1255 } 1256 1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1258 { 1259 struct mv88e6xxx_chip *chip = ds->priv; 1260 int serdes_count = 0; 1261 int count = 0; 1262 1263 if (sset != ETH_SS_STATS) 1264 return 0; 1265 1266 mv88e6xxx_reg_lock(chip); 1267 if (chip->info->ops->stats_get_sset_count) 1268 count = chip->info->ops->stats_get_sset_count(chip); 1269 if (count < 0) 1270 goto out; 1271 1272 if (chip->info->ops->serdes_get_sset_count) 1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1274 port); 1275 if (serdes_count < 0) { 1276 count = serdes_count; 1277 goto out; 1278 } 1279 count += serdes_count; 1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1281 1282 out: 1283 mv88e6xxx_reg_unlock(chip); 1284 1285 return count; 1286 } 1287 1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1289 const struct mv88e6xxx_hw_stat *stat, 1290 uint64_t *data) 1291 { 1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1293 MV88E6XXX_G1_STATS_OP_HIST_RX); 1294 return 1; 1295 } 1296 1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1298 const struct mv88e6xxx_hw_stat *stat, 1299 uint64_t *data) 1300 { 1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1302 MV88E6XXX_G1_STATS_OP_HIST_RX); 1303 return 1; 1304 } 1305 1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1307 const struct mv88e6xxx_hw_stat *stat, 1308 uint64_t *data) 1309 { 1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1312 MV88E6XXX_G1_STATS_OP_HIST_RX); 1313 return 1; 1314 } 1315 1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1317 const struct mv88e6xxx_hw_stat *stat, 1318 uint64_t *data) 1319 { 1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1322 0); 1323 return 1; 1324 } 1325 1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1327 const struct mv88e6xxx_hw_stat *stat, 1328 uint64_t *data) 1329 { 1330 int ret = 0; 1331 1332 if (!(stat->type & chip->info->stats_type)) 1333 return 0; 1334 1335 if (chip->info->ops->stats_get_stat) { 1336 mv88e6xxx_reg_lock(chip); 1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 return ret; 1342 } 1343 1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1345 uint64_t *data) 1346 { 1347 const struct mv88e6xxx_hw_stat *stat; 1348 size_t i, j; 1349 1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1351 stat = &mv88e6xxx_hw_stats[i]; 1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1353 } 1354 return j; 1355 } 1356 1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1358 uint64_t *data) 1359 { 1360 *data++ = chip->ports[port].atu_member_violation; 1361 *data++ = chip->ports[port].atu_miss_violation; 1362 *data++ = chip->ports[port].atu_full_violation; 1363 *data++ = chip->ports[port].vtu_member_violation; 1364 *data++ = chip->ports[port].vtu_miss_violation; 1365 } 1366 1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1368 uint64_t *data) 1369 { 1370 size_t count; 1371 1372 count = mv88e6xxx_stats_get_stats(chip, port, data); 1373 1374 mv88e6xxx_reg_lock(chip); 1375 if (chip->info->ops->serdes_get_stats) { 1376 data += count; 1377 count = chip->info->ops->serdes_get_stats(chip, port, data); 1378 } 1379 data += count; 1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1381 mv88e6xxx_reg_unlock(chip); 1382 } 1383 1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1385 uint64_t *data) 1386 { 1387 struct mv88e6xxx_chip *chip = ds->priv; 1388 int ret; 1389 1390 ret = mv88e6xxx_stats_snapshot(chip, port); 1391 if (ret < 0) 1392 return; 1393 1394 mv88e6xxx_get_stats(chip, port, data); 1395 } 1396 1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1398 struct ethtool_eth_mac_stats *mac_stats) 1399 { 1400 struct mv88e6xxx_chip *chip = ds->priv; 1401 int ret; 1402 1403 ret = mv88e6xxx_stats_snapshot(chip, port); 1404 if (ret < 0) 1405 return; 1406 1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1408 mv88e6xxx_stats_get_stat(chip, port, \ 1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1410 &mac_stats->stats._member) 1411 1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1426 1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1428 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1433 } 1434 1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1436 struct ethtool_rmon_stats *rmon_stats, 1437 const struct ethtool_rmon_hist_range **ranges) 1438 { 1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1440 { 64, 64 }, 1441 { 65, 127 }, 1442 { 128, 255 }, 1443 { 256, 511 }, 1444 { 512, 1023 }, 1445 { 1024, 65535 }, 1446 {} 1447 }; 1448 struct mv88e6xxx_chip *chip = ds->priv; 1449 int ret; 1450 1451 ret = mv88e6xxx_stats_snapshot(chip, port); 1452 if (ret < 0) 1453 return; 1454 1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1456 mv88e6xxx_stats_get_stat(chip, port, \ 1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1458 &rmon_stats->stats._member) 1459 1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1470 1471 #undef MV88E6XXX_RMON_STAT_MAP 1472 1473 *ranges = rmon_ranges; 1474 } 1475 1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int len; 1480 1481 len = 32 * sizeof(u16); 1482 if (chip->info->ops->serdes_get_regs_len) 1483 len += chip->info->ops->serdes_get_regs_len(chip, port); 1484 1485 return len; 1486 } 1487 1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1489 struct ethtool_regs *regs, void *_p) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 int err; 1493 u16 reg; 1494 u16 *p = _p; 1495 int i; 1496 1497 regs->version = chip->info->prod_num; 1498 1499 memset(p, 0xff, 32 * sizeof(u16)); 1500 1501 mv88e6xxx_reg_lock(chip); 1502 1503 for (i = 0; i < 32; i++) { 1504 1505 err = mv88e6xxx_port_read(chip, port, i, ®); 1506 if (!err) 1507 p[i] = reg; 1508 } 1509 1510 if (chip->info->ops->serdes_get_regs) 1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1512 1513 mv88e6xxx_reg_unlock(chip); 1514 } 1515 1516 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1517 struct ethtool_keee *e) 1518 { 1519 /* Nothing to do on the port's MAC */ 1520 return 0; 1521 } 1522 1523 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1525 { 1526 struct dsa_switch *ds = chip->ds; 1527 struct dsa_switch_tree *dst = ds->dst; 1528 struct dsa_port *dp, *other_dp; 1529 bool found = false; 1530 u16 pvlan; 1531 1532 /* dev is a physical switch */ 1533 if (dev <= dst->last_switch) { 1534 list_for_each_entry(dp, &dst->ports, list) { 1535 if (dp->ds->index == dev && dp->index == port) { 1536 /* dp might be a DSA link or a user port, so it 1537 * might or might not have a bridge. 1538 * Use the "found" variable for both cases. 1539 */ 1540 found = true; 1541 break; 1542 } 1543 } 1544 /* dev is a virtual bridge */ 1545 } else { 1546 list_for_each_entry(dp, &dst->ports, list) { 1547 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1548 1549 if (!bridge_num) 1550 continue; 1551 1552 if (bridge_num + dst->last_switch != dev) 1553 continue; 1554 1555 found = true; 1556 break; 1557 } 1558 } 1559 1560 /* Prevent frames from unknown switch or virtual bridge */ 1561 if (!found) 1562 return 0; 1563 1564 /* Frames from DSA links and CPU ports can egress any local port */ 1565 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1566 return mv88e6xxx_port_mask(chip); 1567 1568 pvlan = 0; 1569 1570 /* Frames from standalone user ports can only egress on the 1571 * upstream port. 1572 */ 1573 if (!dsa_port_bridge_dev_get(dp)) 1574 return BIT(dsa_switch_upstream_port(ds)); 1575 1576 /* Frames from bridged user ports can egress any local DSA 1577 * links and CPU ports, as well as any local member of their 1578 * bridge group. 1579 */ 1580 dsa_switch_for_each_port(other_dp, ds) 1581 if (other_dp->type == DSA_PORT_TYPE_CPU || 1582 other_dp->type == DSA_PORT_TYPE_DSA || 1583 dsa_port_bridge_same(dp, other_dp)) 1584 pvlan |= BIT(other_dp->index); 1585 1586 return pvlan; 1587 } 1588 1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1590 { 1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1592 1593 /* prevent frames from going back out of the port they came in on */ 1594 output_ports &= ~BIT(port); 1595 1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1597 } 1598 1599 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1600 u8 state) 1601 { 1602 struct mv88e6xxx_chip *chip = ds->priv; 1603 int err; 1604 1605 mv88e6xxx_reg_lock(chip); 1606 err = mv88e6xxx_port_set_state(chip, port, state); 1607 mv88e6xxx_reg_unlock(chip); 1608 1609 if (err) 1610 dev_err(ds->dev, "p%d: failed to update state\n", port); 1611 } 1612 1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1614 { 1615 int err; 1616 1617 if (chip->info->ops->ieee_pri_map) { 1618 err = chip->info->ops->ieee_pri_map(chip); 1619 if (err) 1620 return err; 1621 } 1622 1623 if (chip->info->ops->ip_pri_map) { 1624 err = chip->info->ops->ip_pri_map(chip); 1625 if (err) 1626 return err; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1633 { 1634 struct dsa_switch *ds = chip->ds; 1635 int target, port; 1636 int err; 1637 1638 if (!chip->info->global2_addr) 1639 return 0; 1640 1641 /* Initialize the routing port to the 32 possible target devices */ 1642 for (target = 0; target < 32; target++) { 1643 port = dsa_routing_port(ds, target); 1644 if (port == ds->num_ports) 1645 port = 0x1f; 1646 1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1648 if (err) 1649 return err; 1650 } 1651 1652 if (chip->info->ops->set_cascade_port) { 1653 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1654 err = chip->info->ops->set_cascade_port(chip, port); 1655 if (err) 1656 return err; 1657 } 1658 1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1660 if (err) 1661 return err; 1662 1663 return 0; 1664 } 1665 1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1667 { 1668 /* Clear all trunk masks and mapping */ 1669 if (chip->info->global2_addr) 1670 return mv88e6xxx_g2_trunk_clear(chip); 1671 1672 return 0; 1673 } 1674 1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1676 { 1677 if (chip->info->ops->rmu_disable) 1678 return chip->info->ops->rmu_disable(chip); 1679 1680 return 0; 1681 } 1682 1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1684 { 1685 if (chip->info->ops->pot_clear) 1686 return chip->info->ops->pot_clear(chip); 1687 1688 return 0; 1689 } 1690 1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1692 { 1693 if (chip->info->ops->mgmt_rsvd2cpu) 1694 return chip->info->ops->mgmt_rsvd2cpu(chip); 1695 1696 return 0; 1697 } 1698 1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1700 { 1701 int err; 1702 1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1704 if (err) 1705 return err; 1706 1707 /* The chips that have a "learn2all" bit in Global1, ATU 1708 * Control are precisely those whose port registers have a 1709 * Message Port bit in Port Control 1 and hence implement 1710 * ->port_setup_message_port. 1711 */ 1712 if (chip->info->ops->port_setup_message_port) { 1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1714 if (err) 1715 return err; 1716 } 1717 1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1719 } 1720 1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1722 { 1723 int port; 1724 int err; 1725 1726 if (!chip->info->ops->irl_init_all) 1727 return 0; 1728 1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1730 /* Disable ingress rate limiting by resetting all per port 1731 * ingress rate limit resources to their initial state. 1732 */ 1733 err = chip->info->ops->irl_init_all(chip, port); 1734 if (err) 1735 return err; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1742 { 1743 if (chip->info->ops->set_switch_mac) { 1744 u8 addr[ETH_ALEN]; 1745 1746 eth_random_addr(addr); 1747 1748 return chip->info->ops->set_switch_mac(chip, addr); 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1755 { 1756 struct dsa_switch_tree *dst = chip->ds->dst; 1757 struct dsa_switch *ds; 1758 struct dsa_port *dp; 1759 u16 pvlan = 0; 1760 1761 if (!mv88e6xxx_has_pvt(chip)) 1762 return 0; 1763 1764 /* Skip the local source device, which uses in-chip port VLAN */ 1765 if (dev != chip->ds->index) { 1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1767 1768 ds = dsa_switch_find(dst->index, dev); 1769 dp = ds ? dsa_to_port(ds, port) : NULL; 1770 if (dp && dp->lag) { 1771 /* As the PVT is used to limit flooding of 1772 * FORWARD frames, which use the LAG ID as the 1773 * source port, we must translate dev/port to 1774 * the special "LAG device" in the PVT, using 1775 * the LAG ID (one-based) as the port number 1776 * (zero-based). 1777 */ 1778 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1779 port = dsa_port_lag_id_get(dp) - 1; 1780 } 1781 } 1782 1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1784 } 1785 1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1787 { 1788 int dev, port; 1789 int err; 1790 1791 if (!mv88e6xxx_has_pvt(chip)) 1792 return 0; 1793 1794 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1795 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1796 */ 1797 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1798 if (err) 1799 return err; 1800 1801 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1802 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1803 err = mv88e6xxx_pvt_map(chip, dev, port); 1804 if (err) 1805 return err; 1806 } 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1813 u16 fid) 1814 { 1815 if (dsa_to_port(chip->ds, port)->lag) 1816 /* Hardware is incapable of fast-aging a LAG through a 1817 * regular ATU move operation. Until we have something 1818 * more fancy in place this is a no-op. 1819 */ 1820 return -EOPNOTSUPP; 1821 1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1823 } 1824 1825 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1826 { 1827 struct mv88e6xxx_chip *chip = ds->priv; 1828 int err; 1829 1830 mv88e6xxx_reg_lock(chip); 1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1832 mv88e6xxx_reg_unlock(chip); 1833 1834 if (err) 1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1836 port, err); 1837 } 1838 1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1840 { 1841 if (!mv88e6xxx_max_vid(chip)) 1842 return 0; 1843 1844 return mv88e6xxx_g1_vtu_flush(chip); 1845 } 1846 1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1848 struct mv88e6xxx_vtu_entry *entry) 1849 { 1850 int err; 1851 1852 if (!chip->info->ops->vtu_getnext) 1853 return -EOPNOTSUPP; 1854 1855 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1856 entry->valid = false; 1857 1858 err = chip->info->ops->vtu_getnext(chip, entry); 1859 1860 if (entry->vid != vid) 1861 entry->valid = false; 1862 1863 return err; 1864 } 1865 1866 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1867 int (*cb)(struct mv88e6xxx_chip *chip, 1868 const struct mv88e6xxx_vtu_entry *entry, 1869 void *priv), 1870 void *priv) 1871 { 1872 struct mv88e6xxx_vtu_entry entry = { 1873 .vid = mv88e6xxx_max_vid(chip), 1874 .valid = false, 1875 }; 1876 int err; 1877 1878 if (!chip->info->ops->vtu_getnext) 1879 return -EOPNOTSUPP; 1880 1881 do { 1882 err = chip->info->ops->vtu_getnext(chip, &entry); 1883 if (err) 1884 return err; 1885 1886 if (!entry.valid) 1887 break; 1888 1889 err = cb(chip, &entry, priv); 1890 if (err) 1891 return err; 1892 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1893 1894 return 0; 1895 } 1896 1897 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1898 struct mv88e6xxx_vtu_entry *entry) 1899 { 1900 if (!chip->info->ops->vtu_loadpurge) 1901 return -EOPNOTSUPP; 1902 1903 return chip->info->ops->vtu_loadpurge(chip, entry); 1904 } 1905 1906 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1907 { 1908 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1909 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1910 return -ENOSPC; 1911 1912 /* Clear the database */ 1913 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1914 } 1915 1916 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1917 struct mv88e6xxx_stu_entry *entry) 1918 { 1919 if (!chip->info->ops->stu_loadpurge) 1920 return -EOPNOTSUPP; 1921 1922 return chip->info->ops->stu_loadpurge(chip, entry); 1923 } 1924 1925 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1926 { 1927 struct mv88e6xxx_stu_entry stu = { 1928 .valid = true, 1929 .sid = 0 1930 }; 1931 1932 if (!mv88e6xxx_has_stu(chip)) 1933 return 0; 1934 1935 /* Make sure that SID 0 is always valid. This is used by VTU 1936 * entries that do not make use of the STU, e.g. when creating 1937 * a VLAN upper on a port that is also part of a VLAN 1938 * filtering bridge. 1939 */ 1940 return mv88e6xxx_stu_loadpurge(chip, &stu); 1941 } 1942 1943 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1944 { 1945 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1946 struct mv88e6xxx_mst *mst; 1947 1948 __set_bit(0, busy); 1949 1950 list_for_each_entry(mst, &chip->msts, node) 1951 __set_bit(mst->stu.sid, busy); 1952 1953 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1954 1955 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1956 } 1957 1958 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1959 { 1960 struct mv88e6xxx_mst *mst, *tmp; 1961 int err; 1962 1963 if (!sid) 1964 return 0; 1965 1966 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1967 if (mst->stu.sid != sid) 1968 continue; 1969 1970 if (!refcount_dec_and_test(&mst->refcnt)) 1971 return 0; 1972 1973 mst->stu.valid = false; 1974 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1975 if (err) { 1976 refcount_set(&mst->refcnt, 1); 1977 return err; 1978 } 1979 1980 list_del(&mst->node); 1981 kfree(mst); 1982 return 0; 1983 } 1984 1985 return -ENOENT; 1986 } 1987 1988 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1989 u16 msti, u8 *sid) 1990 { 1991 struct mv88e6xxx_mst *mst; 1992 int err, i; 1993 1994 if (!mv88e6xxx_has_stu(chip)) { 1995 err = -EOPNOTSUPP; 1996 goto err; 1997 } 1998 1999 if (!msti) { 2000 *sid = 0; 2001 return 0; 2002 } 2003 2004 list_for_each_entry(mst, &chip->msts, node) { 2005 if (mst->br == br && mst->msti == msti) { 2006 refcount_inc(&mst->refcnt); 2007 *sid = mst->stu.sid; 2008 return 0; 2009 } 2010 } 2011 2012 err = mv88e6xxx_sid_get(chip, sid); 2013 if (err) 2014 goto err; 2015 2016 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2017 if (!mst) { 2018 err = -ENOMEM; 2019 goto err; 2020 } 2021 2022 INIT_LIST_HEAD(&mst->node); 2023 refcount_set(&mst->refcnt, 1); 2024 mst->br = br; 2025 mst->msti = msti; 2026 mst->stu.valid = true; 2027 mst->stu.sid = *sid; 2028 2029 /* The bridge starts out all ports in the disabled state. But 2030 * a STU state of disabled means to go by the port-global 2031 * state. So we set all user port's initial state to blocking, 2032 * to match the bridge's behavior. 2033 */ 2034 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2035 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2036 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2037 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2038 2039 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2040 if (err) 2041 goto err_free; 2042 2043 list_add_tail(&mst->node, &chip->msts); 2044 return 0; 2045 2046 err_free: 2047 kfree(mst); 2048 err: 2049 return err; 2050 } 2051 2052 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2053 const struct switchdev_mst_state *st) 2054 { 2055 struct dsa_port *dp = dsa_to_port(ds, port); 2056 struct mv88e6xxx_chip *chip = ds->priv; 2057 struct mv88e6xxx_mst *mst; 2058 u8 state; 2059 int err; 2060 2061 if (!mv88e6xxx_has_stu(chip)) 2062 return -EOPNOTSUPP; 2063 2064 switch (st->state) { 2065 case BR_STATE_DISABLED: 2066 case BR_STATE_BLOCKING: 2067 case BR_STATE_LISTENING: 2068 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2069 break; 2070 case BR_STATE_LEARNING: 2071 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2072 break; 2073 case BR_STATE_FORWARDING: 2074 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2075 break; 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 list_for_each_entry(mst, &chip->msts, node) { 2081 if (mst->br == dsa_port_bridge_dev_get(dp) && 2082 mst->msti == st->msti) { 2083 if (mst->stu.state[port] == state) 2084 return 0; 2085 2086 mst->stu.state[port] = state; 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2089 mv88e6xxx_reg_unlock(chip); 2090 return err; 2091 } 2092 } 2093 2094 return -ENOENT; 2095 } 2096 2097 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2098 u16 vid) 2099 { 2100 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2101 struct mv88e6xxx_chip *chip = ds->priv; 2102 struct mv88e6xxx_vtu_entry vlan; 2103 int err; 2104 2105 /* DSA and CPU ports have to be members of multiple vlans */ 2106 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2107 return 0; 2108 2109 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2110 if (err) 2111 return err; 2112 2113 if (!vlan.valid) 2114 return 0; 2115 2116 dsa_switch_for_each_user_port(other_dp, ds) { 2117 struct net_device *other_br; 2118 2119 if (vlan.member[other_dp->index] == 2120 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2121 continue; 2122 2123 if (dsa_port_bridge_same(dp, other_dp)) 2124 break; /* same bridge, check next VLAN */ 2125 2126 other_br = dsa_port_bridge_dev_get(other_dp); 2127 if (!other_br) 2128 continue; 2129 2130 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2131 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2132 return -EOPNOTSUPP; 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2139 { 2140 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2141 struct net_device *br = dsa_port_bridge_dev_get(dp); 2142 struct mv88e6xxx_port *p = &chip->ports[port]; 2143 u16 pvid = MV88E6XXX_VID_STANDALONE; 2144 bool drop_untagged = false; 2145 int err; 2146 2147 if (br) { 2148 if (br_vlan_enabled(br)) { 2149 pvid = p->bridge_pvid.vid; 2150 drop_untagged = !p->bridge_pvid.valid; 2151 } else { 2152 pvid = MV88E6XXX_VID_BRIDGED; 2153 } 2154 } 2155 2156 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2157 if (err) 2158 return err; 2159 2160 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2161 } 2162 2163 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2164 bool vlan_filtering, 2165 struct netlink_ext_ack *extack) 2166 { 2167 struct mv88e6xxx_chip *chip = ds->priv; 2168 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2169 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2170 int err; 2171 2172 if (!mv88e6xxx_max_vid(chip)) 2173 return -EOPNOTSUPP; 2174 2175 mv88e6xxx_reg_lock(chip); 2176 2177 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2178 if (err) 2179 goto unlock; 2180 2181 err = mv88e6xxx_port_commit_pvid(chip, port); 2182 if (err) 2183 goto unlock; 2184 2185 unlock: 2186 mv88e6xxx_reg_unlock(chip); 2187 2188 return err; 2189 } 2190 2191 static int 2192 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2193 const struct switchdev_obj_port_vlan *vlan) 2194 { 2195 struct mv88e6xxx_chip *chip = ds->priv; 2196 int err; 2197 2198 if (!mv88e6xxx_max_vid(chip)) 2199 return -EOPNOTSUPP; 2200 2201 /* If the requested port doesn't belong to the same bridge as the VLAN 2202 * members, do not support it (yet) and fallback to software VLAN. 2203 */ 2204 mv88e6xxx_reg_lock(chip); 2205 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2206 mv88e6xxx_reg_unlock(chip); 2207 2208 return err; 2209 } 2210 2211 static int mv88e6xxx_port_db_get(struct mv88e6xxx_chip *chip, 2212 const unsigned char *addr, u16 vid, 2213 u16 *fid, struct mv88e6xxx_atu_entry *entry) 2214 { 2215 struct mv88e6xxx_vtu_entry vlan; 2216 int err; 2217 2218 /* Ports have two private address databases: one for when the port is 2219 * standalone and one for when the port is under a bridge and the 2220 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2221 * address database to remain 100% empty, so we never load an ATU entry 2222 * into a standalone port's database. Therefore, translate the null 2223 * VLAN ID into the port's database used for VLAN-unaware bridging. 2224 */ 2225 if (vid == 0) { 2226 *fid = MV88E6XXX_FID_BRIDGED; 2227 } else { 2228 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2229 if (err) 2230 return err; 2231 2232 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2233 if (!vlan.valid) 2234 return -EOPNOTSUPP; 2235 2236 *fid = vlan.fid; 2237 } 2238 2239 entry->state = 0; 2240 ether_addr_copy(entry->mac, addr); 2241 eth_addr_dec(entry->mac); 2242 2243 return mv88e6xxx_g1_atu_getnext(chip, *fid, entry); 2244 } 2245 2246 static bool mv88e6xxx_port_db_find(struct mv88e6xxx_chip *chip, 2247 const unsigned char *addr, u16 vid) 2248 { 2249 struct mv88e6xxx_atu_entry entry; 2250 u16 fid; 2251 int err; 2252 2253 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2254 if (err) 2255 return false; 2256 2257 return entry.state && ether_addr_equal(entry.mac, addr); 2258 } 2259 2260 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2261 const unsigned char *addr, u16 vid, 2262 u8 state) 2263 { 2264 struct mv88e6xxx_atu_entry entry; 2265 u16 fid; 2266 int err; 2267 2268 err = mv88e6xxx_port_db_get(chip, addr, vid, &fid, &entry); 2269 if (err) 2270 return err; 2271 2272 /* Initialize a fresh ATU entry if it isn't found */ 2273 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2274 memset(&entry, 0, sizeof(entry)); 2275 ether_addr_copy(entry.mac, addr); 2276 } 2277 2278 /* Purge the ATU entry only if no port is using it anymore */ 2279 if (!state) { 2280 entry.portvec &= ~BIT(port); 2281 if (!entry.portvec) 2282 entry.state = 0; 2283 } else { 2284 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2285 entry.portvec = BIT(port); 2286 else 2287 entry.portvec |= BIT(port); 2288 2289 entry.state = state; 2290 } 2291 2292 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2293 } 2294 2295 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2296 const struct mv88e6xxx_policy *policy) 2297 { 2298 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2299 enum mv88e6xxx_policy_action action = policy->action; 2300 const u8 *addr = policy->addr; 2301 u16 vid = policy->vid; 2302 u8 state; 2303 int err; 2304 int id; 2305 2306 if (!chip->info->ops->port_set_policy) 2307 return -EOPNOTSUPP; 2308 2309 switch (mapping) { 2310 case MV88E6XXX_POLICY_MAPPING_DA: 2311 case MV88E6XXX_POLICY_MAPPING_SA: 2312 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2313 state = 0; /* Dissociate the port and address */ 2314 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2315 is_multicast_ether_addr(addr)) 2316 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2317 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2318 is_unicast_ether_addr(addr)) 2319 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2320 else 2321 return -EOPNOTSUPP; 2322 2323 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2324 state); 2325 if (err) 2326 return err; 2327 break; 2328 default: 2329 return -EOPNOTSUPP; 2330 } 2331 2332 /* Skip the port's policy clearing if the mapping is still in use */ 2333 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2334 idr_for_each_entry(&chip->policies, policy, id) 2335 if (policy->port == port && 2336 policy->mapping == mapping && 2337 policy->action != action) 2338 return 0; 2339 2340 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2341 } 2342 2343 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2344 struct ethtool_rx_flow_spec *fs) 2345 { 2346 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2347 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2348 enum mv88e6xxx_policy_mapping mapping; 2349 enum mv88e6xxx_policy_action action; 2350 struct mv88e6xxx_policy *policy; 2351 u16 vid = 0; 2352 u8 *addr; 2353 int err; 2354 int id; 2355 2356 if (fs->location != RX_CLS_LOC_ANY) 2357 return -EINVAL; 2358 2359 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2360 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2361 else 2362 return -EOPNOTSUPP; 2363 2364 switch (fs->flow_type & ~FLOW_EXT) { 2365 case ETHER_FLOW: 2366 if (!is_zero_ether_addr(mac_mask->h_dest) && 2367 is_zero_ether_addr(mac_mask->h_source)) { 2368 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2369 addr = mac_entry->h_dest; 2370 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2371 !is_zero_ether_addr(mac_mask->h_source)) { 2372 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2373 addr = mac_entry->h_source; 2374 } else { 2375 /* Cannot support DA and SA mapping in the same rule */ 2376 return -EOPNOTSUPP; 2377 } 2378 break; 2379 default: 2380 return -EOPNOTSUPP; 2381 } 2382 2383 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2384 if (fs->m_ext.vlan_tci != htons(0xffff)) 2385 return -EOPNOTSUPP; 2386 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2387 } 2388 2389 idr_for_each_entry(&chip->policies, policy, id) { 2390 if (policy->port == port && policy->mapping == mapping && 2391 policy->action == action && policy->vid == vid && 2392 ether_addr_equal(policy->addr, addr)) 2393 return -EEXIST; 2394 } 2395 2396 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2397 if (!policy) 2398 return -ENOMEM; 2399 2400 fs->location = 0; 2401 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2402 GFP_KERNEL); 2403 if (err) { 2404 devm_kfree(chip->dev, policy); 2405 return err; 2406 } 2407 2408 memcpy(&policy->fs, fs, sizeof(*fs)); 2409 ether_addr_copy(policy->addr, addr); 2410 policy->mapping = mapping; 2411 policy->action = action; 2412 policy->port = port; 2413 policy->vid = vid; 2414 2415 err = mv88e6xxx_policy_apply(chip, port, policy); 2416 if (err) { 2417 idr_remove(&chip->policies, fs->location); 2418 devm_kfree(chip->dev, policy); 2419 return err; 2420 } 2421 2422 return 0; 2423 } 2424 2425 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2426 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2427 { 2428 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2429 struct mv88e6xxx_chip *chip = ds->priv; 2430 struct mv88e6xxx_policy *policy; 2431 int err; 2432 int id; 2433 2434 mv88e6xxx_reg_lock(chip); 2435 2436 switch (rxnfc->cmd) { 2437 case ETHTOOL_GRXCLSRLCNT: 2438 rxnfc->data = 0; 2439 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2440 rxnfc->rule_cnt = 0; 2441 idr_for_each_entry(&chip->policies, policy, id) 2442 if (policy->port == port) 2443 rxnfc->rule_cnt++; 2444 err = 0; 2445 break; 2446 case ETHTOOL_GRXCLSRULE: 2447 err = -ENOENT; 2448 policy = idr_find(&chip->policies, fs->location); 2449 if (policy) { 2450 memcpy(fs, &policy->fs, sizeof(*fs)); 2451 err = 0; 2452 } 2453 break; 2454 case ETHTOOL_GRXCLSRLALL: 2455 rxnfc->data = 0; 2456 rxnfc->rule_cnt = 0; 2457 idr_for_each_entry(&chip->policies, policy, id) 2458 if (policy->port == port) 2459 rule_locs[rxnfc->rule_cnt++] = id; 2460 err = 0; 2461 break; 2462 default: 2463 err = -EOPNOTSUPP; 2464 break; 2465 } 2466 2467 mv88e6xxx_reg_unlock(chip); 2468 2469 return err; 2470 } 2471 2472 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2473 struct ethtool_rxnfc *rxnfc) 2474 { 2475 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2476 struct mv88e6xxx_chip *chip = ds->priv; 2477 struct mv88e6xxx_policy *policy; 2478 int err; 2479 2480 mv88e6xxx_reg_lock(chip); 2481 2482 switch (rxnfc->cmd) { 2483 case ETHTOOL_SRXCLSRLINS: 2484 err = mv88e6xxx_policy_insert(chip, port, fs); 2485 break; 2486 case ETHTOOL_SRXCLSRLDEL: 2487 err = -ENOENT; 2488 policy = idr_remove(&chip->policies, fs->location); 2489 if (policy) { 2490 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2491 err = mv88e6xxx_policy_apply(chip, port, policy); 2492 devm_kfree(chip->dev, policy); 2493 } 2494 break; 2495 default: 2496 err = -EOPNOTSUPP; 2497 break; 2498 } 2499 2500 mv88e6xxx_reg_unlock(chip); 2501 2502 return err; 2503 } 2504 2505 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2506 u16 vid) 2507 { 2508 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2509 u8 broadcast[ETH_ALEN]; 2510 2511 eth_broadcast_addr(broadcast); 2512 2513 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2514 } 2515 2516 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2517 { 2518 int port; 2519 int err; 2520 2521 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2522 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2523 struct net_device *brport; 2524 2525 if (dsa_is_unused_port(chip->ds, port)) 2526 continue; 2527 2528 brport = dsa_port_to_bridge_port(dp); 2529 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2530 /* Skip bridged user ports where broadcast 2531 * flooding is disabled. 2532 */ 2533 continue; 2534 2535 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2536 if (err) 2537 return err; 2538 } 2539 2540 return 0; 2541 } 2542 2543 struct mv88e6xxx_port_broadcast_sync_ctx { 2544 int port; 2545 bool flood; 2546 }; 2547 2548 static int 2549 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2550 const struct mv88e6xxx_vtu_entry *vlan, 2551 void *_ctx) 2552 { 2553 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2554 u8 broadcast[ETH_ALEN]; 2555 u8 state; 2556 2557 if (ctx->flood) 2558 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2559 else 2560 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2561 2562 eth_broadcast_addr(broadcast); 2563 2564 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2565 vlan->vid, state); 2566 } 2567 2568 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2569 bool flood) 2570 { 2571 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2572 .port = port, 2573 .flood = flood, 2574 }; 2575 struct mv88e6xxx_vtu_entry vid0 = { 2576 .vid = 0, 2577 }; 2578 int err; 2579 2580 /* Update the port's private database... */ 2581 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2582 if (err) 2583 return err; 2584 2585 /* ...and the database for all VLANs. */ 2586 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2587 &ctx); 2588 } 2589 2590 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2591 u16 vid, u8 member, bool warn) 2592 { 2593 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2594 struct mv88e6xxx_vtu_entry vlan; 2595 int i, err; 2596 2597 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2598 if (err) 2599 return err; 2600 2601 if (!vlan.valid) { 2602 memset(&vlan, 0, sizeof(vlan)); 2603 2604 if (vid == MV88E6XXX_VID_STANDALONE) 2605 vlan.policy = true; 2606 2607 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2608 if (err) 2609 return err; 2610 2611 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2612 if (i == port) 2613 vlan.member[i] = member; 2614 else 2615 vlan.member[i] = non_member; 2616 2617 vlan.vid = vid; 2618 vlan.valid = true; 2619 2620 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2621 if (err) 2622 return err; 2623 2624 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2625 if (err) 2626 return err; 2627 } else if (vlan.member[port] != member) { 2628 vlan.member[port] = member; 2629 2630 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2631 if (err) 2632 return err; 2633 } else if (warn) { 2634 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2635 port, vid); 2636 } 2637 2638 /* Record FID used in SW FID map */ 2639 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2640 2641 return 0; 2642 } 2643 2644 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2645 const struct switchdev_obj_port_vlan *vlan, 2646 struct netlink_ext_ack *extack) 2647 { 2648 struct mv88e6xxx_chip *chip = ds->priv; 2649 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2650 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2651 struct mv88e6xxx_port *p = &chip->ports[port]; 2652 bool warn; 2653 u8 member; 2654 int err; 2655 2656 if (!vlan->vid) 2657 return 0; 2658 2659 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2660 if (err) 2661 return err; 2662 2663 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2664 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2665 else if (untagged) 2666 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2667 else 2668 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2669 2670 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2671 * and then the CPU port. Do not warn for duplicates for the CPU port. 2672 */ 2673 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2674 2675 mv88e6xxx_reg_lock(chip); 2676 2677 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2678 if (err) { 2679 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2680 vlan->vid, untagged ? 'u' : 't'); 2681 goto out; 2682 } 2683 2684 if (pvid) { 2685 p->bridge_pvid.vid = vlan->vid; 2686 p->bridge_pvid.valid = true; 2687 2688 err = mv88e6xxx_port_commit_pvid(chip, port); 2689 if (err) 2690 goto out; 2691 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2692 /* The old pvid was reinstalled as a non-pvid VLAN */ 2693 p->bridge_pvid.valid = false; 2694 2695 err = mv88e6xxx_port_commit_pvid(chip, port); 2696 if (err) 2697 goto out; 2698 } 2699 2700 out: 2701 mv88e6xxx_reg_unlock(chip); 2702 2703 return err; 2704 } 2705 2706 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2707 int port, u16 vid) 2708 { 2709 struct mv88e6xxx_vtu_entry vlan; 2710 int i, err; 2711 2712 if (!vid) 2713 return 0; 2714 2715 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2716 if (err) 2717 return err; 2718 2719 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2720 * tell switchdev that this VLAN is likely handled in software. 2721 */ 2722 if (!vlan.valid || 2723 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2724 return -EOPNOTSUPP; 2725 2726 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2727 2728 /* keep the VLAN unless all ports are excluded */ 2729 vlan.valid = false; 2730 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2731 if (vlan.member[i] != 2732 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2733 vlan.valid = true; 2734 break; 2735 } 2736 } 2737 2738 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2739 if (err) 2740 return err; 2741 2742 if (!vlan.valid) { 2743 err = mv88e6xxx_mst_put(chip, vlan.sid); 2744 if (err) 2745 return err; 2746 2747 /* Record FID freed in SW FID map */ 2748 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2749 } 2750 2751 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2752 } 2753 2754 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2755 const struct switchdev_obj_port_vlan *vlan) 2756 { 2757 struct mv88e6xxx_chip *chip = ds->priv; 2758 struct mv88e6xxx_port *p = &chip->ports[port]; 2759 int err = 0; 2760 u16 pvid; 2761 2762 if (!mv88e6xxx_max_vid(chip)) 2763 return -EOPNOTSUPP; 2764 2765 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2766 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2767 * switchdev workqueue to ensure that all FDB entries are deleted 2768 * before we remove the VLAN. 2769 */ 2770 dsa_flush_workqueue(); 2771 2772 mv88e6xxx_reg_lock(chip); 2773 2774 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2775 if (err) 2776 goto unlock; 2777 2778 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2779 if (err) 2780 goto unlock; 2781 2782 if (vlan->vid == pvid) { 2783 p->bridge_pvid.valid = false; 2784 2785 err = mv88e6xxx_port_commit_pvid(chip, port); 2786 if (err) 2787 goto unlock; 2788 } 2789 2790 unlock: 2791 mv88e6xxx_reg_unlock(chip); 2792 2793 return err; 2794 } 2795 2796 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2797 { 2798 struct mv88e6xxx_chip *chip = ds->priv; 2799 struct mv88e6xxx_vtu_entry vlan; 2800 int err; 2801 2802 mv88e6xxx_reg_lock(chip); 2803 2804 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2805 if (err) 2806 goto unlock; 2807 2808 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2809 2810 unlock: 2811 mv88e6xxx_reg_unlock(chip); 2812 2813 return err; 2814 } 2815 2816 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2817 struct dsa_bridge bridge, 2818 const struct switchdev_vlan_msti *msti) 2819 { 2820 struct mv88e6xxx_chip *chip = ds->priv; 2821 struct mv88e6xxx_vtu_entry vlan; 2822 u8 old_sid, new_sid; 2823 int err; 2824 2825 if (!mv88e6xxx_has_stu(chip)) 2826 return -EOPNOTSUPP; 2827 2828 mv88e6xxx_reg_lock(chip); 2829 2830 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2831 if (err) 2832 goto unlock; 2833 2834 if (!vlan.valid) { 2835 err = -EINVAL; 2836 goto unlock; 2837 } 2838 2839 old_sid = vlan.sid; 2840 2841 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2842 if (err) 2843 goto unlock; 2844 2845 if (new_sid != old_sid) { 2846 vlan.sid = new_sid; 2847 2848 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2849 if (err) { 2850 mv88e6xxx_mst_put(chip, new_sid); 2851 goto unlock; 2852 } 2853 } 2854 2855 err = mv88e6xxx_mst_put(chip, old_sid); 2856 2857 unlock: 2858 mv88e6xxx_reg_unlock(chip); 2859 return err; 2860 } 2861 2862 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2863 const unsigned char *addr, u16 vid, 2864 struct dsa_db db) 2865 { 2866 struct mv88e6xxx_chip *chip = ds->priv; 2867 int err; 2868 2869 mv88e6xxx_reg_lock(chip); 2870 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2871 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2872 if (err) 2873 goto out; 2874 2875 if (!mv88e6xxx_port_db_find(chip, addr, vid)) 2876 err = -ENOSPC; 2877 2878 out: 2879 mv88e6xxx_reg_unlock(chip); 2880 2881 return err; 2882 } 2883 2884 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2885 const unsigned char *addr, u16 vid, 2886 struct dsa_db db) 2887 { 2888 struct mv88e6xxx_chip *chip = ds->priv; 2889 int err; 2890 2891 mv88e6xxx_reg_lock(chip); 2892 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2893 mv88e6xxx_reg_unlock(chip); 2894 2895 return err; 2896 } 2897 2898 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2899 u16 fid, u16 vid, int port, 2900 dsa_fdb_dump_cb_t *cb, void *data) 2901 { 2902 struct mv88e6xxx_atu_entry addr; 2903 bool is_static; 2904 int err; 2905 2906 addr.state = 0; 2907 eth_broadcast_addr(addr.mac); 2908 2909 do { 2910 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2911 if (err) 2912 return err; 2913 2914 if (!addr.state) 2915 break; 2916 2917 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2918 continue; 2919 2920 if (!is_unicast_ether_addr(addr.mac)) 2921 continue; 2922 2923 is_static = (addr.state == 2924 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2925 err = cb(addr.mac, vid, is_static, data); 2926 if (err) 2927 return err; 2928 } while (!is_broadcast_ether_addr(addr.mac)); 2929 2930 return err; 2931 } 2932 2933 struct mv88e6xxx_port_db_dump_vlan_ctx { 2934 int port; 2935 dsa_fdb_dump_cb_t *cb; 2936 void *data; 2937 }; 2938 2939 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2940 const struct mv88e6xxx_vtu_entry *entry, 2941 void *_data) 2942 { 2943 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2944 2945 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2946 ctx->port, ctx->cb, ctx->data); 2947 } 2948 2949 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2950 dsa_fdb_dump_cb_t *cb, void *data) 2951 { 2952 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2953 .port = port, 2954 .cb = cb, 2955 .data = data, 2956 }; 2957 u16 fid; 2958 int err; 2959 2960 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2961 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2962 if (err) 2963 return err; 2964 2965 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2966 if (err) 2967 return err; 2968 2969 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2970 } 2971 2972 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2973 dsa_fdb_dump_cb_t *cb, void *data) 2974 { 2975 struct mv88e6xxx_chip *chip = ds->priv; 2976 int err; 2977 2978 mv88e6xxx_reg_lock(chip); 2979 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2980 mv88e6xxx_reg_unlock(chip); 2981 2982 return err; 2983 } 2984 2985 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2986 struct dsa_bridge bridge) 2987 { 2988 struct dsa_switch *ds = chip->ds; 2989 struct dsa_switch_tree *dst = ds->dst; 2990 struct dsa_port *dp; 2991 int err; 2992 2993 list_for_each_entry(dp, &dst->ports, list) { 2994 if (dsa_port_offloads_bridge(dp, &bridge)) { 2995 if (dp->ds == ds) { 2996 /* This is a local bridge group member, 2997 * remap its Port VLAN Map. 2998 */ 2999 err = mv88e6xxx_port_vlan_map(chip, dp->index); 3000 if (err) 3001 return err; 3002 } else { 3003 /* This is an external bridge group member, 3004 * remap its cross-chip Port VLAN Table entry. 3005 */ 3006 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3007 dp->index); 3008 if (err) 3009 return err; 3010 } 3011 } 3012 } 3013 3014 return 0; 3015 } 3016 3017 /* Treat the software bridge as a virtual single-port switch behind the 3018 * CPU and map in the PVT. First dst->last_switch elements are taken by 3019 * physical switches, so start from beyond that range. 3020 */ 3021 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3022 unsigned int bridge_num) 3023 { 3024 u8 dev = bridge_num + ds->dst->last_switch; 3025 struct mv88e6xxx_chip *chip = ds->priv; 3026 3027 return mv88e6xxx_pvt_map(chip, dev, 0); 3028 } 3029 3030 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3031 struct dsa_bridge bridge, 3032 bool *tx_fwd_offload, 3033 struct netlink_ext_ack *extack) 3034 { 3035 struct mv88e6xxx_chip *chip = ds->priv; 3036 int err; 3037 3038 mv88e6xxx_reg_lock(chip); 3039 3040 err = mv88e6xxx_bridge_map(chip, bridge); 3041 if (err) 3042 goto unlock; 3043 3044 err = mv88e6xxx_port_set_map_da(chip, port, true); 3045 if (err) 3046 goto unlock; 3047 3048 err = mv88e6xxx_port_commit_pvid(chip, port); 3049 if (err) 3050 goto unlock; 3051 3052 if (mv88e6xxx_has_pvt(chip)) { 3053 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3054 if (err) 3055 goto unlock; 3056 3057 *tx_fwd_offload = true; 3058 } 3059 3060 unlock: 3061 mv88e6xxx_reg_unlock(chip); 3062 3063 return err; 3064 } 3065 3066 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3067 struct dsa_bridge bridge) 3068 { 3069 struct mv88e6xxx_chip *chip = ds->priv; 3070 int err; 3071 3072 mv88e6xxx_reg_lock(chip); 3073 3074 if (bridge.tx_fwd_offload && 3075 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3076 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3077 3078 if (mv88e6xxx_bridge_map(chip, bridge) || 3079 mv88e6xxx_port_vlan_map(chip, port)) 3080 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3081 3082 err = mv88e6xxx_port_set_map_da(chip, port, false); 3083 if (err) 3084 dev_err(ds->dev, 3085 "port %d failed to restore map-DA: %pe\n", 3086 port, ERR_PTR(err)); 3087 3088 err = mv88e6xxx_port_commit_pvid(chip, port); 3089 if (err) 3090 dev_err(ds->dev, 3091 "port %d failed to restore standalone pvid: %pe\n", 3092 port, ERR_PTR(err)); 3093 3094 mv88e6xxx_reg_unlock(chip); 3095 } 3096 3097 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3098 int tree_index, int sw_index, 3099 int port, struct dsa_bridge bridge, 3100 struct netlink_ext_ack *extack) 3101 { 3102 struct mv88e6xxx_chip *chip = ds->priv; 3103 int err; 3104 3105 if (tree_index != ds->dst->index) 3106 return 0; 3107 3108 mv88e6xxx_reg_lock(chip); 3109 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3110 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3111 mv88e6xxx_reg_unlock(chip); 3112 3113 return err; 3114 } 3115 3116 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3117 int tree_index, int sw_index, 3118 int port, struct dsa_bridge bridge) 3119 { 3120 struct mv88e6xxx_chip *chip = ds->priv; 3121 3122 if (tree_index != ds->dst->index) 3123 return; 3124 3125 mv88e6xxx_reg_lock(chip); 3126 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3127 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3128 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3129 mv88e6xxx_reg_unlock(chip); 3130 } 3131 3132 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3133 { 3134 if (chip->info->ops->reset) 3135 return chip->info->ops->reset(chip); 3136 3137 return 0; 3138 } 3139 3140 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3141 { 3142 struct gpio_desc *gpiod = chip->reset; 3143 int err; 3144 3145 /* If there is a GPIO connected to the reset pin, toggle it */ 3146 if (gpiod) { 3147 /* If the switch has just been reset and not yet completed 3148 * loading EEPROM, the reset may interrupt the I2C transaction 3149 * mid-byte, causing the first EEPROM read after the reset 3150 * from the wrong location resulting in the switch booting 3151 * to wrong mode and inoperable. 3152 * For this reason, switch families with EEPROM support 3153 * generally wait for EEPROM loads to complete as their pre- 3154 * and post-reset handlers. 3155 */ 3156 if (chip->info->ops->hardware_reset_pre) { 3157 err = chip->info->ops->hardware_reset_pre(chip); 3158 if (err) 3159 dev_err(chip->dev, "pre-reset error: %d\n", err); 3160 } 3161 3162 gpiod_set_value_cansleep(gpiod, 1); 3163 usleep_range(10000, 20000); 3164 gpiod_set_value_cansleep(gpiod, 0); 3165 usleep_range(10000, 20000); 3166 3167 if (chip->info->ops->hardware_reset_post) { 3168 err = chip->info->ops->hardware_reset_post(chip); 3169 if (err) 3170 dev_err(chip->dev, "post-reset error: %d\n", err); 3171 } 3172 } 3173 } 3174 3175 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3176 { 3177 int i, err; 3178 3179 /* Set all ports to the Disabled state */ 3180 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3181 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3182 if (err) 3183 return err; 3184 } 3185 3186 /* Wait for transmit queues to drain, 3187 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3188 */ 3189 usleep_range(2000, 4000); 3190 3191 return 0; 3192 } 3193 3194 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3195 { 3196 int err; 3197 3198 err = mv88e6xxx_disable_ports(chip); 3199 if (err) 3200 return err; 3201 3202 mv88e6xxx_hardware_reset(chip); 3203 3204 return mv88e6xxx_software_reset(chip); 3205 } 3206 3207 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3208 enum mv88e6xxx_frame_mode frame, 3209 enum mv88e6xxx_egress_mode egress, u16 etype) 3210 { 3211 int err; 3212 3213 if (!chip->info->ops->port_set_frame_mode) 3214 return -EOPNOTSUPP; 3215 3216 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3217 if (err) 3218 return err; 3219 3220 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3221 if (err) 3222 return err; 3223 3224 if (chip->info->ops->port_set_ether_type) 3225 return chip->info->ops->port_set_ether_type(chip, port, etype); 3226 3227 return 0; 3228 } 3229 3230 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3231 { 3232 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3233 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3234 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3235 } 3236 3237 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3238 { 3239 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3240 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3241 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3242 } 3243 3244 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3245 { 3246 return mv88e6xxx_set_port_mode(chip, port, 3247 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3248 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3249 ETH_P_EDSA); 3250 } 3251 3252 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3253 { 3254 if (dsa_is_dsa_port(chip->ds, port)) 3255 return mv88e6xxx_set_port_mode_dsa(chip, port); 3256 3257 if (dsa_is_user_port(chip->ds, port)) 3258 return mv88e6xxx_set_port_mode_normal(chip, port); 3259 3260 /* Setup CPU port mode depending on its supported tag format */ 3261 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3262 return mv88e6xxx_set_port_mode_dsa(chip, port); 3263 3264 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3265 return mv88e6xxx_set_port_mode_edsa(chip, port); 3266 3267 return -EINVAL; 3268 } 3269 3270 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3271 { 3272 bool message = dsa_is_dsa_port(chip->ds, port); 3273 3274 return mv88e6xxx_port_set_message_port(chip, port, message); 3275 } 3276 3277 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3278 { 3279 int err; 3280 3281 if (chip->info->ops->port_set_ucast_flood) { 3282 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3283 if (err) 3284 return err; 3285 } 3286 if (chip->info->ops->port_set_mcast_flood) { 3287 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3288 if (err) 3289 return err; 3290 } 3291 3292 return 0; 3293 } 3294 3295 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3296 enum mv88e6xxx_egress_direction direction, 3297 int port) 3298 { 3299 int err; 3300 3301 if (!chip->info->ops->set_egress_port) 3302 return -EOPNOTSUPP; 3303 3304 err = chip->info->ops->set_egress_port(chip, direction, port); 3305 if (err) 3306 return err; 3307 3308 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3309 chip->ingress_dest_port = port; 3310 else 3311 chip->egress_dest_port = port; 3312 3313 return 0; 3314 } 3315 3316 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3317 { 3318 struct dsa_switch *ds = chip->ds; 3319 int upstream_port; 3320 int err; 3321 3322 upstream_port = dsa_upstream_port(ds, port); 3323 if (chip->info->ops->port_set_upstream_port) { 3324 err = chip->info->ops->port_set_upstream_port(chip, port, 3325 upstream_port); 3326 if (err) 3327 return err; 3328 } 3329 3330 if (port == upstream_port) { 3331 if (chip->info->ops->set_cpu_port) { 3332 err = chip->info->ops->set_cpu_port(chip, 3333 upstream_port); 3334 if (err) 3335 return err; 3336 } 3337 3338 err = mv88e6xxx_set_egress_port(chip, 3339 MV88E6XXX_EGRESS_DIR_INGRESS, 3340 upstream_port); 3341 if (err && err != -EOPNOTSUPP) 3342 return err; 3343 3344 err = mv88e6xxx_set_egress_port(chip, 3345 MV88E6XXX_EGRESS_DIR_EGRESS, 3346 upstream_port); 3347 if (err && err != -EOPNOTSUPP) 3348 return err; 3349 } 3350 3351 return 0; 3352 } 3353 3354 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3355 { 3356 struct device_node *phy_handle = NULL; 3357 struct fwnode_handle *ports_fwnode; 3358 struct fwnode_handle *port_fwnode; 3359 struct dsa_switch *ds = chip->ds; 3360 struct mv88e6xxx_port *p; 3361 struct dsa_port *dp; 3362 int tx_amp; 3363 int err; 3364 u16 reg; 3365 u32 val; 3366 3367 p = &chip->ports[port]; 3368 p->chip = chip; 3369 p->port = port; 3370 3371 /* Look up corresponding fwnode if any */ 3372 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3373 if (!ports_fwnode) 3374 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3375 if (ports_fwnode) { 3376 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3377 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3378 continue; 3379 if (val == port) { 3380 p->fwnode = port_fwnode; 3381 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3382 break; 3383 } 3384 } 3385 fwnode_handle_put(ports_fwnode); 3386 } else { 3387 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3388 } 3389 3390 if (chip->info->ops->port_setup_leds) { 3391 err = chip->info->ops->port_setup_leds(chip, port); 3392 if (err && err != -EOPNOTSUPP) 3393 return err; 3394 } 3395 3396 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3397 SPEED_UNFORCED, DUPLEX_UNFORCED, 3398 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3399 if (err) 3400 return err; 3401 3402 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3403 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3404 * tunneling, determine priority by looking at 802.1p and IP 3405 * priority fields (IP prio has precedence), and set STP state 3406 * to Forwarding. 3407 * 3408 * If this is the CPU link, use DSA or EDSA tagging depending 3409 * on which tagging mode was configured. 3410 * 3411 * If this is a link to another switch, use DSA tagging mode. 3412 * 3413 * If this is the upstream port for this switch, enable 3414 * forwarding of unknown unicasts and multicasts. 3415 */ 3416 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3417 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3418 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3419 * by a USER port to the CPU port to allow snooping. 3420 */ 3421 if (dsa_is_user_port(ds, port)) 3422 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3423 3424 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3425 if (err) 3426 return err; 3427 3428 err = mv88e6xxx_setup_port_mode(chip, port); 3429 if (err) 3430 return err; 3431 3432 err = mv88e6xxx_setup_egress_floods(chip, port); 3433 if (err) 3434 return err; 3435 3436 /* Port Control 2: don't force a good FCS, set the MTU size to 3437 * 10222 bytes, disable 802.1q tags checking, don't discard 3438 * tagged or untagged frames on this port, skip destination 3439 * address lookup on user ports, disable ARP mirroring and don't 3440 * send a copy of all transmitted/received frames on this port 3441 * to the CPU. 3442 */ 3443 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3444 if (err) 3445 return err; 3446 3447 err = mv88e6xxx_setup_upstream_port(chip, port); 3448 if (err) 3449 return err; 3450 3451 /* On chips that support it, set all downstream DSA ports' 3452 * VLAN policy to TRAP. In combination with loading 3453 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3454 * provides a better isolation barrier between standalone 3455 * ports, as the ATU is bypassed on any intermediate switches 3456 * between the incoming port and the CPU. 3457 */ 3458 if (dsa_is_downstream_port(ds, port) && 3459 chip->info->ops->port_set_policy) { 3460 err = chip->info->ops->port_set_policy(chip, port, 3461 MV88E6XXX_POLICY_MAPPING_VTU, 3462 MV88E6XXX_POLICY_ACTION_TRAP); 3463 if (err) 3464 return err; 3465 } 3466 3467 /* User ports start out in standalone mode and 802.1Q is 3468 * therefore disabled. On DSA ports, all valid VIDs are always 3469 * loaded in the VTU - therefore, enable 802.1Q in order to take 3470 * advantage of VLAN policy on chips that supports it. 3471 */ 3472 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3473 dsa_is_user_port(ds, port) ? 3474 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3475 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3476 if (err) 3477 return err; 3478 3479 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3480 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3481 * the first free FID. This will be used as the private PVID for 3482 * unbridged ports. Shared (DSA and CPU) ports must also be 3483 * members of this VID, in order to trap all frames assigned to 3484 * it to the CPU. 3485 */ 3486 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3487 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3488 false); 3489 if (err) 3490 return err; 3491 3492 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3493 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3494 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3495 * as the private PVID on ports under a VLAN-unaware bridge. 3496 * Shared (DSA and CPU) ports must also be members of it, to translate 3497 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3498 * relying on their port default FID. 3499 */ 3500 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3501 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3502 false); 3503 if (err) 3504 return err; 3505 3506 if (chip->info->ops->port_set_jumbo_size) { 3507 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3508 if (err) 3509 return err; 3510 } 3511 3512 /* Port Association Vector: disable automatic address learning 3513 * on all user ports since they start out in standalone 3514 * mode. When joining a bridge, learning will be configured to 3515 * match the bridge port settings. Enable learning on all 3516 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3517 * learning process. 3518 * 3519 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3520 * and RefreshLocked. I.e. setup standard automatic learning. 3521 */ 3522 if (dsa_is_user_port(ds, port)) 3523 reg = 0; 3524 else 3525 reg = 1 << port; 3526 3527 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3528 reg); 3529 if (err) 3530 return err; 3531 3532 /* Egress rate control 2: disable egress rate control. */ 3533 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3534 0x0000); 3535 if (err) 3536 return err; 3537 3538 if (chip->info->ops->port_pause_limit) { 3539 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3540 if (err) 3541 return err; 3542 } 3543 3544 if (chip->info->ops->port_disable_learn_limit) { 3545 err = chip->info->ops->port_disable_learn_limit(chip, port); 3546 if (err) 3547 return err; 3548 } 3549 3550 if (chip->info->ops->port_disable_pri_override) { 3551 err = chip->info->ops->port_disable_pri_override(chip, port); 3552 if (err) 3553 return err; 3554 } 3555 3556 if (chip->info->ops->port_tag_remap) { 3557 err = chip->info->ops->port_tag_remap(chip, port); 3558 if (err) 3559 return err; 3560 } 3561 3562 if (chip->info->ops->port_egress_rate_limiting) { 3563 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3564 if (err) 3565 return err; 3566 } 3567 3568 if (chip->info->ops->port_setup_message_port) { 3569 err = chip->info->ops->port_setup_message_port(chip, port); 3570 if (err) 3571 return err; 3572 } 3573 3574 if (chip->info->ops->serdes_set_tx_amplitude) { 3575 dp = dsa_to_port(ds, port); 3576 if (dp) 3577 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3578 3579 if (phy_handle && !of_property_read_u32(phy_handle, 3580 "tx-p2p-microvolt", 3581 &tx_amp)) 3582 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3583 port, tx_amp); 3584 if (phy_handle) { 3585 of_node_put(phy_handle); 3586 if (err) 3587 return err; 3588 } 3589 } 3590 3591 /* Port based VLAN map: give each port the same default address 3592 * database, and allow bidirectional communication between the 3593 * CPU and DSA port(s), and the other ports. 3594 */ 3595 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3596 if (err) 3597 return err; 3598 3599 err = mv88e6xxx_port_vlan_map(chip, port); 3600 if (err) 3601 return err; 3602 3603 /* Default VLAN ID and priority: don't set a default VLAN 3604 * ID, and set the default packet priority to zero. 3605 */ 3606 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3607 } 3608 3609 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3610 { 3611 struct mv88e6xxx_chip *chip = ds->priv; 3612 3613 if (chip->info->ops->port_set_jumbo_size) 3614 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3615 else if (chip->info->ops->set_max_frame_size) 3616 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3617 return ETH_DATA_LEN; 3618 } 3619 3620 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3621 { 3622 struct mv88e6xxx_chip *chip = ds->priv; 3623 int ret = 0; 3624 3625 /* For families where we don't know how to alter the MTU, 3626 * just accept any value up to ETH_DATA_LEN 3627 */ 3628 if (!chip->info->ops->port_set_jumbo_size && 3629 !chip->info->ops->set_max_frame_size) { 3630 if (new_mtu > ETH_DATA_LEN) 3631 return -EINVAL; 3632 3633 return 0; 3634 } 3635 3636 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3637 new_mtu += EDSA_HLEN; 3638 3639 mv88e6xxx_reg_lock(chip); 3640 if (chip->info->ops->port_set_jumbo_size) 3641 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3642 else if (chip->info->ops->set_max_frame_size && 3643 dsa_is_cpu_port(ds, port)) 3644 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3645 mv88e6xxx_reg_unlock(chip); 3646 3647 return ret; 3648 } 3649 3650 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3651 unsigned int ageing_time) 3652 { 3653 struct mv88e6xxx_chip *chip = ds->priv; 3654 int err; 3655 3656 mv88e6xxx_reg_lock(chip); 3657 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3658 mv88e6xxx_reg_unlock(chip); 3659 3660 return err; 3661 } 3662 3663 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3664 { 3665 int err; 3666 3667 /* Initialize the statistics unit */ 3668 if (chip->info->ops->stats_set_histogram) { 3669 err = chip->info->ops->stats_set_histogram(chip); 3670 if (err) 3671 return err; 3672 } 3673 3674 return mv88e6xxx_g1_stats_clear(chip); 3675 } 3676 3677 /* Check if the errata has already been applied. */ 3678 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3679 { 3680 int port; 3681 int err; 3682 u16 val; 3683 3684 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3685 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3686 if (err) { 3687 dev_err(chip->dev, 3688 "Error reading hidden register: %d\n", err); 3689 return false; 3690 } 3691 if (val != 0x01c0) 3692 return false; 3693 } 3694 3695 return true; 3696 } 3697 3698 /* The 6390 copper ports have an errata which require poking magic 3699 * values into undocumented hidden registers and then performing a 3700 * software reset. 3701 */ 3702 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3703 { 3704 int port; 3705 int err; 3706 3707 if (mv88e6390_setup_errata_applied(chip)) 3708 return 0; 3709 3710 /* Set the ports into blocking mode */ 3711 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3712 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3713 if (err) 3714 return err; 3715 } 3716 3717 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3718 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3719 if (err) 3720 return err; 3721 } 3722 3723 return mv88e6xxx_software_reset(chip); 3724 } 3725 3726 /* prod_id for switch families which do not have a PHY model number */ 3727 static const u16 family_prod_id_table[] = { 3728 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3729 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3730 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3731 }; 3732 3733 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3734 { 3735 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3736 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3737 u16 prod_id; 3738 u16 val; 3739 int err; 3740 3741 if (!chip->info->ops->phy_read) 3742 return -EOPNOTSUPP; 3743 3744 mv88e6xxx_reg_lock(chip); 3745 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3746 mv88e6xxx_reg_unlock(chip); 3747 3748 /* Some internal PHYs don't have a model number. */ 3749 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3750 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3751 prod_id = family_prod_id_table[chip->info->family]; 3752 if (prod_id) 3753 val |= prod_id >> 4; 3754 } 3755 3756 return err ? err : val; 3757 } 3758 3759 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3760 int reg) 3761 { 3762 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3763 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3764 u16 val; 3765 int err; 3766 3767 if (!chip->info->ops->phy_read_c45) 3768 return -ENODEV; 3769 3770 mv88e6xxx_reg_lock(chip); 3771 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3772 mv88e6xxx_reg_unlock(chip); 3773 3774 return err ? err : val; 3775 } 3776 3777 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3778 { 3779 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3780 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3781 int err; 3782 3783 if (!chip->info->ops->phy_write) 3784 return -EOPNOTSUPP; 3785 3786 mv88e6xxx_reg_lock(chip); 3787 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3788 mv88e6xxx_reg_unlock(chip); 3789 3790 return err; 3791 } 3792 3793 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3794 int reg, u16 val) 3795 { 3796 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3797 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3798 int err; 3799 3800 if (!chip->info->ops->phy_write_c45) 3801 return -EOPNOTSUPP; 3802 3803 mv88e6xxx_reg_lock(chip); 3804 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3805 mv88e6xxx_reg_unlock(chip); 3806 3807 return err; 3808 } 3809 3810 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3811 struct device_node *np, 3812 bool external) 3813 { 3814 static int index; 3815 struct mv88e6xxx_mdio_bus *mdio_bus; 3816 struct mii_bus *bus; 3817 int err; 3818 3819 if (external) { 3820 mv88e6xxx_reg_lock(chip); 3821 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3822 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3823 else 3824 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3825 mv88e6xxx_reg_unlock(chip); 3826 3827 if (err) 3828 return err; 3829 } 3830 3831 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3832 if (!bus) 3833 return -ENOMEM; 3834 3835 mdio_bus = bus->priv; 3836 mdio_bus->bus = bus; 3837 mdio_bus->chip = chip; 3838 INIT_LIST_HEAD(&mdio_bus->list); 3839 mdio_bus->external = external; 3840 3841 if (np) { 3842 bus->name = np->full_name; 3843 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3844 } else { 3845 bus->name = "mv88e6xxx SMI"; 3846 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3847 } 3848 3849 bus->read = mv88e6xxx_mdio_read; 3850 bus->write = mv88e6xxx_mdio_write; 3851 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3852 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3853 bus->parent = chip->dev; 3854 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3855 mv88e6xxx_num_ports(chip) - 1, 3856 chip->info->phy_base_addr); 3857 3858 if (!external) { 3859 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3860 if (err) 3861 goto out; 3862 } 3863 3864 err = of_mdiobus_register(bus, np); 3865 if (err) { 3866 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3867 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3868 goto out; 3869 } 3870 3871 if (external) 3872 list_add_tail(&mdio_bus->list, &chip->mdios); 3873 else 3874 list_add(&mdio_bus->list, &chip->mdios); 3875 3876 return 0; 3877 3878 out: 3879 mdiobus_free(bus); 3880 return err; 3881 } 3882 3883 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3884 3885 { 3886 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3887 struct mii_bus *bus; 3888 3889 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3890 bus = mdio_bus->bus; 3891 3892 if (!mdio_bus->external) 3893 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3894 3895 mdiobus_unregister(bus); 3896 mdiobus_free(bus); 3897 } 3898 } 3899 3900 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3901 { 3902 struct device_node *np = chip->dev->of_node; 3903 struct device_node *child; 3904 int err; 3905 3906 /* Always register one mdio bus for the internal/default mdio 3907 * bus. This maybe represented in the device tree, but is 3908 * optional. 3909 */ 3910 child = of_get_child_by_name(np, "mdio"); 3911 err = mv88e6xxx_mdio_register(chip, child, false); 3912 of_node_put(child); 3913 if (err) 3914 return err; 3915 3916 /* Walk the device tree, and see if there are any other nodes 3917 * which say they are compatible with the external mdio 3918 * bus. 3919 */ 3920 for_each_available_child_of_node(np, child) { 3921 if (of_device_is_compatible( 3922 child, "marvell,mv88e6xxx-mdio-external")) { 3923 err = mv88e6xxx_mdio_register(chip, child, true); 3924 if (err) { 3925 mv88e6xxx_mdios_unregister(chip); 3926 of_node_put(child); 3927 return err; 3928 } 3929 } 3930 } 3931 3932 return 0; 3933 } 3934 3935 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3936 { 3937 struct mv88e6xxx_chip *chip = ds->priv; 3938 3939 mv88e6xxx_teardown_devlink_params(ds); 3940 dsa_devlink_resources_unregister(ds); 3941 mv88e6xxx_teardown_devlink_regions_global(ds); 3942 mv88e6xxx_mdios_unregister(chip); 3943 } 3944 3945 static int mv88e6xxx_setup(struct dsa_switch *ds) 3946 { 3947 struct mv88e6xxx_chip *chip = ds->priv; 3948 u8 cmode; 3949 int err; 3950 int i; 3951 3952 err = mv88e6xxx_mdios_register(chip); 3953 if (err) 3954 return err; 3955 3956 chip->ds = ds; 3957 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3958 3959 /* Since virtual bridges are mapped in the PVT, the number we support 3960 * depends on the physical switch topology. We need to let DSA figure 3961 * that out and therefore we cannot set this at dsa_register_switch() 3962 * time. 3963 */ 3964 if (mv88e6xxx_has_pvt(chip)) 3965 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3966 ds->dst->last_switch - 1; 3967 3968 mv88e6xxx_reg_lock(chip); 3969 3970 if (chip->info->ops->setup_errata) { 3971 err = chip->info->ops->setup_errata(chip); 3972 if (err) 3973 goto unlock; 3974 } 3975 3976 /* Cache the cmode of each port. */ 3977 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3978 if (chip->info->ops->port_get_cmode) { 3979 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3980 if (err) 3981 goto unlock; 3982 3983 chip->ports[i].cmode = cmode; 3984 } 3985 } 3986 3987 err = mv88e6xxx_vtu_setup(chip); 3988 if (err) 3989 goto unlock; 3990 3991 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3992 * VTU, thereby also flushing the STU). 3993 */ 3994 err = mv88e6xxx_stu_setup(chip); 3995 if (err) 3996 goto unlock; 3997 3998 /* Setup Switch Port Registers */ 3999 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 4000 if (dsa_is_unused_port(ds, i)) 4001 continue; 4002 4003 /* Prevent the use of an invalid port. */ 4004 if (mv88e6xxx_is_invalid_port(chip, i)) { 4005 dev_err(chip->dev, "port %d is invalid\n", i); 4006 err = -EINVAL; 4007 goto unlock; 4008 } 4009 4010 err = mv88e6xxx_setup_port(chip, i); 4011 if (err) 4012 goto unlock; 4013 } 4014 4015 err = mv88e6xxx_irl_setup(chip); 4016 if (err) 4017 goto unlock; 4018 4019 err = mv88e6xxx_mac_setup(chip); 4020 if (err) 4021 goto unlock; 4022 4023 err = mv88e6xxx_phy_setup(chip); 4024 if (err) 4025 goto unlock; 4026 4027 err = mv88e6xxx_pvt_setup(chip); 4028 if (err) 4029 goto unlock; 4030 4031 err = mv88e6xxx_atu_setup(chip); 4032 if (err) 4033 goto unlock; 4034 4035 err = mv88e6xxx_broadcast_setup(chip, 0); 4036 if (err) 4037 goto unlock; 4038 4039 err = mv88e6xxx_pot_setup(chip); 4040 if (err) 4041 goto unlock; 4042 4043 err = mv88e6xxx_rmu_setup(chip); 4044 if (err) 4045 goto unlock; 4046 4047 err = mv88e6xxx_rsvd2cpu_setup(chip); 4048 if (err) 4049 goto unlock; 4050 4051 err = mv88e6xxx_trunk_setup(chip); 4052 if (err) 4053 goto unlock; 4054 4055 err = mv88e6xxx_devmap_setup(chip); 4056 if (err) 4057 goto unlock; 4058 4059 err = mv88e6xxx_pri_setup(chip); 4060 if (err) 4061 goto unlock; 4062 4063 /* Setup PTP Hardware Clock and timestamping */ 4064 if (chip->info->ptp_support) { 4065 err = mv88e6xxx_ptp_setup(chip); 4066 if (err) 4067 goto unlock; 4068 4069 err = mv88e6xxx_hwtstamp_setup(chip); 4070 if (err) 4071 goto unlock; 4072 } 4073 4074 err = mv88e6xxx_stats_setup(chip); 4075 if (err) 4076 goto unlock; 4077 4078 unlock: 4079 mv88e6xxx_reg_unlock(chip); 4080 4081 if (err) 4082 goto out_mdios; 4083 4084 /* Have to be called without holding the register lock, since 4085 * they take the devlink lock, and we later take the locks in 4086 * the reverse order when getting/setting parameters or 4087 * resource occupancy. 4088 */ 4089 err = mv88e6xxx_setup_devlink_resources(ds); 4090 if (err) 4091 goto out_mdios; 4092 4093 err = mv88e6xxx_setup_devlink_params(ds); 4094 if (err) 4095 goto out_resources; 4096 4097 err = mv88e6xxx_setup_devlink_regions_global(ds); 4098 if (err) 4099 goto out_params; 4100 4101 return 0; 4102 4103 out_params: 4104 mv88e6xxx_teardown_devlink_params(ds); 4105 out_resources: 4106 dsa_devlink_resources_unregister(ds); 4107 out_mdios: 4108 mv88e6xxx_mdios_unregister(chip); 4109 4110 return err; 4111 } 4112 4113 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4114 { 4115 struct mv88e6xxx_chip *chip = ds->priv; 4116 int err; 4117 4118 if (chip->info->ops->pcs_ops && 4119 chip->info->ops->pcs_ops->pcs_init) { 4120 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4121 if (err) 4122 return err; 4123 } 4124 4125 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4126 } 4127 4128 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4129 { 4130 struct mv88e6xxx_chip *chip = ds->priv; 4131 4132 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4133 4134 if (chip->info->ops->pcs_ops && 4135 chip->info->ops->pcs_ops->pcs_teardown) 4136 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4137 } 4138 4139 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4140 { 4141 struct mv88e6xxx_chip *chip = ds->priv; 4142 4143 return chip->eeprom_len; 4144 } 4145 4146 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4147 struct ethtool_eeprom *eeprom, u8 *data) 4148 { 4149 struct mv88e6xxx_chip *chip = ds->priv; 4150 int err; 4151 4152 if (!chip->info->ops->get_eeprom) 4153 return -EOPNOTSUPP; 4154 4155 mv88e6xxx_reg_lock(chip); 4156 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4157 mv88e6xxx_reg_unlock(chip); 4158 4159 if (err) 4160 return err; 4161 4162 eeprom->magic = 0xc3ec4951; 4163 4164 return 0; 4165 } 4166 4167 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4168 struct ethtool_eeprom *eeprom, u8 *data) 4169 { 4170 struct mv88e6xxx_chip *chip = ds->priv; 4171 int err; 4172 4173 if (!chip->info->ops->set_eeprom) 4174 return -EOPNOTSUPP; 4175 4176 if (eeprom->magic != 0xc3ec4951) 4177 return -EINVAL; 4178 4179 mv88e6xxx_reg_lock(chip); 4180 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4181 mv88e6xxx_reg_unlock(chip); 4182 4183 return err; 4184 } 4185 4186 static const struct mv88e6xxx_ops mv88e6085_ops = { 4187 /* MV88E6XXX_FAMILY_6097 */ 4188 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4189 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4190 .irl_init_all = mv88e6352_g2_irl_init_all, 4191 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4192 .phy_read = mv88e6185_phy_ppu_read, 4193 .phy_write = mv88e6185_phy_ppu_write, 4194 .port_set_link = mv88e6xxx_port_set_link, 4195 .port_sync_link = mv88e6xxx_port_sync_link, 4196 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4197 .port_tag_remap = mv88e6095_port_tag_remap, 4198 .port_set_policy = mv88e6352_port_set_policy, 4199 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4200 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4201 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4202 .port_set_ether_type = mv88e6351_port_set_ether_type, 4203 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4204 .port_pause_limit = mv88e6097_port_pause_limit, 4205 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4206 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4207 .port_get_cmode = mv88e6185_port_get_cmode, 4208 .port_setup_message_port = mv88e6xxx_setup_message_port, 4209 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4210 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4211 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4212 .stats_get_strings = mv88e6095_stats_get_strings, 4213 .stats_get_stat = mv88e6095_stats_get_stat, 4214 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4215 .set_egress_port = mv88e6095_g1_set_egress_port, 4216 .watchdog_ops = &mv88e6097_watchdog_ops, 4217 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4218 .pot_clear = mv88e6xxx_g2_pot_clear, 4219 .ppu_enable = mv88e6185_g1_ppu_enable, 4220 .ppu_disable = mv88e6185_g1_ppu_disable, 4221 .reset = mv88e6185_g1_reset, 4222 .rmu_disable = mv88e6085_g1_rmu_disable, 4223 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4224 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4225 .stu_getnext = mv88e6352_g1_stu_getnext, 4226 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4227 .phylink_get_caps = mv88e6185_phylink_get_caps, 4228 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4229 }; 4230 4231 static const struct mv88e6xxx_ops mv88e6095_ops = { 4232 /* MV88E6XXX_FAMILY_6095 */ 4233 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4234 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4235 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4236 .phy_read = mv88e6185_phy_ppu_read, 4237 .phy_write = mv88e6185_phy_ppu_write, 4238 .port_set_link = mv88e6xxx_port_set_link, 4239 .port_sync_link = mv88e6185_port_sync_link, 4240 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4241 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4242 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4243 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4244 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4245 .port_get_cmode = mv88e6185_port_get_cmode, 4246 .port_setup_message_port = mv88e6xxx_setup_message_port, 4247 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4248 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4249 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4250 .stats_get_strings = mv88e6095_stats_get_strings, 4251 .stats_get_stat = mv88e6095_stats_get_stat, 4252 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4253 .ppu_enable = mv88e6185_g1_ppu_enable, 4254 .ppu_disable = mv88e6185_g1_ppu_disable, 4255 .reset = mv88e6185_g1_reset, 4256 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4257 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4258 .phylink_get_caps = mv88e6095_phylink_get_caps, 4259 .pcs_ops = &mv88e6185_pcs_ops, 4260 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4261 }; 4262 4263 static const struct mv88e6xxx_ops mv88e6097_ops = { 4264 /* MV88E6XXX_FAMILY_6097 */ 4265 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4266 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4267 .irl_init_all = mv88e6352_g2_irl_init_all, 4268 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4269 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4270 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4271 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4272 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4273 .port_set_link = mv88e6xxx_port_set_link, 4274 .port_sync_link = mv88e6185_port_sync_link, 4275 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4276 .port_tag_remap = mv88e6095_port_tag_remap, 4277 .port_set_policy = mv88e6352_port_set_policy, 4278 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4279 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4280 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4281 .port_set_ether_type = mv88e6351_port_set_ether_type, 4282 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4283 .port_pause_limit = mv88e6097_port_pause_limit, 4284 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4285 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4286 .port_get_cmode = mv88e6185_port_get_cmode, 4287 .port_setup_message_port = mv88e6xxx_setup_message_port, 4288 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4289 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4290 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4291 .stats_get_strings = mv88e6095_stats_get_strings, 4292 .stats_get_stat = mv88e6095_stats_get_stat, 4293 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4294 .set_egress_port = mv88e6095_g1_set_egress_port, 4295 .watchdog_ops = &mv88e6097_watchdog_ops, 4296 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4297 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4298 .pot_clear = mv88e6xxx_g2_pot_clear, 4299 .reset = mv88e6352_g1_reset, 4300 .rmu_disable = mv88e6085_g1_rmu_disable, 4301 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4302 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4303 .phylink_get_caps = mv88e6095_phylink_get_caps, 4304 .pcs_ops = &mv88e6185_pcs_ops, 4305 .stu_getnext = mv88e6352_g1_stu_getnext, 4306 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4307 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4308 }; 4309 4310 static const struct mv88e6xxx_ops mv88e6123_ops = { 4311 /* MV88E6XXX_FAMILY_6165 */ 4312 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4313 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4314 .irl_init_all = mv88e6352_g2_irl_init_all, 4315 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4316 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4317 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4318 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4319 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4320 .port_set_link = mv88e6xxx_port_set_link, 4321 .port_sync_link = mv88e6xxx_port_sync_link, 4322 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4323 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4324 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4325 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4326 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4327 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4328 .port_get_cmode = mv88e6185_port_get_cmode, 4329 .port_setup_message_port = mv88e6xxx_setup_message_port, 4330 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4331 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4332 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4333 .stats_get_strings = mv88e6095_stats_get_strings, 4334 .stats_get_stat = mv88e6095_stats_get_stat, 4335 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4336 .set_egress_port = mv88e6095_g1_set_egress_port, 4337 .watchdog_ops = &mv88e6097_watchdog_ops, 4338 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4339 .pot_clear = mv88e6xxx_g2_pot_clear, 4340 .reset = mv88e6352_g1_reset, 4341 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4342 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4343 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4344 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4345 .stu_getnext = mv88e6352_g1_stu_getnext, 4346 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4347 .phylink_get_caps = mv88e6185_phylink_get_caps, 4348 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4349 }; 4350 4351 static const struct mv88e6xxx_ops mv88e6131_ops = { 4352 /* MV88E6XXX_FAMILY_6185 */ 4353 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4354 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4355 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4356 .phy_read = mv88e6185_phy_ppu_read, 4357 .phy_write = mv88e6185_phy_ppu_write, 4358 .port_set_link = mv88e6xxx_port_set_link, 4359 .port_sync_link = mv88e6xxx_port_sync_link, 4360 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4361 .port_tag_remap = mv88e6095_port_tag_remap, 4362 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4363 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4364 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4365 .port_set_ether_type = mv88e6351_port_set_ether_type, 4366 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4367 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4368 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4369 .port_pause_limit = mv88e6097_port_pause_limit, 4370 .port_set_pause = mv88e6185_port_set_pause, 4371 .port_get_cmode = mv88e6185_port_get_cmode, 4372 .port_setup_message_port = mv88e6xxx_setup_message_port, 4373 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4374 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4375 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4376 .stats_get_strings = mv88e6095_stats_get_strings, 4377 .stats_get_stat = mv88e6095_stats_get_stat, 4378 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4379 .set_egress_port = mv88e6095_g1_set_egress_port, 4380 .watchdog_ops = &mv88e6097_watchdog_ops, 4381 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4382 .ppu_enable = mv88e6185_g1_ppu_enable, 4383 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4384 .ppu_disable = mv88e6185_g1_ppu_disable, 4385 .reset = mv88e6185_g1_reset, 4386 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4387 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4388 .phylink_get_caps = mv88e6185_phylink_get_caps, 4389 }; 4390 4391 static const struct mv88e6xxx_ops mv88e6141_ops = { 4392 /* MV88E6XXX_FAMILY_6341 */ 4393 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4394 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4395 .irl_init_all = mv88e6352_g2_irl_init_all, 4396 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4397 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4399 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4400 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4401 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4402 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4403 .port_set_link = mv88e6xxx_port_set_link, 4404 .port_sync_link = mv88e6xxx_port_sync_link, 4405 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4406 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4407 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4408 .port_tag_remap = mv88e6095_port_tag_remap, 4409 .port_set_policy = mv88e6352_port_set_policy, 4410 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4411 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4412 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4413 .port_set_ether_type = mv88e6351_port_set_ether_type, 4414 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4415 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4416 .port_pause_limit = mv88e6097_port_pause_limit, 4417 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4418 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4419 .port_get_cmode = mv88e6352_port_get_cmode, 4420 .port_set_cmode = mv88e6341_port_set_cmode, 4421 .port_setup_message_port = mv88e6xxx_setup_message_port, 4422 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4423 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4424 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4425 .stats_get_strings = mv88e6320_stats_get_strings, 4426 .stats_get_stat = mv88e6390_stats_get_stat, 4427 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4428 .set_egress_port = mv88e6390_g1_set_egress_port, 4429 .watchdog_ops = &mv88e6390_watchdog_ops, 4430 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4431 .pot_clear = mv88e6xxx_g2_pot_clear, 4432 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4433 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4434 .reset = mv88e6352_g1_reset, 4435 .rmu_disable = mv88e6390_g1_rmu_disable, 4436 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4437 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4438 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4439 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4440 .stu_getnext = mv88e6352_g1_stu_getnext, 4441 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4442 .serdes_get_lane = mv88e6341_serdes_get_lane, 4443 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4444 .gpio_ops = &mv88e6352_gpio_ops, 4445 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4446 .serdes_get_strings = mv88e6390_serdes_get_strings, 4447 .serdes_get_stats = mv88e6390_serdes_get_stats, 4448 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4449 .serdes_get_regs = mv88e6390_serdes_get_regs, 4450 .phylink_get_caps = mv88e6341_phylink_get_caps, 4451 .pcs_ops = &mv88e6390_pcs_ops, 4452 }; 4453 4454 static const struct mv88e6xxx_ops mv88e6161_ops = { 4455 /* MV88E6XXX_FAMILY_6165 */ 4456 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4457 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4458 .irl_init_all = mv88e6352_g2_irl_init_all, 4459 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4460 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4461 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4462 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4463 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4464 .port_set_link = mv88e6xxx_port_set_link, 4465 .port_sync_link = mv88e6xxx_port_sync_link, 4466 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4467 .port_tag_remap = mv88e6095_port_tag_remap, 4468 .port_set_policy = mv88e6352_port_set_policy, 4469 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4470 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4471 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4472 .port_set_ether_type = mv88e6351_port_set_ether_type, 4473 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4474 .port_pause_limit = mv88e6097_port_pause_limit, 4475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4477 .port_get_cmode = mv88e6185_port_get_cmode, 4478 .port_setup_message_port = mv88e6xxx_setup_message_port, 4479 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4480 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4481 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4482 .stats_get_strings = mv88e6095_stats_get_strings, 4483 .stats_get_stat = mv88e6095_stats_get_stat, 4484 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4485 .set_egress_port = mv88e6095_g1_set_egress_port, 4486 .watchdog_ops = &mv88e6097_watchdog_ops, 4487 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4488 .pot_clear = mv88e6xxx_g2_pot_clear, 4489 .reset = mv88e6352_g1_reset, 4490 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4491 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4492 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4493 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4494 .stu_getnext = mv88e6352_g1_stu_getnext, 4495 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4496 .avb_ops = &mv88e6165_avb_ops, 4497 .ptp_ops = &mv88e6165_ptp_ops, 4498 .phylink_get_caps = mv88e6185_phylink_get_caps, 4499 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4500 }; 4501 4502 static const struct mv88e6xxx_ops mv88e6165_ops = { 4503 /* MV88E6XXX_FAMILY_6165 */ 4504 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4505 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4506 .irl_init_all = mv88e6352_g2_irl_init_all, 4507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4508 .phy_read = mv88e6165_phy_read, 4509 .phy_write = mv88e6165_phy_write, 4510 .port_set_link = mv88e6xxx_port_set_link, 4511 .port_sync_link = mv88e6xxx_port_sync_link, 4512 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4513 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4514 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4515 .port_get_cmode = mv88e6185_port_get_cmode, 4516 .port_setup_message_port = mv88e6xxx_setup_message_port, 4517 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4518 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4519 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4520 .stats_get_strings = mv88e6095_stats_get_strings, 4521 .stats_get_stat = mv88e6095_stats_get_stat, 4522 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4523 .set_egress_port = mv88e6095_g1_set_egress_port, 4524 .watchdog_ops = &mv88e6097_watchdog_ops, 4525 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4526 .pot_clear = mv88e6xxx_g2_pot_clear, 4527 .reset = mv88e6352_g1_reset, 4528 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4529 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4530 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4531 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4532 .stu_getnext = mv88e6352_g1_stu_getnext, 4533 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4534 .avb_ops = &mv88e6165_avb_ops, 4535 .ptp_ops = &mv88e6165_ptp_ops, 4536 .phylink_get_caps = mv88e6185_phylink_get_caps, 4537 }; 4538 4539 static const struct mv88e6xxx_ops mv88e6171_ops = { 4540 /* MV88E6XXX_FAMILY_6351 */ 4541 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4542 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4543 .irl_init_all = mv88e6352_g2_irl_init_all, 4544 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4545 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4546 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4547 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4548 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4549 .port_set_link = mv88e6xxx_port_set_link, 4550 .port_sync_link = mv88e6xxx_port_sync_link, 4551 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4552 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4553 .port_tag_remap = mv88e6095_port_tag_remap, 4554 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4555 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4556 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4557 .port_set_ether_type = mv88e6351_port_set_ether_type, 4558 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4559 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4560 .port_pause_limit = mv88e6097_port_pause_limit, 4561 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4562 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4563 .port_get_cmode = mv88e6352_port_get_cmode, 4564 .port_setup_message_port = mv88e6xxx_setup_message_port, 4565 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4566 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4567 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4568 .stats_get_strings = mv88e6095_stats_get_strings, 4569 .stats_get_stat = mv88e6095_stats_get_stat, 4570 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4571 .set_egress_port = mv88e6095_g1_set_egress_port, 4572 .watchdog_ops = &mv88e6097_watchdog_ops, 4573 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4574 .pot_clear = mv88e6xxx_g2_pot_clear, 4575 .reset = mv88e6352_g1_reset, 4576 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4577 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4578 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4579 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4580 .stu_getnext = mv88e6352_g1_stu_getnext, 4581 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4582 .phylink_get_caps = mv88e6351_phylink_get_caps, 4583 }; 4584 4585 static const struct mv88e6xxx_ops mv88e6172_ops = { 4586 /* MV88E6XXX_FAMILY_6352 */ 4587 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4588 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4589 .irl_init_all = mv88e6352_g2_irl_init_all, 4590 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4591 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4592 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4593 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4594 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4595 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4596 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4597 .port_set_link = mv88e6xxx_port_set_link, 4598 .port_sync_link = mv88e6xxx_port_sync_link, 4599 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4600 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4601 .port_tag_remap = mv88e6095_port_tag_remap, 4602 .port_set_policy = mv88e6352_port_set_policy, 4603 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4604 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4605 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4606 .port_set_ether_type = mv88e6351_port_set_ether_type, 4607 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4608 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4609 .port_pause_limit = mv88e6097_port_pause_limit, 4610 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4611 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4612 .port_get_cmode = mv88e6352_port_get_cmode, 4613 .port_setup_leds = mv88e6xxx_port_setup_leds, 4614 .port_setup_message_port = mv88e6xxx_setup_message_port, 4615 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4616 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4617 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4618 .stats_get_strings = mv88e6095_stats_get_strings, 4619 .stats_get_stat = mv88e6095_stats_get_stat, 4620 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4621 .set_egress_port = mv88e6095_g1_set_egress_port, 4622 .watchdog_ops = &mv88e6097_watchdog_ops, 4623 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4624 .pot_clear = mv88e6xxx_g2_pot_clear, 4625 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4626 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4627 .reset = mv88e6352_g1_reset, 4628 .rmu_disable = mv88e6352_g1_rmu_disable, 4629 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4630 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4631 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4632 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4633 .stu_getnext = mv88e6352_g1_stu_getnext, 4634 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4635 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4636 .serdes_get_regs = mv88e6352_serdes_get_regs, 4637 .gpio_ops = &mv88e6352_gpio_ops, 4638 .phylink_get_caps = mv88e6352_phylink_get_caps, 4639 .pcs_ops = &mv88e6352_pcs_ops, 4640 }; 4641 4642 static const struct mv88e6xxx_ops mv88e6175_ops = { 4643 /* MV88E6XXX_FAMILY_6351 */ 4644 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4645 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4646 .irl_init_all = mv88e6352_g2_irl_init_all, 4647 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4648 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4649 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4650 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4651 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4652 .port_set_link = mv88e6xxx_port_set_link, 4653 .port_sync_link = mv88e6xxx_port_sync_link, 4654 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4655 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4656 .port_tag_remap = mv88e6095_port_tag_remap, 4657 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4658 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4659 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4660 .port_set_ether_type = mv88e6351_port_set_ether_type, 4661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4663 .port_pause_limit = mv88e6097_port_pause_limit, 4664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4666 .port_get_cmode = mv88e6352_port_get_cmode, 4667 .port_setup_message_port = mv88e6xxx_setup_message_port, 4668 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4669 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4670 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4671 .stats_get_strings = mv88e6095_stats_get_strings, 4672 .stats_get_stat = mv88e6095_stats_get_stat, 4673 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4674 .set_egress_port = mv88e6095_g1_set_egress_port, 4675 .watchdog_ops = &mv88e6097_watchdog_ops, 4676 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4677 .pot_clear = mv88e6xxx_g2_pot_clear, 4678 .reset = mv88e6352_g1_reset, 4679 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4680 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4681 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4682 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4683 .stu_getnext = mv88e6352_g1_stu_getnext, 4684 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4685 .phylink_get_caps = mv88e6351_phylink_get_caps, 4686 }; 4687 4688 static const struct mv88e6xxx_ops mv88e6176_ops = { 4689 /* MV88E6XXX_FAMILY_6352 */ 4690 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4691 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4692 .irl_init_all = mv88e6352_g2_irl_init_all, 4693 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4694 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4695 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4696 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4697 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4698 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4699 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4700 .port_set_link = mv88e6xxx_port_set_link, 4701 .port_sync_link = mv88e6xxx_port_sync_link, 4702 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4703 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4704 .port_tag_remap = mv88e6095_port_tag_remap, 4705 .port_set_policy = mv88e6352_port_set_policy, 4706 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4707 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4708 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4709 .port_set_ether_type = mv88e6351_port_set_ether_type, 4710 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4711 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4712 .port_pause_limit = mv88e6097_port_pause_limit, 4713 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4714 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4715 .port_get_cmode = mv88e6352_port_get_cmode, 4716 .port_setup_leds = mv88e6xxx_port_setup_leds, 4717 .port_setup_message_port = mv88e6xxx_setup_message_port, 4718 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4719 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4720 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4721 .stats_get_strings = mv88e6095_stats_get_strings, 4722 .stats_get_stat = mv88e6095_stats_get_stat, 4723 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4724 .set_egress_port = mv88e6095_g1_set_egress_port, 4725 .watchdog_ops = &mv88e6097_watchdog_ops, 4726 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4727 .pot_clear = mv88e6xxx_g2_pot_clear, 4728 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4729 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4730 .reset = mv88e6352_g1_reset, 4731 .rmu_disable = mv88e6352_g1_rmu_disable, 4732 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4733 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4734 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4735 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4736 .stu_getnext = mv88e6352_g1_stu_getnext, 4737 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4738 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4739 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4740 .serdes_get_regs = mv88e6352_serdes_get_regs, 4741 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4742 .gpio_ops = &mv88e6352_gpio_ops, 4743 .phylink_get_caps = mv88e6352_phylink_get_caps, 4744 .pcs_ops = &mv88e6352_pcs_ops, 4745 }; 4746 4747 static const struct mv88e6xxx_ops mv88e6185_ops = { 4748 /* MV88E6XXX_FAMILY_6185 */ 4749 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4750 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4751 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4752 .phy_read = mv88e6185_phy_ppu_read, 4753 .phy_write = mv88e6185_phy_ppu_write, 4754 .port_set_link = mv88e6xxx_port_set_link, 4755 .port_sync_link = mv88e6185_port_sync_link, 4756 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4757 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4758 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4759 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4760 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4761 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4762 .port_set_pause = mv88e6185_port_set_pause, 4763 .port_get_cmode = mv88e6185_port_get_cmode, 4764 .port_setup_message_port = mv88e6xxx_setup_message_port, 4765 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4766 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4767 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4768 .stats_get_strings = mv88e6095_stats_get_strings, 4769 .stats_get_stat = mv88e6095_stats_get_stat, 4770 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4771 .set_egress_port = mv88e6095_g1_set_egress_port, 4772 .watchdog_ops = &mv88e6097_watchdog_ops, 4773 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4774 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4775 .ppu_enable = mv88e6185_g1_ppu_enable, 4776 .ppu_disable = mv88e6185_g1_ppu_disable, 4777 .reset = mv88e6185_g1_reset, 4778 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4779 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4780 .phylink_get_caps = mv88e6185_phylink_get_caps, 4781 .pcs_ops = &mv88e6185_pcs_ops, 4782 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4783 }; 4784 4785 static const struct mv88e6xxx_ops mv88e6190_ops = { 4786 /* MV88E6XXX_FAMILY_6390 */ 4787 .setup_errata = mv88e6390_setup_errata, 4788 .irl_init_all = mv88e6390_g2_irl_init_all, 4789 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4790 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4791 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4792 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4793 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4794 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4795 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4796 .port_set_link = mv88e6xxx_port_set_link, 4797 .port_sync_link = mv88e6xxx_port_sync_link, 4798 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4799 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4800 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4801 .port_tag_remap = mv88e6390_port_tag_remap, 4802 .port_set_policy = mv88e6352_port_set_policy, 4803 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4804 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4805 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4806 .port_set_ether_type = mv88e6351_port_set_ether_type, 4807 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4808 .port_pause_limit = mv88e6390_port_pause_limit, 4809 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4810 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4811 .port_get_cmode = mv88e6352_port_get_cmode, 4812 .port_set_cmode = mv88e6390_port_set_cmode, 4813 .port_setup_message_port = mv88e6xxx_setup_message_port, 4814 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4815 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4816 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4817 .stats_get_strings = mv88e6320_stats_get_strings, 4818 .stats_get_stat = mv88e6390_stats_get_stat, 4819 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4820 .set_egress_port = mv88e6390_g1_set_egress_port, 4821 .watchdog_ops = &mv88e6390_watchdog_ops, 4822 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4823 .pot_clear = mv88e6xxx_g2_pot_clear, 4824 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4825 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4826 .reset = mv88e6352_g1_reset, 4827 .rmu_disable = mv88e6390_g1_rmu_disable, 4828 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4829 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4830 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4831 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4832 .stu_getnext = mv88e6390_g1_stu_getnext, 4833 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4834 .serdes_get_lane = mv88e6390_serdes_get_lane, 4835 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4836 .serdes_get_strings = mv88e6390_serdes_get_strings, 4837 .serdes_get_stats = mv88e6390_serdes_get_stats, 4838 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4839 .serdes_get_regs = mv88e6390_serdes_get_regs, 4840 .gpio_ops = &mv88e6352_gpio_ops, 4841 .phylink_get_caps = mv88e6390_phylink_get_caps, 4842 .pcs_ops = &mv88e6390_pcs_ops, 4843 }; 4844 4845 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4846 /* MV88E6XXX_FAMILY_6390 */ 4847 .setup_errata = mv88e6390_setup_errata, 4848 .irl_init_all = mv88e6390_g2_irl_init_all, 4849 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4850 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4851 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4852 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4853 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4854 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4855 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4856 .port_set_link = mv88e6xxx_port_set_link, 4857 .port_sync_link = mv88e6xxx_port_sync_link, 4858 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4859 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4860 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4861 .port_tag_remap = mv88e6390_port_tag_remap, 4862 .port_set_policy = mv88e6352_port_set_policy, 4863 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4864 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4865 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4866 .port_set_ether_type = mv88e6351_port_set_ether_type, 4867 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4868 .port_pause_limit = mv88e6390_port_pause_limit, 4869 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4870 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4871 .port_get_cmode = mv88e6352_port_get_cmode, 4872 .port_set_cmode = mv88e6390x_port_set_cmode, 4873 .port_setup_message_port = mv88e6xxx_setup_message_port, 4874 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4875 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4876 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4877 .stats_get_strings = mv88e6320_stats_get_strings, 4878 .stats_get_stat = mv88e6390_stats_get_stat, 4879 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4880 .set_egress_port = mv88e6390_g1_set_egress_port, 4881 .watchdog_ops = &mv88e6390_watchdog_ops, 4882 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4883 .pot_clear = mv88e6xxx_g2_pot_clear, 4884 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4885 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4886 .reset = mv88e6352_g1_reset, 4887 .rmu_disable = mv88e6390_g1_rmu_disable, 4888 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4889 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4890 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4891 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4892 .stu_getnext = mv88e6390_g1_stu_getnext, 4893 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4894 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4895 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4896 .serdes_get_strings = mv88e6390_serdes_get_strings, 4897 .serdes_get_stats = mv88e6390_serdes_get_stats, 4898 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4899 .serdes_get_regs = mv88e6390_serdes_get_regs, 4900 .gpio_ops = &mv88e6352_gpio_ops, 4901 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4902 .pcs_ops = &mv88e6390_pcs_ops, 4903 }; 4904 4905 static const struct mv88e6xxx_ops mv88e6191_ops = { 4906 /* MV88E6XXX_FAMILY_6390 */ 4907 .setup_errata = mv88e6390_setup_errata, 4908 .irl_init_all = mv88e6390_g2_irl_init_all, 4909 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4910 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4911 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4912 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4913 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4914 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4915 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4916 .port_set_link = mv88e6xxx_port_set_link, 4917 .port_sync_link = mv88e6xxx_port_sync_link, 4918 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4919 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4920 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4921 .port_tag_remap = mv88e6390_port_tag_remap, 4922 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4923 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4924 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4925 .port_set_ether_type = mv88e6351_port_set_ether_type, 4926 .port_pause_limit = mv88e6390_port_pause_limit, 4927 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4928 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4929 .port_get_cmode = mv88e6352_port_get_cmode, 4930 .port_set_cmode = mv88e6390_port_set_cmode, 4931 .port_setup_message_port = mv88e6xxx_setup_message_port, 4932 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4933 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4934 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4935 .stats_get_strings = mv88e6320_stats_get_strings, 4936 .stats_get_stat = mv88e6390_stats_get_stat, 4937 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4938 .set_egress_port = mv88e6390_g1_set_egress_port, 4939 .watchdog_ops = &mv88e6390_watchdog_ops, 4940 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4941 .pot_clear = mv88e6xxx_g2_pot_clear, 4942 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4943 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4944 .reset = mv88e6352_g1_reset, 4945 .rmu_disable = mv88e6390_g1_rmu_disable, 4946 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4947 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4948 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4949 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4950 .stu_getnext = mv88e6390_g1_stu_getnext, 4951 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4952 .serdes_get_lane = mv88e6390_serdes_get_lane, 4953 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4954 .serdes_get_strings = mv88e6390_serdes_get_strings, 4955 .serdes_get_stats = mv88e6390_serdes_get_stats, 4956 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4957 .serdes_get_regs = mv88e6390_serdes_get_regs, 4958 .avb_ops = &mv88e6390_avb_ops, 4959 .ptp_ops = &mv88e6352_ptp_ops, 4960 .phylink_get_caps = mv88e6390_phylink_get_caps, 4961 .pcs_ops = &mv88e6390_pcs_ops, 4962 }; 4963 4964 static const struct mv88e6xxx_ops mv88e6240_ops = { 4965 /* MV88E6XXX_FAMILY_6352 */ 4966 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4967 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4968 .irl_init_all = mv88e6352_g2_irl_init_all, 4969 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4970 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4972 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4973 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4974 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4975 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4976 .port_set_link = mv88e6xxx_port_set_link, 4977 .port_sync_link = mv88e6xxx_port_sync_link, 4978 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4979 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4980 .port_tag_remap = mv88e6095_port_tag_remap, 4981 .port_set_policy = mv88e6352_port_set_policy, 4982 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4983 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4984 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4985 .port_set_ether_type = mv88e6351_port_set_ether_type, 4986 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4987 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4988 .port_pause_limit = mv88e6097_port_pause_limit, 4989 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4990 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4991 .port_get_cmode = mv88e6352_port_get_cmode, 4992 .port_setup_leds = mv88e6xxx_port_setup_leds, 4993 .port_setup_message_port = mv88e6xxx_setup_message_port, 4994 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4995 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4996 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4997 .stats_get_strings = mv88e6095_stats_get_strings, 4998 .stats_get_stat = mv88e6095_stats_get_stat, 4999 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5000 .set_egress_port = mv88e6095_g1_set_egress_port, 5001 .watchdog_ops = &mv88e6097_watchdog_ops, 5002 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5003 .pot_clear = mv88e6xxx_g2_pot_clear, 5004 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5005 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5006 .reset = mv88e6352_g1_reset, 5007 .rmu_disable = mv88e6352_g1_rmu_disable, 5008 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5009 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5010 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5011 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5012 .stu_getnext = mv88e6352_g1_stu_getnext, 5013 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5014 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5015 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5016 .serdes_get_regs = mv88e6352_serdes_get_regs, 5017 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5018 .gpio_ops = &mv88e6352_gpio_ops, 5019 .avb_ops = &mv88e6352_avb_ops, 5020 .ptp_ops = &mv88e6352_ptp_ops, 5021 .phylink_get_caps = mv88e6352_phylink_get_caps, 5022 .pcs_ops = &mv88e6352_pcs_ops, 5023 }; 5024 5025 static const struct mv88e6xxx_ops mv88e6250_ops = { 5026 /* MV88E6XXX_FAMILY_6250 */ 5027 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5028 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5029 .irl_init_all = mv88e6352_g2_irl_init_all, 5030 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5031 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5033 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5034 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5035 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5036 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5037 .port_set_link = mv88e6xxx_port_set_link, 5038 .port_sync_link = mv88e6xxx_port_sync_link, 5039 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5040 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5041 .port_tag_remap = mv88e6095_port_tag_remap, 5042 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5043 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5044 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5045 .port_set_ether_type = mv88e6351_port_set_ether_type, 5046 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5047 .port_pause_limit = mv88e6097_port_pause_limit, 5048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5049 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5050 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5051 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5052 .stats_get_strings = mv88e6250_stats_get_strings, 5053 .stats_get_stat = mv88e6250_stats_get_stat, 5054 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5055 .set_egress_port = mv88e6095_g1_set_egress_port, 5056 .watchdog_ops = &mv88e6250_watchdog_ops, 5057 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5058 .pot_clear = mv88e6xxx_g2_pot_clear, 5059 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5060 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5061 .reset = mv88e6250_g1_reset, 5062 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5063 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5064 .avb_ops = &mv88e6352_avb_ops, 5065 .ptp_ops = &mv88e6250_ptp_ops, 5066 .phylink_get_caps = mv88e6250_phylink_get_caps, 5067 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5068 }; 5069 5070 static const struct mv88e6xxx_ops mv88e6290_ops = { 5071 /* MV88E6XXX_FAMILY_6390 */ 5072 .setup_errata = mv88e6390_setup_errata, 5073 .irl_init_all = mv88e6390_g2_irl_init_all, 5074 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5075 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5076 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5077 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5078 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5079 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5080 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5081 .port_set_link = mv88e6xxx_port_set_link, 5082 .port_sync_link = mv88e6xxx_port_sync_link, 5083 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5084 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5085 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5086 .port_tag_remap = mv88e6390_port_tag_remap, 5087 .port_set_policy = mv88e6352_port_set_policy, 5088 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5089 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5090 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5091 .port_set_ether_type = mv88e6351_port_set_ether_type, 5092 .port_pause_limit = mv88e6390_port_pause_limit, 5093 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5094 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5095 .port_get_cmode = mv88e6352_port_get_cmode, 5096 .port_set_cmode = mv88e6390_port_set_cmode, 5097 .port_setup_message_port = mv88e6xxx_setup_message_port, 5098 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5099 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5100 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5101 .stats_get_strings = mv88e6320_stats_get_strings, 5102 .stats_get_stat = mv88e6390_stats_get_stat, 5103 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5104 .set_egress_port = mv88e6390_g1_set_egress_port, 5105 .watchdog_ops = &mv88e6390_watchdog_ops, 5106 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5107 .pot_clear = mv88e6xxx_g2_pot_clear, 5108 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5109 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5110 .reset = mv88e6352_g1_reset, 5111 .rmu_disable = mv88e6390_g1_rmu_disable, 5112 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5113 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5114 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5115 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5116 .stu_getnext = mv88e6390_g1_stu_getnext, 5117 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5118 .serdes_get_lane = mv88e6390_serdes_get_lane, 5119 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5120 .serdes_get_strings = mv88e6390_serdes_get_strings, 5121 .serdes_get_stats = mv88e6390_serdes_get_stats, 5122 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5123 .serdes_get_regs = mv88e6390_serdes_get_regs, 5124 .gpio_ops = &mv88e6352_gpio_ops, 5125 .avb_ops = &mv88e6390_avb_ops, 5126 .ptp_ops = &mv88e6390_ptp_ops, 5127 .phylink_get_caps = mv88e6390_phylink_get_caps, 5128 .pcs_ops = &mv88e6390_pcs_ops, 5129 }; 5130 5131 static const struct mv88e6xxx_ops mv88e6320_ops = { 5132 /* MV88E6XXX_FAMILY_6320 */ 5133 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5134 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5135 .irl_init_all = mv88e6352_g2_irl_init_all, 5136 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5137 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5138 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5139 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5140 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5141 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5142 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5143 .port_set_link = mv88e6xxx_port_set_link, 5144 .port_sync_link = mv88e6xxx_port_sync_link, 5145 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5146 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5147 .port_tag_remap = mv88e6095_port_tag_remap, 5148 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5149 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5150 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5151 .port_set_ether_type = mv88e6351_port_set_ether_type, 5152 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5153 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5154 .port_pause_limit = mv88e6097_port_pause_limit, 5155 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5156 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5157 .port_get_cmode = mv88e6352_port_get_cmode, 5158 .port_setup_message_port = mv88e6xxx_setup_message_port, 5159 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5160 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5161 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5162 .stats_get_strings = mv88e6320_stats_get_strings, 5163 .stats_get_stat = mv88e6320_stats_get_stat, 5164 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5165 .set_egress_port = mv88e6095_g1_set_egress_port, 5166 .watchdog_ops = &mv88e6390_watchdog_ops, 5167 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5168 .pot_clear = mv88e6xxx_g2_pot_clear, 5169 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5170 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5171 .reset = mv88e6352_g1_reset, 5172 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5173 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5174 .gpio_ops = &mv88e6352_gpio_ops, 5175 .avb_ops = &mv88e6352_avb_ops, 5176 .ptp_ops = &mv88e6352_ptp_ops, 5177 .phylink_get_caps = mv88e632x_phylink_get_caps, 5178 }; 5179 5180 static const struct mv88e6xxx_ops mv88e6321_ops = { 5181 /* MV88E6XXX_FAMILY_6320 */ 5182 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5183 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5184 .irl_init_all = mv88e6352_g2_irl_init_all, 5185 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5186 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5187 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5188 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5189 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5190 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5191 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5192 .port_set_link = mv88e6xxx_port_set_link, 5193 .port_sync_link = mv88e6xxx_port_sync_link, 5194 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5195 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5196 .port_tag_remap = mv88e6095_port_tag_remap, 5197 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5198 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5199 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5200 .port_set_ether_type = mv88e6351_port_set_ether_type, 5201 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5202 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5203 .port_pause_limit = mv88e6097_port_pause_limit, 5204 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5205 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5206 .port_get_cmode = mv88e6352_port_get_cmode, 5207 .port_setup_message_port = mv88e6xxx_setup_message_port, 5208 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5209 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5210 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5211 .stats_get_strings = mv88e6320_stats_get_strings, 5212 .stats_get_stat = mv88e6320_stats_get_stat, 5213 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5214 .set_egress_port = mv88e6095_g1_set_egress_port, 5215 .watchdog_ops = &mv88e6390_watchdog_ops, 5216 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5217 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5218 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5219 .reset = mv88e6352_g1_reset, 5220 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5221 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5222 .gpio_ops = &mv88e6352_gpio_ops, 5223 .avb_ops = &mv88e6352_avb_ops, 5224 .ptp_ops = &mv88e6352_ptp_ops, 5225 .phylink_get_caps = mv88e632x_phylink_get_caps, 5226 }; 5227 5228 static const struct mv88e6xxx_ops mv88e6341_ops = { 5229 /* MV88E6XXX_FAMILY_6341 */ 5230 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5231 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5232 .irl_init_all = mv88e6352_g2_irl_init_all, 5233 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5234 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5236 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5237 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5238 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5239 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5240 .port_set_link = mv88e6xxx_port_set_link, 5241 .port_sync_link = mv88e6xxx_port_sync_link, 5242 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5243 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5244 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5245 .port_tag_remap = mv88e6095_port_tag_remap, 5246 .port_set_policy = mv88e6352_port_set_policy, 5247 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5248 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5249 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5250 .port_set_ether_type = mv88e6351_port_set_ether_type, 5251 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5252 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5253 .port_pause_limit = mv88e6097_port_pause_limit, 5254 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5255 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5256 .port_get_cmode = mv88e6352_port_get_cmode, 5257 .port_set_cmode = mv88e6341_port_set_cmode, 5258 .port_setup_message_port = mv88e6xxx_setup_message_port, 5259 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5260 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5261 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5262 .stats_get_strings = mv88e6320_stats_get_strings, 5263 .stats_get_stat = mv88e6390_stats_get_stat, 5264 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5265 .set_egress_port = mv88e6390_g1_set_egress_port, 5266 .watchdog_ops = &mv88e6390_watchdog_ops, 5267 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5268 .pot_clear = mv88e6xxx_g2_pot_clear, 5269 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5270 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5271 .reset = mv88e6352_g1_reset, 5272 .rmu_disable = mv88e6390_g1_rmu_disable, 5273 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5274 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5275 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5276 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5277 .stu_getnext = mv88e6352_g1_stu_getnext, 5278 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5279 .serdes_get_lane = mv88e6341_serdes_get_lane, 5280 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5281 .gpio_ops = &mv88e6352_gpio_ops, 5282 .avb_ops = &mv88e6390_avb_ops, 5283 .ptp_ops = &mv88e6352_ptp_ops, 5284 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5285 .serdes_get_strings = mv88e6390_serdes_get_strings, 5286 .serdes_get_stats = mv88e6390_serdes_get_stats, 5287 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5288 .serdes_get_regs = mv88e6390_serdes_get_regs, 5289 .phylink_get_caps = mv88e6341_phylink_get_caps, 5290 .pcs_ops = &mv88e6390_pcs_ops, 5291 }; 5292 5293 static const struct mv88e6xxx_ops mv88e6350_ops = { 5294 /* MV88E6XXX_FAMILY_6351 */ 5295 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5296 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5297 .irl_init_all = mv88e6352_g2_irl_init_all, 5298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5299 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5300 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5301 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5302 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5303 .port_set_link = mv88e6xxx_port_set_link, 5304 .port_sync_link = mv88e6xxx_port_sync_link, 5305 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5306 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5307 .port_tag_remap = mv88e6095_port_tag_remap, 5308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5309 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5310 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5311 .port_set_ether_type = mv88e6351_port_set_ether_type, 5312 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5313 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5314 .port_pause_limit = mv88e6097_port_pause_limit, 5315 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5316 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5317 .port_get_cmode = mv88e6352_port_get_cmode, 5318 .port_setup_message_port = mv88e6xxx_setup_message_port, 5319 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5320 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5321 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5322 .stats_get_strings = mv88e6095_stats_get_strings, 5323 .stats_get_stat = mv88e6095_stats_get_stat, 5324 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5325 .set_egress_port = mv88e6095_g1_set_egress_port, 5326 .watchdog_ops = &mv88e6097_watchdog_ops, 5327 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5328 .pot_clear = mv88e6xxx_g2_pot_clear, 5329 .reset = mv88e6352_g1_reset, 5330 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5331 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5332 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5333 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5334 .stu_getnext = mv88e6352_g1_stu_getnext, 5335 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5336 .phylink_get_caps = mv88e6351_phylink_get_caps, 5337 }; 5338 5339 static const struct mv88e6xxx_ops mv88e6351_ops = { 5340 /* MV88E6XXX_FAMILY_6351 */ 5341 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5342 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5343 .irl_init_all = mv88e6352_g2_irl_init_all, 5344 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5345 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5346 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5347 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5348 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5349 .port_set_link = mv88e6xxx_port_set_link, 5350 .port_sync_link = mv88e6xxx_port_sync_link, 5351 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5352 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5353 .port_tag_remap = mv88e6095_port_tag_remap, 5354 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5355 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5356 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5357 .port_set_ether_type = mv88e6351_port_set_ether_type, 5358 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5360 .port_pause_limit = mv88e6097_port_pause_limit, 5361 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5362 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5363 .port_get_cmode = mv88e6352_port_get_cmode, 5364 .port_setup_message_port = mv88e6xxx_setup_message_port, 5365 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5366 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5367 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5368 .stats_get_strings = mv88e6095_stats_get_strings, 5369 .stats_get_stat = mv88e6095_stats_get_stat, 5370 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5371 .set_egress_port = mv88e6095_g1_set_egress_port, 5372 .watchdog_ops = &mv88e6097_watchdog_ops, 5373 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5374 .pot_clear = mv88e6xxx_g2_pot_clear, 5375 .reset = mv88e6352_g1_reset, 5376 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5377 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5378 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5379 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5380 .stu_getnext = mv88e6352_g1_stu_getnext, 5381 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5382 .avb_ops = &mv88e6352_avb_ops, 5383 .ptp_ops = &mv88e6352_ptp_ops, 5384 .phylink_get_caps = mv88e6351_phylink_get_caps, 5385 }; 5386 5387 static const struct mv88e6xxx_ops mv88e6352_ops = { 5388 /* MV88E6XXX_FAMILY_6352 */ 5389 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5390 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5391 .irl_init_all = mv88e6352_g2_irl_init_all, 5392 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5393 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5394 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5395 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5396 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5397 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5398 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5399 .port_set_link = mv88e6xxx_port_set_link, 5400 .port_sync_link = mv88e6xxx_port_sync_link, 5401 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5402 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5403 .port_tag_remap = mv88e6095_port_tag_remap, 5404 .port_set_policy = mv88e6352_port_set_policy, 5405 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5406 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5407 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5408 .port_set_ether_type = mv88e6351_port_set_ether_type, 5409 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5410 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5411 .port_pause_limit = mv88e6097_port_pause_limit, 5412 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5413 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5414 .port_get_cmode = mv88e6352_port_get_cmode, 5415 .port_setup_leds = mv88e6xxx_port_setup_leds, 5416 .port_setup_message_port = mv88e6xxx_setup_message_port, 5417 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5418 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5419 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5420 .stats_get_strings = mv88e6095_stats_get_strings, 5421 .stats_get_stat = mv88e6095_stats_get_stat, 5422 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5423 .set_egress_port = mv88e6095_g1_set_egress_port, 5424 .watchdog_ops = &mv88e6097_watchdog_ops, 5425 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5426 .pot_clear = mv88e6xxx_g2_pot_clear, 5427 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5428 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5429 .reset = mv88e6352_g1_reset, 5430 .rmu_disable = mv88e6352_g1_rmu_disable, 5431 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5432 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5433 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5434 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5435 .stu_getnext = mv88e6352_g1_stu_getnext, 5436 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5437 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5438 .gpio_ops = &mv88e6352_gpio_ops, 5439 .avb_ops = &mv88e6352_avb_ops, 5440 .ptp_ops = &mv88e6352_ptp_ops, 5441 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5442 .serdes_get_strings = mv88e6352_serdes_get_strings, 5443 .serdes_get_stats = mv88e6352_serdes_get_stats, 5444 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5445 .serdes_get_regs = mv88e6352_serdes_get_regs, 5446 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5447 .phylink_get_caps = mv88e6352_phylink_get_caps, 5448 .pcs_ops = &mv88e6352_pcs_ops, 5449 }; 5450 5451 static const struct mv88e6xxx_ops mv88e6390_ops = { 5452 /* MV88E6XXX_FAMILY_6390 */ 5453 .setup_errata = mv88e6390_setup_errata, 5454 .irl_init_all = mv88e6390_g2_irl_init_all, 5455 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5456 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5457 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5458 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5459 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5460 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5461 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5462 .port_set_link = mv88e6xxx_port_set_link, 5463 .port_sync_link = mv88e6xxx_port_sync_link, 5464 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5465 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5466 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5467 .port_tag_remap = mv88e6390_port_tag_remap, 5468 .port_set_policy = mv88e6352_port_set_policy, 5469 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5470 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5471 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5472 .port_set_ether_type = mv88e6351_port_set_ether_type, 5473 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5474 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5475 .port_pause_limit = mv88e6390_port_pause_limit, 5476 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5477 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5478 .port_get_cmode = mv88e6352_port_get_cmode, 5479 .port_set_cmode = mv88e6390_port_set_cmode, 5480 .port_setup_message_port = mv88e6xxx_setup_message_port, 5481 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5482 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5483 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5484 .stats_get_strings = mv88e6320_stats_get_strings, 5485 .stats_get_stat = mv88e6390_stats_get_stat, 5486 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5487 .set_egress_port = mv88e6390_g1_set_egress_port, 5488 .watchdog_ops = &mv88e6390_watchdog_ops, 5489 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5490 .pot_clear = mv88e6xxx_g2_pot_clear, 5491 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5492 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5493 .reset = mv88e6352_g1_reset, 5494 .rmu_disable = mv88e6390_g1_rmu_disable, 5495 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5496 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5497 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5498 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5499 .stu_getnext = mv88e6390_g1_stu_getnext, 5500 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5501 .serdes_get_lane = mv88e6390_serdes_get_lane, 5502 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5503 .gpio_ops = &mv88e6352_gpio_ops, 5504 .avb_ops = &mv88e6390_avb_ops, 5505 .ptp_ops = &mv88e6390_ptp_ops, 5506 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5507 .serdes_get_strings = mv88e6390_serdes_get_strings, 5508 .serdes_get_stats = mv88e6390_serdes_get_stats, 5509 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5510 .serdes_get_regs = mv88e6390_serdes_get_regs, 5511 .phylink_get_caps = mv88e6390_phylink_get_caps, 5512 .pcs_ops = &mv88e6390_pcs_ops, 5513 }; 5514 5515 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5516 /* MV88E6XXX_FAMILY_6390 */ 5517 .setup_errata = mv88e6390_setup_errata, 5518 .irl_init_all = mv88e6390_g2_irl_init_all, 5519 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5520 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5522 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5523 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5524 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5525 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5526 .port_set_link = mv88e6xxx_port_set_link, 5527 .port_sync_link = mv88e6xxx_port_sync_link, 5528 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5529 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5530 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5531 .port_tag_remap = mv88e6390_port_tag_remap, 5532 .port_set_policy = mv88e6352_port_set_policy, 5533 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5534 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5535 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5536 .port_set_ether_type = mv88e6351_port_set_ether_type, 5537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5539 .port_pause_limit = mv88e6390_port_pause_limit, 5540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5542 .port_get_cmode = mv88e6352_port_get_cmode, 5543 .port_set_cmode = mv88e6390x_port_set_cmode, 5544 .port_setup_message_port = mv88e6xxx_setup_message_port, 5545 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5546 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5547 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5548 .stats_get_strings = mv88e6320_stats_get_strings, 5549 .stats_get_stat = mv88e6390_stats_get_stat, 5550 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5551 .set_egress_port = mv88e6390_g1_set_egress_port, 5552 .watchdog_ops = &mv88e6390_watchdog_ops, 5553 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5554 .pot_clear = mv88e6xxx_g2_pot_clear, 5555 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5556 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5557 .reset = mv88e6352_g1_reset, 5558 .rmu_disable = mv88e6390_g1_rmu_disable, 5559 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5560 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5561 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5562 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5563 .stu_getnext = mv88e6390_g1_stu_getnext, 5564 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5565 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5566 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5567 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5568 .serdes_get_strings = mv88e6390_serdes_get_strings, 5569 .serdes_get_stats = mv88e6390_serdes_get_stats, 5570 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5571 .serdes_get_regs = mv88e6390_serdes_get_regs, 5572 .gpio_ops = &mv88e6352_gpio_ops, 5573 .avb_ops = &mv88e6390_avb_ops, 5574 .ptp_ops = &mv88e6390_ptp_ops, 5575 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5576 .pcs_ops = &mv88e6390_pcs_ops, 5577 }; 5578 5579 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5580 /* MV88E6XXX_FAMILY_6393 */ 5581 .irl_init_all = mv88e6390_g2_irl_init_all, 5582 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5583 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5584 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5585 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5586 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5587 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5588 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5589 .port_set_link = mv88e6xxx_port_set_link, 5590 .port_sync_link = mv88e6xxx_port_sync_link, 5591 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5592 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5593 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5594 .port_tag_remap = mv88e6390_port_tag_remap, 5595 .port_set_policy = mv88e6393x_port_set_policy, 5596 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5597 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5598 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5599 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5600 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5601 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5602 .port_pause_limit = mv88e6390_port_pause_limit, 5603 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5604 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5605 .port_get_cmode = mv88e6352_port_get_cmode, 5606 .port_set_cmode = mv88e6393x_port_set_cmode, 5607 .port_setup_message_port = mv88e6xxx_setup_message_port, 5608 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5609 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5610 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5611 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5612 .stats_get_strings = mv88e6320_stats_get_strings, 5613 .stats_get_stat = mv88e6390_stats_get_stat, 5614 /* .set_cpu_port is missing because this family does not support a global 5615 * CPU port, only per port CPU port which is set via 5616 * .port_set_upstream_port method. 5617 */ 5618 .set_egress_port = mv88e6393x_set_egress_port, 5619 .watchdog_ops = &mv88e6393x_watchdog_ops, 5620 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5621 .pot_clear = mv88e6xxx_g2_pot_clear, 5622 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5623 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5624 .reset = mv88e6352_g1_reset, 5625 .rmu_disable = mv88e6390_g1_rmu_disable, 5626 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5627 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5628 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5629 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5630 .stu_getnext = mv88e6390_g1_stu_getnext, 5631 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5632 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5633 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5634 /* TODO: serdes stats */ 5635 .gpio_ops = &mv88e6352_gpio_ops, 5636 .avb_ops = &mv88e6390_avb_ops, 5637 .ptp_ops = &mv88e6352_ptp_ops, 5638 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5639 .pcs_ops = &mv88e6393x_pcs_ops, 5640 }; 5641 5642 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5643 [MV88E6020] = { 5644 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5645 .family = MV88E6XXX_FAMILY_6250, 5646 .name = "Marvell 88E6020", 5647 .num_databases = 64, 5648 /* Ports 2-4 are not routed to pins 5649 * => usable ports 0, 1, 5, 6 5650 */ 5651 .num_ports = 7, 5652 .num_internal_phys = 2, 5653 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5654 .max_vid = 4095, 5655 .port_base_addr = 0x8, 5656 .phy_base_addr = 0x0, 5657 .global1_addr = 0xf, 5658 .global2_addr = 0x7, 5659 .age_time_coeff = 15000, 5660 .g1_irqs = 9, 5661 .g2_irqs = 5, 5662 .stats_type = STATS_TYPE_BANK0, 5663 .atu_move_port_mask = 0xf, 5664 .dual_chip = true, 5665 .ops = &mv88e6250_ops, 5666 }, 5667 5668 [MV88E6071] = { 5669 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5670 .family = MV88E6XXX_FAMILY_6250, 5671 .name = "Marvell 88E6071", 5672 .num_databases = 64, 5673 .num_ports = 7, 5674 .num_internal_phys = 5, 5675 .max_vid = 4095, 5676 .port_base_addr = 0x08, 5677 .phy_base_addr = 0x00, 5678 .global1_addr = 0x0f, 5679 .global2_addr = 0x07, 5680 .age_time_coeff = 15000, 5681 .g1_irqs = 9, 5682 .g2_irqs = 5, 5683 .stats_type = STATS_TYPE_BANK0, 5684 .atu_move_port_mask = 0xf, 5685 .dual_chip = true, 5686 .ops = &mv88e6250_ops, 5687 }, 5688 5689 [MV88E6085] = { 5690 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5691 .family = MV88E6XXX_FAMILY_6097, 5692 .name = "Marvell 88E6085", 5693 .num_databases = 4096, 5694 .num_macs = 8192, 5695 .num_ports = 10, 5696 .num_internal_phys = 5, 5697 .max_vid = 4095, 5698 .max_sid = 63, 5699 .port_base_addr = 0x10, 5700 .phy_base_addr = 0x0, 5701 .global1_addr = 0x1b, 5702 .global2_addr = 0x1c, 5703 .age_time_coeff = 15000, 5704 .g1_irqs = 8, 5705 .g2_irqs = 10, 5706 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5707 .atu_move_port_mask = 0xf, 5708 .pvt = true, 5709 .multi_chip = true, 5710 .ops = &mv88e6085_ops, 5711 }, 5712 5713 [MV88E6095] = { 5714 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5715 .family = MV88E6XXX_FAMILY_6095, 5716 .name = "Marvell 88E6095/88E6095F", 5717 .num_databases = 256, 5718 .num_macs = 8192, 5719 .num_ports = 11, 5720 .num_internal_phys = 0, 5721 .max_vid = 4095, 5722 .port_base_addr = 0x10, 5723 .phy_base_addr = 0x0, 5724 .global1_addr = 0x1b, 5725 .global2_addr = 0x1c, 5726 .age_time_coeff = 15000, 5727 .g1_irqs = 8, 5728 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5729 .atu_move_port_mask = 0xf, 5730 .multi_chip = true, 5731 .ops = &mv88e6095_ops, 5732 }, 5733 5734 [MV88E6097] = { 5735 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5736 .family = MV88E6XXX_FAMILY_6097, 5737 .name = "Marvell 88E6097/88E6097F", 5738 .num_databases = 4096, 5739 .num_macs = 8192, 5740 .num_ports = 11, 5741 .num_internal_phys = 8, 5742 .max_vid = 4095, 5743 .max_sid = 63, 5744 .port_base_addr = 0x10, 5745 .phy_base_addr = 0x0, 5746 .global1_addr = 0x1b, 5747 .global2_addr = 0x1c, 5748 .age_time_coeff = 15000, 5749 .g1_irqs = 8, 5750 .g2_irqs = 10, 5751 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5752 .atu_move_port_mask = 0xf, 5753 .pvt = true, 5754 .multi_chip = true, 5755 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5756 .ops = &mv88e6097_ops, 5757 }, 5758 5759 [MV88E6123] = { 5760 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5761 .family = MV88E6XXX_FAMILY_6165, 5762 .name = "Marvell 88E6123", 5763 .num_databases = 4096, 5764 .num_macs = 1024, 5765 .num_ports = 3, 5766 .num_internal_phys = 5, 5767 .max_vid = 4095, 5768 .max_sid = 63, 5769 .port_base_addr = 0x10, 5770 .phy_base_addr = 0x0, 5771 .global1_addr = 0x1b, 5772 .global2_addr = 0x1c, 5773 .age_time_coeff = 15000, 5774 .g1_irqs = 9, 5775 .g2_irqs = 10, 5776 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5777 .atu_move_port_mask = 0xf, 5778 .pvt = true, 5779 .multi_chip = true, 5780 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5781 .ops = &mv88e6123_ops, 5782 }, 5783 5784 [MV88E6131] = { 5785 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5786 .family = MV88E6XXX_FAMILY_6185, 5787 .name = "Marvell 88E6131", 5788 .num_databases = 256, 5789 .num_macs = 8192, 5790 .num_ports = 8, 5791 .num_internal_phys = 0, 5792 .max_vid = 4095, 5793 .port_base_addr = 0x10, 5794 .phy_base_addr = 0x0, 5795 .global1_addr = 0x1b, 5796 .global2_addr = 0x1c, 5797 .age_time_coeff = 15000, 5798 .g1_irqs = 9, 5799 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5800 .atu_move_port_mask = 0xf, 5801 .multi_chip = true, 5802 .ops = &mv88e6131_ops, 5803 }, 5804 5805 [MV88E6141] = { 5806 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5807 .family = MV88E6XXX_FAMILY_6341, 5808 .name = "Marvell 88E6141", 5809 .num_databases = 256, 5810 .num_macs = 2048, 5811 .num_ports = 6, 5812 .num_internal_phys = 5, 5813 .num_gpio = 11, 5814 .max_vid = 4095, 5815 .max_sid = 63, 5816 .port_base_addr = 0x10, 5817 .phy_base_addr = 0x10, 5818 .global1_addr = 0x1b, 5819 .global2_addr = 0x1c, 5820 .age_time_coeff = 3750, 5821 .atu_move_port_mask = 0x1f, 5822 .g1_irqs = 9, 5823 .g2_irqs = 10, 5824 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5825 .pvt = true, 5826 .multi_chip = true, 5827 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5828 .ops = &mv88e6141_ops, 5829 }, 5830 5831 [MV88E6161] = { 5832 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5833 .family = MV88E6XXX_FAMILY_6165, 5834 .name = "Marvell 88E6161", 5835 .num_databases = 4096, 5836 .num_macs = 1024, 5837 .num_ports = 6, 5838 .num_internal_phys = 5, 5839 .max_vid = 4095, 5840 .max_sid = 63, 5841 .port_base_addr = 0x10, 5842 .phy_base_addr = 0x0, 5843 .global1_addr = 0x1b, 5844 .global2_addr = 0x1c, 5845 .age_time_coeff = 15000, 5846 .g1_irqs = 9, 5847 .g2_irqs = 10, 5848 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5849 .atu_move_port_mask = 0xf, 5850 .pvt = true, 5851 .multi_chip = true, 5852 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5853 .ptp_support = true, 5854 .ops = &mv88e6161_ops, 5855 }, 5856 5857 [MV88E6165] = { 5858 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5859 .family = MV88E6XXX_FAMILY_6165, 5860 .name = "Marvell 88E6165", 5861 .num_databases = 4096, 5862 .num_macs = 8192, 5863 .num_ports = 6, 5864 .num_internal_phys = 0, 5865 .max_vid = 4095, 5866 .max_sid = 63, 5867 .port_base_addr = 0x10, 5868 .phy_base_addr = 0x0, 5869 .global1_addr = 0x1b, 5870 .global2_addr = 0x1c, 5871 .age_time_coeff = 15000, 5872 .g1_irqs = 9, 5873 .g2_irqs = 10, 5874 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5875 .atu_move_port_mask = 0xf, 5876 .pvt = true, 5877 .multi_chip = true, 5878 .ptp_support = true, 5879 .ops = &mv88e6165_ops, 5880 }, 5881 5882 [MV88E6171] = { 5883 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5884 .family = MV88E6XXX_FAMILY_6351, 5885 .name = "Marvell 88E6171", 5886 .num_databases = 4096, 5887 .num_macs = 8192, 5888 .num_ports = 7, 5889 .num_internal_phys = 5, 5890 .max_vid = 4095, 5891 .max_sid = 63, 5892 .port_base_addr = 0x10, 5893 .phy_base_addr = 0x0, 5894 .global1_addr = 0x1b, 5895 .global2_addr = 0x1c, 5896 .age_time_coeff = 15000, 5897 .g1_irqs = 9, 5898 .g2_irqs = 10, 5899 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5900 .atu_move_port_mask = 0xf, 5901 .pvt = true, 5902 .multi_chip = true, 5903 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5904 .ops = &mv88e6171_ops, 5905 }, 5906 5907 [MV88E6172] = { 5908 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5909 .family = MV88E6XXX_FAMILY_6352, 5910 .name = "Marvell 88E6172", 5911 .num_databases = 4096, 5912 .num_macs = 8192, 5913 .num_ports = 7, 5914 .num_internal_phys = 5, 5915 .num_gpio = 15, 5916 .max_vid = 4095, 5917 .max_sid = 63, 5918 .port_base_addr = 0x10, 5919 .phy_base_addr = 0x0, 5920 .global1_addr = 0x1b, 5921 .global2_addr = 0x1c, 5922 .age_time_coeff = 15000, 5923 .g1_irqs = 9, 5924 .g2_irqs = 10, 5925 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5926 .atu_move_port_mask = 0xf, 5927 .pvt = true, 5928 .multi_chip = true, 5929 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5930 .ops = &mv88e6172_ops, 5931 }, 5932 5933 [MV88E6175] = { 5934 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5935 .family = MV88E6XXX_FAMILY_6351, 5936 .name = "Marvell 88E6175", 5937 .num_databases = 4096, 5938 .num_macs = 8192, 5939 .num_ports = 7, 5940 .num_internal_phys = 5, 5941 .max_vid = 4095, 5942 .max_sid = 63, 5943 .port_base_addr = 0x10, 5944 .phy_base_addr = 0x0, 5945 .global1_addr = 0x1b, 5946 .global2_addr = 0x1c, 5947 .age_time_coeff = 15000, 5948 .g1_irqs = 9, 5949 .g2_irqs = 10, 5950 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5951 .atu_move_port_mask = 0xf, 5952 .pvt = true, 5953 .multi_chip = true, 5954 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5955 .ops = &mv88e6175_ops, 5956 }, 5957 5958 [MV88E6176] = { 5959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5960 .family = MV88E6XXX_FAMILY_6352, 5961 .name = "Marvell 88E6176", 5962 .num_databases = 4096, 5963 .num_macs = 8192, 5964 .num_ports = 7, 5965 .num_internal_phys = 5, 5966 .num_gpio = 15, 5967 .max_vid = 4095, 5968 .max_sid = 63, 5969 .port_base_addr = 0x10, 5970 .phy_base_addr = 0x0, 5971 .global1_addr = 0x1b, 5972 .global2_addr = 0x1c, 5973 .age_time_coeff = 15000, 5974 .g1_irqs = 9, 5975 .g2_irqs = 10, 5976 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5977 .atu_move_port_mask = 0xf, 5978 .pvt = true, 5979 .multi_chip = true, 5980 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5981 .ops = &mv88e6176_ops, 5982 }, 5983 5984 [MV88E6185] = { 5985 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5986 .family = MV88E6XXX_FAMILY_6185, 5987 .name = "Marvell 88E6185", 5988 .num_databases = 256, 5989 .num_macs = 8192, 5990 .num_ports = 10, 5991 .num_internal_phys = 0, 5992 .max_vid = 4095, 5993 .port_base_addr = 0x10, 5994 .phy_base_addr = 0x0, 5995 .global1_addr = 0x1b, 5996 .global2_addr = 0x1c, 5997 .age_time_coeff = 15000, 5998 .g1_irqs = 8, 5999 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6000 .atu_move_port_mask = 0xf, 6001 .multi_chip = true, 6002 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6003 .ops = &mv88e6185_ops, 6004 }, 6005 6006 [MV88E6190] = { 6007 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6008 .family = MV88E6XXX_FAMILY_6390, 6009 .name = "Marvell 88E6190", 6010 .num_databases = 4096, 6011 .num_macs = 16384, 6012 .num_ports = 11, /* 10 + Z80 */ 6013 .num_internal_phys = 9, 6014 .num_gpio = 16, 6015 .max_vid = 8191, 6016 .max_sid = 63, 6017 .port_base_addr = 0x0, 6018 .phy_base_addr = 0x0, 6019 .global1_addr = 0x1b, 6020 .global2_addr = 0x1c, 6021 .age_time_coeff = 3750, 6022 .g1_irqs = 9, 6023 .g2_irqs = 14, 6024 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6025 .pvt = true, 6026 .multi_chip = true, 6027 .atu_move_port_mask = 0x1f, 6028 .ops = &mv88e6190_ops, 6029 }, 6030 6031 [MV88E6190X] = { 6032 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6033 .family = MV88E6XXX_FAMILY_6390, 6034 .name = "Marvell 88E6190X", 6035 .num_databases = 4096, 6036 .num_macs = 16384, 6037 .num_ports = 11, /* 10 + Z80 */ 6038 .num_internal_phys = 9, 6039 .num_gpio = 16, 6040 .max_vid = 8191, 6041 .max_sid = 63, 6042 .port_base_addr = 0x0, 6043 .phy_base_addr = 0x0, 6044 .global1_addr = 0x1b, 6045 .global2_addr = 0x1c, 6046 .age_time_coeff = 3750, 6047 .g1_irqs = 9, 6048 .g2_irqs = 14, 6049 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6050 .atu_move_port_mask = 0x1f, 6051 .pvt = true, 6052 .multi_chip = true, 6053 .ops = &mv88e6190x_ops, 6054 }, 6055 6056 [MV88E6191] = { 6057 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6058 .family = MV88E6XXX_FAMILY_6390, 6059 .name = "Marvell 88E6191", 6060 .num_databases = 4096, 6061 .num_macs = 16384, 6062 .num_ports = 11, /* 10 + Z80 */ 6063 .num_internal_phys = 9, 6064 .max_vid = 8191, 6065 .max_sid = 63, 6066 .port_base_addr = 0x0, 6067 .phy_base_addr = 0x0, 6068 .global1_addr = 0x1b, 6069 .global2_addr = 0x1c, 6070 .age_time_coeff = 3750, 6071 .g1_irqs = 9, 6072 .g2_irqs = 14, 6073 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6074 .atu_move_port_mask = 0x1f, 6075 .pvt = true, 6076 .multi_chip = true, 6077 .ptp_support = true, 6078 .ops = &mv88e6191_ops, 6079 }, 6080 6081 [MV88E6191X] = { 6082 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6083 .family = MV88E6XXX_FAMILY_6393, 6084 .name = "Marvell 88E6191X", 6085 .num_databases = 4096, 6086 .num_ports = 11, /* 10 + Z80 */ 6087 .num_internal_phys = 8, 6088 .internal_phys_offset = 1, 6089 .max_vid = 8191, 6090 .max_sid = 63, 6091 .port_base_addr = 0x0, 6092 .phy_base_addr = 0x0, 6093 .global1_addr = 0x1b, 6094 .global2_addr = 0x1c, 6095 .age_time_coeff = 3750, 6096 .g1_irqs = 10, 6097 .g2_irqs = 14, 6098 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6099 .atu_move_port_mask = 0x1f, 6100 .pvt = true, 6101 .multi_chip = true, 6102 .ptp_support = true, 6103 .ops = &mv88e6393x_ops, 6104 }, 6105 6106 [MV88E6193X] = { 6107 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6108 .family = MV88E6XXX_FAMILY_6393, 6109 .name = "Marvell 88E6193X", 6110 .num_databases = 4096, 6111 .num_ports = 11, /* 10 + Z80 */ 6112 .num_internal_phys = 8, 6113 .internal_phys_offset = 1, 6114 .max_vid = 8191, 6115 .max_sid = 63, 6116 .port_base_addr = 0x0, 6117 .phy_base_addr = 0x0, 6118 .global1_addr = 0x1b, 6119 .global2_addr = 0x1c, 6120 .age_time_coeff = 3750, 6121 .g1_irqs = 10, 6122 .g2_irqs = 14, 6123 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6124 .atu_move_port_mask = 0x1f, 6125 .pvt = true, 6126 .multi_chip = true, 6127 .ptp_support = true, 6128 .ops = &mv88e6393x_ops, 6129 }, 6130 6131 [MV88E6220] = { 6132 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6133 .family = MV88E6XXX_FAMILY_6250, 6134 .name = "Marvell 88E6220", 6135 .num_databases = 64, 6136 6137 /* Ports 2-4 are not routed to pins 6138 * => usable ports 0, 1, 5, 6 6139 */ 6140 .num_ports = 7, 6141 .num_internal_phys = 2, 6142 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6143 .max_vid = 4095, 6144 .port_base_addr = 0x08, 6145 .phy_base_addr = 0x00, 6146 .global1_addr = 0x0f, 6147 .global2_addr = 0x07, 6148 .age_time_coeff = 15000, 6149 .g1_irqs = 9, 6150 .g2_irqs = 10, 6151 .stats_type = STATS_TYPE_BANK0, 6152 .atu_move_port_mask = 0xf, 6153 .dual_chip = true, 6154 .ptp_support = true, 6155 .ops = &mv88e6250_ops, 6156 }, 6157 6158 [MV88E6240] = { 6159 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6160 .family = MV88E6XXX_FAMILY_6352, 6161 .name = "Marvell 88E6240", 6162 .num_databases = 4096, 6163 .num_macs = 8192, 6164 .num_ports = 7, 6165 .num_internal_phys = 5, 6166 .num_gpio = 15, 6167 .max_vid = 4095, 6168 .max_sid = 63, 6169 .port_base_addr = 0x10, 6170 .phy_base_addr = 0x0, 6171 .global1_addr = 0x1b, 6172 .global2_addr = 0x1c, 6173 .age_time_coeff = 15000, 6174 .g1_irqs = 9, 6175 .g2_irqs = 10, 6176 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6177 .atu_move_port_mask = 0xf, 6178 .pvt = true, 6179 .multi_chip = true, 6180 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6181 .ptp_support = true, 6182 .ops = &mv88e6240_ops, 6183 }, 6184 6185 [MV88E6250] = { 6186 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6187 .family = MV88E6XXX_FAMILY_6250, 6188 .name = "Marvell 88E6250", 6189 .num_databases = 64, 6190 .num_ports = 7, 6191 .num_internal_phys = 5, 6192 .max_vid = 4095, 6193 .port_base_addr = 0x08, 6194 .phy_base_addr = 0x00, 6195 .global1_addr = 0x0f, 6196 .global2_addr = 0x07, 6197 .age_time_coeff = 15000, 6198 .g1_irqs = 9, 6199 .g2_irqs = 10, 6200 .stats_type = STATS_TYPE_BANK0, 6201 .atu_move_port_mask = 0xf, 6202 .dual_chip = true, 6203 .ptp_support = true, 6204 .ops = &mv88e6250_ops, 6205 }, 6206 6207 [MV88E6290] = { 6208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6209 .family = MV88E6XXX_FAMILY_6390, 6210 .name = "Marvell 88E6290", 6211 .num_databases = 4096, 6212 .num_ports = 11, /* 10 + Z80 */ 6213 .num_internal_phys = 9, 6214 .num_gpio = 16, 6215 .max_vid = 8191, 6216 .max_sid = 63, 6217 .port_base_addr = 0x0, 6218 .phy_base_addr = 0x0, 6219 .global1_addr = 0x1b, 6220 .global2_addr = 0x1c, 6221 .age_time_coeff = 3750, 6222 .g1_irqs = 9, 6223 .g2_irqs = 14, 6224 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6225 .atu_move_port_mask = 0x1f, 6226 .pvt = true, 6227 .multi_chip = true, 6228 .ptp_support = true, 6229 .ops = &mv88e6290_ops, 6230 }, 6231 6232 [MV88E6320] = { 6233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6234 .family = MV88E6XXX_FAMILY_6320, 6235 .name = "Marvell 88E6320", 6236 .num_databases = 4096, 6237 .num_macs = 8192, 6238 .num_ports = 7, 6239 .num_internal_phys = 5, 6240 .num_gpio = 15, 6241 .max_vid = 4095, 6242 .port_base_addr = 0x10, 6243 .phy_base_addr = 0x0, 6244 .global1_addr = 0x1b, 6245 .global2_addr = 0x1c, 6246 .age_time_coeff = 15000, 6247 .g1_irqs = 8, 6248 .g2_irqs = 10, 6249 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6250 .atu_move_port_mask = 0xf, 6251 .pvt = true, 6252 .multi_chip = true, 6253 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6254 .ptp_support = true, 6255 .ops = &mv88e6320_ops, 6256 }, 6257 6258 [MV88E6321] = { 6259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6260 .family = MV88E6XXX_FAMILY_6320, 6261 .name = "Marvell 88E6321", 6262 .num_databases = 4096, 6263 .num_macs = 8192, 6264 .num_ports = 7, 6265 .num_internal_phys = 5, 6266 .num_gpio = 15, 6267 .max_vid = 4095, 6268 .port_base_addr = 0x10, 6269 .phy_base_addr = 0x0, 6270 .global1_addr = 0x1b, 6271 .global2_addr = 0x1c, 6272 .age_time_coeff = 15000, 6273 .g1_irqs = 8, 6274 .g2_irqs = 10, 6275 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6276 .atu_move_port_mask = 0xf, 6277 .multi_chip = true, 6278 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6279 .ptp_support = true, 6280 .ops = &mv88e6321_ops, 6281 }, 6282 6283 [MV88E6341] = { 6284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6285 .family = MV88E6XXX_FAMILY_6341, 6286 .name = "Marvell 88E6341", 6287 .num_databases = 256, 6288 .num_macs = 2048, 6289 .num_internal_phys = 5, 6290 .num_ports = 6, 6291 .num_gpio = 11, 6292 .max_vid = 4095, 6293 .max_sid = 63, 6294 .port_base_addr = 0x10, 6295 .phy_base_addr = 0x10, 6296 .global1_addr = 0x1b, 6297 .global2_addr = 0x1c, 6298 .age_time_coeff = 3750, 6299 .atu_move_port_mask = 0x1f, 6300 .g1_irqs = 9, 6301 .g2_irqs = 10, 6302 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6303 .pvt = true, 6304 .multi_chip = true, 6305 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6306 .ptp_support = true, 6307 .ops = &mv88e6341_ops, 6308 }, 6309 6310 [MV88E6350] = { 6311 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6312 .family = MV88E6XXX_FAMILY_6351, 6313 .name = "Marvell 88E6350", 6314 .num_databases = 4096, 6315 .num_macs = 8192, 6316 .num_ports = 7, 6317 .num_internal_phys = 5, 6318 .max_vid = 4095, 6319 .max_sid = 63, 6320 .port_base_addr = 0x10, 6321 .phy_base_addr = 0x0, 6322 .global1_addr = 0x1b, 6323 .global2_addr = 0x1c, 6324 .age_time_coeff = 15000, 6325 .g1_irqs = 9, 6326 .g2_irqs = 10, 6327 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6328 .atu_move_port_mask = 0xf, 6329 .pvt = true, 6330 .multi_chip = true, 6331 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6332 .ops = &mv88e6350_ops, 6333 }, 6334 6335 [MV88E6351] = { 6336 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6337 .family = MV88E6XXX_FAMILY_6351, 6338 .name = "Marvell 88E6351", 6339 .num_databases = 4096, 6340 .num_macs = 8192, 6341 .num_ports = 7, 6342 .num_internal_phys = 5, 6343 .max_vid = 4095, 6344 .max_sid = 63, 6345 .port_base_addr = 0x10, 6346 .phy_base_addr = 0x0, 6347 .global1_addr = 0x1b, 6348 .global2_addr = 0x1c, 6349 .age_time_coeff = 15000, 6350 .g1_irqs = 9, 6351 .g2_irqs = 10, 6352 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6353 .atu_move_port_mask = 0xf, 6354 .pvt = true, 6355 .multi_chip = true, 6356 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6357 .ops = &mv88e6351_ops, 6358 }, 6359 6360 [MV88E6352] = { 6361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6362 .family = MV88E6XXX_FAMILY_6352, 6363 .name = "Marvell 88E6352", 6364 .num_databases = 4096, 6365 .num_macs = 8192, 6366 .num_ports = 7, 6367 .num_internal_phys = 5, 6368 .num_gpio = 15, 6369 .max_vid = 4095, 6370 .max_sid = 63, 6371 .port_base_addr = 0x10, 6372 .phy_base_addr = 0x0, 6373 .global1_addr = 0x1b, 6374 .global2_addr = 0x1c, 6375 .age_time_coeff = 15000, 6376 .g1_irqs = 9, 6377 .g2_irqs = 10, 6378 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6379 .atu_move_port_mask = 0xf, 6380 .pvt = true, 6381 .multi_chip = true, 6382 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6383 .ptp_support = true, 6384 .ops = &mv88e6352_ops, 6385 }, 6386 [MV88E6361] = { 6387 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6388 .family = MV88E6XXX_FAMILY_6393, 6389 .name = "Marvell 88E6361", 6390 .num_databases = 4096, 6391 .num_macs = 16384, 6392 .num_ports = 11, 6393 /* Ports 1, 2 and 8 are not routed */ 6394 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6395 .num_internal_phys = 5, 6396 .internal_phys_offset = 3, 6397 .max_vid = 8191, 6398 .max_sid = 63, 6399 .port_base_addr = 0x0, 6400 .phy_base_addr = 0x0, 6401 .global1_addr = 0x1b, 6402 .global2_addr = 0x1c, 6403 .age_time_coeff = 3750, 6404 .g1_irqs = 10, 6405 .g2_irqs = 14, 6406 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6407 .atu_move_port_mask = 0x1f, 6408 .pvt = true, 6409 .multi_chip = true, 6410 .ptp_support = true, 6411 .ops = &mv88e6393x_ops, 6412 }, 6413 [MV88E6390] = { 6414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6415 .family = MV88E6XXX_FAMILY_6390, 6416 .name = "Marvell 88E6390", 6417 .num_databases = 4096, 6418 .num_macs = 16384, 6419 .num_ports = 11, /* 10 + Z80 */ 6420 .num_internal_phys = 9, 6421 .num_gpio = 16, 6422 .max_vid = 8191, 6423 .max_sid = 63, 6424 .port_base_addr = 0x0, 6425 .phy_base_addr = 0x0, 6426 .global1_addr = 0x1b, 6427 .global2_addr = 0x1c, 6428 .age_time_coeff = 3750, 6429 .g1_irqs = 9, 6430 .g2_irqs = 14, 6431 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6432 .atu_move_port_mask = 0x1f, 6433 .pvt = true, 6434 .multi_chip = true, 6435 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6436 .ptp_support = true, 6437 .ops = &mv88e6390_ops, 6438 }, 6439 [MV88E6390X] = { 6440 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6441 .family = MV88E6XXX_FAMILY_6390, 6442 .name = "Marvell 88E6390X", 6443 .num_databases = 4096, 6444 .num_macs = 16384, 6445 .num_ports = 11, /* 10 + Z80 */ 6446 .num_internal_phys = 9, 6447 .num_gpio = 16, 6448 .max_vid = 8191, 6449 .max_sid = 63, 6450 .port_base_addr = 0x0, 6451 .phy_base_addr = 0x0, 6452 .global1_addr = 0x1b, 6453 .global2_addr = 0x1c, 6454 .age_time_coeff = 3750, 6455 .g1_irqs = 9, 6456 .g2_irqs = 14, 6457 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6458 .atu_move_port_mask = 0x1f, 6459 .pvt = true, 6460 .multi_chip = true, 6461 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6462 .ptp_support = true, 6463 .ops = &mv88e6390x_ops, 6464 }, 6465 6466 [MV88E6393X] = { 6467 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6468 .family = MV88E6XXX_FAMILY_6393, 6469 .name = "Marvell 88E6393X", 6470 .num_databases = 4096, 6471 .num_ports = 11, /* 10 + Z80 */ 6472 .num_internal_phys = 8, 6473 .internal_phys_offset = 1, 6474 .max_vid = 8191, 6475 .max_sid = 63, 6476 .port_base_addr = 0x0, 6477 .phy_base_addr = 0x0, 6478 .global1_addr = 0x1b, 6479 .global2_addr = 0x1c, 6480 .age_time_coeff = 3750, 6481 .g1_irqs = 10, 6482 .g2_irqs = 14, 6483 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6484 .atu_move_port_mask = 0x1f, 6485 .pvt = true, 6486 .multi_chip = true, 6487 .ptp_support = true, 6488 .ops = &mv88e6393x_ops, 6489 }, 6490 }; 6491 6492 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6493 { 6494 int i; 6495 6496 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6497 if (mv88e6xxx_table[i].prod_num == prod_num) 6498 return &mv88e6xxx_table[i]; 6499 6500 return NULL; 6501 } 6502 6503 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6504 { 6505 const struct mv88e6xxx_info *info; 6506 unsigned int prod_num, rev; 6507 u16 id; 6508 int err; 6509 6510 mv88e6xxx_reg_lock(chip); 6511 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6512 mv88e6xxx_reg_unlock(chip); 6513 if (err) 6514 return err; 6515 6516 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6517 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6518 6519 info = mv88e6xxx_lookup_info(prod_num); 6520 if (!info) 6521 return -ENODEV; 6522 6523 /* Update the compatible info with the probed one */ 6524 chip->info = info; 6525 6526 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6527 chip->info->prod_num, chip->info->name, rev); 6528 6529 return 0; 6530 } 6531 6532 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6533 struct mdio_device *mdiodev) 6534 { 6535 int err; 6536 6537 /* dual_chip takes precedence over single/multi-chip modes */ 6538 if (chip->info->dual_chip) 6539 return -EINVAL; 6540 6541 /* If the mdio addr is 16 indicating the first port address of a switch 6542 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6543 * configured in single chip addressing mode. Setup the smi access as 6544 * single chip addressing mode and attempt to detect the model of the 6545 * switch, if this fails the device is not configured in single chip 6546 * addressing mode. 6547 */ 6548 if (mdiodev->addr != 16) 6549 return -EINVAL; 6550 6551 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6552 if (err) 6553 return err; 6554 6555 return mv88e6xxx_detect(chip); 6556 } 6557 6558 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6559 { 6560 struct mv88e6xxx_chip *chip; 6561 6562 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6563 if (!chip) 6564 return NULL; 6565 6566 chip->dev = dev; 6567 6568 mutex_init(&chip->reg_lock); 6569 INIT_LIST_HEAD(&chip->mdios); 6570 idr_init(&chip->policies); 6571 INIT_LIST_HEAD(&chip->msts); 6572 6573 return chip; 6574 } 6575 6576 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6577 int port, 6578 enum dsa_tag_protocol m) 6579 { 6580 struct mv88e6xxx_chip *chip = ds->priv; 6581 6582 return chip->tag_protocol; 6583 } 6584 6585 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6586 enum dsa_tag_protocol proto) 6587 { 6588 struct mv88e6xxx_chip *chip = ds->priv; 6589 enum dsa_tag_protocol old_protocol; 6590 struct dsa_port *cpu_dp; 6591 int err; 6592 6593 switch (proto) { 6594 case DSA_TAG_PROTO_EDSA: 6595 switch (chip->info->edsa_support) { 6596 case MV88E6XXX_EDSA_UNSUPPORTED: 6597 return -EPROTONOSUPPORT; 6598 case MV88E6XXX_EDSA_UNDOCUMENTED: 6599 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6600 fallthrough; 6601 case MV88E6XXX_EDSA_SUPPORTED: 6602 break; 6603 } 6604 break; 6605 case DSA_TAG_PROTO_DSA: 6606 break; 6607 default: 6608 return -EPROTONOSUPPORT; 6609 } 6610 6611 old_protocol = chip->tag_protocol; 6612 chip->tag_protocol = proto; 6613 6614 mv88e6xxx_reg_lock(chip); 6615 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6616 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6617 if (err) { 6618 mv88e6xxx_reg_unlock(chip); 6619 goto unwind; 6620 } 6621 } 6622 mv88e6xxx_reg_unlock(chip); 6623 6624 return 0; 6625 6626 unwind: 6627 chip->tag_protocol = old_protocol; 6628 6629 mv88e6xxx_reg_lock(chip); 6630 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6631 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6632 mv88e6xxx_reg_unlock(chip); 6633 6634 return err; 6635 } 6636 6637 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6638 const struct switchdev_obj_port_mdb *mdb, 6639 struct dsa_db db) 6640 { 6641 struct mv88e6xxx_chip *chip = ds->priv; 6642 int err; 6643 6644 mv88e6xxx_reg_lock(chip); 6645 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6646 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6647 if (err) 6648 goto out; 6649 6650 if (!mv88e6xxx_port_db_find(chip, mdb->addr, mdb->vid)) 6651 err = -ENOSPC; 6652 6653 out: 6654 mv88e6xxx_reg_unlock(chip); 6655 6656 return err; 6657 } 6658 6659 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6660 const struct switchdev_obj_port_mdb *mdb, 6661 struct dsa_db db) 6662 { 6663 struct mv88e6xxx_chip *chip = ds->priv; 6664 int err; 6665 6666 mv88e6xxx_reg_lock(chip); 6667 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6668 mv88e6xxx_reg_unlock(chip); 6669 6670 return err; 6671 } 6672 6673 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6674 struct dsa_mall_mirror_tc_entry *mirror, 6675 bool ingress, 6676 struct netlink_ext_ack *extack) 6677 { 6678 enum mv88e6xxx_egress_direction direction = ingress ? 6679 MV88E6XXX_EGRESS_DIR_INGRESS : 6680 MV88E6XXX_EGRESS_DIR_EGRESS; 6681 struct mv88e6xxx_chip *chip = ds->priv; 6682 bool other_mirrors = false; 6683 int i; 6684 int err; 6685 6686 mutex_lock(&chip->reg_lock); 6687 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6688 mirror->to_local_port) { 6689 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6690 other_mirrors |= ingress ? 6691 chip->ports[i].mirror_ingress : 6692 chip->ports[i].mirror_egress; 6693 6694 /* Can't change egress port when other mirror is active */ 6695 if (other_mirrors) { 6696 err = -EBUSY; 6697 goto out; 6698 } 6699 6700 err = mv88e6xxx_set_egress_port(chip, direction, 6701 mirror->to_local_port); 6702 if (err) 6703 goto out; 6704 } 6705 6706 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6707 out: 6708 mutex_unlock(&chip->reg_lock); 6709 6710 return err; 6711 } 6712 6713 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6714 struct dsa_mall_mirror_tc_entry *mirror) 6715 { 6716 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6717 MV88E6XXX_EGRESS_DIR_INGRESS : 6718 MV88E6XXX_EGRESS_DIR_EGRESS; 6719 struct mv88e6xxx_chip *chip = ds->priv; 6720 bool other_mirrors = false; 6721 int i; 6722 6723 mutex_lock(&chip->reg_lock); 6724 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6725 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6726 6727 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6728 other_mirrors |= mirror->ingress ? 6729 chip->ports[i].mirror_ingress : 6730 chip->ports[i].mirror_egress; 6731 6732 /* Reset egress port when no other mirror is active */ 6733 if (!other_mirrors) { 6734 if (mv88e6xxx_set_egress_port(chip, direction, 6735 dsa_upstream_port(ds, port))) 6736 dev_err(ds->dev, "failed to set egress port\n"); 6737 } 6738 6739 mutex_unlock(&chip->reg_lock); 6740 } 6741 6742 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6743 struct switchdev_brport_flags flags, 6744 struct netlink_ext_ack *extack) 6745 { 6746 struct mv88e6xxx_chip *chip = ds->priv; 6747 const struct mv88e6xxx_ops *ops; 6748 6749 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6750 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6751 return -EINVAL; 6752 6753 ops = chip->info->ops; 6754 6755 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6756 return -EINVAL; 6757 6758 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6759 return -EINVAL; 6760 6761 return 0; 6762 } 6763 6764 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6765 struct switchdev_brport_flags flags, 6766 struct netlink_ext_ack *extack) 6767 { 6768 struct mv88e6xxx_chip *chip = ds->priv; 6769 int err = 0; 6770 6771 mv88e6xxx_reg_lock(chip); 6772 6773 if (flags.mask & BR_LEARNING) { 6774 bool learning = !!(flags.val & BR_LEARNING); 6775 u16 pav = learning ? (1 << port) : 0; 6776 6777 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6778 if (err) 6779 goto out; 6780 } 6781 6782 if (flags.mask & BR_FLOOD) { 6783 bool unicast = !!(flags.val & BR_FLOOD); 6784 6785 err = chip->info->ops->port_set_ucast_flood(chip, port, 6786 unicast); 6787 if (err) 6788 goto out; 6789 } 6790 6791 if (flags.mask & BR_MCAST_FLOOD) { 6792 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6793 6794 err = chip->info->ops->port_set_mcast_flood(chip, port, 6795 multicast); 6796 if (err) 6797 goto out; 6798 } 6799 6800 if (flags.mask & BR_BCAST_FLOOD) { 6801 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6802 6803 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6804 if (err) 6805 goto out; 6806 } 6807 6808 if (flags.mask & BR_PORT_MAB) { 6809 bool mab = !!(flags.val & BR_PORT_MAB); 6810 6811 mv88e6xxx_port_set_mab(chip, port, mab); 6812 } 6813 6814 if (flags.mask & BR_PORT_LOCKED) { 6815 bool locked = !!(flags.val & BR_PORT_LOCKED); 6816 6817 err = mv88e6xxx_port_set_lock(chip, port, locked); 6818 if (err) 6819 goto out; 6820 } 6821 out: 6822 mv88e6xxx_reg_unlock(chip); 6823 6824 return err; 6825 } 6826 6827 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6828 struct dsa_lag lag, 6829 struct netdev_lag_upper_info *info, 6830 struct netlink_ext_ack *extack) 6831 { 6832 struct mv88e6xxx_chip *chip = ds->priv; 6833 struct dsa_port *dp; 6834 int members = 0; 6835 6836 if (!mv88e6xxx_has_lag(chip)) { 6837 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6838 return false; 6839 } 6840 6841 if (!lag.id) 6842 return false; 6843 6844 dsa_lag_foreach_port(dp, ds->dst, &lag) 6845 /* Includes the port joining the LAG */ 6846 members++; 6847 6848 if (members > 8) { 6849 NL_SET_ERR_MSG_MOD(extack, 6850 "Cannot offload more than 8 LAG ports"); 6851 return false; 6852 } 6853 6854 /* We could potentially relax this to include active 6855 * backup in the future. 6856 */ 6857 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6858 NL_SET_ERR_MSG_MOD(extack, 6859 "Can only offload LAG using hash TX type"); 6860 return false; 6861 } 6862 6863 /* Ideally we would also validate that the hash type matches 6864 * the hardware. Alas, this is always set to unknown on team 6865 * interfaces. 6866 */ 6867 return true; 6868 } 6869 6870 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6871 { 6872 struct mv88e6xxx_chip *chip = ds->priv; 6873 struct dsa_port *dp; 6874 u16 map = 0; 6875 int id; 6876 6877 /* DSA LAG IDs are one-based, hardware is zero-based */ 6878 id = lag.id - 1; 6879 6880 /* Build the map of all ports to distribute flows destined for 6881 * this LAG. This can be either a local user port, or a DSA 6882 * port if the LAG port is on a remote chip. 6883 */ 6884 dsa_lag_foreach_port(dp, ds->dst, &lag) 6885 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6886 6887 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6888 } 6889 6890 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6891 /* Row number corresponds to the number of active members in a 6892 * LAG. Each column states which of the eight hash buckets are 6893 * mapped to the column:th port in the LAG. 6894 * 6895 * Example: In a LAG with three active ports, the second port 6896 * ([2][1]) would be selected for traffic mapped to buckets 6897 * 3,4,5 (0x38). 6898 */ 6899 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6900 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6901 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6902 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6903 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6904 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6905 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6906 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6907 }; 6908 6909 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6910 int num_tx, int nth) 6911 { 6912 u8 active = 0; 6913 int i; 6914 6915 num_tx = num_tx <= 8 ? num_tx : 8; 6916 if (nth < num_tx) 6917 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6918 6919 for (i = 0; i < 8; i++) { 6920 if (BIT(i) & active) 6921 mask[i] |= BIT(port); 6922 } 6923 } 6924 6925 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6926 { 6927 struct mv88e6xxx_chip *chip = ds->priv; 6928 unsigned int id, num_tx; 6929 struct dsa_port *dp; 6930 struct dsa_lag *lag; 6931 int i, err, nth; 6932 u16 mask[8]; 6933 u16 ivec; 6934 6935 /* Assume no port is a member of any LAG. */ 6936 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6937 6938 /* Disable all masks for ports that _are_ members of a LAG. */ 6939 dsa_switch_for_each_port(dp, ds) { 6940 if (!dp->lag) 6941 continue; 6942 6943 ivec &= ~BIT(dp->index); 6944 } 6945 6946 for (i = 0; i < 8; i++) 6947 mask[i] = ivec; 6948 6949 /* Enable the correct subset of masks for all LAG ports that 6950 * are in the Tx set. 6951 */ 6952 dsa_lags_foreach_id(id, ds->dst) { 6953 lag = dsa_lag_by_id(ds->dst, id); 6954 if (!lag) 6955 continue; 6956 6957 num_tx = 0; 6958 dsa_lag_foreach_port(dp, ds->dst, lag) { 6959 if (dp->lag_tx_enabled) 6960 num_tx++; 6961 } 6962 6963 if (!num_tx) 6964 continue; 6965 6966 nth = 0; 6967 dsa_lag_foreach_port(dp, ds->dst, lag) { 6968 if (!dp->lag_tx_enabled) 6969 continue; 6970 6971 if (dp->ds == ds) 6972 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6973 num_tx, nth); 6974 6975 nth++; 6976 } 6977 } 6978 6979 for (i = 0; i < 8; i++) { 6980 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6981 if (err) 6982 return err; 6983 } 6984 6985 return 0; 6986 } 6987 6988 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6989 struct dsa_lag lag) 6990 { 6991 int err; 6992 6993 err = mv88e6xxx_lag_sync_masks(ds); 6994 6995 if (!err) 6996 err = mv88e6xxx_lag_sync_map(ds, lag); 6997 6998 return err; 6999 } 7000 7001 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 7002 { 7003 struct mv88e6xxx_chip *chip = ds->priv; 7004 int err; 7005 7006 mv88e6xxx_reg_lock(chip); 7007 err = mv88e6xxx_lag_sync_masks(ds); 7008 mv88e6xxx_reg_unlock(chip); 7009 return err; 7010 } 7011 7012 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 7013 struct dsa_lag lag, 7014 struct netdev_lag_upper_info *info, 7015 struct netlink_ext_ack *extack) 7016 { 7017 struct mv88e6xxx_chip *chip = ds->priv; 7018 int err, id; 7019 7020 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7021 return -EOPNOTSUPP; 7022 7023 /* DSA LAG IDs are one-based */ 7024 id = lag.id - 1; 7025 7026 mv88e6xxx_reg_lock(chip); 7027 7028 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7029 if (err) 7030 goto err_unlock; 7031 7032 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7033 if (err) 7034 goto err_clear_trunk; 7035 7036 mv88e6xxx_reg_unlock(chip); 7037 return 0; 7038 7039 err_clear_trunk: 7040 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7041 err_unlock: 7042 mv88e6xxx_reg_unlock(chip); 7043 return err; 7044 } 7045 7046 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7047 struct dsa_lag lag) 7048 { 7049 struct mv88e6xxx_chip *chip = ds->priv; 7050 int err_sync, err_trunk; 7051 7052 mv88e6xxx_reg_lock(chip); 7053 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7054 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7055 mv88e6xxx_reg_unlock(chip); 7056 return err_sync ? : err_trunk; 7057 } 7058 7059 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7060 int port) 7061 { 7062 struct mv88e6xxx_chip *chip = ds->priv; 7063 int err; 7064 7065 mv88e6xxx_reg_lock(chip); 7066 err = mv88e6xxx_lag_sync_masks(ds); 7067 mv88e6xxx_reg_unlock(chip); 7068 return err; 7069 } 7070 7071 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7072 int port, struct dsa_lag lag, 7073 struct netdev_lag_upper_info *info, 7074 struct netlink_ext_ack *extack) 7075 { 7076 struct mv88e6xxx_chip *chip = ds->priv; 7077 int err; 7078 7079 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7080 return -EOPNOTSUPP; 7081 7082 mv88e6xxx_reg_lock(chip); 7083 7084 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7085 if (err) 7086 goto unlock; 7087 7088 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7089 7090 unlock: 7091 mv88e6xxx_reg_unlock(chip); 7092 return err; 7093 } 7094 7095 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7096 int port, struct dsa_lag lag) 7097 { 7098 struct mv88e6xxx_chip *chip = ds->priv; 7099 int err_sync, err_pvt; 7100 7101 mv88e6xxx_reg_lock(chip); 7102 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7103 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7104 mv88e6xxx_reg_unlock(chip); 7105 return err_sync ? : err_pvt; 7106 } 7107 7108 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7109 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7110 .mac_prepare = mv88e6xxx_mac_prepare, 7111 .mac_config = mv88e6xxx_mac_config, 7112 .mac_finish = mv88e6xxx_mac_finish, 7113 .mac_link_down = mv88e6xxx_mac_link_down, 7114 .mac_link_up = mv88e6xxx_mac_link_up, 7115 }; 7116 7117 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7118 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7119 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7120 .setup = mv88e6xxx_setup, 7121 .teardown = mv88e6xxx_teardown, 7122 .port_setup = mv88e6xxx_port_setup, 7123 .port_teardown = mv88e6xxx_port_teardown, 7124 .phylink_get_caps = mv88e6xxx_get_caps, 7125 .get_strings = mv88e6xxx_get_strings, 7126 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7127 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7128 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7129 .get_sset_count = mv88e6xxx_get_sset_count, 7130 .port_max_mtu = mv88e6xxx_get_max_mtu, 7131 .port_change_mtu = mv88e6xxx_change_mtu, 7132 .support_eee = dsa_supports_eee, 7133 .set_mac_eee = mv88e6xxx_set_mac_eee, 7134 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7135 .get_eeprom = mv88e6xxx_get_eeprom, 7136 .set_eeprom = mv88e6xxx_set_eeprom, 7137 .get_regs_len = mv88e6xxx_get_regs_len, 7138 .get_regs = mv88e6xxx_get_regs, 7139 .get_rxnfc = mv88e6xxx_get_rxnfc, 7140 .set_rxnfc = mv88e6xxx_set_rxnfc, 7141 .set_ageing_time = mv88e6xxx_set_ageing_time, 7142 .port_bridge_join = mv88e6xxx_port_bridge_join, 7143 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7144 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7145 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7146 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7147 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7148 .port_fast_age = mv88e6xxx_port_fast_age, 7149 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7150 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7151 .port_vlan_add = mv88e6xxx_port_vlan_add, 7152 .port_vlan_del = mv88e6xxx_port_vlan_del, 7153 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7154 .port_fdb_add = mv88e6xxx_port_fdb_add, 7155 .port_fdb_del = mv88e6xxx_port_fdb_del, 7156 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7157 .port_mdb_add = mv88e6xxx_port_mdb_add, 7158 .port_mdb_del = mv88e6xxx_port_mdb_del, 7159 .port_mirror_add = mv88e6xxx_port_mirror_add, 7160 .port_mirror_del = mv88e6xxx_port_mirror_del, 7161 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7162 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7163 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7164 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7165 .port_txtstamp = mv88e6xxx_port_txtstamp, 7166 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7167 .get_ts_info = mv88e6xxx_get_ts_info, 7168 .devlink_param_get = mv88e6xxx_devlink_param_get, 7169 .devlink_param_set = mv88e6xxx_devlink_param_set, 7170 .devlink_info_get = mv88e6xxx_devlink_info_get, 7171 .port_lag_change = mv88e6xxx_port_lag_change, 7172 .port_lag_join = mv88e6xxx_port_lag_join, 7173 .port_lag_leave = mv88e6xxx_port_lag_leave, 7174 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7175 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7176 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7177 }; 7178 7179 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7180 { 7181 struct device *dev = chip->dev; 7182 struct dsa_switch *ds; 7183 7184 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7185 if (!ds) 7186 return -ENOMEM; 7187 7188 ds->dev = dev; 7189 ds->num_ports = mv88e6xxx_num_ports(chip); 7190 ds->priv = chip; 7191 ds->dev = dev; 7192 ds->ops = &mv88e6xxx_switch_ops; 7193 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7194 ds->ageing_time_min = chip->info->age_time_coeff; 7195 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7196 7197 /* Some chips support up to 32, but that requires enabling the 7198 * 5-bit port mode, which we do not support. 640k^W16 ought to 7199 * be enough for anyone. 7200 */ 7201 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7202 7203 dev_set_drvdata(dev, ds); 7204 7205 return dsa_register_switch(ds); 7206 } 7207 7208 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7209 { 7210 dsa_unregister_switch(chip->ds); 7211 } 7212 7213 static const void *pdata_device_get_match_data(struct device *dev) 7214 { 7215 const struct of_device_id *matches = dev->driver->of_match_table; 7216 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7217 7218 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7219 matches++) { 7220 if (!strcmp(pdata->compatible, matches->compatible)) 7221 return matches->data; 7222 } 7223 return NULL; 7224 } 7225 7226 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7227 * would be lost after a power cycle so prevent it to be suspended. 7228 */ 7229 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7230 { 7231 return -EOPNOTSUPP; 7232 } 7233 7234 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7235 { 7236 return 0; 7237 } 7238 7239 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7240 7241 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7242 { 7243 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7244 const struct mv88e6xxx_info *compat_info = NULL; 7245 struct device *dev = &mdiodev->dev; 7246 struct device_node *np = dev->of_node; 7247 struct mv88e6xxx_chip *chip; 7248 int port; 7249 int err; 7250 7251 if (!np && !pdata) 7252 return -EINVAL; 7253 7254 if (np) 7255 compat_info = of_device_get_match_data(dev); 7256 7257 if (pdata) { 7258 compat_info = pdata_device_get_match_data(dev); 7259 7260 if (!pdata->netdev) 7261 return -EINVAL; 7262 7263 for (port = 0; port < DSA_MAX_PORTS; port++) { 7264 if (!(pdata->enabled_ports & (1 << port))) 7265 continue; 7266 if (strcmp(pdata->cd.port_names[port], "cpu")) 7267 continue; 7268 pdata->cd.netdev[port] = &pdata->netdev->dev; 7269 break; 7270 } 7271 } 7272 7273 if (!compat_info) 7274 return -EINVAL; 7275 7276 chip = mv88e6xxx_alloc_chip(dev); 7277 if (!chip) { 7278 err = -ENOMEM; 7279 goto out; 7280 } 7281 7282 chip->info = compat_info; 7283 7284 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7285 if (IS_ERR(chip->reset)) { 7286 err = PTR_ERR(chip->reset); 7287 goto out; 7288 } 7289 if (chip->reset) 7290 usleep_range(10000, 20000); 7291 7292 /* Detect if the device is configured in single chip addressing mode, 7293 * otherwise continue with address specific smi init/detection. 7294 */ 7295 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7296 if (err) { 7297 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7298 if (err) 7299 goto out; 7300 7301 err = mv88e6xxx_detect(chip); 7302 if (err) 7303 goto out; 7304 } 7305 7306 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7307 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7308 else 7309 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7310 7311 mv88e6xxx_phy_init(chip); 7312 7313 if (chip->info->ops->get_eeprom) { 7314 if (np) 7315 of_property_read_u32(np, "eeprom-length", 7316 &chip->eeprom_len); 7317 else 7318 chip->eeprom_len = pdata->eeprom_len; 7319 } 7320 7321 mv88e6xxx_reg_lock(chip); 7322 err = mv88e6xxx_switch_reset(chip); 7323 mv88e6xxx_reg_unlock(chip); 7324 if (err) 7325 goto out; 7326 7327 if (np) { 7328 chip->irq = of_irq_get(np, 0); 7329 if (chip->irq == -EPROBE_DEFER) { 7330 err = chip->irq; 7331 goto out; 7332 } 7333 } 7334 7335 if (pdata) 7336 chip->irq = pdata->irq; 7337 7338 /* Has to be performed before the MDIO bus is created, because 7339 * the PHYs will link their interrupts to these interrupt 7340 * controllers 7341 */ 7342 mv88e6xxx_reg_lock(chip); 7343 if (chip->irq > 0) 7344 err = mv88e6xxx_g1_irq_setup(chip); 7345 else 7346 err = mv88e6xxx_irq_poll_setup(chip); 7347 mv88e6xxx_reg_unlock(chip); 7348 7349 if (err) 7350 goto out; 7351 7352 if (chip->info->g2_irqs > 0) { 7353 err = mv88e6xxx_g2_irq_setup(chip); 7354 if (err) 7355 goto out_g1_irq; 7356 } 7357 7358 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7359 if (err) 7360 goto out_g2_irq; 7361 7362 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7363 if (err) 7364 goto out_g1_atu_prob_irq; 7365 7366 err = mv88e6xxx_register_switch(chip); 7367 if (err) 7368 goto out_g1_vtu_prob_irq; 7369 7370 return 0; 7371 7372 out_g1_vtu_prob_irq: 7373 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7374 out_g1_atu_prob_irq: 7375 mv88e6xxx_g1_atu_prob_irq_free(chip); 7376 out_g2_irq: 7377 if (chip->info->g2_irqs > 0) 7378 mv88e6xxx_g2_irq_free(chip); 7379 out_g1_irq: 7380 if (chip->irq > 0) 7381 mv88e6xxx_g1_irq_free(chip); 7382 else 7383 mv88e6xxx_irq_poll_free(chip); 7384 out: 7385 if (pdata) 7386 dev_put(pdata->netdev); 7387 7388 return err; 7389 } 7390 7391 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7392 { 7393 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7394 struct mv88e6xxx_chip *chip; 7395 7396 if (!ds) 7397 return; 7398 7399 chip = ds->priv; 7400 7401 if (chip->info->ptp_support) { 7402 mv88e6xxx_hwtstamp_free(chip); 7403 mv88e6xxx_ptp_free(chip); 7404 } 7405 7406 mv88e6xxx_phy_destroy(chip); 7407 mv88e6xxx_unregister_switch(chip); 7408 7409 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7410 mv88e6xxx_g1_atu_prob_irq_free(chip); 7411 7412 if (chip->info->g2_irqs > 0) 7413 mv88e6xxx_g2_irq_free(chip); 7414 7415 if (chip->irq > 0) 7416 mv88e6xxx_g1_irq_free(chip); 7417 else 7418 mv88e6xxx_irq_poll_free(chip); 7419 } 7420 7421 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7422 { 7423 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7424 7425 if (!ds) 7426 return; 7427 7428 dsa_switch_shutdown(ds); 7429 7430 dev_set_drvdata(&mdiodev->dev, NULL); 7431 } 7432 7433 static const struct of_device_id mv88e6xxx_of_match[] = { 7434 { 7435 .compatible = "marvell,mv88e6085", 7436 .data = &mv88e6xxx_table[MV88E6085], 7437 }, 7438 { 7439 .compatible = "marvell,mv88e6190", 7440 .data = &mv88e6xxx_table[MV88E6190], 7441 }, 7442 { 7443 .compatible = "marvell,mv88e6250", 7444 .data = &mv88e6xxx_table[MV88E6250], 7445 }, 7446 { /* sentinel */ }, 7447 }; 7448 7449 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7450 7451 static struct mdio_driver mv88e6xxx_driver = { 7452 .probe = mv88e6xxx_probe, 7453 .remove = mv88e6xxx_remove, 7454 .shutdown = mv88e6xxx_shutdown, 7455 .mdiodrv.driver = { 7456 .name = "mv88e6085", 7457 .of_match_table = mv88e6xxx_of_match, 7458 .pm = &mv88e6xxx_pm_ops, 7459 }, 7460 }; 7461 7462 mdio_module_driver(mv88e6xxx_driver); 7463 7464 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7465 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7466 MODULE_LICENSE("GPL"); 7467