1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 int lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 int lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane >= 0) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 int lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane >= 0) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 int lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane >= 0) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 639 unsigned long *mask, 640 struct phylink_link_state *state) 641 { 642 if (port == 0 || port == 9 || port == 10) { 643 phylink_set(mask, 10000baseT_Full); 644 phylink_set(mask, 10000baseKR_Full); 645 phylink_set(mask, 10000baseCR_Full); 646 phylink_set(mask, 10000baseSR_Full); 647 phylink_set(mask, 10000baseLR_Full); 648 phylink_set(mask, 10000baseLRM_Full); 649 phylink_set(mask, 10000baseER_Full); 650 phylink_set(mask, 5000baseT_Full); 651 phylink_set(mask, 2500baseX_Full); 652 phylink_set(mask, 2500baseT_Full); 653 } 654 655 phylink_set(mask, 1000baseT_Full); 656 phylink_set(mask, 1000baseX_Full); 657 658 mv88e6065_phylink_validate(chip, port, mask, state); 659 } 660 661 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 662 unsigned long *supported, 663 struct phylink_link_state *state) 664 { 665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 666 struct mv88e6xxx_chip *chip = ds->priv; 667 668 /* Allow all the expected bits */ 669 phylink_set(mask, Autoneg); 670 phylink_set(mask, Pause); 671 phylink_set_port_modes(mask); 672 673 if (chip->info->ops->phylink_validate) 674 chip->info->ops->phylink_validate(chip, port, mask, state); 675 676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 677 bitmap_and(state->advertising, state->advertising, mask, 678 __ETHTOOL_LINK_MODE_MASK_NBITS); 679 680 /* We can only operate at 2500BaseX or 1000BaseX. If requested 681 * to advertise both, only report advertising at 2500BaseX. 682 */ 683 phylink_helper_basex_speed(state); 684 } 685 686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 687 unsigned int mode, 688 const struct phylink_link_state *state) 689 { 690 struct mv88e6xxx_chip *chip = ds->priv; 691 struct mv88e6xxx_port *p; 692 int err; 693 694 p = &chip->ports[port]; 695 696 /* FIXME: is this the correct test? If we're in fixed mode on an 697 * internal port, why should we process this any different from 698 * PHY mode? On the other hand, the port may be automedia between 699 * an internal PHY and the serdes... 700 */ 701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 702 return; 703 704 mv88e6xxx_reg_lock(chip); 705 /* In inband mode, the link may come up at any time while the link 706 * is not forced down. Force the link down while we reconfigure the 707 * interface mode. 708 */ 709 if (mode == MLO_AN_INBAND && p->interface != state->interface && 710 chip->info->ops->port_set_link) 711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 712 713 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 714 if (err && err != -EOPNOTSUPP) 715 goto err_unlock; 716 717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 718 state->advertising); 719 /* FIXME: we should restart negotiation if something changed - which 720 * is something we get if we convert to using phylinks PCS operations. 721 */ 722 if (err > 0) 723 err = 0; 724 725 /* Undo the forced down state above after completing configuration 726 * irrespective of its state on entry, which allows the link to come up. 727 */ 728 if (mode == MLO_AN_INBAND && p->interface != state->interface && 729 chip->info->ops->port_set_link) 730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 731 732 p->interface = state->interface; 733 734 err_unlock: 735 mv88e6xxx_reg_unlock(chip); 736 737 if (err && err != -EOPNOTSUPP) 738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 739 } 740 741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 742 unsigned int mode, 743 phy_interface_t interface) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 753 mode == MLO_AN_FIXED) && ops->port_sync_link) 754 err = ops->port_sync_link(chip, port, mode, false); 755 mv88e6xxx_reg_unlock(chip); 756 757 if (err) 758 dev_err(chip->dev, 759 "p%d: failed to force MAC link down\n", port); 760 } 761 762 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 763 unsigned int mode, phy_interface_t interface, 764 struct phy_device *phydev, 765 int speed, int duplex, 766 bool tx_pause, bool rx_pause) 767 { 768 struct mv88e6xxx_chip *chip = ds->priv; 769 const struct mv88e6xxx_ops *ops; 770 int err = 0; 771 772 ops = chip->info->ops; 773 774 mv88e6xxx_reg_lock(chip); 775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 776 /* FIXME: for an automedia port, should we force the link 777 * down here - what if the link comes up due to "other" media 778 * while we're bringing the port up, how is the exclusivity 779 * handled in the Marvell hardware? E.g. port 2 on 88E6390 780 * shared between internal PHY and Serdes. 781 */ 782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 783 duplex); 784 if (err) 785 goto error; 786 787 if (ops->port_set_speed_duplex) { 788 err = ops->port_set_speed_duplex(chip, port, 789 speed, duplex); 790 if (err && err != -EOPNOTSUPP) 791 goto error; 792 } 793 794 if (ops->port_sync_link) 795 err = ops->port_sync_link(chip, port, mode, true); 796 } 797 error: 798 mv88e6xxx_reg_unlock(chip); 799 800 if (err && err != -EOPNOTSUPP) 801 dev_err(ds->dev, 802 "p%d: failed to configure MAC link up\n", port); 803 } 804 805 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 806 { 807 if (!chip->info->ops->stats_snapshot) 808 return -EOPNOTSUPP; 809 810 return chip->info->ops->stats_snapshot(chip, port); 811 } 812 813 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 834 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 837 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 873 }; 874 875 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 876 struct mv88e6xxx_hw_stat *s, 877 int port, u16 bank1_select, 878 u16 histogram) 879 { 880 u32 low; 881 u32 high = 0; 882 u16 reg = 0; 883 int err; 884 u64 value; 885 886 switch (s->type) { 887 case STATS_TYPE_PORT: 888 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 889 if (err) 890 return U64_MAX; 891 892 low = reg; 893 if (s->size == 4) { 894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 895 if (err) 896 return U64_MAX; 897 low |= ((u32)reg) << 16; 898 } 899 break; 900 case STATS_TYPE_BANK1: 901 reg = bank1_select; 902 fallthrough; 903 case STATS_TYPE_BANK0: 904 reg |= s->reg | histogram; 905 mv88e6xxx_g1_stats_read(chip, reg, &low); 906 if (s->size == 8) 907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 908 break; 909 default: 910 return U64_MAX; 911 } 912 value = (((u64)high) << 32) | low; 913 return value; 914 } 915 916 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 917 uint8_t *data, int types) 918 { 919 struct mv88e6xxx_hw_stat *stat; 920 int i, j; 921 922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 923 stat = &mv88e6xxx_hw_stats[i]; 924 if (stat->type & types) { 925 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 926 ETH_GSTRING_LEN); 927 j++; 928 } 929 } 930 931 return j; 932 } 933 934 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 935 uint8_t *data) 936 { 937 return mv88e6xxx_stats_get_strings(chip, data, 938 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 939 } 940 941 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 942 uint8_t *data) 943 { 944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 945 } 946 947 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 948 uint8_t *data) 949 { 950 return mv88e6xxx_stats_get_strings(chip, data, 951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 952 } 953 954 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 955 "atu_member_violation", 956 "atu_miss_violation", 957 "atu_full_violation", 958 "vtu_member_violation", 959 "vtu_miss_violation", 960 }; 961 962 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 963 { 964 unsigned int i; 965 966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 967 strlcpy(data + i * ETH_GSTRING_LEN, 968 mv88e6xxx_atu_vtu_stats_strings[i], 969 ETH_GSTRING_LEN); 970 } 971 972 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 973 u32 stringset, uint8_t *data) 974 { 975 struct mv88e6xxx_chip *chip = ds->priv; 976 int count = 0; 977 978 if (stringset != ETH_SS_STATS) 979 return; 980 981 mv88e6xxx_reg_lock(chip); 982 983 if (chip->info->ops->stats_get_strings) 984 count = chip->info->ops->stats_get_strings(chip, data); 985 986 if (chip->info->ops->serdes_get_strings) { 987 data += count * ETH_GSTRING_LEN; 988 count = chip->info->ops->serdes_get_strings(chip, port, data); 989 } 990 991 data += count * ETH_GSTRING_LEN; 992 mv88e6xxx_atu_vtu_get_strings(data); 993 994 mv88e6xxx_reg_unlock(chip); 995 } 996 997 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 998 int types) 999 { 1000 struct mv88e6xxx_hw_stat *stat; 1001 int i, j; 1002 1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1004 stat = &mv88e6xxx_hw_stats[i]; 1005 if (stat->type & types) 1006 j++; 1007 } 1008 return j; 1009 } 1010 1011 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1012 { 1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1014 STATS_TYPE_PORT); 1015 } 1016 1017 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1018 { 1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1020 } 1021 1022 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1023 { 1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1025 STATS_TYPE_BANK1); 1026 } 1027 1028 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1029 { 1030 struct mv88e6xxx_chip *chip = ds->priv; 1031 int serdes_count = 0; 1032 int count = 0; 1033 1034 if (sset != ETH_SS_STATS) 1035 return 0; 1036 1037 mv88e6xxx_reg_lock(chip); 1038 if (chip->info->ops->stats_get_sset_count) 1039 count = chip->info->ops->stats_get_sset_count(chip); 1040 if (count < 0) 1041 goto out; 1042 1043 if (chip->info->ops->serdes_get_sset_count) 1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1045 port); 1046 if (serdes_count < 0) { 1047 count = serdes_count; 1048 goto out; 1049 } 1050 count += serdes_count; 1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1052 1053 out: 1054 mv88e6xxx_reg_unlock(chip); 1055 1056 return count; 1057 } 1058 1059 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1060 uint64_t *data, int types, 1061 u16 bank1_select, u16 histogram) 1062 { 1063 struct mv88e6xxx_hw_stat *stat; 1064 int i, j; 1065 1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1067 stat = &mv88e6xxx_hw_stats[i]; 1068 if (stat->type & types) { 1069 mv88e6xxx_reg_lock(chip); 1070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1071 bank1_select, 1072 histogram); 1073 mv88e6xxx_reg_unlock(chip); 1074 1075 j++; 1076 } 1077 } 1078 return j; 1079 } 1080 1081 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1082 uint64_t *data) 1083 { 1084 return mv88e6xxx_stats_get_stats(chip, port, data, 1085 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1087 } 1088 1089 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1090 uint64_t *data) 1091 { 1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1094 } 1095 1096 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1097 uint64_t *data) 1098 { 1099 return mv88e6xxx_stats_get_stats(chip, port, data, 1100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1103 } 1104 1105 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1106 uint64_t *data) 1107 { 1108 return mv88e6xxx_stats_get_stats(chip, port, data, 1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1111 0); 1112 } 1113 1114 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 *data++ = chip->ports[port].atu_member_violation; 1118 *data++ = chip->ports[port].atu_miss_violation; 1119 *data++ = chip->ports[port].atu_full_violation; 1120 *data++ = chip->ports[port].vtu_member_violation; 1121 *data++ = chip->ports[port].vtu_miss_violation; 1122 } 1123 1124 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1125 uint64_t *data) 1126 { 1127 int count = 0; 1128 1129 if (chip->info->ops->stats_get_stats) 1130 count = chip->info->ops->stats_get_stats(chip, port, data); 1131 1132 mv88e6xxx_reg_lock(chip); 1133 if (chip->info->ops->serdes_get_stats) { 1134 data += count; 1135 count = chip->info->ops->serdes_get_stats(chip, port, data); 1136 } 1137 data += count; 1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1139 mv88e6xxx_reg_unlock(chip); 1140 } 1141 1142 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1143 uint64_t *data) 1144 { 1145 struct mv88e6xxx_chip *chip = ds->priv; 1146 int ret; 1147 1148 mv88e6xxx_reg_lock(chip); 1149 1150 ret = mv88e6xxx_stats_snapshot(chip, port); 1151 mv88e6xxx_reg_unlock(chip); 1152 1153 if (ret < 0) 1154 return; 1155 1156 mv88e6xxx_get_stats(chip, port, data); 1157 1158 } 1159 1160 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1161 { 1162 struct mv88e6xxx_chip *chip = ds->priv; 1163 int len; 1164 1165 len = 32 * sizeof(u16); 1166 if (chip->info->ops->serdes_get_regs_len) 1167 len += chip->info->ops->serdes_get_regs_len(chip, port); 1168 1169 return len; 1170 } 1171 1172 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1173 struct ethtool_regs *regs, void *_p) 1174 { 1175 struct mv88e6xxx_chip *chip = ds->priv; 1176 int err; 1177 u16 reg; 1178 u16 *p = _p; 1179 int i; 1180 1181 regs->version = chip->info->prod_num; 1182 1183 memset(p, 0xff, 32 * sizeof(u16)); 1184 1185 mv88e6xxx_reg_lock(chip); 1186 1187 for (i = 0; i < 32; i++) { 1188 1189 err = mv88e6xxx_port_read(chip, port, i, ®); 1190 if (!err) 1191 p[i] = reg; 1192 } 1193 1194 if (chip->info->ops->serdes_get_regs) 1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1196 1197 mv88e6xxx_reg_unlock(chip); 1198 } 1199 1200 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1201 struct ethtool_eee *e) 1202 { 1203 /* Nothing to do on the port's MAC */ 1204 return 0; 1205 } 1206 1207 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1208 struct ethtool_eee *e) 1209 { 1210 /* Nothing to do on the port's MAC */ 1211 return 0; 1212 } 1213 1214 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1215 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1216 { 1217 struct dsa_switch *ds = chip->ds; 1218 struct dsa_switch_tree *dst = ds->dst; 1219 struct net_device *br; 1220 struct dsa_port *dp; 1221 bool found = false; 1222 u16 pvlan; 1223 1224 list_for_each_entry(dp, &dst->ports, list) { 1225 if (dp->ds->index == dev && dp->index == port) { 1226 found = true; 1227 break; 1228 } 1229 } 1230 1231 /* Prevent frames from unknown switch or port */ 1232 if (!found) 1233 return 0; 1234 1235 /* Frames from DSA links and CPU ports can egress any local port */ 1236 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1237 return mv88e6xxx_port_mask(chip); 1238 1239 br = dp->bridge_dev; 1240 pvlan = 0; 1241 1242 /* Frames from user ports can egress any local DSA links and CPU ports, 1243 * as well as any local member of their bridge group. 1244 */ 1245 list_for_each_entry(dp, &dst->ports, list) 1246 if (dp->ds == ds && 1247 (dp->type == DSA_PORT_TYPE_CPU || 1248 dp->type == DSA_PORT_TYPE_DSA || 1249 (br && dp->bridge_dev == br))) 1250 pvlan |= BIT(dp->index); 1251 1252 return pvlan; 1253 } 1254 1255 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1256 { 1257 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1258 1259 /* prevent frames from going back out of the port they came in on */ 1260 output_ports &= ~BIT(port); 1261 1262 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1263 } 1264 1265 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1266 u8 state) 1267 { 1268 struct mv88e6xxx_chip *chip = ds->priv; 1269 int err; 1270 1271 mv88e6xxx_reg_lock(chip); 1272 err = mv88e6xxx_port_set_state(chip, port, state); 1273 mv88e6xxx_reg_unlock(chip); 1274 1275 if (err) 1276 dev_err(ds->dev, "p%d: failed to update state\n", port); 1277 } 1278 1279 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1280 { 1281 int err; 1282 1283 if (chip->info->ops->ieee_pri_map) { 1284 err = chip->info->ops->ieee_pri_map(chip); 1285 if (err) 1286 return err; 1287 } 1288 1289 if (chip->info->ops->ip_pri_map) { 1290 err = chip->info->ops->ip_pri_map(chip); 1291 if (err) 1292 return err; 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1299 { 1300 struct dsa_switch *ds = chip->ds; 1301 int target, port; 1302 int err; 1303 1304 if (!chip->info->global2_addr) 1305 return 0; 1306 1307 /* Initialize the routing port to the 32 possible target devices */ 1308 for (target = 0; target < 32; target++) { 1309 port = dsa_routing_port(ds, target); 1310 if (port == ds->num_ports) 1311 port = 0x1f; 1312 1313 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1314 if (err) 1315 return err; 1316 } 1317 1318 if (chip->info->ops->set_cascade_port) { 1319 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1320 err = chip->info->ops->set_cascade_port(chip, port); 1321 if (err) 1322 return err; 1323 } 1324 1325 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1326 if (err) 1327 return err; 1328 1329 return 0; 1330 } 1331 1332 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1333 { 1334 /* Clear all trunk masks and mapping */ 1335 if (chip->info->global2_addr) 1336 return mv88e6xxx_g2_trunk_clear(chip); 1337 1338 return 0; 1339 } 1340 1341 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1342 { 1343 if (chip->info->ops->rmu_disable) 1344 return chip->info->ops->rmu_disable(chip); 1345 1346 return 0; 1347 } 1348 1349 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1350 { 1351 if (chip->info->ops->pot_clear) 1352 return chip->info->ops->pot_clear(chip); 1353 1354 return 0; 1355 } 1356 1357 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1358 { 1359 if (chip->info->ops->mgmt_rsvd2cpu) 1360 return chip->info->ops->mgmt_rsvd2cpu(chip); 1361 1362 return 0; 1363 } 1364 1365 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1366 { 1367 int err; 1368 1369 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1370 if (err) 1371 return err; 1372 1373 /* The chips that have a "learn2all" bit in Global1, ATU 1374 * Control are precisely those whose port registers have a 1375 * Message Port bit in Port Control 1 and hence implement 1376 * ->port_setup_message_port. 1377 */ 1378 if (chip->info->ops->port_setup_message_port) { 1379 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1380 if (err) 1381 return err; 1382 } 1383 1384 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1385 } 1386 1387 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 int port; 1390 int err; 1391 1392 if (!chip->info->ops->irl_init_all) 1393 return 0; 1394 1395 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1396 /* Disable ingress rate limiting by resetting all per port 1397 * ingress rate limit resources to their initial state. 1398 */ 1399 err = chip->info->ops->irl_init_all(chip, port); 1400 if (err) 1401 return err; 1402 } 1403 1404 return 0; 1405 } 1406 1407 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1408 { 1409 if (chip->info->ops->set_switch_mac) { 1410 u8 addr[ETH_ALEN]; 1411 1412 eth_random_addr(addr); 1413 1414 return chip->info->ops->set_switch_mac(chip, addr); 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1421 { 1422 struct dsa_switch_tree *dst = chip->ds->dst; 1423 struct dsa_switch *ds; 1424 struct dsa_port *dp; 1425 u16 pvlan = 0; 1426 1427 if (!mv88e6xxx_has_pvt(chip)) 1428 return 0; 1429 1430 /* Skip the local source device, which uses in-chip port VLAN */ 1431 if (dev != chip->ds->index) { 1432 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1433 1434 ds = dsa_switch_find(dst->index, dev); 1435 dp = ds ? dsa_to_port(ds, port) : NULL; 1436 if (dp && dp->lag_dev) { 1437 /* As the PVT is used to limit flooding of 1438 * FORWARD frames, which use the LAG ID as the 1439 * source port, we must translate dev/port to 1440 * the special "LAG device" in the PVT, using 1441 * the LAG ID as the port number. 1442 */ 1443 dev = MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK; 1444 port = dsa_lag_id(dst, dp->lag_dev); 1445 } 1446 } 1447 1448 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1449 } 1450 1451 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1452 { 1453 int dev, port; 1454 int err; 1455 1456 if (!mv88e6xxx_has_pvt(chip)) 1457 return 0; 1458 1459 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1460 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1461 */ 1462 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1463 if (err) 1464 return err; 1465 1466 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1467 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1468 err = mv88e6xxx_pvt_map(chip, dev, port); 1469 if (err) 1470 return err; 1471 } 1472 } 1473 1474 return 0; 1475 } 1476 1477 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1478 { 1479 struct mv88e6xxx_chip *chip = ds->priv; 1480 int err; 1481 1482 if (dsa_to_port(ds, port)->lag_dev) 1483 /* Hardware is incapable of fast-aging a LAG through a 1484 * regular ATU move operation. Until we have something 1485 * more fancy in place this is a no-op. 1486 */ 1487 return; 1488 1489 mv88e6xxx_reg_lock(chip); 1490 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1491 mv88e6xxx_reg_unlock(chip); 1492 1493 if (err) 1494 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1495 } 1496 1497 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1498 { 1499 if (!mv88e6xxx_max_vid(chip)) 1500 return 0; 1501 1502 return mv88e6xxx_g1_vtu_flush(chip); 1503 } 1504 1505 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1506 struct mv88e6xxx_vtu_entry *entry) 1507 { 1508 int err; 1509 1510 if (!chip->info->ops->vtu_getnext) 1511 return -EOPNOTSUPP; 1512 1513 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1514 entry->valid = false; 1515 1516 err = chip->info->ops->vtu_getnext(chip, entry); 1517 1518 if (entry->vid != vid) 1519 entry->valid = false; 1520 1521 return err; 1522 } 1523 1524 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1525 int (*cb)(struct mv88e6xxx_chip *chip, 1526 const struct mv88e6xxx_vtu_entry *entry, 1527 void *priv), 1528 void *priv) 1529 { 1530 struct mv88e6xxx_vtu_entry entry = { 1531 .vid = mv88e6xxx_max_vid(chip), 1532 .valid = false, 1533 }; 1534 int err; 1535 1536 if (!chip->info->ops->vtu_getnext) 1537 return -EOPNOTSUPP; 1538 1539 do { 1540 err = chip->info->ops->vtu_getnext(chip, &entry); 1541 if (err) 1542 return err; 1543 1544 if (!entry.valid) 1545 break; 1546 1547 err = cb(chip, &entry, priv); 1548 if (err) 1549 return err; 1550 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1551 1552 return 0; 1553 } 1554 1555 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1556 struct mv88e6xxx_vtu_entry *entry) 1557 { 1558 if (!chip->info->ops->vtu_loadpurge) 1559 return -EOPNOTSUPP; 1560 1561 return chip->info->ops->vtu_loadpurge(chip, entry); 1562 } 1563 1564 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1565 const struct mv88e6xxx_vtu_entry *entry, 1566 void *_fid_bitmap) 1567 { 1568 unsigned long *fid_bitmap = _fid_bitmap; 1569 1570 set_bit(entry->fid, fid_bitmap); 1571 return 0; 1572 } 1573 1574 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1575 { 1576 int i, err; 1577 u16 fid; 1578 1579 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1580 1581 /* Set every FID bit used by the (un)bridged ports */ 1582 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1583 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1584 if (err) 1585 return err; 1586 1587 set_bit(fid, fid_bitmap); 1588 } 1589 1590 /* Set every FID bit used by the VLAN entries */ 1591 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1592 } 1593 1594 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1595 { 1596 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1597 int err; 1598 1599 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1600 if (err) 1601 return err; 1602 1603 /* The reset value 0x000 is used to indicate that multiple address 1604 * databases are not needed. Return the next positive available. 1605 */ 1606 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1607 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1608 return -ENOSPC; 1609 1610 /* Clear the database */ 1611 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1612 } 1613 1614 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1615 u16 vid) 1616 { 1617 struct mv88e6xxx_chip *chip = ds->priv; 1618 struct mv88e6xxx_vtu_entry vlan; 1619 int i, err; 1620 1621 if (!vid) 1622 return -EOPNOTSUPP; 1623 1624 /* DSA and CPU ports have to be members of multiple vlans */ 1625 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1626 return 0; 1627 1628 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1629 if (err) 1630 return err; 1631 1632 if (!vlan.valid) 1633 return 0; 1634 1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1636 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1637 continue; 1638 1639 if (!dsa_to_port(ds, i)->slave) 1640 continue; 1641 1642 if (vlan.member[i] == 1643 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1644 continue; 1645 1646 if (dsa_to_port(ds, i)->bridge_dev == 1647 dsa_to_port(ds, port)->bridge_dev) 1648 break; /* same bridge, check next VLAN */ 1649 1650 if (!dsa_to_port(ds, i)->bridge_dev) 1651 continue; 1652 1653 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1654 port, vlan.vid, i, 1655 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1656 return -EOPNOTSUPP; 1657 } 1658 1659 return 0; 1660 } 1661 1662 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1663 bool vlan_filtering, 1664 struct netlink_ext_ack *extack) 1665 { 1666 struct mv88e6xxx_chip *chip = ds->priv; 1667 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1668 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1669 int err; 1670 1671 if (!mv88e6xxx_max_vid(chip)) 1672 return -EOPNOTSUPP; 1673 1674 mv88e6xxx_reg_lock(chip); 1675 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1676 mv88e6xxx_reg_unlock(chip); 1677 1678 return err; 1679 } 1680 1681 static int 1682 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1683 const struct switchdev_obj_port_vlan *vlan) 1684 { 1685 struct mv88e6xxx_chip *chip = ds->priv; 1686 int err; 1687 1688 if (!mv88e6xxx_max_vid(chip)) 1689 return -EOPNOTSUPP; 1690 1691 /* If the requested port doesn't belong to the same bridge as the VLAN 1692 * members, do not support it (yet) and fallback to software VLAN. 1693 */ 1694 mv88e6xxx_reg_lock(chip); 1695 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1696 mv88e6xxx_reg_unlock(chip); 1697 1698 return err; 1699 } 1700 1701 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1702 const unsigned char *addr, u16 vid, 1703 u8 state) 1704 { 1705 struct mv88e6xxx_atu_entry entry; 1706 struct mv88e6xxx_vtu_entry vlan; 1707 u16 fid; 1708 int err; 1709 1710 /* Null VLAN ID corresponds to the port private database */ 1711 if (vid == 0) { 1712 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1713 if (err) 1714 return err; 1715 } else { 1716 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1717 if (err) 1718 return err; 1719 1720 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1721 if (!vlan.valid) 1722 return -EOPNOTSUPP; 1723 1724 fid = vlan.fid; 1725 } 1726 1727 entry.state = 0; 1728 ether_addr_copy(entry.mac, addr); 1729 eth_addr_dec(entry.mac); 1730 1731 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1732 if (err) 1733 return err; 1734 1735 /* Initialize a fresh ATU entry if it isn't found */ 1736 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1737 memset(&entry, 0, sizeof(entry)); 1738 ether_addr_copy(entry.mac, addr); 1739 } 1740 1741 /* Purge the ATU entry only if no port is using it anymore */ 1742 if (!state) { 1743 entry.portvec &= ~BIT(port); 1744 if (!entry.portvec) 1745 entry.state = 0; 1746 } else { 1747 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1748 entry.portvec = BIT(port); 1749 else 1750 entry.portvec |= BIT(port); 1751 1752 entry.state = state; 1753 } 1754 1755 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1756 } 1757 1758 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1759 const struct mv88e6xxx_policy *policy) 1760 { 1761 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1762 enum mv88e6xxx_policy_action action = policy->action; 1763 const u8 *addr = policy->addr; 1764 u16 vid = policy->vid; 1765 u8 state; 1766 int err; 1767 int id; 1768 1769 if (!chip->info->ops->port_set_policy) 1770 return -EOPNOTSUPP; 1771 1772 switch (mapping) { 1773 case MV88E6XXX_POLICY_MAPPING_DA: 1774 case MV88E6XXX_POLICY_MAPPING_SA: 1775 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1776 state = 0; /* Dissociate the port and address */ 1777 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1778 is_multicast_ether_addr(addr)) 1779 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1780 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1781 is_unicast_ether_addr(addr)) 1782 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1783 else 1784 return -EOPNOTSUPP; 1785 1786 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1787 state); 1788 if (err) 1789 return err; 1790 break; 1791 default: 1792 return -EOPNOTSUPP; 1793 } 1794 1795 /* Skip the port's policy clearing if the mapping is still in use */ 1796 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1797 idr_for_each_entry(&chip->policies, policy, id) 1798 if (policy->port == port && 1799 policy->mapping == mapping && 1800 policy->action != action) 1801 return 0; 1802 1803 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1804 } 1805 1806 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1807 struct ethtool_rx_flow_spec *fs) 1808 { 1809 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1810 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1811 enum mv88e6xxx_policy_mapping mapping; 1812 enum mv88e6xxx_policy_action action; 1813 struct mv88e6xxx_policy *policy; 1814 u16 vid = 0; 1815 u8 *addr; 1816 int err; 1817 int id; 1818 1819 if (fs->location != RX_CLS_LOC_ANY) 1820 return -EINVAL; 1821 1822 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1823 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1824 else 1825 return -EOPNOTSUPP; 1826 1827 switch (fs->flow_type & ~FLOW_EXT) { 1828 case ETHER_FLOW: 1829 if (!is_zero_ether_addr(mac_mask->h_dest) && 1830 is_zero_ether_addr(mac_mask->h_source)) { 1831 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1832 addr = mac_entry->h_dest; 1833 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1834 !is_zero_ether_addr(mac_mask->h_source)) { 1835 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1836 addr = mac_entry->h_source; 1837 } else { 1838 /* Cannot support DA and SA mapping in the same rule */ 1839 return -EOPNOTSUPP; 1840 } 1841 break; 1842 default: 1843 return -EOPNOTSUPP; 1844 } 1845 1846 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1847 if (fs->m_ext.vlan_tci != htons(0xffff)) 1848 return -EOPNOTSUPP; 1849 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1850 } 1851 1852 idr_for_each_entry(&chip->policies, policy, id) { 1853 if (policy->port == port && policy->mapping == mapping && 1854 policy->action == action && policy->vid == vid && 1855 ether_addr_equal(policy->addr, addr)) 1856 return -EEXIST; 1857 } 1858 1859 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1860 if (!policy) 1861 return -ENOMEM; 1862 1863 fs->location = 0; 1864 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1865 GFP_KERNEL); 1866 if (err) { 1867 devm_kfree(chip->dev, policy); 1868 return err; 1869 } 1870 1871 memcpy(&policy->fs, fs, sizeof(*fs)); 1872 ether_addr_copy(policy->addr, addr); 1873 policy->mapping = mapping; 1874 policy->action = action; 1875 policy->port = port; 1876 policy->vid = vid; 1877 1878 err = mv88e6xxx_policy_apply(chip, port, policy); 1879 if (err) { 1880 idr_remove(&chip->policies, fs->location); 1881 devm_kfree(chip->dev, policy); 1882 return err; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1889 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1890 { 1891 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1892 struct mv88e6xxx_chip *chip = ds->priv; 1893 struct mv88e6xxx_policy *policy; 1894 int err; 1895 int id; 1896 1897 mv88e6xxx_reg_lock(chip); 1898 1899 switch (rxnfc->cmd) { 1900 case ETHTOOL_GRXCLSRLCNT: 1901 rxnfc->data = 0; 1902 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1903 rxnfc->rule_cnt = 0; 1904 idr_for_each_entry(&chip->policies, policy, id) 1905 if (policy->port == port) 1906 rxnfc->rule_cnt++; 1907 err = 0; 1908 break; 1909 case ETHTOOL_GRXCLSRULE: 1910 err = -ENOENT; 1911 policy = idr_find(&chip->policies, fs->location); 1912 if (policy) { 1913 memcpy(fs, &policy->fs, sizeof(*fs)); 1914 err = 0; 1915 } 1916 break; 1917 case ETHTOOL_GRXCLSRLALL: 1918 rxnfc->data = 0; 1919 rxnfc->rule_cnt = 0; 1920 idr_for_each_entry(&chip->policies, policy, id) 1921 if (policy->port == port) 1922 rule_locs[rxnfc->rule_cnt++] = id; 1923 err = 0; 1924 break; 1925 default: 1926 err = -EOPNOTSUPP; 1927 break; 1928 } 1929 1930 mv88e6xxx_reg_unlock(chip); 1931 1932 return err; 1933 } 1934 1935 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1936 struct ethtool_rxnfc *rxnfc) 1937 { 1938 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1939 struct mv88e6xxx_chip *chip = ds->priv; 1940 struct mv88e6xxx_policy *policy; 1941 int err; 1942 1943 mv88e6xxx_reg_lock(chip); 1944 1945 switch (rxnfc->cmd) { 1946 case ETHTOOL_SRXCLSRLINS: 1947 err = mv88e6xxx_policy_insert(chip, port, fs); 1948 break; 1949 case ETHTOOL_SRXCLSRLDEL: 1950 err = -ENOENT; 1951 policy = idr_remove(&chip->policies, fs->location); 1952 if (policy) { 1953 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1954 err = mv88e6xxx_policy_apply(chip, port, policy); 1955 devm_kfree(chip->dev, policy); 1956 } 1957 break; 1958 default: 1959 err = -EOPNOTSUPP; 1960 break; 1961 } 1962 1963 mv88e6xxx_reg_unlock(chip); 1964 1965 return err; 1966 } 1967 1968 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1969 u16 vid) 1970 { 1971 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1972 u8 broadcast[ETH_ALEN]; 1973 1974 eth_broadcast_addr(broadcast); 1975 1976 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1977 } 1978 1979 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1980 { 1981 int port; 1982 int err; 1983 1984 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1985 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1986 struct net_device *brport; 1987 1988 if (dsa_is_unused_port(chip->ds, port)) 1989 continue; 1990 1991 brport = dsa_port_to_bridge_port(dp); 1992 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 1993 /* Skip bridged user ports where broadcast 1994 * flooding is disabled. 1995 */ 1996 continue; 1997 1998 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1999 if (err) 2000 return err; 2001 } 2002 2003 return 0; 2004 } 2005 2006 struct mv88e6xxx_port_broadcast_sync_ctx { 2007 int port; 2008 bool flood; 2009 }; 2010 2011 static int 2012 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2013 const struct mv88e6xxx_vtu_entry *vlan, 2014 void *_ctx) 2015 { 2016 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2017 u8 broadcast[ETH_ALEN]; 2018 u8 state; 2019 2020 if (ctx->flood) 2021 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2022 else 2023 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2024 2025 eth_broadcast_addr(broadcast); 2026 2027 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2028 vlan->vid, state); 2029 } 2030 2031 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2032 bool flood) 2033 { 2034 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2035 .port = port, 2036 .flood = flood, 2037 }; 2038 struct mv88e6xxx_vtu_entry vid0 = { 2039 .vid = 0, 2040 }; 2041 int err; 2042 2043 /* Update the port's private database... */ 2044 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2045 if (err) 2046 return err; 2047 2048 /* ...and the database for all VLANs. */ 2049 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2050 &ctx); 2051 } 2052 2053 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2054 u16 vid, u8 member, bool warn) 2055 { 2056 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2057 struct mv88e6xxx_vtu_entry vlan; 2058 int i, err; 2059 2060 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2061 if (err) 2062 return err; 2063 2064 if (!vlan.valid) { 2065 memset(&vlan, 0, sizeof(vlan)); 2066 2067 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2068 if (err) 2069 return err; 2070 2071 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2072 if (i == port) 2073 vlan.member[i] = member; 2074 else 2075 vlan.member[i] = non_member; 2076 2077 vlan.vid = vid; 2078 vlan.valid = true; 2079 2080 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2081 if (err) 2082 return err; 2083 2084 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2085 if (err) 2086 return err; 2087 } else if (vlan.member[port] != member) { 2088 vlan.member[port] = member; 2089 2090 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2091 if (err) 2092 return err; 2093 } else if (warn) { 2094 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2095 port, vid); 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2102 const struct switchdev_obj_port_vlan *vlan, 2103 struct netlink_ext_ack *extack) 2104 { 2105 struct mv88e6xxx_chip *chip = ds->priv; 2106 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2107 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2108 bool warn; 2109 u8 member; 2110 int err; 2111 2112 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2113 if (err) 2114 return err; 2115 2116 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2117 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2118 else if (untagged) 2119 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2120 else 2121 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2122 2123 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2124 * and then the CPU port. Do not warn for duplicates for the CPU port. 2125 */ 2126 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2127 2128 mv88e6xxx_reg_lock(chip); 2129 2130 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2131 if (err) { 2132 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2133 vlan->vid, untagged ? 'u' : 't'); 2134 goto out; 2135 } 2136 2137 if (pvid) { 2138 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid); 2139 if (err) { 2140 dev_err(ds->dev, "p%d: failed to set PVID %d\n", 2141 port, vlan->vid); 2142 goto out; 2143 } 2144 } 2145 out: 2146 mv88e6xxx_reg_unlock(chip); 2147 2148 return err; 2149 } 2150 2151 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2152 int port, u16 vid) 2153 { 2154 struct mv88e6xxx_vtu_entry vlan; 2155 int i, err; 2156 2157 if (!vid) 2158 return -EOPNOTSUPP; 2159 2160 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2161 if (err) 2162 return err; 2163 2164 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2165 * tell switchdev that this VLAN is likely handled in software. 2166 */ 2167 if (!vlan.valid || 2168 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2169 return -EOPNOTSUPP; 2170 2171 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2172 2173 /* keep the VLAN unless all ports are excluded */ 2174 vlan.valid = false; 2175 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2176 if (vlan.member[i] != 2177 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2178 vlan.valid = true; 2179 break; 2180 } 2181 } 2182 2183 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2184 if (err) 2185 return err; 2186 2187 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2188 } 2189 2190 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2191 const struct switchdev_obj_port_vlan *vlan) 2192 { 2193 struct mv88e6xxx_chip *chip = ds->priv; 2194 int err = 0; 2195 u16 pvid; 2196 2197 if (!mv88e6xxx_max_vid(chip)) 2198 return -EOPNOTSUPP; 2199 2200 mv88e6xxx_reg_lock(chip); 2201 2202 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2203 if (err) 2204 goto unlock; 2205 2206 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2207 if (err) 2208 goto unlock; 2209 2210 if (vlan->vid == pvid) { 2211 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2212 if (err) 2213 goto unlock; 2214 } 2215 2216 unlock: 2217 mv88e6xxx_reg_unlock(chip); 2218 2219 return err; 2220 } 2221 2222 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2223 const unsigned char *addr, u16 vid) 2224 { 2225 struct mv88e6xxx_chip *chip = ds->priv; 2226 int err; 2227 2228 mv88e6xxx_reg_lock(chip); 2229 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2230 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2231 mv88e6xxx_reg_unlock(chip); 2232 2233 return err; 2234 } 2235 2236 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2237 const unsigned char *addr, u16 vid) 2238 { 2239 struct mv88e6xxx_chip *chip = ds->priv; 2240 int err; 2241 2242 mv88e6xxx_reg_lock(chip); 2243 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2244 mv88e6xxx_reg_unlock(chip); 2245 2246 return err; 2247 } 2248 2249 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2250 u16 fid, u16 vid, int port, 2251 dsa_fdb_dump_cb_t *cb, void *data) 2252 { 2253 struct mv88e6xxx_atu_entry addr; 2254 bool is_static; 2255 int err; 2256 2257 addr.state = 0; 2258 eth_broadcast_addr(addr.mac); 2259 2260 do { 2261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2262 if (err) 2263 return err; 2264 2265 if (!addr.state) 2266 break; 2267 2268 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2269 continue; 2270 2271 if (!is_unicast_ether_addr(addr.mac)) 2272 continue; 2273 2274 is_static = (addr.state == 2275 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2276 err = cb(addr.mac, vid, is_static, data); 2277 if (err) 2278 return err; 2279 } while (!is_broadcast_ether_addr(addr.mac)); 2280 2281 return err; 2282 } 2283 2284 struct mv88e6xxx_port_db_dump_vlan_ctx { 2285 int port; 2286 dsa_fdb_dump_cb_t *cb; 2287 void *data; 2288 }; 2289 2290 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2291 const struct mv88e6xxx_vtu_entry *entry, 2292 void *_data) 2293 { 2294 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2295 2296 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2297 ctx->port, ctx->cb, ctx->data); 2298 } 2299 2300 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2301 dsa_fdb_dump_cb_t *cb, void *data) 2302 { 2303 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2304 .port = port, 2305 .cb = cb, 2306 .data = data, 2307 }; 2308 u16 fid; 2309 int err; 2310 2311 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2312 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2313 if (err) 2314 return err; 2315 2316 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2317 if (err) 2318 return err; 2319 2320 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2321 } 2322 2323 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2324 dsa_fdb_dump_cb_t *cb, void *data) 2325 { 2326 struct mv88e6xxx_chip *chip = ds->priv; 2327 int err; 2328 2329 mv88e6xxx_reg_lock(chip); 2330 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2331 mv88e6xxx_reg_unlock(chip); 2332 2333 return err; 2334 } 2335 2336 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2337 struct net_device *br) 2338 { 2339 struct dsa_switch *ds = chip->ds; 2340 struct dsa_switch_tree *dst = ds->dst; 2341 struct dsa_port *dp; 2342 int err; 2343 2344 list_for_each_entry(dp, &dst->ports, list) { 2345 if (dp->bridge_dev == br) { 2346 if (dp->ds == ds) { 2347 /* This is a local bridge group member, 2348 * remap its Port VLAN Map. 2349 */ 2350 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2351 if (err) 2352 return err; 2353 } else { 2354 /* This is an external bridge group member, 2355 * remap its cross-chip Port VLAN Table entry. 2356 */ 2357 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2358 dp->index); 2359 if (err) 2360 return err; 2361 } 2362 } 2363 } 2364 2365 return 0; 2366 } 2367 2368 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2369 struct net_device *br) 2370 { 2371 struct mv88e6xxx_chip *chip = ds->priv; 2372 int err; 2373 2374 mv88e6xxx_reg_lock(chip); 2375 err = mv88e6xxx_bridge_map(chip, br); 2376 mv88e6xxx_reg_unlock(chip); 2377 2378 return err; 2379 } 2380 2381 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2382 struct net_device *br) 2383 { 2384 struct mv88e6xxx_chip *chip = ds->priv; 2385 2386 mv88e6xxx_reg_lock(chip); 2387 if (mv88e6xxx_bridge_map(chip, br) || 2388 mv88e6xxx_port_vlan_map(chip, port)) 2389 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2390 mv88e6xxx_reg_unlock(chip); 2391 } 2392 2393 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2394 int tree_index, int sw_index, 2395 int port, struct net_device *br) 2396 { 2397 struct mv88e6xxx_chip *chip = ds->priv; 2398 int err; 2399 2400 if (tree_index != ds->dst->index) 2401 return 0; 2402 2403 mv88e6xxx_reg_lock(chip); 2404 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2405 mv88e6xxx_reg_unlock(chip); 2406 2407 return err; 2408 } 2409 2410 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2411 int tree_index, int sw_index, 2412 int port, struct net_device *br) 2413 { 2414 struct mv88e6xxx_chip *chip = ds->priv; 2415 2416 if (tree_index != ds->dst->index) 2417 return; 2418 2419 mv88e6xxx_reg_lock(chip); 2420 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2421 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2422 mv88e6xxx_reg_unlock(chip); 2423 } 2424 2425 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2426 { 2427 if (chip->info->ops->reset) 2428 return chip->info->ops->reset(chip); 2429 2430 return 0; 2431 } 2432 2433 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2434 { 2435 struct gpio_desc *gpiod = chip->reset; 2436 2437 /* If there is a GPIO connected to the reset pin, toggle it */ 2438 if (gpiod) { 2439 gpiod_set_value_cansleep(gpiod, 1); 2440 usleep_range(10000, 20000); 2441 gpiod_set_value_cansleep(gpiod, 0); 2442 usleep_range(10000, 20000); 2443 2444 mv88e6xxx_g1_wait_eeprom_done(chip); 2445 } 2446 } 2447 2448 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2449 { 2450 int i, err; 2451 2452 /* Set all ports to the Disabled state */ 2453 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2454 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2455 if (err) 2456 return err; 2457 } 2458 2459 /* Wait for transmit queues to drain, 2460 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2461 */ 2462 usleep_range(2000, 4000); 2463 2464 return 0; 2465 } 2466 2467 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2468 { 2469 int err; 2470 2471 err = mv88e6xxx_disable_ports(chip); 2472 if (err) 2473 return err; 2474 2475 mv88e6xxx_hardware_reset(chip); 2476 2477 return mv88e6xxx_software_reset(chip); 2478 } 2479 2480 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2481 enum mv88e6xxx_frame_mode frame, 2482 enum mv88e6xxx_egress_mode egress, u16 etype) 2483 { 2484 int err; 2485 2486 if (!chip->info->ops->port_set_frame_mode) 2487 return -EOPNOTSUPP; 2488 2489 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2490 if (err) 2491 return err; 2492 2493 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2494 if (err) 2495 return err; 2496 2497 if (chip->info->ops->port_set_ether_type) 2498 return chip->info->ops->port_set_ether_type(chip, port, etype); 2499 2500 return 0; 2501 } 2502 2503 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2504 { 2505 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2506 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2507 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2508 } 2509 2510 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2511 { 2512 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2513 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2514 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2515 } 2516 2517 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2518 { 2519 return mv88e6xxx_set_port_mode(chip, port, 2520 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2521 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2522 ETH_P_EDSA); 2523 } 2524 2525 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2526 { 2527 if (dsa_is_dsa_port(chip->ds, port)) 2528 return mv88e6xxx_set_port_mode_dsa(chip, port); 2529 2530 if (dsa_is_user_port(chip->ds, port)) 2531 return mv88e6xxx_set_port_mode_normal(chip, port); 2532 2533 /* Setup CPU port mode depending on its supported tag format */ 2534 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2535 return mv88e6xxx_set_port_mode_dsa(chip, port); 2536 2537 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2538 return mv88e6xxx_set_port_mode_edsa(chip, port); 2539 2540 return -EINVAL; 2541 } 2542 2543 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2544 { 2545 bool message = dsa_is_dsa_port(chip->ds, port); 2546 2547 return mv88e6xxx_port_set_message_port(chip, port, message); 2548 } 2549 2550 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2551 { 2552 int err; 2553 2554 if (chip->info->ops->port_set_ucast_flood) { 2555 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2556 if (err) 2557 return err; 2558 } 2559 if (chip->info->ops->port_set_mcast_flood) { 2560 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2561 if (err) 2562 return err; 2563 } 2564 2565 return 0; 2566 } 2567 2568 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2569 { 2570 struct mv88e6xxx_port *mvp = dev_id; 2571 struct mv88e6xxx_chip *chip = mvp->chip; 2572 irqreturn_t ret = IRQ_NONE; 2573 int port = mvp->port; 2574 int lane; 2575 2576 mv88e6xxx_reg_lock(chip); 2577 lane = mv88e6xxx_serdes_get_lane(chip, port); 2578 if (lane >= 0) 2579 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2580 mv88e6xxx_reg_unlock(chip); 2581 2582 return ret; 2583 } 2584 2585 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2586 int lane) 2587 { 2588 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2589 unsigned int irq; 2590 int err; 2591 2592 /* Nothing to request if this SERDES port has no IRQ */ 2593 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2594 if (!irq) 2595 return 0; 2596 2597 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2598 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2599 2600 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2601 mv88e6xxx_reg_unlock(chip); 2602 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2603 IRQF_ONESHOT, dev_id->serdes_irq_name, 2604 dev_id); 2605 mv88e6xxx_reg_lock(chip); 2606 if (err) 2607 return err; 2608 2609 dev_id->serdes_irq = irq; 2610 2611 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2612 } 2613 2614 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2615 int lane) 2616 { 2617 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2618 unsigned int irq = dev_id->serdes_irq; 2619 int err; 2620 2621 /* Nothing to free if no IRQ has been requested */ 2622 if (!irq) 2623 return 0; 2624 2625 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2626 2627 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2628 mv88e6xxx_reg_unlock(chip); 2629 free_irq(irq, dev_id); 2630 mv88e6xxx_reg_lock(chip); 2631 2632 dev_id->serdes_irq = 0; 2633 2634 return err; 2635 } 2636 2637 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2638 bool on) 2639 { 2640 int lane; 2641 int err; 2642 2643 lane = mv88e6xxx_serdes_get_lane(chip, port); 2644 if (lane < 0) 2645 return 0; 2646 2647 if (on) { 2648 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2649 if (err) 2650 return err; 2651 2652 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2653 } else { 2654 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2655 if (err) 2656 return err; 2657 2658 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2659 } 2660 2661 return err; 2662 } 2663 2664 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2665 enum mv88e6xxx_egress_direction direction, 2666 int port) 2667 { 2668 int err; 2669 2670 if (!chip->info->ops->set_egress_port) 2671 return -EOPNOTSUPP; 2672 2673 err = chip->info->ops->set_egress_port(chip, direction, port); 2674 if (err) 2675 return err; 2676 2677 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2678 chip->ingress_dest_port = port; 2679 else 2680 chip->egress_dest_port = port; 2681 2682 return 0; 2683 } 2684 2685 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2686 { 2687 struct dsa_switch *ds = chip->ds; 2688 int upstream_port; 2689 int err; 2690 2691 upstream_port = dsa_upstream_port(ds, port); 2692 if (chip->info->ops->port_set_upstream_port) { 2693 err = chip->info->ops->port_set_upstream_port(chip, port, 2694 upstream_port); 2695 if (err) 2696 return err; 2697 } 2698 2699 if (port == upstream_port) { 2700 if (chip->info->ops->set_cpu_port) { 2701 err = chip->info->ops->set_cpu_port(chip, 2702 upstream_port); 2703 if (err) 2704 return err; 2705 } 2706 2707 err = mv88e6xxx_set_egress_port(chip, 2708 MV88E6XXX_EGRESS_DIR_INGRESS, 2709 upstream_port); 2710 if (err && err != -EOPNOTSUPP) 2711 return err; 2712 2713 err = mv88e6xxx_set_egress_port(chip, 2714 MV88E6XXX_EGRESS_DIR_EGRESS, 2715 upstream_port); 2716 if (err && err != -EOPNOTSUPP) 2717 return err; 2718 } 2719 2720 return 0; 2721 } 2722 2723 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2724 { 2725 struct dsa_switch *ds = chip->ds; 2726 int err; 2727 u16 reg; 2728 2729 chip->ports[port].chip = chip; 2730 chip->ports[port].port = port; 2731 2732 /* MAC Forcing register: don't force link, speed, duplex or flow control 2733 * state to any particular values on physical ports, but force the CPU 2734 * port and all DSA ports to their maximum bandwidth and full duplex. 2735 */ 2736 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2737 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2738 SPEED_MAX, DUPLEX_FULL, 2739 PAUSE_OFF, 2740 PHY_INTERFACE_MODE_NA); 2741 else 2742 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2743 SPEED_UNFORCED, DUPLEX_UNFORCED, 2744 PAUSE_ON, 2745 PHY_INTERFACE_MODE_NA); 2746 if (err) 2747 return err; 2748 2749 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2750 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2751 * tunneling, determine priority by looking at 802.1p and IP 2752 * priority fields (IP prio has precedence), and set STP state 2753 * to Forwarding. 2754 * 2755 * If this is the CPU link, use DSA or EDSA tagging depending 2756 * on which tagging mode was configured. 2757 * 2758 * If this is a link to another switch, use DSA tagging mode. 2759 * 2760 * If this is the upstream port for this switch, enable 2761 * forwarding of unknown unicasts and multicasts. 2762 */ 2763 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2764 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2765 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2766 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2767 if (err) 2768 return err; 2769 2770 err = mv88e6xxx_setup_port_mode(chip, port); 2771 if (err) 2772 return err; 2773 2774 err = mv88e6xxx_setup_egress_floods(chip, port); 2775 if (err) 2776 return err; 2777 2778 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2779 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2780 * untagged frames on this port, do a destination address lookup on all 2781 * received packets as usual, disable ARP mirroring and don't send a 2782 * copy of all transmitted/received frames on this port to the CPU. 2783 */ 2784 err = mv88e6xxx_port_set_map_da(chip, port); 2785 if (err) 2786 return err; 2787 2788 err = mv88e6xxx_setup_upstream_port(chip, port); 2789 if (err) 2790 return err; 2791 2792 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2793 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2794 if (err) 2795 return err; 2796 2797 if (chip->info->ops->port_set_jumbo_size) { 2798 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2799 if (err) 2800 return err; 2801 } 2802 2803 /* Port Association Vector: disable automatic address learning 2804 * on all user ports since they start out in standalone 2805 * mode. When joining a bridge, learning will be configured to 2806 * match the bridge port settings. Enable learning on all 2807 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2808 * learning process. 2809 * 2810 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2811 * and RefreshLocked. I.e. setup standard automatic learning. 2812 */ 2813 if (dsa_is_user_port(ds, port)) 2814 reg = 0; 2815 else 2816 reg = 1 << port; 2817 2818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2819 reg); 2820 if (err) 2821 return err; 2822 2823 /* Egress rate control 2: disable egress rate control. */ 2824 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2825 0x0000); 2826 if (err) 2827 return err; 2828 2829 if (chip->info->ops->port_pause_limit) { 2830 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2831 if (err) 2832 return err; 2833 } 2834 2835 if (chip->info->ops->port_disable_learn_limit) { 2836 err = chip->info->ops->port_disable_learn_limit(chip, port); 2837 if (err) 2838 return err; 2839 } 2840 2841 if (chip->info->ops->port_disable_pri_override) { 2842 err = chip->info->ops->port_disable_pri_override(chip, port); 2843 if (err) 2844 return err; 2845 } 2846 2847 if (chip->info->ops->port_tag_remap) { 2848 err = chip->info->ops->port_tag_remap(chip, port); 2849 if (err) 2850 return err; 2851 } 2852 2853 if (chip->info->ops->port_egress_rate_limiting) { 2854 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2855 if (err) 2856 return err; 2857 } 2858 2859 if (chip->info->ops->port_setup_message_port) { 2860 err = chip->info->ops->port_setup_message_port(chip, port); 2861 if (err) 2862 return err; 2863 } 2864 2865 /* Port based VLAN map: give each port the same default address 2866 * database, and allow bidirectional communication between the 2867 * CPU and DSA port(s), and the other ports. 2868 */ 2869 err = mv88e6xxx_port_set_fid(chip, port, 0); 2870 if (err) 2871 return err; 2872 2873 err = mv88e6xxx_port_vlan_map(chip, port); 2874 if (err) 2875 return err; 2876 2877 /* Default VLAN ID and priority: don't set a default VLAN 2878 * ID, and set the default packet priority to zero. 2879 */ 2880 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2881 } 2882 2883 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2884 { 2885 struct mv88e6xxx_chip *chip = ds->priv; 2886 2887 if (chip->info->ops->port_set_jumbo_size) 2888 return 10240; 2889 else if (chip->info->ops->set_max_frame_size) 2890 return 1632; 2891 return 1522; 2892 } 2893 2894 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2895 { 2896 struct mv88e6xxx_chip *chip = ds->priv; 2897 int ret = 0; 2898 2899 mv88e6xxx_reg_lock(chip); 2900 if (chip->info->ops->port_set_jumbo_size) 2901 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2902 else if (chip->info->ops->set_max_frame_size) 2903 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2904 else 2905 if (new_mtu > 1522) 2906 ret = -EINVAL; 2907 mv88e6xxx_reg_unlock(chip); 2908 2909 return ret; 2910 } 2911 2912 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2913 struct phy_device *phydev) 2914 { 2915 struct mv88e6xxx_chip *chip = ds->priv; 2916 int err; 2917 2918 mv88e6xxx_reg_lock(chip); 2919 err = mv88e6xxx_serdes_power(chip, port, true); 2920 mv88e6xxx_reg_unlock(chip); 2921 2922 return err; 2923 } 2924 2925 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2926 { 2927 struct mv88e6xxx_chip *chip = ds->priv; 2928 2929 mv88e6xxx_reg_lock(chip); 2930 if (mv88e6xxx_serdes_power(chip, port, false)) 2931 dev_err(chip->dev, "failed to power off SERDES\n"); 2932 mv88e6xxx_reg_unlock(chip); 2933 } 2934 2935 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2936 unsigned int ageing_time) 2937 { 2938 struct mv88e6xxx_chip *chip = ds->priv; 2939 int err; 2940 2941 mv88e6xxx_reg_lock(chip); 2942 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2943 mv88e6xxx_reg_unlock(chip); 2944 2945 return err; 2946 } 2947 2948 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2949 { 2950 int err; 2951 2952 /* Initialize the statistics unit */ 2953 if (chip->info->ops->stats_set_histogram) { 2954 err = chip->info->ops->stats_set_histogram(chip); 2955 if (err) 2956 return err; 2957 } 2958 2959 return mv88e6xxx_g1_stats_clear(chip); 2960 } 2961 2962 /* Check if the errata has already been applied. */ 2963 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2964 { 2965 int port; 2966 int err; 2967 u16 val; 2968 2969 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2970 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2971 if (err) { 2972 dev_err(chip->dev, 2973 "Error reading hidden register: %d\n", err); 2974 return false; 2975 } 2976 if (val != 0x01c0) 2977 return false; 2978 } 2979 2980 return true; 2981 } 2982 2983 /* The 6390 copper ports have an errata which require poking magic 2984 * values into undocumented hidden registers and then performing a 2985 * software reset. 2986 */ 2987 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2988 { 2989 int port; 2990 int err; 2991 2992 if (mv88e6390_setup_errata_applied(chip)) 2993 return 0; 2994 2995 /* Set the ports into blocking mode */ 2996 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2997 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2998 if (err) 2999 return err; 3000 } 3001 3002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3003 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3004 if (err) 3005 return err; 3006 } 3007 3008 return mv88e6xxx_software_reset(chip); 3009 } 3010 3011 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3012 { 3013 mv88e6xxx_teardown_devlink_params(ds); 3014 dsa_devlink_resources_unregister(ds); 3015 mv88e6xxx_teardown_devlink_regions(ds); 3016 } 3017 3018 static int mv88e6xxx_setup(struct dsa_switch *ds) 3019 { 3020 struct mv88e6xxx_chip *chip = ds->priv; 3021 u8 cmode; 3022 int err; 3023 int i; 3024 3025 chip->ds = ds; 3026 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3027 3028 mv88e6xxx_reg_lock(chip); 3029 3030 if (chip->info->ops->setup_errata) { 3031 err = chip->info->ops->setup_errata(chip); 3032 if (err) 3033 goto unlock; 3034 } 3035 3036 /* Cache the cmode of each port. */ 3037 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3038 if (chip->info->ops->port_get_cmode) { 3039 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3040 if (err) 3041 goto unlock; 3042 3043 chip->ports[i].cmode = cmode; 3044 } 3045 } 3046 3047 /* Setup Switch Port Registers */ 3048 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3049 if (dsa_is_unused_port(ds, i)) 3050 continue; 3051 3052 /* Prevent the use of an invalid port. */ 3053 if (mv88e6xxx_is_invalid_port(chip, i)) { 3054 dev_err(chip->dev, "port %d is invalid\n", i); 3055 err = -EINVAL; 3056 goto unlock; 3057 } 3058 3059 err = mv88e6xxx_setup_port(chip, i); 3060 if (err) 3061 goto unlock; 3062 } 3063 3064 err = mv88e6xxx_irl_setup(chip); 3065 if (err) 3066 goto unlock; 3067 3068 err = mv88e6xxx_mac_setup(chip); 3069 if (err) 3070 goto unlock; 3071 3072 err = mv88e6xxx_phy_setup(chip); 3073 if (err) 3074 goto unlock; 3075 3076 err = mv88e6xxx_vtu_setup(chip); 3077 if (err) 3078 goto unlock; 3079 3080 err = mv88e6xxx_pvt_setup(chip); 3081 if (err) 3082 goto unlock; 3083 3084 err = mv88e6xxx_atu_setup(chip); 3085 if (err) 3086 goto unlock; 3087 3088 err = mv88e6xxx_broadcast_setup(chip, 0); 3089 if (err) 3090 goto unlock; 3091 3092 err = mv88e6xxx_pot_setup(chip); 3093 if (err) 3094 goto unlock; 3095 3096 err = mv88e6xxx_rmu_setup(chip); 3097 if (err) 3098 goto unlock; 3099 3100 err = mv88e6xxx_rsvd2cpu_setup(chip); 3101 if (err) 3102 goto unlock; 3103 3104 err = mv88e6xxx_trunk_setup(chip); 3105 if (err) 3106 goto unlock; 3107 3108 err = mv88e6xxx_devmap_setup(chip); 3109 if (err) 3110 goto unlock; 3111 3112 err = mv88e6xxx_pri_setup(chip); 3113 if (err) 3114 goto unlock; 3115 3116 /* Setup PTP Hardware Clock and timestamping */ 3117 if (chip->info->ptp_support) { 3118 err = mv88e6xxx_ptp_setup(chip); 3119 if (err) 3120 goto unlock; 3121 3122 err = mv88e6xxx_hwtstamp_setup(chip); 3123 if (err) 3124 goto unlock; 3125 } 3126 3127 err = mv88e6xxx_stats_setup(chip); 3128 if (err) 3129 goto unlock; 3130 3131 unlock: 3132 mv88e6xxx_reg_unlock(chip); 3133 3134 if (err) 3135 return err; 3136 3137 /* Have to be called without holding the register lock, since 3138 * they take the devlink lock, and we later take the locks in 3139 * the reverse order when getting/setting parameters or 3140 * resource occupancy. 3141 */ 3142 err = mv88e6xxx_setup_devlink_resources(ds); 3143 if (err) 3144 return err; 3145 3146 err = mv88e6xxx_setup_devlink_params(ds); 3147 if (err) 3148 goto out_resources; 3149 3150 err = mv88e6xxx_setup_devlink_regions(ds); 3151 if (err) 3152 goto out_params; 3153 3154 return 0; 3155 3156 out_params: 3157 mv88e6xxx_teardown_devlink_params(ds); 3158 out_resources: 3159 dsa_devlink_resources_unregister(ds); 3160 3161 return err; 3162 } 3163 3164 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3165 { 3166 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3167 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3168 u16 val; 3169 int err; 3170 3171 if (!chip->info->ops->phy_read) 3172 return -EOPNOTSUPP; 3173 3174 mv88e6xxx_reg_lock(chip); 3175 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3176 mv88e6xxx_reg_unlock(chip); 3177 3178 if (reg == MII_PHYSID2) { 3179 /* Some internal PHYs don't have a model number. */ 3180 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3181 /* Then there is the 6165 family. It gets is 3182 * PHYs correct. But it can also have two 3183 * SERDES interfaces in the PHY address 3184 * space. And these don't have a model 3185 * number. But they are not PHYs, so we don't 3186 * want to give them something a PHY driver 3187 * will recognise. 3188 * 3189 * Use the mv88e6390 family model number 3190 * instead, for anything which really could be 3191 * a PHY, 3192 */ 3193 if (!(val & 0x3f0)) 3194 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3195 } 3196 3197 return err ? err : val; 3198 } 3199 3200 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3201 { 3202 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3203 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3204 int err; 3205 3206 if (!chip->info->ops->phy_write) 3207 return -EOPNOTSUPP; 3208 3209 mv88e6xxx_reg_lock(chip); 3210 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3211 mv88e6xxx_reg_unlock(chip); 3212 3213 return err; 3214 } 3215 3216 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3217 struct device_node *np, 3218 bool external) 3219 { 3220 static int index; 3221 struct mv88e6xxx_mdio_bus *mdio_bus; 3222 struct mii_bus *bus; 3223 int err; 3224 3225 if (external) { 3226 mv88e6xxx_reg_lock(chip); 3227 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3228 mv88e6xxx_reg_unlock(chip); 3229 3230 if (err) 3231 return err; 3232 } 3233 3234 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3235 if (!bus) 3236 return -ENOMEM; 3237 3238 mdio_bus = bus->priv; 3239 mdio_bus->bus = bus; 3240 mdio_bus->chip = chip; 3241 INIT_LIST_HEAD(&mdio_bus->list); 3242 mdio_bus->external = external; 3243 3244 if (np) { 3245 bus->name = np->full_name; 3246 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3247 } else { 3248 bus->name = "mv88e6xxx SMI"; 3249 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3250 } 3251 3252 bus->read = mv88e6xxx_mdio_read; 3253 bus->write = mv88e6xxx_mdio_write; 3254 bus->parent = chip->dev; 3255 3256 if (!external) { 3257 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3258 if (err) 3259 return err; 3260 } 3261 3262 err = of_mdiobus_register(bus, np); 3263 if (err) { 3264 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3265 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3266 return err; 3267 } 3268 3269 if (external) 3270 list_add_tail(&mdio_bus->list, &chip->mdios); 3271 else 3272 list_add(&mdio_bus->list, &chip->mdios); 3273 3274 return 0; 3275 } 3276 3277 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3278 3279 { 3280 struct mv88e6xxx_mdio_bus *mdio_bus; 3281 struct mii_bus *bus; 3282 3283 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3284 bus = mdio_bus->bus; 3285 3286 if (!mdio_bus->external) 3287 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3288 3289 mdiobus_unregister(bus); 3290 } 3291 } 3292 3293 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3294 struct device_node *np) 3295 { 3296 struct device_node *child; 3297 int err; 3298 3299 /* Always register one mdio bus for the internal/default mdio 3300 * bus. This maybe represented in the device tree, but is 3301 * optional. 3302 */ 3303 child = of_get_child_by_name(np, "mdio"); 3304 err = mv88e6xxx_mdio_register(chip, child, false); 3305 if (err) 3306 return err; 3307 3308 /* Walk the device tree, and see if there are any other nodes 3309 * which say they are compatible with the external mdio 3310 * bus. 3311 */ 3312 for_each_available_child_of_node(np, child) { 3313 if (of_device_is_compatible( 3314 child, "marvell,mv88e6xxx-mdio-external")) { 3315 err = mv88e6xxx_mdio_register(chip, child, true); 3316 if (err) { 3317 mv88e6xxx_mdios_unregister(chip); 3318 of_node_put(child); 3319 return err; 3320 } 3321 } 3322 } 3323 3324 return 0; 3325 } 3326 3327 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3328 { 3329 struct mv88e6xxx_chip *chip = ds->priv; 3330 3331 return chip->eeprom_len; 3332 } 3333 3334 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3335 struct ethtool_eeprom *eeprom, u8 *data) 3336 { 3337 struct mv88e6xxx_chip *chip = ds->priv; 3338 int err; 3339 3340 if (!chip->info->ops->get_eeprom) 3341 return -EOPNOTSUPP; 3342 3343 mv88e6xxx_reg_lock(chip); 3344 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3345 mv88e6xxx_reg_unlock(chip); 3346 3347 if (err) 3348 return err; 3349 3350 eeprom->magic = 0xc3ec4951; 3351 3352 return 0; 3353 } 3354 3355 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3356 struct ethtool_eeprom *eeprom, u8 *data) 3357 { 3358 struct mv88e6xxx_chip *chip = ds->priv; 3359 int err; 3360 3361 if (!chip->info->ops->set_eeprom) 3362 return -EOPNOTSUPP; 3363 3364 if (eeprom->magic != 0xc3ec4951) 3365 return -EINVAL; 3366 3367 mv88e6xxx_reg_lock(chip); 3368 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3369 mv88e6xxx_reg_unlock(chip); 3370 3371 return err; 3372 } 3373 3374 static const struct mv88e6xxx_ops mv88e6085_ops = { 3375 /* MV88E6XXX_FAMILY_6097 */ 3376 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3377 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3378 .irl_init_all = mv88e6352_g2_irl_init_all, 3379 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3380 .phy_read = mv88e6185_phy_ppu_read, 3381 .phy_write = mv88e6185_phy_ppu_write, 3382 .port_set_link = mv88e6xxx_port_set_link, 3383 .port_sync_link = mv88e6xxx_port_sync_link, 3384 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3385 .port_tag_remap = mv88e6095_port_tag_remap, 3386 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3387 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3388 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3389 .port_set_ether_type = mv88e6351_port_set_ether_type, 3390 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3391 .port_pause_limit = mv88e6097_port_pause_limit, 3392 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3393 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3394 .port_get_cmode = mv88e6185_port_get_cmode, 3395 .port_setup_message_port = mv88e6xxx_setup_message_port, 3396 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3397 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3398 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3399 .stats_get_strings = mv88e6095_stats_get_strings, 3400 .stats_get_stats = mv88e6095_stats_get_stats, 3401 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3402 .set_egress_port = mv88e6095_g1_set_egress_port, 3403 .watchdog_ops = &mv88e6097_watchdog_ops, 3404 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3405 .pot_clear = mv88e6xxx_g2_pot_clear, 3406 .ppu_enable = mv88e6185_g1_ppu_enable, 3407 .ppu_disable = mv88e6185_g1_ppu_disable, 3408 .reset = mv88e6185_g1_reset, 3409 .rmu_disable = mv88e6085_g1_rmu_disable, 3410 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3411 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3412 .phylink_validate = mv88e6185_phylink_validate, 3413 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3414 }; 3415 3416 static const struct mv88e6xxx_ops mv88e6095_ops = { 3417 /* MV88E6XXX_FAMILY_6095 */ 3418 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3419 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3420 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3421 .phy_read = mv88e6185_phy_ppu_read, 3422 .phy_write = mv88e6185_phy_ppu_write, 3423 .port_set_link = mv88e6xxx_port_set_link, 3424 .port_sync_link = mv88e6185_port_sync_link, 3425 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3426 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3427 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3428 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3429 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3430 .port_get_cmode = mv88e6185_port_get_cmode, 3431 .port_setup_message_port = mv88e6xxx_setup_message_port, 3432 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3433 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3434 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3435 .stats_get_strings = mv88e6095_stats_get_strings, 3436 .stats_get_stats = mv88e6095_stats_get_stats, 3437 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3438 .serdes_power = mv88e6185_serdes_power, 3439 .serdes_get_lane = mv88e6185_serdes_get_lane, 3440 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3441 .ppu_enable = mv88e6185_g1_ppu_enable, 3442 .ppu_disable = mv88e6185_g1_ppu_disable, 3443 .reset = mv88e6185_g1_reset, 3444 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3445 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3446 .phylink_validate = mv88e6185_phylink_validate, 3447 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3448 }; 3449 3450 static const struct mv88e6xxx_ops mv88e6097_ops = { 3451 /* MV88E6XXX_FAMILY_6097 */ 3452 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3453 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3454 .irl_init_all = mv88e6352_g2_irl_init_all, 3455 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3456 .phy_read = mv88e6xxx_g2_smi_phy_read, 3457 .phy_write = mv88e6xxx_g2_smi_phy_write, 3458 .port_set_link = mv88e6xxx_port_set_link, 3459 .port_sync_link = mv88e6185_port_sync_link, 3460 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3461 .port_tag_remap = mv88e6095_port_tag_remap, 3462 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3463 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3464 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3465 .port_set_ether_type = mv88e6351_port_set_ether_type, 3466 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3467 .port_pause_limit = mv88e6097_port_pause_limit, 3468 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3469 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3470 .port_get_cmode = mv88e6185_port_get_cmode, 3471 .port_setup_message_port = mv88e6xxx_setup_message_port, 3472 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3473 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3474 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3475 .stats_get_strings = mv88e6095_stats_get_strings, 3476 .stats_get_stats = mv88e6095_stats_get_stats, 3477 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3478 .set_egress_port = mv88e6095_g1_set_egress_port, 3479 .watchdog_ops = &mv88e6097_watchdog_ops, 3480 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3481 .serdes_power = mv88e6185_serdes_power, 3482 .serdes_get_lane = mv88e6185_serdes_get_lane, 3483 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3484 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3485 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3486 .serdes_irq_status = mv88e6097_serdes_irq_status, 3487 .pot_clear = mv88e6xxx_g2_pot_clear, 3488 .reset = mv88e6352_g1_reset, 3489 .rmu_disable = mv88e6085_g1_rmu_disable, 3490 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3491 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3492 .phylink_validate = mv88e6185_phylink_validate, 3493 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3494 }; 3495 3496 static const struct mv88e6xxx_ops mv88e6123_ops = { 3497 /* MV88E6XXX_FAMILY_6165 */ 3498 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3499 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3500 .irl_init_all = mv88e6352_g2_irl_init_all, 3501 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3502 .phy_read = mv88e6xxx_g2_smi_phy_read, 3503 .phy_write = mv88e6xxx_g2_smi_phy_write, 3504 .port_set_link = mv88e6xxx_port_set_link, 3505 .port_sync_link = mv88e6xxx_port_sync_link, 3506 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3507 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3508 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3509 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3510 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3511 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3512 .port_get_cmode = mv88e6185_port_get_cmode, 3513 .port_setup_message_port = mv88e6xxx_setup_message_port, 3514 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3515 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3516 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3517 .stats_get_strings = mv88e6095_stats_get_strings, 3518 .stats_get_stats = mv88e6095_stats_get_stats, 3519 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3520 .set_egress_port = mv88e6095_g1_set_egress_port, 3521 .watchdog_ops = &mv88e6097_watchdog_ops, 3522 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3523 .pot_clear = mv88e6xxx_g2_pot_clear, 3524 .reset = mv88e6352_g1_reset, 3525 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3526 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3527 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3528 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3529 .phylink_validate = mv88e6185_phylink_validate, 3530 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3531 }; 3532 3533 static const struct mv88e6xxx_ops mv88e6131_ops = { 3534 /* MV88E6XXX_FAMILY_6185 */ 3535 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3536 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3537 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3538 .phy_read = mv88e6185_phy_ppu_read, 3539 .phy_write = mv88e6185_phy_ppu_write, 3540 .port_set_link = mv88e6xxx_port_set_link, 3541 .port_sync_link = mv88e6xxx_port_sync_link, 3542 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3543 .port_tag_remap = mv88e6095_port_tag_remap, 3544 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3545 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3546 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3547 .port_set_ether_type = mv88e6351_port_set_ether_type, 3548 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3549 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3550 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3551 .port_pause_limit = mv88e6097_port_pause_limit, 3552 .port_set_pause = mv88e6185_port_set_pause, 3553 .port_get_cmode = mv88e6185_port_get_cmode, 3554 .port_setup_message_port = mv88e6xxx_setup_message_port, 3555 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3556 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3557 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3558 .stats_get_strings = mv88e6095_stats_get_strings, 3559 .stats_get_stats = mv88e6095_stats_get_stats, 3560 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3561 .set_egress_port = mv88e6095_g1_set_egress_port, 3562 .watchdog_ops = &mv88e6097_watchdog_ops, 3563 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3564 .ppu_enable = mv88e6185_g1_ppu_enable, 3565 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3566 .ppu_disable = mv88e6185_g1_ppu_disable, 3567 .reset = mv88e6185_g1_reset, 3568 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3569 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3570 .phylink_validate = mv88e6185_phylink_validate, 3571 }; 3572 3573 static const struct mv88e6xxx_ops mv88e6141_ops = { 3574 /* MV88E6XXX_FAMILY_6341 */ 3575 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3576 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3577 .irl_init_all = mv88e6352_g2_irl_init_all, 3578 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3579 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3580 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3581 .phy_read = mv88e6xxx_g2_smi_phy_read, 3582 .phy_write = mv88e6xxx_g2_smi_phy_write, 3583 .port_set_link = mv88e6xxx_port_set_link, 3584 .port_sync_link = mv88e6xxx_port_sync_link, 3585 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3586 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3587 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3588 .port_tag_remap = mv88e6095_port_tag_remap, 3589 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3590 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3591 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3592 .port_set_ether_type = mv88e6351_port_set_ether_type, 3593 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3594 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3595 .port_pause_limit = mv88e6097_port_pause_limit, 3596 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3597 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3598 .port_get_cmode = mv88e6352_port_get_cmode, 3599 .port_set_cmode = mv88e6341_port_set_cmode, 3600 .port_setup_message_port = mv88e6xxx_setup_message_port, 3601 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3602 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3603 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3604 .stats_get_strings = mv88e6320_stats_get_strings, 3605 .stats_get_stats = mv88e6390_stats_get_stats, 3606 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3607 .set_egress_port = mv88e6390_g1_set_egress_port, 3608 .watchdog_ops = &mv88e6390_watchdog_ops, 3609 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3610 .pot_clear = mv88e6xxx_g2_pot_clear, 3611 .reset = mv88e6352_g1_reset, 3612 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3613 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3614 .serdes_power = mv88e6390_serdes_power, 3615 .serdes_get_lane = mv88e6341_serdes_get_lane, 3616 /* Check status register pause & lpa register */ 3617 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3618 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3619 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3620 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3621 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3622 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3623 .serdes_irq_status = mv88e6390_serdes_irq_status, 3624 .gpio_ops = &mv88e6352_gpio_ops, 3625 .phylink_validate = mv88e6341_phylink_validate, 3626 }; 3627 3628 static const struct mv88e6xxx_ops mv88e6161_ops = { 3629 /* MV88E6XXX_FAMILY_6165 */ 3630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3631 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3632 .irl_init_all = mv88e6352_g2_irl_init_all, 3633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3634 .phy_read = mv88e6xxx_g2_smi_phy_read, 3635 .phy_write = mv88e6xxx_g2_smi_phy_write, 3636 .port_set_link = mv88e6xxx_port_set_link, 3637 .port_sync_link = mv88e6xxx_port_sync_link, 3638 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3639 .port_tag_remap = mv88e6095_port_tag_remap, 3640 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3641 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3642 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3643 .port_set_ether_type = mv88e6351_port_set_ether_type, 3644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3646 .port_pause_limit = mv88e6097_port_pause_limit, 3647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3649 .port_get_cmode = mv88e6185_port_get_cmode, 3650 .port_setup_message_port = mv88e6xxx_setup_message_port, 3651 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3652 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3653 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3654 .stats_get_strings = mv88e6095_stats_get_strings, 3655 .stats_get_stats = mv88e6095_stats_get_stats, 3656 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3657 .set_egress_port = mv88e6095_g1_set_egress_port, 3658 .watchdog_ops = &mv88e6097_watchdog_ops, 3659 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3660 .pot_clear = mv88e6xxx_g2_pot_clear, 3661 .reset = mv88e6352_g1_reset, 3662 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3663 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3664 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3665 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3666 .avb_ops = &mv88e6165_avb_ops, 3667 .ptp_ops = &mv88e6165_ptp_ops, 3668 .phylink_validate = mv88e6185_phylink_validate, 3669 }; 3670 3671 static const struct mv88e6xxx_ops mv88e6165_ops = { 3672 /* MV88E6XXX_FAMILY_6165 */ 3673 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3674 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3675 .irl_init_all = mv88e6352_g2_irl_init_all, 3676 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3677 .phy_read = mv88e6165_phy_read, 3678 .phy_write = mv88e6165_phy_write, 3679 .port_set_link = mv88e6xxx_port_set_link, 3680 .port_sync_link = mv88e6xxx_port_sync_link, 3681 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3682 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3683 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3684 .port_get_cmode = mv88e6185_port_get_cmode, 3685 .port_setup_message_port = mv88e6xxx_setup_message_port, 3686 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3687 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3688 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3689 .stats_get_strings = mv88e6095_stats_get_strings, 3690 .stats_get_stats = mv88e6095_stats_get_stats, 3691 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3692 .set_egress_port = mv88e6095_g1_set_egress_port, 3693 .watchdog_ops = &mv88e6097_watchdog_ops, 3694 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3695 .pot_clear = mv88e6xxx_g2_pot_clear, 3696 .reset = mv88e6352_g1_reset, 3697 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3698 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3699 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3700 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3701 .avb_ops = &mv88e6165_avb_ops, 3702 .ptp_ops = &mv88e6165_ptp_ops, 3703 .phylink_validate = mv88e6185_phylink_validate, 3704 }; 3705 3706 static const struct mv88e6xxx_ops mv88e6171_ops = { 3707 /* MV88E6XXX_FAMILY_6351 */ 3708 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3709 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3710 .irl_init_all = mv88e6352_g2_irl_init_all, 3711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3712 .phy_read = mv88e6xxx_g2_smi_phy_read, 3713 .phy_write = mv88e6xxx_g2_smi_phy_write, 3714 .port_set_link = mv88e6xxx_port_set_link, 3715 .port_sync_link = mv88e6xxx_port_sync_link, 3716 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3717 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3718 .port_tag_remap = mv88e6095_port_tag_remap, 3719 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3720 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3721 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3722 .port_set_ether_type = mv88e6351_port_set_ether_type, 3723 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3724 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3725 .port_pause_limit = mv88e6097_port_pause_limit, 3726 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3727 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3728 .port_get_cmode = mv88e6352_port_get_cmode, 3729 .port_setup_message_port = mv88e6xxx_setup_message_port, 3730 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3731 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3732 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3733 .stats_get_strings = mv88e6095_stats_get_strings, 3734 .stats_get_stats = mv88e6095_stats_get_stats, 3735 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3736 .set_egress_port = mv88e6095_g1_set_egress_port, 3737 .watchdog_ops = &mv88e6097_watchdog_ops, 3738 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3739 .pot_clear = mv88e6xxx_g2_pot_clear, 3740 .reset = mv88e6352_g1_reset, 3741 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3742 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3743 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3744 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3745 .phylink_validate = mv88e6185_phylink_validate, 3746 }; 3747 3748 static const struct mv88e6xxx_ops mv88e6172_ops = { 3749 /* MV88E6XXX_FAMILY_6352 */ 3750 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3751 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3752 .irl_init_all = mv88e6352_g2_irl_init_all, 3753 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3754 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3755 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3756 .phy_read = mv88e6xxx_g2_smi_phy_read, 3757 .phy_write = mv88e6xxx_g2_smi_phy_write, 3758 .port_set_link = mv88e6xxx_port_set_link, 3759 .port_sync_link = mv88e6xxx_port_sync_link, 3760 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3761 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3762 .port_tag_remap = mv88e6095_port_tag_remap, 3763 .port_set_policy = mv88e6352_port_set_policy, 3764 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3765 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3766 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3767 .port_set_ether_type = mv88e6351_port_set_ether_type, 3768 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3769 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3770 .port_pause_limit = mv88e6097_port_pause_limit, 3771 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3772 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3773 .port_get_cmode = mv88e6352_port_get_cmode, 3774 .port_setup_message_port = mv88e6xxx_setup_message_port, 3775 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3776 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3777 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3778 .stats_get_strings = mv88e6095_stats_get_strings, 3779 .stats_get_stats = mv88e6095_stats_get_stats, 3780 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3781 .set_egress_port = mv88e6095_g1_set_egress_port, 3782 .watchdog_ops = &mv88e6097_watchdog_ops, 3783 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3784 .pot_clear = mv88e6xxx_g2_pot_clear, 3785 .reset = mv88e6352_g1_reset, 3786 .rmu_disable = mv88e6352_g1_rmu_disable, 3787 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3788 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3789 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3790 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3791 .serdes_get_lane = mv88e6352_serdes_get_lane, 3792 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3793 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3794 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3795 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3796 .serdes_power = mv88e6352_serdes_power, 3797 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3798 .serdes_get_regs = mv88e6352_serdes_get_regs, 3799 .gpio_ops = &mv88e6352_gpio_ops, 3800 .phylink_validate = mv88e6352_phylink_validate, 3801 }; 3802 3803 static const struct mv88e6xxx_ops mv88e6175_ops = { 3804 /* MV88E6XXX_FAMILY_6351 */ 3805 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3806 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3807 .irl_init_all = mv88e6352_g2_irl_init_all, 3808 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3809 .phy_read = mv88e6xxx_g2_smi_phy_read, 3810 .phy_write = mv88e6xxx_g2_smi_phy_write, 3811 .port_set_link = mv88e6xxx_port_set_link, 3812 .port_sync_link = mv88e6xxx_port_sync_link, 3813 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3814 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3815 .port_tag_remap = mv88e6095_port_tag_remap, 3816 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3817 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3818 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3819 .port_set_ether_type = mv88e6351_port_set_ether_type, 3820 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3821 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3822 .port_pause_limit = mv88e6097_port_pause_limit, 3823 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3824 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3825 .port_get_cmode = mv88e6352_port_get_cmode, 3826 .port_setup_message_port = mv88e6xxx_setup_message_port, 3827 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3828 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3829 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3830 .stats_get_strings = mv88e6095_stats_get_strings, 3831 .stats_get_stats = mv88e6095_stats_get_stats, 3832 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3833 .set_egress_port = mv88e6095_g1_set_egress_port, 3834 .watchdog_ops = &mv88e6097_watchdog_ops, 3835 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3836 .pot_clear = mv88e6xxx_g2_pot_clear, 3837 .reset = mv88e6352_g1_reset, 3838 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3839 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3840 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3841 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3842 .phylink_validate = mv88e6185_phylink_validate, 3843 }; 3844 3845 static const struct mv88e6xxx_ops mv88e6176_ops = { 3846 /* MV88E6XXX_FAMILY_6352 */ 3847 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3848 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3849 .irl_init_all = mv88e6352_g2_irl_init_all, 3850 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3851 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3852 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3853 .phy_read = mv88e6xxx_g2_smi_phy_read, 3854 .phy_write = mv88e6xxx_g2_smi_phy_write, 3855 .port_set_link = mv88e6xxx_port_set_link, 3856 .port_sync_link = mv88e6xxx_port_sync_link, 3857 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3858 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3859 .port_tag_remap = mv88e6095_port_tag_remap, 3860 .port_set_policy = mv88e6352_port_set_policy, 3861 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3862 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3863 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3864 .port_set_ether_type = mv88e6351_port_set_ether_type, 3865 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3866 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3867 .port_pause_limit = mv88e6097_port_pause_limit, 3868 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3869 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3870 .port_get_cmode = mv88e6352_port_get_cmode, 3871 .port_setup_message_port = mv88e6xxx_setup_message_port, 3872 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3873 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3874 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3875 .stats_get_strings = mv88e6095_stats_get_strings, 3876 .stats_get_stats = mv88e6095_stats_get_stats, 3877 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3878 .set_egress_port = mv88e6095_g1_set_egress_port, 3879 .watchdog_ops = &mv88e6097_watchdog_ops, 3880 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3881 .pot_clear = mv88e6xxx_g2_pot_clear, 3882 .reset = mv88e6352_g1_reset, 3883 .rmu_disable = mv88e6352_g1_rmu_disable, 3884 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3885 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3886 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3887 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3888 .serdes_get_lane = mv88e6352_serdes_get_lane, 3889 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3890 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3891 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3892 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3893 .serdes_power = mv88e6352_serdes_power, 3894 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3895 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3896 .serdes_irq_status = mv88e6352_serdes_irq_status, 3897 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3898 .serdes_get_regs = mv88e6352_serdes_get_regs, 3899 .gpio_ops = &mv88e6352_gpio_ops, 3900 .phylink_validate = mv88e6352_phylink_validate, 3901 }; 3902 3903 static const struct mv88e6xxx_ops mv88e6185_ops = { 3904 /* MV88E6XXX_FAMILY_6185 */ 3905 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3906 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3907 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3908 .phy_read = mv88e6185_phy_ppu_read, 3909 .phy_write = mv88e6185_phy_ppu_write, 3910 .port_set_link = mv88e6xxx_port_set_link, 3911 .port_sync_link = mv88e6185_port_sync_link, 3912 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3913 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3914 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3915 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3916 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3917 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3918 .port_set_pause = mv88e6185_port_set_pause, 3919 .port_get_cmode = mv88e6185_port_get_cmode, 3920 .port_setup_message_port = mv88e6xxx_setup_message_port, 3921 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3922 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3923 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3924 .stats_get_strings = mv88e6095_stats_get_strings, 3925 .stats_get_stats = mv88e6095_stats_get_stats, 3926 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3927 .set_egress_port = mv88e6095_g1_set_egress_port, 3928 .watchdog_ops = &mv88e6097_watchdog_ops, 3929 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3930 .serdes_power = mv88e6185_serdes_power, 3931 .serdes_get_lane = mv88e6185_serdes_get_lane, 3932 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3933 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3934 .ppu_enable = mv88e6185_g1_ppu_enable, 3935 .ppu_disable = mv88e6185_g1_ppu_disable, 3936 .reset = mv88e6185_g1_reset, 3937 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3938 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3939 .phylink_validate = mv88e6185_phylink_validate, 3940 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3941 }; 3942 3943 static const struct mv88e6xxx_ops mv88e6190_ops = { 3944 /* MV88E6XXX_FAMILY_6390 */ 3945 .setup_errata = mv88e6390_setup_errata, 3946 .irl_init_all = mv88e6390_g2_irl_init_all, 3947 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3948 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3949 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3950 .phy_read = mv88e6xxx_g2_smi_phy_read, 3951 .phy_write = mv88e6xxx_g2_smi_phy_write, 3952 .port_set_link = mv88e6xxx_port_set_link, 3953 .port_sync_link = mv88e6xxx_port_sync_link, 3954 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3955 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3956 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3957 .port_tag_remap = mv88e6390_port_tag_remap, 3958 .port_set_policy = mv88e6352_port_set_policy, 3959 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3960 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3961 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3962 .port_set_ether_type = mv88e6351_port_set_ether_type, 3963 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3964 .port_pause_limit = mv88e6390_port_pause_limit, 3965 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3966 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3967 .port_get_cmode = mv88e6352_port_get_cmode, 3968 .port_set_cmode = mv88e6390_port_set_cmode, 3969 .port_setup_message_port = mv88e6xxx_setup_message_port, 3970 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3971 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3972 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3973 .stats_get_strings = mv88e6320_stats_get_strings, 3974 .stats_get_stats = mv88e6390_stats_get_stats, 3975 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3976 .set_egress_port = mv88e6390_g1_set_egress_port, 3977 .watchdog_ops = &mv88e6390_watchdog_ops, 3978 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3979 .pot_clear = mv88e6xxx_g2_pot_clear, 3980 .reset = mv88e6352_g1_reset, 3981 .rmu_disable = mv88e6390_g1_rmu_disable, 3982 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3983 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3984 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3985 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3986 .serdes_power = mv88e6390_serdes_power, 3987 .serdes_get_lane = mv88e6390_serdes_get_lane, 3988 /* Check status register pause & lpa register */ 3989 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3990 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3991 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3992 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3993 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3994 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3995 .serdes_irq_status = mv88e6390_serdes_irq_status, 3996 .serdes_get_strings = mv88e6390_serdes_get_strings, 3997 .serdes_get_stats = mv88e6390_serdes_get_stats, 3998 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3999 .serdes_get_regs = mv88e6390_serdes_get_regs, 4000 .gpio_ops = &mv88e6352_gpio_ops, 4001 .phylink_validate = mv88e6390_phylink_validate, 4002 }; 4003 4004 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4005 /* MV88E6XXX_FAMILY_6390 */ 4006 .setup_errata = mv88e6390_setup_errata, 4007 .irl_init_all = mv88e6390_g2_irl_init_all, 4008 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4009 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4010 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4011 .phy_read = mv88e6xxx_g2_smi_phy_read, 4012 .phy_write = mv88e6xxx_g2_smi_phy_write, 4013 .port_set_link = mv88e6xxx_port_set_link, 4014 .port_sync_link = mv88e6xxx_port_sync_link, 4015 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4016 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4017 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4018 .port_tag_remap = mv88e6390_port_tag_remap, 4019 .port_set_policy = mv88e6352_port_set_policy, 4020 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4021 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4022 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4023 .port_set_ether_type = mv88e6351_port_set_ether_type, 4024 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4025 .port_pause_limit = mv88e6390_port_pause_limit, 4026 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4027 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4028 .port_get_cmode = mv88e6352_port_get_cmode, 4029 .port_set_cmode = mv88e6390x_port_set_cmode, 4030 .port_setup_message_port = mv88e6xxx_setup_message_port, 4031 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4032 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4033 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4034 .stats_get_strings = mv88e6320_stats_get_strings, 4035 .stats_get_stats = mv88e6390_stats_get_stats, 4036 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4037 .set_egress_port = mv88e6390_g1_set_egress_port, 4038 .watchdog_ops = &mv88e6390_watchdog_ops, 4039 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4040 .pot_clear = mv88e6xxx_g2_pot_clear, 4041 .reset = mv88e6352_g1_reset, 4042 .rmu_disable = mv88e6390_g1_rmu_disable, 4043 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4044 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4045 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4046 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4047 .serdes_power = mv88e6390_serdes_power, 4048 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4049 /* Check status register pause & lpa register */ 4050 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4051 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4052 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4053 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4054 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4055 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4056 .serdes_irq_status = mv88e6390_serdes_irq_status, 4057 .serdes_get_strings = mv88e6390_serdes_get_strings, 4058 .serdes_get_stats = mv88e6390_serdes_get_stats, 4059 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4060 .serdes_get_regs = mv88e6390_serdes_get_regs, 4061 .gpio_ops = &mv88e6352_gpio_ops, 4062 .phylink_validate = mv88e6390x_phylink_validate, 4063 }; 4064 4065 static const struct mv88e6xxx_ops mv88e6191_ops = { 4066 /* MV88E6XXX_FAMILY_6390 */ 4067 .setup_errata = mv88e6390_setup_errata, 4068 .irl_init_all = mv88e6390_g2_irl_init_all, 4069 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4070 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4071 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4072 .phy_read = mv88e6xxx_g2_smi_phy_read, 4073 .phy_write = mv88e6xxx_g2_smi_phy_write, 4074 .port_set_link = mv88e6xxx_port_set_link, 4075 .port_sync_link = mv88e6xxx_port_sync_link, 4076 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4077 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4078 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4079 .port_tag_remap = mv88e6390_port_tag_remap, 4080 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4081 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4082 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4083 .port_set_ether_type = mv88e6351_port_set_ether_type, 4084 .port_pause_limit = mv88e6390_port_pause_limit, 4085 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4086 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4087 .port_get_cmode = mv88e6352_port_get_cmode, 4088 .port_set_cmode = mv88e6390_port_set_cmode, 4089 .port_setup_message_port = mv88e6xxx_setup_message_port, 4090 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4091 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4092 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4093 .stats_get_strings = mv88e6320_stats_get_strings, 4094 .stats_get_stats = mv88e6390_stats_get_stats, 4095 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4096 .set_egress_port = mv88e6390_g1_set_egress_port, 4097 .watchdog_ops = &mv88e6390_watchdog_ops, 4098 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4099 .pot_clear = mv88e6xxx_g2_pot_clear, 4100 .reset = mv88e6352_g1_reset, 4101 .rmu_disable = mv88e6390_g1_rmu_disable, 4102 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4103 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4104 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4105 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4106 .serdes_power = mv88e6390_serdes_power, 4107 .serdes_get_lane = mv88e6390_serdes_get_lane, 4108 /* Check status register pause & lpa register */ 4109 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4110 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4111 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4112 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4113 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4114 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4115 .serdes_irq_status = mv88e6390_serdes_irq_status, 4116 .serdes_get_strings = mv88e6390_serdes_get_strings, 4117 .serdes_get_stats = mv88e6390_serdes_get_stats, 4118 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4119 .serdes_get_regs = mv88e6390_serdes_get_regs, 4120 .avb_ops = &mv88e6390_avb_ops, 4121 .ptp_ops = &mv88e6352_ptp_ops, 4122 .phylink_validate = mv88e6390_phylink_validate, 4123 }; 4124 4125 static const struct mv88e6xxx_ops mv88e6240_ops = { 4126 /* MV88E6XXX_FAMILY_6352 */ 4127 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4128 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4129 .irl_init_all = mv88e6352_g2_irl_init_all, 4130 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4131 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4132 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4133 .phy_read = mv88e6xxx_g2_smi_phy_read, 4134 .phy_write = mv88e6xxx_g2_smi_phy_write, 4135 .port_set_link = mv88e6xxx_port_set_link, 4136 .port_sync_link = mv88e6xxx_port_sync_link, 4137 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4138 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4139 .port_tag_remap = mv88e6095_port_tag_remap, 4140 .port_set_policy = mv88e6352_port_set_policy, 4141 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4142 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4143 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4144 .port_set_ether_type = mv88e6351_port_set_ether_type, 4145 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4147 .port_pause_limit = mv88e6097_port_pause_limit, 4148 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4149 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4150 .port_get_cmode = mv88e6352_port_get_cmode, 4151 .port_setup_message_port = mv88e6xxx_setup_message_port, 4152 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4153 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4154 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4155 .stats_get_strings = mv88e6095_stats_get_strings, 4156 .stats_get_stats = mv88e6095_stats_get_stats, 4157 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4158 .set_egress_port = mv88e6095_g1_set_egress_port, 4159 .watchdog_ops = &mv88e6097_watchdog_ops, 4160 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4161 .pot_clear = mv88e6xxx_g2_pot_clear, 4162 .reset = mv88e6352_g1_reset, 4163 .rmu_disable = mv88e6352_g1_rmu_disable, 4164 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4165 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4166 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4167 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4168 .serdes_get_lane = mv88e6352_serdes_get_lane, 4169 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4170 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4171 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4172 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4173 .serdes_power = mv88e6352_serdes_power, 4174 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4175 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4176 .serdes_irq_status = mv88e6352_serdes_irq_status, 4177 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4178 .serdes_get_regs = mv88e6352_serdes_get_regs, 4179 .gpio_ops = &mv88e6352_gpio_ops, 4180 .avb_ops = &mv88e6352_avb_ops, 4181 .ptp_ops = &mv88e6352_ptp_ops, 4182 .phylink_validate = mv88e6352_phylink_validate, 4183 }; 4184 4185 static const struct mv88e6xxx_ops mv88e6250_ops = { 4186 /* MV88E6XXX_FAMILY_6250 */ 4187 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4188 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4189 .irl_init_all = mv88e6352_g2_irl_init_all, 4190 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4191 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4192 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4193 .phy_read = mv88e6xxx_g2_smi_phy_read, 4194 .phy_write = mv88e6xxx_g2_smi_phy_write, 4195 .port_set_link = mv88e6xxx_port_set_link, 4196 .port_sync_link = mv88e6xxx_port_sync_link, 4197 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4198 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4199 .port_tag_remap = mv88e6095_port_tag_remap, 4200 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4201 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4202 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4203 .port_set_ether_type = mv88e6351_port_set_ether_type, 4204 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4205 .port_pause_limit = mv88e6097_port_pause_limit, 4206 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4207 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4208 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4209 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4210 .stats_get_strings = mv88e6250_stats_get_strings, 4211 .stats_get_stats = mv88e6250_stats_get_stats, 4212 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4213 .set_egress_port = mv88e6095_g1_set_egress_port, 4214 .watchdog_ops = &mv88e6250_watchdog_ops, 4215 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4216 .pot_clear = mv88e6xxx_g2_pot_clear, 4217 .reset = mv88e6250_g1_reset, 4218 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4219 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4220 .avb_ops = &mv88e6352_avb_ops, 4221 .ptp_ops = &mv88e6250_ptp_ops, 4222 .phylink_validate = mv88e6065_phylink_validate, 4223 }; 4224 4225 static const struct mv88e6xxx_ops mv88e6290_ops = { 4226 /* MV88E6XXX_FAMILY_6390 */ 4227 .setup_errata = mv88e6390_setup_errata, 4228 .irl_init_all = mv88e6390_g2_irl_init_all, 4229 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4230 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4231 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4232 .phy_read = mv88e6xxx_g2_smi_phy_read, 4233 .phy_write = mv88e6xxx_g2_smi_phy_write, 4234 .port_set_link = mv88e6xxx_port_set_link, 4235 .port_sync_link = mv88e6xxx_port_sync_link, 4236 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4237 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4238 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4239 .port_tag_remap = mv88e6390_port_tag_remap, 4240 .port_set_policy = mv88e6352_port_set_policy, 4241 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4242 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4243 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4244 .port_set_ether_type = mv88e6351_port_set_ether_type, 4245 .port_pause_limit = mv88e6390_port_pause_limit, 4246 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4247 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4248 .port_get_cmode = mv88e6352_port_get_cmode, 4249 .port_set_cmode = mv88e6390_port_set_cmode, 4250 .port_setup_message_port = mv88e6xxx_setup_message_port, 4251 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4252 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4253 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4254 .stats_get_strings = mv88e6320_stats_get_strings, 4255 .stats_get_stats = mv88e6390_stats_get_stats, 4256 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4257 .set_egress_port = mv88e6390_g1_set_egress_port, 4258 .watchdog_ops = &mv88e6390_watchdog_ops, 4259 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4260 .pot_clear = mv88e6xxx_g2_pot_clear, 4261 .reset = mv88e6352_g1_reset, 4262 .rmu_disable = mv88e6390_g1_rmu_disable, 4263 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4264 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4265 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4266 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4267 .serdes_power = mv88e6390_serdes_power, 4268 .serdes_get_lane = mv88e6390_serdes_get_lane, 4269 /* Check status register pause & lpa register */ 4270 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4271 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4272 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4273 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4274 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4275 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4276 .serdes_irq_status = mv88e6390_serdes_irq_status, 4277 .serdes_get_strings = mv88e6390_serdes_get_strings, 4278 .serdes_get_stats = mv88e6390_serdes_get_stats, 4279 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4280 .serdes_get_regs = mv88e6390_serdes_get_regs, 4281 .gpio_ops = &mv88e6352_gpio_ops, 4282 .avb_ops = &mv88e6390_avb_ops, 4283 .ptp_ops = &mv88e6352_ptp_ops, 4284 .phylink_validate = mv88e6390_phylink_validate, 4285 }; 4286 4287 static const struct mv88e6xxx_ops mv88e6320_ops = { 4288 /* MV88E6XXX_FAMILY_6320 */ 4289 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4290 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4291 .irl_init_all = mv88e6352_g2_irl_init_all, 4292 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4293 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4295 .phy_read = mv88e6xxx_g2_smi_phy_read, 4296 .phy_write = mv88e6xxx_g2_smi_phy_write, 4297 .port_set_link = mv88e6xxx_port_set_link, 4298 .port_sync_link = mv88e6xxx_port_sync_link, 4299 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4300 .port_tag_remap = mv88e6095_port_tag_remap, 4301 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4302 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4303 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4304 .port_set_ether_type = mv88e6351_port_set_ether_type, 4305 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4307 .port_pause_limit = mv88e6097_port_pause_limit, 4308 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4309 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4310 .port_get_cmode = mv88e6352_port_get_cmode, 4311 .port_setup_message_port = mv88e6xxx_setup_message_port, 4312 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4313 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4314 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4315 .stats_get_strings = mv88e6320_stats_get_strings, 4316 .stats_get_stats = mv88e6320_stats_get_stats, 4317 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4318 .set_egress_port = mv88e6095_g1_set_egress_port, 4319 .watchdog_ops = &mv88e6390_watchdog_ops, 4320 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4321 .pot_clear = mv88e6xxx_g2_pot_clear, 4322 .reset = mv88e6352_g1_reset, 4323 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4324 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4325 .gpio_ops = &mv88e6352_gpio_ops, 4326 .avb_ops = &mv88e6352_avb_ops, 4327 .ptp_ops = &mv88e6352_ptp_ops, 4328 .phylink_validate = mv88e6185_phylink_validate, 4329 }; 4330 4331 static const struct mv88e6xxx_ops mv88e6321_ops = { 4332 /* MV88E6XXX_FAMILY_6320 */ 4333 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4334 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4335 .irl_init_all = mv88e6352_g2_irl_init_all, 4336 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4337 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4338 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4339 .phy_read = mv88e6xxx_g2_smi_phy_read, 4340 .phy_write = mv88e6xxx_g2_smi_phy_write, 4341 .port_set_link = mv88e6xxx_port_set_link, 4342 .port_sync_link = mv88e6xxx_port_sync_link, 4343 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4344 .port_tag_remap = mv88e6095_port_tag_remap, 4345 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4346 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4347 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4348 .port_set_ether_type = mv88e6351_port_set_ether_type, 4349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4351 .port_pause_limit = mv88e6097_port_pause_limit, 4352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4354 .port_get_cmode = mv88e6352_port_get_cmode, 4355 .port_setup_message_port = mv88e6xxx_setup_message_port, 4356 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4357 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4358 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4359 .stats_get_strings = mv88e6320_stats_get_strings, 4360 .stats_get_stats = mv88e6320_stats_get_stats, 4361 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4362 .set_egress_port = mv88e6095_g1_set_egress_port, 4363 .watchdog_ops = &mv88e6390_watchdog_ops, 4364 .reset = mv88e6352_g1_reset, 4365 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4366 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4367 .gpio_ops = &mv88e6352_gpio_ops, 4368 .avb_ops = &mv88e6352_avb_ops, 4369 .ptp_ops = &mv88e6352_ptp_ops, 4370 .phylink_validate = mv88e6185_phylink_validate, 4371 }; 4372 4373 static const struct mv88e6xxx_ops mv88e6341_ops = { 4374 /* MV88E6XXX_FAMILY_6341 */ 4375 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4376 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4377 .irl_init_all = mv88e6352_g2_irl_init_all, 4378 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4379 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4381 .phy_read = mv88e6xxx_g2_smi_phy_read, 4382 .phy_write = mv88e6xxx_g2_smi_phy_write, 4383 .port_set_link = mv88e6xxx_port_set_link, 4384 .port_sync_link = mv88e6xxx_port_sync_link, 4385 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4386 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4387 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4388 .port_tag_remap = mv88e6095_port_tag_remap, 4389 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4390 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4391 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4392 .port_set_ether_type = mv88e6351_port_set_ether_type, 4393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4395 .port_pause_limit = mv88e6097_port_pause_limit, 4396 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4397 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4398 .port_get_cmode = mv88e6352_port_get_cmode, 4399 .port_set_cmode = mv88e6341_port_set_cmode, 4400 .port_setup_message_port = mv88e6xxx_setup_message_port, 4401 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4402 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4403 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4404 .stats_get_strings = mv88e6320_stats_get_strings, 4405 .stats_get_stats = mv88e6390_stats_get_stats, 4406 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4407 .set_egress_port = mv88e6390_g1_set_egress_port, 4408 .watchdog_ops = &mv88e6390_watchdog_ops, 4409 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4410 .pot_clear = mv88e6xxx_g2_pot_clear, 4411 .reset = mv88e6352_g1_reset, 4412 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4413 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4414 .serdes_power = mv88e6390_serdes_power, 4415 .serdes_get_lane = mv88e6341_serdes_get_lane, 4416 /* Check status register pause & lpa register */ 4417 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4418 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4419 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4420 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4421 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4422 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4423 .serdes_irq_status = mv88e6390_serdes_irq_status, 4424 .gpio_ops = &mv88e6352_gpio_ops, 4425 .avb_ops = &mv88e6390_avb_ops, 4426 .ptp_ops = &mv88e6352_ptp_ops, 4427 .phylink_validate = mv88e6341_phylink_validate, 4428 }; 4429 4430 static const struct mv88e6xxx_ops mv88e6350_ops = { 4431 /* MV88E6XXX_FAMILY_6351 */ 4432 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4433 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4434 .irl_init_all = mv88e6352_g2_irl_init_all, 4435 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4436 .phy_read = mv88e6xxx_g2_smi_phy_read, 4437 .phy_write = mv88e6xxx_g2_smi_phy_write, 4438 .port_set_link = mv88e6xxx_port_set_link, 4439 .port_sync_link = mv88e6xxx_port_sync_link, 4440 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4441 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4442 .port_tag_remap = mv88e6095_port_tag_remap, 4443 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4444 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4445 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4446 .port_set_ether_type = mv88e6351_port_set_ether_type, 4447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4449 .port_pause_limit = mv88e6097_port_pause_limit, 4450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4452 .port_get_cmode = mv88e6352_port_get_cmode, 4453 .port_setup_message_port = mv88e6xxx_setup_message_port, 4454 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4455 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4456 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4457 .stats_get_strings = mv88e6095_stats_get_strings, 4458 .stats_get_stats = mv88e6095_stats_get_stats, 4459 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4460 .set_egress_port = mv88e6095_g1_set_egress_port, 4461 .watchdog_ops = &mv88e6097_watchdog_ops, 4462 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4463 .pot_clear = mv88e6xxx_g2_pot_clear, 4464 .reset = mv88e6352_g1_reset, 4465 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4466 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4467 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4468 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4469 .phylink_validate = mv88e6185_phylink_validate, 4470 }; 4471 4472 static const struct mv88e6xxx_ops mv88e6351_ops = { 4473 /* MV88E6XXX_FAMILY_6351 */ 4474 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4475 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4476 .irl_init_all = mv88e6352_g2_irl_init_all, 4477 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4478 .phy_read = mv88e6xxx_g2_smi_phy_read, 4479 .phy_write = mv88e6xxx_g2_smi_phy_write, 4480 .port_set_link = mv88e6xxx_port_set_link, 4481 .port_sync_link = mv88e6xxx_port_sync_link, 4482 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4483 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4484 .port_tag_remap = mv88e6095_port_tag_remap, 4485 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4486 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4487 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4488 .port_set_ether_type = mv88e6351_port_set_ether_type, 4489 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4491 .port_pause_limit = mv88e6097_port_pause_limit, 4492 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4493 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4494 .port_get_cmode = mv88e6352_port_get_cmode, 4495 .port_setup_message_port = mv88e6xxx_setup_message_port, 4496 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4497 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4498 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4499 .stats_get_strings = mv88e6095_stats_get_strings, 4500 .stats_get_stats = mv88e6095_stats_get_stats, 4501 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4502 .set_egress_port = mv88e6095_g1_set_egress_port, 4503 .watchdog_ops = &mv88e6097_watchdog_ops, 4504 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4505 .pot_clear = mv88e6xxx_g2_pot_clear, 4506 .reset = mv88e6352_g1_reset, 4507 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4508 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4509 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4510 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4511 .avb_ops = &mv88e6352_avb_ops, 4512 .ptp_ops = &mv88e6352_ptp_ops, 4513 .phylink_validate = mv88e6185_phylink_validate, 4514 }; 4515 4516 static const struct mv88e6xxx_ops mv88e6352_ops = { 4517 /* MV88E6XXX_FAMILY_6352 */ 4518 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4519 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4520 .irl_init_all = mv88e6352_g2_irl_init_all, 4521 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4522 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4523 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4524 .phy_read = mv88e6xxx_g2_smi_phy_read, 4525 .phy_write = mv88e6xxx_g2_smi_phy_write, 4526 .port_set_link = mv88e6xxx_port_set_link, 4527 .port_sync_link = mv88e6xxx_port_sync_link, 4528 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4529 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4530 .port_tag_remap = mv88e6095_port_tag_remap, 4531 .port_set_policy = mv88e6352_port_set_policy, 4532 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4533 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4534 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4535 .port_set_ether_type = mv88e6351_port_set_ether_type, 4536 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4537 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4538 .port_pause_limit = mv88e6097_port_pause_limit, 4539 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4540 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4541 .port_get_cmode = mv88e6352_port_get_cmode, 4542 .port_setup_message_port = mv88e6xxx_setup_message_port, 4543 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4544 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4545 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4546 .stats_get_strings = mv88e6095_stats_get_strings, 4547 .stats_get_stats = mv88e6095_stats_get_stats, 4548 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4549 .set_egress_port = mv88e6095_g1_set_egress_port, 4550 .watchdog_ops = &mv88e6097_watchdog_ops, 4551 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4552 .pot_clear = mv88e6xxx_g2_pot_clear, 4553 .reset = mv88e6352_g1_reset, 4554 .rmu_disable = mv88e6352_g1_rmu_disable, 4555 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4556 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4557 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4558 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4559 .serdes_get_lane = mv88e6352_serdes_get_lane, 4560 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4561 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4562 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4563 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4564 .serdes_power = mv88e6352_serdes_power, 4565 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4566 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4567 .serdes_irq_status = mv88e6352_serdes_irq_status, 4568 .gpio_ops = &mv88e6352_gpio_ops, 4569 .avb_ops = &mv88e6352_avb_ops, 4570 .ptp_ops = &mv88e6352_ptp_ops, 4571 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4572 .serdes_get_strings = mv88e6352_serdes_get_strings, 4573 .serdes_get_stats = mv88e6352_serdes_get_stats, 4574 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4575 .serdes_get_regs = mv88e6352_serdes_get_regs, 4576 .phylink_validate = mv88e6352_phylink_validate, 4577 }; 4578 4579 static const struct mv88e6xxx_ops mv88e6390_ops = { 4580 /* MV88E6XXX_FAMILY_6390 */ 4581 .setup_errata = mv88e6390_setup_errata, 4582 .irl_init_all = mv88e6390_g2_irl_init_all, 4583 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4584 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4585 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4586 .phy_read = mv88e6xxx_g2_smi_phy_read, 4587 .phy_write = mv88e6xxx_g2_smi_phy_write, 4588 .port_set_link = mv88e6xxx_port_set_link, 4589 .port_sync_link = mv88e6xxx_port_sync_link, 4590 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4591 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4592 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4593 .port_tag_remap = mv88e6390_port_tag_remap, 4594 .port_set_policy = mv88e6352_port_set_policy, 4595 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4596 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4597 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4598 .port_set_ether_type = mv88e6351_port_set_ether_type, 4599 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4600 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4601 .port_pause_limit = mv88e6390_port_pause_limit, 4602 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4603 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4604 .port_get_cmode = mv88e6352_port_get_cmode, 4605 .port_set_cmode = mv88e6390_port_set_cmode, 4606 .port_setup_message_port = mv88e6xxx_setup_message_port, 4607 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4608 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4609 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4610 .stats_get_strings = mv88e6320_stats_get_strings, 4611 .stats_get_stats = mv88e6390_stats_get_stats, 4612 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4613 .set_egress_port = mv88e6390_g1_set_egress_port, 4614 .watchdog_ops = &mv88e6390_watchdog_ops, 4615 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4616 .pot_clear = mv88e6xxx_g2_pot_clear, 4617 .reset = mv88e6352_g1_reset, 4618 .rmu_disable = mv88e6390_g1_rmu_disable, 4619 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4620 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4621 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4622 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4623 .serdes_power = mv88e6390_serdes_power, 4624 .serdes_get_lane = mv88e6390_serdes_get_lane, 4625 /* Check status register pause & lpa register */ 4626 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4627 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4628 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4629 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4630 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4631 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4632 .serdes_irq_status = mv88e6390_serdes_irq_status, 4633 .gpio_ops = &mv88e6352_gpio_ops, 4634 .avb_ops = &mv88e6390_avb_ops, 4635 .ptp_ops = &mv88e6352_ptp_ops, 4636 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4637 .serdes_get_strings = mv88e6390_serdes_get_strings, 4638 .serdes_get_stats = mv88e6390_serdes_get_stats, 4639 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4640 .serdes_get_regs = mv88e6390_serdes_get_regs, 4641 .phylink_validate = mv88e6390_phylink_validate, 4642 }; 4643 4644 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4645 /* MV88E6XXX_FAMILY_6390 */ 4646 .setup_errata = mv88e6390_setup_errata, 4647 .irl_init_all = mv88e6390_g2_irl_init_all, 4648 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4649 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4650 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4651 .phy_read = mv88e6xxx_g2_smi_phy_read, 4652 .phy_write = mv88e6xxx_g2_smi_phy_write, 4653 .port_set_link = mv88e6xxx_port_set_link, 4654 .port_sync_link = mv88e6xxx_port_sync_link, 4655 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4656 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4657 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4658 .port_tag_remap = mv88e6390_port_tag_remap, 4659 .port_set_policy = mv88e6352_port_set_policy, 4660 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4661 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4662 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4663 .port_set_ether_type = mv88e6351_port_set_ether_type, 4664 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4665 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4666 .port_pause_limit = mv88e6390_port_pause_limit, 4667 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4668 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4669 .port_get_cmode = mv88e6352_port_get_cmode, 4670 .port_set_cmode = mv88e6390x_port_set_cmode, 4671 .port_setup_message_port = mv88e6xxx_setup_message_port, 4672 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4673 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4674 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4675 .stats_get_strings = mv88e6320_stats_get_strings, 4676 .stats_get_stats = mv88e6390_stats_get_stats, 4677 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4678 .set_egress_port = mv88e6390_g1_set_egress_port, 4679 .watchdog_ops = &mv88e6390_watchdog_ops, 4680 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4681 .pot_clear = mv88e6xxx_g2_pot_clear, 4682 .reset = mv88e6352_g1_reset, 4683 .rmu_disable = mv88e6390_g1_rmu_disable, 4684 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4685 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4686 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4687 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4688 .serdes_power = mv88e6390_serdes_power, 4689 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4690 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4691 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4692 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4693 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4694 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4695 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4696 .serdes_irq_status = mv88e6390_serdes_irq_status, 4697 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4698 .serdes_get_strings = mv88e6390_serdes_get_strings, 4699 .serdes_get_stats = mv88e6390_serdes_get_stats, 4700 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4701 .serdes_get_regs = mv88e6390_serdes_get_regs, 4702 .gpio_ops = &mv88e6352_gpio_ops, 4703 .avb_ops = &mv88e6390_avb_ops, 4704 .ptp_ops = &mv88e6352_ptp_ops, 4705 .phylink_validate = mv88e6390x_phylink_validate, 4706 }; 4707 4708 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4709 /* MV88E6XXX_FAMILY_6393 */ 4710 .setup_errata = mv88e6393x_serdes_setup_errata, 4711 .irl_init_all = mv88e6390_g2_irl_init_all, 4712 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4713 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4714 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4715 .phy_read = mv88e6xxx_g2_smi_phy_read, 4716 .phy_write = mv88e6xxx_g2_smi_phy_write, 4717 .port_set_link = mv88e6xxx_port_set_link, 4718 .port_sync_link = mv88e6xxx_port_sync_link, 4719 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4720 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4721 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4722 .port_tag_remap = mv88e6390_port_tag_remap, 4723 .port_set_policy = mv88e6393x_port_set_policy, 4724 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4725 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4726 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4727 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4728 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4729 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4730 .port_pause_limit = mv88e6390_port_pause_limit, 4731 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4732 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4733 .port_get_cmode = mv88e6352_port_get_cmode, 4734 .port_set_cmode = mv88e6393x_port_set_cmode, 4735 .port_setup_message_port = mv88e6xxx_setup_message_port, 4736 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4737 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4738 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4739 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4740 .stats_get_strings = mv88e6320_stats_get_strings, 4741 .stats_get_stats = mv88e6390_stats_get_stats, 4742 /* .set_cpu_port is missing because this family does not support a global 4743 * CPU port, only per port CPU port which is set via 4744 * .port_set_upstream_port method. 4745 */ 4746 .set_egress_port = mv88e6393x_set_egress_port, 4747 .watchdog_ops = &mv88e6390_watchdog_ops, 4748 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4749 .pot_clear = mv88e6xxx_g2_pot_clear, 4750 .reset = mv88e6352_g1_reset, 4751 .rmu_disable = mv88e6390_g1_rmu_disable, 4752 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4753 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4754 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4755 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4756 .serdes_power = mv88e6393x_serdes_power, 4757 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4758 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4759 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4760 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4761 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4762 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4763 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4764 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4765 /* TODO: serdes stats */ 4766 .gpio_ops = &mv88e6352_gpio_ops, 4767 .avb_ops = &mv88e6390_avb_ops, 4768 .ptp_ops = &mv88e6352_ptp_ops, 4769 .phylink_validate = mv88e6393x_phylink_validate, 4770 }; 4771 4772 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4773 [MV88E6085] = { 4774 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4775 .family = MV88E6XXX_FAMILY_6097, 4776 .name = "Marvell 88E6085", 4777 .num_databases = 4096, 4778 .num_macs = 8192, 4779 .num_ports = 10, 4780 .num_internal_phys = 5, 4781 .max_vid = 4095, 4782 .port_base_addr = 0x10, 4783 .phy_base_addr = 0x0, 4784 .global1_addr = 0x1b, 4785 .global2_addr = 0x1c, 4786 .age_time_coeff = 15000, 4787 .g1_irqs = 8, 4788 .g2_irqs = 10, 4789 .atu_move_port_mask = 0xf, 4790 .pvt = true, 4791 .multi_chip = true, 4792 .tag_protocol = DSA_TAG_PROTO_DSA, 4793 .ops = &mv88e6085_ops, 4794 }, 4795 4796 [MV88E6095] = { 4797 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4798 .family = MV88E6XXX_FAMILY_6095, 4799 .name = "Marvell 88E6095/88E6095F", 4800 .num_databases = 256, 4801 .num_macs = 8192, 4802 .num_ports = 11, 4803 .num_internal_phys = 0, 4804 .max_vid = 4095, 4805 .port_base_addr = 0x10, 4806 .phy_base_addr = 0x0, 4807 .global1_addr = 0x1b, 4808 .global2_addr = 0x1c, 4809 .age_time_coeff = 15000, 4810 .g1_irqs = 8, 4811 .atu_move_port_mask = 0xf, 4812 .multi_chip = true, 4813 .tag_protocol = DSA_TAG_PROTO_DSA, 4814 .ops = &mv88e6095_ops, 4815 }, 4816 4817 [MV88E6097] = { 4818 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4819 .family = MV88E6XXX_FAMILY_6097, 4820 .name = "Marvell 88E6097/88E6097F", 4821 .num_databases = 4096, 4822 .num_macs = 8192, 4823 .num_ports = 11, 4824 .num_internal_phys = 8, 4825 .max_vid = 4095, 4826 .port_base_addr = 0x10, 4827 .phy_base_addr = 0x0, 4828 .global1_addr = 0x1b, 4829 .global2_addr = 0x1c, 4830 .age_time_coeff = 15000, 4831 .g1_irqs = 8, 4832 .g2_irqs = 10, 4833 .atu_move_port_mask = 0xf, 4834 .pvt = true, 4835 .multi_chip = true, 4836 .tag_protocol = DSA_TAG_PROTO_EDSA, 4837 .ops = &mv88e6097_ops, 4838 }, 4839 4840 [MV88E6123] = { 4841 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4842 .family = MV88E6XXX_FAMILY_6165, 4843 .name = "Marvell 88E6123", 4844 .num_databases = 4096, 4845 .num_macs = 1024, 4846 .num_ports = 3, 4847 .num_internal_phys = 5, 4848 .max_vid = 4095, 4849 .port_base_addr = 0x10, 4850 .phy_base_addr = 0x0, 4851 .global1_addr = 0x1b, 4852 .global2_addr = 0x1c, 4853 .age_time_coeff = 15000, 4854 .g1_irqs = 9, 4855 .g2_irqs = 10, 4856 .atu_move_port_mask = 0xf, 4857 .pvt = true, 4858 .multi_chip = true, 4859 .tag_protocol = DSA_TAG_PROTO_EDSA, 4860 .ops = &mv88e6123_ops, 4861 }, 4862 4863 [MV88E6131] = { 4864 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4865 .family = MV88E6XXX_FAMILY_6185, 4866 .name = "Marvell 88E6131", 4867 .num_databases = 256, 4868 .num_macs = 8192, 4869 .num_ports = 8, 4870 .num_internal_phys = 0, 4871 .max_vid = 4095, 4872 .port_base_addr = 0x10, 4873 .phy_base_addr = 0x0, 4874 .global1_addr = 0x1b, 4875 .global2_addr = 0x1c, 4876 .age_time_coeff = 15000, 4877 .g1_irqs = 9, 4878 .atu_move_port_mask = 0xf, 4879 .multi_chip = true, 4880 .tag_protocol = DSA_TAG_PROTO_DSA, 4881 .ops = &mv88e6131_ops, 4882 }, 4883 4884 [MV88E6141] = { 4885 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4886 .family = MV88E6XXX_FAMILY_6341, 4887 .name = "Marvell 88E6141", 4888 .num_databases = 4096, 4889 .num_macs = 2048, 4890 .num_ports = 6, 4891 .num_internal_phys = 5, 4892 .num_gpio = 11, 4893 .max_vid = 4095, 4894 .port_base_addr = 0x10, 4895 .phy_base_addr = 0x10, 4896 .global1_addr = 0x1b, 4897 .global2_addr = 0x1c, 4898 .age_time_coeff = 3750, 4899 .atu_move_port_mask = 0x1f, 4900 .g1_irqs = 9, 4901 .g2_irqs = 10, 4902 .pvt = true, 4903 .multi_chip = true, 4904 .tag_protocol = DSA_TAG_PROTO_EDSA, 4905 .ops = &mv88e6141_ops, 4906 }, 4907 4908 [MV88E6161] = { 4909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4910 .family = MV88E6XXX_FAMILY_6165, 4911 .name = "Marvell 88E6161", 4912 .num_databases = 4096, 4913 .num_macs = 1024, 4914 .num_ports = 6, 4915 .num_internal_phys = 5, 4916 .max_vid = 4095, 4917 .port_base_addr = 0x10, 4918 .phy_base_addr = 0x0, 4919 .global1_addr = 0x1b, 4920 .global2_addr = 0x1c, 4921 .age_time_coeff = 15000, 4922 .g1_irqs = 9, 4923 .g2_irqs = 10, 4924 .atu_move_port_mask = 0xf, 4925 .pvt = true, 4926 .multi_chip = true, 4927 .tag_protocol = DSA_TAG_PROTO_EDSA, 4928 .ptp_support = true, 4929 .ops = &mv88e6161_ops, 4930 }, 4931 4932 [MV88E6165] = { 4933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4934 .family = MV88E6XXX_FAMILY_6165, 4935 .name = "Marvell 88E6165", 4936 .num_databases = 4096, 4937 .num_macs = 8192, 4938 .num_ports = 6, 4939 .num_internal_phys = 0, 4940 .max_vid = 4095, 4941 .port_base_addr = 0x10, 4942 .phy_base_addr = 0x0, 4943 .global1_addr = 0x1b, 4944 .global2_addr = 0x1c, 4945 .age_time_coeff = 15000, 4946 .g1_irqs = 9, 4947 .g2_irqs = 10, 4948 .atu_move_port_mask = 0xf, 4949 .pvt = true, 4950 .multi_chip = true, 4951 .tag_protocol = DSA_TAG_PROTO_DSA, 4952 .ptp_support = true, 4953 .ops = &mv88e6165_ops, 4954 }, 4955 4956 [MV88E6171] = { 4957 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4958 .family = MV88E6XXX_FAMILY_6351, 4959 .name = "Marvell 88E6171", 4960 .num_databases = 4096, 4961 .num_macs = 8192, 4962 .num_ports = 7, 4963 .num_internal_phys = 5, 4964 .max_vid = 4095, 4965 .port_base_addr = 0x10, 4966 .phy_base_addr = 0x0, 4967 .global1_addr = 0x1b, 4968 .global2_addr = 0x1c, 4969 .age_time_coeff = 15000, 4970 .g1_irqs = 9, 4971 .g2_irqs = 10, 4972 .atu_move_port_mask = 0xf, 4973 .pvt = true, 4974 .multi_chip = true, 4975 .tag_protocol = DSA_TAG_PROTO_EDSA, 4976 .ops = &mv88e6171_ops, 4977 }, 4978 4979 [MV88E6172] = { 4980 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4981 .family = MV88E6XXX_FAMILY_6352, 4982 .name = "Marvell 88E6172", 4983 .num_databases = 4096, 4984 .num_macs = 8192, 4985 .num_ports = 7, 4986 .num_internal_phys = 5, 4987 .num_gpio = 15, 4988 .max_vid = 4095, 4989 .port_base_addr = 0x10, 4990 .phy_base_addr = 0x0, 4991 .global1_addr = 0x1b, 4992 .global2_addr = 0x1c, 4993 .age_time_coeff = 15000, 4994 .g1_irqs = 9, 4995 .g2_irqs = 10, 4996 .atu_move_port_mask = 0xf, 4997 .pvt = true, 4998 .multi_chip = true, 4999 .tag_protocol = DSA_TAG_PROTO_EDSA, 5000 .ops = &mv88e6172_ops, 5001 }, 5002 5003 [MV88E6175] = { 5004 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5005 .family = MV88E6XXX_FAMILY_6351, 5006 .name = "Marvell 88E6175", 5007 .num_databases = 4096, 5008 .num_macs = 8192, 5009 .num_ports = 7, 5010 .num_internal_phys = 5, 5011 .max_vid = 4095, 5012 .port_base_addr = 0x10, 5013 .phy_base_addr = 0x0, 5014 .global1_addr = 0x1b, 5015 .global2_addr = 0x1c, 5016 .age_time_coeff = 15000, 5017 .g1_irqs = 9, 5018 .g2_irqs = 10, 5019 .atu_move_port_mask = 0xf, 5020 .pvt = true, 5021 .multi_chip = true, 5022 .tag_protocol = DSA_TAG_PROTO_EDSA, 5023 .ops = &mv88e6175_ops, 5024 }, 5025 5026 [MV88E6176] = { 5027 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5028 .family = MV88E6XXX_FAMILY_6352, 5029 .name = "Marvell 88E6176", 5030 .num_databases = 4096, 5031 .num_macs = 8192, 5032 .num_ports = 7, 5033 .num_internal_phys = 5, 5034 .num_gpio = 15, 5035 .max_vid = 4095, 5036 .port_base_addr = 0x10, 5037 .phy_base_addr = 0x0, 5038 .global1_addr = 0x1b, 5039 .global2_addr = 0x1c, 5040 .age_time_coeff = 15000, 5041 .g1_irqs = 9, 5042 .g2_irqs = 10, 5043 .atu_move_port_mask = 0xf, 5044 .pvt = true, 5045 .multi_chip = true, 5046 .tag_protocol = DSA_TAG_PROTO_EDSA, 5047 .ops = &mv88e6176_ops, 5048 }, 5049 5050 [MV88E6185] = { 5051 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5052 .family = MV88E6XXX_FAMILY_6185, 5053 .name = "Marvell 88E6185", 5054 .num_databases = 256, 5055 .num_macs = 8192, 5056 .num_ports = 10, 5057 .num_internal_phys = 0, 5058 .max_vid = 4095, 5059 .port_base_addr = 0x10, 5060 .phy_base_addr = 0x0, 5061 .global1_addr = 0x1b, 5062 .global2_addr = 0x1c, 5063 .age_time_coeff = 15000, 5064 .g1_irqs = 8, 5065 .atu_move_port_mask = 0xf, 5066 .multi_chip = true, 5067 .tag_protocol = DSA_TAG_PROTO_EDSA, 5068 .ops = &mv88e6185_ops, 5069 }, 5070 5071 [MV88E6190] = { 5072 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5073 .family = MV88E6XXX_FAMILY_6390, 5074 .name = "Marvell 88E6190", 5075 .num_databases = 4096, 5076 .num_macs = 16384, 5077 .num_ports = 11, /* 10 + Z80 */ 5078 .num_internal_phys = 9, 5079 .num_gpio = 16, 5080 .max_vid = 8191, 5081 .port_base_addr = 0x0, 5082 .phy_base_addr = 0x0, 5083 .global1_addr = 0x1b, 5084 .global2_addr = 0x1c, 5085 .tag_protocol = DSA_TAG_PROTO_DSA, 5086 .age_time_coeff = 3750, 5087 .g1_irqs = 9, 5088 .g2_irqs = 14, 5089 .pvt = true, 5090 .multi_chip = true, 5091 .atu_move_port_mask = 0x1f, 5092 .ops = &mv88e6190_ops, 5093 }, 5094 5095 [MV88E6190X] = { 5096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5097 .family = MV88E6XXX_FAMILY_6390, 5098 .name = "Marvell 88E6190X", 5099 .num_databases = 4096, 5100 .num_macs = 16384, 5101 .num_ports = 11, /* 10 + Z80 */ 5102 .num_internal_phys = 9, 5103 .num_gpio = 16, 5104 .max_vid = 8191, 5105 .port_base_addr = 0x0, 5106 .phy_base_addr = 0x0, 5107 .global1_addr = 0x1b, 5108 .global2_addr = 0x1c, 5109 .age_time_coeff = 3750, 5110 .g1_irqs = 9, 5111 .g2_irqs = 14, 5112 .atu_move_port_mask = 0x1f, 5113 .pvt = true, 5114 .multi_chip = true, 5115 .tag_protocol = DSA_TAG_PROTO_DSA, 5116 .ops = &mv88e6190x_ops, 5117 }, 5118 5119 [MV88E6191] = { 5120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5121 .family = MV88E6XXX_FAMILY_6390, 5122 .name = "Marvell 88E6191", 5123 .num_databases = 4096, 5124 .num_macs = 16384, 5125 .num_ports = 11, /* 10 + Z80 */ 5126 .num_internal_phys = 9, 5127 .max_vid = 8191, 5128 .port_base_addr = 0x0, 5129 .phy_base_addr = 0x0, 5130 .global1_addr = 0x1b, 5131 .global2_addr = 0x1c, 5132 .age_time_coeff = 3750, 5133 .g1_irqs = 9, 5134 .g2_irqs = 14, 5135 .atu_move_port_mask = 0x1f, 5136 .pvt = true, 5137 .multi_chip = true, 5138 .tag_protocol = DSA_TAG_PROTO_DSA, 5139 .ptp_support = true, 5140 .ops = &mv88e6191_ops, 5141 }, 5142 5143 [MV88E6191X] = { 5144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5145 .family = MV88E6XXX_FAMILY_6393, 5146 .name = "Marvell 88E6191X", 5147 .num_databases = 4096, 5148 .num_ports = 11, /* 10 + Z80 */ 5149 .num_internal_phys = 9, 5150 .max_vid = 8191, 5151 .port_base_addr = 0x0, 5152 .phy_base_addr = 0x0, 5153 .global1_addr = 0x1b, 5154 .global2_addr = 0x1c, 5155 .age_time_coeff = 3750, 5156 .g1_irqs = 10, 5157 .g2_irqs = 14, 5158 .atu_move_port_mask = 0x1f, 5159 .pvt = true, 5160 .multi_chip = true, 5161 .tag_protocol = DSA_TAG_PROTO_DSA, 5162 .ptp_support = true, 5163 .ops = &mv88e6393x_ops, 5164 }, 5165 5166 [MV88E6193X] = { 5167 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5168 .family = MV88E6XXX_FAMILY_6393, 5169 .name = "Marvell 88E6193X", 5170 .num_databases = 4096, 5171 .num_ports = 11, /* 10 + Z80 */ 5172 .num_internal_phys = 9, 5173 .max_vid = 8191, 5174 .port_base_addr = 0x0, 5175 .phy_base_addr = 0x0, 5176 .global1_addr = 0x1b, 5177 .global2_addr = 0x1c, 5178 .age_time_coeff = 3750, 5179 .g1_irqs = 10, 5180 .g2_irqs = 14, 5181 .atu_move_port_mask = 0x1f, 5182 .pvt = true, 5183 .multi_chip = true, 5184 .tag_protocol = DSA_TAG_PROTO_DSA, 5185 .ptp_support = true, 5186 .ops = &mv88e6393x_ops, 5187 }, 5188 5189 [MV88E6220] = { 5190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5191 .family = MV88E6XXX_FAMILY_6250, 5192 .name = "Marvell 88E6220", 5193 .num_databases = 64, 5194 5195 /* Ports 2-4 are not routed to pins 5196 * => usable ports 0, 1, 5, 6 5197 */ 5198 .num_ports = 7, 5199 .num_internal_phys = 2, 5200 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5201 .max_vid = 4095, 5202 .port_base_addr = 0x08, 5203 .phy_base_addr = 0x00, 5204 .global1_addr = 0x0f, 5205 .global2_addr = 0x07, 5206 .age_time_coeff = 15000, 5207 .g1_irqs = 9, 5208 .g2_irqs = 10, 5209 .atu_move_port_mask = 0xf, 5210 .dual_chip = true, 5211 .tag_protocol = DSA_TAG_PROTO_DSA, 5212 .ptp_support = true, 5213 .ops = &mv88e6250_ops, 5214 }, 5215 5216 [MV88E6240] = { 5217 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5218 .family = MV88E6XXX_FAMILY_6352, 5219 .name = "Marvell 88E6240", 5220 .num_databases = 4096, 5221 .num_macs = 8192, 5222 .num_ports = 7, 5223 .num_internal_phys = 5, 5224 .num_gpio = 15, 5225 .max_vid = 4095, 5226 .port_base_addr = 0x10, 5227 .phy_base_addr = 0x0, 5228 .global1_addr = 0x1b, 5229 .global2_addr = 0x1c, 5230 .age_time_coeff = 15000, 5231 .g1_irqs = 9, 5232 .g2_irqs = 10, 5233 .atu_move_port_mask = 0xf, 5234 .pvt = true, 5235 .multi_chip = true, 5236 .tag_protocol = DSA_TAG_PROTO_EDSA, 5237 .ptp_support = true, 5238 .ops = &mv88e6240_ops, 5239 }, 5240 5241 [MV88E6250] = { 5242 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5243 .family = MV88E6XXX_FAMILY_6250, 5244 .name = "Marvell 88E6250", 5245 .num_databases = 64, 5246 .num_ports = 7, 5247 .num_internal_phys = 5, 5248 .max_vid = 4095, 5249 .port_base_addr = 0x08, 5250 .phy_base_addr = 0x00, 5251 .global1_addr = 0x0f, 5252 .global2_addr = 0x07, 5253 .age_time_coeff = 15000, 5254 .g1_irqs = 9, 5255 .g2_irqs = 10, 5256 .atu_move_port_mask = 0xf, 5257 .dual_chip = true, 5258 .tag_protocol = DSA_TAG_PROTO_DSA, 5259 .ptp_support = true, 5260 .ops = &mv88e6250_ops, 5261 }, 5262 5263 [MV88E6290] = { 5264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5265 .family = MV88E6XXX_FAMILY_6390, 5266 .name = "Marvell 88E6290", 5267 .num_databases = 4096, 5268 .num_ports = 11, /* 10 + Z80 */ 5269 .num_internal_phys = 9, 5270 .num_gpio = 16, 5271 .max_vid = 8191, 5272 .port_base_addr = 0x0, 5273 .phy_base_addr = 0x0, 5274 .global1_addr = 0x1b, 5275 .global2_addr = 0x1c, 5276 .age_time_coeff = 3750, 5277 .g1_irqs = 9, 5278 .g2_irqs = 14, 5279 .atu_move_port_mask = 0x1f, 5280 .pvt = true, 5281 .multi_chip = true, 5282 .tag_protocol = DSA_TAG_PROTO_DSA, 5283 .ptp_support = true, 5284 .ops = &mv88e6290_ops, 5285 }, 5286 5287 [MV88E6320] = { 5288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5289 .family = MV88E6XXX_FAMILY_6320, 5290 .name = "Marvell 88E6320", 5291 .num_databases = 4096, 5292 .num_macs = 8192, 5293 .num_ports = 7, 5294 .num_internal_phys = 5, 5295 .num_gpio = 15, 5296 .max_vid = 4095, 5297 .port_base_addr = 0x10, 5298 .phy_base_addr = 0x0, 5299 .global1_addr = 0x1b, 5300 .global2_addr = 0x1c, 5301 .age_time_coeff = 15000, 5302 .g1_irqs = 8, 5303 .g2_irqs = 10, 5304 .atu_move_port_mask = 0xf, 5305 .pvt = true, 5306 .multi_chip = true, 5307 .tag_protocol = DSA_TAG_PROTO_EDSA, 5308 .ptp_support = true, 5309 .ops = &mv88e6320_ops, 5310 }, 5311 5312 [MV88E6321] = { 5313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5314 .family = MV88E6XXX_FAMILY_6320, 5315 .name = "Marvell 88E6321", 5316 .num_databases = 4096, 5317 .num_macs = 8192, 5318 .num_ports = 7, 5319 .num_internal_phys = 5, 5320 .num_gpio = 15, 5321 .max_vid = 4095, 5322 .port_base_addr = 0x10, 5323 .phy_base_addr = 0x0, 5324 .global1_addr = 0x1b, 5325 .global2_addr = 0x1c, 5326 .age_time_coeff = 15000, 5327 .g1_irqs = 8, 5328 .g2_irqs = 10, 5329 .atu_move_port_mask = 0xf, 5330 .multi_chip = true, 5331 .tag_protocol = DSA_TAG_PROTO_EDSA, 5332 .ptp_support = true, 5333 .ops = &mv88e6321_ops, 5334 }, 5335 5336 [MV88E6341] = { 5337 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5338 .family = MV88E6XXX_FAMILY_6341, 5339 .name = "Marvell 88E6341", 5340 .num_databases = 4096, 5341 .num_macs = 2048, 5342 .num_internal_phys = 5, 5343 .num_ports = 6, 5344 .num_gpio = 11, 5345 .max_vid = 4095, 5346 .port_base_addr = 0x10, 5347 .phy_base_addr = 0x10, 5348 .global1_addr = 0x1b, 5349 .global2_addr = 0x1c, 5350 .age_time_coeff = 3750, 5351 .atu_move_port_mask = 0x1f, 5352 .g1_irqs = 9, 5353 .g2_irqs = 10, 5354 .pvt = true, 5355 .multi_chip = true, 5356 .tag_protocol = DSA_TAG_PROTO_EDSA, 5357 .ptp_support = true, 5358 .ops = &mv88e6341_ops, 5359 }, 5360 5361 [MV88E6350] = { 5362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5363 .family = MV88E6XXX_FAMILY_6351, 5364 .name = "Marvell 88E6350", 5365 .num_databases = 4096, 5366 .num_macs = 8192, 5367 .num_ports = 7, 5368 .num_internal_phys = 5, 5369 .max_vid = 4095, 5370 .port_base_addr = 0x10, 5371 .phy_base_addr = 0x0, 5372 .global1_addr = 0x1b, 5373 .global2_addr = 0x1c, 5374 .age_time_coeff = 15000, 5375 .g1_irqs = 9, 5376 .g2_irqs = 10, 5377 .atu_move_port_mask = 0xf, 5378 .pvt = true, 5379 .multi_chip = true, 5380 .tag_protocol = DSA_TAG_PROTO_EDSA, 5381 .ops = &mv88e6350_ops, 5382 }, 5383 5384 [MV88E6351] = { 5385 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5386 .family = MV88E6XXX_FAMILY_6351, 5387 .name = "Marvell 88E6351", 5388 .num_databases = 4096, 5389 .num_macs = 8192, 5390 .num_ports = 7, 5391 .num_internal_phys = 5, 5392 .max_vid = 4095, 5393 .port_base_addr = 0x10, 5394 .phy_base_addr = 0x0, 5395 .global1_addr = 0x1b, 5396 .global2_addr = 0x1c, 5397 .age_time_coeff = 15000, 5398 .g1_irqs = 9, 5399 .g2_irqs = 10, 5400 .atu_move_port_mask = 0xf, 5401 .pvt = true, 5402 .multi_chip = true, 5403 .tag_protocol = DSA_TAG_PROTO_EDSA, 5404 .ops = &mv88e6351_ops, 5405 }, 5406 5407 [MV88E6352] = { 5408 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5409 .family = MV88E6XXX_FAMILY_6352, 5410 .name = "Marvell 88E6352", 5411 .num_databases = 4096, 5412 .num_macs = 8192, 5413 .num_ports = 7, 5414 .num_internal_phys = 5, 5415 .num_gpio = 15, 5416 .max_vid = 4095, 5417 .port_base_addr = 0x10, 5418 .phy_base_addr = 0x0, 5419 .global1_addr = 0x1b, 5420 .global2_addr = 0x1c, 5421 .age_time_coeff = 15000, 5422 .g1_irqs = 9, 5423 .g2_irqs = 10, 5424 .atu_move_port_mask = 0xf, 5425 .pvt = true, 5426 .multi_chip = true, 5427 .tag_protocol = DSA_TAG_PROTO_EDSA, 5428 .ptp_support = true, 5429 .ops = &mv88e6352_ops, 5430 }, 5431 [MV88E6390] = { 5432 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5433 .family = MV88E6XXX_FAMILY_6390, 5434 .name = "Marvell 88E6390", 5435 .num_databases = 4096, 5436 .num_macs = 16384, 5437 .num_ports = 11, /* 10 + Z80 */ 5438 .num_internal_phys = 9, 5439 .num_gpio = 16, 5440 .max_vid = 8191, 5441 .port_base_addr = 0x0, 5442 .phy_base_addr = 0x0, 5443 .global1_addr = 0x1b, 5444 .global2_addr = 0x1c, 5445 .age_time_coeff = 3750, 5446 .g1_irqs = 9, 5447 .g2_irqs = 14, 5448 .atu_move_port_mask = 0x1f, 5449 .pvt = true, 5450 .multi_chip = true, 5451 .tag_protocol = DSA_TAG_PROTO_DSA, 5452 .ptp_support = true, 5453 .ops = &mv88e6390_ops, 5454 }, 5455 [MV88E6390X] = { 5456 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5457 .family = MV88E6XXX_FAMILY_6390, 5458 .name = "Marvell 88E6390X", 5459 .num_databases = 4096, 5460 .num_macs = 16384, 5461 .num_ports = 11, /* 10 + Z80 */ 5462 .num_internal_phys = 9, 5463 .num_gpio = 16, 5464 .max_vid = 8191, 5465 .port_base_addr = 0x0, 5466 .phy_base_addr = 0x0, 5467 .global1_addr = 0x1b, 5468 .global2_addr = 0x1c, 5469 .age_time_coeff = 3750, 5470 .g1_irqs = 9, 5471 .g2_irqs = 14, 5472 .atu_move_port_mask = 0x1f, 5473 .pvt = true, 5474 .multi_chip = true, 5475 .tag_protocol = DSA_TAG_PROTO_DSA, 5476 .ptp_support = true, 5477 .ops = &mv88e6390x_ops, 5478 }, 5479 5480 [MV88E6393X] = { 5481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5482 .family = MV88E6XXX_FAMILY_6393, 5483 .name = "Marvell 88E6393X", 5484 .num_databases = 4096, 5485 .num_ports = 11, /* 10 + Z80 */ 5486 .num_internal_phys = 9, 5487 .max_vid = 8191, 5488 .port_base_addr = 0x0, 5489 .phy_base_addr = 0x0, 5490 .global1_addr = 0x1b, 5491 .global2_addr = 0x1c, 5492 .age_time_coeff = 3750, 5493 .g1_irqs = 10, 5494 .g2_irqs = 14, 5495 .atu_move_port_mask = 0x1f, 5496 .pvt = true, 5497 .multi_chip = true, 5498 .tag_protocol = DSA_TAG_PROTO_DSA, 5499 .ptp_support = true, 5500 .ops = &mv88e6393x_ops, 5501 }, 5502 }; 5503 5504 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5505 { 5506 int i; 5507 5508 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5509 if (mv88e6xxx_table[i].prod_num == prod_num) 5510 return &mv88e6xxx_table[i]; 5511 5512 return NULL; 5513 } 5514 5515 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5516 { 5517 const struct mv88e6xxx_info *info; 5518 unsigned int prod_num, rev; 5519 u16 id; 5520 int err; 5521 5522 mv88e6xxx_reg_lock(chip); 5523 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5524 mv88e6xxx_reg_unlock(chip); 5525 if (err) 5526 return err; 5527 5528 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5529 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5530 5531 info = mv88e6xxx_lookup_info(prod_num); 5532 if (!info) 5533 return -ENODEV; 5534 5535 /* Update the compatible info with the probed one */ 5536 chip->info = info; 5537 5538 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5539 chip->info->prod_num, chip->info->name, rev); 5540 5541 return 0; 5542 } 5543 5544 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5545 { 5546 struct mv88e6xxx_chip *chip; 5547 5548 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5549 if (!chip) 5550 return NULL; 5551 5552 chip->dev = dev; 5553 5554 mutex_init(&chip->reg_lock); 5555 INIT_LIST_HEAD(&chip->mdios); 5556 idr_init(&chip->policies); 5557 5558 return chip; 5559 } 5560 5561 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5562 int port, 5563 enum dsa_tag_protocol m) 5564 { 5565 struct mv88e6xxx_chip *chip = ds->priv; 5566 5567 return chip->info->tag_protocol; 5568 } 5569 5570 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5571 const struct switchdev_obj_port_mdb *mdb) 5572 { 5573 struct mv88e6xxx_chip *chip = ds->priv; 5574 int err; 5575 5576 mv88e6xxx_reg_lock(chip); 5577 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5578 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5579 mv88e6xxx_reg_unlock(chip); 5580 5581 return err; 5582 } 5583 5584 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5585 const struct switchdev_obj_port_mdb *mdb) 5586 { 5587 struct mv88e6xxx_chip *chip = ds->priv; 5588 int err; 5589 5590 mv88e6xxx_reg_lock(chip); 5591 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5592 mv88e6xxx_reg_unlock(chip); 5593 5594 return err; 5595 } 5596 5597 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5598 struct dsa_mall_mirror_tc_entry *mirror, 5599 bool ingress) 5600 { 5601 enum mv88e6xxx_egress_direction direction = ingress ? 5602 MV88E6XXX_EGRESS_DIR_INGRESS : 5603 MV88E6XXX_EGRESS_DIR_EGRESS; 5604 struct mv88e6xxx_chip *chip = ds->priv; 5605 bool other_mirrors = false; 5606 int i; 5607 int err; 5608 5609 mutex_lock(&chip->reg_lock); 5610 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5611 mirror->to_local_port) { 5612 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5613 other_mirrors |= ingress ? 5614 chip->ports[i].mirror_ingress : 5615 chip->ports[i].mirror_egress; 5616 5617 /* Can't change egress port when other mirror is active */ 5618 if (other_mirrors) { 5619 err = -EBUSY; 5620 goto out; 5621 } 5622 5623 err = mv88e6xxx_set_egress_port(chip, direction, 5624 mirror->to_local_port); 5625 if (err) 5626 goto out; 5627 } 5628 5629 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5630 out: 5631 mutex_unlock(&chip->reg_lock); 5632 5633 return err; 5634 } 5635 5636 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5637 struct dsa_mall_mirror_tc_entry *mirror) 5638 { 5639 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5640 MV88E6XXX_EGRESS_DIR_INGRESS : 5641 MV88E6XXX_EGRESS_DIR_EGRESS; 5642 struct mv88e6xxx_chip *chip = ds->priv; 5643 bool other_mirrors = false; 5644 int i; 5645 5646 mutex_lock(&chip->reg_lock); 5647 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5648 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5649 5650 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5651 other_mirrors |= mirror->ingress ? 5652 chip->ports[i].mirror_ingress : 5653 chip->ports[i].mirror_egress; 5654 5655 /* Reset egress port when no other mirror is active */ 5656 if (!other_mirrors) { 5657 if (mv88e6xxx_set_egress_port(chip, direction, 5658 dsa_upstream_port(ds, port))) 5659 dev_err(ds->dev, "failed to set egress port\n"); 5660 } 5661 5662 mutex_unlock(&chip->reg_lock); 5663 } 5664 5665 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5666 struct switchdev_brport_flags flags, 5667 struct netlink_ext_ack *extack) 5668 { 5669 struct mv88e6xxx_chip *chip = ds->priv; 5670 const struct mv88e6xxx_ops *ops; 5671 5672 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5673 BR_BCAST_FLOOD)) 5674 return -EINVAL; 5675 5676 ops = chip->info->ops; 5677 5678 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5679 return -EINVAL; 5680 5681 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5682 return -EINVAL; 5683 5684 return 0; 5685 } 5686 5687 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5688 struct switchdev_brport_flags flags, 5689 struct netlink_ext_ack *extack) 5690 { 5691 struct mv88e6xxx_chip *chip = ds->priv; 5692 bool do_fast_age = false; 5693 int err = -EOPNOTSUPP; 5694 5695 mv88e6xxx_reg_lock(chip); 5696 5697 if (flags.mask & BR_LEARNING) { 5698 bool learning = !!(flags.val & BR_LEARNING); 5699 u16 pav = learning ? (1 << port) : 0; 5700 5701 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5702 if (err) 5703 goto out; 5704 5705 if (!learning) 5706 do_fast_age = true; 5707 } 5708 5709 if (flags.mask & BR_FLOOD) { 5710 bool unicast = !!(flags.val & BR_FLOOD); 5711 5712 err = chip->info->ops->port_set_ucast_flood(chip, port, 5713 unicast); 5714 if (err) 5715 goto out; 5716 } 5717 5718 if (flags.mask & BR_MCAST_FLOOD) { 5719 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5720 5721 err = chip->info->ops->port_set_mcast_flood(chip, port, 5722 multicast); 5723 if (err) 5724 goto out; 5725 } 5726 5727 if (flags.mask & BR_BCAST_FLOOD) { 5728 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5729 5730 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5731 if (err) 5732 goto out; 5733 } 5734 5735 out: 5736 mv88e6xxx_reg_unlock(chip); 5737 5738 if (do_fast_age) 5739 mv88e6xxx_port_fast_age(ds, port); 5740 5741 return err; 5742 } 5743 5744 static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port, 5745 bool mrouter, 5746 struct netlink_ext_ack *extack) 5747 { 5748 struct mv88e6xxx_chip *chip = ds->priv; 5749 int err; 5750 5751 if (!chip->info->ops->port_set_mcast_flood) 5752 return -EOPNOTSUPP; 5753 5754 mv88e6xxx_reg_lock(chip); 5755 err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter); 5756 mv88e6xxx_reg_unlock(chip); 5757 5758 return err; 5759 } 5760 5761 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5762 struct net_device *lag, 5763 struct netdev_lag_upper_info *info) 5764 { 5765 struct mv88e6xxx_chip *chip = ds->priv; 5766 struct dsa_port *dp; 5767 int id, members = 0; 5768 5769 if (!mv88e6xxx_has_lag(chip)) 5770 return false; 5771 5772 id = dsa_lag_id(ds->dst, lag); 5773 if (id < 0 || id >= ds->num_lag_ids) 5774 return false; 5775 5776 dsa_lag_foreach_port(dp, ds->dst, lag) 5777 /* Includes the port joining the LAG */ 5778 members++; 5779 5780 if (members > 8) 5781 return false; 5782 5783 /* We could potentially relax this to include active 5784 * backup in the future. 5785 */ 5786 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5787 return false; 5788 5789 /* Ideally we would also validate that the hash type matches 5790 * the hardware. Alas, this is always set to unknown on team 5791 * interfaces. 5792 */ 5793 return true; 5794 } 5795 5796 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5797 { 5798 struct mv88e6xxx_chip *chip = ds->priv; 5799 struct dsa_port *dp; 5800 u16 map = 0; 5801 int id; 5802 5803 id = dsa_lag_id(ds->dst, lag); 5804 5805 /* Build the map of all ports to distribute flows destined for 5806 * this LAG. This can be either a local user port, or a DSA 5807 * port if the LAG port is on a remote chip. 5808 */ 5809 dsa_lag_foreach_port(dp, ds->dst, lag) 5810 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5811 5812 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5813 } 5814 5815 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5816 /* Row number corresponds to the number of active members in a 5817 * LAG. Each column states which of the eight hash buckets are 5818 * mapped to the column:th port in the LAG. 5819 * 5820 * Example: In a LAG with three active ports, the second port 5821 * ([2][1]) would be selected for traffic mapped to buckets 5822 * 3,4,5 (0x38). 5823 */ 5824 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 5825 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 5826 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 5827 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 5828 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 5829 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 5830 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 5831 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 5832 }; 5833 5834 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 5835 int num_tx, int nth) 5836 { 5837 u8 active = 0; 5838 int i; 5839 5840 num_tx = num_tx <= 8 ? num_tx : 8; 5841 if (nth < num_tx) 5842 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 5843 5844 for (i = 0; i < 8; i++) { 5845 if (BIT(i) & active) 5846 mask[i] |= BIT(port); 5847 } 5848 } 5849 5850 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 5851 { 5852 struct mv88e6xxx_chip *chip = ds->priv; 5853 unsigned int id, num_tx; 5854 struct net_device *lag; 5855 struct dsa_port *dp; 5856 int i, err, nth; 5857 u16 mask[8]; 5858 u16 ivec; 5859 5860 /* Assume no port is a member of any LAG. */ 5861 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 5862 5863 /* Disable all masks for ports that _are_ members of a LAG. */ 5864 list_for_each_entry(dp, &ds->dst->ports, list) { 5865 if (!dp->lag_dev || dp->ds != ds) 5866 continue; 5867 5868 ivec &= ~BIT(dp->index); 5869 } 5870 5871 for (i = 0; i < 8; i++) 5872 mask[i] = ivec; 5873 5874 /* Enable the correct subset of masks for all LAG ports that 5875 * are in the Tx set. 5876 */ 5877 dsa_lags_foreach_id(id, ds->dst) { 5878 lag = dsa_lag_dev(ds->dst, id); 5879 if (!lag) 5880 continue; 5881 5882 num_tx = 0; 5883 dsa_lag_foreach_port(dp, ds->dst, lag) { 5884 if (dp->lag_tx_enabled) 5885 num_tx++; 5886 } 5887 5888 if (!num_tx) 5889 continue; 5890 5891 nth = 0; 5892 dsa_lag_foreach_port(dp, ds->dst, lag) { 5893 if (!dp->lag_tx_enabled) 5894 continue; 5895 5896 if (dp->ds == ds) 5897 mv88e6xxx_lag_set_port_mask(mask, dp->index, 5898 num_tx, nth); 5899 5900 nth++; 5901 } 5902 } 5903 5904 for (i = 0; i < 8; i++) { 5905 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 5906 if (err) 5907 return err; 5908 } 5909 5910 return 0; 5911 } 5912 5913 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 5914 struct net_device *lag) 5915 { 5916 int err; 5917 5918 err = mv88e6xxx_lag_sync_masks(ds); 5919 5920 if (!err) 5921 err = mv88e6xxx_lag_sync_map(ds, lag); 5922 5923 return err; 5924 } 5925 5926 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 5927 { 5928 struct mv88e6xxx_chip *chip = ds->priv; 5929 int err; 5930 5931 mv88e6xxx_reg_lock(chip); 5932 err = mv88e6xxx_lag_sync_masks(ds); 5933 mv88e6xxx_reg_unlock(chip); 5934 return err; 5935 } 5936 5937 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 5938 struct net_device *lag, 5939 struct netdev_lag_upper_info *info) 5940 { 5941 struct mv88e6xxx_chip *chip = ds->priv; 5942 int err, id; 5943 5944 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 5945 return -EOPNOTSUPP; 5946 5947 id = dsa_lag_id(ds->dst, lag); 5948 5949 mv88e6xxx_reg_lock(chip); 5950 5951 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 5952 if (err) 5953 goto err_unlock; 5954 5955 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 5956 if (err) 5957 goto err_clear_trunk; 5958 5959 mv88e6xxx_reg_unlock(chip); 5960 return 0; 5961 5962 err_clear_trunk: 5963 mv88e6xxx_port_set_trunk(chip, port, false, 0); 5964 err_unlock: 5965 mv88e6xxx_reg_unlock(chip); 5966 return err; 5967 } 5968 5969 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 5970 struct net_device *lag) 5971 { 5972 struct mv88e6xxx_chip *chip = ds->priv; 5973 int err_sync, err_trunk; 5974 5975 mv88e6xxx_reg_lock(chip); 5976 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 5977 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 5978 mv88e6xxx_reg_unlock(chip); 5979 return err_sync ? : err_trunk; 5980 } 5981 5982 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 5983 int port) 5984 { 5985 struct mv88e6xxx_chip *chip = ds->priv; 5986 int err; 5987 5988 mv88e6xxx_reg_lock(chip); 5989 err = mv88e6xxx_lag_sync_masks(ds); 5990 mv88e6xxx_reg_unlock(chip); 5991 return err; 5992 } 5993 5994 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 5995 int port, struct net_device *lag, 5996 struct netdev_lag_upper_info *info) 5997 { 5998 struct mv88e6xxx_chip *chip = ds->priv; 5999 int err; 6000 6001 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6002 return -EOPNOTSUPP; 6003 6004 mv88e6xxx_reg_lock(chip); 6005 6006 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6007 if (err) 6008 goto unlock; 6009 6010 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6011 6012 unlock: 6013 mv88e6xxx_reg_unlock(chip); 6014 return err; 6015 } 6016 6017 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6018 int port, struct net_device *lag) 6019 { 6020 struct mv88e6xxx_chip *chip = ds->priv; 6021 int err_sync, err_pvt; 6022 6023 mv88e6xxx_reg_lock(chip); 6024 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6025 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6026 mv88e6xxx_reg_unlock(chip); 6027 return err_sync ? : err_pvt; 6028 } 6029 6030 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6031 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6032 .setup = mv88e6xxx_setup, 6033 .teardown = mv88e6xxx_teardown, 6034 .phylink_validate = mv88e6xxx_validate, 6035 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6036 .phylink_mac_config = mv88e6xxx_mac_config, 6037 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6038 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6039 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6040 .get_strings = mv88e6xxx_get_strings, 6041 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6042 .get_sset_count = mv88e6xxx_get_sset_count, 6043 .port_enable = mv88e6xxx_port_enable, 6044 .port_disable = mv88e6xxx_port_disable, 6045 .port_max_mtu = mv88e6xxx_get_max_mtu, 6046 .port_change_mtu = mv88e6xxx_change_mtu, 6047 .get_mac_eee = mv88e6xxx_get_mac_eee, 6048 .set_mac_eee = mv88e6xxx_set_mac_eee, 6049 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6050 .get_eeprom = mv88e6xxx_get_eeprom, 6051 .set_eeprom = mv88e6xxx_set_eeprom, 6052 .get_regs_len = mv88e6xxx_get_regs_len, 6053 .get_regs = mv88e6xxx_get_regs, 6054 .get_rxnfc = mv88e6xxx_get_rxnfc, 6055 .set_rxnfc = mv88e6xxx_set_rxnfc, 6056 .set_ageing_time = mv88e6xxx_set_ageing_time, 6057 .port_bridge_join = mv88e6xxx_port_bridge_join, 6058 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6059 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6060 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6061 .port_set_mrouter = mv88e6xxx_port_set_mrouter, 6062 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6063 .port_fast_age = mv88e6xxx_port_fast_age, 6064 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6065 .port_vlan_add = mv88e6xxx_port_vlan_add, 6066 .port_vlan_del = mv88e6xxx_port_vlan_del, 6067 .port_fdb_add = mv88e6xxx_port_fdb_add, 6068 .port_fdb_del = mv88e6xxx_port_fdb_del, 6069 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6070 .port_mdb_add = mv88e6xxx_port_mdb_add, 6071 .port_mdb_del = mv88e6xxx_port_mdb_del, 6072 .port_mirror_add = mv88e6xxx_port_mirror_add, 6073 .port_mirror_del = mv88e6xxx_port_mirror_del, 6074 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6075 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6076 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6077 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6078 .port_txtstamp = mv88e6xxx_port_txtstamp, 6079 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6080 .get_ts_info = mv88e6xxx_get_ts_info, 6081 .devlink_param_get = mv88e6xxx_devlink_param_get, 6082 .devlink_param_set = mv88e6xxx_devlink_param_set, 6083 .devlink_info_get = mv88e6xxx_devlink_info_get, 6084 .port_lag_change = mv88e6xxx_port_lag_change, 6085 .port_lag_join = mv88e6xxx_port_lag_join, 6086 .port_lag_leave = mv88e6xxx_port_lag_leave, 6087 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6088 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6089 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6090 }; 6091 6092 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6093 { 6094 struct device *dev = chip->dev; 6095 struct dsa_switch *ds; 6096 6097 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6098 if (!ds) 6099 return -ENOMEM; 6100 6101 ds->dev = dev; 6102 ds->num_ports = mv88e6xxx_num_ports(chip); 6103 ds->priv = chip; 6104 ds->dev = dev; 6105 ds->ops = &mv88e6xxx_switch_ops; 6106 ds->ageing_time_min = chip->info->age_time_coeff; 6107 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6108 6109 /* Some chips support up to 32, but that requires enabling the 6110 * 5-bit port mode, which we do not support. 640k^W16 ought to 6111 * be enough for anyone. 6112 */ 6113 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6114 6115 dev_set_drvdata(dev, ds); 6116 6117 return dsa_register_switch(ds); 6118 } 6119 6120 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6121 { 6122 dsa_unregister_switch(chip->ds); 6123 } 6124 6125 static const void *pdata_device_get_match_data(struct device *dev) 6126 { 6127 const struct of_device_id *matches = dev->driver->of_match_table; 6128 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6129 6130 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6131 matches++) { 6132 if (!strcmp(pdata->compatible, matches->compatible)) 6133 return matches->data; 6134 } 6135 return NULL; 6136 } 6137 6138 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6139 * would be lost after a power cycle so prevent it to be suspended. 6140 */ 6141 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6142 { 6143 return -EOPNOTSUPP; 6144 } 6145 6146 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6147 { 6148 return 0; 6149 } 6150 6151 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6152 6153 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6154 { 6155 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6156 const struct mv88e6xxx_info *compat_info = NULL; 6157 struct device *dev = &mdiodev->dev; 6158 struct device_node *np = dev->of_node; 6159 struct mv88e6xxx_chip *chip; 6160 int port; 6161 int err; 6162 6163 if (!np && !pdata) 6164 return -EINVAL; 6165 6166 if (np) 6167 compat_info = of_device_get_match_data(dev); 6168 6169 if (pdata) { 6170 compat_info = pdata_device_get_match_data(dev); 6171 6172 if (!pdata->netdev) 6173 return -EINVAL; 6174 6175 for (port = 0; port < DSA_MAX_PORTS; port++) { 6176 if (!(pdata->enabled_ports & (1 << port))) 6177 continue; 6178 if (strcmp(pdata->cd.port_names[port], "cpu")) 6179 continue; 6180 pdata->cd.netdev[port] = &pdata->netdev->dev; 6181 break; 6182 } 6183 } 6184 6185 if (!compat_info) 6186 return -EINVAL; 6187 6188 chip = mv88e6xxx_alloc_chip(dev); 6189 if (!chip) { 6190 err = -ENOMEM; 6191 goto out; 6192 } 6193 6194 chip->info = compat_info; 6195 6196 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6197 if (err) 6198 goto out; 6199 6200 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6201 if (IS_ERR(chip->reset)) { 6202 err = PTR_ERR(chip->reset); 6203 goto out; 6204 } 6205 if (chip->reset) 6206 usleep_range(1000, 2000); 6207 6208 err = mv88e6xxx_detect(chip); 6209 if (err) 6210 goto out; 6211 6212 mv88e6xxx_phy_init(chip); 6213 6214 if (chip->info->ops->get_eeprom) { 6215 if (np) 6216 of_property_read_u32(np, "eeprom-length", 6217 &chip->eeprom_len); 6218 else 6219 chip->eeprom_len = pdata->eeprom_len; 6220 } 6221 6222 mv88e6xxx_reg_lock(chip); 6223 err = mv88e6xxx_switch_reset(chip); 6224 mv88e6xxx_reg_unlock(chip); 6225 if (err) 6226 goto out; 6227 6228 if (np) { 6229 chip->irq = of_irq_get(np, 0); 6230 if (chip->irq == -EPROBE_DEFER) { 6231 err = chip->irq; 6232 goto out; 6233 } 6234 } 6235 6236 if (pdata) 6237 chip->irq = pdata->irq; 6238 6239 /* Has to be performed before the MDIO bus is created, because 6240 * the PHYs will link their interrupts to these interrupt 6241 * controllers 6242 */ 6243 mv88e6xxx_reg_lock(chip); 6244 if (chip->irq > 0) 6245 err = mv88e6xxx_g1_irq_setup(chip); 6246 else 6247 err = mv88e6xxx_irq_poll_setup(chip); 6248 mv88e6xxx_reg_unlock(chip); 6249 6250 if (err) 6251 goto out; 6252 6253 if (chip->info->g2_irqs > 0) { 6254 err = mv88e6xxx_g2_irq_setup(chip); 6255 if (err) 6256 goto out_g1_irq; 6257 } 6258 6259 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6260 if (err) 6261 goto out_g2_irq; 6262 6263 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6264 if (err) 6265 goto out_g1_atu_prob_irq; 6266 6267 err = mv88e6xxx_mdios_register(chip, np); 6268 if (err) 6269 goto out_g1_vtu_prob_irq; 6270 6271 err = mv88e6xxx_register_switch(chip); 6272 if (err) 6273 goto out_mdio; 6274 6275 return 0; 6276 6277 out_mdio: 6278 mv88e6xxx_mdios_unregister(chip); 6279 out_g1_vtu_prob_irq: 6280 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6281 out_g1_atu_prob_irq: 6282 mv88e6xxx_g1_atu_prob_irq_free(chip); 6283 out_g2_irq: 6284 if (chip->info->g2_irqs > 0) 6285 mv88e6xxx_g2_irq_free(chip); 6286 out_g1_irq: 6287 if (chip->irq > 0) 6288 mv88e6xxx_g1_irq_free(chip); 6289 else 6290 mv88e6xxx_irq_poll_free(chip); 6291 out: 6292 if (pdata) 6293 dev_put(pdata->netdev); 6294 6295 return err; 6296 } 6297 6298 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6299 { 6300 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6301 struct mv88e6xxx_chip *chip = ds->priv; 6302 6303 if (chip->info->ptp_support) { 6304 mv88e6xxx_hwtstamp_free(chip); 6305 mv88e6xxx_ptp_free(chip); 6306 } 6307 6308 mv88e6xxx_phy_destroy(chip); 6309 mv88e6xxx_unregister_switch(chip); 6310 mv88e6xxx_mdios_unregister(chip); 6311 6312 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6313 mv88e6xxx_g1_atu_prob_irq_free(chip); 6314 6315 if (chip->info->g2_irqs > 0) 6316 mv88e6xxx_g2_irq_free(chip); 6317 6318 if (chip->irq > 0) 6319 mv88e6xxx_g1_irq_free(chip); 6320 else 6321 mv88e6xxx_irq_poll_free(chip); 6322 } 6323 6324 static const struct of_device_id mv88e6xxx_of_match[] = { 6325 { 6326 .compatible = "marvell,mv88e6085", 6327 .data = &mv88e6xxx_table[MV88E6085], 6328 }, 6329 { 6330 .compatible = "marvell,mv88e6190", 6331 .data = &mv88e6xxx_table[MV88E6190], 6332 }, 6333 { 6334 .compatible = "marvell,mv88e6250", 6335 .data = &mv88e6xxx_table[MV88E6250], 6336 }, 6337 { /* sentinel */ }, 6338 }; 6339 6340 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6341 6342 static struct mdio_driver mv88e6xxx_driver = { 6343 .probe = mv88e6xxx_probe, 6344 .remove = mv88e6xxx_remove, 6345 .mdiodrv.driver = { 6346 .name = "mv88e6085", 6347 .of_match_table = mv88e6xxx_of_match, 6348 .pm = &mv88e6xxx_pm_ops, 6349 }, 6350 }; 6351 6352 mdio_module_driver(mv88e6xxx_driver); 6353 6354 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6355 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6356 MODULE_LICENSE("GPL"); 6357