1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_add_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t *data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i, j; 1161 1162 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) { 1165 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1166 ETH_GSTRING_LEN); 1167 j++; 1168 } 1169 } 1170 1171 return j; 1172 } 1173 1174 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1175 uint8_t *data) 1176 { 1177 return mv88e6xxx_stats_get_strings(chip, data, 1178 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1179 } 1180 1181 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1182 uint8_t *data) 1183 { 1184 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1185 } 1186 1187 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1188 uint8_t *data) 1189 { 1190 return mv88e6xxx_stats_get_strings(chip, data, 1191 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1192 } 1193 1194 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1195 "atu_member_violation", 1196 "atu_miss_violation", 1197 "atu_full_violation", 1198 "vtu_member_violation", 1199 "vtu_miss_violation", 1200 }; 1201 1202 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1203 { 1204 unsigned int i; 1205 1206 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1207 strscpy(data + i * ETH_GSTRING_LEN, 1208 mv88e6xxx_atu_vtu_stats_strings[i], 1209 ETH_GSTRING_LEN); 1210 } 1211 1212 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1213 u32 stringset, uint8_t *data) 1214 { 1215 struct mv88e6xxx_chip *chip = ds->priv; 1216 int count = 0; 1217 1218 if (stringset != ETH_SS_STATS) 1219 return; 1220 1221 mv88e6xxx_reg_lock(chip); 1222 1223 if (chip->info->ops->stats_get_strings) 1224 count = chip->info->ops->stats_get_strings(chip, data); 1225 1226 if (chip->info->ops->serdes_get_strings) { 1227 data += count * ETH_GSTRING_LEN; 1228 count = chip->info->ops->serdes_get_strings(chip, port, data); 1229 } 1230 1231 data += count * ETH_GSTRING_LEN; 1232 mv88e6xxx_atu_vtu_get_strings(data); 1233 1234 mv88e6xxx_reg_unlock(chip); 1235 } 1236 1237 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1238 int types) 1239 { 1240 const struct mv88e6xxx_hw_stat *stat; 1241 int i, j; 1242 1243 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1244 stat = &mv88e6xxx_hw_stats[i]; 1245 if (stat->type & types) 1246 j++; 1247 } 1248 return j; 1249 } 1250 1251 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_PORT); 1255 } 1256 1257 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1258 { 1259 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1260 } 1261 1262 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1263 { 1264 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1265 STATS_TYPE_BANK1); 1266 } 1267 1268 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1269 { 1270 struct mv88e6xxx_chip *chip = ds->priv; 1271 int serdes_count = 0; 1272 int count = 0; 1273 1274 if (sset != ETH_SS_STATS) 1275 return 0; 1276 1277 mv88e6xxx_reg_lock(chip); 1278 if (chip->info->ops->stats_get_sset_count) 1279 count = chip->info->ops->stats_get_sset_count(chip); 1280 if (count < 0) 1281 goto out; 1282 1283 if (chip->info->ops->serdes_get_sset_count) 1284 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1285 port); 1286 if (serdes_count < 0) { 1287 count = serdes_count; 1288 goto out; 1289 } 1290 count += serdes_count; 1291 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1292 1293 out: 1294 mv88e6xxx_reg_unlock(chip); 1295 1296 return count; 1297 } 1298 1299 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1300 const struct mv88e6xxx_hw_stat *stat, 1301 uint64_t *data) 1302 { 1303 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT))) 1304 return 0; 1305 1306 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1307 MV88E6XXX_G1_STATS_OP_HIST_RX); 1308 return 1; 1309 } 1310 1311 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1312 const struct mv88e6xxx_hw_stat *stat, 1313 uint64_t *data) 1314 { 1315 if (!(stat->type & STATS_TYPE_BANK0)) 1316 return 0; 1317 1318 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1319 MV88E6XXX_G1_STATS_OP_HIST_RX); 1320 return 1; 1321 } 1322 1323 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1324 const struct mv88e6xxx_hw_stat *stat, 1325 uint64_t *data) 1326 { 1327 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1328 return 0; 1329 1330 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1331 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1332 MV88E6XXX_G1_STATS_OP_HIST_RX); 1333 return 1; 1334 } 1335 1336 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1337 const struct mv88e6xxx_hw_stat *stat, 1338 uint64_t *data) 1339 { 1340 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) 1341 return 0; 1342 1343 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1344 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1345 0); 1346 return 1; 1347 } 1348 1349 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1350 const struct mv88e6xxx_hw_stat *stat, 1351 uint64_t *data) 1352 { 1353 int ret = 0; 1354 1355 if (chip->info->ops->stats_get_stat) { 1356 mv88e6xxx_reg_lock(chip); 1357 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1358 mv88e6xxx_reg_unlock(chip); 1359 } 1360 1361 return ret; 1362 } 1363 1364 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1365 uint64_t *data) 1366 { 1367 const struct mv88e6xxx_hw_stat *stat; 1368 size_t i, j; 1369 1370 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1371 stat = &mv88e6xxx_hw_stats[i]; 1372 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1373 } 1374 return j; 1375 } 1376 1377 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1378 uint64_t *data) 1379 { 1380 *data++ = chip->ports[port].atu_member_violation; 1381 *data++ = chip->ports[port].atu_miss_violation; 1382 *data++ = chip->ports[port].atu_full_violation; 1383 *data++ = chip->ports[port].vtu_member_violation; 1384 *data++ = chip->ports[port].vtu_miss_violation; 1385 } 1386 1387 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1388 uint64_t *data) 1389 { 1390 size_t count; 1391 1392 count = mv88e6xxx_stats_get_stats(chip, port, data); 1393 1394 mv88e6xxx_reg_lock(chip); 1395 if (chip->info->ops->serdes_get_stats) { 1396 data += count; 1397 count = chip->info->ops->serdes_get_stats(chip, port, data); 1398 } 1399 data += count; 1400 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1401 mv88e6xxx_reg_unlock(chip); 1402 } 1403 1404 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1405 uint64_t *data) 1406 { 1407 struct mv88e6xxx_chip *chip = ds->priv; 1408 int ret; 1409 1410 ret = mv88e6xxx_stats_snapshot(chip, port); 1411 if (ret < 0) 1412 return; 1413 1414 mv88e6xxx_get_stats(chip, port, data); 1415 } 1416 1417 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1418 struct ethtool_eth_mac_stats *mac_stats) 1419 { 1420 struct mv88e6xxx_chip *chip = ds->priv; 1421 int ret; 1422 1423 ret = mv88e6xxx_stats_snapshot(chip, port); 1424 if (ret < 0) 1425 return; 1426 1427 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1428 mv88e6xxx_stats_get_stat(chip, port, \ 1429 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1430 &mac_stats->stats._member) 1431 1432 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1433 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1434 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1435 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1436 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1437 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1438 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1439 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1440 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1441 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1442 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1443 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1444 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1445 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1446 1447 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1448 1449 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1450 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1451 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1452 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1453 } 1454 1455 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1456 struct ethtool_rmon_stats *rmon_stats, 1457 const struct ethtool_rmon_hist_range **ranges) 1458 { 1459 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1460 { 64, 64 }, 1461 { 65, 127 }, 1462 { 128, 255 }, 1463 { 256, 511 }, 1464 { 512, 1023 }, 1465 { 1024, 65535 }, 1466 {} 1467 }; 1468 struct mv88e6xxx_chip *chip = ds->priv; 1469 int ret; 1470 1471 ret = mv88e6xxx_stats_snapshot(chip, port); 1472 if (ret < 0) 1473 return; 1474 1475 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1476 mv88e6xxx_stats_get_stat(chip, port, \ 1477 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1478 &rmon_stats->stats._member) 1479 1480 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1481 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1482 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1483 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1484 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1485 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1486 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1487 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1488 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1489 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1490 1491 #undef MV88E6XXX_RMON_STAT_MAP 1492 1493 *ranges = rmon_ranges; 1494 } 1495 1496 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1497 { 1498 struct mv88e6xxx_chip *chip = ds->priv; 1499 int len; 1500 1501 len = 32 * sizeof(u16); 1502 if (chip->info->ops->serdes_get_regs_len) 1503 len += chip->info->ops->serdes_get_regs_len(chip, port); 1504 1505 return len; 1506 } 1507 1508 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1509 struct ethtool_regs *regs, void *_p) 1510 { 1511 struct mv88e6xxx_chip *chip = ds->priv; 1512 int err; 1513 u16 reg; 1514 u16 *p = _p; 1515 int i; 1516 1517 regs->version = chip->info->prod_num; 1518 1519 memset(p, 0xff, 32 * sizeof(u16)); 1520 1521 mv88e6xxx_reg_lock(chip); 1522 1523 for (i = 0; i < 32; i++) { 1524 1525 err = mv88e6xxx_port_read(chip, port, i, ®); 1526 if (!err) 1527 p[i] = reg; 1528 } 1529 1530 if (chip->info->ops->serdes_get_regs) 1531 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1532 1533 mv88e6xxx_reg_unlock(chip); 1534 } 1535 1536 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1537 struct ethtool_keee *e) 1538 { 1539 /* Nothing to do on the port's MAC */ 1540 return 0; 1541 } 1542 1543 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1544 struct ethtool_keee *e) 1545 { 1546 /* Nothing to do on the port's MAC */ 1547 return 0; 1548 } 1549 1550 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1551 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1552 { 1553 struct dsa_switch *ds = chip->ds; 1554 struct dsa_switch_tree *dst = ds->dst; 1555 struct dsa_port *dp, *other_dp; 1556 bool found = false; 1557 u16 pvlan; 1558 1559 /* dev is a physical switch */ 1560 if (dev <= dst->last_switch) { 1561 list_for_each_entry(dp, &dst->ports, list) { 1562 if (dp->ds->index == dev && dp->index == port) { 1563 /* dp might be a DSA link or a user port, so it 1564 * might or might not have a bridge. 1565 * Use the "found" variable for both cases. 1566 */ 1567 found = true; 1568 break; 1569 } 1570 } 1571 /* dev is a virtual bridge */ 1572 } else { 1573 list_for_each_entry(dp, &dst->ports, list) { 1574 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1575 1576 if (!bridge_num) 1577 continue; 1578 1579 if (bridge_num + dst->last_switch != dev) 1580 continue; 1581 1582 found = true; 1583 break; 1584 } 1585 } 1586 1587 /* Prevent frames from unknown switch or virtual bridge */ 1588 if (!found) 1589 return 0; 1590 1591 /* Frames from DSA links and CPU ports can egress any local port */ 1592 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1593 return mv88e6xxx_port_mask(chip); 1594 1595 pvlan = 0; 1596 1597 /* Frames from standalone user ports can only egress on the 1598 * upstream port. 1599 */ 1600 if (!dsa_port_bridge_dev_get(dp)) 1601 return BIT(dsa_switch_upstream_port(ds)); 1602 1603 /* Frames from bridged user ports can egress any local DSA 1604 * links and CPU ports, as well as any local member of their 1605 * bridge group. 1606 */ 1607 dsa_switch_for_each_port(other_dp, ds) 1608 if (other_dp->type == DSA_PORT_TYPE_CPU || 1609 other_dp->type == DSA_PORT_TYPE_DSA || 1610 dsa_port_bridge_same(dp, other_dp)) 1611 pvlan |= BIT(other_dp->index); 1612 1613 return pvlan; 1614 } 1615 1616 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1617 { 1618 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1619 1620 /* prevent frames from going back out of the port they came in on */ 1621 output_ports &= ~BIT(port); 1622 1623 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1624 } 1625 1626 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1627 u8 state) 1628 { 1629 struct mv88e6xxx_chip *chip = ds->priv; 1630 int err; 1631 1632 mv88e6xxx_reg_lock(chip); 1633 err = mv88e6xxx_port_set_state(chip, port, state); 1634 mv88e6xxx_reg_unlock(chip); 1635 1636 if (err) 1637 dev_err(ds->dev, "p%d: failed to update state\n", port); 1638 } 1639 1640 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1641 { 1642 int err; 1643 1644 if (chip->info->ops->ieee_pri_map) { 1645 err = chip->info->ops->ieee_pri_map(chip); 1646 if (err) 1647 return err; 1648 } 1649 1650 if (chip->info->ops->ip_pri_map) { 1651 err = chip->info->ops->ip_pri_map(chip); 1652 if (err) 1653 return err; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1660 { 1661 struct dsa_switch *ds = chip->ds; 1662 int target, port; 1663 int err; 1664 1665 if (!chip->info->global2_addr) 1666 return 0; 1667 1668 /* Initialize the routing port to the 32 possible target devices */ 1669 for (target = 0; target < 32; target++) { 1670 port = dsa_routing_port(ds, target); 1671 if (port == ds->num_ports) 1672 port = 0x1f; 1673 1674 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1675 if (err) 1676 return err; 1677 } 1678 1679 if (chip->info->ops->set_cascade_port) { 1680 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1681 err = chip->info->ops->set_cascade_port(chip, port); 1682 if (err) 1683 return err; 1684 } 1685 1686 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1687 if (err) 1688 return err; 1689 1690 return 0; 1691 } 1692 1693 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1694 { 1695 /* Clear all trunk masks and mapping */ 1696 if (chip->info->global2_addr) 1697 return mv88e6xxx_g2_trunk_clear(chip); 1698 1699 return 0; 1700 } 1701 1702 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1703 { 1704 if (chip->info->ops->rmu_disable) 1705 return chip->info->ops->rmu_disable(chip); 1706 1707 return 0; 1708 } 1709 1710 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1711 { 1712 if (chip->info->ops->pot_clear) 1713 return chip->info->ops->pot_clear(chip); 1714 1715 return 0; 1716 } 1717 1718 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1719 { 1720 if (chip->info->ops->mgmt_rsvd2cpu) 1721 return chip->info->ops->mgmt_rsvd2cpu(chip); 1722 1723 return 0; 1724 } 1725 1726 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1727 { 1728 int err; 1729 1730 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1731 if (err) 1732 return err; 1733 1734 /* The chips that have a "learn2all" bit in Global1, ATU 1735 * Control are precisely those whose port registers have a 1736 * Message Port bit in Port Control 1 and hence implement 1737 * ->port_setup_message_port. 1738 */ 1739 if (chip->info->ops->port_setup_message_port) { 1740 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1741 if (err) 1742 return err; 1743 } 1744 1745 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1746 } 1747 1748 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1749 { 1750 int port; 1751 int err; 1752 1753 if (!chip->info->ops->irl_init_all) 1754 return 0; 1755 1756 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1757 /* Disable ingress rate limiting by resetting all per port 1758 * ingress rate limit resources to their initial state. 1759 */ 1760 err = chip->info->ops->irl_init_all(chip, port); 1761 if (err) 1762 return err; 1763 } 1764 1765 return 0; 1766 } 1767 1768 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1769 { 1770 if (chip->info->ops->set_switch_mac) { 1771 u8 addr[ETH_ALEN]; 1772 1773 eth_random_addr(addr); 1774 1775 return chip->info->ops->set_switch_mac(chip, addr); 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1782 { 1783 struct dsa_switch_tree *dst = chip->ds->dst; 1784 struct dsa_switch *ds; 1785 struct dsa_port *dp; 1786 u16 pvlan = 0; 1787 1788 if (!mv88e6xxx_has_pvt(chip)) 1789 return 0; 1790 1791 /* Skip the local source device, which uses in-chip port VLAN */ 1792 if (dev != chip->ds->index) { 1793 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1794 1795 ds = dsa_switch_find(dst->index, dev); 1796 dp = ds ? dsa_to_port(ds, port) : NULL; 1797 if (dp && dp->lag) { 1798 /* As the PVT is used to limit flooding of 1799 * FORWARD frames, which use the LAG ID as the 1800 * source port, we must translate dev/port to 1801 * the special "LAG device" in the PVT, using 1802 * the LAG ID (one-based) as the port number 1803 * (zero-based). 1804 */ 1805 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1806 port = dsa_port_lag_id_get(dp) - 1; 1807 } 1808 } 1809 1810 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1811 } 1812 1813 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1814 { 1815 int dev, port; 1816 int err; 1817 1818 if (!mv88e6xxx_has_pvt(chip)) 1819 return 0; 1820 1821 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1822 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1823 */ 1824 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1825 if (err) 1826 return err; 1827 1828 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1829 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1830 err = mv88e6xxx_pvt_map(chip, dev, port); 1831 if (err) 1832 return err; 1833 } 1834 } 1835 1836 return 0; 1837 } 1838 1839 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1840 u16 fid) 1841 { 1842 if (dsa_to_port(chip->ds, port)->lag) 1843 /* Hardware is incapable of fast-aging a LAG through a 1844 * regular ATU move operation. Until we have something 1845 * more fancy in place this is a no-op. 1846 */ 1847 return -EOPNOTSUPP; 1848 1849 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1850 } 1851 1852 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1853 { 1854 struct mv88e6xxx_chip *chip = ds->priv; 1855 int err; 1856 1857 mv88e6xxx_reg_lock(chip); 1858 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1859 mv88e6xxx_reg_unlock(chip); 1860 1861 if (err) 1862 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1863 port, err); 1864 } 1865 1866 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1867 { 1868 if (!mv88e6xxx_max_vid(chip)) 1869 return 0; 1870 1871 return mv88e6xxx_g1_vtu_flush(chip); 1872 } 1873 1874 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1875 struct mv88e6xxx_vtu_entry *entry) 1876 { 1877 int err; 1878 1879 if (!chip->info->ops->vtu_getnext) 1880 return -EOPNOTSUPP; 1881 1882 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1883 entry->valid = false; 1884 1885 err = chip->info->ops->vtu_getnext(chip, entry); 1886 1887 if (entry->vid != vid) 1888 entry->valid = false; 1889 1890 return err; 1891 } 1892 1893 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1894 int (*cb)(struct mv88e6xxx_chip *chip, 1895 const struct mv88e6xxx_vtu_entry *entry, 1896 void *priv), 1897 void *priv) 1898 { 1899 struct mv88e6xxx_vtu_entry entry = { 1900 .vid = mv88e6xxx_max_vid(chip), 1901 .valid = false, 1902 }; 1903 int err; 1904 1905 if (!chip->info->ops->vtu_getnext) 1906 return -EOPNOTSUPP; 1907 1908 do { 1909 err = chip->info->ops->vtu_getnext(chip, &entry); 1910 if (err) 1911 return err; 1912 1913 if (!entry.valid) 1914 break; 1915 1916 err = cb(chip, &entry, priv); 1917 if (err) 1918 return err; 1919 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1920 1921 return 0; 1922 } 1923 1924 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1925 struct mv88e6xxx_vtu_entry *entry) 1926 { 1927 if (!chip->info->ops->vtu_loadpurge) 1928 return -EOPNOTSUPP; 1929 1930 return chip->info->ops->vtu_loadpurge(chip, entry); 1931 } 1932 1933 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1934 { 1935 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1936 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1937 return -ENOSPC; 1938 1939 /* Clear the database */ 1940 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1941 } 1942 1943 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1944 struct mv88e6xxx_stu_entry *entry) 1945 { 1946 if (!chip->info->ops->stu_loadpurge) 1947 return -EOPNOTSUPP; 1948 1949 return chip->info->ops->stu_loadpurge(chip, entry); 1950 } 1951 1952 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1953 { 1954 struct mv88e6xxx_stu_entry stu = { 1955 .valid = true, 1956 .sid = 0 1957 }; 1958 1959 if (!mv88e6xxx_has_stu(chip)) 1960 return 0; 1961 1962 /* Make sure that SID 0 is always valid. This is used by VTU 1963 * entries that do not make use of the STU, e.g. when creating 1964 * a VLAN upper on a port that is also part of a VLAN 1965 * filtering bridge. 1966 */ 1967 return mv88e6xxx_stu_loadpurge(chip, &stu); 1968 } 1969 1970 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1971 { 1972 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1973 struct mv88e6xxx_mst *mst; 1974 1975 __set_bit(0, busy); 1976 1977 list_for_each_entry(mst, &chip->msts, node) 1978 __set_bit(mst->stu.sid, busy); 1979 1980 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1981 1982 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1983 } 1984 1985 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1986 { 1987 struct mv88e6xxx_mst *mst, *tmp; 1988 int err; 1989 1990 if (!sid) 1991 return 0; 1992 1993 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1994 if (mst->stu.sid != sid) 1995 continue; 1996 1997 if (!refcount_dec_and_test(&mst->refcnt)) 1998 return 0; 1999 2000 mst->stu.valid = false; 2001 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2002 if (err) { 2003 refcount_set(&mst->refcnt, 1); 2004 return err; 2005 } 2006 2007 list_del(&mst->node); 2008 kfree(mst); 2009 return 0; 2010 } 2011 2012 return -ENOENT; 2013 } 2014 2015 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 2016 u16 msti, u8 *sid) 2017 { 2018 struct mv88e6xxx_mst *mst; 2019 int err, i; 2020 2021 if (!mv88e6xxx_has_stu(chip)) { 2022 err = -EOPNOTSUPP; 2023 goto err; 2024 } 2025 2026 if (!msti) { 2027 *sid = 0; 2028 return 0; 2029 } 2030 2031 list_for_each_entry(mst, &chip->msts, node) { 2032 if (mst->br == br && mst->msti == msti) { 2033 refcount_inc(&mst->refcnt); 2034 *sid = mst->stu.sid; 2035 return 0; 2036 } 2037 } 2038 2039 err = mv88e6xxx_sid_get(chip, sid); 2040 if (err) 2041 goto err; 2042 2043 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2044 if (!mst) { 2045 err = -ENOMEM; 2046 goto err; 2047 } 2048 2049 INIT_LIST_HEAD(&mst->node); 2050 refcount_set(&mst->refcnt, 1); 2051 mst->br = br; 2052 mst->msti = msti; 2053 mst->stu.valid = true; 2054 mst->stu.sid = *sid; 2055 2056 /* The bridge starts out all ports in the disabled state. But 2057 * a STU state of disabled means to go by the port-global 2058 * state. So we set all user port's initial state to blocking, 2059 * to match the bridge's behavior. 2060 */ 2061 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2062 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2063 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2064 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2065 2066 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2067 if (err) 2068 goto err_free; 2069 2070 list_add_tail(&mst->node, &chip->msts); 2071 return 0; 2072 2073 err_free: 2074 kfree(mst); 2075 err: 2076 return err; 2077 } 2078 2079 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2080 const struct switchdev_mst_state *st) 2081 { 2082 struct dsa_port *dp = dsa_to_port(ds, port); 2083 struct mv88e6xxx_chip *chip = ds->priv; 2084 struct mv88e6xxx_mst *mst; 2085 u8 state; 2086 int err; 2087 2088 if (!mv88e6xxx_has_stu(chip)) 2089 return -EOPNOTSUPP; 2090 2091 switch (st->state) { 2092 case BR_STATE_DISABLED: 2093 case BR_STATE_BLOCKING: 2094 case BR_STATE_LISTENING: 2095 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2096 break; 2097 case BR_STATE_LEARNING: 2098 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2099 break; 2100 case BR_STATE_FORWARDING: 2101 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2102 break; 2103 default: 2104 return -EINVAL; 2105 } 2106 2107 list_for_each_entry(mst, &chip->msts, node) { 2108 if (mst->br == dsa_port_bridge_dev_get(dp) && 2109 mst->msti == st->msti) { 2110 if (mst->stu.state[port] == state) 2111 return 0; 2112 2113 mst->stu.state[port] = state; 2114 mv88e6xxx_reg_lock(chip); 2115 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2116 mv88e6xxx_reg_unlock(chip); 2117 return err; 2118 } 2119 } 2120 2121 return -ENOENT; 2122 } 2123 2124 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2125 u16 vid) 2126 { 2127 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2128 struct mv88e6xxx_chip *chip = ds->priv; 2129 struct mv88e6xxx_vtu_entry vlan; 2130 int err; 2131 2132 /* DSA and CPU ports have to be members of multiple vlans */ 2133 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2134 return 0; 2135 2136 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2137 if (err) 2138 return err; 2139 2140 if (!vlan.valid) 2141 return 0; 2142 2143 dsa_switch_for_each_user_port(other_dp, ds) { 2144 struct net_device *other_br; 2145 2146 if (vlan.member[other_dp->index] == 2147 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2148 continue; 2149 2150 if (dsa_port_bridge_same(dp, other_dp)) 2151 break; /* same bridge, check next VLAN */ 2152 2153 other_br = dsa_port_bridge_dev_get(other_dp); 2154 if (!other_br) 2155 continue; 2156 2157 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2158 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2159 return -EOPNOTSUPP; 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2166 { 2167 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2168 struct net_device *br = dsa_port_bridge_dev_get(dp); 2169 struct mv88e6xxx_port *p = &chip->ports[port]; 2170 u16 pvid = MV88E6XXX_VID_STANDALONE; 2171 bool drop_untagged = false; 2172 int err; 2173 2174 if (br) { 2175 if (br_vlan_enabled(br)) { 2176 pvid = p->bridge_pvid.vid; 2177 drop_untagged = !p->bridge_pvid.valid; 2178 } else { 2179 pvid = MV88E6XXX_VID_BRIDGED; 2180 } 2181 } 2182 2183 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2184 if (err) 2185 return err; 2186 2187 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2188 } 2189 2190 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2191 bool vlan_filtering, 2192 struct netlink_ext_ack *extack) 2193 { 2194 struct mv88e6xxx_chip *chip = ds->priv; 2195 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2196 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2197 int err; 2198 2199 if (!mv88e6xxx_max_vid(chip)) 2200 return -EOPNOTSUPP; 2201 2202 mv88e6xxx_reg_lock(chip); 2203 2204 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2205 if (err) 2206 goto unlock; 2207 2208 err = mv88e6xxx_port_commit_pvid(chip, port); 2209 if (err) 2210 goto unlock; 2211 2212 unlock: 2213 mv88e6xxx_reg_unlock(chip); 2214 2215 return err; 2216 } 2217 2218 static int 2219 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2220 const struct switchdev_obj_port_vlan *vlan) 2221 { 2222 struct mv88e6xxx_chip *chip = ds->priv; 2223 int err; 2224 2225 if (!mv88e6xxx_max_vid(chip)) 2226 return -EOPNOTSUPP; 2227 2228 /* If the requested port doesn't belong to the same bridge as the VLAN 2229 * members, do not support it (yet) and fallback to software VLAN. 2230 */ 2231 mv88e6xxx_reg_lock(chip); 2232 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2233 mv88e6xxx_reg_unlock(chip); 2234 2235 return err; 2236 } 2237 2238 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2239 const unsigned char *addr, u16 vid, 2240 u8 state) 2241 { 2242 struct mv88e6xxx_atu_entry entry; 2243 struct mv88e6xxx_vtu_entry vlan; 2244 u16 fid; 2245 int err; 2246 2247 /* Ports have two private address databases: one for when the port is 2248 * standalone and one for when the port is under a bridge and the 2249 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2250 * address database to remain 100% empty, so we never load an ATU entry 2251 * into a standalone port's database. Therefore, translate the null 2252 * VLAN ID into the port's database used for VLAN-unaware bridging. 2253 */ 2254 if (vid == 0) { 2255 fid = MV88E6XXX_FID_BRIDGED; 2256 } else { 2257 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2258 if (err) 2259 return err; 2260 2261 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2262 if (!vlan.valid) 2263 return -EOPNOTSUPP; 2264 2265 fid = vlan.fid; 2266 } 2267 2268 entry.state = 0; 2269 ether_addr_copy(entry.mac, addr); 2270 eth_addr_dec(entry.mac); 2271 2272 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2273 if (err) 2274 return err; 2275 2276 /* Initialize a fresh ATU entry if it isn't found */ 2277 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2278 memset(&entry, 0, sizeof(entry)); 2279 ether_addr_copy(entry.mac, addr); 2280 } 2281 2282 /* Purge the ATU entry only if no port is using it anymore */ 2283 if (!state) { 2284 entry.portvec &= ~BIT(port); 2285 if (!entry.portvec) 2286 entry.state = 0; 2287 } else { 2288 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2289 entry.portvec = BIT(port); 2290 else 2291 entry.portvec |= BIT(port); 2292 2293 entry.state = state; 2294 } 2295 2296 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2297 } 2298 2299 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2300 const struct mv88e6xxx_policy *policy) 2301 { 2302 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2303 enum mv88e6xxx_policy_action action = policy->action; 2304 const u8 *addr = policy->addr; 2305 u16 vid = policy->vid; 2306 u8 state; 2307 int err; 2308 int id; 2309 2310 if (!chip->info->ops->port_set_policy) 2311 return -EOPNOTSUPP; 2312 2313 switch (mapping) { 2314 case MV88E6XXX_POLICY_MAPPING_DA: 2315 case MV88E6XXX_POLICY_MAPPING_SA: 2316 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2317 state = 0; /* Dissociate the port and address */ 2318 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2319 is_multicast_ether_addr(addr)) 2320 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2321 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2322 is_unicast_ether_addr(addr)) 2323 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2324 else 2325 return -EOPNOTSUPP; 2326 2327 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2328 state); 2329 if (err) 2330 return err; 2331 break; 2332 default: 2333 return -EOPNOTSUPP; 2334 } 2335 2336 /* Skip the port's policy clearing if the mapping is still in use */ 2337 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2338 idr_for_each_entry(&chip->policies, policy, id) 2339 if (policy->port == port && 2340 policy->mapping == mapping && 2341 policy->action != action) 2342 return 0; 2343 2344 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2345 } 2346 2347 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2348 struct ethtool_rx_flow_spec *fs) 2349 { 2350 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2351 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2352 enum mv88e6xxx_policy_mapping mapping; 2353 enum mv88e6xxx_policy_action action; 2354 struct mv88e6xxx_policy *policy; 2355 u16 vid = 0; 2356 u8 *addr; 2357 int err; 2358 int id; 2359 2360 if (fs->location != RX_CLS_LOC_ANY) 2361 return -EINVAL; 2362 2363 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2364 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2365 else 2366 return -EOPNOTSUPP; 2367 2368 switch (fs->flow_type & ~FLOW_EXT) { 2369 case ETHER_FLOW: 2370 if (!is_zero_ether_addr(mac_mask->h_dest) && 2371 is_zero_ether_addr(mac_mask->h_source)) { 2372 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2373 addr = mac_entry->h_dest; 2374 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2375 !is_zero_ether_addr(mac_mask->h_source)) { 2376 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2377 addr = mac_entry->h_source; 2378 } else { 2379 /* Cannot support DA and SA mapping in the same rule */ 2380 return -EOPNOTSUPP; 2381 } 2382 break; 2383 default: 2384 return -EOPNOTSUPP; 2385 } 2386 2387 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2388 if (fs->m_ext.vlan_tci != htons(0xffff)) 2389 return -EOPNOTSUPP; 2390 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2391 } 2392 2393 idr_for_each_entry(&chip->policies, policy, id) { 2394 if (policy->port == port && policy->mapping == mapping && 2395 policy->action == action && policy->vid == vid && 2396 ether_addr_equal(policy->addr, addr)) 2397 return -EEXIST; 2398 } 2399 2400 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2401 if (!policy) 2402 return -ENOMEM; 2403 2404 fs->location = 0; 2405 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2406 GFP_KERNEL); 2407 if (err) { 2408 devm_kfree(chip->dev, policy); 2409 return err; 2410 } 2411 2412 memcpy(&policy->fs, fs, sizeof(*fs)); 2413 ether_addr_copy(policy->addr, addr); 2414 policy->mapping = mapping; 2415 policy->action = action; 2416 policy->port = port; 2417 policy->vid = vid; 2418 2419 err = mv88e6xxx_policy_apply(chip, port, policy); 2420 if (err) { 2421 idr_remove(&chip->policies, fs->location); 2422 devm_kfree(chip->dev, policy); 2423 return err; 2424 } 2425 2426 return 0; 2427 } 2428 2429 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2430 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2431 { 2432 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2433 struct mv88e6xxx_chip *chip = ds->priv; 2434 struct mv88e6xxx_policy *policy; 2435 int err; 2436 int id; 2437 2438 mv88e6xxx_reg_lock(chip); 2439 2440 switch (rxnfc->cmd) { 2441 case ETHTOOL_GRXCLSRLCNT: 2442 rxnfc->data = 0; 2443 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2444 rxnfc->rule_cnt = 0; 2445 idr_for_each_entry(&chip->policies, policy, id) 2446 if (policy->port == port) 2447 rxnfc->rule_cnt++; 2448 err = 0; 2449 break; 2450 case ETHTOOL_GRXCLSRULE: 2451 err = -ENOENT; 2452 policy = idr_find(&chip->policies, fs->location); 2453 if (policy) { 2454 memcpy(fs, &policy->fs, sizeof(*fs)); 2455 err = 0; 2456 } 2457 break; 2458 case ETHTOOL_GRXCLSRLALL: 2459 rxnfc->data = 0; 2460 rxnfc->rule_cnt = 0; 2461 idr_for_each_entry(&chip->policies, policy, id) 2462 if (policy->port == port) 2463 rule_locs[rxnfc->rule_cnt++] = id; 2464 err = 0; 2465 break; 2466 default: 2467 err = -EOPNOTSUPP; 2468 break; 2469 } 2470 2471 mv88e6xxx_reg_unlock(chip); 2472 2473 return err; 2474 } 2475 2476 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2477 struct ethtool_rxnfc *rxnfc) 2478 { 2479 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2480 struct mv88e6xxx_chip *chip = ds->priv; 2481 struct mv88e6xxx_policy *policy; 2482 int err; 2483 2484 mv88e6xxx_reg_lock(chip); 2485 2486 switch (rxnfc->cmd) { 2487 case ETHTOOL_SRXCLSRLINS: 2488 err = mv88e6xxx_policy_insert(chip, port, fs); 2489 break; 2490 case ETHTOOL_SRXCLSRLDEL: 2491 err = -ENOENT; 2492 policy = idr_remove(&chip->policies, fs->location); 2493 if (policy) { 2494 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2495 err = mv88e6xxx_policy_apply(chip, port, policy); 2496 devm_kfree(chip->dev, policy); 2497 } 2498 break; 2499 default: 2500 err = -EOPNOTSUPP; 2501 break; 2502 } 2503 2504 mv88e6xxx_reg_unlock(chip); 2505 2506 return err; 2507 } 2508 2509 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2510 u16 vid) 2511 { 2512 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2513 u8 broadcast[ETH_ALEN]; 2514 2515 eth_broadcast_addr(broadcast); 2516 2517 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2518 } 2519 2520 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2521 { 2522 int port; 2523 int err; 2524 2525 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2526 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2527 struct net_device *brport; 2528 2529 if (dsa_is_unused_port(chip->ds, port)) 2530 continue; 2531 2532 brport = dsa_port_to_bridge_port(dp); 2533 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2534 /* Skip bridged user ports where broadcast 2535 * flooding is disabled. 2536 */ 2537 continue; 2538 2539 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2540 if (err) 2541 return err; 2542 } 2543 2544 return 0; 2545 } 2546 2547 struct mv88e6xxx_port_broadcast_sync_ctx { 2548 int port; 2549 bool flood; 2550 }; 2551 2552 static int 2553 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2554 const struct mv88e6xxx_vtu_entry *vlan, 2555 void *_ctx) 2556 { 2557 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2558 u8 broadcast[ETH_ALEN]; 2559 u8 state; 2560 2561 if (ctx->flood) 2562 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2563 else 2564 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2565 2566 eth_broadcast_addr(broadcast); 2567 2568 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2569 vlan->vid, state); 2570 } 2571 2572 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2573 bool flood) 2574 { 2575 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2576 .port = port, 2577 .flood = flood, 2578 }; 2579 struct mv88e6xxx_vtu_entry vid0 = { 2580 .vid = 0, 2581 }; 2582 int err; 2583 2584 /* Update the port's private database... */ 2585 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2586 if (err) 2587 return err; 2588 2589 /* ...and the database for all VLANs. */ 2590 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2591 &ctx); 2592 } 2593 2594 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2595 u16 vid, u8 member, bool warn) 2596 { 2597 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2598 struct mv88e6xxx_vtu_entry vlan; 2599 int i, err; 2600 2601 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2602 if (err) 2603 return err; 2604 2605 if (!vlan.valid) { 2606 memset(&vlan, 0, sizeof(vlan)); 2607 2608 if (vid == MV88E6XXX_VID_STANDALONE) 2609 vlan.policy = true; 2610 2611 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2612 if (err) 2613 return err; 2614 2615 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2616 if (i == port) 2617 vlan.member[i] = member; 2618 else 2619 vlan.member[i] = non_member; 2620 2621 vlan.vid = vid; 2622 vlan.valid = true; 2623 2624 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2625 if (err) 2626 return err; 2627 2628 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2629 if (err) 2630 return err; 2631 } else if (vlan.member[port] != member) { 2632 vlan.member[port] = member; 2633 2634 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2635 if (err) 2636 return err; 2637 } else if (warn) { 2638 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2639 port, vid); 2640 } 2641 2642 /* Record FID used in SW FID map */ 2643 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2644 2645 return 0; 2646 } 2647 2648 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2649 const struct switchdev_obj_port_vlan *vlan, 2650 struct netlink_ext_ack *extack) 2651 { 2652 struct mv88e6xxx_chip *chip = ds->priv; 2653 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2654 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2655 struct mv88e6xxx_port *p = &chip->ports[port]; 2656 bool warn; 2657 u8 member; 2658 int err; 2659 2660 if (!vlan->vid) 2661 return 0; 2662 2663 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2664 if (err) 2665 return err; 2666 2667 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2668 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2669 else if (untagged) 2670 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2671 else 2672 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2673 2674 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2675 * and then the CPU port. Do not warn for duplicates for the CPU port. 2676 */ 2677 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2678 2679 mv88e6xxx_reg_lock(chip); 2680 2681 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2682 if (err) { 2683 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2684 vlan->vid, untagged ? 'u' : 't'); 2685 goto out; 2686 } 2687 2688 if (pvid) { 2689 p->bridge_pvid.vid = vlan->vid; 2690 p->bridge_pvid.valid = true; 2691 2692 err = mv88e6xxx_port_commit_pvid(chip, port); 2693 if (err) 2694 goto out; 2695 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2696 /* The old pvid was reinstalled as a non-pvid VLAN */ 2697 p->bridge_pvid.valid = false; 2698 2699 err = mv88e6xxx_port_commit_pvid(chip, port); 2700 if (err) 2701 goto out; 2702 } 2703 2704 out: 2705 mv88e6xxx_reg_unlock(chip); 2706 2707 return err; 2708 } 2709 2710 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2711 int port, u16 vid) 2712 { 2713 struct mv88e6xxx_vtu_entry vlan; 2714 int i, err; 2715 2716 if (!vid) 2717 return 0; 2718 2719 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2720 if (err) 2721 return err; 2722 2723 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2724 * tell switchdev that this VLAN is likely handled in software. 2725 */ 2726 if (!vlan.valid || 2727 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2728 return -EOPNOTSUPP; 2729 2730 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2731 2732 /* keep the VLAN unless all ports are excluded */ 2733 vlan.valid = false; 2734 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2735 if (vlan.member[i] != 2736 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2737 vlan.valid = true; 2738 break; 2739 } 2740 } 2741 2742 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2743 if (err) 2744 return err; 2745 2746 if (!vlan.valid) { 2747 err = mv88e6xxx_mst_put(chip, vlan.sid); 2748 if (err) 2749 return err; 2750 2751 /* Record FID freed in SW FID map */ 2752 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2753 } 2754 2755 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2756 } 2757 2758 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2759 const struct switchdev_obj_port_vlan *vlan) 2760 { 2761 struct mv88e6xxx_chip *chip = ds->priv; 2762 struct mv88e6xxx_port *p = &chip->ports[port]; 2763 int err = 0; 2764 u16 pvid; 2765 2766 if (!mv88e6xxx_max_vid(chip)) 2767 return -EOPNOTSUPP; 2768 2769 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2770 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2771 * switchdev workqueue to ensure that all FDB entries are deleted 2772 * before we remove the VLAN. 2773 */ 2774 dsa_flush_workqueue(); 2775 2776 mv88e6xxx_reg_lock(chip); 2777 2778 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2779 if (err) 2780 goto unlock; 2781 2782 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2783 if (err) 2784 goto unlock; 2785 2786 if (vlan->vid == pvid) { 2787 p->bridge_pvid.valid = false; 2788 2789 err = mv88e6xxx_port_commit_pvid(chip, port); 2790 if (err) 2791 goto unlock; 2792 } 2793 2794 unlock: 2795 mv88e6xxx_reg_unlock(chip); 2796 2797 return err; 2798 } 2799 2800 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2801 { 2802 struct mv88e6xxx_chip *chip = ds->priv; 2803 struct mv88e6xxx_vtu_entry vlan; 2804 int err; 2805 2806 mv88e6xxx_reg_lock(chip); 2807 2808 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2809 if (err) 2810 goto unlock; 2811 2812 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2813 2814 unlock: 2815 mv88e6xxx_reg_unlock(chip); 2816 2817 return err; 2818 } 2819 2820 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2821 struct dsa_bridge bridge, 2822 const struct switchdev_vlan_msti *msti) 2823 { 2824 struct mv88e6xxx_chip *chip = ds->priv; 2825 struct mv88e6xxx_vtu_entry vlan; 2826 u8 old_sid, new_sid; 2827 int err; 2828 2829 if (!mv88e6xxx_has_stu(chip)) 2830 return -EOPNOTSUPP; 2831 2832 mv88e6xxx_reg_lock(chip); 2833 2834 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2835 if (err) 2836 goto unlock; 2837 2838 if (!vlan.valid) { 2839 err = -EINVAL; 2840 goto unlock; 2841 } 2842 2843 old_sid = vlan.sid; 2844 2845 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2846 if (err) 2847 goto unlock; 2848 2849 if (new_sid != old_sid) { 2850 vlan.sid = new_sid; 2851 2852 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2853 if (err) { 2854 mv88e6xxx_mst_put(chip, new_sid); 2855 goto unlock; 2856 } 2857 } 2858 2859 err = mv88e6xxx_mst_put(chip, old_sid); 2860 2861 unlock: 2862 mv88e6xxx_reg_unlock(chip); 2863 return err; 2864 } 2865 2866 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2867 const unsigned char *addr, u16 vid, 2868 struct dsa_db db) 2869 { 2870 struct mv88e6xxx_chip *chip = ds->priv; 2871 int err; 2872 2873 mv88e6xxx_reg_lock(chip); 2874 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2875 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2876 mv88e6xxx_reg_unlock(chip); 2877 2878 return err; 2879 } 2880 2881 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2882 const unsigned char *addr, u16 vid, 2883 struct dsa_db db) 2884 { 2885 struct mv88e6xxx_chip *chip = ds->priv; 2886 int err; 2887 2888 mv88e6xxx_reg_lock(chip); 2889 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2890 mv88e6xxx_reg_unlock(chip); 2891 2892 return err; 2893 } 2894 2895 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2896 u16 fid, u16 vid, int port, 2897 dsa_fdb_dump_cb_t *cb, void *data) 2898 { 2899 struct mv88e6xxx_atu_entry addr; 2900 bool is_static; 2901 int err; 2902 2903 addr.state = 0; 2904 eth_broadcast_addr(addr.mac); 2905 2906 do { 2907 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2908 if (err) 2909 return err; 2910 2911 if (!addr.state) 2912 break; 2913 2914 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2915 continue; 2916 2917 if (!is_unicast_ether_addr(addr.mac)) 2918 continue; 2919 2920 is_static = (addr.state == 2921 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2922 err = cb(addr.mac, vid, is_static, data); 2923 if (err) 2924 return err; 2925 } while (!is_broadcast_ether_addr(addr.mac)); 2926 2927 return err; 2928 } 2929 2930 struct mv88e6xxx_port_db_dump_vlan_ctx { 2931 int port; 2932 dsa_fdb_dump_cb_t *cb; 2933 void *data; 2934 }; 2935 2936 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2937 const struct mv88e6xxx_vtu_entry *entry, 2938 void *_data) 2939 { 2940 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2941 2942 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2943 ctx->port, ctx->cb, ctx->data); 2944 } 2945 2946 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2947 dsa_fdb_dump_cb_t *cb, void *data) 2948 { 2949 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2950 .port = port, 2951 .cb = cb, 2952 .data = data, 2953 }; 2954 u16 fid; 2955 int err; 2956 2957 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2958 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2959 if (err) 2960 return err; 2961 2962 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2963 if (err) 2964 return err; 2965 2966 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2967 } 2968 2969 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2970 dsa_fdb_dump_cb_t *cb, void *data) 2971 { 2972 struct mv88e6xxx_chip *chip = ds->priv; 2973 int err; 2974 2975 mv88e6xxx_reg_lock(chip); 2976 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2977 mv88e6xxx_reg_unlock(chip); 2978 2979 return err; 2980 } 2981 2982 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2983 struct dsa_bridge bridge) 2984 { 2985 struct dsa_switch *ds = chip->ds; 2986 struct dsa_switch_tree *dst = ds->dst; 2987 struct dsa_port *dp; 2988 int err; 2989 2990 list_for_each_entry(dp, &dst->ports, list) { 2991 if (dsa_port_offloads_bridge(dp, &bridge)) { 2992 if (dp->ds == ds) { 2993 /* This is a local bridge group member, 2994 * remap its Port VLAN Map. 2995 */ 2996 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2997 if (err) 2998 return err; 2999 } else { 3000 /* This is an external bridge group member, 3001 * remap its cross-chip Port VLAN Table entry. 3002 */ 3003 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 3004 dp->index); 3005 if (err) 3006 return err; 3007 } 3008 } 3009 } 3010 3011 return 0; 3012 } 3013 3014 /* Treat the software bridge as a virtual single-port switch behind the 3015 * CPU and map in the PVT. First dst->last_switch elements are taken by 3016 * physical switches, so start from beyond that range. 3017 */ 3018 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 3019 unsigned int bridge_num) 3020 { 3021 u8 dev = bridge_num + ds->dst->last_switch; 3022 struct mv88e6xxx_chip *chip = ds->priv; 3023 3024 return mv88e6xxx_pvt_map(chip, dev, 0); 3025 } 3026 3027 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3028 struct dsa_bridge bridge, 3029 bool *tx_fwd_offload, 3030 struct netlink_ext_ack *extack) 3031 { 3032 struct mv88e6xxx_chip *chip = ds->priv; 3033 int err; 3034 3035 mv88e6xxx_reg_lock(chip); 3036 3037 err = mv88e6xxx_bridge_map(chip, bridge); 3038 if (err) 3039 goto unlock; 3040 3041 err = mv88e6xxx_port_set_map_da(chip, port, true); 3042 if (err) 3043 goto unlock; 3044 3045 err = mv88e6xxx_port_commit_pvid(chip, port); 3046 if (err) 3047 goto unlock; 3048 3049 if (mv88e6xxx_has_pvt(chip)) { 3050 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3051 if (err) 3052 goto unlock; 3053 3054 *tx_fwd_offload = true; 3055 } 3056 3057 unlock: 3058 mv88e6xxx_reg_unlock(chip); 3059 3060 return err; 3061 } 3062 3063 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3064 struct dsa_bridge bridge) 3065 { 3066 struct mv88e6xxx_chip *chip = ds->priv; 3067 int err; 3068 3069 mv88e6xxx_reg_lock(chip); 3070 3071 if (bridge.tx_fwd_offload && 3072 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3073 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3074 3075 if (mv88e6xxx_bridge_map(chip, bridge) || 3076 mv88e6xxx_port_vlan_map(chip, port)) 3077 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3078 3079 err = mv88e6xxx_port_set_map_da(chip, port, false); 3080 if (err) 3081 dev_err(ds->dev, 3082 "port %d failed to restore map-DA: %pe\n", 3083 port, ERR_PTR(err)); 3084 3085 err = mv88e6xxx_port_commit_pvid(chip, port); 3086 if (err) 3087 dev_err(ds->dev, 3088 "port %d failed to restore standalone pvid: %pe\n", 3089 port, ERR_PTR(err)); 3090 3091 mv88e6xxx_reg_unlock(chip); 3092 } 3093 3094 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3095 int tree_index, int sw_index, 3096 int port, struct dsa_bridge bridge, 3097 struct netlink_ext_ack *extack) 3098 { 3099 struct mv88e6xxx_chip *chip = ds->priv; 3100 int err; 3101 3102 if (tree_index != ds->dst->index) 3103 return 0; 3104 3105 mv88e6xxx_reg_lock(chip); 3106 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3107 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3108 mv88e6xxx_reg_unlock(chip); 3109 3110 return err; 3111 } 3112 3113 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3114 int tree_index, int sw_index, 3115 int port, struct dsa_bridge bridge) 3116 { 3117 struct mv88e6xxx_chip *chip = ds->priv; 3118 3119 if (tree_index != ds->dst->index) 3120 return; 3121 3122 mv88e6xxx_reg_lock(chip); 3123 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3124 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3125 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3126 mv88e6xxx_reg_unlock(chip); 3127 } 3128 3129 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3130 { 3131 if (chip->info->ops->reset) 3132 return chip->info->ops->reset(chip); 3133 3134 return 0; 3135 } 3136 3137 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3138 { 3139 struct gpio_desc *gpiod = chip->reset; 3140 int err; 3141 3142 /* If there is a GPIO connected to the reset pin, toggle it */ 3143 if (gpiod) { 3144 /* If the switch has just been reset and not yet completed 3145 * loading EEPROM, the reset may interrupt the I2C transaction 3146 * mid-byte, causing the first EEPROM read after the reset 3147 * from the wrong location resulting in the switch booting 3148 * to wrong mode and inoperable. 3149 * For this reason, switch families with EEPROM support 3150 * generally wait for EEPROM loads to complete as their pre- 3151 * and post-reset handlers. 3152 */ 3153 if (chip->info->ops->hardware_reset_pre) { 3154 err = chip->info->ops->hardware_reset_pre(chip); 3155 if (err) 3156 dev_err(chip->dev, "pre-reset error: %d\n", err); 3157 } 3158 3159 gpiod_set_value_cansleep(gpiod, 1); 3160 usleep_range(10000, 20000); 3161 gpiod_set_value_cansleep(gpiod, 0); 3162 usleep_range(10000, 20000); 3163 3164 if (chip->info->ops->hardware_reset_post) { 3165 err = chip->info->ops->hardware_reset_post(chip); 3166 if (err) 3167 dev_err(chip->dev, "post-reset error: %d\n", err); 3168 } 3169 } 3170 } 3171 3172 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3173 { 3174 int i, err; 3175 3176 /* Set all ports to the Disabled state */ 3177 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3178 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3179 if (err) 3180 return err; 3181 } 3182 3183 /* Wait for transmit queues to drain, 3184 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3185 */ 3186 usleep_range(2000, 4000); 3187 3188 return 0; 3189 } 3190 3191 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3192 { 3193 int err; 3194 3195 err = mv88e6xxx_disable_ports(chip); 3196 if (err) 3197 return err; 3198 3199 mv88e6xxx_hardware_reset(chip); 3200 3201 return mv88e6xxx_software_reset(chip); 3202 } 3203 3204 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3205 enum mv88e6xxx_frame_mode frame, 3206 enum mv88e6xxx_egress_mode egress, u16 etype) 3207 { 3208 int err; 3209 3210 if (!chip->info->ops->port_set_frame_mode) 3211 return -EOPNOTSUPP; 3212 3213 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3214 if (err) 3215 return err; 3216 3217 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3218 if (err) 3219 return err; 3220 3221 if (chip->info->ops->port_set_ether_type) 3222 return chip->info->ops->port_set_ether_type(chip, port, etype); 3223 3224 return 0; 3225 } 3226 3227 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3228 { 3229 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3230 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3231 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3232 } 3233 3234 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3235 { 3236 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3237 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3238 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3239 } 3240 3241 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3242 { 3243 return mv88e6xxx_set_port_mode(chip, port, 3244 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3245 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3246 ETH_P_EDSA); 3247 } 3248 3249 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3250 { 3251 if (dsa_is_dsa_port(chip->ds, port)) 3252 return mv88e6xxx_set_port_mode_dsa(chip, port); 3253 3254 if (dsa_is_user_port(chip->ds, port)) 3255 return mv88e6xxx_set_port_mode_normal(chip, port); 3256 3257 /* Setup CPU port mode depending on its supported tag format */ 3258 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3259 return mv88e6xxx_set_port_mode_dsa(chip, port); 3260 3261 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3262 return mv88e6xxx_set_port_mode_edsa(chip, port); 3263 3264 return -EINVAL; 3265 } 3266 3267 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3268 { 3269 bool message = dsa_is_dsa_port(chip->ds, port); 3270 3271 return mv88e6xxx_port_set_message_port(chip, port, message); 3272 } 3273 3274 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3275 { 3276 int err; 3277 3278 if (chip->info->ops->port_set_ucast_flood) { 3279 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3280 if (err) 3281 return err; 3282 } 3283 if (chip->info->ops->port_set_mcast_flood) { 3284 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3285 if (err) 3286 return err; 3287 } 3288 3289 return 0; 3290 } 3291 3292 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3293 enum mv88e6xxx_egress_direction direction, 3294 int port) 3295 { 3296 int err; 3297 3298 if (!chip->info->ops->set_egress_port) 3299 return -EOPNOTSUPP; 3300 3301 err = chip->info->ops->set_egress_port(chip, direction, port); 3302 if (err) 3303 return err; 3304 3305 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3306 chip->ingress_dest_port = port; 3307 else 3308 chip->egress_dest_port = port; 3309 3310 return 0; 3311 } 3312 3313 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3314 { 3315 struct dsa_switch *ds = chip->ds; 3316 int upstream_port; 3317 int err; 3318 3319 upstream_port = dsa_upstream_port(ds, port); 3320 if (chip->info->ops->port_set_upstream_port) { 3321 err = chip->info->ops->port_set_upstream_port(chip, port, 3322 upstream_port); 3323 if (err) 3324 return err; 3325 } 3326 3327 if (port == upstream_port) { 3328 if (chip->info->ops->set_cpu_port) { 3329 err = chip->info->ops->set_cpu_port(chip, 3330 upstream_port); 3331 if (err) 3332 return err; 3333 } 3334 3335 err = mv88e6xxx_set_egress_port(chip, 3336 MV88E6XXX_EGRESS_DIR_INGRESS, 3337 upstream_port); 3338 if (err && err != -EOPNOTSUPP) 3339 return err; 3340 3341 err = mv88e6xxx_set_egress_port(chip, 3342 MV88E6XXX_EGRESS_DIR_EGRESS, 3343 upstream_port); 3344 if (err && err != -EOPNOTSUPP) 3345 return err; 3346 } 3347 3348 return 0; 3349 } 3350 3351 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3352 { 3353 struct device_node *phy_handle = NULL; 3354 struct fwnode_handle *ports_fwnode; 3355 struct fwnode_handle *port_fwnode; 3356 struct dsa_switch *ds = chip->ds; 3357 struct mv88e6xxx_port *p; 3358 struct dsa_port *dp; 3359 int tx_amp; 3360 int err; 3361 u16 reg; 3362 u32 val; 3363 3364 p = &chip->ports[port]; 3365 p->chip = chip; 3366 p->port = port; 3367 3368 /* Look up corresponding fwnode if any */ 3369 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3370 if (!ports_fwnode) 3371 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3372 if (ports_fwnode) { 3373 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3374 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3375 continue; 3376 if (val == port) { 3377 p->fwnode = port_fwnode; 3378 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3379 break; 3380 } 3381 } 3382 fwnode_handle_put(ports_fwnode); 3383 } else { 3384 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3385 } 3386 3387 if (chip->info->ops->port_setup_leds) { 3388 err = chip->info->ops->port_setup_leds(chip, port); 3389 if (err && err != -EOPNOTSUPP) 3390 return err; 3391 } 3392 3393 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3394 SPEED_UNFORCED, DUPLEX_UNFORCED, 3395 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3396 if (err) 3397 return err; 3398 3399 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3400 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3401 * tunneling, determine priority by looking at 802.1p and IP 3402 * priority fields (IP prio has precedence), and set STP state 3403 * to Forwarding. 3404 * 3405 * If this is the CPU link, use DSA or EDSA tagging depending 3406 * on which tagging mode was configured. 3407 * 3408 * If this is a link to another switch, use DSA tagging mode. 3409 * 3410 * If this is the upstream port for this switch, enable 3411 * forwarding of unknown unicasts and multicasts. 3412 */ 3413 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3414 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3415 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3416 * by a USER port to the CPU port to allow snooping. 3417 */ 3418 if (dsa_is_user_port(ds, port)) 3419 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3420 3421 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3422 if (err) 3423 return err; 3424 3425 err = mv88e6xxx_setup_port_mode(chip, port); 3426 if (err) 3427 return err; 3428 3429 err = mv88e6xxx_setup_egress_floods(chip, port); 3430 if (err) 3431 return err; 3432 3433 /* Port Control 2: don't force a good FCS, set the MTU size to 3434 * 10222 bytes, disable 802.1q tags checking, don't discard 3435 * tagged or untagged frames on this port, skip destination 3436 * address lookup on user ports, disable ARP mirroring and don't 3437 * send a copy of all transmitted/received frames on this port 3438 * to the CPU. 3439 */ 3440 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3441 if (err) 3442 return err; 3443 3444 err = mv88e6xxx_setup_upstream_port(chip, port); 3445 if (err) 3446 return err; 3447 3448 /* On chips that support it, set all downstream DSA ports' 3449 * VLAN policy to TRAP. In combination with loading 3450 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3451 * provides a better isolation barrier between standalone 3452 * ports, as the ATU is bypassed on any intermediate switches 3453 * between the incoming port and the CPU. 3454 */ 3455 if (dsa_is_downstream_port(ds, port) && 3456 chip->info->ops->port_set_policy) { 3457 err = chip->info->ops->port_set_policy(chip, port, 3458 MV88E6XXX_POLICY_MAPPING_VTU, 3459 MV88E6XXX_POLICY_ACTION_TRAP); 3460 if (err) 3461 return err; 3462 } 3463 3464 /* User ports start out in standalone mode and 802.1Q is 3465 * therefore disabled. On DSA ports, all valid VIDs are always 3466 * loaded in the VTU - therefore, enable 802.1Q in order to take 3467 * advantage of VLAN policy on chips that supports it. 3468 */ 3469 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3470 dsa_is_user_port(ds, port) ? 3471 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3472 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3473 if (err) 3474 return err; 3475 3476 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3477 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3478 * the first free FID. This will be used as the private PVID for 3479 * unbridged ports. Shared (DSA and CPU) ports must also be 3480 * members of this VID, in order to trap all frames assigned to 3481 * it to the CPU. 3482 */ 3483 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3484 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3485 false); 3486 if (err) 3487 return err; 3488 3489 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3490 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3491 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3492 * as the private PVID on ports under a VLAN-unaware bridge. 3493 * Shared (DSA and CPU) ports must also be members of it, to translate 3494 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3495 * relying on their port default FID. 3496 */ 3497 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3498 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3499 false); 3500 if (err) 3501 return err; 3502 3503 if (chip->info->ops->port_set_jumbo_size) { 3504 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3505 if (err) 3506 return err; 3507 } 3508 3509 /* Port Association Vector: disable automatic address learning 3510 * on all user ports since they start out in standalone 3511 * mode. When joining a bridge, learning will be configured to 3512 * match the bridge port settings. Enable learning on all 3513 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3514 * learning process. 3515 * 3516 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3517 * and RefreshLocked. I.e. setup standard automatic learning. 3518 */ 3519 if (dsa_is_user_port(ds, port)) 3520 reg = 0; 3521 else 3522 reg = 1 << port; 3523 3524 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3525 reg); 3526 if (err) 3527 return err; 3528 3529 /* Egress rate control 2: disable egress rate control. */ 3530 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3531 0x0000); 3532 if (err) 3533 return err; 3534 3535 if (chip->info->ops->port_pause_limit) { 3536 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3537 if (err) 3538 return err; 3539 } 3540 3541 if (chip->info->ops->port_disable_learn_limit) { 3542 err = chip->info->ops->port_disable_learn_limit(chip, port); 3543 if (err) 3544 return err; 3545 } 3546 3547 if (chip->info->ops->port_disable_pri_override) { 3548 err = chip->info->ops->port_disable_pri_override(chip, port); 3549 if (err) 3550 return err; 3551 } 3552 3553 if (chip->info->ops->port_tag_remap) { 3554 err = chip->info->ops->port_tag_remap(chip, port); 3555 if (err) 3556 return err; 3557 } 3558 3559 if (chip->info->ops->port_egress_rate_limiting) { 3560 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3561 if (err) 3562 return err; 3563 } 3564 3565 if (chip->info->ops->port_setup_message_port) { 3566 err = chip->info->ops->port_setup_message_port(chip, port); 3567 if (err) 3568 return err; 3569 } 3570 3571 if (chip->info->ops->serdes_set_tx_amplitude) { 3572 dp = dsa_to_port(ds, port); 3573 if (dp) 3574 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3575 3576 if (phy_handle && !of_property_read_u32(phy_handle, 3577 "tx-p2p-microvolt", 3578 &tx_amp)) 3579 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3580 port, tx_amp); 3581 if (phy_handle) { 3582 of_node_put(phy_handle); 3583 if (err) 3584 return err; 3585 } 3586 } 3587 3588 /* Port based VLAN map: give each port the same default address 3589 * database, and allow bidirectional communication between the 3590 * CPU and DSA port(s), and the other ports. 3591 */ 3592 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3593 if (err) 3594 return err; 3595 3596 err = mv88e6xxx_port_vlan_map(chip, port); 3597 if (err) 3598 return err; 3599 3600 /* Default VLAN ID and priority: don't set a default VLAN 3601 * ID, and set the default packet priority to zero. 3602 */ 3603 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3604 } 3605 3606 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3607 { 3608 struct mv88e6xxx_chip *chip = ds->priv; 3609 3610 if (chip->info->ops->port_set_jumbo_size) 3611 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3612 else if (chip->info->ops->set_max_frame_size) 3613 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3614 return ETH_DATA_LEN; 3615 } 3616 3617 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3618 { 3619 struct mv88e6xxx_chip *chip = ds->priv; 3620 int ret = 0; 3621 3622 /* For families where we don't know how to alter the MTU, 3623 * just accept any value up to ETH_DATA_LEN 3624 */ 3625 if (!chip->info->ops->port_set_jumbo_size && 3626 !chip->info->ops->set_max_frame_size) { 3627 if (new_mtu > ETH_DATA_LEN) 3628 return -EINVAL; 3629 3630 return 0; 3631 } 3632 3633 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3634 new_mtu += EDSA_HLEN; 3635 3636 mv88e6xxx_reg_lock(chip); 3637 if (chip->info->ops->port_set_jumbo_size) 3638 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3639 else if (chip->info->ops->set_max_frame_size && 3640 dsa_is_cpu_port(ds, port)) 3641 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3642 mv88e6xxx_reg_unlock(chip); 3643 3644 return ret; 3645 } 3646 3647 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3648 unsigned int ageing_time) 3649 { 3650 struct mv88e6xxx_chip *chip = ds->priv; 3651 int err; 3652 3653 mv88e6xxx_reg_lock(chip); 3654 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3655 mv88e6xxx_reg_unlock(chip); 3656 3657 return err; 3658 } 3659 3660 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3661 { 3662 int err; 3663 3664 /* Initialize the statistics unit */ 3665 if (chip->info->ops->stats_set_histogram) { 3666 err = chip->info->ops->stats_set_histogram(chip); 3667 if (err) 3668 return err; 3669 } 3670 3671 return mv88e6xxx_g1_stats_clear(chip); 3672 } 3673 3674 /* Check if the errata has already been applied. */ 3675 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3676 { 3677 int port; 3678 int err; 3679 u16 val; 3680 3681 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3682 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3683 if (err) { 3684 dev_err(chip->dev, 3685 "Error reading hidden register: %d\n", err); 3686 return false; 3687 } 3688 if (val != 0x01c0) 3689 return false; 3690 } 3691 3692 return true; 3693 } 3694 3695 /* The 6390 copper ports have an errata which require poking magic 3696 * values into undocumented hidden registers and then performing a 3697 * software reset. 3698 */ 3699 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3700 { 3701 int port; 3702 int err; 3703 3704 if (mv88e6390_setup_errata_applied(chip)) 3705 return 0; 3706 3707 /* Set the ports into blocking mode */ 3708 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3709 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3710 if (err) 3711 return err; 3712 } 3713 3714 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3715 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3716 if (err) 3717 return err; 3718 } 3719 3720 return mv88e6xxx_software_reset(chip); 3721 } 3722 3723 /* prod_id for switch families which do not have a PHY model number */ 3724 static const u16 family_prod_id_table[] = { 3725 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3726 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3727 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3728 }; 3729 3730 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3731 { 3732 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3733 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3734 u16 prod_id; 3735 u16 val; 3736 int err; 3737 3738 if (!chip->info->ops->phy_read) 3739 return -EOPNOTSUPP; 3740 3741 mv88e6xxx_reg_lock(chip); 3742 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3743 mv88e6xxx_reg_unlock(chip); 3744 3745 /* Some internal PHYs don't have a model number. */ 3746 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3747 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3748 prod_id = family_prod_id_table[chip->info->family]; 3749 if (prod_id) 3750 val |= prod_id >> 4; 3751 } 3752 3753 return err ? err : val; 3754 } 3755 3756 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3757 int reg) 3758 { 3759 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3760 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3761 u16 val; 3762 int err; 3763 3764 if (!chip->info->ops->phy_read_c45) 3765 return -ENODEV; 3766 3767 mv88e6xxx_reg_lock(chip); 3768 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3769 mv88e6xxx_reg_unlock(chip); 3770 3771 return err ? err : val; 3772 } 3773 3774 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3775 { 3776 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3777 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3778 int err; 3779 3780 if (!chip->info->ops->phy_write) 3781 return -EOPNOTSUPP; 3782 3783 mv88e6xxx_reg_lock(chip); 3784 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3785 mv88e6xxx_reg_unlock(chip); 3786 3787 return err; 3788 } 3789 3790 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3791 int reg, u16 val) 3792 { 3793 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3794 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3795 int err; 3796 3797 if (!chip->info->ops->phy_write_c45) 3798 return -EOPNOTSUPP; 3799 3800 mv88e6xxx_reg_lock(chip); 3801 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3802 mv88e6xxx_reg_unlock(chip); 3803 3804 return err; 3805 } 3806 3807 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3808 struct device_node *np, 3809 bool external) 3810 { 3811 static int index; 3812 struct mv88e6xxx_mdio_bus *mdio_bus; 3813 struct mii_bus *bus; 3814 int err; 3815 3816 if (external) { 3817 mv88e6xxx_reg_lock(chip); 3818 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3819 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3820 else 3821 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3822 mv88e6xxx_reg_unlock(chip); 3823 3824 if (err) 3825 return err; 3826 } 3827 3828 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3829 if (!bus) 3830 return -ENOMEM; 3831 3832 mdio_bus = bus->priv; 3833 mdio_bus->bus = bus; 3834 mdio_bus->chip = chip; 3835 INIT_LIST_HEAD(&mdio_bus->list); 3836 mdio_bus->external = external; 3837 3838 if (np) { 3839 bus->name = np->full_name; 3840 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3841 } else { 3842 bus->name = "mv88e6xxx SMI"; 3843 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3844 } 3845 3846 bus->read = mv88e6xxx_mdio_read; 3847 bus->write = mv88e6xxx_mdio_write; 3848 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3849 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3850 bus->parent = chip->dev; 3851 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3852 mv88e6xxx_num_ports(chip) - 1, 3853 chip->info->phy_base_addr); 3854 3855 if (!external) { 3856 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3857 if (err) 3858 goto out; 3859 } 3860 3861 err = of_mdiobus_register(bus, np); 3862 if (err) { 3863 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3864 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3865 goto out; 3866 } 3867 3868 if (external) 3869 list_add_tail(&mdio_bus->list, &chip->mdios); 3870 else 3871 list_add(&mdio_bus->list, &chip->mdios); 3872 3873 return 0; 3874 3875 out: 3876 mdiobus_free(bus); 3877 return err; 3878 } 3879 3880 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3881 3882 { 3883 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3884 struct mii_bus *bus; 3885 3886 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3887 bus = mdio_bus->bus; 3888 3889 if (!mdio_bus->external) 3890 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3891 3892 mdiobus_unregister(bus); 3893 mdiobus_free(bus); 3894 } 3895 } 3896 3897 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3898 { 3899 struct device_node *np = chip->dev->of_node; 3900 struct device_node *child; 3901 int err; 3902 3903 /* Always register one mdio bus for the internal/default mdio 3904 * bus. This maybe represented in the device tree, but is 3905 * optional. 3906 */ 3907 child = of_get_child_by_name(np, "mdio"); 3908 err = mv88e6xxx_mdio_register(chip, child, false); 3909 of_node_put(child); 3910 if (err) 3911 return err; 3912 3913 /* Walk the device tree, and see if there are any other nodes 3914 * which say they are compatible with the external mdio 3915 * bus. 3916 */ 3917 for_each_available_child_of_node(np, child) { 3918 if (of_device_is_compatible( 3919 child, "marvell,mv88e6xxx-mdio-external")) { 3920 err = mv88e6xxx_mdio_register(chip, child, true); 3921 if (err) { 3922 mv88e6xxx_mdios_unregister(chip); 3923 of_node_put(child); 3924 return err; 3925 } 3926 } 3927 } 3928 3929 return 0; 3930 } 3931 3932 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3933 { 3934 struct mv88e6xxx_chip *chip = ds->priv; 3935 3936 mv88e6xxx_teardown_devlink_params(ds); 3937 dsa_devlink_resources_unregister(ds); 3938 mv88e6xxx_teardown_devlink_regions_global(ds); 3939 mv88e6xxx_mdios_unregister(chip); 3940 } 3941 3942 static int mv88e6xxx_setup(struct dsa_switch *ds) 3943 { 3944 struct mv88e6xxx_chip *chip = ds->priv; 3945 u8 cmode; 3946 int err; 3947 int i; 3948 3949 err = mv88e6xxx_mdios_register(chip); 3950 if (err) 3951 return err; 3952 3953 chip->ds = ds; 3954 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3955 3956 /* Since virtual bridges are mapped in the PVT, the number we support 3957 * depends on the physical switch topology. We need to let DSA figure 3958 * that out and therefore we cannot set this at dsa_register_switch() 3959 * time. 3960 */ 3961 if (mv88e6xxx_has_pvt(chip)) 3962 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3963 ds->dst->last_switch - 1; 3964 3965 mv88e6xxx_reg_lock(chip); 3966 3967 if (chip->info->ops->setup_errata) { 3968 err = chip->info->ops->setup_errata(chip); 3969 if (err) 3970 goto unlock; 3971 } 3972 3973 /* Cache the cmode of each port. */ 3974 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3975 if (chip->info->ops->port_get_cmode) { 3976 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3977 if (err) 3978 goto unlock; 3979 3980 chip->ports[i].cmode = cmode; 3981 } 3982 } 3983 3984 err = mv88e6xxx_vtu_setup(chip); 3985 if (err) 3986 goto unlock; 3987 3988 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3989 * VTU, thereby also flushing the STU). 3990 */ 3991 err = mv88e6xxx_stu_setup(chip); 3992 if (err) 3993 goto unlock; 3994 3995 /* Setup Switch Port Registers */ 3996 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3997 if (dsa_is_unused_port(ds, i)) 3998 continue; 3999 4000 /* Prevent the use of an invalid port. */ 4001 if (mv88e6xxx_is_invalid_port(chip, i)) { 4002 dev_err(chip->dev, "port %d is invalid\n", i); 4003 err = -EINVAL; 4004 goto unlock; 4005 } 4006 4007 err = mv88e6xxx_setup_port(chip, i); 4008 if (err) 4009 goto unlock; 4010 } 4011 4012 err = mv88e6xxx_irl_setup(chip); 4013 if (err) 4014 goto unlock; 4015 4016 err = mv88e6xxx_mac_setup(chip); 4017 if (err) 4018 goto unlock; 4019 4020 err = mv88e6xxx_phy_setup(chip); 4021 if (err) 4022 goto unlock; 4023 4024 err = mv88e6xxx_pvt_setup(chip); 4025 if (err) 4026 goto unlock; 4027 4028 err = mv88e6xxx_atu_setup(chip); 4029 if (err) 4030 goto unlock; 4031 4032 err = mv88e6xxx_broadcast_setup(chip, 0); 4033 if (err) 4034 goto unlock; 4035 4036 err = mv88e6xxx_pot_setup(chip); 4037 if (err) 4038 goto unlock; 4039 4040 err = mv88e6xxx_rmu_setup(chip); 4041 if (err) 4042 goto unlock; 4043 4044 err = mv88e6xxx_rsvd2cpu_setup(chip); 4045 if (err) 4046 goto unlock; 4047 4048 err = mv88e6xxx_trunk_setup(chip); 4049 if (err) 4050 goto unlock; 4051 4052 err = mv88e6xxx_devmap_setup(chip); 4053 if (err) 4054 goto unlock; 4055 4056 err = mv88e6xxx_pri_setup(chip); 4057 if (err) 4058 goto unlock; 4059 4060 /* Setup PTP Hardware Clock and timestamping */ 4061 if (chip->info->ptp_support) { 4062 err = mv88e6xxx_ptp_setup(chip); 4063 if (err) 4064 goto unlock; 4065 4066 err = mv88e6xxx_hwtstamp_setup(chip); 4067 if (err) 4068 goto unlock; 4069 } 4070 4071 err = mv88e6xxx_stats_setup(chip); 4072 if (err) 4073 goto unlock; 4074 4075 unlock: 4076 mv88e6xxx_reg_unlock(chip); 4077 4078 if (err) 4079 goto out_mdios; 4080 4081 /* Have to be called without holding the register lock, since 4082 * they take the devlink lock, and we later take the locks in 4083 * the reverse order when getting/setting parameters or 4084 * resource occupancy. 4085 */ 4086 err = mv88e6xxx_setup_devlink_resources(ds); 4087 if (err) 4088 goto out_mdios; 4089 4090 err = mv88e6xxx_setup_devlink_params(ds); 4091 if (err) 4092 goto out_resources; 4093 4094 err = mv88e6xxx_setup_devlink_regions_global(ds); 4095 if (err) 4096 goto out_params; 4097 4098 return 0; 4099 4100 out_params: 4101 mv88e6xxx_teardown_devlink_params(ds); 4102 out_resources: 4103 dsa_devlink_resources_unregister(ds); 4104 out_mdios: 4105 mv88e6xxx_mdios_unregister(chip); 4106 4107 return err; 4108 } 4109 4110 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4111 { 4112 struct mv88e6xxx_chip *chip = ds->priv; 4113 int err; 4114 4115 if (chip->info->ops->pcs_ops && 4116 chip->info->ops->pcs_ops->pcs_init) { 4117 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4118 if (err) 4119 return err; 4120 } 4121 4122 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4123 } 4124 4125 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4126 { 4127 struct mv88e6xxx_chip *chip = ds->priv; 4128 4129 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4130 4131 if (chip->info->ops->pcs_ops && 4132 chip->info->ops->pcs_ops->pcs_teardown) 4133 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4134 } 4135 4136 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4137 { 4138 struct mv88e6xxx_chip *chip = ds->priv; 4139 4140 return chip->eeprom_len; 4141 } 4142 4143 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4144 struct ethtool_eeprom *eeprom, u8 *data) 4145 { 4146 struct mv88e6xxx_chip *chip = ds->priv; 4147 int err; 4148 4149 if (!chip->info->ops->get_eeprom) 4150 return -EOPNOTSUPP; 4151 4152 mv88e6xxx_reg_lock(chip); 4153 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4154 mv88e6xxx_reg_unlock(chip); 4155 4156 if (err) 4157 return err; 4158 4159 eeprom->magic = 0xc3ec4951; 4160 4161 return 0; 4162 } 4163 4164 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4165 struct ethtool_eeprom *eeprom, u8 *data) 4166 { 4167 struct mv88e6xxx_chip *chip = ds->priv; 4168 int err; 4169 4170 if (!chip->info->ops->set_eeprom) 4171 return -EOPNOTSUPP; 4172 4173 if (eeprom->magic != 0xc3ec4951) 4174 return -EINVAL; 4175 4176 mv88e6xxx_reg_lock(chip); 4177 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4178 mv88e6xxx_reg_unlock(chip); 4179 4180 return err; 4181 } 4182 4183 static const struct mv88e6xxx_ops mv88e6085_ops = { 4184 /* MV88E6XXX_FAMILY_6097 */ 4185 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4186 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4187 .irl_init_all = mv88e6352_g2_irl_init_all, 4188 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4189 .phy_read = mv88e6185_phy_ppu_read, 4190 .phy_write = mv88e6185_phy_ppu_write, 4191 .port_set_link = mv88e6xxx_port_set_link, 4192 .port_sync_link = mv88e6xxx_port_sync_link, 4193 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4194 .port_tag_remap = mv88e6095_port_tag_remap, 4195 .port_set_policy = mv88e6352_port_set_policy, 4196 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4197 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4198 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4199 .port_set_ether_type = mv88e6351_port_set_ether_type, 4200 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4201 .port_pause_limit = mv88e6097_port_pause_limit, 4202 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4203 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4204 .port_get_cmode = mv88e6185_port_get_cmode, 4205 .port_setup_message_port = mv88e6xxx_setup_message_port, 4206 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4207 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4208 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4209 .stats_get_strings = mv88e6095_stats_get_strings, 4210 .stats_get_stat = mv88e6095_stats_get_stat, 4211 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4212 .set_egress_port = mv88e6095_g1_set_egress_port, 4213 .watchdog_ops = &mv88e6097_watchdog_ops, 4214 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4215 .pot_clear = mv88e6xxx_g2_pot_clear, 4216 .ppu_enable = mv88e6185_g1_ppu_enable, 4217 .ppu_disable = mv88e6185_g1_ppu_disable, 4218 .reset = mv88e6185_g1_reset, 4219 .rmu_disable = mv88e6085_g1_rmu_disable, 4220 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4221 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4222 .stu_getnext = mv88e6352_g1_stu_getnext, 4223 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4224 .phylink_get_caps = mv88e6185_phylink_get_caps, 4225 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4226 }; 4227 4228 static const struct mv88e6xxx_ops mv88e6095_ops = { 4229 /* MV88E6XXX_FAMILY_6095 */ 4230 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4231 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4232 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4233 .phy_read = mv88e6185_phy_ppu_read, 4234 .phy_write = mv88e6185_phy_ppu_write, 4235 .port_set_link = mv88e6xxx_port_set_link, 4236 .port_sync_link = mv88e6185_port_sync_link, 4237 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4238 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4239 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4240 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4241 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4242 .port_get_cmode = mv88e6185_port_get_cmode, 4243 .port_setup_message_port = mv88e6xxx_setup_message_port, 4244 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4245 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4246 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4247 .stats_get_strings = mv88e6095_stats_get_strings, 4248 .stats_get_stat = mv88e6095_stats_get_stat, 4249 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4250 .ppu_enable = mv88e6185_g1_ppu_enable, 4251 .ppu_disable = mv88e6185_g1_ppu_disable, 4252 .reset = mv88e6185_g1_reset, 4253 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4254 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4255 .phylink_get_caps = mv88e6095_phylink_get_caps, 4256 .pcs_ops = &mv88e6185_pcs_ops, 4257 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4258 }; 4259 4260 static const struct mv88e6xxx_ops mv88e6097_ops = { 4261 /* MV88E6XXX_FAMILY_6097 */ 4262 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4263 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4264 .irl_init_all = mv88e6352_g2_irl_init_all, 4265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4266 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4267 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4268 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4269 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4270 .port_set_link = mv88e6xxx_port_set_link, 4271 .port_sync_link = mv88e6185_port_sync_link, 4272 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4273 .port_tag_remap = mv88e6095_port_tag_remap, 4274 .port_set_policy = mv88e6352_port_set_policy, 4275 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4276 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4277 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4278 .port_set_ether_type = mv88e6351_port_set_ether_type, 4279 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4280 .port_pause_limit = mv88e6097_port_pause_limit, 4281 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4282 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4283 .port_get_cmode = mv88e6185_port_get_cmode, 4284 .port_setup_message_port = mv88e6xxx_setup_message_port, 4285 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4286 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4287 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4288 .stats_get_strings = mv88e6095_stats_get_strings, 4289 .stats_get_stat = mv88e6095_stats_get_stat, 4290 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4291 .set_egress_port = mv88e6095_g1_set_egress_port, 4292 .watchdog_ops = &mv88e6097_watchdog_ops, 4293 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4294 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4295 .pot_clear = mv88e6xxx_g2_pot_clear, 4296 .reset = mv88e6352_g1_reset, 4297 .rmu_disable = mv88e6085_g1_rmu_disable, 4298 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4299 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4300 .phylink_get_caps = mv88e6095_phylink_get_caps, 4301 .pcs_ops = &mv88e6185_pcs_ops, 4302 .stu_getnext = mv88e6352_g1_stu_getnext, 4303 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4304 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4305 }; 4306 4307 static const struct mv88e6xxx_ops mv88e6123_ops = { 4308 /* MV88E6XXX_FAMILY_6165 */ 4309 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4310 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4311 .irl_init_all = mv88e6352_g2_irl_init_all, 4312 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4313 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4314 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4315 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4316 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4317 .port_set_link = mv88e6xxx_port_set_link, 4318 .port_sync_link = mv88e6xxx_port_sync_link, 4319 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4320 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4321 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4322 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4323 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4324 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4325 .port_get_cmode = mv88e6185_port_get_cmode, 4326 .port_setup_message_port = mv88e6xxx_setup_message_port, 4327 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4328 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4329 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4330 .stats_get_strings = mv88e6095_stats_get_strings, 4331 .stats_get_stat = mv88e6095_stats_get_stat, 4332 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4333 .set_egress_port = mv88e6095_g1_set_egress_port, 4334 .watchdog_ops = &mv88e6097_watchdog_ops, 4335 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4336 .pot_clear = mv88e6xxx_g2_pot_clear, 4337 .reset = mv88e6352_g1_reset, 4338 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4339 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4340 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4341 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4342 .stu_getnext = mv88e6352_g1_stu_getnext, 4343 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4344 .phylink_get_caps = mv88e6185_phylink_get_caps, 4345 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4346 }; 4347 4348 static const struct mv88e6xxx_ops mv88e6131_ops = { 4349 /* MV88E6XXX_FAMILY_6185 */ 4350 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4351 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4352 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4353 .phy_read = mv88e6185_phy_ppu_read, 4354 .phy_write = mv88e6185_phy_ppu_write, 4355 .port_set_link = mv88e6xxx_port_set_link, 4356 .port_sync_link = mv88e6xxx_port_sync_link, 4357 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4358 .port_tag_remap = mv88e6095_port_tag_remap, 4359 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4360 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4361 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4362 .port_set_ether_type = mv88e6351_port_set_ether_type, 4363 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4364 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4365 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4366 .port_pause_limit = mv88e6097_port_pause_limit, 4367 .port_set_pause = mv88e6185_port_set_pause, 4368 .port_get_cmode = mv88e6185_port_get_cmode, 4369 .port_setup_message_port = mv88e6xxx_setup_message_port, 4370 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4371 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4372 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4373 .stats_get_strings = mv88e6095_stats_get_strings, 4374 .stats_get_stat = mv88e6095_stats_get_stat, 4375 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4376 .set_egress_port = mv88e6095_g1_set_egress_port, 4377 .watchdog_ops = &mv88e6097_watchdog_ops, 4378 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4379 .ppu_enable = mv88e6185_g1_ppu_enable, 4380 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4381 .ppu_disable = mv88e6185_g1_ppu_disable, 4382 .reset = mv88e6185_g1_reset, 4383 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4384 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4385 .phylink_get_caps = mv88e6185_phylink_get_caps, 4386 }; 4387 4388 static const struct mv88e6xxx_ops mv88e6141_ops = { 4389 /* MV88E6XXX_FAMILY_6341 */ 4390 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4391 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4392 .irl_init_all = mv88e6352_g2_irl_init_all, 4393 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4394 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4395 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4396 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4397 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4398 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4399 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4400 .port_set_link = mv88e6xxx_port_set_link, 4401 .port_sync_link = mv88e6xxx_port_sync_link, 4402 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4403 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4404 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4405 .port_tag_remap = mv88e6095_port_tag_remap, 4406 .port_set_policy = mv88e6352_port_set_policy, 4407 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4408 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4409 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4410 .port_set_ether_type = mv88e6351_port_set_ether_type, 4411 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4412 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4413 .port_pause_limit = mv88e6097_port_pause_limit, 4414 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4415 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4416 .port_get_cmode = mv88e6352_port_get_cmode, 4417 .port_set_cmode = mv88e6341_port_set_cmode, 4418 .port_setup_message_port = mv88e6xxx_setup_message_port, 4419 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4420 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4421 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4422 .stats_get_strings = mv88e6320_stats_get_strings, 4423 .stats_get_stat = mv88e6390_stats_get_stat, 4424 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4425 .set_egress_port = mv88e6390_g1_set_egress_port, 4426 .watchdog_ops = &mv88e6390_watchdog_ops, 4427 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4428 .pot_clear = mv88e6xxx_g2_pot_clear, 4429 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4430 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4431 .reset = mv88e6352_g1_reset, 4432 .rmu_disable = mv88e6390_g1_rmu_disable, 4433 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4434 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4435 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4436 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4437 .stu_getnext = mv88e6352_g1_stu_getnext, 4438 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4439 .serdes_get_lane = mv88e6341_serdes_get_lane, 4440 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4441 .gpio_ops = &mv88e6352_gpio_ops, 4442 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4443 .serdes_get_strings = mv88e6390_serdes_get_strings, 4444 .serdes_get_stats = mv88e6390_serdes_get_stats, 4445 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4446 .serdes_get_regs = mv88e6390_serdes_get_regs, 4447 .phylink_get_caps = mv88e6341_phylink_get_caps, 4448 .pcs_ops = &mv88e6390_pcs_ops, 4449 }; 4450 4451 static const struct mv88e6xxx_ops mv88e6161_ops = { 4452 /* MV88E6XXX_FAMILY_6165 */ 4453 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4454 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4455 .irl_init_all = mv88e6352_g2_irl_init_all, 4456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4457 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4458 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4459 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4460 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4461 .port_set_link = mv88e6xxx_port_set_link, 4462 .port_sync_link = mv88e6xxx_port_sync_link, 4463 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4464 .port_tag_remap = mv88e6095_port_tag_remap, 4465 .port_set_policy = mv88e6352_port_set_policy, 4466 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4467 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4468 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4469 .port_set_ether_type = mv88e6351_port_set_ether_type, 4470 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4471 .port_pause_limit = mv88e6097_port_pause_limit, 4472 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4473 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4474 .port_get_cmode = mv88e6185_port_get_cmode, 4475 .port_setup_message_port = mv88e6xxx_setup_message_port, 4476 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4477 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4478 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4479 .stats_get_strings = mv88e6095_stats_get_strings, 4480 .stats_get_stat = mv88e6095_stats_get_stat, 4481 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4482 .set_egress_port = mv88e6095_g1_set_egress_port, 4483 .watchdog_ops = &mv88e6097_watchdog_ops, 4484 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4485 .pot_clear = mv88e6xxx_g2_pot_clear, 4486 .reset = mv88e6352_g1_reset, 4487 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4488 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4489 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4490 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4491 .stu_getnext = mv88e6352_g1_stu_getnext, 4492 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4493 .avb_ops = &mv88e6165_avb_ops, 4494 .ptp_ops = &mv88e6165_ptp_ops, 4495 .phylink_get_caps = mv88e6185_phylink_get_caps, 4496 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4497 }; 4498 4499 static const struct mv88e6xxx_ops mv88e6165_ops = { 4500 /* MV88E6XXX_FAMILY_6165 */ 4501 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4502 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4503 .irl_init_all = mv88e6352_g2_irl_init_all, 4504 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4505 .phy_read = mv88e6165_phy_read, 4506 .phy_write = mv88e6165_phy_write, 4507 .port_set_link = mv88e6xxx_port_set_link, 4508 .port_sync_link = mv88e6xxx_port_sync_link, 4509 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4510 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4511 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4512 .port_get_cmode = mv88e6185_port_get_cmode, 4513 .port_setup_message_port = mv88e6xxx_setup_message_port, 4514 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4515 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4516 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4517 .stats_get_strings = mv88e6095_stats_get_strings, 4518 .stats_get_stat = mv88e6095_stats_get_stat, 4519 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4520 .set_egress_port = mv88e6095_g1_set_egress_port, 4521 .watchdog_ops = &mv88e6097_watchdog_ops, 4522 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4523 .pot_clear = mv88e6xxx_g2_pot_clear, 4524 .reset = mv88e6352_g1_reset, 4525 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4526 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4527 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4528 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4529 .stu_getnext = mv88e6352_g1_stu_getnext, 4530 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4531 .avb_ops = &mv88e6165_avb_ops, 4532 .ptp_ops = &mv88e6165_ptp_ops, 4533 .phylink_get_caps = mv88e6185_phylink_get_caps, 4534 }; 4535 4536 static const struct mv88e6xxx_ops mv88e6171_ops = { 4537 /* MV88E6XXX_FAMILY_6351 */ 4538 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4539 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4540 .irl_init_all = mv88e6352_g2_irl_init_all, 4541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4542 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4543 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4544 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4545 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4546 .port_set_link = mv88e6xxx_port_set_link, 4547 .port_sync_link = mv88e6xxx_port_sync_link, 4548 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4549 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4550 .port_tag_remap = mv88e6095_port_tag_remap, 4551 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4552 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4553 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4554 .port_set_ether_type = mv88e6351_port_set_ether_type, 4555 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4556 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4557 .port_pause_limit = mv88e6097_port_pause_limit, 4558 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4559 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4560 .port_get_cmode = mv88e6352_port_get_cmode, 4561 .port_setup_message_port = mv88e6xxx_setup_message_port, 4562 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4563 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4564 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4565 .stats_get_strings = mv88e6095_stats_get_strings, 4566 .stats_get_stat = mv88e6095_stats_get_stat, 4567 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4568 .set_egress_port = mv88e6095_g1_set_egress_port, 4569 .watchdog_ops = &mv88e6097_watchdog_ops, 4570 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4571 .pot_clear = mv88e6xxx_g2_pot_clear, 4572 .reset = mv88e6352_g1_reset, 4573 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4574 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4575 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4576 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4577 .stu_getnext = mv88e6352_g1_stu_getnext, 4578 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4579 .phylink_get_caps = mv88e6351_phylink_get_caps, 4580 }; 4581 4582 static const struct mv88e6xxx_ops mv88e6172_ops = { 4583 /* MV88E6XXX_FAMILY_6352 */ 4584 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4585 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4586 .irl_init_all = mv88e6352_g2_irl_init_all, 4587 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4588 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4589 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4590 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4591 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4592 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4593 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4594 .port_set_link = mv88e6xxx_port_set_link, 4595 .port_sync_link = mv88e6xxx_port_sync_link, 4596 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4597 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4598 .port_tag_remap = mv88e6095_port_tag_remap, 4599 .port_set_policy = mv88e6352_port_set_policy, 4600 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4601 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4602 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4603 .port_set_ether_type = mv88e6351_port_set_ether_type, 4604 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4605 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4606 .port_pause_limit = mv88e6097_port_pause_limit, 4607 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4608 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4609 .port_get_cmode = mv88e6352_port_get_cmode, 4610 .port_setup_leds = mv88e6xxx_port_setup_leds, 4611 .port_setup_message_port = mv88e6xxx_setup_message_port, 4612 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4613 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4614 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4615 .stats_get_strings = mv88e6095_stats_get_strings, 4616 .stats_get_stat = mv88e6095_stats_get_stat, 4617 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4618 .set_egress_port = mv88e6095_g1_set_egress_port, 4619 .watchdog_ops = &mv88e6097_watchdog_ops, 4620 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4621 .pot_clear = mv88e6xxx_g2_pot_clear, 4622 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4623 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4624 .reset = mv88e6352_g1_reset, 4625 .rmu_disable = mv88e6352_g1_rmu_disable, 4626 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4627 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4628 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4629 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4630 .stu_getnext = mv88e6352_g1_stu_getnext, 4631 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4632 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4633 .serdes_get_regs = mv88e6352_serdes_get_regs, 4634 .gpio_ops = &mv88e6352_gpio_ops, 4635 .phylink_get_caps = mv88e6352_phylink_get_caps, 4636 .pcs_ops = &mv88e6352_pcs_ops, 4637 }; 4638 4639 static const struct mv88e6xxx_ops mv88e6175_ops = { 4640 /* MV88E6XXX_FAMILY_6351 */ 4641 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4642 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4643 .irl_init_all = mv88e6352_g2_irl_init_all, 4644 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4645 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4646 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4647 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4648 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4649 .port_set_link = mv88e6xxx_port_set_link, 4650 .port_sync_link = mv88e6xxx_port_sync_link, 4651 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4652 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4653 .port_tag_remap = mv88e6095_port_tag_remap, 4654 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4655 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4656 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4657 .port_set_ether_type = mv88e6351_port_set_ether_type, 4658 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4659 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4660 .port_pause_limit = mv88e6097_port_pause_limit, 4661 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4662 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4663 .port_get_cmode = mv88e6352_port_get_cmode, 4664 .port_setup_message_port = mv88e6xxx_setup_message_port, 4665 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4666 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4667 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4668 .stats_get_strings = mv88e6095_stats_get_strings, 4669 .stats_get_stat = mv88e6095_stats_get_stat, 4670 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4671 .set_egress_port = mv88e6095_g1_set_egress_port, 4672 .watchdog_ops = &mv88e6097_watchdog_ops, 4673 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4674 .pot_clear = mv88e6xxx_g2_pot_clear, 4675 .reset = mv88e6352_g1_reset, 4676 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4677 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4678 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4679 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4680 .stu_getnext = mv88e6352_g1_stu_getnext, 4681 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4682 .phylink_get_caps = mv88e6351_phylink_get_caps, 4683 }; 4684 4685 static const struct mv88e6xxx_ops mv88e6176_ops = { 4686 /* MV88E6XXX_FAMILY_6352 */ 4687 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4688 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4689 .irl_init_all = mv88e6352_g2_irl_init_all, 4690 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4691 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4692 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4693 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4694 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4695 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4696 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4697 .port_set_link = mv88e6xxx_port_set_link, 4698 .port_sync_link = mv88e6xxx_port_sync_link, 4699 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4700 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4701 .port_tag_remap = mv88e6095_port_tag_remap, 4702 .port_set_policy = mv88e6352_port_set_policy, 4703 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4704 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4705 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4706 .port_set_ether_type = mv88e6351_port_set_ether_type, 4707 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4708 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4709 .port_pause_limit = mv88e6097_port_pause_limit, 4710 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4711 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4712 .port_get_cmode = mv88e6352_port_get_cmode, 4713 .port_setup_leds = mv88e6xxx_port_setup_leds, 4714 .port_setup_message_port = mv88e6xxx_setup_message_port, 4715 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4716 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4717 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4718 .stats_get_strings = mv88e6095_stats_get_strings, 4719 .stats_get_stat = mv88e6095_stats_get_stat, 4720 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4721 .set_egress_port = mv88e6095_g1_set_egress_port, 4722 .watchdog_ops = &mv88e6097_watchdog_ops, 4723 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4724 .pot_clear = mv88e6xxx_g2_pot_clear, 4725 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4726 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4727 .reset = mv88e6352_g1_reset, 4728 .rmu_disable = mv88e6352_g1_rmu_disable, 4729 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4730 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4731 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4732 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4733 .stu_getnext = mv88e6352_g1_stu_getnext, 4734 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4735 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4736 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4737 .serdes_get_regs = mv88e6352_serdes_get_regs, 4738 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4739 .gpio_ops = &mv88e6352_gpio_ops, 4740 .phylink_get_caps = mv88e6352_phylink_get_caps, 4741 .pcs_ops = &mv88e6352_pcs_ops, 4742 }; 4743 4744 static const struct mv88e6xxx_ops mv88e6185_ops = { 4745 /* MV88E6XXX_FAMILY_6185 */ 4746 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4747 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4748 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4749 .phy_read = mv88e6185_phy_ppu_read, 4750 .phy_write = mv88e6185_phy_ppu_write, 4751 .port_set_link = mv88e6xxx_port_set_link, 4752 .port_sync_link = mv88e6185_port_sync_link, 4753 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4754 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4755 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4756 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4757 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4758 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4759 .port_set_pause = mv88e6185_port_set_pause, 4760 .port_get_cmode = mv88e6185_port_get_cmode, 4761 .port_setup_message_port = mv88e6xxx_setup_message_port, 4762 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4763 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4764 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4765 .stats_get_strings = mv88e6095_stats_get_strings, 4766 .stats_get_stat = mv88e6095_stats_get_stat, 4767 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4768 .set_egress_port = mv88e6095_g1_set_egress_port, 4769 .watchdog_ops = &mv88e6097_watchdog_ops, 4770 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4771 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4772 .ppu_enable = mv88e6185_g1_ppu_enable, 4773 .ppu_disable = mv88e6185_g1_ppu_disable, 4774 .reset = mv88e6185_g1_reset, 4775 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4776 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4777 .phylink_get_caps = mv88e6185_phylink_get_caps, 4778 .pcs_ops = &mv88e6185_pcs_ops, 4779 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4780 }; 4781 4782 static const struct mv88e6xxx_ops mv88e6190_ops = { 4783 /* MV88E6XXX_FAMILY_6390 */ 4784 .setup_errata = mv88e6390_setup_errata, 4785 .irl_init_all = mv88e6390_g2_irl_init_all, 4786 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4787 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4788 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4789 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4790 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4791 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4792 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4793 .port_set_link = mv88e6xxx_port_set_link, 4794 .port_sync_link = mv88e6xxx_port_sync_link, 4795 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4796 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4797 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4798 .port_tag_remap = mv88e6390_port_tag_remap, 4799 .port_set_policy = mv88e6352_port_set_policy, 4800 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4801 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4802 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4803 .port_set_ether_type = mv88e6351_port_set_ether_type, 4804 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4805 .port_pause_limit = mv88e6390_port_pause_limit, 4806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4808 .port_get_cmode = mv88e6352_port_get_cmode, 4809 .port_set_cmode = mv88e6390_port_set_cmode, 4810 .port_setup_message_port = mv88e6xxx_setup_message_port, 4811 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4812 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4813 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4814 .stats_get_strings = mv88e6320_stats_get_strings, 4815 .stats_get_stat = mv88e6390_stats_get_stat, 4816 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4817 .set_egress_port = mv88e6390_g1_set_egress_port, 4818 .watchdog_ops = &mv88e6390_watchdog_ops, 4819 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4820 .pot_clear = mv88e6xxx_g2_pot_clear, 4821 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4822 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4823 .reset = mv88e6352_g1_reset, 4824 .rmu_disable = mv88e6390_g1_rmu_disable, 4825 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4826 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4827 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4828 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4829 .stu_getnext = mv88e6390_g1_stu_getnext, 4830 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4831 .serdes_get_lane = mv88e6390_serdes_get_lane, 4832 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4833 .serdes_get_strings = mv88e6390_serdes_get_strings, 4834 .serdes_get_stats = mv88e6390_serdes_get_stats, 4835 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4836 .serdes_get_regs = mv88e6390_serdes_get_regs, 4837 .gpio_ops = &mv88e6352_gpio_ops, 4838 .phylink_get_caps = mv88e6390_phylink_get_caps, 4839 .pcs_ops = &mv88e6390_pcs_ops, 4840 }; 4841 4842 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4843 /* MV88E6XXX_FAMILY_6390 */ 4844 .setup_errata = mv88e6390_setup_errata, 4845 .irl_init_all = mv88e6390_g2_irl_init_all, 4846 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4847 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4849 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4850 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4851 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4852 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4853 .port_set_link = mv88e6xxx_port_set_link, 4854 .port_sync_link = mv88e6xxx_port_sync_link, 4855 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4856 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4857 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4858 .port_tag_remap = mv88e6390_port_tag_remap, 4859 .port_set_policy = mv88e6352_port_set_policy, 4860 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4861 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4862 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4863 .port_set_ether_type = mv88e6351_port_set_ether_type, 4864 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4865 .port_pause_limit = mv88e6390_port_pause_limit, 4866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4868 .port_get_cmode = mv88e6352_port_get_cmode, 4869 .port_set_cmode = mv88e6390x_port_set_cmode, 4870 .port_setup_message_port = mv88e6xxx_setup_message_port, 4871 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4872 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4873 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4874 .stats_get_strings = mv88e6320_stats_get_strings, 4875 .stats_get_stat = mv88e6390_stats_get_stat, 4876 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4877 .set_egress_port = mv88e6390_g1_set_egress_port, 4878 .watchdog_ops = &mv88e6390_watchdog_ops, 4879 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4880 .pot_clear = mv88e6xxx_g2_pot_clear, 4881 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4882 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4883 .reset = mv88e6352_g1_reset, 4884 .rmu_disable = mv88e6390_g1_rmu_disable, 4885 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4886 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4887 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4888 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4889 .stu_getnext = mv88e6390_g1_stu_getnext, 4890 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4891 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4892 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4893 .serdes_get_strings = mv88e6390_serdes_get_strings, 4894 .serdes_get_stats = mv88e6390_serdes_get_stats, 4895 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4896 .serdes_get_regs = mv88e6390_serdes_get_regs, 4897 .gpio_ops = &mv88e6352_gpio_ops, 4898 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4899 .pcs_ops = &mv88e6390_pcs_ops, 4900 }; 4901 4902 static const struct mv88e6xxx_ops mv88e6191_ops = { 4903 /* MV88E6XXX_FAMILY_6390 */ 4904 .setup_errata = mv88e6390_setup_errata, 4905 .irl_init_all = mv88e6390_g2_irl_init_all, 4906 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4907 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4908 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4909 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4910 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4911 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4912 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4913 .port_set_link = mv88e6xxx_port_set_link, 4914 .port_sync_link = mv88e6xxx_port_sync_link, 4915 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4916 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4917 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4918 .port_tag_remap = mv88e6390_port_tag_remap, 4919 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4920 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4921 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4922 .port_set_ether_type = mv88e6351_port_set_ether_type, 4923 .port_pause_limit = mv88e6390_port_pause_limit, 4924 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4925 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4926 .port_get_cmode = mv88e6352_port_get_cmode, 4927 .port_set_cmode = mv88e6390_port_set_cmode, 4928 .port_setup_message_port = mv88e6xxx_setup_message_port, 4929 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4930 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4931 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4932 .stats_get_strings = mv88e6320_stats_get_strings, 4933 .stats_get_stat = mv88e6390_stats_get_stat, 4934 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4935 .set_egress_port = mv88e6390_g1_set_egress_port, 4936 .watchdog_ops = &mv88e6390_watchdog_ops, 4937 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4938 .pot_clear = mv88e6xxx_g2_pot_clear, 4939 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4940 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4941 .reset = mv88e6352_g1_reset, 4942 .rmu_disable = mv88e6390_g1_rmu_disable, 4943 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4944 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4945 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4946 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4947 .stu_getnext = mv88e6390_g1_stu_getnext, 4948 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4949 .serdes_get_lane = mv88e6390_serdes_get_lane, 4950 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4951 .serdes_get_strings = mv88e6390_serdes_get_strings, 4952 .serdes_get_stats = mv88e6390_serdes_get_stats, 4953 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4954 .serdes_get_regs = mv88e6390_serdes_get_regs, 4955 .avb_ops = &mv88e6390_avb_ops, 4956 .ptp_ops = &mv88e6352_ptp_ops, 4957 .phylink_get_caps = mv88e6390_phylink_get_caps, 4958 .pcs_ops = &mv88e6390_pcs_ops, 4959 }; 4960 4961 static const struct mv88e6xxx_ops mv88e6240_ops = { 4962 /* MV88E6XXX_FAMILY_6352 */ 4963 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4964 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4965 .irl_init_all = mv88e6352_g2_irl_init_all, 4966 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4967 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4968 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4969 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4970 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4971 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4972 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4973 .port_set_link = mv88e6xxx_port_set_link, 4974 .port_sync_link = mv88e6xxx_port_sync_link, 4975 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4976 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4977 .port_tag_remap = mv88e6095_port_tag_remap, 4978 .port_set_policy = mv88e6352_port_set_policy, 4979 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4980 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4981 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4982 .port_set_ether_type = mv88e6351_port_set_ether_type, 4983 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4984 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4985 .port_pause_limit = mv88e6097_port_pause_limit, 4986 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4987 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4988 .port_get_cmode = mv88e6352_port_get_cmode, 4989 .port_setup_leds = mv88e6xxx_port_setup_leds, 4990 .port_setup_message_port = mv88e6xxx_setup_message_port, 4991 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4992 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4993 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4994 .stats_get_strings = mv88e6095_stats_get_strings, 4995 .stats_get_stat = mv88e6095_stats_get_stat, 4996 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4997 .set_egress_port = mv88e6095_g1_set_egress_port, 4998 .watchdog_ops = &mv88e6097_watchdog_ops, 4999 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5000 .pot_clear = mv88e6xxx_g2_pot_clear, 5001 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5002 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5003 .reset = mv88e6352_g1_reset, 5004 .rmu_disable = mv88e6352_g1_rmu_disable, 5005 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5006 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5007 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5008 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5009 .stu_getnext = mv88e6352_g1_stu_getnext, 5010 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5011 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5012 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5013 .serdes_get_regs = mv88e6352_serdes_get_regs, 5014 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5015 .gpio_ops = &mv88e6352_gpio_ops, 5016 .avb_ops = &mv88e6352_avb_ops, 5017 .ptp_ops = &mv88e6352_ptp_ops, 5018 .phylink_get_caps = mv88e6352_phylink_get_caps, 5019 .pcs_ops = &mv88e6352_pcs_ops, 5020 }; 5021 5022 static const struct mv88e6xxx_ops mv88e6250_ops = { 5023 /* MV88E6XXX_FAMILY_6250 */ 5024 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5025 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5026 .irl_init_all = mv88e6352_g2_irl_init_all, 5027 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5028 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5030 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5031 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5032 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5033 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5034 .port_set_link = mv88e6xxx_port_set_link, 5035 .port_sync_link = mv88e6xxx_port_sync_link, 5036 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5037 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5038 .port_tag_remap = mv88e6095_port_tag_remap, 5039 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5040 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5041 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5042 .port_set_ether_type = mv88e6351_port_set_ether_type, 5043 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5044 .port_pause_limit = mv88e6097_port_pause_limit, 5045 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5046 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5047 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5048 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5049 .stats_get_strings = mv88e6250_stats_get_strings, 5050 .stats_get_stat = mv88e6250_stats_get_stat, 5051 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5052 .set_egress_port = mv88e6095_g1_set_egress_port, 5053 .watchdog_ops = &mv88e6250_watchdog_ops, 5054 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5055 .pot_clear = mv88e6xxx_g2_pot_clear, 5056 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5057 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5058 .reset = mv88e6250_g1_reset, 5059 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5060 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5061 .avb_ops = &mv88e6352_avb_ops, 5062 .ptp_ops = &mv88e6250_ptp_ops, 5063 .phylink_get_caps = mv88e6250_phylink_get_caps, 5064 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5065 }; 5066 5067 static const struct mv88e6xxx_ops mv88e6290_ops = { 5068 /* MV88E6XXX_FAMILY_6390 */ 5069 .setup_errata = mv88e6390_setup_errata, 5070 .irl_init_all = mv88e6390_g2_irl_init_all, 5071 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5072 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5073 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5074 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5075 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5076 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5077 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5078 .port_set_link = mv88e6xxx_port_set_link, 5079 .port_sync_link = mv88e6xxx_port_sync_link, 5080 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5081 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5082 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5083 .port_tag_remap = mv88e6390_port_tag_remap, 5084 .port_set_policy = mv88e6352_port_set_policy, 5085 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5086 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5087 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5088 .port_set_ether_type = mv88e6351_port_set_ether_type, 5089 .port_pause_limit = mv88e6390_port_pause_limit, 5090 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5091 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5092 .port_get_cmode = mv88e6352_port_get_cmode, 5093 .port_set_cmode = mv88e6390_port_set_cmode, 5094 .port_setup_message_port = mv88e6xxx_setup_message_port, 5095 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5096 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5097 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5098 .stats_get_strings = mv88e6320_stats_get_strings, 5099 .stats_get_stat = mv88e6390_stats_get_stat, 5100 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5101 .set_egress_port = mv88e6390_g1_set_egress_port, 5102 .watchdog_ops = &mv88e6390_watchdog_ops, 5103 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5104 .pot_clear = mv88e6xxx_g2_pot_clear, 5105 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5106 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5107 .reset = mv88e6352_g1_reset, 5108 .rmu_disable = mv88e6390_g1_rmu_disable, 5109 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5110 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5111 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5112 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5113 .stu_getnext = mv88e6390_g1_stu_getnext, 5114 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5115 .serdes_get_lane = mv88e6390_serdes_get_lane, 5116 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5117 .serdes_get_strings = mv88e6390_serdes_get_strings, 5118 .serdes_get_stats = mv88e6390_serdes_get_stats, 5119 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5120 .serdes_get_regs = mv88e6390_serdes_get_regs, 5121 .gpio_ops = &mv88e6352_gpio_ops, 5122 .avb_ops = &mv88e6390_avb_ops, 5123 .ptp_ops = &mv88e6390_ptp_ops, 5124 .phylink_get_caps = mv88e6390_phylink_get_caps, 5125 .pcs_ops = &mv88e6390_pcs_ops, 5126 }; 5127 5128 static const struct mv88e6xxx_ops mv88e6320_ops = { 5129 /* MV88E6XXX_FAMILY_6320 */ 5130 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5131 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5132 .irl_init_all = mv88e6352_g2_irl_init_all, 5133 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5134 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5135 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5136 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5137 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5138 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5139 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5140 .port_set_link = mv88e6xxx_port_set_link, 5141 .port_sync_link = mv88e6xxx_port_sync_link, 5142 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5143 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5144 .port_tag_remap = mv88e6095_port_tag_remap, 5145 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5146 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5147 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5148 .port_set_ether_type = mv88e6351_port_set_ether_type, 5149 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5150 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5151 .port_pause_limit = mv88e6097_port_pause_limit, 5152 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5153 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5154 .port_get_cmode = mv88e6352_port_get_cmode, 5155 .port_setup_message_port = mv88e6xxx_setup_message_port, 5156 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5157 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5158 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5159 .stats_get_strings = mv88e6320_stats_get_strings, 5160 .stats_get_stat = mv88e6320_stats_get_stat, 5161 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5162 .set_egress_port = mv88e6095_g1_set_egress_port, 5163 .watchdog_ops = &mv88e6390_watchdog_ops, 5164 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5165 .pot_clear = mv88e6xxx_g2_pot_clear, 5166 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5167 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5168 .reset = mv88e6352_g1_reset, 5169 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5170 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5171 .gpio_ops = &mv88e6352_gpio_ops, 5172 .avb_ops = &mv88e6352_avb_ops, 5173 .ptp_ops = &mv88e6352_ptp_ops, 5174 .phylink_get_caps = mv88e632x_phylink_get_caps, 5175 }; 5176 5177 static const struct mv88e6xxx_ops mv88e6321_ops = { 5178 /* MV88E6XXX_FAMILY_6320 */ 5179 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5180 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5181 .irl_init_all = mv88e6352_g2_irl_init_all, 5182 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5183 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5184 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5185 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5186 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5187 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5188 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5189 .port_set_link = mv88e6xxx_port_set_link, 5190 .port_sync_link = mv88e6xxx_port_sync_link, 5191 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5192 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5193 .port_tag_remap = mv88e6095_port_tag_remap, 5194 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5195 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5196 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5197 .port_set_ether_type = mv88e6351_port_set_ether_type, 5198 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5199 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5200 .port_pause_limit = mv88e6097_port_pause_limit, 5201 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5202 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5203 .port_get_cmode = mv88e6352_port_get_cmode, 5204 .port_setup_message_port = mv88e6xxx_setup_message_port, 5205 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5206 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5207 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5208 .stats_get_strings = mv88e6320_stats_get_strings, 5209 .stats_get_stat = mv88e6320_stats_get_stat, 5210 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5211 .set_egress_port = mv88e6095_g1_set_egress_port, 5212 .watchdog_ops = &mv88e6390_watchdog_ops, 5213 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5214 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5215 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5216 .reset = mv88e6352_g1_reset, 5217 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5218 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5219 .gpio_ops = &mv88e6352_gpio_ops, 5220 .avb_ops = &mv88e6352_avb_ops, 5221 .ptp_ops = &mv88e6352_ptp_ops, 5222 .phylink_get_caps = mv88e632x_phylink_get_caps, 5223 }; 5224 5225 static const struct mv88e6xxx_ops mv88e6341_ops = { 5226 /* MV88E6XXX_FAMILY_6341 */ 5227 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5228 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5229 .irl_init_all = mv88e6352_g2_irl_init_all, 5230 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5231 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5232 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5233 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5234 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5235 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5236 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5237 .port_set_link = mv88e6xxx_port_set_link, 5238 .port_sync_link = mv88e6xxx_port_sync_link, 5239 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5240 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5241 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5242 .port_tag_remap = mv88e6095_port_tag_remap, 5243 .port_set_policy = mv88e6352_port_set_policy, 5244 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5245 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5246 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5247 .port_set_ether_type = mv88e6351_port_set_ether_type, 5248 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5249 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5250 .port_pause_limit = mv88e6097_port_pause_limit, 5251 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5252 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5253 .port_get_cmode = mv88e6352_port_get_cmode, 5254 .port_set_cmode = mv88e6341_port_set_cmode, 5255 .port_setup_message_port = mv88e6xxx_setup_message_port, 5256 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5257 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5258 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5259 .stats_get_strings = mv88e6320_stats_get_strings, 5260 .stats_get_stat = mv88e6390_stats_get_stat, 5261 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5262 .set_egress_port = mv88e6390_g1_set_egress_port, 5263 .watchdog_ops = &mv88e6390_watchdog_ops, 5264 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5265 .pot_clear = mv88e6xxx_g2_pot_clear, 5266 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5267 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5268 .reset = mv88e6352_g1_reset, 5269 .rmu_disable = mv88e6390_g1_rmu_disable, 5270 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5271 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5272 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5273 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5274 .stu_getnext = mv88e6352_g1_stu_getnext, 5275 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5276 .serdes_get_lane = mv88e6341_serdes_get_lane, 5277 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5278 .gpio_ops = &mv88e6352_gpio_ops, 5279 .avb_ops = &mv88e6390_avb_ops, 5280 .ptp_ops = &mv88e6352_ptp_ops, 5281 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5282 .serdes_get_strings = mv88e6390_serdes_get_strings, 5283 .serdes_get_stats = mv88e6390_serdes_get_stats, 5284 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5285 .serdes_get_regs = mv88e6390_serdes_get_regs, 5286 .phylink_get_caps = mv88e6341_phylink_get_caps, 5287 .pcs_ops = &mv88e6390_pcs_ops, 5288 }; 5289 5290 static const struct mv88e6xxx_ops mv88e6350_ops = { 5291 /* MV88E6XXX_FAMILY_6351 */ 5292 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5293 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5294 .irl_init_all = mv88e6352_g2_irl_init_all, 5295 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5296 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5297 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5298 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5299 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5300 .port_set_link = mv88e6xxx_port_set_link, 5301 .port_sync_link = mv88e6xxx_port_sync_link, 5302 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5303 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5304 .port_tag_remap = mv88e6095_port_tag_remap, 5305 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5306 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5307 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5308 .port_set_ether_type = mv88e6351_port_set_ether_type, 5309 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5310 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5311 .port_pause_limit = mv88e6097_port_pause_limit, 5312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5314 .port_get_cmode = mv88e6352_port_get_cmode, 5315 .port_setup_message_port = mv88e6xxx_setup_message_port, 5316 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5318 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5319 .stats_get_strings = mv88e6095_stats_get_strings, 5320 .stats_get_stat = mv88e6095_stats_get_stat, 5321 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5322 .set_egress_port = mv88e6095_g1_set_egress_port, 5323 .watchdog_ops = &mv88e6097_watchdog_ops, 5324 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5325 .pot_clear = mv88e6xxx_g2_pot_clear, 5326 .reset = mv88e6352_g1_reset, 5327 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5328 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5329 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5330 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5331 .stu_getnext = mv88e6352_g1_stu_getnext, 5332 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5333 .phylink_get_caps = mv88e6351_phylink_get_caps, 5334 }; 5335 5336 static const struct mv88e6xxx_ops mv88e6351_ops = { 5337 /* MV88E6XXX_FAMILY_6351 */ 5338 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5339 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5340 .irl_init_all = mv88e6352_g2_irl_init_all, 5341 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5342 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5343 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5344 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5345 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5346 .port_set_link = mv88e6xxx_port_set_link, 5347 .port_sync_link = mv88e6xxx_port_sync_link, 5348 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5349 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5350 .port_tag_remap = mv88e6095_port_tag_remap, 5351 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5352 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5353 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5354 .port_set_ether_type = mv88e6351_port_set_ether_type, 5355 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5356 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5357 .port_pause_limit = mv88e6097_port_pause_limit, 5358 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5359 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5360 .port_get_cmode = mv88e6352_port_get_cmode, 5361 .port_setup_message_port = mv88e6xxx_setup_message_port, 5362 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5363 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5364 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5365 .stats_get_strings = mv88e6095_stats_get_strings, 5366 .stats_get_stat = mv88e6095_stats_get_stat, 5367 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5368 .set_egress_port = mv88e6095_g1_set_egress_port, 5369 .watchdog_ops = &mv88e6097_watchdog_ops, 5370 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5371 .pot_clear = mv88e6xxx_g2_pot_clear, 5372 .reset = mv88e6352_g1_reset, 5373 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5374 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5375 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5376 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5377 .stu_getnext = mv88e6352_g1_stu_getnext, 5378 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5379 .avb_ops = &mv88e6352_avb_ops, 5380 .ptp_ops = &mv88e6352_ptp_ops, 5381 .phylink_get_caps = mv88e6351_phylink_get_caps, 5382 }; 5383 5384 static const struct mv88e6xxx_ops mv88e6352_ops = { 5385 /* MV88E6XXX_FAMILY_6352 */ 5386 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5387 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5388 .irl_init_all = mv88e6352_g2_irl_init_all, 5389 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5390 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5391 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5392 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5393 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5394 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5395 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5396 .port_set_link = mv88e6xxx_port_set_link, 5397 .port_sync_link = mv88e6xxx_port_sync_link, 5398 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5399 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5400 .port_tag_remap = mv88e6095_port_tag_remap, 5401 .port_set_policy = mv88e6352_port_set_policy, 5402 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5403 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5404 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5405 .port_set_ether_type = mv88e6351_port_set_ether_type, 5406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5407 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5408 .port_pause_limit = mv88e6097_port_pause_limit, 5409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5411 .port_get_cmode = mv88e6352_port_get_cmode, 5412 .port_setup_leds = mv88e6xxx_port_setup_leds, 5413 .port_setup_message_port = mv88e6xxx_setup_message_port, 5414 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5415 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5416 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5417 .stats_get_strings = mv88e6095_stats_get_strings, 5418 .stats_get_stat = mv88e6095_stats_get_stat, 5419 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5420 .set_egress_port = mv88e6095_g1_set_egress_port, 5421 .watchdog_ops = &mv88e6097_watchdog_ops, 5422 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5423 .pot_clear = mv88e6xxx_g2_pot_clear, 5424 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5425 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5426 .reset = mv88e6352_g1_reset, 5427 .rmu_disable = mv88e6352_g1_rmu_disable, 5428 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5429 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5430 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5431 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5432 .stu_getnext = mv88e6352_g1_stu_getnext, 5433 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5434 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5435 .gpio_ops = &mv88e6352_gpio_ops, 5436 .avb_ops = &mv88e6352_avb_ops, 5437 .ptp_ops = &mv88e6352_ptp_ops, 5438 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5439 .serdes_get_strings = mv88e6352_serdes_get_strings, 5440 .serdes_get_stats = mv88e6352_serdes_get_stats, 5441 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5442 .serdes_get_regs = mv88e6352_serdes_get_regs, 5443 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5444 .phylink_get_caps = mv88e6352_phylink_get_caps, 5445 .pcs_ops = &mv88e6352_pcs_ops, 5446 }; 5447 5448 static const struct mv88e6xxx_ops mv88e6390_ops = { 5449 /* MV88E6XXX_FAMILY_6390 */ 5450 .setup_errata = mv88e6390_setup_errata, 5451 .irl_init_all = mv88e6390_g2_irl_init_all, 5452 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5453 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5454 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5455 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5456 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5457 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5458 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5459 .port_set_link = mv88e6xxx_port_set_link, 5460 .port_sync_link = mv88e6xxx_port_sync_link, 5461 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5462 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5463 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5464 .port_tag_remap = mv88e6390_port_tag_remap, 5465 .port_set_policy = mv88e6352_port_set_policy, 5466 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5467 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5468 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5469 .port_set_ether_type = mv88e6351_port_set_ether_type, 5470 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5471 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5472 .port_pause_limit = mv88e6390_port_pause_limit, 5473 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5474 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5475 .port_get_cmode = mv88e6352_port_get_cmode, 5476 .port_set_cmode = mv88e6390_port_set_cmode, 5477 .port_setup_message_port = mv88e6xxx_setup_message_port, 5478 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5479 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5480 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5481 .stats_get_strings = mv88e6320_stats_get_strings, 5482 .stats_get_stat = mv88e6390_stats_get_stat, 5483 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5484 .set_egress_port = mv88e6390_g1_set_egress_port, 5485 .watchdog_ops = &mv88e6390_watchdog_ops, 5486 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5487 .pot_clear = mv88e6xxx_g2_pot_clear, 5488 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5489 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5490 .reset = mv88e6352_g1_reset, 5491 .rmu_disable = mv88e6390_g1_rmu_disable, 5492 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5493 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5494 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5495 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5496 .stu_getnext = mv88e6390_g1_stu_getnext, 5497 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5498 .serdes_get_lane = mv88e6390_serdes_get_lane, 5499 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5500 .gpio_ops = &mv88e6352_gpio_ops, 5501 .avb_ops = &mv88e6390_avb_ops, 5502 .ptp_ops = &mv88e6390_ptp_ops, 5503 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5504 .serdes_get_strings = mv88e6390_serdes_get_strings, 5505 .serdes_get_stats = mv88e6390_serdes_get_stats, 5506 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5507 .serdes_get_regs = mv88e6390_serdes_get_regs, 5508 .phylink_get_caps = mv88e6390_phylink_get_caps, 5509 .pcs_ops = &mv88e6390_pcs_ops, 5510 }; 5511 5512 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5513 /* MV88E6XXX_FAMILY_6390 */ 5514 .setup_errata = mv88e6390_setup_errata, 5515 .irl_init_all = mv88e6390_g2_irl_init_all, 5516 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5517 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5518 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5519 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5520 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5521 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5522 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5523 .port_set_link = mv88e6xxx_port_set_link, 5524 .port_sync_link = mv88e6xxx_port_sync_link, 5525 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5526 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5527 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5528 .port_tag_remap = mv88e6390_port_tag_remap, 5529 .port_set_policy = mv88e6352_port_set_policy, 5530 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5531 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5532 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5533 .port_set_ether_type = mv88e6351_port_set_ether_type, 5534 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5535 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5536 .port_pause_limit = mv88e6390_port_pause_limit, 5537 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5538 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5539 .port_get_cmode = mv88e6352_port_get_cmode, 5540 .port_set_cmode = mv88e6390x_port_set_cmode, 5541 .port_setup_message_port = mv88e6xxx_setup_message_port, 5542 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5543 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5544 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5545 .stats_get_strings = mv88e6320_stats_get_strings, 5546 .stats_get_stat = mv88e6390_stats_get_stat, 5547 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5548 .set_egress_port = mv88e6390_g1_set_egress_port, 5549 .watchdog_ops = &mv88e6390_watchdog_ops, 5550 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5551 .pot_clear = mv88e6xxx_g2_pot_clear, 5552 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5553 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5554 .reset = mv88e6352_g1_reset, 5555 .rmu_disable = mv88e6390_g1_rmu_disable, 5556 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5557 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5558 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5559 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5560 .stu_getnext = mv88e6390_g1_stu_getnext, 5561 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5562 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5563 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5564 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5565 .serdes_get_strings = mv88e6390_serdes_get_strings, 5566 .serdes_get_stats = mv88e6390_serdes_get_stats, 5567 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5568 .serdes_get_regs = mv88e6390_serdes_get_regs, 5569 .gpio_ops = &mv88e6352_gpio_ops, 5570 .avb_ops = &mv88e6390_avb_ops, 5571 .ptp_ops = &mv88e6390_ptp_ops, 5572 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5573 .pcs_ops = &mv88e6390_pcs_ops, 5574 }; 5575 5576 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5577 /* MV88E6XXX_FAMILY_6393 */ 5578 .irl_init_all = mv88e6390_g2_irl_init_all, 5579 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5580 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5581 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5582 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5583 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5584 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5585 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5586 .port_set_link = mv88e6xxx_port_set_link, 5587 .port_sync_link = mv88e6xxx_port_sync_link, 5588 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5589 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5590 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5591 .port_tag_remap = mv88e6390_port_tag_remap, 5592 .port_set_policy = mv88e6393x_port_set_policy, 5593 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5594 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5595 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5596 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5597 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5598 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5599 .port_pause_limit = mv88e6390_port_pause_limit, 5600 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5601 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5602 .port_get_cmode = mv88e6352_port_get_cmode, 5603 .port_set_cmode = mv88e6393x_port_set_cmode, 5604 .port_setup_message_port = mv88e6xxx_setup_message_port, 5605 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5606 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5607 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5608 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5609 .stats_get_strings = mv88e6320_stats_get_strings, 5610 .stats_get_stat = mv88e6390_stats_get_stat, 5611 /* .set_cpu_port is missing because this family does not support a global 5612 * CPU port, only per port CPU port which is set via 5613 * .port_set_upstream_port method. 5614 */ 5615 .set_egress_port = mv88e6393x_set_egress_port, 5616 .watchdog_ops = &mv88e6393x_watchdog_ops, 5617 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5618 .pot_clear = mv88e6xxx_g2_pot_clear, 5619 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5620 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5621 .reset = mv88e6352_g1_reset, 5622 .rmu_disable = mv88e6390_g1_rmu_disable, 5623 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5624 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5625 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5626 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5627 .stu_getnext = mv88e6390_g1_stu_getnext, 5628 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5629 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5630 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5631 /* TODO: serdes stats */ 5632 .gpio_ops = &mv88e6352_gpio_ops, 5633 .avb_ops = &mv88e6390_avb_ops, 5634 .ptp_ops = &mv88e6352_ptp_ops, 5635 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5636 .pcs_ops = &mv88e6393x_pcs_ops, 5637 }; 5638 5639 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5640 [MV88E6020] = { 5641 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5642 .family = MV88E6XXX_FAMILY_6250, 5643 .name = "Marvell 88E6020", 5644 .num_databases = 64, 5645 /* Ports 2-4 are not routed to pins 5646 * => usable ports 0, 1, 5, 6 5647 */ 5648 .num_ports = 7, 5649 .num_internal_phys = 2, 5650 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5651 .max_vid = 4095, 5652 .port_base_addr = 0x8, 5653 .phy_base_addr = 0x0, 5654 .global1_addr = 0xf, 5655 .global2_addr = 0x7, 5656 .age_time_coeff = 15000, 5657 .g1_irqs = 9, 5658 .g2_irqs = 5, 5659 .atu_move_port_mask = 0xf, 5660 .dual_chip = true, 5661 .ops = &mv88e6250_ops, 5662 }, 5663 5664 [MV88E6071] = { 5665 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5666 .family = MV88E6XXX_FAMILY_6250, 5667 .name = "Marvell 88E6071", 5668 .num_databases = 64, 5669 .num_ports = 7, 5670 .num_internal_phys = 5, 5671 .max_vid = 4095, 5672 .port_base_addr = 0x08, 5673 .phy_base_addr = 0x00, 5674 .global1_addr = 0x0f, 5675 .global2_addr = 0x07, 5676 .age_time_coeff = 15000, 5677 .g1_irqs = 9, 5678 .g2_irqs = 5, 5679 .atu_move_port_mask = 0xf, 5680 .dual_chip = true, 5681 .ops = &mv88e6250_ops, 5682 }, 5683 5684 [MV88E6085] = { 5685 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5686 .family = MV88E6XXX_FAMILY_6097, 5687 .name = "Marvell 88E6085", 5688 .num_databases = 4096, 5689 .num_macs = 8192, 5690 .num_ports = 10, 5691 .num_internal_phys = 5, 5692 .max_vid = 4095, 5693 .max_sid = 63, 5694 .port_base_addr = 0x10, 5695 .phy_base_addr = 0x0, 5696 .global1_addr = 0x1b, 5697 .global2_addr = 0x1c, 5698 .age_time_coeff = 15000, 5699 .g1_irqs = 8, 5700 .g2_irqs = 10, 5701 .atu_move_port_mask = 0xf, 5702 .pvt = true, 5703 .multi_chip = true, 5704 .ops = &mv88e6085_ops, 5705 }, 5706 5707 [MV88E6095] = { 5708 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5709 .family = MV88E6XXX_FAMILY_6095, 5710 .name = "Marvell 88E6095/88E6095F", 5711 .num_databases = 256, 5712 .num_macs = 8192, 5713 .num_ports = 11, 5714 .num_internal_phys = 0, 5715 .max_vid = 4095, 5716 .port_base_addr = 0x10, 5717 .phy_base_addr = 0x0, 5718 .global1_addr = 0x1b, 5719 .global2_addr = 0x1c, 5720 .age_time_coeff = 15000, 5721 .g1_irqs = 8, 5722 .atu_move_port_mask = 0xf, 5723 .multi_chip = true, 5724 .ops = &mv88e6095_ops, 5725 }, 5726 5727 [MV88E6097] = { 5728 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5729 .family = MV88E6XXX_FAMILY_6097, 5730 .name = "Marvell 88E6097/88E6097F", 5731 .num_databases = 4096, 5732 .num_macs = 8192, 5733 .num_ports = 11, 5734 .num_internal_phys = 8, 5735 .max_vid = 4095, 5736 .max_sid = 63, 5737 .port_base_addr = 0x10, 5738 .phy_base_addr = 0x0, 5739 .global1_addr = 0x1b, 5740 .global2_addr = 0x1c, 5741 .age_time_coeff = 15000, 5742 .g1_irqs = 8, 5743 .g2_irqs = 10, 5744 .atu_move_port_mask = 0xf, 5745 .pvt = true, 5746 .multi_chip = true, 5747 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5748 .ops = &mv88e6097_ops, 5749 }, 5750 5751 [MV88E6123] = { 5752 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5753 .family = MV88E6XXX_FAMILY_6165, 5754 .name = "Marvell 88E6123", 5755 .num_databases = 4096, 5756 .num_macs = 1024, 5757 .num_ports = 3, 5758 .num_internal_phys = 5, 5759 .max_vid = 4095, 5760 .max_sid = 63, 5761 .port_base_addr = 0x10, 5762 .phy_base_addr = 0x0, 5763 .global1_addr = 0x1b, 5764 .global2_addr = 0x1c, 5765 .age_time_coeff = 15000, 5766 .g1_irqs = 9, 5767 .g2_irqs = 10, 5768 .atu_move_port_mask = 0xf, 5769 .pvt = true, 5770 .multi_chip = true, 5771 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5772 .ops = &mv88e6123_ops, 5773 }, 5774 5775 [MV88E6131] = { 5776 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5777 .family = MV88E6XXX_FAMILY_6185, 5778 .name = "Marvell 88E6131", 5779 .num_databases = 256, 5780 .num_macs = 8192, 5781 .num_ports = 8, 5782 .num_internal_phys = 0, 5783 .max_vid = 4095, 5784 .port_base_addr = 0x10, 5785 .phy_base_addr = 0x0, 5786 .global1_addr = 0x1b, 5787 .global2_addr = 0x1c, 5788 .age_time_coeff = 15000, 5789 .g1_irqs = 9, 5790 .atu_move_port_mask = 0xf, 5791 .multi_chip = true, 5792 .ops = &mv88e6131_ops, 5793 }, 5794 5795 [MV88E6141] = { 5796 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5797 .family = MV88E6XXX_FAMILY_6341, 5798 .name = "Marvell 88E6141", 5799 .num_databases = 256, 5800 .num_macs = 2048, 5801 .num_ports = 6, 5802 .num_internal_phys = 5, 5803 .num_gpio = 11, 5804 .max_vid = 4095, 5805 .max_sid = 63, 5806 .port_base_addr = 0x10, 5807 .phy_base_addr = 0x10, 5808 .global1_addr = 0x1b, 5809 .global2_addr = 0x1c, 5810 .age_time_coeff = 3750, 5811 .atu_move_port_mask = 0x1f, 5812 .g1_irqs = 9, 5813 .g2_irqs = 10, 5814 .pvt = true, 5815 .multi_chip = true, 5816 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5817 .ops = &mv88e6141_ops, 5818 }, 5819 5820 [MV88E6161] = { 5821 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5822 .family = MV88E6XXX_FAMILY_6165, 5823 .name = "Marvell 88E6161", 5824 .num_databases = 4096, 5825 .num_macs = 1024, 5826 .num_ports = 6, 5827 .num_internal_phys = 5, 5828 .max_vid = 4095, 5829 .max_sid = 63, 5830 .port_base_addr = 0x10, 5831 .phy_base_addr = 0x0, 5832 .global1_addr = 0x1b, 5833 .global2_addr = 0x1c, 5834 .age_time_coeff = 15000, 5835 .g1_irqs = 9, 5836 .g2_irqs = 10, 5837 .atu_move_port_mask = 0xf, 5838 .pvt = true, 5839 .multi_chip = true, 5840 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5841 .ptp_support = true, 5842 .ops = &mv88e6161_ops, 5843 }, 5844 5845 [MV88E6165] = { 5846 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5847 .family = MV88E6XXX_FAMILY_6165, 5848 .name = "Marvell 88E6165", 5849 .num_databases = 4096, 5850 .num_macs = 8192, 5851 .num_ports = 6, 5852 .num_internal_phys = 0, 5853 .max_vid = 4095, 5854 .max_sid = 63, 5855 .port_base_addr = 0x10, 5856 .phy_base_addr = 0x0, 5857 .global1_addr = 0x1b, 5858 .global2_addr = 0x1c, 5859 .age_time_coeff = 15000, 5860 .g1_irqs = 9, 5861 .g2_irqs = 10, 5862 .atu_move_port_mask = 0xf, 5863 .pvt = true, 5864 .multi_chip = true, 5865 .ptp_support = true, 5866 .ops = &mv88e6165_ops, 5867 }, 5868 5869 [MV88E6171] = { 5870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5871 .family = MV88E6XXX_FAMILY_6351, 5872 .name = "Marvell 88E6171", 5873 .num_databases = 4096, 5874 .num_macs = 8192, 5875 .num_ports = 7, 5876 .num_internal_phys = 5, 5877 .max_vid = 4095, 5878 .max_sid = 63, 5879 .port_base_addr = 0x10, 5880 .phy_base_addr = 0x0, 5881 .global1_addr = 0x1b, 5882 .global2_addr = 0x1c, 5883 .age_time_coeff = 15000, 5884 .g1_irqs = 9, 5885 .g2_irqs = 10, 5886 .atu_move_port_mask = 0xf, 5887 .pvt = true, 5888 .multi_chip = true, 5889 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5890 .ops = &mv88e6171_ops, 5891 }, 5892 5893 [MV88E6172] = { 5894 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5895 .family = MV88E6XXX_FAMILY_6352, 5896 .name = "Marvell 88E6172", 5897 .num_databases = 4096, 5898 .num_macs = 8192, 5899 .num_ports = 7, 5900 .num_internal_phys = 5, 5901 .num_gpio = 15, 5902 .max_vid = 4095, 5903 .max_sid = 63, 5904 .port_base_addr = 0x10, 5905 .phy_base_addr = 0x0, 5906 .global1_addr = 0x1b, 5907 .global2_addr = 0x1c, 5908 .age_time_coeff = 15000, 5909 .g1_irqs = 9, 5910 .g2_irqs = 10, 5911 .atu_move_port_mask = 0xf, 5912 .pvt = true, 5913 .multi_chip = true, 5914 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5915 .ops = &mv88e6172_ops, 5916 }, 5917 5918 [MV88E6175] = { 5919 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5920 .family = MV88E6XXX_FAMILY_6351, 5921 .name = "Marvell 88E6175", 5922 .num_databases = 4096, 5923 .num_macs = 8192, 5924 .num_ports = 7, 5925 .num_internal_phys = 5, 5926 .max_vid = 4095, 5927 .max_sid = 63, 5928 .port_base_addr = 0x10, 5929 .phy_base_addr = 0x0, 5930 .global1_addr = 0x1b, 5931 .global2_addr = 0x1c, 5932 .age_time_coeff = 15000, 5933 .g1_irqs = 9, 5934 .g2_irqs = 10, 5935 .atu_move_port_mask = 0xf, 5936 .pvt = true, 5937 .multi_chip = true, 5938 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5939 .ops = &mv88e6175_ops, 5940 }, 5941 5942 [MV88E6176] = { 5943 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5944 .family = MV88E6XXX_FAMILY_6352, 5945 .name = "Marvell 88E6176", 5946 .num_databases = 4096, 5947 .num_macs = 8192, 5948 .num_ports = 7, 5949 .num_internal_phys = 5, 5950 .num_gpio = 15, 5951 .max_vid = 4095, 5952 .max_sid = 63, 5953 .port_base_addr = 0x10, 5954 .phy_base_addr = 0x0, 5955 .global1_addr = 0x1b, 5956 .global2_addr = 0x1c, 5957 .age_time_coeff = 15000, 5958 .g1_irqs = 9, 5959 .g2_irqs = 10, 5960 .atu_move_port_mask = 0xf, 5961 .pvt = true, 5962 .multi_chip = true, 5963 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5964 .ops = &mv88e6176_ops, 5965 }, 5966 5967 [MV88E6185] = { 5968 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5969 .family = MV88E6XXX_FAMILY_6185, 5970 .name = "Marvell 88E6185", 5971 .num_databases = 256, 5972 .num_macs = 8192, 5973 .num_ports = 10, 5974 .num_internal_phys = 0, 5975 .max_vid = 4095, 5976 .port_base_addr = 0x10, 5977 .phy_base_addr = 0x0, 5978 .global1_addr = 0x1b, 5979 .global2_addr = 0x1c, 5980 .age_time_coeff = 15000, 5981 .g1_irqs = 8, 5982 .atu_move_port_mask = 0xf, 5983 .multi_chip = true, 5984 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5985 .ops = &mv88e6185_ops, 5986 }, 5987 5988 [MV88E6190] = { 5989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5990 .family = MV88E6XXX_FAMILY_6390, 5991 .name = "Marvell 88E6190", 5992 .num_databases = 4096, 5993 .num_macs = 16384, 5994 .num_ports = 11, /* 10 + Z80 */ 5995 .num_internal_phys = 9, 5996 .num_gpio = 16, 5997 .max_vid = 8191, 5998 .max_sid = 63, 5999 .port_base_addr = 0x0, 6000 .phy_base_addr = 0x0, 6001 .global1_addr = 0x1b, 6002 .global2_addr = 0x1c, 6003 .age_time_coeff = 3750, 6004 .g1_irqs = 9, 6005 .g2_irqs = 14, 6006 .pvt = true, 6007 .multi_chip = true, 6008 .atu_move_port_mask = 0x1f, 6009 .ops = &mv88e6190_ops, 6010 }, 6011 6012 [MV88E6190X] = { 6013 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6014 .family = MV88E6XXX_FAMILY_6390, 6015 .name = "Marvell 88E6190X", 6016 .num_databases = 4096, 6017 .num_macs = 16384, 6018 .num_ports = 11, /* 10 + Z80 */ 6019 .num_internal_phys = 9, 6020 .num_gpio = 16, 6021 .max_vid = 8191, 6022 .max_sid = 63, 6023 .port_base_addr = 0x0, 6024 .phy_base_addr = 0x0, 6025 .global1_addr = 0x1b, 6026 .global2_addr = 0x1c, 6027 .age_time_coeff = 3750, 6028 .g1_irqs = 9, 6029 .g2_irqs = 14, 6030 .atu_move_port_mask = 0x1f, 6031 .pvt = true, 6032 .multi_chip = true, 6033 .ops = &mv88e6190x_ops, 6034 }, 6035 6036 [MV88E6191] = { 6037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6038 .family = MV88E6XXX_FAMILY_6390, 6039 .name = "Marvell 88E6191", 6040 .num_databases = 4096, 6041 .num_macs = 16384, 6042 .num_ports = 11, /* 10 + Z80 */ 6043 .num_internal_phys = 9, 6044 .max_vid = 8191, 6045 .max_sid = 63, 6046 .port_base_addr = 0x0, 6047 .phy_base_addr = 0x0, 6048 .global1_addr = 0x1b, 6049 .global2_addr = 0x1c, 6050 .age_time_coeff = 3750, 6051 .g1_irqs = 9, 6052 .g2_irqs = 14, 6053 .atu_move_port_mask = 0x1f, 6054 .pvt = true, 6055 .multi_chip = true, 6056 .ptp_support = true, 6057 .ops = &mv88e6191_ops, 6058 }, 6059 6060 [MV88E6191X] = { 6061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6062 .family = MV88E6XXX_FAMILY_6393, 6063 .name = "Marvell 88E6191X", 6064 .num_databases = 4096, 6065 .num_ports = 11, /* 10 + Z80 */ 6066 .num_internal_phys = 8, 6067 .internal_phys_offset = 1, 6068 .max_vid = 8191, 6069 .max_sid = 63, 6070 .port_base_addr = 0x0, 6071 .phy_base_addr = 0x0, 6072 .global1_addr = 0x1b, 6073 .global2_addr = 0x1c, 6074 .age_time_coeff = 3750, 6075 .g1_irqs = 10, 6076 .g2_irqs = 14, 6077 .atu_move_port_mask = 0x1f, 6078 .pvt = true, 6079 .multi_chip = true, 6080 .ptp_support = true, 6081 .ops = &mv88e6393x_ops, 6082 }, 6083 6084 [MV88E6193X] = { 6085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6086 .family = MV88E6XXX_FAMILY_6393, 6087 .name = "Marvell 88E6193X", 6088 .num_databases = 4096, 6089 .num_ports = 11, /* 10 + Z80 */ 6090 .num_internal_phys = 8, 6091 .internal_phys_offset = 1, 6092 .max_vid = 8191, 6093 .max_sid = 63, 6094 .port_base_addr = 0x0, 6095 .phy_base_addr = 0x0, 6096 .global1_addr = 0x1b, 6097 .global2_addr = 0x1c, 6098 .age_time_coeff = 3750, 6099 .g1_irqs = 10, 6100 .g2_irqs = 14, 6101 .atu_move_port_mask = 0x1f, 6102 .pvt = true, 6103 .multi_chip = true, 6104 .ptp_support = true, 6105 .ops = &mv88e6393x_ops, 6106 }, 6107 6108 [MV88E6220] = { 6109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6110 .family = MV88E6XXX_FAMILY_6250, 6111 .name = "Marvell 88E6220", 6112 .num_databases = 64, 6113 6114 /* Ports 2-4 are not routed to pins 6115 * => usable ports 0, 1, 5, 6 6116 */ 6117 .num_ports = 7, 6118 .num_internal_phys = 2, 6119 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6120 .max_vid = 4095, 6121 .port_base_addr = 0x08, 6122 .phy_base_addr = 0x00, 6123 .global1_addr = 0x0f, 6124 .global2_addr = 0x07, 6125 .age_time_coeff = 15000, 6126 .g1_irqs = 9, 6127 .g2_irqs = 10, 6128 .atu_move_port_mask = 0xf, 6129 .dual_chip = true, 6130 .ptp_support = true, 6131 .ops = &mv88e6250_ops, 6132 }, 6133 6134 [MV88E6240] = { 6135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6136 .family = MV88E6XXX_FAMILY_6352, 6137 .name = "Marvell 88E6240", 6138 .num_databases = 4096, 6139 .num_macs = 8192, 6140 .num_ports = 7, 6141 .num_internal_phys = 5, 6142 .num_gpio = 15, 6143 .max_vid = 4095, 6144 .max_sid = 63, 6145 .port_base_addr = 0x10, 6146 .phy_base_addr = 0x0, 6147 .global1_addr = 0x1b, 6148 .global2_addr = 0x1c, 6149 .age_time_coeff = 15000, 6150 .g1_irqs = 9, 6151 .g2_irqs = 10, 6152 .atu_move_port_mask = 0xf, 6153 .pvt = true, 6154 .multi_chip = true, 6155 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6156 .ptp_support = true, 6157 .ops = &mv88e6240_ops, 6158 }, 6159 6160 [MV88E6250] = { 6161 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6162 .family = MV88E6XXX_FAMILY_6250, 6163 .name = "Marvell 88E6250", 6164 .num_databases = 64, 6165 .num_ports = 7, 6166 .num_internal_phys = 5, 6167 .max_vid = 4095, 6168 .port_base_addr = 0x08, 6169 .phy_base_addr = 0x00, 6170 .global1_addr = 0x0f, 6171 .global2_addr = 0x07, 6172 .age_time_coeff = 15000, 6173 .g1_irqs = 9, 6174 .g2_irqs = 10, 6175 .atu_move_port_mask = 0xf, 6176 .dual_chip = true, 6177 .ptp_support = true, 6178 .ops = &mv88e6250_ops, 6179 }, 6180 6181 [MV88E6290] = { 6182 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6183 .family = MV88E6XXX_FAMILY_6390, 6184 .name = "Marvell 88E6290", 6185 .num_databases = 4096, 6186 .num_ports = 11, /* 10 + Z80 */ 6187 .num_internal_phys = 9, 6188 .num_gpio = 16, 6189 .max_vid = 8191, 6190 .max_sid = 63, 6191 .port_base_addr = 0x0, 6192 .phy_base_addr = 0x0, 6193 .global1_addr = 0x1b, 6194 .global2_addr = 0x1c, 6195 .age_time_coeff = 3750, 6196 .g1_irqs = 9, 6197 .g2_irqs = 14, 6198 .atu_move_port_mask = 0x1f, 6199 .pvt = true, 6200 .multi_chip = true, 6201 .ptp_support = true, 6202 .ops = &mv88e6290_ops, 6203 }, 6204 6205 [MV88E6320] = { 6206 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6207 .family = MV88E6XXX_FAMILY_6320, 6208 .name = "Marvell 88E6320", 6209 .num_databases = 4096, 6210 .num_macs = 8192, 6211 .num_ports = 7, 6212 .num_internal_phys = 5, 6213 .num_gpio = 15, 6214 .max_vid = 4095, 6215 .port_base_addr = 0x10, 6216 .phy_base_addr = 0x0, 6217 .global1_addr = 0x1b, 6218 .global2_addr = 0x1c, 6219 .age_time_coeff = 15000, 6220 .g1_irqs = 8, 6221 .g2_irqs = 10, 6222 .atu_move_port_mask = 0xf, 6223 .pvt = true, 6224 .multi_chip = true, 6225 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6226 .ptp_support = true, 6227 .ops = &mv88e6320_ops, 6228 }, 6229 6230 [MV88E6321] = { 6231 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6232 .family = MV88E6XXX_FAMILY_6320, 6233 .name = "Marvell 88E6321", 6234 .num_databases = 4096, 6235 .num_macs = 8192, 6236 .num_ports = 7, 6237 .num_internal_phys = 5, 6238 .num_gpio = 15, 6239 .max_vid = 4095, 6240 .port_base_addr = 0x10, 6241 .phy_base_addr = 0x0, 6242 .global1_addr = 0x1b, 6243 .global2_addr = 0x1c, 6244 .age_time_coeff = 15000, 6245 .g1_irqs = 8, 6246 .g2_irqs = 10, 6247 .atu_move_port_mask = 0xf, 6248 .multi_chip = true, 6249 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6250 .ptp_support = true, 6251 .ops = &mv88e6321_ops, 6252 }, 6253 6254 [MV88E6341] = { 6255 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6256 .family = MV88E6XXX_FAMILY_6341, 6257 .name = "Marvell 88E6341", 6258 .num_databases = 256, 6259 .num_macs = 2048, 6260 .num_internal_phys = 5, 6261 .num_ports = 6, 6262 .num_gpio = 11, 6263 .max_vid = 4095, 6264 .max_sid = 63, 6265 .port_base_addr = 0x10, 6266 .phy_base_addr = 0x10, 6267 .global1_addr = 0x1b, 6268 .global2_addr = 0x1c, 6269 .age_time_coeff = 3750, 6270 .atu_move_port_mask = 0x1f, 6271 .g1_irqs = 9, 6272 .g2_irqs = 10, 6273 .pvt = true, 6274 .multi_chip = true, 6275 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6276 .ptp_support = true, 6277 .ops = &mv88e6341_ops, 6278 }, 6279 6280 [MV88E6350] = { 6281 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6282 .family = MV88E6XXX_FAMILY_6351, 6283 .name = "Marvell 88E6350", 6284 .num_databases = 4096, 6285 .num_macs = 8192, 6286 .num_ports = 7, 6287 .num_internal_phys = 5, 6288 .max_vid = 4095, 6289 .max_sid = 63, 6290 .port_base_addr = 0x10, 6291 .phy_base_addr = 0x0, 6292 .global1_addr = 0x1b, 6293 .global2_addr = 0x1c, 6294 .age_time_coeff = 15000, 6295 .g1_irqs = 9, 6296 .g2_irqs = 10, 6297 .atu_move_port_mask = 0xf, 6298 .pvt = true, 6299 .multi_chip = true, 6300 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6301 .ops = &mv88e6350_ops, 6302 }, 6303 6304 [MV88E6351] = { 6305 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6306 .family = MV88E6XXX_FAMILY_6351, 6307 .name = "Marvell 88E6351", 6308 .num_databases = 4096, 6309 .num_macs = 8192, 6310 .num_ports = 7, 6311 .num_internal_phys = 5, 6312 .max_vid = 4095, 6313 .max_sid = 63, 6314 .port_base_addr = 0x10, 6315 .phy_base_addr = 0x0, 6316 .global1_addr = 0x1b, 6317 .global2_addr = 0x1c, 6318 .age_time_coeff = 15000, 6319 .g1_irqs = 9, 6320 .g2_irqs = 10, 6321 .atu_move_port_mask = 0xf, 6322 .pvt = true, 6323 .multi_chip = true, 6324 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6325 .ops = &mv88e6351_ops, 6326 }, 6327 6328 [MV88E6352] = { 6329 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6330 .family = MV88E6XXX_FAMILY_6352, 6331 .name = "Marvell 88E6352", 6332 .num_databases = 4096, 6333 .num_macs = 8192, 6334 .num_ports = 7, 6335 .num_internal_phys = 5, 6336 .num_gpio = 15, 6337 .max_vid = 4095, 6338 .max_sid = 63, 6339 .port_base_addr = 0x10, 6340 .phy_base_addr = 0x0, 6341 .global1_addr = 0x1b, 6342 .global2_addr = 0x1c, 6343 .age_time_coeff = 15000, 6344 .g1_irqs = 9, 6345 .g2_irqs = 10, 6346 .atu_move_port_mask = 0xf, 6347 .pvt = true, 6348 .multi_chip = true, 6349 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6350 .ptp_support = true, 6351 .ops = &mv88e6352_ops, 6352 }, 6353 [MV88E6361] = { 6354 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6355 .family = MV88E6XXX_FAMILY_6393, 6356 .name = "Marvell 88E6361", 6357 .num_databases = 4096, 6358 .num_macs = 16384, 6359 .num_ports = 11, 6360 /* Ports 1, 2 and 8 are not routed */ 6361 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6362 .num_internal_phys = 5, 6363 .internal_phys_offset = 3, 6364 .max_vid = 8191, 6365 .max_sid = 63, 6366 .port_base_addr = 0x0, 6367 .phy_base_addr = 0x0, 6368 .global1_addr = 0x1b, 6369 .global2_addr = 0x1c, 6370 .age_time_coeff = 3750, 6371 .g1_irqs = 10, 6372 .g2_irqs = 14, 6373 .atu_move_port_mask = 0x1f, 6374 .pvt = true, 6375 .multi_chip = true, 6376 .ptp_support = true, 6377 .ops = &mv88e6393x_ops, 6378 }, 6379 [MV88E6390] = { 6380 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6381 .family = MV88E6XXX_FAMILY_6390, 6382 .name = "Marvell 88E6390", 6383 .num_databases = 4096, 6384 .num_macs = 16384, 6385 .num_ports = 11, /* 10 + Z80 */ 6386 .num_internal_phys = 9, 6387 .num_gpio = 16, 6388 .max_vid = 8191, 6389 .max_sid = 63, 6390 .port_base_addr = 0x0, 6391 .phy_base_addr = 0x0, 6392 .global1_addr = 0x1b, 6393 .global2_addr = 0x1c, 6394 .age_time_coeff = 3750, 6395 .g1_irqs = 9, 6396 .g2_irqs = 14, 6397 .atu_move_port_mask = 0x1f, 6398 .pvt = true, 6399 .multi_chip = true, 6400 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6401 .ptp_support = true, 6402 .ops = &mv88e6390_ops, 6403 }, 6404 [MV88E6390X] = { 6405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6406 .family = MV88E6XXX_FAMILY_6390, 6407 .name = "Marvell 88E6390X", 6408 .num_databases = 4096, 6409 .num_macs = 16384, 6410 .num_ports = 11, /* 10 + Z80 */ 6411 .num_internal_phys = 9, 6412 .num_gpio = 16, 6413 .max_vid = 8191, 6414 .max_sid = 63, 6415 .port_base_addr = 0x0, 6416 .phy_base_addr = 0x0, 6417 .global1_addr = 0x1b, 6418 .global2_addr = 0x1c, 6419 .age_time_coeff = 3750, 6420 .g1_irqs = 9, 6421 .g2_irqs = 14, 6422 .atu_move_port_mask = 0x1f, 6423 .pvt = true, 6424 .multi_chip = true, 6425 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6426 .ptp_support = true, 6427 .ops = &mv88e6390x_ops, 6428 }, 6429 6430 [MV88E6393X] = { 6431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6432 .family = MV88E6XXX_FAMILY_6393, 6433 .name = "Marvell 88E6393X", 6434 .num_databases = 4096, 6435 .num_ports = 11, /* 10 + Z80 */ 6436 .num_internal_phys = 8, 6437 .internal_phys_offset = 1, 6438 .max_vid = 8191, 6439 .max_sid = 63, 6440 .port_base_addr = 0x0, 6441 .phy_base_addr = 0x0, 6442 .global1_addr = 0x1b, 6443 .global2_addr = 0x1c, 6444 .age_time_coeff = 3750, 6445 .g1_irqs = 10, 6446 .g2_irqs = 14, 6447 .atu_move_port_mask = 0x1f, 6448 .pvt = true, 6449 .multi_chip = true, 6450 .ptp_support = true, 6451 .ops = &mv88e6393x_ops, 6452 }, 6453 }; 6454 6455 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6456 { 6457 int i; 6458 6459 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6460 if (mv88e6xxx_table[i].prod_num == prod_num) 6461 return &mv88e6xxx_table[i]; 6462 6463 return NULL; 6464 } 6465 6466 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6467 { 6468 const struct mv88e6xxx_info *info; 6469 unsigned int prod_num, rev; 6470 u16 id; 6471 int err; 6472 6473 mv88e6xxx_reg_lock(chip); 6474 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6475 mv88e6xxx_reg_unlock(chip); 6476 if (err) 6477 return err; 6478 6479 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6480 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6481 6482 info = mv88e6xxx_lookup_info(prod_num); 6483 if (!info) 6484 return -ENODEV; 6485 6486 /* Update the compatible info with the probed one */ 6487 chip->info = info; 6488 6489 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6490 chip->info->prod_num, chip->info->name, rev); 6491 6492 return 0; 6493 } 6494 6495 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6496 struct mdio_device *mdiodev) 6497 { 6498 int err; 6499 6500 /* dual_chip takes precedence over single/multi-chip modes */ 6501 if (chip->info->dual_chip) 6502 return -EINVAL; 6503 6504 /* If the mdio addr is 16 indicating the first port address of a switch 6505 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6506 * configured in single chip addressing mode. Setup the smi access as 6507 * single chip addressing mode and attempt to detect the model of the 6508 * switch, if this fails the device is not configured in single chip 6509 * addressing mode. 6510 */ 6511 if (mdiodev->addr != 16) 6512 return -EINVAL; 6513 6514 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6515 if (err) 6516 return err; 6517 6518 return mv88e6xxx_detect(chip); 6519 } 6520 6521 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6522 { 6523 struct mv88e6xxx_chip *chip; 6524 6525 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6526 if (!chip) 6527 return NULL; 6528 6529 chip->dev = dev; 6530 6531 mutex_init(&chip->reg_lock); 6532 INIT_LIST_HEAD(&chip->mdios); 6533 idr_init(&chip->policies); 6534 INIT_LIST_HEAD(&chip->msts); 6535 6536 return chip; 6537 } 6538 6539 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6540 int port, 6541 enum dsa_tag_protocol m) 6542 { 6543 struct mv88e6xxx_chip *chip = ds->priv; 6544 6545 return chip->tag_protocol; 6546 } 6547 6548 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6549 enum dsa_tag_protocol proto) 6550 { 6551 struct mv88e6xxx_chip *chip = ds->priv; 6552 enum dsa_tag_protocol old_protocol; 6553 struct dsa_port *cpu_dp; 6554 int err; 6555 6556 switch (proto) { 6557 case DSA_TAG_PROTO_EDSA: 6558 switch (chip->info->edsa_support) { 6559 case MV88E6XXX_EDSA_UNSUPPORTED: 6560 return -EPROTONOSUPPORT; 6561 case MV88E6XXX_EDSA_UNDOCUMENTED: 6562 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6563 fallthrough; 6564 case MV88E6XXX_EDSA_SUPPORTED: 6565 break; 6566 } 6567 break; 6568 case DSA_TAG_PROTO_DSA: 6569 break; 6570 default: 6571 return -EPROTONOSUPPORT; 6572 } 6573 6574 old_protocol = chip->tag_protocol; 6575 chip->tag_protocol = proto; 6576 6577 mv88e6xxx_reg_lock(chip); 6578 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6579 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6580 if (err) { 6581 mv88e6xxx_reg_unlock(chip); 6582 goto unwind; 6583 } 6584 } 6585 mv88e6xxx_reg_unlock(chip); 6586 6587 return 0; 6588 6589 unwind: 6590 chip->tag_protocol = old_protocol; 6591 6592 mv88e6xxx_reg_lock(chip); 6593 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6594 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6595 mv88e6xxx_reg_unlock(chip); 6596 6597 return err; 6598 } 6599 6600 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6601 const struct switchdev_obj_port_mdb *mdb, 6602 struct dsa_db db) 6603 { 6604 struct mv88e6xxx_chip *chip = ds->priv; 6605 int err; 6606 6607 mv88e6xxx_reg_lock(chip); 6608 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6609 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6610 mv88e6xxx_reg_unlock(chip); 6611 6612 return err; 6613 } 6614 6615 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6616 const struct switchdev_obj_port_mdb *mdb, 6617 struct dsa_db db) 6618 { 6619 struct mv88e6xxx_chip *chip = ds->priv; 6620 int err; 6621 6622 mv88e6xxx_reg_lock(chip); 6623 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6624 mv88e6xxx_reg_unlock(chip); 6625 6626 return err; 6627 } 6628 6629 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6630 struct dsa_mall_mirror_tc_entry *mirror, 6631 bool ingress, 6632 struct netlink_ext_ack *extack) 6633 { 6634 enum mv88e6xxx_egress_direction direction = ingress ? 6635 MV88E6XXX_EGRESS_DIR_INGRESS : 6636 MV88E6XXX_EGRESS_DIR_EGRESS; 6637 struct mv88e6xxx_chip *chip = ds->priv; 6638 bool other_mirrors = false; 6639 int i; 6640 int err; 6641 6642 mutex_lock(&chip->reg_lock); 6643 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6644 mirror->to_local_port) { 6645 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6646 other_mirrors |= ingress ? 6647 chip->ports[i].mirror_ingress : 6648 chip->ports[i].mirror_egress; 6649 6650 /* Can't change egress port when other mirror is active */ 6651 if (other_mirrors) { 6652 err = -EBUSY; 6653 goto out; 6654 } 6655 6656 err = mv88e6xxx_set_egress_port(chip, direction, 6657 mirror->to_local_port); 6658 if (err) 6659 goto out; 6660 } 6661 6662 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6663 out: 6664 mutex_unlock(&chip->reg_lock); 6665 6666 return err; 6667 } 6668 6669 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6670 struct dsa_mall_mirror_tc_entry *mirror) 6671 { 6672 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6673 MV88E6XXX_EGRESS_DIR_INGRESS : 6674 MV88E6XXX_EGRESS_DIR_EGRESS; 6675 struct mv88e6xxx_chip *chip = ds->priv; 6676 bool other_mirrors = false; 6677 int i; 6678 6679 mutex_lock(&chip->reg_lock); 6680 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6681 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6682 6683 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6684 other_mirrors |= mirror->ingress ? 6685 chip->ports[i].mirror_ingress : 6686 chip->ports[i].mirror_egress; 6687 6688 /* Reset egress port when no other mirror is active */ 6689 if (!other_mirrors) { 6690 if (mv88e6xxx_set_egress_port(chip, direction, 6691 dsa_upstream_port(ds, port))) 6692 dev_err(ds->dev, "failed to set egress port\n"); 6693 } 6694 6695 mutex_unlock(&chip->reg_lock); 6696 } 6697 6698 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6699 struct switchdev_brport_flags flags, 6700 struct netlink_ext_ack *extack) 6701 { 6702 struct mv88e6xxx_chip *chip = ds->priv; 6703 const struct mv88e6xxx_ops *ops; 6704 6705 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6706 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6707 return -EINVAL; 6708 6709 ops = chip->info->ops; 6710 6711 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6712 return -EINVAL; 6713 6714 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6715 return -EINVAL; 6716 6717 return 0; 6718 } 6719 6720 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6721 struct switchdev_brport_flags flags, 6722 struct netlink_ext_ack *extack) 6723 { 6724 struct mv88e6xxx_chip *chip = ds->priv; 6725 int err = 0; 6726 6727 mv88e6xxx_reg_lock(chip); 6728 6729 if (flags.mask & BR_LEARNING) { 6730 bool learning = !!(flags.val & BR_LEARNING); 6731 u16 pav = learning ? (1 << port) : 0; 6732 6733 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6734 if (err) 6735 goto out; 6736 } 6737 6738 if (flags.mask & BR_FLOOD) { 6739 bool unicast = !!(flags.val & BR_FLOOD); 6740 6741 err = chip->info->ops->port_set_ucast_flood(chip, port, 6742 unicast); 6743 if (err) 6744 goto out; 6745 } 6746 6747 if (flags.mask & BR_MCAST_FLOOD) { 6748 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6749 6750 err = chip->info->ops->port_set_mcast_flood(chip, port, 6751 multicast); 6752 if (err) 6753 goto out; 6754 } 6755 6756 if (flags.mask & BR_BCAST_FLOOD) { 6757 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6758 6759 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6760 if (err) 6761 goto out; 6762 } 6763 6764 if (flags.mask & BR_PORT_MAB) { 6765 bool mab = !!(flags.val & BR_PORT_MAB); 6766 6767 mv88e6xxx_port_set_mab(chip, port, mab); 6768 } 6769 6770 if (flags.mask & BR_PORT_LOCKED) { 6771 bool locked = !!(flags.val & BR_PORT_LOCKED); 6772 6773 err = mv88e6xxx_port_set_lock(chip, port, locked); 6774 if (err) 6775 goto out; 6776 } 6777 out: 6778 mv88e6xxx_reg_unlock(chip); 6779 6780 return err; 6781 } 6782 6783 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6784 struct dsa_lag lag, 6785 struct netdev_lag_upper_info *info, 6786 struct netlink_ext_ack *extack) 6787 { 6788 struct mv88e6xxx_chip *chip = ds->priv; 6789 struct dsa_port *dp; 6790 int members = 0; 6791 6792 if (!mv88e6xxx_has_lag(chip)) { 6793 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6794 return false; 6795 } 6796 6797 if (!lag.id) 6798 return false; 6799 6800 dsa_lag_foreach_port(dp, ds->dst, &lag) 6801 /* Includes the port joining the LAG */ 6802 members++; 6803 6804 if (members > 8) { 6805 NL_SET_ERR_MSG_MOD(extack, 6806 "Cannot offload more than 8 LAG ports"); 6807 return false; 6808 } 6809 6810 /* We could potentially relax this to include active 6811 * backup in the future. 6812 */ 6813 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6814 NL_SET_ERR_MSG_MOD(extack, 6815 "Can only offload LAG using hash TX type"); 6816 return false; 6817 } 6818 6819 /* Ideally we would also validate that the hash type matches 6820 * the hardware. Alas, this is always set to unknown on team 6821 * interfaces. 6822 */ 6823 return true; 6824 } 6825 6826 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6827 { 6828 struct mv88e6xxx_chip *chip = ds->priv; 6829 struct dsa_port *dp; 6830 u16 map = 0; 6831 int id; 6832 6833 /* DSA LAG IDs are one-based, hardware is zero-based */ 6834 id = lag.id - 1; 6835 6836 /* Build the map of all ports to distribute flows destined for 6837 * this LAG. This can be either a local user port, or a DSA 6838 * port if the LAG port is on a remote chip. 6839 */ 6840 dsa_lag_foreach_port(dp, ds->dst, &lag) 6841 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6842 6843 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6844 } 6845 6846 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6847 /* Row number corresponds to the number of active members in a 6848 * LAG. Each column states which of the eight hash buckets are 6849 * mapped to the column:th port in the LAG. 6850 * 6851 * Example: In a LAG with three active ports, the second port 6852 * ([2][1]) would be selected for traffic mapped to buckets 6853 * 3,4,5 (0x38). 6854 */ 6855 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6856 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6857 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6858 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6859 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6860 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6861 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6862 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6863 }; 6864 6865 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6866 int num_tx, int nth) 6867 { 6868 u8 active = 0; 6869 int i; 6870 6871 num_tx = num_tx <= 8 ? num_tx : 8; 6872 if (nth < num_tx) 6873 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6874 6875 for (i = 0; i < 8; i++) { 6876 if (BIT(i) & active) 6877 mask[i] |= BIT(port); 6878 } 6879 } 6880 6881 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6882 { 6883 struct mv88e6xxx_chip *chip = ds->priv; 6884 unsigned int id, num_tx; 6885 struct dsa_port *dp; 6886 struct dsa_lag *lag; 6887 int i, err, nth; 6888 u16 mask[8]; 6889 u16 ivec; 6890 6891 /* Assume no port is a member of any LAG. */ 6892 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6893 6894 /* Disable all masks for ports that _are_ members of a LAG. */ 6895 dsa_switch_for_each_port(dp, ds) { 6896 if (!dp->lag) 6897 continue; 6898 6899 ivec &= ~BIT(dp->index); 6900 } 6901 6902 for (i = 0; i < 8; i++) 6903 mask[i] = ivec; 6904 6905 /* Enable the correct subset of masks for all LAG ports that 6906 * are in the Tx set. 6907 */ 6908 dsa_lags_foreach_id(id, ds->dst) { 6909 lag = dsa_lag_by_id(ds->dst, id); 6910 if (!lag) 6911 continue; 6912 6913 num_tx = 0; 6914 dsa_lag_foreach_port(dp, ds->dst, lag) { 6915 if (dp->lag_tx_enabled) 6916 num_tx++; 6917 } 6918 6919 if (!num_tx) 6920 continue; 6921 6922 nth = 0; 6923 dsa_lag_foreach_port(dp, ds->dst, lag) { 6924 if (!dp->lag_tx_enabled) 6925 continue; 6926 6927 if (dp->ds == ds) 6928 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6929 num_tx, nth); 6930 6931 nth++; 6932 } 6933 } 6934 6935 for (i = 0; i < 8; i++) { 6936 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6937 if (err) 6938 return err; 6939 } 6940 6941 return 0; 6942 } 6943 6944 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6945 struct dsa_lag lag) 6946 { 6947 int err; 6948 6949 err = mv88e6xxx_lag_sync_masks(ds); 6950 6951 if (!err) 6952 err = mv88e6xxx_lag_sync_map(ds, lag); 6953 6954 return err; 6955 } 6956 6957 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6958 { 6959 struct mv88e6xxx_chip *chip = ds->priv; 6960 int err; 6961 6962 mv88e6xxx_reg_lock(chip); 6963 err = mv88e6xxx_lag_sync_masks(ds); 6964 mv88e6xxx_reg_unlock(chip); 6965 return err; 6966 } 6967 6968 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6969 struct dsa_lag lag, 6970 struct netdev_lag_upper_info *info, 6971 struct netlink_ext_ack *extack) 6972 { 6973 struct mv88e6xxx_chip *chip = ds->priv; 6974 int err, id; 6975 6976 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6977 return -EOPNOTSUPP; 6978 6979 /* DSA LAG IDs are one-based */ 6980 id = lag.id - 1; 6981 6982 mv88e6xxx_reg_lock(chip); 6983 6984 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6985 if (err) 6986 goto err_unlock; 6987 6988 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6989 if (err) 6990 goto err_clear_trunk; 6991 6992 mv88e6xxx_reg_unlock(chip); 6993 return 0; 6994 6995 err_clear_trunk: 6996 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6997 err_unlock: 6998 mv88e6xxx_reg_unlock(chip); 6999 return err; 7000 } 7001 7002 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7003 struct dsa_lag lag) 7004 { 7005 struct mv88e6xxx_chip *chip = ds->priv; 7006 int err_sync, err_trunk; 7007 7008 mv88e6xxx_reg_lock(chip); 7009 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7010 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7011 mv88e6xxx_reg_unlock(chip); 7012 return err_sync ? : err_trunk; 7013 } 7014 7015 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7016 int port) 7017 { 7018 struct mv88e6xxx_chip *chip = ds->priv; 7019 int err; 7020 7021 mv88e6xxx_reg_lock(chip); 7022 err = mv88e6xxx_lag_sync_masks(ds); 7023 mv88e6xxx_reg_unlock(chip); 7024 return err; 7025 } 7026 7027 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7028 int port, struct dsa_lag lag, 7029 struct netdev_lag_upper_info *info, 7030 struct netlink_ext_ack *extack) 7031 { 7032 struct mv88e6xxx_chip *chip = ds->priv; 7033 int err; 7034 7035 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7036 return -EOPNOTSUPP; 7037 7038 mv88e6xxx_reg_lock(chip); 7039 7040 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7041 if (err) 7042 goto unlock; 7043 7044 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7045 7046 unlock: 7047 mv88e6xxx_reg_unlock(chip); 7048 return err; 7049 } 7050 7051 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7052 int port, struct dsa_lag lag) 7053 { 7054 struct mv88e6xxx_chip *chip = ds->priv; 7055 int err_sync, err_pvt; 7056 7057 mv88e6xxx_reg_lock(chip); 7058 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7059 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7060 mv88e6xxx_reg_unlock(chip); 7061 return err_sync ? : err_pvt; 7062 } 7063 7064 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7065 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7066 .mac_prepare = mv88e6xxx_mac_prepare, 7067 .mac_config = mv88e6xxx_mac_config, 7068 .mac_finish = mv88e6xxx_mac_finish, 7069 .mac_link_down = mv88e6xxx_mac_link_down, 7070 .mac_link_up = mv88e6xxx_mac_link_up, 7071 }; 7072 7073 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7074 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7075 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7076 .setup = mv88e6xxx_setup, 7077 .teardown = mv88e6xxx_teardown, 7078 .port_setup = mv88e6xxx_port_setup, 7079 .port_teardown = mv88e6xxx_port_teardown, 7080 .phylink_get_caps = mv88e6xxx_get_caps, 7081 .get_strings = mv88e6xxx_get_strings, 7082 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7083 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7084 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7085 .get_sset_count = mv88e6xxx_get_sset_count, 7086 .port_max_mtu = mv88e6xxx_get_max_mtu, 7087 .port_change_mtu = mv88e6xxx_change_mtu, 7088 .get_mac_eee = mv88e6xxx_get_mac_eee, 7089 .set_mac_eee = mv88e6xxx_set_mac_eee, 7090 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7091 .get_eeprom = mv88e6xxx_get_eeprom, 7092 .set_eeprom = mv88e6xxx_set_eeprom, 7093 .get_regs_len = mv88e6xxx_get_regs_len, 7094 .get_regs = mv88e6xxx_get_regs, 7095 .get_rxnfc = mv88e6xxx_get_rxnfc, 7096 .set_rxnfc = mv88e6xxx_set_rxnfc, 7097 .set_ageing_time = mv88e6xxx_set_ageing_time, 7098 .port_bridge_join = mv88e6xxx_port_bridge_join, 7099 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7100 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7101 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7102 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7103 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7104 .port_fast_age = mv88e6xxx_port_fast_age, 7105 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7106 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7107 .port_vlan_add = mv88e6xxx_port_vlan_add, 7108 .port_vlan_del = mv88e6xxx_port_vlan_del, 7109 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7110 .port_fdb_add = mv88e6xxx_port_fdb_add, 7111 .port_fdb_del = mv88e6xxx_port_fdb_del, 7112 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7113 .port_mdb_add = mv88e6xxx_port_mdb_add, 7114 .port_mdb_del = mv88e6xxx_port_mdb_del, 7115 .port_mirror_add = mv88e6xxx_port_mirror_add, 7116 .port_mirror_del = mv88e6xxx_port_mirror_del, 7117 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7118 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7119 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7120 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7121 .port_txtstamp = mv88e6xxx_port_txtstamp, 7122 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7123 .get_ts_info = mv88e6xxx_get_ts_info, 7124 .devlink_param_get = mv88e6xxx_devlink_param_get, 7125 .devlink_param_set = mv88e6xxx_devlink_param_set, 7126 .devlink_info_get = mv88e6xxx_devlink_info_get, 7127 .port_lag_change = mv88e6xxx_port_lag_change, 7128 .port_lag_join = mv88e6xxx_port_lag_join, 7129 .port_lag_leave = mv88e6xxx_port_lag_leave, 7130 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7131 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7132 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7133 }; 7134 7135 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7136 { 7137 struct device *dev = chip->dev; 7138 struct dsa_switch *ds; 7139 7140 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7141 if (!ds) 7142 return -ENOMEM; 7143 7144 ds->dev = dev; 7145 ds->num_ports = mv88e6xxx_num_ports(chip); 7146 ds->priv = chip; 7147 ds->dev = dev; 7148 ds->ops = &mv88e6xxx_switch_ops; 7149 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7150 ds->ageing_time_min = chip->info->age_time_coeff; 7151 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7152 7153 /* Some chips support up to 32, but that requires enabling the 7154 * 5-bit port mode, which we do not support. 640k^W16 ought to 7155 * be enough for anyone. 7156 */ 7157 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7158 7159 dev_set_drvdata(dev, ds); 7160 7161 return dsa_register_switch(ds); 7162 } 7163 7164 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7165 { 7166 dsa_unregister_switch(chip->ds); 7167 } 7168 7169 static const void *pdata_device_get_match_data(struct device *dev) 7170 { 7171 const struct of_device_id *matches = dev->driver->of_match_table; 7172 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7173 7174 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7175 matches++) { 7176 if (!strcmp(pdata->compatible, matches->compatible)) 7177 return matches->data; 7178 } 7179 return NULL; 7180 } 7181 7182 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7183 * would be lost after a power cycle so prevent it to be suspended. 7184 */ 7185 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7186 { 7187 return -EOPNOTSUPP; 7188 } 7189 7190 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7191 { 7192 return 0; 7193 } 7194 7195 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7196 7197 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7198 { 7199 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7200 const struct mv88e6xxx_info *compat_info = NULL; 7201 struct device *dev = &mdiodev->dev; 7202 struct device_node *np = dev->of_node; 7203 struct mv88e6xxx_chip *chip; 7204 int port; 7205 int err; 7206 7207 if (!np && !pdata) 7208 return -EINVAL; 7209 7210 if (np) 7211 compat_info = of_device_get_match_data(dev); 7212 7213 if (pdata) { 7214 compat_info = pdata_device_get_match_data(dev); 7215 7216 if (!pdata->netdev) 7217 return -EINVAL; 7218 7219 for (port = 0; port < DSA_MAX_PORTS; port++) { 7220 if (!(pdata->enabled_ports & (1 << port))) 7221 continue; 7222 if (strcmp(pdata->cd.port_names[port], "cpu")) 7223 continue; 7224 pdata->cd.netdev[port] = &pdata->netdev->dev; 7225 break; 7226 } 7227 } 7228 7229 if (!compat_info) 7230 return -EINVAL; 7231 7232 chip = mv88e6xxx_alloc_chip(dev); 7233 if (!chip) { 7234 err = -ENOMEM; 7235 goto out; 7236 } 7237 7238 chip->info = compat_info; 7239 7240 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7241 if (IS_ERR(chip->reset)) { 7242 err = PTR_ERR(chip->reset); 7243 goto out; 7244 } 7245 if (chip->reset) 7246 usleep_range(10000, 20000); 7247 7248 /* Detect if the device is configured in single chip addressing mode, 7249 * otherwise continue with address specific smi init/detection. 7250 */ 7251 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7252 if (err) { 7253 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7254 if (err) 7255 goto out; 7256 7257 err = mv88e6xxx_detect(chip); 7258 if (err) 7259 goto out; 7260 } 7261 7262 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7263 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7264 else 7265 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7266 7267 mv88e6xxx_phy_init(chip); 7268 7269 if (chip->info->ops->get_eeprom) { 7270 if (np) 7271 of_property_read_u32(np, "eeprom-length", 7272 &chip->eeprom_len); 7273 else 7274 chip->eeprom_len = pdata->eeprom_len; 7275 } 7276 7277 mv88e6xxx_reg_lock(chip); 7278 err = mv88e6xxx_switch_reset(chip); 7279 mv88e6xxx_reg_unlock(chip); 7280 if (err) 7281 goto out; 7282 7283 if (np) { 7284 chip->irq = of_irq_get(np, 0); 7285 if (chip->irq == -EPROBE_DEFER) { 7286 err = chip->irq; 7287 goto out; 7288 } 7289 } 7290 7291 if (pdata) 7292 chip->irq = pdata->irq; 7293 7294 /* Has to be performed before the MDIO bus is created, because 7295 * the PHYs will link their interrupts to these interrupt 7296 * controllers 7297 */ 7298 mv88e6xxx_reg_lock(chip); 7299 if (chip->irq > 0) 7300 err = mv88e6xxx_g1_irq_setup(chip); 7301 else 7302 err = mv88e6xxx_irq_poll_setup(chip); 7303 mv88e6xxx_reg_unlock(chip); 7304 7305 if (err) 7306 goto out; 7307 7308 if (chip->info->g2_irqs > 0) { 7309 err = mv88e6xxx_g2_irq_setup(chip); 7310 if (err) 7311 goto out_g1_irq; 7312 } 7313 7314 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7315 if (err) 7316 goto out_g2_irq; 7317 7318 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7319 if (err) 7320 goto out_g1_atu_prob_irq; 7321 7322 err = mv88e6xxx_register_switch(chip); 7323 if (err) 7324 goto out_g1_vtu_prob_irq; 7325 7326 return 0; 7327 7328 out_g1_vtu_prob_irq: 7329 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7330 out_g1_atu_prob_irq: 7331 mv88e6xxx_g1_atu_prob_irq_free(chip); 7332 out_g2_irq: 7333 if (chip->info->g2_irqs > 0) 7334 mv88e6xxx_g2_irq_free(chip); 7335 out_g1_irq: 7336 if (chip->irq > 0) 7337 mv88e6xxx_g1_irq_free(chip); 7338 else 7339 mv88e6xxx_irq_poll_free(chip); 7340 out: 7341 if (pdata) 7342 dev_put(pdata->netdev); 7343 7344 return err; 7345 } 7346 7347 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7348 { 7349 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7350 struct mv88e6xxx_chip *chip; 7351 7352 if (!ds) 7353 return; 7354 7355 chip = ds->priv; 7356 7357 if (chip->info->ptp_support) { 7358 mv88e6xxx_hwtstamp_free(chip); 7359 mv88e6xxx_ptp_free(chip); 7360 } 7361 7362 mv88e6xxx_phy_destroy(chip); 7363 mv88e6xxx_unregister_switch(chip); 7364 7365 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7366 mv88e6xxx_g1_atu_prob_irq_free(chip); 7367 7368 if (chip->info->g2_irqs > 0) 7369 mv88e6xxx_g2_irq_free(chip); 7370 7371 if (chip->irq > 0) 7372 mv88e6xxx_g1_irq_free(chip); 7373 else 7374 mv88e6xxx_irq_poll_free(chip); 7375 } 7376 7377 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7378 { 7379 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7380 7381 if (!ds) 7382 return; 7383 7384 dsa_switch_shutdown(ds); 7385 7386 dev_set_drvdata(&mdiodev->dev, NULL); 7387 } 7388 7389 static const struct of_device_id mv88e6xxx_of_match[] = { 7390 { 7391 .compatible = "marvell,mv88e6085", 7392 .data = &mv88e6xxx_table[MV88E6085], 7393 }, 7394 { 7395 .compatible = "marvell,mv88e6190", 7396 .data = &mv88e6xxx_table[MV88E6190], 7397 }, 7398 { 7399 .compatible = "marvell,mv88e6250", 7400 .data = &mv88e6xxx_table[MV88E6250], 7401 }, 7402 { /* sentinel */ }, 7403 }; 7404 7405 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7406 7407 static struct mdio_driver mv88e6xxx_driver = { 7408 .probe = mv88e6xxx_probe, 7409 .remove = mv88e6xxx_remove, 7410 .shutdown = mv88e6xxx_shutdown, 7411 .mdiodrv.driver = { 7412 .name = "mv88e6085", 7413 .of_match_table = mv88e6xxx_of_match, 7414 .pm = &mv88e6xxx_pm_ops, 7415 }, 7416 }; 7417 7418 mdio_module_driver(mv88e6xxx_driver); 7419 7420 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7421 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7422 MODULE_LICENSE("GPL"); 7423