1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 u16 ctl1; 265 int err; 266 267 mutex_lock(&chip->reg_lock); 268 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 269 mutex_unlock(&chip->reg_lock); 270 271 if (err) 272 goto out; 273 274 do { 275 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 276 if (reg & (1 << n)) { 277 sub_irq = irq_find_mapping(chip->g1_irq.domain, 278 n); 279 handle_nested_irq(sub_irq); 280 ++nhandled; 281 } 282 } 283 284 mutex_lock(&chip->reg_lock); 285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 286 if (err) 287 goto unlock; 288 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 289 unlock: 290 mutex_unlock(&chip->reg_lock); 291 if (err) 292 goto out; 293 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 294 } while (reg & ctl1); 295 296 out: 297 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 298 } 299 300 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 301 { 302 struct mv88e6xxx_chip *chip = dev_id; 303 304 return mv88e6xxx_g1_irq_thread_work(chip); 305 } 306 307 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 308 { 309 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 310 311 mutex_lock(&chip->reg_lock); 312 } 313 314 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 315 { 316 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 317 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 318 u16 reg; 319 int err; 320 321 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 322 if (err) 323 goto out; 324 325 reg &= ~mask; 326 reg |= (~chip->g1_irq.masked & mask); 327 328 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 329 if (err) 330 goto out; 331 332 out: 333 mutex_unlock(&chip->reg_lock); 334 } 335 336 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 337 .name = "mv88e6xxx-g1", 338 .irq_mask = mv88e6xxx_g1_irq_mask, 339 .irq_unmask = mv88e6xxx_g1_irq_unmask, 340 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 341 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 342 }; 343 344 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 345 unsigned int irq, 346 irq_hw_number_t hwirq) 347 { 348 struct mv88e6xxx_chip *chip = d->host_data; 349 350 irq_set_chip_data(irq, d->host_data); 351 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 352 irq_set_noprobe(irq); 353 354 return 0; 355 } 356 357 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 358 .map = mv88e6xxx_g1_irq_domain_map, 359 .xlate = irq_domain_xlate_twocell, 360 }; 361 362 /* To be called with reg_lock held */ 363 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 364 { 365 int irq, virq; 366 u16 mask; 367 368 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 369 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 370 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 371 372 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 373 virq = irq_find_mapping(chip->g1_irq.domain, irq); 374 irq_dispose_mapping(virq); 375 } 376 377 irq_domain_remove(chip->g1_irq.domain); 378 } 379 380 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 381 { 382 /* 383 * free_irq must be called without reg_lock taken because the irq 384 * handler takes this lock, too. 385 */ 386 free_irq(chip->irq, chip); 387 388 mutex_lock(&chip->reg_lock); 389 mv88e6xxx_g1_irq_free_common(chip); 390 mutex_unlock(&chip->reg_lock); 391 } 392 393 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 394 { 395 int err, irq, virq; 396 u16 reg, mask; 397 398 chip->g1_irq.nirqs = chip->info->g1_irqs; 399 chip->g1_irq.domain = irq_domain_add_simple( 400 NULL, chip->g1_irq.nirqs, 0, 401 &mv88e6xxx_g1_irq_domain_ops, chip); 402 if (!chip->g1_irq.domain) 403 return -ENOMEM; 404 405 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 406 irq_create_mapping(chip->g1_irq.domain, irq); 407 408 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 409 chip->g1_irq.masked = ~0; 410 411 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 412 if (err) 413 goto out_mapping; 414 415 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 416 417 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 418 if (err) 419 goto out_disable; 420 421 /* Reading the interrupt status clears (most of) them */ 422 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 423 if (err) 424 goto out_disable; 425 426 return 0; 427 428 out_disable: 429 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 430 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 431 432 out_mapping: 433 for (irq = 0; irq < 16; irq++) { 434 virq = irq_find_mapping(chip->g1_irq.domain, irq); 435 irq_dispose_mapping(virq); 436 } 437 438 irq_domain_remove(chip->g1_irq.domain); 439 440 return err; 441 } 442 443 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 444 { 445 static struct lock_class_key lock_key; 446 static struct lock_class_key request_key; 447 int err; 448 449 err = mv88e6xxx_g1_irq_setup_common(chip); 450 if (err) 451 return err; 452 453 /* These lock classes tells lockdep that global 1 irqs are in 454 * a different category than their parent GPIO, so it won't 455 * report false recursion. 456 */ 457 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 458 459 mutex_unlock(&chip->reg_lock); 460 err = request_threaded_irq(chip->irq, NULL, 461 mv88e6xxx_g1_irq_thread_fn, 462 IRQF_ONESHOT | IRQF_SHARED, 463 dev_name(chip->dev), chip); 464 mutex_lock(&chip->reg_lock); 465 if (err) 466 mv88e6xxx_g1_irq_free_common(chip); 467 468 return err; 469 } 470 471 static void mv88e6xxx_irq_poll(struct kthread_work *work) 472 { 473 struct mv88e6xxx_chip *chip = container_of(work, 474 struct mv88e6xxx_chip, 475 irq_poll_work.work); 476 mv88e6xxx_g1_irq_thread_work(chip); 477 478 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 479 msecs_to_jiffies(100)); 480 } 481 482 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 483 { 484 int err; 485 486 err = mv88e6xxx_g1_irq_setup_common(chip); 487 if (err) 488 return err; 489 490 kthread_init_delayed_work(&chip->irq_poll_work, 491 mv88e6xxx_irq_poll); 492 493 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 494 if (IS_ERR(chip->kworker)) 495 return PTR_ERR(chip->kworker); 496 497 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 498 msecs_to_jiffies(100)); 499 500 return 0; 501 } 502 503 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 504 { 505 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 506 kthread_destroy_worker(chip->kworker); 507 508 mutex_lock(&chip->reg_lock); 509 mv88e6xxx_g1_irq_free_common(chip); 510 mutex_unlock(&chip->reg_lock); 511 } 512 513 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 514 { 515 int i; 516 517 for (i = 0; i < 16; i++) { 518 u16 val; 519 int err; 520 521 err = mv88e6xxx_read(chip, addr, reg, &val); 522 if (err) 523 return err; 524 525 if (!(val & mask)) 526 return 0; 527 528 usleep_range(1000, 2000); 529 } 530 531 dev_err(chip->dev, "Timeout while waiting for switch\n"); 532 return -ETIMEDOUT; 533 } 534 535 /* Indirect write to single pointer-data register with an Update bit */ 536 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 537 { 538 u16 val; 539 int err; 540 541 /* Wait until the previous operation is completed */ 542 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 543 if (err) 544 return err; 545 546 /* Set the Update bit to trigger a write operation */ 547 val = BIT(15) | update; 548 549 return mv88e6xxx_write(chip, addr, reg, val); 550 } 551 552 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 553 int speed, int duplex, int pause, 554 phy_interface_t mode) 555 { 556 struct phylink_link_state state; 557 int err; 558 559 if (!chip->info->ops->port_set_link) 560 return 0; 561 562 if (!chip->info->ops->port_link_state) 563 return 0; 564 565 err = chip->info->ops->port_link_state(chip, port, &state); 566 if (err) 567 return err; 568 569 /* Has anything actually changed? We don't expect the 570 * interface mode to change without one of the other 571 * parameters also changing 572 */ 573 if (state.link == link && 574 state.speed == speed && 575 state.duplex == duplex) 576 return 0; 577 578 /* Port's MAC control must not be changed unless the link is down */ 579 err = chip->info->ops->port_set_link(chip, port, 0); 580 if (err) 581 return err; 582 583 if (chip->info->ops->port_set_speed) { 584 err = chip->info->ops->port_set_speed(chip, port, speed); 585 if (err && err != -EOPNOTSUPP) 586 goto restore_link; 587 } 588 589 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 590 mode = chip->info->ops->port_max_speed_mode(port); 591 592 if (chip->info->ops->port_set_pause) { 593 err = chip->info->ops->port_set_pause(chip, port, pause); 594 if (err) 595 goto restore_link; 596 } 597 598 if (chip->info->ops->port_set_duplex) { 599 err = chip->info->ops->port_set_duplex(chip, port, duplex); 600 if (err && err != -EOPNOTSUPP) 601 goto restore_link; 602 } 603 604 if (chip->info->ops->port_set_rgmii_delay) { 605 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 606 if (err && err != -EOPNOTSUPP) 607 goto restore_link; 608 } 609 610 if (chip->info->ops->port_set_cmode) { 611 err = chip->info->ops->port_set_cmode(chip, port, mode); 612 if (err && err != -EOPNOTSUPP) 613 goto restore_link; 614 } 615 616 err = 0; 617 restore_link: 618 if (chip->info->ops->port_set_link(chip, port, link)) 619 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 620 621 return err; 622 } 623 624 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 625 { 626 struct mv88e6xxx_chip *chip = ds->priv; 627 628 return port < chip->info->num_internal_phys; 629 } 630 631 /* We expect the switch to perform auto negotiation if there is a real 632 * phy. However, in the case of a fixed link phy, we force the port 633 * settings from the fixed link settings. 634 */ 635 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 636 struct phy_device *phydev) 637 { 638 struct mv88e6xxx_chip *chip = ds->priv; 639 int err; 640 641 if (!phy_is_pseudo_fixed_link(phydev) && 642 mv88e6xxx_phy_is_internal(ds, port)) 643 return; 644 645 mutex_lock(&chip->reg_lock); 646 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 647 phydev->duplex, phydev->pause, 648 phydev->interface); 649 mutex_unlock(&chip->reg_lock); 650 651 if (err && err != -EOPNOTSUPP) 652 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 653 } 654 655 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 656 unsigned long *mask, 657 struct phylink_link_state *state) 658 { 659 if (!phy_interface_mode_is_8023z(state->interface)) { 660 /* 10M and 100M are only supported in non-802.3z mode */ 661 phylink_set(mask, 10baseT_Half); 662 phylink_set(mask, 10baseT_Full); 663 phylink_set(mask, 100baseT_Half); 664 phylink_set(mask, 100baseT_Full); 665 } 666 } 667 668 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 669 unsigned long *mask, 670 struct phylink_link_state *state) 671 { 672 /* FIXME: if the port is in 1000Base-X mode, then it only supports 673 * 1000M FD speeds. In this case, CMODE will indicate 5. 674 */ 675 phylink_set(mask, 1000baseT_Full); 676 phylink_set(mask, 1000baseX_Full); 677 678 mv88e6065_phylink_validate(chip, port, mask, state); 679 } 680 681 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 682 unsigned long *mask, 683 struct phylink_link_state *state) 684 { 685 if (port >= 5) 686 phylink_set(mask, 2500baseX_Full); 687 688 /* No ethtool bits for 200Mbps */ 689 phylink_set(mask, 1000baseT_Full); 690 phylink_set(mask, 1000baseX_Full); 691 692 mv88e6065_phylink_validate(chip, port, mask, state); 693 } 694 695 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 696 unsigned long *mask, 697 struct phylink_link_state *state) 698 { 699 /* No ethtool bits for 200Mbps */ 700 phylink_set(mask, 1000baseT_Full); 701 phylink_set(mask, 1000baseX_Full); 702 703 mv88e6065_phylink_validate(chip, port, mask, state); 704 } 705 706 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 707 unsigned long *mask, 708 struct phylink_link_state *state) 709 { 710 if (port >= 9) { 711 phylink_set(mask, 2500baseX_Full); 712 phylink_set(mask, 2500baseT_Full); 713 } 714 715 /* No ethtool bits for 200Mbps */ 716 phylink_set(mask, 1000baseT_Full); 717 phylink_set(mask, 1000baseX_Full); 718 719 mv88e6065_phylink_validate(chip, port, mask, state); 720 } 721 722 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 723 unsigned long *mask, 724 struct phylink_link_state *state) 725 { 726 if (port >= 9) { 727 phylink_set(mask, 10000baseT_Full); 728 phylink_set(mask, 10000baseKR_Full); 729 } 730 731 mv88e6390_phylink_validate(chip, port, mask, state); 732 } 733 734 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 735 unsigned long *supported, 736 struct phylink_link_state *state) 737 { 738 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 739 struct mv88e6xxx_chip *chip = ds->priv; 740 741 /* Allow all the expected bits */ 742 phylink_set(mask, Autoneg); 743 phylink_set(mask, Pause); 744 phylink_set_port_modes(mask); 745 746 if (chip->info->ops->phylink_validate) 747 chip->info->ops->phylink_validate(chip, port, mask, state); 748 749 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 750 bitmap_and(state->advertising, state->advertising, mask, 751 __ETHTOOL_LINK_MODE_MASK_NBITS); 752 753 /* We can only operate at 2500BaseX or 1000BaseX. If requested 754 * to advertise both, only report advertising at 2500BaseX. 755 */ 756 phylink_helper_basex_speed(state); 757 } 758 759 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 760 struct phylink_link_state *state) 761 { 762 struct mv88e6xxx_chip *chip = ds->priv; 763 int err; 764 765 mutex_lock(&chip->reg_lock); 766 if (chip->info->ops->port_link_state) 767 err = chip->info->ops->port_link_state(chip, port, state); 768 else 769 err = -EOPNOTSUPP; 770 mutex_unlock(&chip->reg_lock); 771 772 return err; 773 } 774 775 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 776 unsigned int mode, 777 const struct phylink_link_state *state) 778 { 779 struct mv88e6xxx_chip *chip = ds->priv; 780 int speed, duplex, link, pause, err; 781 782 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 783 return; 784 785 if (mode == MLO_AN_FIXED) { 786 link = LINK_FORCED_UP; 787 speed = state->speed; 788 duplex = state->duplex; 789 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 790 link = state->link; 791 speed = state->speed; 792 duplex = state->duplex; 793 } else { 794 speed = SPEED_UNFORCED; 795 duplex = DUPLEX_UNFORCED; 796 link = LINK_UNFORCED; 797 } 798 pause = !!phylink_test(state->advertising, Pause); 799 800 mutex_lock(&chip->reg_lock); 801 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 802 state->interface); 803 mutex_unlock(&chip->reg_lock); 804 805 if (err && err != -EOPNOTSUPP) 806 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 807 } 808 809 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 810 { 811 struct mv88e6xxx_chip *chip = ds->priv; 812 int err; 813 814 mutex_lock(&chip->reg_lock); 815 err = chip->info->ops->port_set_link(chip, port, link); 816 mutex_unlock(&chip->reg_lock); 817 818 if (err) 819 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 820 } 821 822 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 823 unsigned int mode, 824 phy_interface_t interface) 825 { 826 if (mode == MLO_AN_FIXED) 827 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 828 } 829 830 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 831 unsigned int mode, phy_interface_t interface, 832 struct phy_device *phydev) 833 { 834 if (mode == MLO_AN_FIXED) 835 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 836 } 837 838 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 839 { 840 if (!chip->info->ops->stats_snapshot) 841 return -EOPNOTSUPP; 842 843 return chip->info->ops->stats_snapshot(chip, port); 844 } 845 846 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 847 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 848 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 849 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 850 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 851 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 852 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 853 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 854 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 855 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 856 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 857 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 858 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 859 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 860 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 861 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 862 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 863 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 864 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 865 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 866 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 867 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 868 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 869 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 870 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 871 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 872 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 873 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 874 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 875 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 876 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 877 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 878 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 879 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 880 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 881 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 882 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 883 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 884 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 885 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 886 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 887 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 888 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 889 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 890 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 891 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 892 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 893 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 894 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 895 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 896 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 897 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 898 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 899 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 900 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 901 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 902 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 903 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 904 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 905 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 906 }; 907 908 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 909 struct mv88e6xxx_hw_stat *s, 910 int port, u16 bank1_select, 911 u16 histogram) 912 { 913 u32 low; 914 u32 high = 0; 915 u16 reg = 0; 916 int err; 917 u64 value; 918 919 switch (s->type) { 920 case STATS_TYPE_PORT: 921 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 922 if (err) 923 return U64_MAX; 924 925 low = reg; 926 if (s->size == 4) { 927 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 928 if (err) 929 return U64_MAX; 930 high = reg; 931 } 932 break; 933 case STATS_TYPE_BANK1: 934 reg = bank1_select; 935 /* fall through */ 936 case STATS_TYPE_BANK0: 937 reg |= s->reg | histogram; 938 mv88e6xxx_g1_stats_read(chip, reg, &low); 939 if (s->size == 8) 940 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 941 break; 942 default: 943 return U64_MAX; 944 } 945 value = (((u64)high) << 32) | low; 946 return value; 947 } 948 949 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 950 uint8_t *data, int types) 951 { 952 struct mv88e6xxx_hw_stat *stat; 953 int i, j; 954 955 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 956 stat = &mv88e6xxx_hw_stats[i]; 957 if (stat->type & types) { 958 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 959 ETH_GSTRING_LEN); 960 j++; 961 } 962 } 963 964 return j; 965 } 966 967 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 968 uint8_t *data) 969 { 970 return mv88e6xxx_stats_get_strings(chip, data, 971 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 972 } 973 974 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 975 uint8_t *data) 976 { 977 return mv88e6xxx_stats_get_strings(chip, data, 978 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 979 } 980 981 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 982 "atu_member_violation", 983 "atu_miss_violation", 984 "atu_full_violation", 985 "vtu_member_violation", 986 "vtu_miss_violation", 987 }; 988 989 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 990 { 991 unsigned int i; 992 993 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 994 strlcpy(data + i * ETH_GSTRING_LEN, 995 mv88e6xxx_atu_vtu_stats_strings[i], 996 ETH_GSTRING_LEN); 997 } 998 999 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1000 u32 stringset, uint8_t *data) 1001 { 1002 struct mv88e6xxx_chip *chip = ds->priv; 1003 int count = 0; 1004 1005 if (stringset != ETH_SS_STATS) 1006 return; 1007 1008 mutex_lock(&chip->reg_lock); 1009 1010 if (chip->info->ops->stats_get_strings) 1011 count = chip->info->ops->stats_get_strings(chip, data); 1012 1013 if (chip->info->ops->serdes_get_strings) { 1014 data += count * ETH_GSTRING_LEN; 1015 count = chip->info->ops->serdes_get_strings(chip, port, data); 1016 } 1017 1018 data += count * ETH_GSTRING_LEN; 1019 mv88e6xxx_atu_vtu_get_strings(data); 1020 1021 mutex_unlock(&chip->reg_lock); 1022 } 1023 1024 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1025 int types) 1026 { 1027 struct mv88e6xxx_hw_stat *stat; 1028 int i, j; 1029 1030 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1031 stat = &mv88e6xxx_hw_stats[i]; 1032 if (stat->type & types) 1033 j++; 1034 } 1035 return j; 1036 } 1037 1038 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1039 { 1040 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1041 STATS_TYPE_PORT); 1042 } 1043 1044 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1045 { 1046 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1047 STATS_TYPE_BANK1); 1048 } 1049 1050 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1051 { 1052 struct mv88e6xxx_chip *chip = ds->priv; 1053 int serdes_count = 0; 1054 int count = 0; 1055 1056 if (sset != ETH_SS_STATS) 1057 return 0; 1058 1059 mutex_lock(&chip->reg_lock); 1060 if (chip->info->ops->stats_get_sset_count) 1061 count = chip->info->ops->stats_get_sset_count(chip); 1062 if (count < 0) 1063 goto out; 1064 1065 if (chip->info->ops->serdes_get_sset_count) 1066 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1067 port); 1068 if (serdes_count < 0) { 1069 count = serdes_count; 1070 goto out; 1071 } 1072 count += serdes_count; 1073 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1074 1075 out: 1076 mutex_unlock(&chip->reg_lock); 1077 1078 return count; 1079 } 1080 1081 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1082 uint64_t *data, int types, 1083 u16 bank1_select, u16 histogram) 1084 { 1085 struct mv88e6xxx_hw_stat *stat; 1086 int i, j; 1087 1088 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1089 stat = &mv88e6xxx_hw_stats[i]; 1090 if (stat->type & types) { 1091 mutex_lock(&chip->reg_lock); 1092 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1093 bank1_select, 1094 histogram); 1095 mutex_unlock(&chip->reg_lock); 1096 1097 j++; 1098 } 1099 } 1100 return j; 1101 } 1102 1103 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1104 uint64_t *data) 1105 { 1106 return mv88e6xxx_stats_get_stats(chip, port, data, 1107 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1108 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1109 } 1110 1111 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1112 uint64_t *data) 1113 { 1114 return mv88e6xxx_stats_get_stats(chip, port, data, 1115 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1116 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1117 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1118 } 1119 1120 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1121 uint64_t *data) 1122 { 1123 return mv88e6xxx_stats_get_stats(chip, port, data, 1124 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1125 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1126 0); 1127 } 1128 1129 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1130 uint64_t *data) 1131 { 1132 *data++ = chip->ports[port].atu_member_violation; 1133 *data++ = chip->ports[port].atu_miss_violation; 1134 *data++ = chip->ports[port].atu_full_violation; 1135 *data++ = chip->ports[port].vtu_member_violation; 1136 *data++ = chip->ports[port].vtu_miss_violation; 1137 } 1138 1139 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1140 uint64_t *data) 1141 { 1142 int count = 0; 1143 1144 if (chip->info->ops->stats_get_stats) 1145 count = chip->info->ops->stats_get_stats(chip, port, data); 1146 1147 mutex_lock(&chip->reg_lock); 1148 if (chip->info->ops->serdes_get_stats) { 1149 data += count; 1150 count = chip->info->ops->serdes_get_stats(chip, port, data); 1151 } 1152 data += count; 1153 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1154 mutex_unlock(&chip->reg_lock); 1155 } 1156 1157 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1158 uint64_t *data) 1159 { 1160 struct mv88e6xxx_chip *chip = ds->priv; 1161 int ret; 1162 1163 mutex_lock(&chip->reg_lock); 1164 1165 ret = mv88e6xxx_stats_snapshot(chip, port); 1166 mutex_unlock(&chip->reg_lock); 1167 1168 if (ret < 0) 1169 return; 1170 1171 mv88e6xxx_get_stats(chip, port, data); 1172 1173 } 1174 1175 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1176 { 1177 return 32 * sizeof(u16); 1178 } 1179 1180 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1181 struct ethtool_regs *regs, void *_p) 1182 { 1183 struct mv88e6xxx_chip *chip = ds->priv; 1184 int err; 1185 u16 reg; 1186 u16 *p = _p; 1187 int i; 1188 1189 regs->version = chip->info->prod_num; 1190 1191 memset(p, 0xff, 32 * sizeof(u16)); 1192 1193 mutex_lock(&chip->reg_lock); 1194 1195 for (i = 0; i < 32; i++) { 1196 1197 err = mv88e6xxx_port_read(chip, port, i, ®); 1198 if (!err) 1199 p[i] = reg; 1200 } 1201 1202 mutex_unlock(&chip->reg_lock); 1203 } 1204 1205 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1206 struct ethtool_eee *e) 1207 { 1208 /* Nothing to do on the port's MAC */ 1209 return 0; 1210 } 1211 1212 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1213 struct ethtool_eee *e) 1214 { 1215 /* Nothing to do on the port's MAC */ 1216 return 0; 1217 } 1218 1219 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1220 { 1221 struct dsa_switch *ds = NULL; 1222 struct net_device *br; 1223 u16 pvlan; 1224 int i; 1225 1226 if (dev < DSA_MAX_SWITCHES) 1227 ds = chip->ds->dst->ds[dev]; 1228 1229 /* Prevent frames from unknown switch or port */ 1230 if (!ds || port >= ds->num_ports) 1231 return 0; 1232 1233 /* Frames from DSA links and CPU ports can egress any local port */ 1234 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1235 return mv88e6xxx_port_mask(chip); 1236 1237 br = ds->ports[port].bridge_dev; 1238 pvlan = 0; 1239 1240 /* Frames from user ports can egress any local DSA links and CPU ports, 1241 * as well as any local member of their bridge group. 1242 */ 1243 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1244 if (dsa_is_cpu_port(chip->ds, i) || 1245 dsa_is_dsa_port(chip->ds, i) || 1246 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1247 pvlan |= BIT(i); 1248 1249 return pvlan; 1250 } 1251 1252 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1253 { 1254 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1255 1256 /* prevent frames from going back out of the port they came in on */ 1257 output_ports &= ~BIT(port); 1258 1259 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1260 } 1261 1262 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1263 u8 state) 1264 { 1265 struct mv88e6xxx_chip *chip = ds->priv; 1266 int err; 1267 1268 mutex_lock(&chip->reg_lock); 1269 err = mv88e6xxx_port_set_state(chip, port, state); 1270 mutex_unlock(&chip->reg_lock); 1271 1272 if (err) 1273 dev_err(ds->dev, "p%d: failed to update state\n", port); 1274 } 1275 1276 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1277 { 1278 int err; 1279 1280 if (chip->info->ops->ieee_pri_map) { 1281 err = chip->info->ops->ieee_pri_map(chip); 1282 if (err) 1283 return err; 1284 } 1285 1286 if (chip->info->ops->ip_pri_map) { 1287 err = chip->info->ops->ip_pri_map(chip); 1288 if (err) 1289 return err; 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1296 { 1297 int target, port; 1298 int err; 1299 1300 if (!chip->info->global2_addr) 1301 return 0; 1302 1303 /* Initialize the routing port to the 32 possible target devices */ 1304 for (target = 0; target < 32; target++) { 1305 port = 0x1f; 1306 if (target < DSA_MAX_SWITCHES) 1307 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1308 port = chip->ds->rtable[target]; 1309 1310 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1311 if (err) 1312 return err; 1313 } 1314 1315 if (chip->info->ops->set_cascade_port) { 1316 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1317 err = chip->info->ops->set_cascade_port(chip, port); 1318 if (err) 1319 return err; 1320 } 1321 1322 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1323 if (err) 1324 return err; 1325 1326 return 0; 1327 } 1328 1329 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1330 { 1331 /* Clear all trunk masks and mapping */ 1332 if (chip->info->global2_addr) 1333 return mv88e6xxx_g2_trunk_clear(chip); 1334 1335 return 0; 1336 } 1337 1338 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1339 { 1340 if (chip->info->ops->rmu_disable) 1341 return chip->info->ops->rmu_disable(chip); 1342 1343 return 0; 1344 } 1345 1346 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1347 { 1348 if (chip->info->ops->pot_clear) 1349 return chip->info->ops->pot_clear(chip); 1350 1351 return 0; 1352 } 1353 1354 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1355 { 1356 if (chip->info->ops->mgmt_rsvd2cpu) 1357 return chip->info->ops->mgmt_rsvd2cpu(chip); 1358 1359 return 0; 1360 } 1361 1362 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1363 { 1364 int err; 1365 1366 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1367 if (err) 1368 return err; 1369 1370 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1371 if (err) 1372 return err; 1373 1374 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1375 } 1376 1377 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1378 { 1379 int port; 1380 int err; 1381 1382 if (!chip->info->ops->irl_init_all) 1383 return 0; 1384 1385 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1386 /* Disable ingress rate limiting by resetting all per port 1387 * ingress rate limit resources to their initial state. 1388 */ 1389 err = chip->info->ops->irl_init_all(chip, port); 1390 if (err) 1391 return err; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1398 { 1399 if (chip->info->ops->set_switch_mac) { 1400 u8 addr[ETH_ALEN]; 1401 1402 eth_random_addr(addr); 1403 1404 return chip->info->ops->set_switch_mac(chip, addr); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1411 { 1412 u16 pvlan = 0; 1413 1414 if (!mv88e6xxx_has_pvt(chip)) 1415 return -EOPNOTSUPP; 1416 1417 /* Skip the local source device, which uses in-chip port VLAN */ 1418 if (dev != chip->ds->index) 1419 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1420 1421 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1422 } 1423 1424 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1425 { 1426 int dev, port; 1427 int err; 1428 1429 if (!mv88e6xxx_has_pvt(chip)) 1430 return 0; 1431 1432 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1433 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1434 */ 1435 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1436 if (err) 1437 return err; 1438 1439 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1440 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1441 err = mv88e6xxx_pvt_map(chip, dev, port); 1442 if (err) 1443 return err; 1444 } 1445 } 1446 1447 return 0; 1448 } 1449 1450 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1451 { 1452 struct mv88e6xxx_chip *chip = ds->priv; 1453 int err; 1454 1455 mutex_lock(&chip->reg_lock); 1456 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1457 mutex_unlock(&chip->reg_lock); 1458 1459 if (err) 1460 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1461 } 1462 1463 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1464 { 1465 if (!chip->info->max_vid) 1466 return 0; 1467 1468 return mv88e6xxx_g1_vtu_flush(chip); 1469 } 1470 1471 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1472 struct mv88e6xxx_vtu_entry *entry) 1473 { 1474 if (!chip->info->ops->vtu_getnext) 1475 return -EOPNOTSUPP; 1476 1477 return chip->info->ops->vtu_getnext(chip, entry); 1478 } 1479 1480 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1481 struct mv88e6xxx_vtu_entry *entry) 1482 { 1483 if (!chip->info->ops->vtu_loadpurge) 1484 return -EOPNOTSUPP; 1485 1486 return chip->info->ops->vtu_loadpurge(chip, entry); 1487 } 1488 1489 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1490 { 1491 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1492 struct mv88e6xxx_vtu_entry vlan = { 1493 .vid = chip->info->max_vid, 1494 }; 1495 int i, err; 1496 1497 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1498 1499 /* Set every FID bit used by the (un)bridged ports */ 1500 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1501 err = mv88e6xxx_port_get_fid(chip, i, fid); 1502 if (err) 1503 return err; 1504 1505 set_bit(*fid, fid_bitmap); 1506 } 1507 1508 /* Set every FID bit used by the VLAN entries */ 1509 do { 1510 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1511 if (err) 1512 return err; 1513 1514 if (!vlan.valid) 1515 break; 1516 1517 set_bit(vlan.fid, fid_bitmap); 1518 } while (vlan.vid < chip->info->max_vid); 1519 1520 /* The reset value 0x000 is used to indicate that multiple address 1521 * databases are not needed. Return the next positive available. 1522 */ 1523 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1524 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1525 return -ENOSPC; 1526 1527 /* Clear the database */ 1528 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1529 } 1530 1531 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1532 struct mv88e6xxx_vtu_entry *entry, bool new) 1533 { 1534 int err; 1535 1536 if (!vid) 1537 return -EINVAL; 1538 1539 entry->vid = vid - 1; 1540 entry->valid = false; 1541 1542 err = mv88e6xxx_vtu_getnext(chip, entry); 1543 if (err) 1544 return err; 1545 1546 if (entry->vid == vid && entry->valid) 1547 return 0; 1548 1549 if (new) { 1550 int i; 1551 1552 /* Initialize a fresh VLAN entry */ 1553 memset(entry, 0, sizeof(*entry)); 1554 entry->valid = true; 1555 entry->vid = vid; 1556 1557 /* Exclude all ports */ 1558 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1559 entry->member[i] = 1560 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1561 1562 return mv88e6xxx_atu_new(chip, &entry->fid); 1563 } 1564 1565 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1566 return -EOPNOTSUPP; 1567 } 1568 1569 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1570 u16 vid_begin, u16 vid_end) 1571 { 1572 struct mv88e6xxx_chip *chip = ds->priv; 1573 struct mv88e6xxx_vtu_entry vlan = { 1574 .vid = vid_begin - 1, 1575 }; 1576 int i, err; 1577 1578 /* DSA and CPU ports have to be members of multiple vlans */ 1579 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1580 return 0; 1581 1582 if (!vid_begin) 1583 return -EOPNOTSUPP; 1584 1585 mutex_lock(&chip->reg_lock); 1586 1587 do { 1588 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1589 if (err) 1590 goto unlock; 1591 1592 if (!vlan.valid) 1593 break; 1594 1595 if (vlan.vid > vid_end) 1596 break; 1597 1598 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1599 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1600 continue; 1601 1602 if (!ds->ports[i].slave) 1603 continue; 1604 1605 if (vlan.member[i] == 1606 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1607 continue; 1608 1609 if (dsa_to_port(ds, i)->bridge_dev == 1610 ds->ports[port].bridge_dev) 1611 break; /* same bridge, check next VLAN */ 1612 1613 if (!dsa_to_port(ds, i)->bridge_dev) 1614 continue; 1615 1616 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1617 port, vlan.vid, i, 1618 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1619 err = -EOPNOTSUPP; 1620 goto unlock; 1621 } 1622 } while (vlan.vid < vid_end); 1623 1624 unlock: 1625 mutex_unlock(&chip->reg_lock); 1626 1627 return err; 1628 } 1629 1630 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1631 bool vlan_filtering) 1632 { 1633 struct mv88e6xxx_chip *chip = ds->priv; 1634 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1635 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1636 int err; 1637 1638 if (!chip->info->max_vid) 1639 return -EOPNOTSUPP; 1640 1641 mutex_lock(&chip->reg_lock); 1642 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1643 mutex_unlock(&chip->reg_lock); 1644 1645 return err; 1646 } 1647 1648 static int 1649 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1650 const struct switchdev_obj_port_vlan *vlan) 1651 { 1652 struct mv88e6xxx_chip *chip = ds->priv; 1653 int err; 1654 1655 if (!chip->info->max_vid) 1656 return -EOPNOTSUPP; 1657 1658 /* If the requested port doesn't belong to the same bridge as the VLAN 1659 * members, do not support it (yet) and fallback to software VLAN. 1660 */ 1661 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1662 vlan->vid_end); 1663 if (err) 1664 return err; 1665 1666 /* We don't need any dynamic resource from the kernel (yet), 1667 * so skip the prepare phase. 1668 */ 1669 return 0; 1670 } 1671 1672 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1673 const unsigned char *addr, u16 vid, 1674 u8 state) 1675 { 1676 struct mv88e6xxx_vtu_entry vlan; 1677 struct mv88e6xxx_atu_entry entry; 1678 int err; 1679 1680 /* Null VLAN ID corresponds to the port private database */ 1681 if (vid == 0) 1682 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1683 else 1684 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1685 if (err) 1686 return err; 1687 1688 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1689 ether_addr_copy(entry.mac, addr); 1690 eth_addr_dec(entry.mac); 1691 1692 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1693 if (err) 1694 return err; 1695 1696 /* Initialize a fresh ATU entry if it isn't found */ 1697 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1698 !ether_addr_equal(entry.mac, addr)) { 1699 memset(&entry, 0, sizeof(entry)); 1700 ether_addr_copy(entry.mac, addr); 1701 } 1702 1703 /* Purge the ATU entry only if no port is using it anymore */ 1704 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1705 entry.portvec &= ~BIT(port); 1706 if (!entry.portvec) 1707 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1708 } else { 1709 entry.portvec |= BIT(port); 1710 entry.state = state; 1711 } 1712 1713 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1714 } 1715 1716 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1717 u16 vid) 1718 { 1719 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1720 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1721 1722 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1723 } 1724 1725 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1726 { 1727 int port; 1728 int err; 1729 1730 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1731 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1732 if (err) 1733 return err; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1740 u16 vid, u8 member) 1741 { 1742 struct mv88e6xxx_vtu_entry vlan; 1743 int err; 1744 1745 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1746 if (err) 1747 return err; 1748 1749 vlan.member[port] = member; 1750 1751 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1752 if (err) 1753 return err; 1754 1755 return mv88e6xxx_broadcast_setup(chip, vid); 1756 } 1757 1758 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1759 const struct switchdev_obj_port_vlan *vlan) 1760 { 1761 struct mv88e6xxx_chip *chip = ds->priv; 1762 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1763 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1764 u8 member; 1765 u16 vid; 1766 1767 if (!chip->info->max_vid) 1768 return; 1769 1770 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1771 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1772 else if (untagged) 1773 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1774 else 1775 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1776 1777 mutex_lock(&chip->reg_lock); 1778 1779 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1780 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1781 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1782 vid, untagged ? 'u' : 't'); 1783 1784 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1785 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1786 vlan->vid_end); 1787 1788 mutex_unlock(&chip->reg_lock); 1789 } 1790 1791 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1792 int port, u16 vid) 1793 { 1794 struct mv88e6xxx_vtu_entry vlan; 1795 int i, err; 1796 1797 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1798 if (err) 1799 return err; 1800 1801 /* Tell switchdev if this VLAN is handled in software */ 1802 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1803 return -EOPNOTSUPP; 1804 1805 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1806 1807 /* keep the VLAN unless all ports are excluded */ 1808 vlan.valid = false; 1809 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1810 if (vlan.member[i] != 1811 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1812 vlan.valid = true; 1813 break; 1814 } 1815 } 1816 1817 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1818 if (err) 1819 return err; 1820 1821 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1822 } 1823 1824 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1825 const struct switchdev_obj_port_vlan *vlan) 1826 { 1827 struct mv88e6xxx_chip *chip = ds->priv; 1828 u16 pvid, vid; 1829 int err = 0; 1830 1831 if (!chip->info->max_vid) 1832 return -EOPNOTSUPP; 1833 1834 mutex_lock(&chip->reg_lock); 1835 1836 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1837 if (err) 1838 goto unlock; 1839 1840 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1841 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1842 if (err) 1843 goto unlock; 1844 1845 if (vid == pvid) { 1846 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1847 if (err) 1848 goto unlock; 1849 } 1850 } 1851 1852 unlock: 1853 mutex_unlock(&chip->reg_lock); 1854 1855 return err; 1856 } 1857 1858 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1859 const unsigned char *addr, u16 vid) 1860 { 1861 struct mv88e6xxx_chip *chip = ds->priv; 1862 int err; 1863 1864 mutex_lock(&chip->reg_lock); 1865 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1866 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1867 mutex_unlock(&chip->reg_lock); 1868 1869 return err; 1870 } 1871 1872 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1873 const unsigned char *addr, u16 vid) 1874 { 1875 struct mv88e6xxx_chip *chip = ds->priv; 1876 int err; 1877 1878 mutex_lock(&chip->reg_lock); 1879 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1880 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1881 mutex_unlock(&chip->reg_lock); 1882 1883 return err; 1884 } 1885 1886 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1887 u16 fid, u16 vid, int port, 1888 dsa_fdb_dump_cb_t *cb, void *data) 1889 { 1890 struct mv88e6xxx_atu_entry addr; 1891 bool is_static; 1892 int err; 1893 1894 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1895 eth_broadcast_addr(addr.mac); 1896 1897 do { 1898 mutex_lock(&chip->reg_lock); 1899 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1900 mutex_unlock(&chip->reg_lock); 1901 if (err) 1902 return err; 1903 1904 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1905 break; 1906 1907 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1908 continue; 1909 1910 if (!is_unicast_ether_addr(addr.mac)) 1911 continue; 1912 1913 is_static = (addr.state == 1914 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1915 err = cb(addr.mac, vid, is_static, data); 1916 if (err) 1917 return err; 1918 } while (!is_broadcast_ether_addr(addr.mac)); 1919 1920 return err; 1921 } 1922 1923 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1924 dsa_fdb_dump_cb_t *cb, void *data) 1925 { 1926 struct mv88e6xxx_vtu_entry vlan = { 1927 .vid = chip->info->max_vid, 1928 }; 1929 u16 fid; 1930 int err; 1931 1932 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1933 mutex_lock(&chip->reg_lock); 1934 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1935 mutex_unlock(&chip->reg_lock); 1936 1937 if (err) 1938 return err; 1939 1940 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1941 if (err) 1942 return err; 1943 1944 /* Dump VLANs' Filtering Information Databases */ 1945 do { 1946 mutex_lock(&chip->reg_lock); 1947 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1948 mutex_unlock(&chip->reg_lock); 1949 if (err) 1950 return err; 1951 1952 if (!vlan.valid) 1953 break; 1954 1955 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1956 cb, data); 1957 if (err) 1958 return err; 1959 } while (vlan.vid < chip->info->max_vid); 1960 1961 return err; 1962 } 1963 1964 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1965 dsa_fdb_dump_cb_t *cb, void *data) 1966 { 1967 struct mv88e6xxx_chip *chip = ds->priv; 1968 1969 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1970 } 1971 1972 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1973 struct net_device *br) 1974 { 1975 struct dsa_switch *ds; 1976 int port; 1977 int dev; 1978 int err; 1979 1980 /* Remap the Port VLAN of each local bridge group member */ 1981 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1982 if (chip->ds->ports[port].bridge_dev == br) { 1983 err = mv88e6xxx_port_vlan_map(chip, port); 1984 if (err) 1985 return err; 1986 } 1987 } 1988 1989 if (!mv88e6xxx_has_pvt(chip)) 1990 return 0; 1991 1992 /* Remap the Port VLAN of each cross-chip bridge group member */ 1993 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1994 ds = chip->ds->dst->ds[dev]; 1995 if (!ds) 1996 break; 1997 1998 for (port = 0; port < ds->num_ports; ++port) { 1999 if (ds->ports[port].bridge_dev == br) { 2000 err = mv88e6xxx_pvt_map(chip, dev, port); 2001 if (err) 2002 return err; 2003 } 2004 } 2005 } 2006 2007 return 0; 2008 } 2009 2010 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2011 struct net_device *br) 2012 { 2013 struct mv88e6xxx_chip *chip = ds->priv; 2014 int err; 2015 2016 mutex_lock(&chip->reg_lock); 2017 err = mv88e6xxx_bridge_map(chip, br); 2018 mutex_unlock(&chip->reg_lock); 2019 2020 return err; 2021 } 2022 2023 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2024 struct net_device *br) 2025 { 2026 struct mv88e6xxx_chip *chip = ds->priv; 2027 2028 mutex_lock(&chip->reg_lock); 2029 if (mv88e6xxx_bridge_map(chip, br) || 2030 mv88e6xxx_port_vlan_map(chip, port)) 2031 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2032 mutex_unlock(&chip->reg_lock); 2033 } 2034 2035 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2036 int port, struct net_device *br) 2037 { 2038 struct mv88e6xxx_chip *chip = ds->priv; 2039 int err; 2040 2041 if (!mv88e6xxx_has_pvt(chip)) 2042 return 0; 2043 2044 mutex_lock(&chip->reg_lock); 2045 err = mv88e6xxx_pvt_map(chip, dev, port); 2046 mutex_unlock(&chip->reg_lock); 2047 2048 return err; 2049 } 2050 2051 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2052 int port, struct net_device *br) 2053 { 2054 struct mv88e6xxx_chip *chip = ds->priv; 2055 2056 if (!mv88e6xxx_has_pvt(chip)) 2057 return; 2058 2059 mutex_lock(&chip->reg_lock); 2060 if (mv88e6xxx_pvt_map(chip, dev, port)) 2061 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2062 mutex_unlock(&chip->reg_lock); 2063 } 2064 2065 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2066 { 2067 if (chip->info->ops->reset) 2068 return chip->info->ops->reset(chip); 2069 2070 return 0; 2071 } 2072 2073 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2074 { 2075 struct gpio_desc *gpiod = chip->reset; 2076 2077 /* If there is a GPIO connected to the reset pin, toggle it */ 2078 if (gpiod) { 2079 gpiod_set_value_cansleep(gpiod, 1); 2080 usleep_range(10000, 20000); 2081 gpiod_set_value_cansleep(gpiod, 0); 2082 usleep_range(10000, 20000); 2083 } 2084 } 2085 2086 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2087 { 2088 int i, err; 2089 2090 /* Set all ports to the Disabled state */ 2091 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2092 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2093 if (err) 2094 return err; 2095 } 2096 2097 /* Wait for transmit queues to drain, 2098 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2099 */ 2100 usleep_range(2000, 4000); 2101 2102 return 0; 2103 } 2104 2105 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2106 { 2107 int err; 2108 2109 err = mv88e6xxx_disable_ports(chip); 2110 if (err) 2111 return err; 2112 2113 mv88e6xxx_hardware_reset(chip); 2114 2115 return mv88e6xxx_software_reset(chip); 2116 } 2117 2118 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2119 enum mv88e6xxx_frame_mode frame, 2120 enum mv88e6xxx_egress_mode egress, u16 etype) 2121 { 2122 int err; 2123 2124 if (!chip->info->ops->port_set_frame_mode) 2125 return -EOPNOTSUPP; 2126 2127 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2128 if (err) 2129 return err; 2130 2131 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2132 if (err) 2133 return err; 2134 2135 if (chip->info->ops->port_set_ether_type) 2136 return chip->info->ops->port_set_ether_type(chip, port, etype); 2137 2138 return 0; 2139 } 2140 2141 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2142 { 2143 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2144 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2145 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2146 } 2147 2148 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2149 { 2150 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2151 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2152 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2153 } 2154 2155 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2156 { 2157 return mv88e6xxx_set_port_mode(chip, port, 2158 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2159 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2160 ETH_P_EDSA); 2161 } 2162 2163 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2164 { 2165 if (dsa_is_dsa_port(chip->ds, port)) 2166 return mv88e6xxx_set_port_mode_dsa(chip, port); 2167 2168 if (dsa_is_user_port(chip->ds, port)) 2169 return mv88e6xxx_set_port_mode_normal(chip, port); 2170 2171 /* Setup CPU port mode depending on its supported tag format */ 2172 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2173 return mv88e6xxx_set_port_mode_dsa(chip, port); 2174 2175 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2176 return mv88e6xxx_set_port_mode_edsa(chip, port); 2177 2178 return -EINVAL; 2179 } 2180 2181 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2182 { 2183 bool message = dsa_is_dsa_port(chip->ds, port); 2184 2185 return mv88e6xxx_port_set_message_port(chip, port, message); 2186 } 2187 2188 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2189 { 2190 struct dsa_switch *ds = chip->ds; 2191 bool flood; 2192 2193 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2194 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2195 if (chip->info->ops->port_set_egress_floods) 2196 return chip->info->ops->port_set_egress_floods(chip, port, 2197 flood, flood); 2198 2199 return 0; 2200 } 2201 2202 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2203 bool on) 2204 { 2205 if (chip->info->ops->serdes_power) 2206 return chip->info->ops->serdes_power(chip, port, on); 2207 2208 return 0; 2209 } 2210 2211 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2212 { 2213 struct dsa_switch *ds = chip->ds; 2214 int upstream_port; 2215 int err; 2216 2217 upstream_port = dsa_upstream_port(ds, port); 2218 if (chip->info->ops->port_set_upstream_port) { 2219 err = chip->info->ops->port_set_upstream_port(chip, port, 2220 upstream_port); 2221 if (err) 2222 return err; 2223 } 2224 2225 if (port == upstream_port) { 2226 if (chip->info->ops->set_cpu_port) { 2227 err = chip->info->ops->set_cpu_port(chip, 2228 upstream_port); 2229 if (err) 2230 return err; 2231 } 2232 2233 if (chip->info->ops->set_egress_port) { 2234 err = chip->info->ops->set_egress_port(chip, 2235 upstream_port); 2236 if (err) 2237 return err; 2238 } 2239 } 2240 2241 return 0; 2242 } 2243 2244 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2245 { 2246 struct dsa_switch *ds = chip->ds; 2247 int err; 2248 u16 reg; 2249 2250 chip->ports[port].chip = chip; 2251 chip->ports[port].port = port; 2252 2253 /* MAC Forcing register: don't force link, speed, duplex or flow control 2254 * state to any particular values on physical ports, but force the CPU 2255 * port and all DSA ports to their maximum bandwidth and full duplex. 2256 */ 2257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2258 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2259 SPEED_MAX, DUPLEX_FULL, 2260 PAUSE_OFF, 2261 PHY_INTERFACE_MODE_NA); 2262 else 2263 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2264 SPEED_UNFORCED, DUPLEX_UNFORCED, 2265 PAUSE_ON, 2266 PHY_INTERFACE_MODE_NA); 2267 if (err) 2268 return err; 2269 2270 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2271 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2272 * tunneling, determine priority by looking at 802.1p and IP 2273 * priority fields (IP prio has precedence), and set STP state 2274 * to Forwarding. 2275 * 2276 * If this is the CPU link, use DSA or EDSA tagging depending 2277 * on which tagging mode was configured. 2278 * 2279 * If this is a link to another switch, use DSA tagging mode. 2280 * 2281 * If this is the upstream port for this switch, enable 2282 * forwarding of unknown unicasts and multicasts. 2283 */ 2284 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2285 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2286 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2287 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2288 if (err) 2289 return err; 2290 2291 err = mv88e6xxx_setup_port_mode(chip, port); 2292 if (err) 2293 return err; 2294 2295 err = mv88e6xxx_setup_egress_floods(chip, port); 2296 if (err) 2297 return err; 2298 2299 /* Enable the SERDES interface for DSA and CPU ports. Normal 2300 * ports SERDES are enabled when the port is enabled, thus 2301 * saving a bit of power. 2302 */ 2303 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2304 err = mv88e6xxx_serdes_power(chip, port, true); 2305 if (err) 2306 return err; 2307 } 2308 2309 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2310 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2311 * untagged frames on this port, do a destination address lookup on all 2312 * received packets as usual, disable ARP mirroring and don't send a 2313 * copy of all transmitted/received frames on this port to the CPU. 2314 */ 2315 err = mv88e6xxx_port_set_map_da(chip, port); 2316 if (err) 2317 return err; 2318 2319 err = mv88e6xxx_setup_upstream_port(chip, port); 2320 if (err) 2321 return err; 2322 2323 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2324 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2325 if (err) 2326 return err; 2327 2328 if (chip->info->ops->port_set_jumbo_size) { 2329 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2330 if (err) 2331 return err; 2332 } 2333 2334 /* Port Association Vector: when learning source addresses 2335 * of packets, add the address to the address database using 2336 * a port bitmap that has only the bit for this port set and 2337 * the other bits clear. 2338 */ 2339 reg = 1 << port; 2340 /* Disable learning for CPU port */ 2341 if (dsa_is_cpu_port(ds, port)) 2342 reg = 0; 2343 2344 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2345 reg); 2346 if (err) 2347 return err; 2348 2349 /* Egress rate control 2: disable egress rate control. */ 2350 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2351 0x0000); 2352 if (err) 2353 return err; 2354 2355 if (chip->info->ops->port_pause_limit) { 2356 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2357 if (err) 2358 return err; 2359 } 2360 2361 if (chip->info->ops->port_disable_learn_limit) { 2362 err = chip->info->ops->port_disable_learn_limit(chip, port); 2363 if (err) 2364 return err; 2365 } 2366 2367 if (chip->info->ops->port_disable_pri_override) { 2368 err = chip->info->ops->port_disable_pri_override(chip, port); 2369 if (err) 2370 return err; 2371 } 2372 2373 if (chip->info->ops->port_tag_remap) { 2374 err = chip->info->ops->port_tag_remap(chip, port); 2375 if (err) 2376 return err; 2377 } 2378 2379 if (chip->info->ops->port_egress_rate_limiting) { 2380 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2381 if (err) 2382 return err; 2383 } 2384 2385 err = mv88e6xxx_setup_message_port(chip, port); 2386 if (err) 2387 return err; 2388 2389 /* Port based VLAN map: give each port the same default address 2390 * database, and allow bidirectional communication between the 2391 * CPU and DSA port(s), and the other ports. 2392 */ 2393 err = mv88e6xxx_port_set_fid(chip, port, 0); 2394 if (err) 2395 return err; 2396 2397 err = mv88e6xxx_port_vlan_map(chip, port); 2398 if (err) 2399 return err; 2400 2401 /* Default VLAN ID and priority: don't set a default VLAN 2402 * ID, and set the default packet priority to zero. 2403 */ 2404 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2405 } 2406 2407 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2408 struct phy_device *phydev) 2409 { 2410 struct mv88e6xxx_chip *chip = ds->priv; 2411 int err; 2412 2413 mutex_lock(&chip->reg_lock); 2414 2415 err = mv88e6xxx_serdes_power(chip, port, true); 2416 2417 if (!err && chip->info->ops->serdes_irq_setup) 2418 err = chip->info->ops->serdes_irq_setup(chip, port); 2419 2420 mutex_unlock(&chip->reg_lock); 2421 2422 return err; 2423 } 2424 2425 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2426 { 2427 struct mv88e6xxx_chip *chip = ds->priv; 2428 2429 mutex_lock(&chip->reg_lock); 2430 2431 if (chip->info->ops->serdes_irq_free) 2432 chip->info->ops->serdes_irq_free(chip, port); 2433 2434 if (mv88e6xxx_serdes_power(chip, port, false)) 2435 dev_err(chip->dev, "failed to power off SERDES\n"); 2436 2437 mutex_unlock(&chip->reg_lock); 2438 } 2439 2440 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2441 unsigned int ageing_time) 2442 { 2443 struct mv88e6xxx_chip *chip = ds->priv; 2444 int err; 2445 2446 mutex_lock(&chip->reg_lock); 2447 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2448 mutex_unlock(&chip->reg_lock); 2449 2450 return err; 2451 } 2452 2453 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2454 { 2455 int err; 2456 2457 /* Initialize the statistics unit */ 2458 if (chip->info->ops->stats_set_histogram) { 2459 err = chip->info->ops->stats_set_histogram(chip); 2460 if (err) 2461 return err; 2462 } 2463 2464 return mv88e6xxx_g1_stats_clear(chip); 2465 } 2466 2467 /* The mv88e6390 has some hidden registers used for debug and 2468 * development. The errata also makes use of them. 2469 */ 2470 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2471 int reg, u16 val) 2472 { 2473 u16 ctrl; 2474 int err; 2475 2476 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2477 PORT_RESERVED_1A, val); 2478 if (err) 2479 return err; 2480 2481 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2482 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2483 reg; 2484 2485 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2486 PORT_RESERVED_1A, ctrl); 2487 } 2488 2489 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2490 { 2491 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT, 2492 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY); 2493 } 2494 2495 2496 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2497 int reg, u16 *val) 2498 { 2499 u16 ctrl; 2500 int err; 2501 2502 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2503 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2504 reg; 2505 2506 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2507 PORT_RESERVED_1A, ctrl); 2508 if (err) 2509 return err; 2510 2511 err = mv88e6390_hidden_wait(chip); 2512 if (err) 2513 return err; 2514 2515 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2516 PORT_RESERVED_1A, val); 2517 } 2518 2519 /* Check if the errata has already been applied. */ 2520 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2521 { 2522 int port; 2523 int err; 2524 u16 val; 2525 2526 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2527 err = mv88e6390_hidden_read(chip, port, 0, &val); 2528 if (err) { 2529 dev_err(chip->dev, 2530 "Error reading hidden register: %d\n", err); 2531 return false; 2532 } 2533 if (val != 0x01c0) 2534 return false; 2535 } 2536 2537 return true; 2538 } 2539 2540 /* The 6390 copper ports have an errata which require poking magic 2541 * values into undocumented hidden registers and then performing a 2542 * software reset. 2543 */ 2544 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2545 { 2546 int port; 2547 int err; 2548 2549 if (mv88e6390_setup_errata_applied(chip)) 2550 return 0; 2551 2552 /* Set the ports into blocking mode */ 2553 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2554 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2555 if (err) 2556 return err; 2557 } 2558 2559 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2560 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2561 if (err) 2562 return err; 2563 } 2564 2565 return mv88e6xxx_software_reset(chip); 2566 } 2567 2568 static int mv88e6xxx_setup(struct dsa_switch *ds) 2569 { 2570 struct mv88e6xxx_chip *chip = ds->priv; 2571 u8 cmode; 2572 int err; 2573 int i; 2574 2575 chip->ds = ds; 2576 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2577 2578 mutex_lock(&chip->reg_lock); 2579 2580 if (chip->info->ops->setup_errata) { 2581 err = chip->info->ops->setup_errata(chip); 2582 if (err) 2583 goto unlock; 2584 } 2585 2586 /* Cache the cmode of each port. */ 2587 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2588 if (chip->info->ops->port_get_cmode) { 2589 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2590 if (err) 2591 goto unlock; 2592 2593 chip->ports[i].cmode = cmode; 2594 } 2595 } 2596 2597 /* Setup Switch Port Registers */ 2598 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2599 if (dsa_is_unused_port(ds, i)) 2600 continue; 2601 2602 err = mv88e6xxx_setup_port(chip, i); 2603 if (err) 2604 goto unlock; 2605 } 2606 2607 err = mv88e6xxx_irl_setup(chip); 2608 if (err) 2609 goto unlock; 2610 2611 err = mv88e6xxx_mac_setup(chip); 2612 if (err) 2613 goto unlock; 2614 2615 err = mv88e6xxx_phy_setup(chip); 2616 if (err) 2617 goto unlock; 2618 2619 err = mv88e6xxx_vtu_setup(chip); 2620 if (err) 2621 goto unlock; 2622 2623 err = mv88e6xxx_pvt_setup(chip); 2624 if (err) 2625 goto unlock; 2626 2627 err = mv88e6xxx_atu_setup(chip); 2628 if (err) 2629 goto unlock; 2630 2631 err = mv88e6xxx_broadcast_setup(chip, 0); 2632 if (err) 2633 goto unlock; 2634 2635 err = mv88e6xxx_pot_setup(chip); 2636 if (err) 2637 goto unlock; 2638 2639 err = mv88e6xxx_rmu_setup(chip); 2640 if (err) 2641 goto unlock; 2642 2643 err = mv88e6xxx_rsvd2cpu_setup(chip); 2644 if (err) 2645 goto unlock; 2646 2647 err = mv88e6xxx_trunk_setup(chip); 2648 if (err) 2649 goto unlock; 2650 2651 err = mv88e6xxx_devmap_setup(chip); 2652 if (err) 2653 goto unlock; 2654 2655 err = mv88e6xxx_pri_setup(chip); 2656 if (err) 2657 goto unlock; 2658 2659 /* Setup PTP Hardware Clock and timestamping */ 2660 if (chip->info->ptp_support) { 2661 err = mv88e6xxx_ptp_setup(chip); 2662 if (err) 2663 goto unlock; 2664 2665 err = mv88e6xxx_hwtstamp_setup(chip); 2666 if (err) 2667 goto unlock; 2668 } 2669 2670 err = mv88e6xxx_stats_setup(chip); 2671 if (err) 2672 goto unlock; 2673 2674 unlock: 2675 mutex_unlock(&chip->reg_lock); 2676 2677 return err; 2678 } 2679 2680 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2681 { 2682 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2683 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2684 u16 val; 2685 int err; 2686 2687 if (!chip->info->ops->phy_read) 2688 return -EOPNOTSUPP; 2689 2690 mutex_lock(&chip->reg_lock); 2691 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2692 mutex_unlock(&chip->reg_lock); 2693 2694 if (reg == MII_PHYSID2) { 2695 /* Some internal PHYs don't have a model number. */ 2696 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2697 /* Then there is the 6165 family. It gets is 2698 * PHYs correct. But it can also have two 2699 * SERDES interfaces in the PHY address 2700 * space. And these don't have a model 2701 * number. But they are not PHYs, so we don't 2702 * want to give them something a PHY driver 2703 * will recognise. 2704 * 2705 * Use the mv88e6390 family model number 2706 * instead, for anything which really could be 2707 * a PHY, 2708 */ 2709 if (!(val & 0x3f0)) 2710 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2711 } 2712 2713 return err ? err : val; 2714 } 2715 2716 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2717 { 2718 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2719 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2720 int err; 2721 2722 if (!chip->info->ops->phy_write) 2723 return -EOPNOTSUPP; 2724 2725 mutex_lock(&chip->reg_lock); 2726 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2727 mutex_unlock(&chip->reg_lock); 2728 2729 return err; 2730 } 2731 2732 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2733 struct device_node *np, 2734 bool external) 2735 { 2736 static int index; 2737 struct mv88e6xxx_mdio_bus *mdio_bus; 2738 struct mii_bus *bus; 2739 int err; 2740 2741 if (external) { 2742 mutex_lock(&chip->reg_lock); 2743 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2744 mutex_unlock(&chip->reg_lock); 2745 2746 if (err) 2747 return err; 2748 } 2749 2750 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2751 if (!bus) 2752 return -ENOMEM; 2753 2754 mdio_bus = bus->priv; 2755 mdio_bus->bus = bus; 2756 mdio_bus->chip = chip; 2757 INIT_LIST_HEAD(&mdio_bus->list); 2758 mdio_bus->external = external; 2759 2760 if (np) { 2761 bus->name = np->full_name; 2762 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2763 } else { 2764 bus->name = "mv88e6xxx SMI"; 2765 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2766 } 2767 2768 bus->read = mv88e6xxx_mdio_read; 2769 bus->write = mv88e6xxx_mdio_write; 2770 bus->parent = chip->dev; 2771 2772 if (!external) { 2773 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2774 if (err) 2775 return err; 2776 } 2777 2778 err = of_mdiobus_register(bus, np); 2779 if (err) { 2780 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2781 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2782 return err; 2783 } 2784 2785 if (external) 2786 list_add_tail(&mdio_bus->list, &chip->mdios); 2787 else 2788 list_add(&mdio_bus->list, &chip->mdios); 2789 2790 return 0; 2791 } 2792 2793 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2794 { .compatible = "marvell,mv88e6xxx-mdio-external", 2795 .data = (void *)true }, 2796 { }, 2797 }; 2798 2799 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2800 2801 { 2802 struct mv88e6xxx_mdio_bus *mdio_bus; 2803 struct mii_bus *bus; 2804 2805 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2806 bus = mdio_bus->bus; 2807 2808 if (!mdio_bus->external) 2809 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2810 2811 mdiobus_unregister(bus); 2812 } 2813 } 2814 2815 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2816 struct device_node *np) 2817 { 2818 const struct of_device_id *match; 2819 struct device_node *child; 2820 int err; 2821 2822 /* Always register one mdio bus for the internal/default mdio 2823 * bus. This maybe represented in the device tree, but is 2824 * optional. 2825 */ 2826 child = of_get_child_by_name(np, "mdio"); 2827 err = mv88e6xxx_mdio_register(chip, child, false); 2828 if (err) 2829 return err; 2830 2831 /* Walk the device tree, and see if there are any other nodes 2832 * which say they are compatible with the external mdio 2833 * bus. 2834 */ 2835 for_each_available_child_of_node(np, child) { 2836 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2837 if (match) { 2838 err = mv88e6xxx_mdio_register(chip, child, true); 2839 if (err) { 2840 mv88e6xxx_mdios_unregister(chip); 2841 return err; 2842 } 2843 } 2844 } 2845 2846 return 0; 2847 } 2848 2849 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2850 { 2851 struct mv88e6xxx_chip *chip = ds->priv; 2852 2853 return chip->eeprom_len; 2854 } 2855 2856 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2857 struct ethtool_eeprom *eeprom, u8 *data) 2858 { 2859 struct mv88e6xxx_chip *chip = ds->priv; 2860 int err; 2861 2862 if (!chip->info->ops->get_eeprom) 2863 return -EOPNOTSUPP; 2864 2865 mutex_lock(&chip->reg_lock); 2866 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2867 mutex_unlock(&chip->reg_lock); 2868 2869 if (err) 2870 return err; 2871 2872 eeprom->magic = 0xc3ec4951; 2873 2874 return 0; 2875 } 2876 2877 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2878 struct ethtool_eeprom *eeprom, u8 *data) 2879 { 2880 struct mv88e6xxx_chip *chip = ds->priv; 2881 int err; 2882 2883 if (!chip->info->ops->set_eeprom) 2884 return -EOPNOTSUPP; 2885 2886 if (eeprom->magic != 0xc3ec4951) 2887 return -EINVAL; 2888 2889 mutex_lock(&chip->reg_lock); 2890 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2891 mutex_unlock(&chip->reg_lock); 2892 2893 return err; 2894 } 2895 2896 static const struct mv88e6xxx_ops mv88e6085_ops = { 2897 /* MV88E6XXX_FAMILY_6097 */ 2898 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2899 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2900 .irl_init_all = mv88e6352_g2_irl_init_all, 2901 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2902 .phy_read = mv88e6185_phy_ppu_read, 2903 .phy_write = mv88e6185_phy_ppu_write, 2904 .port_set_link = mv88e6xxx_port_set_link, 2905 .port_set_duplex = mv88e6xxx_port_set_duplex, 2906 .port_set_speed = mv88e6185_port_set_speed, 2907 .port_tag_remap = mv88e6095_port_tag_remap, 2908 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2909 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2910 .port_set_ether_type = mv88e6351_port_set_ether_type, 2911 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2912 .port_pause_limit = mv88e6097_port_pause_limit, 2913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2915 .port_link_state = mv88e6352_port_link_state, 2916 .port_get_cmode = mv88e6185_port_get_cmode, 2917 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2918 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2919 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2920 .stats_get_strings = mv88e6095_stats_get_strings, 2921 .stats_get_stats = mv88e6095_stats_get_stats, 2922 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2923 .set_egress_port = mv88e6095_g1_set_egress_port, 2924 .watchdog_ops = &mv88e6097_watchdog_ops, 2925 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2926 .pot_clear = mv88e6xxx_g2_pot_clear, 2927 .ppu_enable = mv88e6185_g1_ppu_enable, 2928 .ppu_disable = mv88e6185_g1_ppu_disable, 2929 .reset = mv88e6185_g1_reset, 2930 .rmu_disable = mv88e6085_g1_rmu_disable, 2931 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2932 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2933 .phylink_validate = mv88e6185_phylink_validate, 2934 }; 2935 2936 static const struct mv88e6xxx_ops mv88e6095_ops = { 2937 /* MV88E6XXX_FAMILY_6095 */ 2938 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2939 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2940 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2941 .phy_read = mv88e6185_phy_ppu_read, 2942 .phy_write = mv88e6185_phy_ppu_write, 2943 .port_set_link = mv88e6xxx_port_set_link, 2944 .port_set_duplex = mv88e6xxx_port_set_duplex, 2945 .port_set_speed = mv88e6185_port_set_speed, 2946 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2947 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2948 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2949 .port_link_state = mv88e6185_port_link_state, 2950 .port_get_cmode = mv88e6185_port_get_cmode, 2951 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2952 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2953 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2954 .stats_get_strings = mv88e6095_stats_get_strings, 2955 .stats_get_stats = mv88e6095_stats_get_stats, 2956 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2957 .ppu_enable = mv88e6185_g1_ppu_enable, 2958 .ppu_disable = mv88e6185_g1_ppu_disable, 2959 .reset = mv88e6185_g1_reset, 2960 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2961 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2962 .phylink_validate = mv88e6185_phylink_validate, 2963 }; 2964 2965 static const struct mv88e6xxx_ops mv88e6097_ops = { 2966 /* MV88E6XXX_FAMILY_6097 */ 2967 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2968 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2969 .irl_init_all = mv88e6352_g2_irl_init_all, 2970 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2971 .phy_read = mv88e6xxx_g2_smi_phy_read, 2972 .phy_write = mv88e6xxx_g2_smi_phy_write, 2973 .port_set_link = mv88e6xxx_port_set_link, 2974 .port_set_duplex = mv88e6xxx_port_set_duplex, 2975 .port_set_speed = mv88e6185_port_set_speed, 2976 .port_tag_remap = mv88e6095_port_tag_remap, 2977 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2978 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2979 .port_set_ether_type = mv88e6351_port_set_ether_type, 2980 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2981 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2982 .port_pause_limit = mv88e6097_port_pause_limit, 2983 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2984 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2985 .port_link_state = mv88e6352_port_link_state, 2986 .port_get_cmode = mv88e6185_port_get_cmode, 2987 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2988 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2989 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2990 .stats_get_strings = mv88e6095_stats_get_strings, 2991 .stats_get_stats = mv88e6095_stats_get_stats, 2992 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2993 .set_egress_port = mv88e6095_g1_set_egress_port, 2994 .watchdog_ops = &mv88e6097_watchdog_ops, 2995 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2996 .pot_clear = mv88e6xxx_g2_pot_clear, 2997 .reset = mv88e6352_g1_reset, 2998 .rmu_disable = mv88e6085_g1_rmu_disable, 2999 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3000 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3001 .phylink_validate = mv88e6185_phylink_validate, 3002 }; 3003 3004 static const struct mv88e6xxx_ops mv88e6123_ops = { 3005 /* MV88E6XXX_FAMILY_6165 */ 3006 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3007 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3008 .irl_init_all = mv88e6352_g2_irl_init_all, 3009 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3010 .phy_read = mv88e6xxx_g2_smi_phy_read, 3011 .phy_write = mv88e6xxx_g2_smi_phy_write, 3012 .port_set_link = mv88e6xxx_port_set_link, 3013 .port_set_duplex = mv88e6xxx_port_set_duplex, 3014 .port_set_speed = mv88e6185_port_set_speed, 3015 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3016 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3017 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3018 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3019 .port_link_state = mv88e6352_port_link_state, 3020 .port_get_cmode = mv88e6185_port_get_cmode, 3021 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3022 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3023 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3024 .stats_get_strings = mv88e6095_stats_get_strings, 3025 .stats_get_stats = mv88e6095_stats_get_stats, 3026 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3027 .set_egress_port = mv88e6095_g1_set_egress_port, 3028 .watchdog_ops = &mv88e6097_watchdog_ops, 3029 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3030 .pot_clear = mv88e6xxx_g2_pot_clear, 3031 .reset = mv88e6352_g1_reset, 3032 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3033 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3034 .phylink_validate = mv88e6185_phylink_validate, 3035 }; 3036 3037 static const struct mv88e6xxx_ops mv88e6131_ops = { 3038 /* MV88E6XXX_FAMILY_6185 */ 3039 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3040 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3041 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3042 .phy_read = mv88e6185_phy_ppu_read, 3043 .phy_write = mv88e6185_phy_ppu_write, 3044 .port_set_link = mv88e6xxx_port_set_link, 3045 .port_set_duplex = mv88e6xxx_port_set_duplex, 3046 .port_set_speed = mv88e6185_port_set_speed, 3047 .port_tag_remap = mv88e6095_port_tag_remap, 3048 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3049 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3050 .port_set_ether_type = mv88e6351_port_set_ether_type, 3051 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3054 .port_pause_limit = mv88e6097_port_pause_limit, 3055 .port_set_pause = mv88e6185_port_set_pause, 3056 .port_link_state = mv88e6352_port_link_state, 3057 .port_get_cmode = mv88e6185_port_get_cmode, 3058 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3059 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3060 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3061 .stats_get_strings = mv88e6095_stats_get_strings, 3062 .stats_get_stats = mv88e6095_stats_get_stats, 3063 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3064 .set_egress_port = mv88e6095_g1_set_egress_port, 3065 .watchdog_ops = &mv88e6097_watchdog_ops, 3066 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3067 .ppu_enable = mv88e6185_g1_ppu_enable, 3068 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3069 .ppu_disable = mv88e6185_g1_ppu_disable, 3070 .reset = mv88e6185_g1_reset, 3071 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3072 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3073 .phylink_validate = mv88e6185_phylink_validate, 3074 }; 3075 3076 static const struct mv88e6xxx_ops mv88e6141_ops = { 3077 /* MV88E6XXX_FAMILY_6341 */ 3078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3079 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3080 .irl_init_all = mv88e6352_g2_irl_init_all, 3081 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3082 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3083 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3084 .phy_read = mv88e6xxx_g2_smi_phy_read, 3085 .phy_write = mv88e6xxx_g2_smi_phy_write, 3086 .port_set_link = mv88e6xxx_port_set_link, 3087 .port_set_duplex = mv88e6xxx_port_set_duplex, 3088 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3089 .port_set_speed = mv88e6341_port_set_speed, 3090 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3091 .port_tag_remap = mv88e6095_port_tag_remap, 3092 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3093 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3094 .port_set_ether_type = mv88e6351_port_set_ether_type, 3095 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3096 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3097 .port_pause_limit = mv88e6097_port_pause_limit, 3098 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3099 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3100 .port_link_state = mv88e6352_port_link_state, 3101 .port_get_cmode = mv88e6352_port_get_cmode, 3102 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3103 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3104 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3105 .stats_get_strings = mv88e6320_stats_get_strings, 3106 .stats_get_stats = mv88e6390_stats_get_stats, 3107 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3108 .set_egress_port = mv88e6390_g1_set_egress_port, 3109 .watchdog_ops = &mv88e6390_watchdog_ops, 3110 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3111 .pot_clear = mv88e6xxx_g2_pot_clear, 3112 .reset = mv88e6352_g1_reset, 3113 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3114 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3115 .serdes_power = mv88e6341_serdes_power, 3116 .gpio_ops = &mv88e6352_gpio_ops, 3117 .phylink_validate = mv88e6341_phylink_validate, 3118 }; 3119 3120 static const struct mv88e6xxx_ops mv88e6161_ops = { 3121 /* MV88E6XXX_FAMILY_6165 */ 3122 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3123 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3124 .irl_init_all = mv88e6352_g2_irl_init_all, 3125 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3126 .phy_read = mv88e6xxx_g2_smi_phy_read, 3127 .phy_write = mv88e6xxx_g2_smi_phy_write, 3128 .port_set_link = mv88e6xxx_port_set_link, 3129 .port_set_duplex = mv88e6xxx_port_set_duplex, 3130 .port_set_speed = mv88e6185_port_set_speed, 3131 .port_tag_remap = mv88e6095_port_tag_remap, 3132 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3133 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3134 .port_set_ether_type = mv88e6351_port_set_ether_type, 3135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3136 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3137 .port_pause_limit = mv88e6097_port_pause_limit, 3138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3140 .port_link_state = mv88e6352_port_link_state, 3141 .port_get_cmode = mv88e6185_port_get_cmode, 3142 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3143 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3144 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3145 .stats_get_strings = mv88e6095_stats_get_strings, 3146 .stats_get_stats = mv88e6095_stats_get_stats, 3147 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3148 .set_egress_port = mv88e6095_g1_set_egress_port, 3149 .watchdog_ops = &mv88e6097_watchdog_ops, 3150 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3151 .pot_clear = mv88e6xxx_g2_pot_clear, 3152 .reset = mv88e6352_g1_reset, 3153 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3154 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3155 .avb_ops = &mv88e6165_avb_ops, 3156 .ptp_ops = &mv88e6165_ptp_ops, 3157 .phylink_validate = mv88e6185_phylink_validate, 3158 }; 3159 3160 static const struct mv88e6xxx_ops mv88e6165_ops = { 3161 /* MV88E6XXX_FAMILY_6165 */ 3162 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3163 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3164 .irl_init_all = mv88e6352_g2_irl_init_all, 3165 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3166 .phy_read = mv88e6165_phy_read, 3167 .phy_write = mv88e6165_phy_write, 3168 .port_set_link = mv88e6xxx_port_set_link, 3169 .port_set_duplex = mv88e6xxx_port_set_duplex, 3170 .port_set_speed = mv88e6185_port_set_speed, 3171 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3172 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3173 .port_link_state = mv88e6352_port_link_state, 3174 .port_get_cmode = mv88e6185_port_get_cmode, 3175 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3176 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3177 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3178 .stats_get_strings = mv88e6095_stats_get_strings, 3179 .stats_get_stats = mv88e6095_stats_get_stats, 3180 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3181 .set_egress_port = mv88e6095_g1_set_egress_port, 3182 .watchdog_ops = &mv88e6097_watchdog_ops, 3183 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3184 .pot_clear = mv88e6xxx_g2_pot_clear, 3185 .reset = mv88e6352_g1_reset, 3186 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3187 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3188 .avb_ops = &mv88e6165_avb_ops, 3189 .ptp_ops = &mv88e6165_ptp_ops, 3190 .phylink_validate = mv88e6185_phylink_validate, 3191 }; 3192 3193 static const struct mv88e6xxx_ops mv88e6171_ops = { 3194 /* MV88E6XXX_FAMILY_6351 */ 3195 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3196 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3197 .irl_init_all = mv88e6352_g2_irl_init_all, 3198 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3199 .phy_read = mv88e6xxx_g2_smi_phy_read, 3200 .phy_write = mv88e6xxx_g2_smi_phy_write, 3201 .port_set_link = mv88e6xxx_port_set_link, 3202 .port_set_duplex = mv88e6xxx_port_set_duplex, 3203 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3204 .port_set_speed = mv88e6185_port_set_speed, 3205 .port_tag_remap = mv88e6095_port_tag_remap, 3206 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3207 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3208 .port_set_ether_type = mv88e6351_port_set_ether_type, 3209 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3210 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3211 .port_pause_limit = mv88e6097_port_pause_limit, 3212 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3213 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3214 .port_link_state = mv88e6352_port_link_state, 3215 .port_get_cmode = mv88e6352_port_get_cmode, 3216 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3217 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3218 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3219 .stats_get_strings = mv88e6095_stats_get_strings, 3220 .stats_get_stats = mv88e6095_stats_get_stats, 3221 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3222 .set_egress_port = mv88e6095_g1_set_egress_port, 3223 .watchdog_ops = &mv88e6097_watchdog_ops, 3224 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3225 .pot_clear = mv88e6xxx_g2_pot_clear, 3226 .reset = mv88e6352_g1_reset, 3227 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3228 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3229 .phylink_validate = mv88e6185_phylink_validate, 3230 }; 3231 3232 static const struct mv88e6xxx_ops mv88e6172_ops = { 3233 /* MV88E6XXX_FAMILY_6352 */ 3234 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3235 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3236 .irl_init_all = mv88e6352_g2_irl_init_all, 3237 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3238 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3240 .phy_read = mv88e6xxx_g2_smi_phy_read, 3241 .phy_write = mv88e6xxx_g2_smi_phy_write, 3242 .port_set_link = mv88e6xxx_port_set_link, 3243 .port_set_duplex = mv88e6xxx_port_set_duplex, 3244 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3245 .port_set_speed = mv88e6352_port_set_speed, 3246 .port_tag_remap = mv88e6095_port_tag_remap, 3247 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3248 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3249 .port_set_ether_type = mv88e6351_port_set_ether_type, 3250 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3251 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3252 .port_pause_limit = mv88e6097_port_pause_limit, 3253 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3254 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3255 .port_link_state = mv88e6352_port_link_state, 3256 .port_get_cmode = mv88e6352_port_get_cmode, 3257 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3258 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3259 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3260 .stats_get_strings = mv88e6095_stats_get_strings, 3261 .stats_get_stats = mv88e6095_stats_get_stats, 3262 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3263 .set_egress_port = mv88e6095_g1_set_egress_port, 3264 .watchdog_ops = &mv88e6097_watchdog_ops, 3265 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3266 .pot_clear = mv88e6xxx_g2_pot_clear, 3267 .reset = mv88e6352_g1_reset, 3268 .rmu_disable = mv88e6352_g1_rmu_disable, 3269 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3270 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3271 .serdes_power = mv88e6352_serdes_power, 3272 .gpio_ops = &mv88e6352_gpio_ops, 3273 .phylink_validate = mv88e6352_phylink_validate, 3274 }; 3275 3276 static const struct mv88e6xxx_ops mv88e6175_ops = { 3277 /* MV88E6XXX_FAMILY_6351 */ 3278 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3279 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3280 .irl_init_all = mv88e6352_g2_irl_init_all, 3281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3282 .phy_read = mv88e6xxx_g2_smi_phy_read, 3283 .phy_write = mv88e6xxx_g2_smi_phy_write, 3284 .port_set_link = mv88e6xxx_port_set_link, 3285 .port_set_duplex = mv88e6xxx_port_set_duplex, 3286 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3287 .port_set_speed = mv88e6185_port_set_speed, 3288 .port_tag_remap = mv88e6095_port_tag_remap, 3289 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3290 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3291 .port_set_ether_type = mv88e6351_port_set_ether_type, 3292 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3293 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3294 .port_pause_limit = mv88e6097_port_pause_limit, 3295 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3296 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3297 .port_link_state = mv88e6352_port_link_state, 3298 .port_get_cmode = mv88e6352_port_get_cmode, 3299 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3300 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3301 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3302 .stats_get_strings = mv88e6095_stats_get_strings, 3303 .stats_get_stats = mv88e6095_stats_get_stats, 3304 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3305 .set_egress_port = mv88e6095_g1_set_egress_port, 3306 .watchdog_ops = &mv88e6097_watchdog_ops, 3307 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3308 .pot_clear = mv88e6xxx_g2_pot_clear, 3309 .reset = mv88e6352_g1_reset, 3310 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3311 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3312 .phylink_validate = mv88e6185_phylink_validate, 3313 }; 3314 3315 static const struct mv88e6xxx_ops mv88e6176_ops = { 3316 /* MV88E6XXX_FAMILY_6352 */ 3317 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3318 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3319 .irl_init_all = mv88e6352_g2_irl_init_all, 3320 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3321 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3322 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3323 .phy_read = mv88e6xxx_g2_smi_phy_read, 3324 .phy_write = mv88e6xxx_g2_smi_phy_write, 3325 .port_set_link = mv88e6xxx_port_set_link, 3326 .port_set_duplex = mv88e6xxx_port_set_duplex, 3327 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3328 .port_set_speed = mv88e6352_port_set_speed, 3329 .port_tag_remap = mv88e6095_port_tag_remap, 3330 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3331 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3332 .port_set_ether_type = mv88e6351_port_set_ether_type, 3333 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3334 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3335 .port_pause_limit = mv88e6097_port_pause_limit, 3336 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3337 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3338 .port_link_state = mv88e6352_port_link_state, 3339 .port_get_cmode = mv88e6352_port_get_cmode, 3340 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3341 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3342 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3343 .stats_get_strings = mv88e6095_stats_get_strings, 3344 .stats_get_stats = mv88e6095_stats_get_stats, 3345 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3346 .set_egress_port = mv88e6095_g1_set_egress_port, 3347 .watchdog_ops = &mv88e6097_watchdog_ops, 3348 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3349 .pot_clear = mv88e6xxx_g2_pot_clear, 3350 .reset = mv88e6352_g1_reset, 3351 .rmu_disable = mv88e6352_g1_rmu_disable, 3352 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3353 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3354 .serdes_power = mv88e6352_serdes_power, 3355 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3356 .serdes_irq_free = mv88e6352_serdes_irq_free, 3357 .gpio_ops = &mv88e6352_gpio_ops, 3358 .phylink_validate = mv88e6352_phylink_validate, 3359 }; 3360 3361 static const struct mv88e6xxx_ops mv88e6185_ops = { 3362 /* MV88E6XXX_FAMILY_6185 */ 3363 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3364 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3365 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3366 .phy_read = mv88e6185_phy_ppu_read, 3367 .phy_write = mv88e6185_phy_ppu_write, 3368 .port_set_link = mv88e6xxx_port_set_link, 3369 .port_set_duplex = mv88e6xxx_port_set_duplex, 3370 .port_set_speed = mv88e6185_port_set_speed, 3371 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3372 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3373 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3374 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3375 .port_set_pause = mv88e6185_port_set_pause, 3376 .port_link_state = mv88e6185_port_link_state, 3377 .port_get_cmode = mv88e6185_port_get_cmode, 3378 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3379 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3380 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3381 .stats_get_strings = mv88e6095_stats_get_strings, 3382 .stats_get_stats = mv88e6095_stats_get_stats, 3383 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3384 .set_egress_port = mv88e6095_g1_set_egress_port, 3385 .watchdog_ops = &mv88e6097_watchdog_ops, 3386 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3387 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3388 .ppu_enable = mv88e6185_g1_ppu_enable, 3389 .ppu_disable = mv88e6185_g1_ppu_disable, 3390 .reset = mv88e6185_g1_reset, 3391 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3392 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3393 .phylink_validate = mv88e6185_phylink_validate, 3394 }; 3395 3396 static const struct mv88e6xxx_ops mv88e6190_ops = { 3397 /* MV88E6XXX_FAMILY_6390 */ 3398 .setup_errata = mv88e6390_setup_errata, 3399 .irl_init_all = mv88e6390_g2_irl_init_all, 3400 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3401 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3402 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3403 .phy_read = mv88e6xxx_g2_smi_phy_read, 3404 .phy_write = mv88e6xxx_g2_smi_phy_write, 3405 .port_set_link = mv88e6xxx_port_set_link, 3406 .port_set_duplex = mv88e6xxx_port_set_duplex, 3407 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3408 .port_set_speed = mv88e6390_port_set_speed, 3409 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3410 .port_tag_remap = mv88e6390_port_tag_remap, 3411 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3412 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3413 .port_set_ether_type = mv88e6351_port_set_ether_type, 3414 .port_pause_limit = mv88e6390_port_pause_limit, 3415 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3416 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3417 .port_link_state = mv88e6352_port_link_state, 3418 .port_get_cmode = mv88e6352_port_get_cmode, 3419 .port_set_cmode = mv88e6390_port_set_cmode, 3420 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3421 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3422 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3423 .stats_get_strings = mv88e6320_stats_get_strings, 3424 .stats_get_stats = mv88e6390_stats_get_stats, 3425 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3426 .set_egress_port = mv88e6390_g1_set_egress_port, 3427 .watchdog_ops = &mv88e6390_watchdog_ops, 3428 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3429 .pot_clear = mv88e6xxx_g2_pot_clear, 3430 .reset = mv88e6352_g1_reset, 3431 .rmu_disable = mv88e6390_g1_rmu_disable, 3432 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3433 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3434 .serdes_power = mv88e6390_serdes_power, 3435 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3436 .serdes_irq_free = mv88e6390_serdes_irq_free, 3437 .gpio_ops = &mv88e6352_gpio_ops, 3438 .phylink_validate = mv88e6390_phylink_validate, 3439 }; 3440 3441 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3442 /* MV88E6XXX_FAMILY_6390 */ 3443 .setup_errata = mv88e6390_setup_errata, 3444 .irl_init_all = mv88e6390_g2_irl_init_all, 3445 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3446 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3447 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3448 .phy_read = mv88e6xxx_g2_smi_phy_read, 3449 .phy_write = mv88e6xxx_g2_smi_phy_write, 3450 .port_set_link = mv88e6xxx_port_set_link, 3451 .port_set_duplex = mv88e6xxx_port_set_duplex, 3452 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3453 .port_set_speed = mv88e6390x_port_set_speed, 3454 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3455 .port_tag_remap = mv88e6390_port_tag_remap, 3456 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3457 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3458 .port_set_ether_type = mv88e6351_port_set_ether_type, 3459 .port_pause_limit = mv88e6390_port_pause_limit, 3460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3462 .port_link_state = mv88e6352_port_link_state, 3463 .port_get_cmode = mv88e6352_port_get_cmode, 3464 .port_set_cmode = mv88e6390x_port_set_cmode, 3465 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3466 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3467 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3468 .stats_get_strings = mv88e6320_stats_get_strings, 3469 .stats_get_stats = mv88e6390_stats_get_stats, 3470 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3471 .set_egress_port = mv88e6390_g1_set_egress_port, 3472 .watchdog_ops = &mv88e6390_watchdog_ops, 3473 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3474 .pot_clear = mv88e6xxx_g2_pot_clear, 3475 .reset = mv88e6352_g1_reset, 3476 .rmu_disable = mv88e6390_g1_rmu_disable, 3477 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3478 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3479 .serdes_power = mv88e6390x_serdes_power, 3480 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3481 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3482 .gpio_ops = &mv88e6352_gpio_ops, 3483 .phylink_validate = mv88e6390x_phylink_validate, 3484 }; 3485 3486 static const struct mv88e6xxx_ops mv88e6191_ops = { 3487 /* MV88E6XXX_FAMILY_6390 */ 3488 .setup_errata = mv88e6390_setup_errata, 3489 .irl_init_all = mv88e6390_g2_irl_init_all, 3490 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3491 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3492 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3493 .phy_read = mv88e6xxx_g2_smi_phy_read, 3494 .phy_write = mv88e6xxx_g2_smi_phy_write, 3495 .port_set_link = mv88e6xxx_port_set_link, 3496 .port_set_duplex = mv88e6xxx_port_set_duplex, 3497 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3498 .port_set_speed = mv88e6390_port_set_speed, 3499 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3500 .port_tag_remap = mv88e6390_port_tag_remap, 3501 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3502 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3503 .port_set_ether_type = mv88e6351_port_set_ether_type, 3504 .port_pause_limit = mv88e6390_port_pause_limit, 3505 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3506 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3507 .port_link_state = mv88e6352_port_link_state, 3508 .port_get_cmode = mv88e6352_port_get_cmode, 3509 .port_set_cmode = mv88e6390_port_set_cmode, 3510 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3511 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3512 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3513 .stats_get_strings = mv88e6320_stats_get_strings, 3514 .stats_get_stats = mv88e6390_stats_get_stats, 3515 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3516 .set_egress_port = mv88e6390_g1_set_egress_port, 3517 .watchdog_ops = &mv88e6390_watchdog_ops, 3518 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3519 .pot_clear = mv88e6xxx_g2_pot_clear, 3520 .reset = mv88e6352_g1_reset, 3521 .rmu_disable = mv88e6390_g1_rmu_disable, 3522 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3523 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3524 .serdes_power = mv88e6390_serdes_power, 3525 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3526 .serdes_irq_free = mv88e6390_serdes_irq_free, 3527 .avb_ops = &mv88e6390_avb_ops, 3528 .ptp_ops = &mv88e6352_ptp_ops, 3529 .phylink_validate = mv88e6390_phylink_validate, 3530 }; 3531 3532 static const struct mv88e6xxx_ops mv88e6240_ops = { 3533 /* MV88E6XXX_FAMILY_6352 */ 3534 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3535 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3536 .irl_init_all = mv88e6352_g2_irl_init_all, 3537 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3538 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3540 .phy_read = mv88e6xxx_g2_smi_phy_read, 3541 .phy_write = mv88e6xxx_g2_smi_phy_write, 3542 .port_set_link = mv88e6xxx_port_set_link, 3543 .port_set_duplex = mv88e6xxx_port_set_duplex, 3544 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3545 .port_set_speed = mv88e6352_port_set_speed, 3546 .port_tag_remap = mv88e6095_port_tag_remap, 3547 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3548 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3549 .port_set_ether_type = mv88e6351_port_set_ether_type, 3550 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3552 .port_pause_limit = mv88e6097_port_pause_limit, 3553 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3554 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3555 .port_link_state = mv88e6352_port_link_state, 3556 .port_get_cmode = mv88e6352_port_get_cmode, 3557 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3558 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3559 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3560 .stats_get_strings = mv88e6095_stats_get_strings, 3561 .stats_get_stats = mv88e6095_stats_get_stats, 3562 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3563 .set_egress_port = mv88e6095_g1_set_egress_port, 3564 .watchdog_ops = &mv88e6097_watchdog_ops, 3565 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3566 .pot_clear = mv88e6xxx_g2_pot_clear, 3567 .reset = mv88e6352_g1_reset, 3568 .rmu_disable = mv88e6352_g1_rmu_disable, 3569 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3570 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3571 .serdes_power = mv88e6352_serdes_power, 3572 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3573 .serdes_irq_free = mv88e6352_serdes_irq_free, 3574 .gpio_ops = &mv88e6352_gpio_ops, 3575 .avb_ops = &mv88e6352_avb_ops, 3576 .ptp_ops = &mv88e6352_ptp_ops, 3577 .phylink_validate = mv88e6352_phylink_validate, 3578 }; 3579 3580 static const struct mv88e6xxx_ops mv88e6290_ops = { 3581 /* MV88E6XXX_FAMILY_6390 */ 3582 .setup_errata = mv88e6390_setup_errata, 3583 .irl_init_all = mv88e6390_g2_irl_init_all, 3584 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3585 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3587 .phy_read = mv88e6xxx_g2_smi_phy_read, 3588 .phy_write = mv88e6xxx_g2_smi_phy_write, 3589 .port_set_link = mv88e6xxx_port_set_link, 3590 .port_set_duplex = mv88e6xxx_port_set_duplex, 3591 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3592 .port_set_speed = mv88e6390_port_set_speed, 3593 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3594 .port_tag_remap = mv88e6390_port_tag_remap, 3595 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3596 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3597 .port_set_ether_type = mv88e6351_port_set_ether_type, 3598 .port_pause_limit = mv88e6390_port_pause_limit, 3599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3601 .port_link_state = mv88e6352_port_link_state, 3602 .port_get_cmode = mv88e6352_port_get_cmode, 3603 .port_set_cmode = mv88e6390_port_set_cmode, 3604 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3605 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3606 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3607 .stats_get_strings = mv88e6320_stats_get_strings, 3608 .stats_get_stats = mv88e6390_stats_get_stats, 3609 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3610 .set_egress_port = mv88e6390_g1_set_egress_port, 3611 .watchdog_ops = &mv88e6390_watchdog_ops, 3612 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3613 .pot_clear = mv88e6xxx_g2_pot_clear, 3614 .reset = mv88e6352_g1_reset, 3615 .rmu_disable = mv88e6390_g1_rmu_disable, 3616 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3617 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3618 .serdes_power = mv88e6390_serdes_power, 3619 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3620 .serdes_irq_free = mv88e6390_serdes_irq_free, 3621 .gpio_ops = &mv88e6352_gpio_ops, 3622 .avb_ops = &mv88e6390_avb_ops, 3623 .ptp_ops = &mv88e6352_ptp_ops, 3624 .phylink_validate = mv88e6390_phylink_validate, 3625 }; 3626 3627 static const struct mv88e6xxx_ops mv88e6320_ops = { 3628 /* MV88E6XXX_FAMILY_6320 */ 3629 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3630 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3631 .irl_init_all = mv88e6352_g2_irl_init_all, 3632 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3633 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3634 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3635 .phy_read = mv88e6xxx_g2_smi_phy_read, 3636 .phy_write = mv88e6xxx_g2_smi_phy_write, 3637 .port_set_link = mv88e6xxx_port_set_link, 3638 .port_set_duplex = mv88e6xxx_port_set_duplex, 3639 .port_set_speed = mv88e6185_port_set_speed, 3640 .port_tag_remap = mv88e6095_port_tag_remap, 3641 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3642 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3643 .port_set_ether_type = mv88e6351_port_set_ether_type, 3644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3646 .port_pause_limit = mv88e6097_port_pause_limit, 3647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3649 .port_link_state = mv88e6352_port_link_state, 3650 .port_get_cmode = mv88e6352_port_get_cmode, 3651 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3652 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3653 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3654 .stats_get_strings = mv88e6320_stats_get_strings, 3655 .stats_get_stats = mv88e6320_stats_get_stats, 3656 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3657 .set_egress_port = mv88e6095_g1_set_egress_port, 3658 .watchdog_ops = &mv88e6390_watchdog_ops, 3659 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3660 .pot_clear = mv88e6xxx_g2_pot_clear, 3661 .reset = mv88e6352_g1_reset, 3662 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3663 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3664 .gpio_ops = &mv88e6352_gpio_ops, 3665 .avb_ops = &mv88e6352_avb_ops, 3666 .ptp_ops = &mv88e6352_ptp_ops, 3667 .phylink_validate = mv88e6185_phylink_validate, 3668 }; 3669 3670 static const struct mv88e6xxx_ops mv88e6321_ops = { 3671 /* MV88E6XXX_FAMILY_6320 */ 3672 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3673 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3674 .irl_init_all = mv88e6352_g2_irl_init_all, 3675 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3676 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3677 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3678 .phy_read = mv88e6xxx_g2_smi_phy_read, 3679 .phy_write = mv88e6xxx_g2_smi_phy_write, 3680 .port_set_link = mv88e6xxx_port_set_link, 3681 .port_set_duplex = mv88e6xxx_port_set_duplex, 3682 .port_set_speed = mv88e6185_port_set_speed, 3683 .port_tag_remap = mv88e6095_port_tag_remap, 3684 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3685 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3686 .port_set_ether_type = mv88e6351_port_set_ether_type, 3687 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3688 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3689 .port_pause_limit = mv88e6097_port_pause_limit, 3690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3692 .port_link_state = mv88e6352_port_link_state, 3693 .port_get_cmode = mv88e6352_port_get_cmode, 3694 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3695 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3696 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3697 .stats_get_strings = mv88e6320_stats_get_strings, 3698 .stats_get_stats = mv88e6320_stats_get_stats, 3699 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3700 .set_egress_port = mv88e6095_g1_set_egress_port, 3701 .watchdog_ops = &mv88e6390_watchdog_ops, 3702 .reset = mv88e6352_g1_reset, 3703 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3704 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3705 .gpio_ops = &mv88e6352_gpio_ops, 3706 .avb_ops = &mv88e6352_avb_ops, 3707 .ptp_ops = &mv88e6352_ptp_ops, 3708 .phylink_validate = mv88e6185_phylink_validate, 3709 }; 3710 3711 static const struct mv88e6xxx_ops mv88e6341_ops = { 3712 /* MV88E6XXX_FAMILY_6341 */ 3713 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3714 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3715 .irl_init_all = mv88e6352_g2_irl_init_all, 3716 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3717 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3718 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3719 .phy_read = mv88e6xxx_g2_smi_phy_read, 3720 .phy_write = mv88e6xxx_g2_smi_phy_write, 3721 .port_set_link = mv88e6xxx_port_set_link, 3722 .port_set_duplex = mv88e6xxx_port_set_duplex, 3723 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3724 .port_set_speed = mv88e6341_port_set_speed, 3725 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3726 .port_tag_remap = mv88e6095_port_tag_remap, 3727 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3728 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3729 .port_set_ether_type = mv88e6351_port_set_ether_type, 3730 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3731 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3732 .port_pause_limit = mv88e6097_port_pause_limit, 3733 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3734 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3735 .port_link_state = mv88e6352_port_link_state, 3736 .port_get_cmode = mv88e6352_port_get_cmode, 3737 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3738 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3739 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3740 .stats_get_strings = mv88e6320_stats_get_strings, 3741 .stats_get_stats = mv88e6390_stats_get_stats, 3742 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3743 .set_egress_port = mv88e6390_g1_set_egress_port, 3744 .watchdog_ops = &mv88e6390_watchdog_ops, 3745 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3746 .pot_clear = mv88e6xxx_g2_pot_clear, 3747 .reset = mv88e6352_g1_reset, 3748 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3749 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3750 .serdes_power = mv88e6341_serdes_power, 3751 .gpio_ops = &mv88e6352_gpio_ops, 3752 .avb_ops = &mv88e6390_avb_ops, 3753 .ptp_ops = &mv88e6352_ptp_ops, 3754 .phylink_validate = mv88e6341_phylink_validate, 3755 }; 3756 3757 static const struct mv88e6xxx_ops mv88e6350_ops = { 3758 /* MV88E6XXX_FAMILY_6351 */ 3759 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3760 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3761 .irl_init_all = mv88e6352_g2_irl_init_all, 3762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3763 .phy_read = mv88e6xxx_g2_smi_phy_read, 3764 .phy_write = mv88e6xxx_g2_smi_phy_write, 3765 .port_set_link = mv88e6xxx_port_set_link, 3766 .port_set_duplex = mv88e6xxx_port_set_duplex, 3767 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3768 .port_set_speed = mv88e6185_port_set_speed, 3769 .port_tag_remap = mv88e6095_port_tag_remap, 3770 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3771 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3772 .port_set_ether_type = mv88e6351_port_set_ether_type, 3773 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3774 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3775 .port_pause_limit = mv88e6097_port_pause_limit, 3776 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3777 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3778 .port_link_state = mv88e6352_port_link_state, 3779 .port_get_cmode = mv88e6352_port_get_cmode, 3780 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3781 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3782 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3783 .stats_get_strings = mv88e6095_stats_get_strings, 3784 .stats_get_stats = mv88e6095_stats_get_stats, 3785 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3786 .set_egress_port = mv88e6095_g1_set_egress_port, 3787 .watchdog_ops = &mv88e6097_watchdog_ops, 3788 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3789 .pot_clear = mv88e6xxx_g2_pot_clear, 3790 .reset = mv88e6352_g1_reset, 3791 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3792 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3793 .phylink_validate = mv88e6185_phylink_validate, 3794 }; 3795 3796 static const struct mv88e6xxx_ops mv88e6351_ops = { 3797 /* MV88E6XXX_FAMILY_6351 */ 3798 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3799 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3800 .irl_init_all = mv88e6352_g2_irl_init_all, 3801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3802 .phy_read = mv88e6xxx_g2_smi_phy_read, 3803 .phy_write = mv88e6xxx_g2_smi_phy_write, 3804 .port_set_link = mv88e6xxx_port_set_link, 3805 .port_set_duplex = mv88e6xxx_port_set_duplex, 3806 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3807 .port_set_speed = mv88e6185_port_set_speed, 3808 .port_tag_remap = mv88e6095_port_tag_remap, 3809 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3810 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3811 .port_set_ether_type = mv88e6351_port_set_ether_type, 3812 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3813 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3814 .port_pause_limit = mv88e6097_port_pause_limit, 3815 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3816 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3817 .port_link_state = mv88e6352_port_link_state, 3818 .port_get_cmode = mv88e6352_port_get_cmode, 3819 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3820 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3821 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3822 .stats_get_strings = mv88e6095_stats_get_strings, 3823 .stats_get_stats = mv88e6095_stats_get_stats, 3824 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3825 .set_egress_port = mv88e6095_g1_set_egress_port, 3826 .watchdog_ops = &mv88e6097_watchdog_ops, 3827 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3828 .pot_clear = mv88e6xxx_g2_pot_clear, 3829 .reset = mv88e6352_g1_reset, 3830 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3831 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3832 .avb_ops = &mv88e6352_avb_ops, 3833 .ptp_ops = &mv88e6352_ptp_ops, 3834 .phylink_validate = mv88e6185_phylink_validate, 3835 }; 3836 3837 static const struct mv88e6xxx_ops mv88e6352_ops = { 3838 /* MV88E6XXX_FAMILY_6352 */ 3839 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3840 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3841 .irl_init_all = mv88e6352_g2_irl_init_all, 3842 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3843 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3844 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3845 .phy_read = mv88e6xxx_g2_smi_phy_read, 3846 .phy_write = mv88e6xxx_g2_smi_phy_write, 3847 .port_set_link = mv88e6xxx_port_set_link, 3848 .port_set_duplex = mv88e6xxx_port_set_duplex, 3849 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3850 .port_set_speed = mv88e6352_port_set_speed, 3851 .port_tag_remap = mv88e6095_port_tag_remap, 3852 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3853 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3854 .port_set_ether_type = mv88e6351_port_set_ether_type, 3855 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3856 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3857 .port_pause_limit = mv88e6097_port_pause_limit, 3858 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3859 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3860 .port_link_state = mv88e6352_port_link_state, 3861 .port_get_cmode = mv88e6352_port_get_cmode, 3862 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3863 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3864 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3865 .stats_get_strings = mv88e6095_stats_get_strings, 3866 .stats_get_stats = mv88e6095_stats_get_stats, 3867 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3868 .set_egress_port = mv88e6095_g1_set_egress_port, 3869 .watchdog_ops = &mv88e6097_watchdog_ops, 3870 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3871 .pot_clear = mv88e6xxx_g2_pot_clear, 3872 .reset = mv88e6352_g1_reset, 3873 .rmu_disable = mv88e6352_g1_rmu_disable, 3874 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3875 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3876 .serdes_power = mv88e6352_serdes_power, 3877 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3878 .serdes_irq_free = mv88e6352_serdes_irq_free, 3879 .gpio_ops = &mv88e6352_gpio_ops, 3880 .avb_ops = &mv88e6352_avb_ops, 3881 .ptp_ops = &mv88e6352_ptp_ops, 3882 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3883 .serdes_get_strings = mv88e6352_serdes_get_strings, 3884 .serdes_get_stats = mv88e6352_serdes_get_stats, 3885 .phylink_validate = mv88e6352_phylink_validate, 3886 }; 3887 3888 static const struct mv88e6xxx_ops mv88e6390_ops = { 3889 /* MV88E6XXX_FAMILY_6390 */ 3890 .setup_errata = mv88e6390_setup_errata, 3891 .irl_init_all = mv88e6390_g2_irl_init_all, 3892 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3893 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3895 .phy_read = mv88e6xxx_g2_smi_phy_read, 3896 .phy_write = mv88e6xxx_g2_smi_phy_write, 3897 .port_set_link = mv88e6xxx_port_set_link, 3898 .port_set_duplex = mv88e6xxx_port_set_duplex, 3899 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3900 .port_set_speed = mv88e6390_port_set_speed, 3901 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3902 .port_tag_remap = mv88e6390_port_tag_remap, 3903 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3904 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3905 .port_set_ether_type = mv88e6351_port_set_ether_type, 3906 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3907 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3908 .port_pause_limit = mv88e6390_port_pause_limit, 3909 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3910 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3911 .port_link_state = mv88e6352_port_link_state, 3912 .port_get_cmode = mv88e6352_port_get_cmode, 3913 .port_set_cmode = mv88e6390_port_set_cmode, 3914 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3915 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3916 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3917 .stats_get_strings = mv88e6320_stats_get_strings, 3918 .stats_get_stats = mv88e6390_stats_get_stats, 3919 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3920 .set_egress_port = mv88e6390_g1_set_egress_port, 3921 .watchdog_ops = &mv88e6390_watchdog_ops, 3922 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3923 .pot_clear = mv88e6xxx_g2_pot_clear, 3924 .reset = mv88e6352_g1_reset, 3925 .rmu_disable = mv88e6390_g1_rmu_disable, 3926 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3927 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3928 .serdes_power = mv88e6390_serdes_power, 3929 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3930 .serdes_irq_free = mv88e6390_serdes_irq_free, 3931 .gpio_ops = &mv88e6352_gpio_ops, 3932 .avb_ops = &mv88e6390_avb_ops, 3933 .ptp_ops = &mv88e6352_ptp_ops, 3934 .phylink_validate = mv88e6390_phylink_validate, 3935 }; 3936 3937 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3938 /* MV88E6XXX_FAMILY_6390 */ 3939 .setup_errata = mv88e6390_setup_errata, 3940 .irl_init_all = mv88e6390_g2_irl_init_all, 3941 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3942 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3943 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3944 .phy_read = mv88e6xxx_g2_smi_phy_read, 3945 .phy_write = mv88e6xxx_g2_smi_phy_write, 3946 .port_set_link = mv88e6xxx_port_set_link, 3947 .port_set_duplex = mv88e6xxx_port_set_duplex, 3948 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3949 .port_set_speed = mv88e6390x_port_set_speed, 3950 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3951 .port_tag_remap = mv88e6390_port_tag_remap, 3952 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3953 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3954 .port_set_ether_type = mv88e6351_port_set_ether_type, 3955 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3956 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3957 .port_pause_limit = mv88e6390_port_pause_limit, 3958 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3959 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3960 .port_link_state = mv88e6352_port_link_state, 3961 .port_get_cmode = mv88e6352_port_get_cmode, 3962 .port_set_cmode = mv88e6390x_port_set_cmode, 3963 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3964 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3965 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3966 .stats_get_strings = mv88e6320_stats_get_strings, 3967 .stats_get_stats = mv88e6390_stats_get_stats, 3968 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3969 .set_egress_port = mv88e6390_g1_set_egress_port, 3970 .watchdog_ops = &mv88e6390_watchdog_ops, 3971 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3972 .pot_clear = mv88e6xxx_g2_pot_clear, 3973 .reset = mv88e6352_g1_reset, 3974 .rmu_disable = mv88e6390_g1_rmu_disable, 3975 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3976 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3977 .serdes_power = mv88e6390x_serdes_power, 3978 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3979 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3980 .gpio_ops = &mv88e6352_gpio_ops, 3981 .avb_ops = &mv88e6390_avb_ops, 3982 .ptp_ops = &mv88e6352_ptp_ops, 3983 .phylink_validate = mv88e6390x_phylink_validate, 3984 }; 3985 3986 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3987 [MV88E6085] = { 3988 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3989 .family = MV88E6XXX_FAMILY_6097, 3990 .name = "Marvell 88E6085", 3991 .num_databases = 4096, 3992 .num_ports = 10, 3993 .num_internal_phys = 5, 3994 .max_vid = 4095, 3995 .port_base_addr = 0x10, 3996 .phy_base_addr = 0x0, 3997 .global1_addr = 0x1b, 3998 .global2_addr = 0x1c, 3999 .age_time_coeff = 15000, 4000 .g1_irqs = 8, 4001 .g2_irqs = 10, 4002 .atu_move_port_mask = 0xf, 4003 .pvt = true, 4004 .multi_chip = true, 4005 .tag_protocol = DSA_TAG_PROTO_DSA, 4006 .ops = &mv88e6085_ops, 4007 }, 4008 4009 [MV88E6095] = { 4010 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4011 .family = MV88E6XXX_FAMILY_6095, 4012 .name = "Marvell 88E6095/88E6095F", 4013 .num_databases = 256, 4014 .num_ports = 11, 4015 .num_internal_phys = 0, 4016 .max_vid = 4095, 4017 .port_base_addr = 0x10, 4018 .phy_base_addr = 0x0, 4019 .global1_addr = 0x1b, 4020 .global2_addr = 0x1c, 4021 .age_time_coeff = 15000, 4022 .g1_irqs = 8, 4023 .atu_move_port_mask = 0xf, 4024 .multi_chip = true, 4025 .tag_protocol = DSA_TAG_PROTO_DSA, 4026 .ops = &mv88e6095_ops, 4027 }, 4028 4029 [MV88E6097] = { 4030 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4031 .family = MV88E6XXX_FAMILY_6097, 4032 .name = "Marvell 88E6097/88E6097F", 4033 .num_databases = 4096, 4034 .num_ports = 11, 4035 .num_internal_phys = 8, 4036 .max_vid = 4095, 4037 .port_base_addr = 0x10, 4038 .phy_base_addr = 0x0, 4039 .global1_addr = 0x1b, 4040 .global2_addr = 0x1c, 4041 .age_time_coeff = 15000, 4042 .g1_irqs = 8, 4043 .g2_irqs = 10, 4044 .atu_move_port_mask = 0xf, 4045 .pvt = true, 4046 .multi_chip = true, 4047 .tag_protocol = DSA_TAG_PROTO_EDSA, 4048 .ops = &mv88e6097_ops, 4049 }, 4050 4051 [MV88E6123] = { 4052 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4053 .family = MV88E6XXX_FAMILY_6165, 4054 .name = "Marvell 88E6123", 4055 .num_databases = 4096, 4056 .num_ports = 3, 4057 .num_internal_phys = 5, 4058 .max_vid = 4095, 4059 .port_base_addr = 0x10, 4060 .phy_base_addr = 0x0, 4061 .global1_addr = 0x1b, 4062 .global2_addr = 0x1c, 4063 .age_time_coeff = 15000, 4064 .g1_irqs = 9, 4065 .g2_irqs = 10, 4066 .atu_move_port_mask = 0xf, 4067 .pvt = true, 4068 .multi_chip = true, 4069 .tag_protocol = DSA_TAG_PROTO_EDSA, 4070 .ops = &mv88e6123_ops, 4071 }, 4072 4073 [MV88E6131] = { 4074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4075 .family = MV88E6XXX_FAMILY_6185, 4076 .name = "Marvell 88E6131", 4077 .num_databases = 256, 4078 .num_ports = 8, 4079 .num_internal_phys = 0, 4080 .max_vid = 4095, 4081 .port_base_addr = 0x10, 4082 .phy_base_addr = 0x0, 4083 .global1_addr = 0x1b, 4084 .global2_addr = 0x1c, 4085 .age_time_coeff = 15000, 4086 .g1_irqs = 9, 4087 .atu_move_port_mask = 0xf, 4088 .multi_chip = true, 4089 .tag_protocol = DSA_TAG_PROTO_DSA, 4090 .ops = &mv88e6131_ops, 4091 }, 4092 4093 [MV88E6141] = { 4094 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4095 .family = MV88E6XXX_FAMILY_6341, 4096 .name = "Marvell 88E6141", 4097 .num_databases = 4096, 4098 .num_ports = 6, 4099 .num_internal_phys = 5, 4100 .num_gpio = 11, 4101 .max_vid = 4095, 4102 .port_base_addr = 0x10, 4103 .phy_base_addr = 0x10, 4104 .global1_addr = 0x1b, 4105 .global2_addr = 0x1c, 4106 .age_time_coeff = 3750, 4107 .atu_move_port_mask = 0x1f, 4108 .g1_irqs = 9, 4109 .g2_irqs = 10, 4110 .pvt = true, 4111 .multi_chip = true, 4112 .tag_protocol = DSA_TAG_PROTO_EDSA, 4113 .ops = &mv88e6141_ops, 4114 }, 4115 4116 [MV88E6161] = { 4117 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4118 .family = MV88E6XXX_FAMILY_6165, 4119 .name = "Marvell 88E6161", 4120 .num_databases = 4096, 4121 .num_ports = 6, 4122 .num_internal_phys = 5, 4123 .max_vid = 4095, 4124 .port_base_addr = 0x10, 4125 .phy_base_addr = 0x0, 4126 .global1_addr = 0x1b, 4127 .global2_addr = 0x1c, 4128 .age_time_coeff = 15000, 4129 .g1_irqs = 9, 4130 .g2_irqs = 10, 4131 .atu_move_port_mask = 0xf, 4132 .pvt = true, 4133 .multi_chip = true, 4134 .tag_protocol = DSA_TAG_PROTO_EDSA, 4135 .ptp_support = true, 4136 .ops = &mv88e6161_ops, 4137 }, 4138 4139 [MV88E6165] = { 4140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4141 .family = MV88E6XXX_FAMILY_6165, 4142 .name = "Marvell 88E6165", 4143 .num_databases = 4096, 4144 .num_ports = 6, 4145 .num_internal_phys = 0, 4146 .max_vid = 4095, 4147 .port_base_addr = 0x10, 4148 .phy_base_addr = 0x0, 4149 .global1_addr = 0x1b, 4150 .global2_addr = 0x1c, 4151 .age_time_coeff = 15000, 4152 .g1_irqs = 9, 4153 .g2_irqs = 10, 4154 .atu_move_port_mask = 0xf, 4155 .pvt = true, 4156 .multi_chip = true, 4157 .tag_protocol = DSA_TAG_PROTO_DSA, 4158 .ptp_support = true, 4159 .ops = &mv88e6165_ops, 4160 }, 4161 4162 [MV88E6171] = { 4163 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4164 .family = MV88E6XXX_FAMILY_6351, 4165 .name = "Marvell 88E6171", 4166 .num_databases = 4096, 4167 .num_ports = 7, 4168 .num_internal_phys = 5, 4169 .max_vid = 4095, 4170 .port_base_addr = 0x10, 4171 .phy_base_addr = 0x0, 4172 .global1_addr = 0x1b, 4173 .global2_addr = 0x1c, 4174 .age_time_coeff = 15000, 4175 .g1_irqs = 9, 4176 .g2_irqs = 10, 4177 .atu_move_port_mask = 0xf, 4178 .pvt = true, 4179 .multi_chip = true, 4180 .tag_protocol = DSA_TAG_PROTO_EDSA, 4181 .ops = &mv88e6171_ops, 4182 }, 4183 4184 [MV88E6172] = { 4185 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4186 .family = MV88E6XXX_FAMILY_6352, 4187 .name = "Marvell 88E6172", 4188 .num_databases = 4096, 4189 .num_ports = 7, 4190 .num_internal_phys = 5, 4191 .num_gpio = 15, 4192 .max_vid = 4095, 4193 .port_base_addr = 0x10, 4194 .phy_base_addr = 0x0, 4195 .global1_addr = 0x1b, 4196 .global2_addr = 0x1c, 4197 .age_time_coeff = 15000, 4198 .g1_irqs = 9, 4199 .g2_irqs = 10, 4200 .atu_move_port_mask = 0xf, 4201 .pvt = true, 4202 .multi_chip = true, 4203 .tag_protocol = DSA_TAG_PROTO_EDSA, 4204 .ops = &mv88e6172_ops, 4205 }, 4206 4207 [MV88E6175] = { 4208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4209 .family = MV88E6XXX_FAMILY_6351, 4210 .name = "Marvell 88E6175", 4211 .num_databases = 4096, 4212 .num_ports = 7, 4213 .num_internal_phys = 5, 4214 .max_vid = 4095, 4215 .port_base_addr = 0x10, 4216 .phy_base_addr = 0x0, 4217 .global1_addr = 0x1b, 4218 .global2_addr = 0x1c, 4219 .age_time_coeff = 15000, 4220 .g1_irqs = 9, 4221 .g2_irqs = 10, 4222 .atu_move_port_mask = 0xf, 4223 .pvt = true, 4224 .multi_chip = true, 4225 .tag_protocol = DSA_TAG_PROTO_EDSA, 4226 .ops = &mv88e6175_ops, 4227 }, 4228 4229 [MV88E6176] = { 4230 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4231 .family = MV88E6XXX_FAMILY_6352, 4232 .name = "Marvell 88E6176", 4233 .num_databases = 4096, 4234 .num_ports = 7, 4235 .num_internal_phys = 5, 4236 .num_gpio = 15, 4237 .max_vid = 4095, 4238 .port_base_addr = 0x10, 4239 .phy_base_addr = 0x0, 4240 .global1_addr = 0x1b, 4241 .global2_addr = 0x1c, 4242 .age_time_coeff = 15000, 4243 .g1_irqs = 9, 4244 .g2_irqs = 10, 4245 .atu_move_port_mask = 0xf, 4246 .pvt = true, 4247 .multi_chip = true, 4248 .tag_protocol = DSA_TAG_PROTO_EDSA, 4249 .ops = &mv88e6176_ops, 4250 }, 4251 4252 [MV88E6185] = { 4253 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4254 .family = MV88E6XXX_FAMILY_6185, 4255 .name = "Marvell 88E6185", 4256 .num_databases = 256, 4257 .num_ports = 10, 4258 .num_internal_phys = 0, 4259 .max_vid = 4095, 4260 .port_base_addr = 0x10, 4261 .phy_base_addr = 0x0, 4262 .global1_addr = 0x1b, 4263 .global2_addr = 0x1c, 4264 .age_time_coeff = 15000, 4265 .g1_irqs = 8, 4266 .atu_move_port_mask = 0xf, 4267 .multi_chip = true, 4268 .tag_protocol = DSA_TAG_PROTO_EDSA, 4269 .ops = &mv88e6185_ops, 4270 }, 4271 4272 [MV88E6190] = { 4273 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4274 .family = MV88E6XXX_FAMILY_6390, 4275 .name = "Marvell 88E6190", 4276 .num_databases = 4096, 4277 .num_ports = 11, /* 10 + Z80 */ 4278 .num_internal_phys = 9, 4279 .num_gpio = 16, 4280 .max_vid = 8191, 4281 .port_base_addr = 0x0, 4282 .phy_base_addr = 0x0, 4283 .global1_addr = 0x1b, 4284 .global2_addr = 0x1c, 4285 .tag_protocol = DSA_TAG_PROTO_DSA, 4286 .age_time_coeff = 3750, 4287 .g1_irqs = 9, 4288 .g2_irqs = 14, 4289 .pvt = true, 4290 .multi_chip = true, 4291 .atu_move_port_mask = 0x1f, 4292 .ops = &mv88e6190_ops, 4293 }, 4294 4295 [MV88E6190X] = { 4296 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4297 .family = MV88E6XXX_FAMILY_6390, 4298 .name = "Marvell 88E6190X", 4299 .num_databases = 4096, 4300 .num_ports = 11, /* 10 + Z80 */ 4301 .num_internal_phys = 9, 4302 .num_gpio = 16, 4303 .max_vid = 8191, 4304 .port_base_addr = 0x0, 4305 .phy_base_addr = 0x0, 4306 .global1_addr = 0x1b, 4307 .global2_addr = 0x1c, 4308 .age_time_coeff = 3750, 4309 .g1_irqs = 9, 4310 .g2_irqs = 14, 4311 .atu_move_port_mask = 0x1f, 4312 .pvt = true, 4313 .multi_chip = true, 4314 .tag_protocol = DSA_TAG_PROTO_DSA, 4315 .ops = &mv88e6190x_ops, 4316 }, 4317 4318 [MV88E6191] = { 4319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4320 .family = MV88E6XXX_FAMILY_6390, 4321 .name = "Marvell 88E6191", 4322 .num_databases = 4096, 4323 .num_ports = 11, /* 10 + Z80 */ 4324 .num_internal_phys = 9, 4325 .max_vid = 8191, 4326 .port_base_addr = 0x0, 4327 .phy_base_addr = 0x0, 4328 .global1_addr = 0x1b, 4329 .global2_addr = 0x1c, 4330 .age_time_coeff = 3750, 4331 .g1_irqs = 9, 4332 .g2_irqs = 14, 4333 .atu_move_port_mask = 0x1f, 4334 .pvt = true, 4335 .multi_chip = true, 4336 .tag_protocol = DSA_TAG_PROTO_DSA, 4337 .ptp_support = true, 4338 .ops = &mv88e6191_ops, 4339 }, 4340 4341 [MV88E6240] = { 4342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4343 .family = MV88E6XXX_FAMILY_6352, 4344 .name = "Marvell 88E6240", 4345 .num_databases = 4096, 4346 .num_ports = 7, 4347 .num_internal_phys = 5, 4348 .num_gpio = 15, 4349 .max_vid = 4095, 4350 .port_base_addr = 0x10, 4351 .phy_base_addr = 0x0, 4352 .global1_addr = 0x1b, 4353 .global2_addr = 0x1c, 4354 .age_time_coeff = 15000, 4355 .g1_irqs = 9, 4356 .g2_irqs = 10, 4357 .atu_move_port_mask = 0xf, 4358 .pvt = true, 4359 .multi_chip = true, 4360 .tag_protocol = DSA_TAG_PROTO_EDSA, 4361 .ptp_support = true, 4362 .ops = &mv88e6240_ops, 4363 }, 4364 4365 [MV88E6290] = { 4366 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4367 .family = MV88E6XXX_FAMILY_6390, 4368 .name = "Marvell 88E6290", 4369 .num_databases = 4096, 4370 .num_ports = 11, /* 10 + Z80 */ 4371 .num_internal_phys = 9, 4372 .num_gpio = 16, 4373 .max_vid = 8191, 4374 .port_base_addr = 0x0, 4375 .phy_base_addr = 0x0, 4376 .global1_addr = 0x1b, 4377 .global2_addr = 0x1c, 4378 .age_time_coeff = 3750, 4379 .g1_irqs = 9, 4380 .g2_irqs = 14, 4381 .atu_move_port_mask = 0x1f, 4382 .pvt = true, 4383 .multi_chip = true, 4384 .tag_protocol = DSA_TAG_PROTO_DSA, 4385 .ptp_support = true, 4386 .ops = &mv88e6290_ops, 4387 }, 4388 4389 [MV88E6320] = { 4390 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4391 .family = MV88E6XXX_FAMILY_6320, 4392 .name = "Marvell 88E6320", 4393 .num_databases = 4096, 4394 .num_ports = 7, 4395 .num_internal_phys = 5, 4396 .num_gpio = 15, 4397 .max_vid = 4095, 4398 .port_base_addr = 0x10, 4399 .phy_base_addr = 0x0, 4400 .global1_addr = 0x1b, 4401 .global2_addr = 0x1c, 4402 .age_time_coeff = 15000, 4403 .g1_irqs = 8, 4404 .g2_irqs = 10, 4405 .atu_move_port_mask = 0xf, 4406 .pvt = true, 4407 .multi_chip = true, 4408 .tag_protocol = DSA_TAG_PROTO_EDSA, 4409 .ptp_support = true, 4410 .ops = &mv88e6320_ops, 4411 }, 4412 4413 [MV88E6321] = { 4414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4415 .family = MV88E6XXX_FAMILY_6320, 4416 .name = "Marvell 88E6321", 4417 .num_databases = 4096, 4418 .num_ports = 7, 4419 .num_internal_phys = 5, 4420 .num_gpio = 15, 4421 .max_vid = 4095, 4422 .port_base_addr = 0x10, 4423 .phy_base_addr = 0x0, 4424 .global1_addr = 0x1b, 4425 .global2_addr = 0x1c, 4426 .age_time_coeff = 15000, 4427 .g1_irqs = 8, 4428 .g2_irqs = 10, 4429 .atu_move_port_mask = 0xf, 4430 .multi_chip = true, 4431 .tag_protocol = DSA_TAG_PROTO_EDSA, 4432 .ptp_support = true, 4433 .ops = &mv88e6321_ops, 4434 }, 4435 4436 [MV88E6341] = { 4437 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4438 .family = MV88E6XXX_FAMILY_6341, 4439 .name = "Marvell 88E6341", 4440 .num_databases = 4096, 4441 .num_internal_phys = 5, 4442 .num_ports = 6, 4443 .num_gpio = 11, 4444 .max_vid = 4095, 4445 .port_base_addr = 0x10, 4446 .phy_base_addr = 0x10, 4447 .global1_addr = 0x1b, 4448 .global2_addr = 0x1c, 4449 .age_time_coeff = 3750, 4450 .atu_move_port_mask = 0x1f, 4451 .g1_irqs = 9, 4452 .g2_irqs = 10, 4453 .pvt = true, 4454 .multi_chip = true, 4455 .tag_protocol = DSA_TAG_PROTO_EDSA, 4456 .ptp_support = true, 4457 .ops = &mv88e6341_ops, 4458 }, 4459 4460 [MV88E6350] = { 4461 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4462 .family = MV88E6XXX_FAMILY_6351, 4463 .name = "Marvell 88E6350", 4464 .num_databases = 4096, 4465 .num_ports = 7, 4466 .num_internal_phys = 5, 4467 .max_vid = 4095, 4468 .port_base_addr = 0x10, 4469 .phy_base_addr = 0x0, 4470 .global1_addr = 0x1b, 4471 .global2_addr = 0x1c, 4472 .age_time_coeff = 15000, 4473 .g1_irqs = 9, 4474 .g2_irqs = 10, 4475 .atu_move_port_mask = 0xf, 4476 .pvt = true, 4477 .multi_chip = true, 4478 .tag_protocol = DSA_TAG_PROTO_EDSA, 4479 .ops = &mv88e6350_ops, 4480 }, 4481 4482 [MV88E6351] = { 4483 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4484 .family = MV88E6XXX_FAMILY_6351, 4485 .name = "Marvell 88E6351", 4486 .num_databases = 4096, 4487 .num_ports = 7, 4488 .num_internal_phys = 5, 4489 .max_vid = 4095, 4490 .port_base_addr = 0x10, 4491 .phy_base_addr = 0x0, 4492 .global1_addr = 0x1b, 4493 .global2_addr = 0x1c, 4494 .age_time_coeff = 15000, 4495 .g1_irqs = 9, 4496 .g2_irqs = 10, 4497 .atu_move_port_mask = 0xf, 4498 .pvt = true, 4499 .multi_chip = true, 4500 .tag_protocol = DSA_TAG_PROTO_EDSA, 4501 .ops = &mv88e6351_ops, 4502 }, 4503 4504 [MV88E6352] = { 4505 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4506 .family = MV88E6XXX_FAMILY_6352, 4507 .name = "Marvell 88E6352", 4508 .num_databases = 4096, 4509 .num_ports = 7, 4510 .num_internal_phys = 5, 4511 .num_gpio = 15, 4512 .max_vid = 4095, 4513 .port_base_addr = 0x10, 4514 .phy_base_addr = 0x0, 4515 .global1_addr = 0x1b, 4516 .global2_addr = 0x1c, 4517 .age_time_coeff = 15000, 4518 .g1_irqs = 9, 4519 .g2_irqs = 10, 4520 .atu_move_port_mask = 0xf, 4521 .pvt = true, 4522 .multi_chip = true, 4523 .tag_protocol = DSA_TAG_PROTO_EDSA, 4524 .ptp_support = true, 4525 .ops = &mv88e6352_ops, 4526 }, 4527 [MV88E6390] = { 4528 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4529 .family = MV88E6XXX_FAMILY_6390, 4530 .name = "Marvell 88E6390", 4531 .num_databases = 4096, 4532 .num_ports = 11, /* 10 + Z80 */ 4533 .num_internal_phys = 9, 4534 .num_gpio = 16, 4535 .max_vid = 8191, 4536 .port_base_addr = 0x0, 4537 .phy_base_addr = 0x0, 4538 .global1_addr = 0x1b, 4539 .global2_addr = 0x1c, 4540 .age_time_coeff = 3750, 4541 .g1_irqs = 9, 4542 .g2_irqs = 14, 4543 .atu_move_port_mask = 0x1f, 4544 .pvt = true, 4545 .multi_chip = true, 4546 .tag_protocol = DSA_TAG_PROTO_DSA, 4547 .ptp_support = true, 4548 .ops = &mv88e6390_ops, 4549 }, 4550 [MV88E6390X] = { 4551 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4552 .family = MV88E6XXX_FAMILY_6390, 4553 .name = "Marvell 88E6390X", 4554 .num_databases = 4096, 4555 .num_ports = 11, /* 10 + Z80 */ 4556 .num_internal_phys = 9, 4557 .num_gpio = 16, 4558 .max_vid = 8191, 4559 .port_base_addr = 0x0, 4560 .phy_base_addr = 0x0, 4561 .global1_addr = 0x1b, 4562 .global2_addr = 0x1c, 4563 .age_time_coeff = 3750, 4564 .g1_irqs = 9, 4565 .g2_irqs = 14, 4566 .atu_move_port_mask = 0x1f, 4567 .pvt = true, 4568 .multi_chip = true, 4569 .tag_protocol = DSA_TAG_PROTO_DSA, 4570 .ptp_support = true, 4571 .ops = &mv88e6390x_ops, 4572 }, 4573 }; 4574 4575 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4576 { 4577 int i; 4578 4579 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4580 if (mv88e6xxx_table[i].prod_num == prod_num) 4581 return &mv88e6xxx_table[i]; 4582 4583 return NULL; 4584 } 4585 4586 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4587 { 4588 const struct mv88e6xxx_info *info; 4589 unsigned int prod_num, rev; 4590 u16 id; 4591 int err; 4592 4593 mutex_lock(&chip->reg_lock); 4594 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4595 mutex_unlock(&chip->reg_lock); 4596 if (err) 4597 return err; 4598 4599 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4600 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4601 4602 info = mv88e6xxx_lookup_info(prod_num); 4603 if (!info) 4604 return -ENODEV; 4605 4606 /* Update the compatible info with the probed one */ 4607 chip->info = info; 4608 4609 err = mv88e6xxx_g2_require(chip); 4610 if (err) 4611 return err; 4612 4613 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4614 chip->info->prod_num, chip->info->name, rev); 4615 4616 return 0; 4617 } 4618 4619 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4620 { 4621 struct mv88e6xxx_chip *chip; 4622 4623 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4624 if (!chip) 4625 return NULL; 4626 4627 chip->dev = dev; 4628 4629 mutex_init(&chip->reg_lock); 4630 INIT_LIST_HEAD(&chip->mdios); 4631 4632 return chip; 4633 } 4634 4635 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4636 struct mii_bus *bus, int sw_addr) 4637 { 4638 if (sw_addr == 0) 4639 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4640 else if (chip->info->multi_chip) 4641 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4642 else 4643 return -EINVAL; 4644 4645 chip->bus = bus; 4646 chip->sw_addr = sw_addr; 4647 4648 return 0; 4649 } 4650 4651 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4652 int port) 4653 { 4654 struct mv88e6xxx_chip *chip = ds->priv; 4655 4656 return chip->info->tag_protocol; 4657 } 4658 4659 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4660 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4661 struct device *host_dev, int sw_addr, 4662 void **priv) 4663 { 4664 struct mv88e6xxx_chip *chip; 4665 struct mii_bus *bus; 4666 int err; 4667 4668 bus = dsa_host_dev_to_mii_bus(host_dev); 4669 if (!bus) 4670 return NULL; 4671 4672 chip = mv88e6xxx_alloc_chip(dsa_dev); 4673 if (!chip) 4674 return NULL; 4675 4676 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4677 chip->info = &mv88e6xxx_table[MV88E6085]; 4678 4679 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4680 if (err) 4681 goto free; 4682 4683 err = mv88e6xxx_detect(chip); 4684 if (err) 4685 goto free; 4686 4687 mutex_lock(&chip->reg_lock); 4688 err = mv88e6xxx_switch_reset(chip); 4689 mutex_unlock(&chip->reg_lock); 4690 if (err) 4691 goto free; 4692 4693 mv88e6xxx_phy_init(chip); 4694 4695 err = mv88e6xxx_mdios_register(chip, NULL); 4696 if (err) 4697 goto free; 4698 4699 *priv = chip; 4700 4701 return chip->info->name; 4702 free: 4703 devm_kfree(dsa_dev, chip); 4704 4705 return NULL; 4706 } 4707 #endif 4708 4709 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4710 const struct switchdev_obj_port_mdb *mdb) 4711 { 4712 /* We don't need any dynamic resource from the kernel (yet), 4713 * so skip the prepare phase. 4714 */ 4715 4716 return 0; 4717 } 4718 4719 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4720 const struct switchdev_obj_port_mdb *mdb) 4721 { 4722 struct mv88e6xxx_chip *chip = ds->priv; 4723 4724 mutex_lock(&chip->reg_lock); 4725 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4726 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4727 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4728 port); 4729 mutex_unlock(&chip->reg_lock); 4730 } 4731 4732 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4733 const struct switchdev_obj_port_mdb *mdb) 4734 { 4735 struct mv88e6xxx_chip *chip = ds->priv; 4736 int err; 4737 4738 mutex_lock(&chip->reg_lock); 4739 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4740 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4741 mutex_unlock(&chip->reg_lock); 4742 4743 return err; 4744 } 4745 4746 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4747 bool unicast, bool multicast) 4748 { 4749 struct mv88e6xxx_chip *chip = ds->priv; 4750 int err = -EOPNOTSUPP; 4751 4752 mutex_lock(&chip->reg_lock); 4753 if (chip->info->ops->port_set_egress_floods) 4754 err = chip->info->ops->port_set_egress_floods(chip, port, 4755 unicast, 4756 multicast); 4757 mutex_unlock(&chip->reg_lock); 4758 4759 return err; 4760 } 4761 4762 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4763 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4764 .probe = mv88e6xxx_drv_probe, 4765 #endif 4766 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4767 .setup = mv88e6xxx_setup, 4768 .adjust_link = mv88e6xxx_adjust_link, 4769 .phylink_validate = mv88e6xxx_validate, 4770 .phylink_mac_link_state = mv88e6xxx_link_state, 4771 .phylink_mac_config = mv88e6xxx_mac_config, 4772 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4773 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4774 .get_strings = mv88e6xxx_get_strings, 4775 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4776 .get_sset_count = mv88e6xxx_get_sset_count, 4777 .port_enable = mv88e6xxx_port_enable, 4778 .port_disable = mv88e6xxx_port_disable, 4779 .get_mac_eee = mv88e6xxx_get_mac_eee, 4780 .set_mac_eee = mv88e6xxx_set_mac_eee, 4781 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4782 .get_eeprom = mv88e6xxx_get_eeprom, 4783 .set_eeprom = mv88e6xxx_set_eeprom, 4784 .get_regs_len = mv88e6xxx_get_regs_len, 4785 .get_regs = mv88e6xxx_get_regs, 4786 .set_ageing_time = mv88e6xxx_set_ageing_time, 4787 .port_bridge_join = mv88e6xxx_port_bridge_join, 4788 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4789 .port_egress_floods = mv88e6xxx_port_egress_floods, 4790 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4791 .port_fast_age = mv88e6xxx_port_fast_age, 4792 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4793 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4794 .port_vlan_add = mv88e6xxx_port_vlan_add, 4795 .port_vlan_del = mv88e6xxx_port_vlan_del, 4796 .port_fdb_add = mv88e6xxx_port_fdb_add, 4797 .port_fdb_del = mv88e6xxx_port_fdb_del, 4798 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4799 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4800 .port_mdb_add = mv88e6xxx_port_mdb_add, 4801 .port_mdb_del = mv88e6xxx_port_mdb_del, 4802 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4803 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4804 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4805 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4806 .port_txtstamp = mv88e6xxx_port_txtstamp, 4807 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4808 .get_ts_info = mv88e6xxx_get_ts_info, 4809 }; 4810 4811 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4812 .ops = &mv88e6xxx_switch_ops, 4813 }; 4814 4815 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4816 { 4817 struct device *dev = chip->dev; 4818 struct dsa_switch *ds; 4819 4820 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4821 if (!ds) 4822 return -ENOMEM; 4823 4824 ds->priv = chip; 4825 ds->dev = dev; 4826 ds->ops = &mv88e6xxx_switch_ops; 4827 ds->ageing_time_min = chip->info->age_time_coeff; 4828 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4829 4830 dev_set_drvdata(dev, ds); 4831 4832 return dsa_register_switch(ds); 4833 } 4834 4835 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4836 { 4837 dsa_unregister_switch(chip->ds); 4838 } 4839 4840 static const void *pdata_device_get_match_data(struct device *dev) 4841 { 4842 const struct of_device_id *matches = dev->driver->of_match_table; 4843 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4844 4845 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4846 matches++) { 4847 if (!strcmp(pdata->compatible, matches->compatible)) 4848 return matches->data; 4849 } 4850 return NULL; 4851 } 4852 4853 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4854 * would be lost after a power cycle so prevent it to be suspended. 4855 */ 4856 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4857 { 4858 return -EOPNOTSUPP; 4859 } 4860 4861 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4862 { 4863 return 0; 4864 } 4865 4866 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4867 4868 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4869 { 4870 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4871 const struct mv88e6xxx_info *compat_info = NULL; 4872 struct device *dev = &mdiodev->dev; 4873 struct device_node *np = dev->of_node; 4874 struct mv88e6xxx_chip *chip; 4875 int port; 4876 int err; 4877 4878 if (!np && !pdata) 4879 return -EINVAL; 4880 4881 if (np) 4882 compat_info = of_device_get_match_data(dev); 4883 4884 if (pdata) { 4885 compat_info = pdata_device_get_match_data(dev); 4886 4887 if (!pdata->netdev) 4888 return -EINVAL; 4889 4890 for (port = 0; port < DSA_MAX_PORTS; port++) { 4891 if (!(pdata->enabled_ports & (1 << port))) 4892 continue; 4893 if (strcmp(pdata->cd.port_names[port], "cpu")) 4894 continue; 4895 pdata->cd.netdev[port] = &pdata->netdev->dev; 4896 break; 4897 } 4898 } 4899 4900 if (!compat_info) 4901 return -EINVAL; 4902 4903 chip = mv88e6xxx_alloc_chip(dev); 4904 if (!chip) { 4905 err = -ENOMEM; 4906 goto out; 4907 } 4908 4909 chip->info = compat_info; 4910 4911 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4912 if (err) 4913 goto out; 4914 4915 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4916 if (IS_ERR(chip->reset)) { 4917 err = PTR_ERR(chip->reset); 4918 goto out; 4919 } 4920 4921 err = mv88e6xxx_detect(chip); 4922 if (err) 4923 goto out; 4924 4925 mv88e6xxx_phy_init(chip); 4926 4927 if (chip->info->ops->get_eeprom) { 4928 if (np) 4929 of_property_read_u32(np, "eeprom-length", 4930 &chip->eeprom_len); 4931 else 4932 chip->eeprom_len = pdata->eeprom_len; 4933 } 4934 4935 mutex_lock(&chip->reg_lock); 4936 err = mv88e6xxx_switch_reset(chip); 4937 mutex_unlock(&chip->reg_lock); 4938 if (err) 4939 goto out; 4940 4941 chip->irq = of_irq_get(np, 0); 4942 if (chip->irq == -EPROBE_DEFER) { 4943 err = chip->irq; 4944 goto out; 4945 } 4946 4947 /* Has to be performed before the MDIO bus is created, because 4948 * the PHYs will link their interrupts to these interrupt 4949 * controllers 4950 */ 4951 mutex_lock(&chip->reg_lock); 4952 if (chip->irq > 0) 4953 err = mv88e6xxx_g1_irq_setup(chip); 4954 else 4955 err = mv88e6xxx_irq_poll_setup(chip); 4956 mutex_unlock(&chip->reg_lock); 4957 4958 if (err) 4959 goto out; 4960 4961 if (chip->info->g2_irqs > 0) { 4962 err = mv88e6xxx_g2_irq_setup(chip); 4963 if (err) 4964 goto out_g1_irq; 4965 } 4966 4967 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4968 if (err) 4969 goto out_g2_irq; 4970 4971 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4972 if (err) 4973 goto out_g1_atu_prob_irq; 4974 4975 err = mv88e6xxx_mdios_register(chip, np); 4976 if (err) 4977 goto out_g1_vtu_prob_irq; 4978 4979 err = mv88e6xxx_register_switch(chip); 4980 if (err) 4981 goto out_mdio; 4982 4983 return 0; 4984 4985 out_mdio: 4986 mv88e6xxx_mdios_unregister(chip); 4987 out_g1_vtu_prob_irq: 4988 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4989 out_g1_atu_prob_irq: 4990 mv88e6xxx_g1_atu_prob_irq_free(chip); 4991 out_g2_irq: 4992 if (chip->info->g2_irqs > 0) 4993 mv88e6xxx_g2_irq_free(chip); 4994 out_g1_irq: 4995 if (chip->irq > 0) 4996 mv88e6xxx_g1_irq_free(chip); 4997 else 4998 mv88e6xxx_irq_poll_free(chip); 4999 out: 5000 if (pdata) 5001 dev_put(pdata->netdev); 5002 5003 return err; 5004 } 5005 5006 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5007 { 5008 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5009 struct mv88e6xxx_chip *chip = ds->priv; 5010 5011 if (chip->info->ptp_support) { 5012 mv88e6xxx_hwtstamp_free(chip); 5013 mv88e6xxx_ptp_free(chip); 5014 } 5015 5016 mv88e6xxx_phy_destroy(chip); 5017 mv88e6xxx_unregister_switch(chip); 5018 mv88e6xxx_mdios_unregister(chip); 5019 5020 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5021 mv88e6xxx_g1_atu_prob_irq_free(chip); 5022 5023 if (chip->info->g2_irqs > 0) 5024 mv88e6xxx_g2_irq_free(chip); 5025 5026 if (chip->irq > 0) 5027 mv88e6xxx_g1_irq_free(chip); 5028 else 5029 mv88e6xxx_irq_poll_free(chip); 5030 } 5031 5032 static const struct of_device_id mv88e6xxx_of_match[] = { 5033 { 5034 .compatible = "marvell,mv88e6085", 5035 .data = &mv88e6xxx_table[MV88E6085], 5036 }, 5037 { 5038 .compatible = "marvell,mv88e6190", 5039 .data = &mv88e6xxx_table[MV88E6190], 5040 }, 5041 { /* sentinel */ }, 5042 }; 5043 5044 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5045 5046 static struct mdio_driver mv88e6xxx_driver = { 5047 .probe = mv88e6xxx_probe, 5048 .remove = mv88e6xxx_remove, 5049 .mdiodrv.driver = { 5050 .name = "mv88e6085", 5051 .of_match_table = mv88e6xxx_of_match, 5052 .pm = &mv88e6xxx_pm_ops, 5053 }, 5054 }; 5055 5056 static int __init mv88e6xxx_init(void) 5057 { 5058 register_switch_driver(&mv88e6xxx_switch_drv); 5059 return mdio_driver_register(&mv88e6xxx_driver); 5060 } 5061 module_init(mv88e6xxx_init); 5062 5063 static void __exit mv88e6xxx_cleanup(void) 5064 { 5065 mdio_driver_unregister(&mv88e6xxx_driver); 5066 unregister_switch_driver(&mv88e6xxx_switch_drv); 5067 } 5068 module_exit(mv88e6xxx_cleanup); 5069 5070 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5071 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5072 MODULE_LICENSE("GPL"); 5073