1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 475 if (err) { 476 dev_err(chip->dev, 477 "p%d: %s: failed to read port status\n", 478 port, __func__); 479 return err; 480 } 481 482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 483 } 484 485 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 486 struct phylink_link_state *state) 487 { 488 struct mv88e6xxx_chip *chip = ds->priv; 489 int lane; 490 int err; 491 492 mv88e6xxx_reg_lock(chip); 493 lane = mv88e6xxx_serdes_get_lane(chip, port); 494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 496 state); 497 else 498 err = -EOPNOTSUPP; 499 mv88e6xxx_reg_unlock(chip); 500 501 return err; 502 } 503 504 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 505 unsigned int mode, 506 phy_interface_t interface, 507 const unsigned long *advertise) 508 { 509 const struct mv88e6xxx_ops *ops = chip->info->ops; 510 int lane; 511 512 if (ops->serdes_pcs_config) { 513 lane = mv88e6xxx_serdes_get_lane(chip, port); 514 if (lane >= 0) 515 return ops->serdes_pcs_config(chip, port, lane, mode, 516 interface, advertise); 517 } 518 519 return 0; 520 } 521 522 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 523 { 524 struct mv88e6xxx_chip *chip = ds->priv; 525 const struct mv88e6xxx_ops *ops; 526 int err = 0; 527 int lane; 528 529 ops = chip->info->ops; 530 531 if (ops->serdes_pcs_an_restart) { 532 mv88e6xxx_reg_lock(chip); 533 lane = mv88e6xxx_serdes_get_lane(chip, port); 534 if (lane >= 0) 535 err = ops->serdes_pcs_an_restart(chip, port, lane); 536 mv88e6xxx_reg_unlock(chip); 537 538 if (err) 539 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 540 } 541 } 542 543 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 544 unsigned int mode, 545 int speed, int duplex) 546 { 547 const struct mv88e6xxx_ops *ops = chip->info->ops; 548 int lane; 549 550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 551 lane = mv88e6xxx_serdes_get_lane(chip, port); 552 if (lane >= 0) 553 return ops->serdes_pcs_link_up(chip, port, lane, 554 speed, duplex); 555 } 556 557 return 0; 558 } 559 560 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 561 unsigned long *mask, 562 struct phylink_link_state *state) 563 { 564 if (!phy_interface_mode_is_8023z(state->interface)) { 565 /* 10M and 100M are only supported in non-802.3z mode */ 566 phylink_set(mask, 10baseT_Half); 567 phylink_set(mask, 10baseT_Full); 568 phylink_set(mask, 100baseT_Half); 569 phylink_set(mask, 100baseT_Full); 570 } 571 } 572 573 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 574 unsigned long *mask, 575 struct phylink_link_state *state) 576 { 577 /* FIXME: if the port is in 1000Base-X mode, then it only supports 578 * 1000M FD speeds. In this case, CMODE will indicate 5. 579 */ 580 phylink_set(mask, 1000baseT_Full); 581 phylink_set(mask, 1000baseX_Full); 582 583 mv88e6065_phylink_validate(chip, port, mask, state); 584 } 585 586 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 587 unsigned long *mask, 588 struct phylink_link_state *state) 589 { 590 if (port >= 5) 591 phylink_set(mask, 2500baseX_Full); 592 593 /* No ethtool bits for 200Mbps */ 594 phylink_set(mask, 1000baseT_Full); 595 phylink_set(mask, 1000baseX_Full); 596 597 mv88e6065_phylink_validate(chip, port, mask, state); 598 } 599 600 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 601 unsigned long *mask, 602 struct phylink_link_state *state) 603 { 604 /* No ethtool bits for 200Mbps */ 605 phylink_set(mask, 1000baseT_Full); 606 phylink_set(mask, 1000baseX_Full); 607 608 mv88e6065_phylink_validate(chip, port, mask, state); 609 } 610 611 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 612 unsigned long *mask, 613 struct phylink_link_state *state) 614 { 615 if (port >= 9) { 616 phylink_set(mask, 2500baseX_Full); 617 phylink_set(mask, 2500baseT_Full); 618 } 619 620 /* No ethtool bits for 200Mbps */ 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseX_Full); 623 624 mv88e6065_phylink_validate(chip, port, mask, state); 625 } 626 627 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 628 unsigned long *mask, 629 struct phylink_link_state *state) 630 { 631 if (port >= 9) { 632 phylink_set(mask, 10000baseT_Full); 633 phylink_set(mask, 10000baseKR_Full); 634 } 635 636 mv88e6390_phylink_validate(chip, port, mask, state); 637 } 638 639 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 640 unsigned long *mask, 641 struct phylink_link_state *state) 642 { 643 if (port == 0 || port == 9 || port == 10) { 644 phylink_set(mask, 10000baseT_Full); 645 phylink_set(mask, 10000baseKR_Full); 646 phylink_set(mask, 10000baseCR_Full); 647 phylink_set(mask, 10000baseSR_Full); 648 phylink_set(mask, 10000baseLR_Full); 649 phylink_set(mask, 10000baseLRM_Full); 650 phylink_set(mask, 10000baseER_Full); 651 phylink_set(mask, 5000baseT_Full); 652 phylink_set(mask, 2500baseX_Full); 653 phylink_set(mask, 2500baseT_Full); 654 } 655 656 phylink_set(mask, 1000baseT_Full); 657 phylink_set(mask, 1000baseX_Full); 658 659 mv88e6065_phylink_validate(chip, port, mask, state); 660 } 661 662 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 663 unsigned long *supported, 664 struct phylink_link_state *state) 665 { 666 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 667 struct mv88e6xxx_chip *chip = ds->priv; 668 669 /* Allow all the expected bits */ 670 phylink_set(mask, Autoneg); 671 phylink_set(mask, Pause); 672 phylink_set_port_modes(mask); 673 674 if (chip->info->ops->phylink_validate) 675 chip->info->ops->phylink_validate(chip, port, mask, state); 676 677 linkmode_and(supported, supported, mask); 678 linkmode_and(state->advertising, state->advertising, mask); 679 680 /* We can only operate at 2500BaseX or 1000BaseX. If requested 681 * to advertise both, only report advertising at 2500BaseX. 682 */ 683 phylink_helper_basex_speed(state); 684 } 685 686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 687 unsigned int mode, 688 const struct phylink_link_state *state) 689 { 690 struct mv88e6xxx_chip *chip = ds->priv; 691 struct mv88e6xxx_port *p; 692 int err; 693 694 p = &chip->ports[port]; 695 696 /* FIXME: is this the correct test? If we're in fixed mode on an 697 * internal port, why should we process this any different from 698 * PHY mode? On the other hand, the port may be automedia between 699 * an internal PHY and the serdes... 700 */ 701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 702 return; 703 704 mv88e6xxx_reg_lock(chip); 705 /* In inband mode, the link may come up at any time while the link 706 * is not forced down. Force the link down while we reconfigure the 707 * interface mode. 708 */ 709 if (mode == MLO_AN_INBAND && p->interface != state->interface && 710 chip->info->ops->port_set_link) 711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 712 713 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 714 if (err && err != -EOPNOTSUPP) 715 goto err_unlock; 716 717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 718 state->advertising); 719 /* FIXME: we should restart negotiation if something changed - which 720 * is something we get if we convert to using phylinks PCS operations. 721 */ 722 if (err > 0) 723 err = 0; 724 725 /* Undo the forced down state above after completing configuration 726 * irrespective of its state on entry, which allows the link to come up. 727 */ 728 if (mode == MLO_AN_INBAND && p->interface != state->interface && 729 chip->info->ops->port_set_link) 730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 731 732 p->interface = state->interface; 733 734 err_unlock: 735 mv88e6xxx_reg_unlock(chip); 736 737 if (err && err != -EOPNOTSUPP) 738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 739 } 740 741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 742 unsigned int mode, 743 phy_interface_t interface) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 /* Internal PHYs propagate their configuration directly to the MAC. 753 * External PHYs depend on whether the PPU is enabled for this port. 754 */ 755 if (((!mv88e6xxx_phy_is_internal(ds, port) && 756 !mv88e6xxx_port_ppu_updates(chip, port)) || 757 mode == MLO_AN_FIXED) && ops->port_sync_link) 758 err = ops->port_sync_link(chip, port, mode, false); 759 mv88e6xxx_reg_unlock(chip); 760 761 if (err) 762 dev_err(chip->dev, 763 "p%d: failed to force MAC link down\n", port); 764 } 765 766 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 767 unsigned int mode, phy_interface_t interface, 768 struct phy_device *phydev, 769 int speed, int duplex, 770 bool tx_pause, bool rx_pause) 771 { 772 struct mv88e6xxx_chip *chip = ds->priv; 773 const struct mv88e6xxx_ops *ops; 774 int err = 0; 775 776 ops = chip->info->ops; 777 778 mv88e6xxx_reg_lock(chip); 779 /* Internal PHYs propagate their configuration directly to the MAC. 780 * External PHYs depend on whether the PPU is enabled for this port. 781 */ 782 if ((!mv88e6xxx_phy_is_internal(ds, port) && 783 !mv88e6xxx_port_ppu_updates(chip, port)) || 784 mode == MLO_AN_FIXED) { 785 /* FIXME: for an automedia port, should we force the link 786 * down here - what if the link comes up due to "other" media 787 * while we're bringing the port up, how is the exclusivity 788 * handled in the Marvell hardware? E.g. port 2 on 88E6390 789 * shared between internal PHY and Serdes. 790 */ 791 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 792 duplex); 793 if (err) 794 goto error; 795 796 if (ops->port_set_speed_duplex) { 797 err = ops->port_set_speed_duplex(chip, port, 798 speed, duplex); 799 if (err && err != -EOPNOTSUPP) 800 goto error; 801 } 802 803 if (ops->port_sync_link) 804 err = ops->port_sync_link(chip, port, mode, true); 805 } 806 error: 807 mv88e6xxx_reg_unlock(chip); 808 809 if (err && err != -EOPNOTSUPP) 810 dev_err(ds->dev, 811 "p%d: failed to configure MAC link up\n", port); 812 } 813 814 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 815 { 816 if (!chip->info->ops->stats_snapshot) 817 return -EOPNOTSUPP; 818 819 return chip->info->ops->stats_snapshot(chip, port); 820 } 821 822 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 823 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 824 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 825 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 826 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 827 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 828 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 829 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 830 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 831 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 832 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 833 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 834 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 835 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 836 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 837 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 838 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 839 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 840 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 841 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 842 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 843 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 844 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 845 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 846 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 847 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 848 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 849 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 850 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 851 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 852 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 853 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 854 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 855 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 856 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 857 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 858 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 859 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 860 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 861 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 862 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 863 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 864 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 865 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 866 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 867 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 868 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 869 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 870 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 871 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 872 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 873 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 874 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 875 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 876 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 877 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 878 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 879 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 880 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 881 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 882 }; 883 884 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 885 struct mv88e6xxx_hw_stat *s, 886 int port, u16 bank1_select, 887 u16 histogram) 888 { 889 u32 low; 890 u32 high = 0; 891 u16 reg = 0; 892 int err; 893 u64 value; 894 895 switch (s->type) { 896 case STATS_TYPE_PORT: 897 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 898 if (err) 899 return U64_MAX; 900 901 low = reg; 902 if (s->size == 4) { 903 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 904 if (err) 905 return U64_MAX; 906 low |= ((u32)reg) << 16; 907 } 908 break; 909 case STATS_TYPE_BANK1: 910 reg = bank1_select; 911 fallthrough; 912 case STATS_TYPE_BANK0: 913 reg |= s->reg | histogram; 914 mv88e6xxx_g1_stats_read(chip, reg, &low); 915 if (s->size == 8) 916 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 917 break; 918 default: 919 return U64_MAX; 920 } 921 value = (((u64)high) << 32) | low; 922 return value; 923 } 924 925 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 926 uint8_t *data, int types) 927 { 928 struct mv88e6xxx_hw_stat *stat; 929 int i, j; 930 931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 932 stat = &mv88e6xxx_hw_stats[i]; 933 if (stat->type & types) { 934 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 935 ETH_GSTRING_LEN); 936 j++; 937 } 938 } 939 940 return j; 941 } 942 943 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 944 uint8_t *data) 945 { 946 return mv88e6xxx_stats_get_strings(chip, data, 947 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 948 } 949 950 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 951 uint8_t *data) 952 { 953 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 954 } 955 956 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 957 uint8_t *data) 958 { 959 return mv88e6xxx_stats_get_strings(chip, data, 960 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 961 } 962 963 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 964 "atu_member_violation", 965 "atu_miss_violation", 966 "atu_full_violation", 967 "vtu_member_violation", 968 "vtu_miss_violation", 969 }; 970 971 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 972 { 973 unsigned int i; 974 975 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 976 strlcpy(data + i * ETH_GSTRING_LEN, 977 mv88e6xxx_atu_vtu_stats_strings[i], 978 ETH_GSTRING_LEN); 979 } 980 981 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 982 u32 stringset, uint8_t *data) 983 { 984 struct mv88e6xxx_chip *chip = ds->priv; 985 int count = 0; 986 987 if (stringset != ETH_SS_STATS) 988 return; 989 990 mv88e6xxx_reg_lock(chip); 991 992 if (chip->info->ops->stats_get_strings) 993 count = chip->info->ops->stats_get_strings(chip, data); 994 995 if (chip->info->ops->serdes_get_strings) { 996 data += count * ETH_GSTRING_LEN; 997 count = chip->info->ops->serdes_get_strings(chip, port, data); 998 } 999 1000 data += count * ETH_GSTRING_LEN; 1001 mv88e6xxx_atu_vtu_get_strings(data); 1002 1003 mv88e6xxx_reg_unlock(chip); 1004 } 1005 1006 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1007 int types) 1008 { 1009 struct mv88e6xxx_hw_stat *stat; 1010 int i, j; 1011 1012 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1013 stat = &mv88e6xxx_hw_stats[i]; 1014 if (stat->type & types) 1015 j++; 1016 } 1017 return j; 1018 } 1019 1020 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1021 { 1022 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1023 STATS_TYPE_PORT); 1024 } 1025 1026 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1027 { 1028 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1029 } 1030 1031 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1032 { 1033 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1034 STATS_TYPE_BANK1); 1035 } 1036 1037 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1038 { 1039 struct mv88e6xxx_chip *chip = ds->priv; 1040 int serdes_count = 0; 1041 int count = 0; 1042 1043 if (sset != ETH_SS_STATS) 1044 return 0; 1045 1046 mv88e6xxx_reg_lock(chip); 1047 if (chip->info->ops->stats_get_sset_count) 1048 count = chip->info->ops->stats_get_sset_count(chip); 1049 if (count < 0) 1050 goto out; 1051 1052 if (chip->info->ops->serdes_get_sset_count) 1053 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1054 port); 1055 if (serdes_count < 0) { 1056 count = serdes_count; 1057 goto out; 1058 } 1059 count += serdes_count; 1060 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1061 1062 out: 1063 mv88e6xxx_reg_unlock(chip); 1064 1065 return count; 1066 } 1067 1068 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1069 uint64_t *data, int types, 1070 u16 bank1_select, u16 histogram) 1071 { 1072 struct mv88e6xxx_hw_stat *stat; 1073 int i, j; 1074 1075 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1076 stat = &mv88e6xxx_hw_stats[i]; 1077 if (stat->type & types) { 1078 mv88e6xxx_reg_lock(chip); 1079 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1080 bank1_select, 1081 histogram); 1082 mv88e6xxx_reg_unlock(chip); 1083 1084 j++; 1085 } 1086 } 1087 return j; 1088 } 1089 1090 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1091 uint64_t *data) 1092 { 1093 return mv88e6xxx_stats_get_stats(chip, port, data, 1094 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1095 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1096 } 1097 1098 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1099 uint64_t *data) 1100 { 1101 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1102 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1103 } 1104 1105 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1106 uint64_t *data) 1107 { 1108 return mv88e6xxx_stats_get_stats(chip, port, data, 1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1111 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1112 } 1113 1114 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 return mv88e6xxx_stats_get_stats(chip, port, data, 1118 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1119 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1120 0); 1121 } 1122 1123 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1124 uint64_t *data) 1125 { 1126 *data++ = chip->ports[port].atu_member_violation; 1127 *data++ = chip->ports[port].atu_miss_violation; 1128 *data++ = chip->ports[port].atu_full_violation; 1129 *data++ = chip->ports[port].vtu_member_violation; 1130 *data++ = chip->ports[port].vtu_miss_violation; 1131 } 1132 1133 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1134 uint64_t *data) 1135 { 1136 int count = 0; 1137 1138 if (chip->info->ops->stats_get_stats) 1139 count = chip->info->ops->stats_get_stats(chip, port, data); 1140 1141 mv88e6xxx_reg_lock(chip); 1142 if (chip->info->ops->serdes_get_stats) { 1143 data += count; 1144 count = chip->info->ops->serdes_get_stats(chip, port, data); 1145 } 1146 data += count; 1147 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1148 mv88e6xxx_reg_unlock(chip); 1149 } 1150 1151 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1152 uint64_t *data) 1153 { 1154 struct mv88e6xxx_chip *chip = ds->priv; 1155 int ret; 1156 1157 mv88e6xxx_reg_lock(chip); 1158 1159 ret = mv88e6xxx_stats_snapshot(chip, port); 1160 mv88e6xxx_reg_unlock(chip); 1161 1162 if (ret < 0) 1163 return; 1164 1165 mv88e6xxx_get_stats(chip, port, data); 1166 1167 } 1168 1169 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1170 { 1171 struct mv88e6xxx_chip *chip = ds->priv; 1172 int len; 1173 1174 len = 32 * sizeof(u16); 1175 if (chip->info->ops->serdes_get_regs_len) 1176 len += chip->info->ops->serdes_get_regs_len(chip, port); 1177 1178 return len; 1179 } 1180 1181 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1182 struct ethtool_regs *regs, void *_p) 1183 { 1184 struct mv88e6xxx_chip *chip = ds->priv; 1185 int err; 1186 u16 reg; 1187 u16 *p = _p; 1188 int i; 1189 1190 regs->version = chip->info->prod_num; 1191 1192 memset(p, 0xff, 32 * sizeof(u16)); 1193 1194 mv88e6xxx_reg_lock(chip); 1195 1196 for (i = 0; i < 32; i++) { 1197 1198 err = mv88e6xxx_port_read(chip, port, i, ®); 1199 if (!err) 1200 p[i] = reg; 1201 } 1202 1203 if (chip->info->ops->serdes_get_regs) 1204 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1205 1206 mv88e6xxx_reg_unlock(chip); 1207 } 1208 1209 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1210 struct ethtool_eee *e) 1211 { 1212 /* Nothing to do on the port's MAC */ 1213 return 0; 1214 } 1215 1216 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1217 struct ethtool_eee *e) 1218 { 1219 /* Nothing to do on the port's MAC */ 1220 return 0; 1221 } 1222 1223 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1224 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1225 { 1226 struct dsa_switch *ds = chip->ds; 1227 struct dsa_switch_tree *dst = ds->dst; 1228 struct net_device *br; 1229 struct dsa_port *dp; 1230 bool found = false; 1231 u16 pvlan; 1232 1233 /* dev is a physical switch */ 1234 if (dev <= dst->last_switch) { 1235 list_for_each_entry(dp, &dst->ports, list) { 1236 if (dp->ds->index == dev && dp->index == port) { 1237 /* dp might be a DSA link or a user port, so it 1238 * might or might not have a bridge_dev 1239 * pointer. Use the "found" variable for both 1240 * cases. 1241 */ 1242 br = dp->bridge_dev; 1243 found = true; 1244 break; 1245 } 1246 } 1247 /* dev is a virtual bridge */ 1248 } else { 1249 list_for_each_entry(dp, &dst->ports, list) { 1250 if (dp->bridge_num < 0) 1251 continue; 1252 1253 if (dp->bridge_num + 1 + dst->last_switch != dev) 1254 continue; 1255 1256 br = dp->bridge_dev; 1257 found = true; 1258 break; 1259 } 1260 } 1261 1262 /* Prevent frames from unknown switch or virtual bridge */ 1263 if (!found) 1264 return 0; 1265 1266 /* Frames from DSA links and CPU ports can egress any local port */ 1267 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1268 return mv88e6xxx_port_mask(chip); 1269 1270 pvlan = 0; 1271 1272 /* Frames from user ports can egress any local DSA links and CPU ports, 1273 * as well as any local member of their bridge group. 1274 */ 1275 list_for_each_entry(dp, &dst->ports, list) 1276 if (dp->ds == ds && 1277 (dp->type == DSA_PORT_TYPE_CPU || 1278 dp->type == DSA_PORT_TYPE_DSA || 1279 (br && dp->bridge_dev == br))) 1280 pvlan |= BIT(dp->index); 1281 1282 return pvlan; 1283 } 1284 1285 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1286 { 1287 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1288 1289 /* prevent frames from going back out of the port they came in on */ 1290 output_ports &= ~BIT(port); 1291 1292 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1293 } 1294 1295 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1296 u8 state) 1297 { 1298 struct mv88e6xxx_chip *chip = ds->priv; 1299 int err; 1300 1301 mv88e6xxx_reg_lock(chip); 1302 err = mv88e6xxx_port_set_state(chip, port, state); 1303 mv88e6xxx_reg_unlock(chip); 1304 1305 if (err) 1306 dev_err(ds->dev, "p%d: failed to update state\n", port); 1307 } 1308 1309 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 int err; 1312 1313 if (chip->info->ops->ieee_pri_map) { 1314 err = chip->info->ops->ieee_pri_map(chip); 1315 if (err) 1316 return err; 1317 } 1318 1319 if (chip->info->ops->ip_pri_map) { 1320 err = chip->info->ops->ip_pri_map(chip); 1321 if (err) 1322 return err; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1329 { 1330 struct dsa_switch *ds = chip->ds; 1331 int target, port; 1332 int err; 1333 1334 if (!chip->info->global2_addr) 1335 return 0; 1336 1337 /* Initialize the routing port to the 32 possible target devices */ 1338 for (target = 0; target < 32; target++) { 1339 port = dsa_routing_port(ds, target); 1340 if (port == ds->num_ports) 1341 port = 0x1f; 1342 1343 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1344 if (err) 1345 return err; 1346 } 1347 1348 if (chip->info->ops->set_cascade_port) { 1349 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1350 err = chip->info->ops->set_cascade_port(chip, port); 1351 if (err) 1352 return err; 1353 } 1354 1355 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1356 if (err) 1357 return err; 1358 1359 return 0; 1360 } 1361 1362 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1363 { 1364 /* Clear all trunk masks and mapping */ 1365 if (chip->info->global2_addr) 1366 return mv88e6xxx_g2_trunk_clear(chip); 1367 1368 return 0; 1369 } 1370 1371 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1372 { 1373 if (chip->info->ops->rmu_disable) 1374 return chip->info->ops->rmu_disable(chip); 1375 1376 return 0; 1377 } 1378 1379 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1380 { 1381 if (chip->info->ops->pot_clear) 1382 return chip->info->ops->pot_clear(chip); 1383 1384 return 0; 1385 } 1386 1387 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 if (chip->info->ops->mgmt_rsvd2cpu) 1390 return chip->info->ops->mgmt_rsvd2cpu(chip); 1391 1392 return 0; 1393 } 1394 1395 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1396 { 1397 int err; 1398 1399 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1400 if (err) 1401 return err; 1402 1403 /* The chips that have a "learn2all" bit in Global1, ATU 1404 * Control are precisely those whose port registers have a 1405 * Message Port bit in Port Control 1 and hence implement 1406 * ->port_setup_message_port. 1407 */ 1408 if (chip->info->ops->port_setup_message_port) { 1409 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1410 if (err) 1411 return err; 1412 } 1413 1414 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1415 } 1416 1417 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1418 { 1419 int port; 1420 int err; 1421 1422 if (!chip->info->ops->irl_init_all) 1423 return 0; 1424 1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1426 /* Disable ingress rate limiting by resetting all per port 1427 * ingress rate limit resources to their initial state. 1428 */ 1429 err = chip->info->ops->irl_init_all(chip, port); 1430 if (err) 1431 return err; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1438 { 1439 if (chip->info->ops->set_switch_mac) { 1440 u8 addr[ETH_ALEN]; 1441 1442 eth_random_addr(addr); 1443 1444 return chip->info->ops->set_switch_mac(chip, addr); 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1451 { 1452 struct dsa_switch_tree *dst = chip->ds->dst; 1453 struct dsa_switch *ds; 1454 struct dsa_port *dp; 1455 u16 pvlan = 0; 1456 1457 if (!mv88e6xxx_has_pvt(chip)) 1458 return 0; 1459 1460 /* Skip the local source device, which uses in-chip port VLAN */ 1461 if (dev != chip->ds->index) { 1462 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1463 1464 ds = dsa_switch_find(dst->index, dev); 1465 dp = ds ? dsa_to_port(ds, port) : NULL; 1466 if (dp && dp->lag_dev) { 1467 /* As the PVT is used to limit flooding of 1468 * FORWARD frames, which use the LAG ID as the 1469 * source port, we must translate dev/port to 1470 * the special "LAG device" in the PVT, using 1471 * the LAG ID as the port number. 1472 */ 1473 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1474 port = dsa_lag_id(dst, dp->lag_dev); 1475 } 1476 } 1477 1478 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1479 } 1480 1481 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1482 { 1483 int dev, port; 1484 int err; 1485 1486 if (!mv88e6xxx_has_pvt(chip)) 1487 return 0; 1488 1489 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1490 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1491 */ 1492 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1493 if (err) 1494 return err; 1495 1496 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1497 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1498 err = mv88e6xxx_pvt_map(chip, dev, port); 1499 if (err) 1500 return err; 1501 } 1502 } 1503 1504 return 0; 1505 } 1506 1507 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1508 { 1509 struct mv88e6xxx_chip *chip = ds->priv; 1510 int err; 1511 1512 if (dsa_to_port(ds, port)->lag_dev) 1513 /* Hardware is incapable of fast-aging a LAG through a 1514 * regular ATU move operation. Until we have something 1515 * more fancy in place this is a no-op. 1516 */ 1517 return; 1518 1519 mv88e6xxx_reg_lock(chip); 1520 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1521 mv88e6xxx_reg_unlock(chip); 1522 1523 if (err) 1524 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1525 } 1526 1527 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1528 { 1529 if (!mv88e6xxx_max_vid(chip)) 1530 return 0; 1531 1532 return mv88e6xxx_g1_vtu_flush(chip); 1533 } 1534 1535 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1536 struct mv88e6xxx_vtu_entry *entry) 1537 { 1538 int err; 1539 1540 if (!chip->info->ops->vtu_getnext) 1541 return -EOPNOTSUPP; 1542 1543 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1544 entry->valid = false; 1545 1546 err = chip->info->ops->vtu_getnext(chip, entry); 1547 1548 if (entry->vid != vid) 1549 entry->valid = false; 1550 1551 return err; 1552 } 1553 1554 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1555 int (*cb)(struct mv88e6xxx_chip *chip, 1556 const struct mv88e6xxx_vtu_entry *entry, 1557 void *priv), 1558 void *priv) 1559 { 1560 struct mv88e6xxx_vtu_entry entry = { 1561 .vid = mv88e6xxx_max_vid(chip), 1562 .valid = false, 1563 }; 1564 int err; 1565 1566 if (!chip->info->ops->vtu_getnext) 1567 return -EOPNOTSUPP; 1568 1569 do { 1570 err = chip->info->ops->vtu_getnext(chip, &entry); 1571 if (err) 1572 return err; 1573 1574 if (!entry.valid) 1575 break; 1576 1577 err = cb(chip, &entry, priv); 1578 if (err) 1579 return err; 1580 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1581 1582 return 0; 1583 } 1584 1585 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1586 struct mv88e6xxx_vtu_entry *entry) 1587 { 1588 if (!chip->info->ops->vtu_loadpurge) 1589 return -EOPNOTSUPP; 1590 1591 return chip->info->ops->vtu_loadpurge(chip, entry); 1592 } 1593 1594 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1595 const struct mv88e6xxx_vtu_entry *entry, 1596 void *_fid_bitmap) 1597 { 1598 unsigned long *fid_bitmap = _fid_bitmap; 1599 1600 set_bit(entry->fid, fid_bitmap); 1601 return 0; 1602 } 1603 1604 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1605 { 1606 int i, err; 1607 u16 fid; 1608 1609 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1610 1611 /* Set every FID bit used by the (un)bridged ports */ 1612 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1613 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1614 if (err) 1615 return err; 1616 1617 set_bit(fid, fid_bitmap); 1618 } 1619 1620 /* Set every FID bit used by the VLAN entries */ 1621 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1622 } 1623 1624 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1625 { 1626 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1627 int err; 1628 1629 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1630 if (err) 1631 return err; 1632 1633 /* The reset value 0x000 is used to indicate that multiple address 1634 * databases are not needed. Return the next positive available. 1635 */ 1636 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1637 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1638 return -ENOSPC; 1639 1640 /* Clear the database */ 1641 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1642 } 1643 1644 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1645 u16 vid) 1646 { 1647 struct mv88e6xxx_chip *chip = ds->priv; 1648 struct mv88e6xxx_vtu_entry vlan; 1649 int i, err; 1650 1651 /* DSA and CPU ports have to be members of multiple vlans */ 1652 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1653 return 0; 1654 1655 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1656 if (err) 1657 return err; 1658 1659 if (!vlan.valid) 1660 return 0; 1661 1662 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1663 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1664 continue; 1665 1666 if (!dsa_to_port(ds, i)->slave) 1667 continue; 1668 1669 if (vlan.member[i] == 1670 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1671 continue; 1672 1673 if (dsa_to_port(ds, i)->bridge_dev == 1674 dsa_to_port(ds, port)->bridge_dev) 1675 break; /* same bridge, check next VLAN */ 1676 1677 if (!dsa_to_port(ds, i)->bridge_dev) 1678 continue; 1679 1680 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1681 port, vlan.vid, i, 1682 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1683 return -EOPNOTSUPP; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1690 { 1691 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1692 struct mv88e6xxx_port *p = &chip->ports[port]; 1693 u16 pvid = MV88E6XXX_VID_STANDALONE; 1694 bool drop_untagged = false; 1695 int err; 1696 1697 if (dp->bridge_dev) { 1698 if (br_vlan_enabled(dp->bridge_dev)) { 1699 pvid = p->bridge_pvid.vid; 1700 drop_untagged = !p->bridge_pvid.valid; 1701 } else { 1702 pvid = MV88E6XXX_VID_BRIDGED; 1703 } 1704 } 1705 1706 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1707 if (err) 1708 return err; 1709 1710 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1711 } 1712 1713 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1714 bool vlan_filtering, 1715 struct netlink_ext_ack *extack) 1716 { 1717 struct mv88e6xxx_chip *chip = ds->priv; 1718 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1719 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1720 int err; 1721 1722 if (!mv88e6xxx_max_vid(chip)) 1723 return -EOPNOTSUPP; 1724 1725 mv88e6xxx_reg_lock(chip); 1726 1727 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1728 if (err) 1729 goto unlock; 1730 1731 err = mv88e6xxx_port_commit_pvid(chip, port); 1732 if (err) 1733 goto unlock; 1734 1735 unlock: 1736 mv88e6xxx_reg_unlock(chip); 1737 1738 return err; 1739 } 1740 1741 static int 1742 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1743 const struct switchdev_obj_port_vlan *vlan) 1744 { 1745 struct mv88e6xxx_chip *chip = ds->priv; 1746 int err; 1747 1748 if (!mv88e6xxx_max_vid(chip)) 1749 return -EOPNOTSUPP; 1750 1751 /* If the requested port doesn't belong to the same bridge as the VLAN 1752 * members, do not support it (yet) and fallback to software VLAN. 1753 */ 1754 mv88e6xxx_reg_lock(chip); 1755 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1756 mv88e6xxx_reg_unlock(chip); 1757 1758 return err; 1759 } 1760 1761 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1762 const unsigned char *addr, u16 vid, 1763 u8 state) 1764 { 1765 struct mv88e6xxx_atu_entry entry; 1766 struct mv88e6xxx_vtu_entry vlan; 1767 u16 fid; 1768 int err; 1769 1770 /* Ports have two private address databases: one for when the port is 1771 * standalone and one for when the port is under a bridge and the 1772 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1773 * address database to remain 100% empty, so we never load an ATU entry 1774 * into a standalone port's database. Therefore, translate the null 1775 * VLAN ID into the port's database used for VLAN-unaware bridging. 1776 */ 1777 if (vid == 0) { 1778 fid = MV88E6XXX_FID_BRIDGED; 1779 } else { 1780 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1781 if (err) 1782 return err; 1783 1784 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1785 if (!vlan.valid) 1786 return -EOPNOTSUPP; 1787 1788 fid = vlan.fid; 1789 } 1790 1791 entry.state = 0; 1792 ether_addr_copy(entry.mac, addr); 1793 eth_addr_dec(entry.mac); 1794 1795 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1796 if (err) 1797 return err; 1798 1799 /* Initialize a fresh ATU entry if it isn't found */ 1800 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1801 memset(&entry, 0, sizeof(entry)); 1802 ether_addr_copy(entry.mac, addr); 1803 } 1804 1805 /* Purge the ATU entry only if no port is using it anymore */ 1806 if (!state) { 1807 entry.portvec &= ~BIT(port); 1808 if (!entry.portvec) 1809 entry.state = 0; 1810 } else { 1811 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1812 entry.portvec = BIT(port); 1813 else 1814 entry.portvec |= BIT(port); 1815 1816 entry.state = state; 1817 } 1818 1819 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1820 } 1821 1822 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1823 const struct mv88e6xxx_policy *policy) 1824 { 1825 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1826 enum mv88e6xxx_policy_action action = policy->action; 1827 const u8 *addr = policy->addr; 1828 u16 vid = policy->vid; 1829 u8 state; 1830 int err; 1831 int id; 1832 1833 if (!chip->info->ops->port_set_policy) 1834 return -EOPNOTSUPP; 1835 1836 switch (mapping) { 1837 case MV88E6XXX_POLICY_MAPPING_DA: 1838 case MV88E6XXX_POLICY_MAPPING_SA: 1839 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1840 state = 0; /* Dissociate the port and address */ 1841 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1842 is_multicast_ether_addr(addr)) 1843 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1844 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1845 is_unicast_ether_addr(addr)) 1846 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1847 else 1848 return -EOPNOTSUPP; 1849 1850 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1851 state); 1852 if (err) 1853 return err; 1854 break; 1855 default: 1856 return -EOPNOTSUPP; 1857 } 1858 1859 /* Skip the port's policy clearing if the mapping is still in use */ 1860 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1861 idr_for_each_entry(&chip->policies, policy, id) 1862 if (policy->port == port && 1863 policy->mapping == mapping && 1864 policy->action != action) 1865 return 0; 1866 1867 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1868 } 1869 1870 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1871 struct ethtool_rx_flow_spec *fs) 1872 { 1873 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1874 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1875 enum mv88e6xxx_policy_mapping mapping; 1876 enum mv88e6xxx_policy_action action; 1877 struct mv88e6xxx_policy *policy; 1878 u16 vid = 0; 1879 u8 *addr; 1880 int err; 1881 int id; 1882 1883 if (fs->location != RX_CLS_LOC_ANY) 1884 return -EINVAL; 1885 1886 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1887 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1888 else 1889 return -EOPNOTSUPP; 1890 1891 switch (fs->flow_type & ~FLOW_EXT) { 1892 case ETHER_FLOW: 1893 if (!is_zero_ether_addr(mac_mask->h_dest) && 1894 is_zero_ether_addr(mac_mask->h_source)) { 1895 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1896 addr = mac_entry->h_dest; 1897 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1898 !is_zero_ether_addr(mac_mask->h_source)) { 1899 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1900 addr = mac_entry->h_source; 1901 } else { 1902 /* Cannot support DA and SA mapping in the same rule */ 1903 return -EOPNOTSUPP; 1904 } 1905 break; 1906 default: 1907 return -EOPNOTSUPP; 1908 } 1909 1910 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1911 if (fs->m_ext.vlan_tci != htons(0xffff)) 1912 return -EOPNOTSUPP; 1913 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1914 } 1915 1916 idr_for_each_entry(&chip->policies, policy, id) { 1917 if (policy->port == port && policy->mapping == mapping && 1918 policy->action == action && policy->vid == vid && 1919 ether_addr_equal(policy->addr, addr)) 1920 return -EEXIST; 1921 } 1922 1923 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1924 if (!policy) 1925 return -ENOMEM; 1926 1927 fs->location = 0; 1928 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1929 GFP_KERNEL); 1930 if (err) { 1931 devm_kfree(chip->dev, policy); 1932 return err; 1933 } 1934 1935 memcpy(&policy->fs, fs, sizeof(*fs)); 1936 ether_addr_copy(policy->addr, addr); 1937 policy->mapping = mapping; 1938 policy->action = action; 1939 policy->port = port; 1940 policy->vid = vid; 1941 1942 err = mv88e6xxx_policy_apply(chip, port, policy); 1943 if (err) { 1944 idr_remove(&chip->policies, fs->location); 1945 devm_kfree(chip->dev, policy); 1946 return err; 1947 } 1948 1949 return 0; 1950 } 1951 1952 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1953 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1954 { 1955 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1956 struct mv88e6xxx_chip *chip = ds->priv; 1957 struct mv88e6xxx_policy *policy; 1958 int err; 1959 int id; 1960 1961 mv88e6xxx_reg_lock(chip); 1962 1963 switch (rxnfc->cmd) { 1964 case ETHTOOL_GRXCLSRLCNT: 1965 rxnfc->data = 0; 1966 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1967 rxnfc->rule_cnt = 0; 1968 idr_for_each_entry(&chip->policies, policy, id) 1969 if (policy->port == port) 1970 rxnfc->rule_cnt++; 1971 err = 0; 1972 break; 1973 case ETHTOOL_GRXCLSRULE: 1974 err = -ENOENT; 1975 policy = idr_find(&chip->policies, fs->location); 1976 if (policy) { 1977 memcpy(fs, &policy->fs, sizeof(*fs)); 1978 err = 0; 1979 } 1980 break; 1981 case ETHTOOL_GRXCLSRLALL: 1982 rxnfc->data = 0; 1983 rxnfc->rule_cnt = 0; 1984 idr_for_each_entry(&chip->policies, policy, id) 1985 if (policy->port == port) 1986 rule_locs[rxnfc->rule_cnt++] = id; 1987 err = 0; 1988 break; 1989 default: 1990 err = -EOPNOTSUPP; 1991 break; 1992 } 1993 1994 mv88e6xxx_reg_unlock(chip); 1995 1996 return err; 1997 } 1998 1999 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2000 struct ethtool_rxnfc *rxnfc) 2001 { 2002 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2003 struct mv88e6xxx_chip *chip = ds->priv; 2004 struct mv88e6xxx_policy *policy; 2005 int err; 2006 2007 mv88e6xxx_reg_lock(chip); 2008 2009 switch (rxnfc->cmd) { 2010 case ETHTOOL_SRXCLSRLINS: 2011 err = mv88e6xxx_policy_insert(chip, port, fs); 2012 break; 2013 case ETHTOOL_SRXCLSRLDEL: 2014 err = -ENOENT; 2015 policy = idr_remove(&chip->policies, fs->location); 2016 if (policy) { 2017 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2018 err = mv88e6xxx_policy_apply(chip, port, policy); 2019 devm_kfree(chip->dev, policy); 2020 } 2021 break; 2022 default: 2023 err = -EOPNOTSUPP; 2024 break; 2025 } 2026 2027 mv88e6xxx_reg_unlock(chip); 2028 2029 return err; 2030 } 2031 2032 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2033 u16 vid) 2034 { 2035 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2036 u8 broadcast[ETH_ALEN]; 2037 2038 eth_broadcast_addr(broadcast); 2039 2040 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2041 } 2042 2043 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2044 { 2045 int port; 2046 int err; 2047 2048 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2049 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2050 struct net_device *brport; 2051 2052 if (dsa_is_unused_port(chip->ds, port)) 2053 continue; 2054 2055 brport = dsa_port_to_bridge_port(dp); 2056 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2057 /* Skip bridged user ports where broadcast 2058 * flooding is disabled. 2059 */ 2060 continue; 2061 2062 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2063 if (err) 2064 return err; 2065 } 2066 2067 return 0; 2068 } 2069 2070 struct mv88e6xxx_port_broadcast_sync_ctx { 2071 int port; 2072 bool flood; 2073 }; 2074 2075 static int 2076 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2077 const struct mv88e6xxx_vtu_entry *vlan, 2078 void *_ctx) 2079 { 2080 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2081 u8 broadcast[ETH_ALEN]; 2082 u8 state; 2083 2084 if (ctx->flood) 2085 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2086 else 2087 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2088 2089 eth_broadcast_addr(broadcast); 2090 2091 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2092 vlan->vid, state); 2093 } 2094 2095 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2096 bool flood) 2097 { 2098 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2099 .port = port, 2100 .flood = flood, 2101 }; 2102 struct mv88e6xxx_vtu_entry vid0 = { 2103 .vid = 0, 2104 }; 2105 int err; 2106 2107 /* Update the port's private database... */ 2108 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2109 if (err) 2110 return err; 2111 2112 /* ...and the database for all VLANs. */ 2113 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2114 &ctx); 2115 } 2116 2117 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2118 u16 vid, u8 member, bool warn) 2119 { 2120 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2121 struct mv88e6xxx_vtu_entry vlan; 2122 int i, err; 2123 2124 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2125 if (err) 2126 return err; 2127 2128 if (!vlan.valid) { 2129 memset(&vlan, 0, sizeof(vlan)); 2130 2131 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2132 if (err) 2133 return err; 2134 2135 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2136 if (i == port) 2137 vlan.member[i] = member; 2138 else 2139 vlan.member[i] = non_member; 2140 2141 vlan.vid = vid; 2142 vlan.valid = true; 2143 2144 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2145 if (err) 2146 return err; 2147 2148 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2149 if (err) 2150 return err; 2151 } else if (vlan.member[port] != member) { 2152 vlan.member[port] = member; 2153 2154 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2155 if (err) 2156 return err; 2157 } else if (warn) { 2158 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2159 port, vid); 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2166 const struct switchdev_obj_port_vlan *vlan, 2167 struct netlink_ext_ack *extack) 2168 { 2169 struct mv88e6xxx_chip *chip = ds->priv; 2170 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2171 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2172 struct mv88e6xxx_port *p = &chip->ports[port]; 2173 bool warn; 2174 u8 member; 2175 int err; 2176 2177 if (!vlan->vid) 2178 return 0; 2179 2180 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2181 if (err) 2182 return err; 2183 2184 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2185 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2186 else if (untagged) 2187 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2188 else 2189 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2190 2191 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2192 * and then the CPU port. Do not warn for duplicates for the CPU port. 2193 */ 2194 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2195 2196 mv88e6xxx_reg_lock(chip); 2197 2198 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2199 if (err) { 2200 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2201 vlan->vid, untagged ? 'u' : 't'); 2202 goto out; 2203 } 2204 2205 if (pvid) { 2206 p->bridge_pvid.vid = vlan->vid; 2207 p->bridge_pvid.valid = true; 2208 2209 err = mv88e6xxx_port_commit_pvid(chip, port); 2210 if (err) 2211 goto out; 2212 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2213 /* The old pvid was reinstalled as a non-pvid VLAN */ 2214 p->bridge_pvid.valid = false; 2215 2216 err = mv88e6xxx_port_commit_pvid(chip, port); 2217 if (err) 2218 goto out; 2219 } 2220 2221 out: 2222 mv88e6xxx_reg_unlock(chip); 2223 2224 return err; 2225 } 2226 2227 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2228 int port, u16 vid) 2229 { 2230 struct mv88e6xxx_vtu_entry vlan; 2231 int i, err; 2232 2233 if (!vid) 2234 return 0; 2235 2236 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2237 if (err) 2238 return err; 2239 2240 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2241 * tell switchdev that this VLAN is likely handled in software. 2242 */ 2243 if (!vlan.valid || 2244 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2245 return -EOPNOTSUPP; 2246 2247 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2248 2249 /* keep the VLAN unless all ports are excluded */ 2250 vlan.valid = false; 2251 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2252 if (vlan.member[i] != 2253 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2254 vlan.valid = true; 2255 break; 2256 } 2257 } 2258 2259 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2260 if (err) 2261 return err; 2262 2263 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2264 } 2265 2266 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2267 const struct switchdev_obj_port_vlan *vlan) 2268 { 2269 struct mv88e6xxx_chip *chip = ds->priv; 2270 struct mv88e6xxx_port *p = &chip->ports[port]; 2271 int err = 0; 2272 u16 pvid; 2273 2274 if (!mv88e6xxx_max_vid(chip)) 2275 return -EOPNOTSUPP; 2276 2277 mv88e6xxx_reg_lock(chip); 2278 2279 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2280 if (err) 2281 goto unlock; 2282 2283 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2284 if (err) 2285 goto unlock; 2286 2287 if (vlan->vid == pvid) { 2288 p->bridge_pvid.valid = false; 2289 2290 err = mv88e6xxx_port_commit_pvid(chip, port); 2291 if (err) 2292 goto unlock; 2293 } 2294 2295 unlock: 2296 mv88e6xxx_reg_unlock(chip); 2297 2298 return err; 2299 } 2300 2301 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2302 const unsigned char *addr, u16 vid) 2303 { 2304 struct mv88e6xxx_chip *chip = ds->priv; 2305 int err; 2306 2307 mv88e6xxx_reg_lock(chip); 2308 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2309 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2310 mv88e6xxx_reg_unlock(chip); 2311 2312 return err; 2313 } 2314 2315 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2316 const unsigned char *addr, u16 vid) 2317 { 2318 struct mv88e6xxx_chip *chip = ds->priv; 2319 int err; 2320 2321 mv88e6xxx_reg_lock(chip); 2322 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2323 mv88e6xxx_reg_unlock(chip); 2324 2325 return err; 2326 } 2327 2328 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2329 u16 fid, u16 vid, int port, 2330 dsa_fdb_dump_cb_t *cb, void *data) 2331 { 2332 struct mv88e6xxx_atu_entry addr; 2333 bool is_static; 2334 int err; 2335 2336 addr.state = 0; 2337 eth_broadcast_addr(addr.mac); 2338 2339 do { 2340 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2341 if (err) 2342 return err; 2343 2344 if (!addr.state) 2345 break; 2346 2347 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2348 continue; 2349 2350 if (!is_unicast_ether_addr(addr.mac)) 2351 continue; 2352 2353 is_static = (addr.state == 2354 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2355 err = cb(addr.mac, vid, is_static, data); 2356 if (err) 2357 return err; 2358 } while (!is_broadcast_ether_addr(addr.mac)); 2359 2360 return err; 2361 } 2362 2363 struct mv88e6xxx_port_db_dump_vlan_ctx { 2364 int port; 2365 dsa_fdb_dump_cb_t *cb; 2366 void *data; 2367 }; 2368 2369 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2370 const struct mv88e6xxx_vtu_entry *entry, 2371 void *_data) 2372 { 2373 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2374 2375 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2376 ctx->port, ctx->cb, ctx->data); 2377 } 2378 2379 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2380 dsa_fdb_dump_cb_t *cb, void *data) 2381 { 2382 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2383 .port = port, 2384 .cb = cb, 2385 .data = data, 2386 }; 2387 u16 fid; 2388 int err; 2389 2390 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2391 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2392 if (err) 2393 return err; 2394 2395 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2396 if (err) 2397 return err; 2398 2399 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2400 } 2401 2402 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2403 dsa_fdb_dump_cb_t *cb, void *data) 2404 { 2405 struct mv88e6xxx_chip *chip = ds->priv; 2406 int err; 2407 2408 mv88e6xxx_reg_lock(chip); 2409 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2410 mv88e6xxx_reg_unlock(chip); 2411 2412 return err; 2413 } 2414 2415 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2416 struct net_device *br) 2417 { 2418 struct dsa_switch *ds = chip->ds; 2419 struct dsa_switch_tree *dst = ds->dst; 2420 struct dsa_port *dp; 2421 int err; 2422 2423 list_for_each_entry(dp, &dst->ports, list) { 2424 if (dp->bridge_dev == br) { 2425 if (dp->ds == ds) { 2426 /* This is a local bridge group member, 2427 * remap its Port VLAN Map. 2428 */ 2429 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2430 if (err) 2431 return err; 2432 } else { 2433 /* This is an external bridge group member, 2434 * remap its cross-chip Port VLAN Table entry. 2435 */ 2436 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2437 dp->index); 2438 if (err) 2439 return err; 2440 } 2441 } 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2448 struct net_device *br) 2449 { 2450 struct mv88e6xxx_chip *chip = ds->priv; 2451 int err; 2452 2453 mv88e6xxx_reg_lock(chip); 2454 2455 err = mv88e6xxx_bridge_map(chip, br); 2456 if (err) 2457 goto unlock; 2458 2459 err = mv88e6xxx_port_commit_pvid(chip, port); 2460 if (err) 2461 goto unlock; 2462 2463 unlock: 2464 mv88e6xxx_reg_unlock(chip); 2465 2466 return err; 2467 } 2468 2469 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2470 struct net_device *br) 2471 { 2472 struct mv88e6xxx_chip *chip = ds->priv; 2473 int err; 2474 2475 mv88e6xxx_reg_lock(chip); 2476 2477 if (mv88e6xxx_bridge_map(chip, br) || 2478 mv88e6xxx_port_vlan_map(chip, port)) 2479 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2480 2481 err = mv88e6xxx_port_commit_pvid(chip, port); 2482 if (err) 2483 dev_err(ds->dev, 2484 "port %d failed to restore standalone pvid: %pe\n", 2485 port, ERR_PTR(err)); 2486 2487 mv88e6xxx_reg_unlock(chip); 2488 } 2489 2490 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2491 int tree_index, int sw_index, 2492 int port, struct net_device *br) 2493 { 2494 struct mv88e6xxx_chip *chip = ds->priv; 2495 int err; 2496 2497 if (tree_index != ds->dst->index) 2498 return 0; 2499 2500 mv88e6xxx_reg_lock(chip); 2501 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2502 mv88e6xxx_reg_unlock(chip); 2503 2504 return err; 2505 } 2506 2507 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2508 int tree_index, int sw_index, 2509 int port, struct net_device *br) 2510 { 2511 struct mv88e6xxx_chip *chip = ds->priv; 2512 2513 if (tree_index != ds->dst->index) 2514 return; 2515 2516 mv88e6xxx_reg_lock(chip); 2517 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2518 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2519 mv88e6xxx_reg_unlock(chip); 2520 } 2521 2522 /* Treat the software bridge as a virtual single-port switch behind the 2523 * CPU and map in the PVT. First dst->last_switch elements are taken by 2524 * physical switches, so start from beyond that range. 2525 */ 2526 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2527 int bridge_num) 2528 { 2529 u8 dev = bridge_num + ds->dst->last_switch + 1; 2530 struct mv88e6xxx_chip *chip = ds->priv; 2531 int err; 2532 2533 mv88e6xxx_reg_lock(chip); 2534 err = mv88e6xxx_pvt_map(chip, dev, 0); 2535 mv88e6xxx_reg_unlock(chip); 2536 2537 return err; 2538 } 2539 2540 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2541 struct net_device *br, 2542 int bridge_num) 2543 { 2544 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2545 } 2546 2547 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2548 struct net_device *br, 2549 int bridge_num) 2550 { 2551 int err; 2552 2553 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2554 if (err) { 2555 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2556 ERR_PTR(err)); 2557 } 2558 } 2559 2560 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2561 { 2562 if (chip->info->ops->reset) 2563 return chip->info->ops->reset(chip); 2564 2565 return 0; 2566 } 2567 2568 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2569 { 2570 struct gpio_desc *gpiod = chip->reset; 2571 2572 /* If there is a GPIO connected to the reset pin, toggle it */ 2573 if (gpiod) { 2574 gpiod_set_value_cansleep(gpiod, 1); 2575 usleep_range(10000, 20000); 2576 gpiod_set_value_cansleep(gpiod, 0); 2577 usleep_range(10000, 20000); 2578 2579 mv88e6xxx_g1_wait_eeprom_done(chip); 2580 } 2581 } 2582 2583 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2584 { 2585 int i, err; 2586 2587 /* Set all ports to the Disabled state */ 2588 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2589 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2590 if (err) 2591 return err; 2592 } 2593 2594 /* Wait for transmit queues to drain, 2595 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2596 */ 2597 usleep_range(2000, 4000); 2598 2599 return 0; 2600 } 2601 2602 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2603 { 2604 int err; 2605 2606 err = mv88e6xxx_disable_ports(chip); 2607 if (err) 2608 return err; 2609 2610 mv88e6xxx_hardware_reset(chip); 2611 2612 return mv88e6xxx_software_reset(chip); 2613 } 2614 2615 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2616 enum mv88e6xxx_frame_mode frame, 2617 enum mv88e6xxx_egress_mode egress, u16 etype) 2618 { 2619 int err; 2620 2621 if (!chip->info->ops->port_set_frame_mode) 2622 return -EOPNOTSUPP; 2623 2624 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2625 if (err) 2626 return err; 2627 2628 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2629 if (err) 2630 return err; 2631 2632 if (chip->info->ops->port_set_ether_type) 2633 return chip->info->ops->port_set_ether_type(chip, port, etype); 2634 2635 return 0; 2636 } 2637 2638 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2639 { 2640 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2641 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2642 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2643 } 2644 2645 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2646 { 2647 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2648 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2649 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2650 } 2651 2652 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2653 { 2654 return mv88e6xxx_set_port_mode(chip, port, 2655 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2656 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2657 ETH_P_EDSA); 2658 } 2659 2660 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2661 { 2662 if (dsa_is_dsa_port(chip->ds, port)) 2663 return mv88e6xxx_set_port_mode_dsa(chip, port); 2664 2665 if (dsa_is_user_port(chip->ds, port)) 2666 return mv88e6xxx_set_port_mode_normal(chip, port); 2667 2668 /* Setup CPU port mode depending on its supported tag format */ 2669 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2670 return mv88e6xxx_set_port_mode_dsa(chip, port); 2671 2672 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2673 return mv88e6xxx_set_port_mode_edsa(chip, port); 2674 2675 return -EINVAL; 2676 } 2677 2678 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2679 { 2680 bool message = dsa_is_dsa_port(chip->ds, port); 2681 2682 return mv88e6xxx_port_set_message_port(chip, port, message); 2683 } 2684 2685 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2686 { 2687 int err; 2688 2689 if (chip->info->ops->port_set_ucast_flood) { 2690 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2691 if (err) 2692 return err; 2693 } 2694 if (chip->info->ops->port_set_mcast_flood) { 2695 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2696 if (err) 2697 return err; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2704 { 2705 struct mv88e6xxx_port *mvp = dev_id; 2706 struct mv88e6xxx_chip *chip = mvp->chip; 2707 irqreturn_t ret = IRQ_NONE; 2708 int port = mvp->port; 2709 int lane; 2710 2711 mv88e6xxx_reg_lock(chip); 2712 lane = mv88e6xxx_serdes_get_lane(chip, port); 2713 if (lane >= 0) 2714 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2715 mv88e6xxx_reg_unlock(chip); 2716 2717 return ret; 2718 } 2719 2720 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2721 int lane) 2722 { 2723 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2724 unsigned int irq; 2725 int err; 2726 2727 /* Nothing to request if this SERDES port has no IRQ */ 2728 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2729 if (!irq) 2730 return 0; 2731 2732 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2733 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2734 2735 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2736 mv88e6xxx_reg_unlock(chip); 2737 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2738 IRQF_ONESHOT, dev_id->serdes_irq_name, 2739 dev_id); 2740 mv88e6xxx_reg_lock(chip); 2741 if (err) 2742 return err; 2743 2744 dev_id->serdes_irq = irq; 2745 2746 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2747 } 2748 2749 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2750 int lane) 2751 { 2752 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2753 unsigned int irq = dev_id->serdes_irq; 2754 int err; 2755 2756 /* Nothing to free if no IRQ has been requested */ 2757 if (!irq) 2758 return 0; 2759 2760 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2761 2762 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2763 mv88e6xxx_reg_unlock(chip); 2764 free_irq(irq, dev_id); 2765 mv88e6xxx_reg_lock(chip); 2766 2767 dev_id->serdes_irq = 0; 2768 2769 return err; 2770 } 2771 2772 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2773 bool on) 2774 { 2775 int lane; 2776 int err; 2777 2778 lane = mv88e6xxx_serdes_get_lane(chip, port); 2779 if (lane < 0) 2780 return 0; 2781 2782 if (on) { 2783 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2784 if (err) 2785 return err; 2786 2787 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2788 } else { 2789 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2790 if (err) 2791 return err; 2792 2793 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2794 } 2795 2796 return err; 2797 } 2798 2799 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2800 enum mv88e6xxx_egress_direction direction, 2801 int port) 2802 { 2803 int err; 2804 2805 if (!chip->info->ops->set_egress_port) 2806 return -EOPNOTSUPP; 2807 2808 err = chip->info->ops->set_egress_port(chip, direction, port); 2809 if (err) 2810 return err; 2811 2812 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2813 chip->ingress_dest_port = port; 2814 else 2815 chip->egress_dest_port = port; 2816 2817 return 0; 2818 } 2819 2820 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2821 { 2822 struct dsa_switch *ds = chip->ds; 2823 int upstream_port; 2824 int err; 2825 2826 upstream_port = dsa_upstream_port(ds, port); 2827 if (chip->info->ops->port_set_upstream_port) { 2828 err = chip->info->ops->port_set_upstream_port(chip, port, 2829 upstream_port); 2830 if (err) 2831 return err; 2832 } 2833 2834 if (port == upstream_port) { 2835 if (chip->info->ops->set_cpu_port) { 2836 err = chip->info->ops->set_cpu_port(chip, 2837 upstream_port); 2838 if (err) 2839 return err; 2840 } 2841 2842 err = mv88e6xxx_set_egress_port(chip, 2843 MV88E6XXX_EGRESS_DIR_INGRESS, 2844 upstream_port); 2845 if (err && err != -EOPNOTSUPP) 2846 return err; 2847 2848 err = mv88e6xxx_set_egress_port(chip, 2849 MV88E6XXX_EGRESS_DIR_EGRESS, 2850 upstream_port); 2851 if (err && err != -EOPNOTSUPP) 2852 return err; 2853 } 2854 2855 return 0; 2856 } 2857 2858 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2859 { 2860 struct dsa_switch *ds = chip->ds; 2861 int err; 2862 u16 reg; 2863 2864 chip->ports[port].chip = chip; 2865 chip->ports[port].port = port; 2866 2867 /* MAC Forcing register: don't force link, speed, duplex or flow control 2868 * state to any particular values on physical ports, but force the CPU 2869 * port and all DSA ports to their maximum bandwidth and full duplex. 2870 */ 2871 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2872 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2873 SPEED_MAX, DUPLEX_FULL, 2874 PAUSE_OFF, 2875 PHY_INTERFACE_MODE_NA); 2876 else 2877 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2878 SPEED_UNFORCED, DUPLEX_UNFORCED, 2879 PAUSE_ON, 2880 PHY_INTERFACE_MODE_NA); 2881 if (err) 2882 return err; 2883 2884 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2885 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2886 * tunneling, determine priority by looking at 802.1p and IP 2887 * priority fields (IP prio has precedence), and set STP state 2888 * to Forwarding. 2889 * 2890 * If this is the CPU link, use DSA or EDSA tagging depending 2891 * on which tagging mode was configured. 2892 * 2893 * If this is a link to another switch, use DSA tagging mode. 2894 * 2895 * If this is the upstream port for this switch, enable 2896 * forwarding of unknown unicasts and multicasts. 2897 */ 2898 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2899 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2900 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2901 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2902 if (err) 2903 return err; 2904 2905 err = mv88e6xxx_setup_port_mode(chip, port); 2906 if (err) 2907 return err; 2908 2909 err = mv88e6xxx_setup_egress_floods(chip, port); 2910 if (err) 2911 return err; 2912 2913 /* Port Control 2: don't force a good FCS, set the MTU size to 2914 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2915 * untagged frames on this port, do a destination address lookup on all 2916 * received packets as usual, disable ARP mirroring and don't send a 2917 * copy of all transmitted/received frames on this port to the CPU. 2918 */ 2919 err = mv88e6xxx_port_set_map_da(chip, port); 2920 if (err) 2921 return err; 2922 2923 err = mv88e6xxx_setup_upstream_port(chip, port); 2924 if (err) 2925 return err; 2926 2927 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2928 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2929 if (err) 2930 return err; 2931 2932 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2933 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2934 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2935 * as the private PVID on ports under a VLAN-unaware bridge. 2936 * Shared (DSA and CPU) ports must also be members of it, to translate 2937 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2938 * relying on their port default FID. 2939 */ 2940 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2941 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2942 false); 2943 if (err) 2944 return err; 2945 2946 if (chip->info->ops->port_set_jumbo_size) { 2947 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2948 if (err) 2949 return err; 2950 } 2951 2952 /* Port Association Vector: disable automatic address learning 2953 * on all user ports since they start out in standalone 2954 * mode. When joining a bridge, learning will be configured to 2955 * match the bridge port settings. Enable learning on all 2956 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2957 * learning process. 2958 * 2959 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2960 * and RefreshLocked. I.e. setup standard automatic learning. 2961 */ 2962 if (dsa_is_user_port(ds, port)) 2963 reg = 0; 2964 else 2965 reg = 1 << port; 2966 2967 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2968 reg); 2969 if (err) 2970 return err; 2971 2972 /* Egress rate control 2: disable egress rate control. */ 2973 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2974 0x0000); 2975 if (err) 2976 return err; 2977 2978 if (chip->info->ops->port_pause_limit) { 2979 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2980 if (err) 2981 return err; 2982 } 2983 2984 if (chip->info->ops->port_disable_learn_limit) { 2985 err = chip->info->ops->port_disable_learn_limit(chip, port); 2986 if (err) 2987 return err; 2988 } 2989 2990 if (chip->info->ops->port_disable_pri_override) { 2991 err = chip->info->ops->port_disable_pri_override(chip, port); 2992 if (err) 2993 return err; 2994 } 2995 2996 if (chip->info->ops->port_tag_remap) { 2997 err = chip->info->ops->port_tag_remap(chip, port); 2998 if (err) 2999 return err; 3000 } 3001 3002 if (chip->info->ops->port_egress_rate_limiting) { 3003 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3004 if (err) 3005 return err; 3006 } 3007 3008 if (chip->info->ops->port_setup_message_port) { 3009 err = chip->info->ops->port_setup_message_port(chip, port); 3010 if (err) 3011 return err; 3012 } 3013 3014 /* Port based VLAN map: give each port the same default address 3015 * database, and allow bidirectional communication between the 3016 * CPU and DSA port(s), and the other ports. 3017 */ 3018 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3019 if (err) 3020 return err; 3021 3022 err = mv88e6xxx_port_vlan_map(chip, port); 3023 if (err) 3024 return err; 3025 3026 /* Default VLAN ID and priority: don't set a default VLAN 3027 * ID, and set the default packet priority to zero. 3028 */ 3029 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3030 } 3031 3032 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3033 { 3034 struct mv88e6xxx_chip *chip = ds->priv; 3035 3036 if (chip->info->ops->port_set_jumbo_size) 3037 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3038 else if (chip->info->ops->set_max_frame_size) 3039 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3040 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3041 } 3042 3043 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3044 { 3045 struct mv88e6xxx_chip *chip = ds->priv; 3046 int ret = 0; 3047 3048 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3049 new_mtu += EDSA_HLEN; 3050 3051 mv88e6xxx_reg_lock(chip); 3052 if (chip->info->ops->port_set_jumbo_size) 3053 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3054 else if (chip->info->ops->set_max_frame_size) 3055 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3056 else 3057 if (new_mtu > 1522) 3058 ret = -EINVAL; 3059 mv88e6xxx_reg_unlock(chip); 3060 3061 return ret; 3062 } 3063 3064 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3065 struct phy_device *phydev) 3066 { 3067 struct mv88e6xxx_chip *chip = ds->priv; 3068 int err; 3069 3070 mv88e6xxx_reg_lock(chip); 3071 err = mv88e6xxx_serdes_power(chip, port, true); 3072 mv88e6xxx_reg_unlock(chip); 3073 3074 return err; 3075 } 3076 3077 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3078 { 3079 struct mv88e6xxx_chip *chip = ds->priv; 3080 3081 mv88e6xxx_reg_lock(chip); 3082 if (mv88e6xxx_serdes_power(chip, port, false)) 3083 dev_err(chip->dev, "failed to power off SERDES\n"); 3084 mv88e6xxx_reg_unlock(chip); 3085 } 3086 3087 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3088 unsigned int ageing_time) 3089 { 3090 struct mv88e6xxx_chip *chip = ds->priv; 3091 int err; 3092 3093 mv88e6xxx_reg_lock(chip); 3094 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3095 mv88e6xxx_reg_unlock(chip); 3096 3097 return err; 3098 } 3099 3100 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3101 { 3102 int err; 3103 3104 /* Initialize the statistics unit */ 3105 if (chip->info->ops->stats_set_histogram) { 3106 err = chip->info->ops->stats_set_histogram(chip); 3107 if (err) 3108 return err; 3109 } 3110 3111 return mv88e6xxx_g1_stats_clear(chip); 3112 } 3113 3114 /* Check if the errata has already been applied. */ 3115 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3116 { 3117 int port; 3118 int err; 3119 u16 val; 3120 3121 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3122 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3123 if (err) { 3124 dev_err(chip->dev, 3125 "Error reading hidden register: %d\n", err); 3126 return false; 3127 } 3128 if (val != 0x01c0) 3129 return false; 3130 } 3131 3132 return true; 3133 } 3134 3135 /* The 6390 copper ports have an errata which require poking magic 3136 * values into undocumented hidden registers and then performing a 3137 * software reset. 3138 */ 3139 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3140 { 3141 int port; 3142 int err; 3143 3144 if (mv88e6390_setup_errata_applied(chip)) 3145 return 0; 3146 3147 /* Set the ports into blocking mode */ 3148 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3149 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3150 if (err) 3151 return err; 3152 } 3153 3154 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3155 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3156 if (err) 3157 return err; 3158 } 3159 3160 return mv88e6xxx_software_reset(chip); 3161 } 3162 3163 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3164 { 3165 mv88e6xxx_teardown_devlink_params(ds); 3166 dsa_devlink_resources_unregister(ds); 3167 mv88e6xxx_teardown_devlink_regions_global(ds); 3168 } 3169 3170 static int mv88e6xxx_setup(struct dsa_switch *ds) 3171 { 3172 struct mv88e6xxx_chip *chip = ds->priv; 3173 u8 cmode; 3174 int err; 3175 int i; 3176 3177 chip->ds = ds; 3178 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3179 3180 /* Since virtual bridges are mapped in the PVT, the number we support 3181 * depends on the physical switch topology. We need to let DSA figure 3182 * that out and therefore we cannot set this at dsa_register_switch() 3183 * time. 3184 */ 3185 if (mv88e6xxx_has_pvt(chip)) 3186 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3187 ds->dst->last_switch - 1; 3188 3189 mv88e6xxx_reg_lock(chip); 3190 3191 if (chip->info->ops->setup_errata) { 3192 err = chip->info->ops->setup_errata(chip); 3193 if (err) 3194 goto unlock; 3195 } 3196 3197 /* Cache the cmode of each port. */ 3198 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3199 if (chip->info->ops->port_get_cmode) { 3200 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3201 if (err) 3202 goto unlock; 3203 3204 chip->ports[i].cmode = cmode; 3205 } 3206 } 3207 3208 err = mv88e6xxx_vtu_setup(chip); 3209 if (err) 3210 goto unlock; 3211 3212 /* Setup Switch Port Registers */ 3213 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3214 if (dsa_is_unused_port(ds, i)) 3215 continue; 3216 3217 /* Prevent the use of an invalid port. */ 3218 if (mv88e6xxx_is_invalid_port(chip, i)) { 3219 dev_err(chip->dev, "port %d is invalid\n", i); 3220 err = -EINVAL; 3221 goto unlock; 3222 } 3223 3224 err = mv88e6xxx_setup_port(chip, i); 3225 if (err) 3226 goto unlock; 3227 } 3228 3229 err = mv88e6xxx_irl_setup(chip); 3230 if (err) 3231 goto unlock; 3232 3233 err = mv88e6xxx_mac_setup(chip); 3234 if (err) 3235 goto unlock; 3236 3237 err = mv88e6xxx_phy_setup(chip); 3238 if (err) 3239 goto unlock; 3240 3241 err = mv88e6xxx_pvt_setup(chip); 3242 if (err) 3243 goto unlock; 3244 3245 err = mv88e6xxx_atu_setup(chip); 3246 if (err) 3247 goto unlock; 3248 3249 err = mv88e6xxx_broadcast_setup(chip, 0); 3250 if (err) 3251 goto unlock; 3252 3253 err = mv88e6xxx_pot_setup(chip); 3254 if (err) 3255 goto unlock; 3256 3257 err = mv88e6xxx_rmu_setup(chip); 3258 if (err) 3259 goto unlock; 3260 3261 err = mv88e6xxx_rsvd2cpu_setup(chip); 3262 if (err) 3263 goto unlock; 3264 3265 err = mv88e6xxx_trunk_setup(chip); 3266 if (err) 3267 goto unlock; 3268 3269 err = mv88e6xxx_devmap_setup(chip); 3270 if (err) 3271 goto unlock; 3272 3273 err = mv88e6xxx_pri_setup(chip); 3274 if (err) 3275 goto unlock; 3276 3277 /* Setup PTP Hardware Clock and timestamping */ 3278 if (chip->info->ptp_support) { 3279 err = mv88e6xxx_ptp_setup(chip); 3280 if (err) 3281 goto unlock; 3282 3283 err = mv88e6xxx_hwtstamp_setup(chip); 3284 if (err) 3285 goto unlock; 3286 } 3287 3288 err = mv88e6xxx_stats_setup(chip); 3289 if (err) 3290 goto unlock; 3291 3292 unlock: 3293 mv88e6xxx_reg_unlock(chip); 3294 3295 if (err) 3296 return err; 3297 3298 /* Have to be called without holding the register lock, since 3299 * they take the devlink lock, and we later take the locks in 3300 * the reverse order when getting/setting parameters or 3301 * resource occupancy. 3302 */ 3303 err = mv88e6xxx_setup_devlink_resources(ds); 3304 if (err) 3305 return err; 3306 3307 err = mv88e6xxx_setup_devlink_params(ds); 3308 if (err) 3309 goto out_resources; 3310 3311 err = mv88e6xxx_setup_devlink_regions_global(ds); 3312 if (err) 3313 goto out_params; 3314 3315 return 0; 3316 3317 out_params: 3318 mv88e6xxx_teardown_devlink_params(ds); 3319 out_resources: 3320 dsa_devlink_resources_unregister(ds); 3321 3322 return err; 3323 } 3324 3325 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3326 { 3327 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3328 } 3329 3330 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3331 { 3332 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3333 } 3334 3335 /* prod_id for switch families which do not have a PHY model number */ 3336 static const u16 family_prod_id_table[] = { 3337 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3338 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3339 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3340 }; 3341 3342 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3343 { 3344 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3345 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3346 u16 prod_id; 3347 u16 val; 3348 int err; 3349 3350 if (!chip->info->ops->phy_read) 3351 return -EOPNOTSUPP; 3352 3353 mv88e6xxx_reg_lock(chip); 3354 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3355 mv88e6xxx_reg_unlock(chip); 3356 3357 /* Some internal PHYs don't have a model number. */ 3358 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3359 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3360 prod_id = family_prod_id_table[chip->info->family]; 3361 if (prod_id) 3362 val |= prod_id >> 4; 3363 } 3364 3365 return err ? err : val; 3366 } 3367 3368 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3369 { 3370 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3371 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3372 int err; 3373 3374 if (!chip->info->ops->phy_write) 3375 return -EOPNOTSUPP; 3376 3377 mv88e6xxx_reg_lock(chip); 3378 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3379 mv88e6xxx_reg_unlock(chip); 3380 3381 return err; 3382 } 3383 3384 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3385 struct device_node *np, 3386 bool external) 3387 { 3388 static int index; 3389 struct mv88e6xxx_mdio_bus *mdio_bus; 3390 struct mii_bus *bus; 3391 int err; 3392 3393 if (external) { 3394 mv88e6xxx_reg_lock(chip); 3395 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3396 mv88e6xxx_reg_unlock(chip); 3397 3398 if (err) 3399 return err; 3400 } 3401 3402 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3403 if (!bus) 3404 return -ENOMEM; 3405 3406 mdio_bus = bus->priv; 3407 mdio_bus->bus = bus; 3408 mdio_bus->chip = chip; 3409 INIT_LIST_HEAD(&mdio_bus->list); 3410 mdio_bus->external = external; 3411 3412 if (np) { 3413 bus->name = np->full_name; 3414 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3415 } else { 3416 bus->name = "mv88e6xxx SMI"; 3417 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3418 } 3419 3420 bus->read = mv88e6xxx_mdio_read; 3421 bus->write = mv88e6xxx_mdio_write; 3422 bus->parent = chip->dev; 3423 3424 if (!external) { 3425 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3426 if (err) 3427 return err; 3428 } 3429 3430 err = of_mdiobus_register(bus, np); 3431 if (err) { 3432 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3433 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3434 return err; 3435 } 3436 3437 if (external) 3438 list_add_tail(&mdio_bus->list, &chip->mdios); 3439 else 3440 list_add(&mdio_bus->list, &chip->mdios); 3441 3442 return 0; 3443 } 3444 3445 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3446 3447 { 3448 struct mv88e6xxx_mdio_bus *mdio_bus; 3449 struct mii_bus *bus; 3450 3451 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3452 bus = mdio_bus->bus; 3453 3454 if (!mdio_bus->external) 3455 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3456 3457 mdiobus_unregister(bus); 3458 } 3459 } 3460 3461 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3462 struct device_node *np) 3463 { 3464 struct device_node *child; 3465 int err; 3466 3467 /* Always register one mdio bus for the internal/default mdio 3468 * bus. This maybe represented in the device tree, but is 3469 * optional. 3470 */ 3471 child = of_get_child_by_name(np, "mdio"); 3472 err = mv88e6xxx_mdio_register(chip, child, false); 3473 if (err) 3474 return err; 3475 3476 /* Walk the device tree, and see if there are any other nodes 3477 * which say they are compatible with the external mdio 3478 * bus. 3479 */ 3480 for_each_available_child_of_node(np, child) { 3481 if (of_device_is_compatible( 3482 child, "marvell,mv88e6xxx-mdio-external")) { 3483 err = mv88e6xxx_mdio_register(chip, child, true); 3484 if (err) { 3485 mv88e6xxx_mdios_unregister(chip); 3486 of_node_put(child); 3487 return err; 3488 } 3489 } 3490 } 3491 3492 return 0; 3493 } 3494 3495 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3496 { 3497 struct mv88e6xxx_chip *chip = ds->priv; 3498 3499 return chip->eeprom_len; 3500 } 3501 3502 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3503 struct ethtool_eeprom *eeprom, u8 *data) 3504 { 3505 struct mv88e6xxx_chip *chip = ds->priv; 3506 int err; 3507 3508 if (!chip->info->ops->get_eeprom) 3509 return -EOPNOTSUPP; 3510 3511 mv88e6xxx_reg_lock(chip); 3512 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3513 mv88e6xxx_reg_unlock(chip); 3514 3515 if (err) 3516 return err; 3517 3518 eeprom->magic = 0xc3ec4951; 3519 3520 return 0; 3521 } 3522 3523 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3524 struct ethtool_eeprom *eeprom, u8 *data) 3525 { 3526 struct mv88e6xxx_chip *chip = ds->priv; 3527 int err; 3528 3529 if (!chip->info->ops->set_eeprom) 3530 return -EOPNOTSUPP; 3531 3532 if (eeprom->magic != 0xc3ec4951) 3533 return -EINVAL; 3534 3535 mv88e6xxx_reg_lock(chip); 3536 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3537 mv88e6xxx_reg_unlock(chip); 3538 3539 return err; 3540 } 3541 3542 static const struct mv88e6xxx_ops mv88e6085_ops = { 3543 /* MV88E6XXX_FAMILY_6097 */ 3544 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3545 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3546 .irl_init_all = mv88e6352_g2_irl_init_all, 3547 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3548 .phy_read = mv88e6185_phy_ppu_read, 3549 .phy_write = mv88e6185_phy_ppu_write, 3550 .port_set_link = mv88e6xxx_port_set_link, 3551 .port_sync_link = mv88e6xxx_port_sync_link, 3552 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3553 .port_tag_remap = mv88e6095_port_tag_remap, 3554 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3555 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3556 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3557 .port_set_ether_type = mv88e6351_port_set_ether_type, 3558 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3559 .port_pause_limit = mv88e6097_port_pause_limit, 3560 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3561 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3562 .port_get_cmode = mv88e6185_port_get_cmode, 3563 .port_setup_message_port = mv88e6xxx_setup_message_port, 3564 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3565 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3566 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3567 .stats_get_strings = mv88e6095_stats_get_strings, 3568 .stats_get_stats = mv88e6095_stats_get_stats, 3569 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3570 .set_egress_port = mv88e6095_g1_set_egress_port, 3571 .watchdog_ops = &mv88e6097_watchdog_ops, 3572 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3573 .pot_clear = mv88e6xxx_g2_pot_clear, 3574 .ppu_enable = mv88e6185_g1_ppu_enable, 3575 .ppu_disable = mv88e6185_g1_ppu_disable, 3576 .reset = mv88e6185_g1_reset, 3577 .rmu_disable = mv88e6085_g1_rmu_disable, 3578 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3579 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3580 .phylink_validate = mv88e6185_phylink_validate, 3581 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3582 }; 3583 3584 static const struct mv88e6xxx_ops mv88e6095_ops = { 3585 /* MV88E6XXX_FAMILY_6095 */ 3586 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3587 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3588 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3589 .phy_read = mv88e6185_phy_ppu_read, 3590 .phy_write = mv88e6185_phy_ppu_write, 3591 .port_set_link = mv88e6xxx_port_set_link, 3592 .port_sync_link = mv88e6185_port_sync_link, 3593 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3594 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3595 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3596 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3597 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3598 .port_get_cmode = mv88e6185_port_get_cmode, 3599 .port_setup_message_port = mv88e6xxx_setup_message_port, 3600 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3601 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3602 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3603 .stats_get_strings = mv88e6095_stats_get_strings, 3604 .stats_get_stats = mv88e6095_stats_get_stats, 3605 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3606 .serdes_power = mv88e6185_serdes_power, 3607 .serdes_get_lane = mv88e6185_serdes_get_lane, 3608 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3609 .ppu_enable = mv88e6185_g1_ppu_enable, 3610 .ppu_disable = mv88e6185_g1_ppu_disable, 3611 .reset = mv88e6185_g1_reset, 3612 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3613 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3614 .phylink_validate = mv88e6185_phylink_validate, 3615 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3616 }; 3617 3618 static const struct mv88e6xxx_ops mv88e6097_ops = { 3619 /* MV88E6XXX_FAMILY_6097 */ 3620 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3621 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3622 .irl_init_all = mv88e6352_g2_irl_init_all, 3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3624 .phy_read = mv88e6xxx_g2_smi_phy_read, 3625 .phy_write = mv88e6xxx_g2_smi_phy_write, 3626 .port_set_link = mv88e6xxx_port_set_link, 3627 .port_sync_link = mv88e6185_port_sync_link, 3628 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3629 .port_tag_remap = mv88e6095_port_tag_remap, 3630 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3633 .port_set_ether_type = mv88e6351_port_set_ether_type, 3634 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3635 .port_pause_limit = mv88e6097_port_pause_limit, 3636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3638 .port_get_cmode = mv88e6185_port_get_cmode, 3639 .port_setup_message_port = mv88e6xxx_setup_message_port, 3640 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3643 .stats_get_strings = mv88e6095_stats_get_strings, 3644 .stats_get_stats = mv88e6095_stats_get_stats, 3645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3646 .set_egress_port = mv88e6095_g1_set_egress_port, 3647 .watchdog_ops = &mv88e6097_watchdog_ops, 3648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3649 .serdes_power = mv88e6185_serdes_power, 3650 .serdes_get_lane = mv88e6185_serdes_get_lane, 3651 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3652 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3653 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3654 .serdes_irq_status = mv88e6097_serdes_irq_status, 3655 .pot_clear = mv88e6xxx_g2_pot_clear, 3656 .reset = mv88e6352_g1_reset, 3657 .rmu_disable = mv88e6085_g1_rmu_disable, 3658 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3660 .phylink_validate = mv88e6185_phylink_validate, 3661 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3662 }; 3663 3664 static const struct mv88e6xxx_ops mv88e6123_ops = { 3665 /* MV88E6XXX_FAMILY_6165 */ 3666 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3667 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3668 .irl_init_all = mv88e6352_g2_irl_init_all, 3669 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3670 .phy_read = mv88e6xxx_g2_smi_phy_read, 3671 .phy_write = mv88e6xxx_g2_smi_phy_write, 3672 .port_set_link = mv88e6xxx_port_set_link, 3673 .port_sync_link = mv88e6xxx_port_sync_link, 3674 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3675 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3676 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3677 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3680 .port_get_cmode = mv88e6185_port_get_cmode, 3681 .port_setup_message_port = mv88e6xxx_setup_message_port, 3682 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3683 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3684 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3685 .stats_get_strings = mv88e6095_stats_get_strings, 3686 .stats_get_stats = mv88e6095_stats_get_stats, 3687 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3688 .set_egress_port = mv88e6095_g1_set_egress_port, 3689 .watchdog_ops = &mv88e6097_watchdog_ops, 3690 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3691 .pot_clear = mv88e6xxx_g2_pot_clear, 3692 .reset = mv88e6352_g1_reset, 3693 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3694 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3695 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3697 .phylink_validate = mv88e6185_phylink_validate, 3698 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3699 }; 3700 3701 static const struct mv88e6xxx_ops mv88e6131_ops = { 3702 /* MV88E6XXX_FAMILY_6185 */ 3703 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3704 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3705 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3706 .phy_read = mv88e6185_phy_ppu_read, 3707 .phy_write = mv88e6185_phy_ppu_write, 3708 .port_set_link = mv88e6xxx_port_set_link, 3709 .port_sync_link = mv88e6xxx_port_sync_link, 3710 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3711 .port_tag_remap = mv88e6095_port_tag_remap, 3712 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3713 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3714 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3715 .port_set_ether_type = mv88e6351_port_set_ether_type, 3716 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3717 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3718 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3719 .port_pause_limit = mv88e6097_port_pause_limit, 3720 .port_set_pause = mv88e6185_port_set_pause, 3721 .port_get_cmode = mv88e6185_port_get_cmode, 3722 .port_setup_message_port = mv88e6xxx_setup_message_port, 3723 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3724 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3725 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3726 .stats_get_strings = mv88e6095_stats_get_strings, 3727 .stats_get_stats = mv88e6095_stats_get_stats, 3728 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3729 .set_egress_port = mv88e6095_g1_set_egress_port, 3730 .watchdog_ops = &mv88e6097_watchdog_ops, 3731 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3732 .ppu_enable = mv88e6185_g1_ppu_enable, 3733 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3734 .ppu_disable = mv88e6185_g1_ppu_disable, 3735 .reset = mv88e6185_g1_reset, 3736 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3737 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3738 .phylink_validate = mv88e6185_phylink_validate, 3739 }; 3740 3741 static const struct mv88e6xxx_ops mv88e6141_ops = { 3742 /* MV88E6XXX_FAMILY_6341 */ 3743 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3744 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3745 .irl_init_all = mv88e6352_g2_irl_init_all, 3746 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3747 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3749 .phy_read = mv88e6xxx_g2_smi_phy_read, 3750 .phy_write = mv88e6xxx_g2_smi_phy_write, 3751 .port_set_link = mv88e6xxx_port_set_link, 3752 .port_sync_link = mv88e6xxx_port_sync_link, 3753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3754 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3755 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3756 .port_tag_remap = mv88e6095_port_tag_remap, 3757 .port_set_policy = mv88e6352_port_set_policy, 3758 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3759 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3760 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3761 .port_set_ether_type = mv88e6351_port_set_ether_type, 3762 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3763 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3764 .port_pause_limit = mv88e6097_port_pause_limit, 3765 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3766 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3767 .port_get_cmode = mv88e6352_port_get_cmode, 3768 .port_set_cmode = mv88e6341_port_set_cmode, 3769 .port_setup_message_port = mv88e6xxx_setup_message_port, 3770 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3771 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3772 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3773 .stats_get_strings = mv88e6320_stats_get_strings, 3774 .stats_get_stats = mv88e6390_stats_get_stats, 3775 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3776 .set_egress_port = mv88e6390_g1_set_egress_port, 3777 .watchdog_ops = &mv88e6390_watchdog_ops, 3778 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3779 .pot_clear = mv88e6xxx_g2_pot_clear, 3780 .reset = mv88e6352_g1_reset, 3781 .rmu_disable = mv88e6390_g1_rmu_disable, 3782 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3783 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3784 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3785 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3786 .serdes_power = mv88e6390_serdes_power, 3787 .serdes_get_lane = mv88e6341_serdes_get_lane, 3788 /* Check status register pause & lpa register */ 3789 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3790 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3791 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3792 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3793 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3794 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3795 .serdes_irq_status = mv88e6390_serdes_irq_status, 3796 .gpio_ops = &mv88e6352_gpio_ops, 3797 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3798 .serdes_get_strings = mv88e6390_serdes_get_strings, 3799 .serdes_get_stats = mv88e6390_serdes_get_stats, 3800 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3801 .serdes_get_regs = mv88e6390_serdes_get_regs, 3802 .phylink_validate = mv88e6341_phylink_validate, 3803 }; 3804 3805 static const struct mv88e6xxx_ops mv88e6161_ops = { 3806 /* MV88E6XXX_FAMILY_6165 */ 3807 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3808 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3809 .irl_init_all = mv88e6352_g2_irl_init_all, 3810 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3811 .phy_read = mv88e6xxx_g2_smi_phy_read, 3812 .phy_write = mv88e6xxx_g2_smi_phy_write, 3813 .port_set_link = mv88e6xxx_port_set_link, 3814 .port_sync_link = mv88e6xxx_port_sync_link, 3815 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3816 .port_tag_remap = mv88e6095_port_tag_remap, 3817 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3818 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3819 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3820 .port_set_ether_type = mv88e6351_port_set_ether_type, 3821 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3822 .port_pause_limit = mv88e6097_port_pause_limit, 3823 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3824 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3825 .port_get_cmode = mv88e6185_port_get_cmode, 3826 .port_setup_message_port = mv88e6xxx_setup_message_port, 3827 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3828 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3829 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3830 .stats_get_strings = mv88e6095_stats_get_strings, 3831 .stats_get_stats = mv88e6095_stats_get_stats, 3832 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3833 .set_egress_port = mv88e6095_g1_set_egress_port, 3834 .watchdog_ops = &mv88e6097_watchdog_ops, 3835 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3836 .pot_clear = mv88e6xxx_g2_pot_clear, 3837 .reset = mv88e6352_g1_reset, 3838 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3839 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3840 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3841 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3842 .avb_ops = &mv88e6165_avb_ops, 3843 .ptp_ops = &mv88e6165_ptp_ops, 3844 .phylink_validate = mv88e6185_phylink_validate, 3845 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3846 }; 3847 3848 static const struct mv88e6xxx_ops mv88e6165_ops = { 3849 /* MV88E6XXX_FAMILY_6165 */ 3850 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3851 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3852 .irl_init_all = mv88e6352_g2_irl_init_all, 3853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3854 .phy_read = mv88e6165_phy_read, 3855 .phy_write = mv88e6165_phy_write, 3856 .port_set_link = mv88e6xxx_port_set_link, 3857 .port_sync_link = mv88e6xxx_port_sync_link, 3858 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3859 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3860 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3861 .port_get_cmode = mv88e6185_port_get_cmode, 3862 .port_setup_message_port = mv88e6xxx_setup_message_port, 3863 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3864 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3865 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3866 .stats_get_strings = mv88e6095_stats_get_strings, 3867 .stats_get_stats = mv88e6095_stats_get_stats, 3868 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3869 .set_egress_port = mv88e6095_g1_set_egress_port, 3870 .watchdog_ops = &mv88e6097_watchdog_ops, 3871 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3872 .pot_clear = mv88e6xxx_g2_pot_clear, 3873 .reset = mv88e6352_g1_reset, 3874 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3875 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3876 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3877 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3878 .avb_ops = &mv88e6165_avb_ops, 3879 .ptp_ops = &mv88e6165_ptp_ops, 3880 .phylink_validate = mv88e6185_phylink_validate, 3881 }; 3882 3883 static const struct mv88e6xxx_ops mv88e6171_ops = { 3884 /* MV88E6XXX_FAMILY_6351 */ 3885 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3886 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3887 .irl_init_all = mv88e6352_g2_irl_init_all, 3888 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3889 .phy_read = mv88e6xxx_g2_smi_phy_read, 3890 .phy_write = mv88e6xxx_g2_smi_phy_write, 3891 .port_set_link = mv88e6xxx_port_set_link, 3892 .port_sync_link = mv88e6xxx_port_sync_link, 3893 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3894 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3895 .port_tag_remap = mv88e6095_port_tag_remap, 3896 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3897 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3898 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3899 .port_set_ether_type = mv88e6351_port_set_ether_type, 3900 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3901 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3902 .port_pause_limit = mv88e6097_port_pause_limit, 3903 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3904 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3905 .port_get_cmode = mv88e6352_port_get_cmode, 3906 .port_setup_message_port = mv88e6xxx_setup_message_port, 3907 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3908 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3909 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3910 .stats_get_strings = mv88e6095_stats_get_strings, 3911 .stats_get_stats = mv88e6095_stats_get_stats, 3912 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3913 .set_egress_port = mv88e6095_g1_set_egress_port, 3914 .watchdog_ops = &mv88e6097_watchdog_ops, 3915 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3916 .pot_clear = mv88e6xxx_g2_pot_clear, 3917 .reset = mv88e6352_g1_reset, 3918 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3919 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3920 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3921 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3922 .phylink_validate = mv88e6185_phylink_validate, 3923 }; 3924 3925 static const struct mv88e6xxx_ops mv88e6172_ops = { 3926 /* MV88E6XXX_FAMILY_6352 */ 3927 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3928 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3929 .irl_init_all = mv88e6352_g2_irl_init_all, 3930 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3931 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3932 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3933 .phy_read = mv88e6xxx_g2_smi_phy_read, 3934 .phy_write = mv88e6xxx_g2_smi_phy_write, 3935 .port_set_link = mv88e6xxx_port_set_link, 3936 .port_sync_link = mv88e6xxx_port_sync_link, 3937 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3938 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3939 .port_tag_remap = mv88e6095_port_tag_remap, 3940 .port_set_policy = mv88e6352_port_set_policy, 3941 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3942 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3943 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3944 .port_set_ether_type = mv88e6351_port_set_ether_type, 3945 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3946 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3947 .port_pause_limit = mv88e6097_port_pause_limit, 3948 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3949 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3950 .port_get_cmode = mv88e6352_port_get_cmode, 3951 .port_setup_message_port = mv88e6xxx_setup_message_port, 3952 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3953 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3954 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3955 .stats_get_strings = mv88e6095_stats_get_strings, 3956 .stats_get_stats = mv88e6095_stats_get_stats, 3957 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3958 .set_egress_port = mv88e6095_g1_set_egress_port, 3959 .watchdog_ops = &mv88e6097_watchdog_ops, 3960 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3961 .pot_clear = mv88e6xxx_g2_pot_clear, 3962 .reset = mv88e6352_g1_reset, 3963 .rmu_disable = mv88e6352_g1_rmu_disable, 3964 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3965 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3966 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3967 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3968 .serdes_get_lane = mv88e6352_serdes_get_lane, 3969 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3970 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3971 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3972 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3973 .serdes_power = mv88e6352_serdes_power, 3974 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3975 .serdes_get_regs = mv88e6352_serdes_get_regs, 3976 .gpio_ops = &mv88e6352_gpio_ops, 3977 .phylink_validate = mv88e6352_phylink_validate, 3978 }; 3979 3980 static const struct mv88e6xxx_ops mv88e6175_ops = { 3981 /* MV88E6XXX_FAMILY_6351 */ 3982 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3983 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3984 .irl_init_all = mv88e6352_g2_irl_init_all, 3985 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3986 .phy_read = mv88e6xxx_g2_smi_phy_read, 3987 .phy_write = mv88e6xxx_g2_smi_phy_write, 3988 .port_set_link = mv88e6xxx_port_set_link, 3989 .port_sync_link = mv88e6xxx_port_sync_link, 3990 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3991 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3992 .port_tag_remap = mv88e6095_port_tag_remap, 3993 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3994 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3995 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3996 .port_set_ether_type = mv88e6351_port_set_ether_type, 3997 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3998 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3999 .port_pause_limit = mv88e6097_port_pause_limit, 4000 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4001 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4002 .port_get_cmode = mv88e6352_port_get_cmode, 4003 .port_setup_message_port = mv88e6xxx_setup_message_port, 4004 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4005 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4006 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4007 .stats_get_strings = mv88e6095_stats_get_strings, 4008 .stats_get_stats = mv88e6095_stats_get_stats, 4009 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4010 .set_egress_port = mv88e6095_g1_set_egress_port, 4011 .watchdog_ops = &mv88e6097_watchdog_ops, 4012 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4013 .pot_clear = mv88e6xxx_g2_pot_clear, 4014 .reset = mv88e6352_g1_reset, 4015 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4016 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4017 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4018 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4019 .phylink_validate = mv88e6185_phylink_validate, 4020 }; 4021 4022 static const struct mv88e6xxx_ops mv88e6176_ops = { 4023 /* MV88E6XXX_FAMILY_6352 */ 4024 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4025 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4026 .irl_init_all = mv88e6352_g2_irl_init_all, 4027 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4028 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4030 .phy_read = mv88e6xxx_g2_smi_phy_read, 4031 .phy_write = mv88e6xxx_g2_smi_phy_write, 4032 .port_set_link = mv88e6xxx_port_set_link, 4033 .port_sync_link = mv88e6xxx_port_sync_link, 4034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4035 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4036 .port_tag_remap = mv88e6095_port_tag_remap, 4037 .port_set_policy = mv88e6352_port_set_policy, 4038 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4039 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4040 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4041 .port_set_ether_type = mv88e6351_port_set_ether_type, 4042 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4043 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4044 .port_pause_limit = mv88e6097_port_pause_limit, 4045 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4046 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4047 .port_get_cmode = mv88e6352_port_get_cmode, 4048 .port_setup_message_port = mv88e6xxx_setup_message_port, 4049 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4050 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4051 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4052 .stats_get_strings = mv88e6095_stats_get_strings, 4053 .stats_get_stats = mv88e6095_stats_get_stats, 4054 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4055 .set_egress_port = mv88e6095_g1_set_egress_port, 4056 .watchdog_ops = &mv88e6097_watchdog_ops, 4057 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4058 .pot_clear = mv88e6xxx_g2_pot_clear, 4059 .reset = mv88e6352_g1_reset, 4060 .rmu_disable = mv88e6352_g1_rmu_disable, 4061 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4062 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4063 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4064 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4065 .serdes_get_lane = mv88e6352_serdes_get_lane, 4066 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4067 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4068 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4069 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4070 .serdes_power = mv88e6352_serdes_power, 4071 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4072 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4073 .serdes_irq_status = mv88e6352_serdes_irq_status, 4074 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4075 .serdes_get_regs = mv88e6352_serdes_get_regs, 4076 .gpio_ops = &mv88e6352_gpio_ops, 4077 .phylink_validate = mv88e6352_phylink_validate, 4078 }; 4079 4080 static const struct mv88e6xxx_ops mv88e6185_ops = { 4081 /* MV88E6XXX_FAMILY_6185 */ 4082 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4083 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4084 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4085 .phy_read = mv88e6185_phy_ppu_read, 4086 .phy_write = mv88e6185_phy_ppu_write, 4087 .port_set_link = mv88e6xxx_port_set_link, 4088 .port_sync_link = mv88e6185_port_sync_link, 4089 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4090 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4091 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4092 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4093 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4094 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4095 .port_set_pause = mv88e6185_port_set_pause, 4096 .port_get_cmode = mv88e6185_port_get_cmode, 4097 .port_setup_message_port = mv88e6xxx_setup_message_port, 4098 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4099 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4100 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4101 .stats_get_strings = mv88e6095_stats_get_strings, 4102 .stats_get_stats = mv88e6095_stats_get_stats, 4103 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4104 .set_egress_port = mv88e6095_g1_set_egress_port, 4105 .watchdog_ops = &mv88e6097_watchdog_ops, 4106 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4107 .serdes_power = mv88e6185_serdes_power, 4108 .serdes_get_lane = mv88e6185_serdes_get_lane, 4109 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4110 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4111 .ppu_enable = mv88e6185_g1_ppu_enable, 4112 .ppu_disable = mv88e6185_g1_ppu_disable, 4113 .reset = mv88e6185_g1_reset, 4114 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4115 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4116 .phylink_validate = mv88e6185_phylink_validate, 4117 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4118 }; 4119 4120 static const struct mv88e6xxx_ops mv88e6190_ops = { 4121 /* MV88E6XXX_FAMILY_6390 */ 4122 .setup_errata = mv88e6390_setup_errata, 4123 .irl_init_all = mv88e6390_g2_irl_init_all, 4124 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4125 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4126 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4127 .phy_read = mv88e6xxx_g2_smi_phy_read, 4128 .phy_write = mv88e6xxx_g2_smi_phy_write, 4129 .port_set_link = mv88e6xxx_port_set_link, 4130 .port_sync_link = mv88e6xxx_port_sync_link, 4131 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4132 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4133 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4134 .port_tag_remap = mv88e6390_port_tag_remap, 4135 .port_set_policy = mv88e6352_port_set_policy, 4136 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4137 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4138 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4139 .port_set_ether_type = mv88e6351_port_set_ether_type, 4140 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4141 .port_pause_limit = mv88e6390_port_pause_limit, 4142 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4143 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4144 .port_get_cmode = mv88e6352_port_get_cmode, 4145 .port_set_cmode = mv88e6390_port_set_cmode, 4146 .port_setup_message_port = mv88e6xxx_setup_message_port, 4147 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4148 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4149 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4150 .stats_get_strings = mv88e6320_stats_get_strings, 4151 .stats_get_stats = mv88e6390_stats_get_stats, 4152 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4153 .set_egress_port = mv88e6390_g1_set_egress_port, 4154 .watchdog_ops = &mv88e6390_watchdog_ops, 4155 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4156 .pot_clear = mv88e6xxx_g2_pot_clear, 4157 .reset = mv88e6352_g1_reset, 4158 .rmu_disable = mv88e6390_g1_rmu_disable, 4159 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4160 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4161 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4162 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4163 .serdes_power = mv88e6390_serdes_power, 4164 .serdes_get_lane = mv88e6390_serdes_get_lane, 4165 /* Check status register pause & lpa register */ 4166 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4167 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4168 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4169 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4170 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4171 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4172 .serdes_irq_status = mv88e6390_serdes_irq_status, 4173 .serdes_get_strings = mv88e6390_serdes_get_strings, 4174 .serdes_get_stats = mv88e6390_serdes_get_stats, 4175 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4176 .serdes_get_regs = mv88e6390_serdes_get_regs, 4177 .gpio_ops = &mv88e6352_gpio_ops, 4178 .phylink_validate = mv88e6390_phylink_validate, 4179 }; 4180 4181 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4182 /* MV88E6XXX_FAMILY_6390 */ 4183 .setup_errata = mv88e6390_setup_errata, 4184 .irl_init_all = mv88e6390_g2_irl_init_all, 4185 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4186 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4187 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4188 .phy_read = mv88e6xxx_g2_smi_phy_read, 4189 .phy_write = mv88e6xxx_g2_smi_phy_write, 4190 .port_set_link = mv88e6xxx_port_set_link, 4191 .port_sync_link = mv88e6xxx_port_sync_link, 4192 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4193 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4194 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4195 .port_tag_remap = mv88e6390_port_tag_remap, 4196 .port_set_policy = mv88e6352_port_set_policy, 4197 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4198 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4199 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4200 .port_set_ether_type = mv88e6351_port_set_ether_type, 4201 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4202 .port_pause_limit = mv88e6390_port_pause_limit, 4203 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4204 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4205 .port_get_cmode = mv88e6352_port_get_cmode, 4206 .port_set_cmode = mv88e6390x_port_set_cmode, 4207 .port_setup_message_port = mv88e6xxx_setup_message_port, 4208 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4209 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4210 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4211 .stats_get_strings = mv88e6320_stats_get_strings, 4212 .stats_get_stats = mv88e6390_stats_get_stats, 4213 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4214 .set_egress_port = mv88e6390_g1_set_egress_port, 4215 .watchdog_ops = &mv88e6390_watchdog_ops, 4216 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4217 .pot_clear = mv88e6xxx_g2_pot_clear, 4218 .reset = mv88e6352_g1_reset, 4219 .rmu_disable = mv88e6390_g1_rmu_disable, 4220 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4221 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4222 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4223 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4224 .serdes_power = mv88e6390_serdes_power, 4225 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4226 /* Check status register pause & lpa register */ 4227 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4228 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4229 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4230 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4231 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4232 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4233 .serdes_irq_status = mv88e6390_serdes_irq_status, 4234 .serdes_get_strings = mv88e6390_serdes_get_strings, 4235 .serdes_get_stats = mv88e6390_serdes_get_stats, 4236 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4237 .serdes_get_regs = mv88e6390_serdes_get_regs, 4238 .gpio_ops = &mv88e6352_gpio_ops, 4239 .phylink_validate = mv88e6390x_phylink_validate, 4240 }; 4241 4242 static const struct mv88e6xxx_ops mv88e6191_ops = { 4243 /* MV88E6XXX_FAMILY_6390 */ 4244 .setup_errata = mv88e6390_setup_errata, 4245 .irl_init_all = mv88e6390_g2_irl_init_all, 4246 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4247 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4248 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4249 .phy_read = mv88e6xxx_g2_smi_phy_read, 4250 .phy_write = mv88e6xxx_g2_smi_phy_write, 4251 .port_set_link = mv88e6xxx_port_set_link, 4252 .port_sync_link = mv88e6xxx_port_sync_link, 4253 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4254 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4255 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4256 .port_tag_remap = mv88e6390_port_tag_remap, 4257 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4258 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4259 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4260 .port_set_ether_type = mv88e6351_port_set_ether_type, 4261 .port_pause_limit = mv88e6390_port_pause_limit, 4262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4264 .port_get_cmode = mv88e6352_port_get_cmode, 4265 .port_set_cmode = mv88e6390_port_set_cmode, 4266 .port_setup_message_port = mv88e6xxx_setup_message_port, 4267 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4268 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4269 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4270 .stats_get_strings = mv88e6320_stats_get_strings, 4271 .stats_get_stats = mv88e6390_stats_get_stats, 4272 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4273 .set_egress_port = mv88e6390_g1_set_egress_port, 4274 .watchdog_ops = &mv88e6390_watchdog_ops, 4275 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4276 .pot_clear = mv88e6xxx_g2_pot_clear, 4277 .reset = mv88e6352_g1_reset, 4278 .rmu_disable = mv88e6390_g1_rmu_disable, 4279 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4280 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4281 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4282 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4283 .serdes_power = mv88e6390_serdes_power, 4284 .serdes_get_lane = mv88e6390_serdes_get_lane, 4285 /* Check status register pause & lpa register */ 4286 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4287 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4288 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4289 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4290 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4291 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4292 .serdes_irq_status = mv88e6390_serdes_irq_status, 4293 .serdes_get_strings = mv88e6390_serdes_get_strings, 4294 .serdes_get_stats = mv88e6390_serdes_get_stats, 4295 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4296 .serdes_get_regs = mv88e6390_serdes_get_regs, 4297 .avb_ops = &mv88e6390_avb_ops, 4298 .ptp_ops = &mv88e6352_ptp_ops, 4299 .phylink_validate = mv88e6390_phylink_validate, 4300 }; 4301 4302 static const struct mv88e6xxx_ops mv88e6240_ops = { 4303 /* MV88E6XXX_FAMILY_6352 */ 4304 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4305 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4306 .irl_init_all = mv88e6352_g2_irl_init_all, 4307 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4308 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4309 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4310 .phy_read = mv88e6xxx_g2_smi_phy_read, 4311 .phy_write = mv88e6xxx_g2_smi_phy_write, 4312 .port_set_link = mv88e6xxx_port_set_link, 4313 .port_sync_link = mv88e6xxx_port_sync_link, 4314 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4315 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4316 .port_tag_remap = mv88e6095_port_tag_remap, 4317 .port_set_policy = mv88e6352_port_set_policy, 4318 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4319 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4320 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4321 .port_set_ether_type = mv88e6351_port_set_ether_type, 4322 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4323 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4324 .port_pause_limit = mv88e6097_port_pause_limit, 4325 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4326 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4327 .port_get_cmode = mv88e6352_port_get_cmode, 4328 .port_setup_message_port = mv88e6xxx_setup_message_port, 4329 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4330 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4331 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4332 .stats_get_strings = mv88e6095_stats_get_strings, 4333 .stats_get_stats = mv88e6095_stats_get_stats, 4334 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4335 .set_egress_port = mv88e6095_g1_set_egress_port, 4336 .watchdog_ops = &mv88e6097_watchdog_ops, 4337 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4338 .pot_clear = mv88e6xxx_g2_pot_clear, 4339 .reset = mv88e6352_g1_reset, 4340 .rmu_disable = mv88e6352_g1_rmu_disable, 4341 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4342 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4343 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4344 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4345 .serdes_get_lane = mv88e6352_serdes_get_lane, 4346 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4347 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4348 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4349 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4350 .serdes_power = mv88e6352_serdes_power, 4351 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4352 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4353 .serdes_irq_status = mv88e6352_serdes_irq_status, 4354 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4355 .serdes_get_regs = mv88e6352_serdes_get_regs, 4356 .gpio_ops = &mv88e6352_gpio_ops, 4357 .avb_ops = &mv88e6352_avb_ops, 4358 .ptp_ops = &mv88e6352_ptp_ops, 4359 .phylink_validate = mv88e6352_phylink_validate, 4360 }; 4361 4362 static const struct mv88e6xxx_ops mv88e6250_ops = { 4363 /* MV88E6XXX_FAMILY_6250 */ 4364 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4365 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4366 .irl_init_all = mv88e6352_g2_irl_init_all, 4367 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4368 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4369 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4370 .phy_read = mv88e6xxx_g2_smi_phy_read, 4371 .phy_write = mv88e6xxx_g2_smi_phy_write, 4372 .port_set_link = mv88e6xxx_port_set_link, 4373 .port_sync_link = mv88e6xxx_port_sync_link, 4374 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4375 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4376 .port_tag_remap = mv88e6095_port_tag_remap, 4377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4380 .port_set_ether_type = mv88e6351_port_set_ether_type, 4381 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4382 .port_pause_limit = mv88e6097_port_pause_limit, 4383 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4384 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4385 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4386 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4387 .stats_get_strings = mv88e6250_stats_get_strings, 4388 .stats_get_stats = mv88e6250_stats_get_stats, 4389 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4390 .set_egress_port = mv88e6095_g1_set_egress_port, 4391 .watchdog_ops = &mv88e6250_watchdog_ops, 4392 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4393 .pot_clear = mv88e6xxx_g2_pot_clear, 4394 .reset = mv88e6250_g1_reset, 4395 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4396 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4397 .avb_ops = &mv88e6352_avb_ops, 4398 .ptp_ops = &mv88e6250_ptp_ops, 4399 .phylink_validate = mv88e6065_phylink_validate, 4400 }; 4401 4402 static const struct mv88e6xxx_ops mv88e6290_ops = { 4403 /* MV88E6XXX_FAMILY_6390 */ 4404 .setup_errata = mv88e6390_setup_errata, 4405 .irl_init_all = mv88e6390_g2_irl_init_all, 4406 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4407 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4408 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4409 .phy_read = mv88e6xxx_g2_smi_phy_read, 4410 .phy_write = mv88e6xxx_g2_smi_phy_write, 4411 .port_set_link = mv88e6xxx_port_set_link, 4412 .port_sync_link = mv88e6xxx_port_sync_link, 4413 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4414 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4415 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4416 .port_tag_remap = mv88e6390_port_tag_remap, 4417 .port_set_policy = mv88e6352_port_set_policy, 4418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4419 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4420 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4421 .port_set_ether_type = mv88e6351_port_set_ether_type, 4422 .port_pause_limit = mv88e6390_port_pause_limit, 4423 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4424 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4425 .port_get_cmode = mv88e6352_port_get_cmode, 4426 .port_set_cmode = mv88e6390_port_set_cmode, 4427 .port_setup_message_port = mv88e6xxx_setup_message_port, 4428 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4429 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4430 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4431 .stats_get_strings = mv88e6320_stats_get_strings, 4432 .stats_get_stats = mv88e6390_stats_get_stats, 4433 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4434 .set_egress_port = mv88e6390_g1_set_egress_port, 4435 .watchdog_ops = &mv88e6390_watchdog_ops, 4436 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4437 .pot_clear = mv88e6xxx_g2_pot_clear, 4438 .reset = mv88e6352_g1_reset, 4439 .rmu_disable = mv88e6390_g1_rmu_disable, 4440 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4441 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4442 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4443 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4444 .serdes_power = mv88e6390_serdes_power, 4445 .serdes_get_lane = mv88e6390_serdes_get_lane, 4446 /* Check status register pause & lpa register */ 4447 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4448 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4449 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4450 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4451 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4452 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4453 .serdes_irq_status = mv88e6390_serdes_irq_status, 4454 .serdes_get_strings = mv88e6390_serdes_get_strings, 4455 .serdes_get_stats = mv88e6390_serdes_get_stats, 4456 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4457 .serdes_get_regs = mv88e6390_serdes_get_regs, 4458 .gpio_ops = &mv88e6352_gpio_ops, 4459 .avb_ops = &mv88e6390_avb_ops, 4460 .ptp_ops = &mv88e6352_ptp_ops, 4461 .phylink_validate = mv88e6390_phylink_validate, 4462 }; 4463 4464 static const struct mv88e6xxx_ops mv88e6320_ops = { 4465 /* MV88E6XXX_FAMILY_6320 */ 4466 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4467 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4468 .irl_init_all = mv88e6352_g2_irl_init_all, 4469 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4470 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4471 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4472 .phy_read = mv88e6xxx_g2_smi_phy_read, 4473 .phy_write = mv88e6xxx_g2_smi_phy_write, 4474 .port_set_link = mv88e6xxx_port_set_link, 4475 .port_sync_link = mv88e6xxx_port_sync_link, 4476 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4477 .port_tag_remap = mv88e6095_port_tag_remap, 4478 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4479 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4480 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4481 .port_set_ether_type = mv88e6351_port_set_ether_type, 4482 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4483 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4484 .port_pause_limit = mv88e6097_port_pause_limit, 4485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4487 .port_get_cmode = mv88e6352_port_get_cmode, 4488 .port_setup_message_port = mv88e6xxx_setup_message_port, 4489 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4491 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4492 .stats_get_strings = mv88e6320_stats_get_strings, 4493 .stats_get_stats = mv88e6320_stats_get_stats, 4494 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4495 .set_egress_port = mv88e6095_g1_set_egress_port, 4496 .watchdog_ops = &mv88e6390_watchdog_ops, 4497 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4498 .pot_clear = mv88e6xxx_g2_pot_clear, 4499 .reset = mv88e6352_g1_reset, 4500 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4501 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4502 .gpio_ops = &mv88e6352_gpio_ops, 4503 .avb_ops = &mv88e6352_avb_ops, 4504 .ptp_ops = &mv88e6352_ptp_ops, 4505 .phylink_validate = mv88e6185_phylink_validate, 4506 }; 4507 4508 static const struct mv88e6xxx_ops mv88e6321_ops = { 4509 /* MV88E6XXX_FAMILY_6320 */ 4510 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4511 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4512 .irl_init_all = mv88e6352_g2_irl_init_all, 4513 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4514 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4516 .phy_read = mv88e6xxx_g2_smi_phy_read, 4517 .phy_write = mv88e6xxx_g2_smi_phy_write, 4518 .port_set_link = mv88e6xxx_port_set_link, 4519 .port_sync_link = mv88e6xxx_port_sync_link, 4520 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4521 .port_tag_remap = mv88e6095_port_tag_remap, 4522 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4523 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4524 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4525 .port_set_ether_type = mv88e6351_port_set_ether_type, 4526 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4527 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4528 .port_pause_limit = mv88e6097_port_pause_limit, 4529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4531 .port_get_cmode = mv88e6352_port_get_cmode, 4532 .port_setup_message_port = mv88e6xxx_setup_message_port, 4533 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4534 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4535 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4536 .stats_get_strings = mv88e6320_stats_get_strings, 4537 .stats_get_stats = mv88e6320_stats_get_stats, 4538 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4539 .set_egress_port = mv88e6095_g1_set_egress_port, 4540 .watchdog_ops = &mv88e6390_watchdog_ops, 4541 .reset = mv88e6352_g1_reset, 4542 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4543 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4544 .gpio_ops = &mv88e6352_gpio_ops, 4545 .avb_ops = &mv88e6352_avb_ops, 4546 .ptp_ops = &mv88e6352_ptp_ops, 4547 .phylink_validate = mv88e6185_phylink_validate, 4548 }; 4549 4550 static const struct mv88e6xxx_ops mv88e6341_ops = { 4551 /* MV88E6XXX_FAMILY_6341 */ 4552 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4553 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4554 .irl_init_all = mv88e6352_g2_irl_init_all, 4555 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4556 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4558 .phy_read = mv88e6xxx_g2_smi_phy_read, 4559 .phy_write = mv88e6xxx_g2_smi_phy_write, 4560 .port_set_link = mv88e6xxx_port_set_link, 4561 .port_sync_link = mv88e6xxx_port_sync_link, 4562 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4563 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4564 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4565 .port_tag_remap = mv88e6095_port_tag_remap, 4566 .port_set_policy = mv88e6352_port_set_policy, 4567 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4568 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4569 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4570 .port_set_ether_type = mv88e6351_port_set_ether_type, 4571 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4573 .port_pause_limit = mv88e6097_port_pause_limit, 4574 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4575 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4576 .port_get_cmode = mv88e6352_port_get_cmode, 4577 .port_set_cmode = mv88e6341_port_set_cmode, 4578 .port_setup_message_port = mv88e6xxx_setup_message_port, 4579 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4581 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4582 .stats_get_strings = mv88e6320_stats_get_strings, 4583 .stats_get_stats = mv88e6390_stats_get_stats, 4584 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4585 .set_egress_port = mv88e6390_g1_set_egress_port, 4586 .watchdog_ops = &mv88e6390_watchdog_ops, 4587 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4588 .pot_clear = mv88e6xxx_g2_pot_clear, 4589 .reset = mv88e6352_g1_reset, 4590 .rmu_disable = mv88e6390_g1_rmu_disable, 4591 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4592 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4593 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4595 .serdes_power = mv88e6390_serdes_power, 4596 .serdes_get_lane = mv88e6341_serdes_get_lane, 4597 /* Check status register pause & lpa register */ 4598 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4599 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4600 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4601 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4602 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4603 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4604 .serdes_irq_status = mv88e6390_serdes_irq_status, 4605 .gpio_ops = &mv88e6352_gpio_ops, 4606 .avb_ops = &mv88e6390_avb_ops, 4607 .ptp_ops = &mv88e6352_ptp_ops, 4608 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4609 .serdes_get_strings = mv88e6390_serdes_get_strings, 4610 .serdes_get_stats = mv88e6390_serdes_get_stats, 4611 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4612 .serdes_get_regs = mv88e6390_serdes_get_regs, 4613 .phylink_validate = mv88e6341_phylink_validate, 4614 }; 4615 4616 static const struct mv88e6xxx_ops mv88e6350_ops = { 4617 /* MV88E6XXX_FAMILY_6351 */ 4618 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4619 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4620 .irl_init_all = mv88e6352_g2_irl_init_all, 4621 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4622 .phy_read = mv88e6xxx_g2_smi_phy_read, 4623 .phy_write = mv88e6xxx_g2_smi_phy_write, 4624 .port_set_link = mv88e6xxx_port_set_link, 4625 .port_sync_link = mv88e6xxx_port_sync_link, 4626 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4627 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4628 .port_tag_remap = mv88e6095_port_tag_remap, 4629 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4630 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4631 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4632 .port_set_ether_type = mv88e6351_port_set_ether_type, 4633 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4634 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4635 .port_pause_limit = mv88e6097_port_pause_limit, 4636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4638 .port_get_cmode = mv88e6352_port_get_cmode, 4639 .port_setup_message_port = mv88e6xxx_setup_message_port, 4640 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4643 .stats_get_strings = mv88e6095_stats_get_strings, 4644 .stats_get_stats = mv88e6095_stats_get_stats, 4645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4646 .set_egress_port = mv88e6095_g1_set_egress_port, 4647 .watchdog_ops = &mv88e6097_watchdog_ops, 4648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4649 .pot_clear = mv88e6xxx_g2_pot_clear, 4650 .reset = mv88e6352_g1_reset, 4651 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4652 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4653 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4655 .phylink_validate = mv88e6185_phylink_validate, 4656 }; 4657 4658 static const struct mv88e6xxx_ops mv88e6351_ops = { 4659 /* MV88E6XXX_FAMILY_6351 */ 4660 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4661 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4662 .irl_init_all = mv88e6352_g2_irl_init_all, 4663 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4664 .phy_read = mv88e6xxx_g2_smi_phy_read, 4665 .phy_write = mv88e6xxx_g2_smi_phy_write, 4666 .port_set_link = mv88e6xxx_port_set_link, 4667 .port_sync_link = mv88e6xxx_port_sync_link, 4668 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4669 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4670 .port_tag_remap = mv88e6095_port_tag_remap, 4671 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4672 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4673 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4674 .port_set_ether_type = mv88e6351_port_set_ether_type, 4675 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4676 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4677 .port_pause_limit = mv88e6097_port_pause_limit, 4678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4680 .port_get_cmode = mv88e6352_port_get_cmode, 4681 .port_setup_message_port = mv88e6xxx_setup_message_port, 4682 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4683 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4684 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4685 .stats_get_strings = mv88e6095_stats_get_strings, 4686 .stats_get_stats = mv88e6095_stats_get_stats, 4687 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4688 .set_egress_port = mv88e6095_g1_set_egress_port, 4689 .watchdog_ops = &mv88e6097_watchdog_ops, 4690 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4691 .pot_clear = mv88e6xxx_g2_pot_clear, 4692 .reset = mv88e6352_g1_reset, 4693 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4694 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4695 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4697 .avb_ops = &mv88e6352_avb_ops, 4698 .ptp_ops = &mv88e6352_ptp_ops, 4699 .phylink_validate = mv88e6185_phylink_validate, 4700 }; 4701 4702 static const struct mv88e6xxx_ops mv88e6352_ops = { 4703 /* MV88E6XXX_FAMILY_6352 */ 4704 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4705 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4706 .irl_init_all = mv88e6352_g2_irl_init_all, 4707 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4708 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4709 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4710 .phy_read = mv88e6xxx_g2_smi_phy_read, 4711 .phy_write = mv88e6xxx_g2_smi_phy_write, 4712 .port_set_link = mv88e6xxx_port_set_link, 4713 .port_sync_link = mv88e6xxx_port_sync_link, 4714 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4715 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4716 .port_tag_remap = mv88e6095_port_tag_remap, 4717 .port_set_policy = mv88e6352_port_set_policy, 4718 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4719 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4720 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4721 .port_set_ether_type = mv88e6351_port_set_ether_type, 4722 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4724 .port_pause_limit = mv88e6097_port_pause_limit, 4725 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4726 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4727 .port_get_cmode = mv88e6352_port_get_cmode, 4728 .port_setup_message_port = mv88e6xxx_setup_message_port, 4729 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4730 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4731 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4732 .stats_get_strings = mv88e6095_stats_get_strings, 4733 .stats_get_stats = mv88e6095_stats_get_stats, 4734 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4735 .set_egress_port = mv88e6095_g1_set_egress_port, 4736 .watchdog_ops = &mv88e6097_watchdog_ops, 4737 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4738 .pot_clear = mv88e6xxx_g2_pot_clear, 4739 .reset = mv88e6352_g1_reset, 4740 .rmu_disable = mv88e6352_g1_rmu_disable, 4741 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4742 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4743 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4744 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4745 .serdes_get_lane = mv88e6352_serdes_get_lane, 4746 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4747 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4748 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4749 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4750 .serdes_power = mv88e6352_serdes_power, 4751 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4752 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4753 .serdes_irq_status = mv88e6352_serdes_irq_status, 4754 .gpio_ops = &mv88e6352_gpio_ops, 4755 .avb_ops = &mv88e6352_avb_ops, 4756 .ptp_ops = &mv88e6352_ptp_ops, 4757 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4758 .serdes_get_strings = mv88e6352_serdes_get_strings, 4759 .serdes_get_stats = mv88e6352_serdes_get_stats, 4760 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4761 .serdes_get_regs = mv88e6352_serdes_get_regs, 4762 .phylink_validate = mv88e6352_phylink_validate, 4763 }; 4764 4765 static const struct mv88e6xxx_ops mv88e6390_ops = { 4766 /* MV88E6XXX_FAMILY_6390 */ 4767 .setup_errata = mv88e6390_setup_errata, 4768 .irl_init_all = mv88e6390_g2_irl_init_all, 4769 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4770 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4772 .phy_read = mv88e6xxx_g2_smi_phy_read, 4773 .phy_write = mv88e6xxx_g2_smi_phy_write, 4774 .port_set_link = mv88e6xxx_port_set_link, 4775 .port_sync_link = mv88e6xxx_port_sync_link, 4776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4777 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4778 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4779 .port_tag_remap = mv88e6390_port_tag_remap, 4780 .port_set_policy = mv88e6352_port_set_policy, 4781 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4782 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4783 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4784 .port_set_ether_type = mv88e6351_port_set_ether_type, 4785 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4786 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4787 .port_pause_limit = mv88e6390_port_pause_limit, 4788 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4789 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4790 .port_get_cmode = mv88e6352_port_get_cmode, 4791 .port_set_cmode = mv88e6390_port_set_cmode, 4792 .port_setup_message_port = mv88e6xxx_setup_message_port, 4793 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4794 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4795 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4796 .stats_get_strings = mv88e6320_stats_get_strings, 4797 .stats_get_stats = mv88e6390_stats_get_stats, 4798 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4799 .set_egress_port = mv88e6390_g1_set_egress_port, 4800 .watchdog_ops = &mv88e6390_watchdog_ops, 4801 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4802 .pot_clear = mv88e6xxx_g2_pot_clear, 4803 .reset = mv88e6352_g1_reset, 4804 .rmu_disable = mv88e6390_g1_rmu_disable, 4805 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4806 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4807 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4808 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4809 .serdes_power = mv88e6390_serdes_power, 4810 .serdes_get_lane = mv88e6390_serdes_get_lane, 4811 /* Check status register pause & lpa register */ 4812 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4813 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4814 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4815 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4816 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4817 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4818 .serdes_irq_status = mv88e6390_serdes_irq_status, 4819 .gpio_ops = &mv88e6352_gpio_ops, 4820 .avb_ops = &mv88e6390_avb_ops, 4821 .ptp_ops = &mv88e6352_ptp_ops, 4822 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4823 .serdes_get_strings = mv88e6390_serdes_get_strings, 4824 .serdes_get_stats = mv88e6390_serdes_get_stats, 4825 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4826 .serdes_get_regs = mv88e6390_serdes_get_regs, 4827 .phylink_validate = mv88e6390_phylink_validate, 4828 }; 4829 4830 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4831 /* MV88E6XXX_FAMILY_6390 */ 4832 .setup_errata = mv88e6390_setup_errata, 4833 .irl_init_all = mv88e6390_g2_irl_init_all, 4834 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4835 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4836 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4837 .phy_read = mv88e6xxx_g2_smi_phy_read, 4838 .phy_write = mv88e6xxx_g2_smi_phy_write, 4839 .port_set_link = mv88e6xxx_port_set_link, 4840 .port_sync_link = mv88e6xxx_port_sync_link, 4841 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4842 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4843 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4844 .port_tag_remap = mv88e6390_port_tag_remap, 4845 .port_set_policy = mv88e6352_port_set_policy, 4846 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4847 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4848 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4849 .port_set_ether_type = mv88e6351_port_set_ether_type, 4850 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4851 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4852 .port_pause_limit = mv88e6390_port_pause_limit, 4853 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4854 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4855 .port_get_cmode = mv88e6352_port_get_cmode, 4856 .port_set_cmode = mv88e6390x_port_set_cmode, 4857 .port_setup_message_port = mv88e6xxx_setup_message_port, 4858 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4859 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4860 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4861 .stats_get_strings = mv88e6320_stats_get_strings, 4862 .stats_get_stats = mv88e6390_stats_get_stats, 4863 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4864 .set_egress_port = mv88e6390_g1_set_egress_port, 4865 .watchdog_ops = &mv88e6390_watchdog_ops, 4866 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4867 .pot_clear = mv88e6xxx_g2_pot_clear, 4868 .reset = mv88e6352_g1_reset, 4869 .rmu_disable = mv88e6390_g1_rmu_disable, 4870 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4871 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4872 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4873 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4874 .serdes_power = mv88e6390_serdes_power, 4875 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4876 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4877 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4878 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4879 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4880 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4881 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4882 .serdes_irq_status = mv88e6390_serdes_irq_status, 4883 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4884 .serdes_get_strings = mv88e6390_serdes_get_strings, 4885 .serdes_get_stats = mv88e6390_serdes_get_stats, 4886 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4887 .serdes_get_regs = mv88e6390_serdes_get_regs, 4888 .gpio_ops = &mv88e6352_gpio_ops, 4889 .avb_ops = &mv88e6390_avb_ops, 4890 .ptp_ops = &mv88e6352_ptp_ops, 4891 .phylink_validate = mv88e6390x_phylink_validate, 4892 }; 4893 4894 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4895 /* MV88E6XXX_FAMILY_6393 */ 4896 .setup_errata = mv88e6393x_serdes_setup_errata, 4897 .irl_init_all = mv88e6390_g2_irl_init_all, 4898 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4899 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4901 .phy_read = mv88e6xxx_g2_smi_phy_read, 4902 .phy_write = mv88e6xxx_g2_smi_phy_write, 4903 .port_set_link = mv88e6xxx_port_set_link, 4904 .port_sync_link = mv88e6xxx_port_sync_link, 4905 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4906 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4907 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4908 .port_tag_remap = mv88e6390_port_tag_remap, 4909 .port_set_policy = mv88e6393x_port_set_policy, 4910 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4911 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4912 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4913 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4914 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4915 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4916 .port_pause_limit = mv88e6390_port_pause_limit, 4917 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4918 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4919 .port_get_cmode = mv88e6352_port_get_cmode, 4920 .port_set_cmode = mv88e6393x_port_set_cmode, 4921 .port_setup_message_port = mv88e6xxx_setup_message_port, 4922 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4923 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4924 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4925 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4926 .stats_get_strings = mv88e6320_stats_get_strings, 4927 .stats_get_stats = mv88e6390_stats_get_stats, 4928 /* .set_cpu_port is missing because this family does not support a global 4929 * CPU port, only per port CPU port which is set via 4930 * .port_set_upstream_port method. 4931 */ 4932 .set_egress_port = mv88e6393x_set_egress_port, 4933 .watchdog_ops = &mv88e6390_watchdog_ops, 4934 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4935 .pot_clear = mv88e6xxx_g2_pot_clear, 4936 .reset = mv88e6352_g1_reset, 4937 .rmu_disable = mv88e6390_g1_rmu_disable, 4938 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4939 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4940 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4941 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4942 .serdes_power = mv88e6393x_serdes_power, 4943 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4944 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4945 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4946 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4947 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4948 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4949 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4950 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4951 /* TODO: serdes stats */ 4952 .gpio_ops = &mv88e6352_gpio_ops, 4953 .avb_ops = &mv88e6390_avb_ops, 4954 .ptp_ops = &mv88e6352_ptp_ops, 4955 .phylink_validate = mv88e6393x_phylink_validate, 4956 }; 4957 4958 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4959 [MV88E6085] = { 4960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4961 .family = MV88E6XXX_FAMILY_6097, 4962 .name = "Marvell 88E6085", 4963 .num_databases = 4096, 4964 .num_macs = 8192, 4965 .num_ports = 10, 4966 .num_internal_phys = 5, 4967 .max_vid = 4095, 4968 .port_base_addr = 0x10, 4969 .phy_base_addr = 0x0, 4970 .global1_addr = 0x1b, 4971 .global2_addr = 0x1c, 4972 .age_time_coeff = 15000, 4973 .g1_irqs = 8, 4974 .g2_irqs = 10, 4975 .atu_move_port_mask = 0xf, 4976 .pvt = true, 4977 .multi_chip = true, 4978 .ops = &mv88e6085_ops, 4979 }, 4980 4981 [MV88E6095] = { 4982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4983 .family = MV88E6XXX_FAMILY_6095, 4984 .name = "Marvell 88E6095/88E6095F", 4985 .num_databases = 256, 4986 .num_macs = 8192, 4987 .num_ports = 11, 4988 .num_internal_phys = 0, 4989 .max_vid = 4095, 4990 .port_base_addr = 0x10, 4991 .phy_base_addr = 0x0, 4992 .global1_addr = 0x1b, 4993 .global2_addr = 0x1c, 4994 .age_time_coeff = 15000, 4995 .g1_irqs = 8, 4996 .atu_move_port_mask = 0xf, 4997 .multi_chip = true, 4998 .ops = &mv88e6095_ops, 4999 }, 5000 5001 [MV88E6097] = { 5002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5003 .family = MV88E6XXX_FAMILY_6097, 5004 .name = "Marvell 88E6097/88E6097F", 5005 .num_databases = 4096, 5006 .num_macs = 8192, 5007 .num_ports = 11, 5008 .num_internal_phys = 8, 5009 .max_vid = 4095, 5010 .port_base_addr = 0x10, 5011 .phy_base_addr = 0x0, 5012 .global1_addr = 0x1b, 5013 .global2_addr = 0x1c, 5014 .age_time_coeff = 15000, 5015 .g1_irqs = 8, 5016 .g2_irqs = 10, 5017 .atu_move_port_mask = 0xf, 5018 .pvt = true, 5019 .multi_chip = true, 5020 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5021 .ops = &mv88e6097_ops, 5022 }, 5023 5024 [MV88E6123] = { 5025 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5026 .family = MV88E6XXX_FAMILY_6165, 5027 .name = "Marvell 88E6123", 5028 .num_databases = 4096, 5029 .num_macs = 1024, 5030 .num_ports = 3, 5031 .num_internal_phys = 5, 5032 .max_vid = 4095, 5033 .port_base_addr = 0x10, 5034 .phy_base_addr = 0x0, 5035 .global1_addr = 0x1b, 5036 .global2_addr = 0x1c, 5037 .age_time_coeff = 15000, 5038 .g1_irqs = 9, 5039 .g2_irqs = 10, 5040 .atu_move_port_mask = 0xf, 5041 .pvt = true, 5042 .multi_chip = true, 5043 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5044 .ops = &mv88e6123_ops, 5045 }, 5046 5047 [MV88E6131] = { 5048 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5049 .family = MV88E6XXX_FAMILY_6185, 5050 .name = "Marvell 88E6131", 5051 .num_databases = 256, 5052 .num_macs = 8192, 5053 .num_ports = 8, 5054 .num_internal_phys = 0, 5055 .max_vid = 4095, 5056 .port_base_addr = 0x10, 5057 .phy_base_addr = 0x0, 5058 .global1_addr = 0x1b, 5059 .global2_addr = 0x1c, 5060 .age_time_coeff = 15000, 5061 .g1_irqs = 9, 5062 .atu_move_port_mask = 0xf, 5063 .multi_chip = true, 5064 .ops = &mv88e6131_ops, 5065 }, 5066 5067 [MV88E6141] = { 5068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5069 .family = MV88E6XXX_FAMILY_6341, 5070 .name = "Marvell 88E6141", 5071 .num_databases = 4096, 5072 .num_macs = 2048, 5073 .num_ports = 6, 5074 .num_internal_phys = 5, 5075 .num_gpio = 11, 5076 .max_vid = 4095, 5077 .port_base_addr = 0x10, 5078 .phy_base_addr = 0x10, 5079 .global1_addr = 0x1b, 5080 .global2_addr = 0x1c, 5081 .age_time_coeff = 3750, 5082 .atu_move_port_mask = 0x1f, 5083 .g1_irqs = 9, 5084 .g2_irqs = 10, 5085 .pvt = true, 5086 .multi_chip = true, 5087 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5088 .ops = &mv88e6141_ops, 5089 }, 5090 5091 [MV88E6161] = { 5092 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5093 .family = MV88E6XXX_FAMILY_6165, 5094 .name = "Marvell 88E6161", 5095 .num_databases = 4096, 5096 .num_macs = 1024, 5097 .num_ports = 6, 5098 .num_internal_phys = 5, 5099 .max_vid = 4095, 5100 .port_base_addr = 0x10, 5101 .phy_base_addr = 0x0, 5102 .global1_addr = 0x1b, 5103 .global2_addr = 0x1c, 5104 .age_time_coeff = 15000, 5105 .g1_irqs = 9, 5106 .g2_irqs = 10, 5107 .atu_move_port_mask = 0xf, 5108 .pvt = true, 5109 .multi_chip = true, 5110 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5111 .ptp_support = true, 5112 .ops = &mv88e6161_ops, 5113 }, 5114 5115 [MV88E6165] = { 5116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5117 .family = MV88E6XXX_FAMILY_6165, 5118 .name = "Marvell 88E6165", 5119 .num_databases = 4096, 5120 .num_macs = 8192, 5121 .num_ports = 6, 5122 .num_internal_phys = 0, 5123 .max_vid = 4095, 5124 .port_base_addr = 0x10, 5125 .phy_base_addr = 0x0, 5126 .global1_addr = 0x1b, 5127 .global2_addr = 0x1c, 5128 .age_time_coeff = 15000, 5129 .g1_irqs = 9, 5130 .g2_irqs = 10, 5131 .atu_move_port_mask = 0xf, 5132 .pvt = true, 5133 .multi_chip = true, 5134 .ptp_support = true, 5135 .ops = &mv88e6165_ops, 5136 }, 5137 5138 [MV88E6171] = { 5139 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5140 .family = MV88E6XXX_FAMILY_6351, 5141 .name = "Marvell 88E6171", 5142 .num_databases = 4096, 5143 .num_macs = 8192, 5144 .num_ports = 7, 5145 .num_internal_phys = 5, 5146 .max_vid = 4095, 5147 .port_base_addr = 0x10, 5148 .phy_base_addr = 0x0, 5149 .global1_addr = 0x1b, 5150 .global2_addr = 0x1c, 5151 .age_time_coeff = 15000, 5152 .g1_irqs = 9, 5153 .g2_irqs = 10, 5154 .atu_move_port_mask = 0xf, 5155 .pvt = true, 5156 .multi_chip = true, 5157 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5158 .ops = &mv88e6171_ops, 5159 }, 5160 5161 [MV88E6172] = { 5162 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5163 .family = MV88E6XXX_FAMILY_6352, 5164 .name = "Marvell 88E6172", 5165 .num_databases = 4096, 5166 .num_macs = 8192, 5167 .num_ports = 7, 5168 .num_internal_phys = 5, 5169 .num_gpio = 15, 5170 .max_vid = 4095, 5171 .port_base_addr = 0x10, 5172 .phy_base_addr = 0x0, 5173 .global1_addr = 0x1b, 5174 .global2_addr = 0x1c, 5175 .age_time_coeff = 15000, 5176 .g1_irqs = 9, 5177 .g2_irqs = 10, 5178 .atu_move_port_mask = 0xf, 5179 .pvt = true, 5180 .multi_chip = true, 5181 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5182 .ops = &mv88e6172_ops, 5183 }, 5184 5185 [MV88E6175] = { 5186 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5187 .family = MV88E6XXX_FAMILY_6351, 5188 .name = "Marvell 88E6175", 5189 .num_databases = 4096, 5190 .num_macs = 8192, 5191 .num_ports = 7, 5192 .num_internal_phys = 5, 5193 .max_vid = 4095, 5194 .port_base_addr = 0x10, 5195 .phy_base_addr = 0x0, 5196 .global1_addr = 0x1b, 5197 .global2_addr = 0x1c, 5198 .age_time_coeff = 15000, 5199 .g1_irqs = 9, 5200 .g2_irqs = 10, 5201 .atu_move_port_mask = 0xf, 5202 .pvt = true, 5203 .multi_chip = true, 5204 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5205 .ops = &mv88e6175_ops, 5206 }, 5207 5208 [MV88E6176] = { 5209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5210 .family = MV88E6XXX_FAMILY_6352, 5211 .name = "Marvell 88E6176", 5212 .num_databases = 4096, 5213 .num_macs = 8192, 5214 .num_ports = 7, 5215 .num_internal_phys = 5, 5216 .num_gpio = 15, 5217 .max_vid = 4095, 5218 .port_base_addr = 0x10, 5219 .phy_base_addr = 0x0, 5220 .global1_addr = 0x1b, 5221 .global2_addr = 0x1c, 5222 .age_time_coeff = 15000, 5223 .g1_irqs = 9, 5224 .g2_irqs = 10, 5225 .atu_move_port_mask = 0xf, 5226 .pvt = true, 5227 .multi_chip = true, 5228 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5229 .ops = &mv88e6176_ops, 5230 }, 5231 5232 [MV88E6185] = { 5233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5234 .family = MV88E6XXX_FAMILY_6185, 5235 .name = "Marvell 88E6185", 5236 .num_databases = 256, 5237 .num_macs = 8192, 5238 .num_ports = 10, 5239 .num_internal_phys = 0, 5240 .max_vid = 4095, 5241 .port_base_addr = 0x10, 5242 .phy_base_addr = 0x0, 5243 .global1_addr = 0x1b, 5244 .global2_addr = 0x1c, 5245 .age_time_coeff = 15000, 5246 .g1_irqs = 8, 5247 .atu_move_port_mask = 0xf, 5248 .multi_chip = true, 5249 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5250 .ops = &mv88e6185_ops, 5251 }, 5252 5253 [MV88E6190] = { 5254 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5255 .family = MV88E6XXX_FAMILY_6390, 5256 .name = "Marvell 88E6190", 5257 .num_databases = 4096, 5258 .num_macs = 16384, 5259 .num_ports = 11, /* 10 + Z80 */ 5260 .num_internal_phys = 9, 5261 .num_gpio = 16, 5262 .max_vid = 8191, 5263 .port_base_addr = 0x0, 5264 .phy_base_addr = 0x0, 5265 .global1_addr = 0x1b, 5266 .global2_addr = 0x1c, 5267 .age_time_coeff = 3750, 5268 .g1_irqs = 9, 5269 .g2_irqs = 14, 5270 .pvt = true, 5271 .multi_chip = true, 5272 .atu_move_port_mask = 0x1f, 5273 .ops = &mv88e6190_ops, 5274 }, 5275 5276 [MV88E6190X] = { 5277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5278 .family = MV88E6XXX_FAMILY_6390, 5279 .name = "Marvell 88E6190X", 5280 .num_databases = 4096, 5281 .num_macs = 16384, 5282 .num_ports = 11, /* 10 + Z80 */ 5283 .num_internal_phys = 9, 5284 .num_gpio = 16, 5285 .max_vid = 8191, 5286 .port_base_addr = 0x0, 5287 .phy_base_addr = 0x0, 5288 .global1_addr = 0x1b, 5289 .global2_addr = 0x1c, 5290 .age_time_coeff = 3750, 5291 .g1_irqs = 9, 5292 .g2_irqs = 14, 5293 .atu_move_port_mask = 0x1f, 5294 .pvt = true, 5295 .multi_chip = true, 5296 .ops = &mv88e6190x_ops, 5297 }, 5298 5299 [MV88E6191] = { 5300 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5301 .family = MV88E6XXX_FAMILY_6390, 5302 .name = "Marvell 88E6191", 5303 .num_databases = 4096, 5304 .num_macs = 16384, 5305 .num_ports = 11, /* 10 + Z80 */ 5306 .num_internal_phys = 9, 5307 .max_vid = 8191, 5308 .port_base_addr = 0x0, 5309 .phy_base_addr = 0x0, 5310 .global1_addr = 0x1b, 5311 .global2_addr = 0x1c, 5312 .age_time_coeff = 3750, 5313 .g1_irqs = 9, 5314 .g2_irqs = 14, 5315 .atu_move_port_mask = 0x1f, 5316 .pvt = true, 5317 .multi_chip = true, 5318 .ptp_support = true, 5319 .ops = &mv88e6191_ops, 5320 }, 5321 5322 [MV88E6191X] = { 5323 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5324 .family = MV88E6XXX_FAMILY_6393, 5325 .name = "Marvell 88E6191X", 5326 .num_databases = 4096, 5327 .num_ports = 11, /* 10 + Z80 */ 5328 .num_internal_phys = 9, 5329 .max_vid = 8191, 5330 .port_base_addr = 0x0, 5331 .phy_base_addr = 0x0, 5332 .global1_addr = 0x1b, 5333 .global2_addr = 0x1c, 5334 .age_time_coeff = 3750, 5335 .g1_irqs = 10, 5336 .g2_irqs = 14, 5337 .atu_move_port_mask = 0x1f, 5338 .pvt = true, 5339 .multi_chip = true, 5340 .ptp_support = true, 5341 .ops = &mv88e6393x_ops, 5342 }, 5343 5344 [MV88E6193X] = { 5345 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5346 .family = MV88E6XXX_FAMILY_6393, 5347 .name = "Marvell 88E6193X", 5348 .num_databases = 4096, 5349 .num_ports = 11, /* 10 + Z80 */ 5350 .num_internal_phys = 9, 5351 .max_vid = 8191, 5352 .port_base_addr = 0x0, 5353 .phy_base_addr = 0x0, 5354 .global1_addr = 0x1b, 5355 .global2_addr = 0x1c, 5356 .age_time_coeff = 3750, 5357 .g1_irqs = 10, 5358 .g2_irqs = 14, 5359 .atu_move_port_mask = 0x1f, 5360 .pvt = true, 5361 .multi_chip = true, 5362 .ptp_support = true, 5363 .ops = &mv88e6393x_ops, 5364 }, 5365 5366 [MV88E6220] = { 5367 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5368 .family = MV88E6XXX_FAMILY_6250, 5369 .name = "Marvell 88E6220", 5370 .num_databases = 64, 5371 5372 /* Ports 2-4 are not routed to pins 5373 * => usable ports 0, 1, 5, 6 5374 */ 5375 .num_ports = 7, 5376 .num_internal_phys = 2, 5377 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5378 .max_vid = 4095, 5379 .port_base_addr = 0x08, 5380 .phy_base_addr = 0x00, 5381 .global1_addr = 0x0f, 5382 .global2_addr = 0x07, 5383 .age_time_coeff = 15000, 5384 .g1_irqs = 9, 5385 .g2_irqs = 10, 5386 .atu_move_port_mask = 0xf, 5387 .dual_chip = true, 5388 .ptp_support = true, 5389 .ops = &mv88e6250_ops, 5390 }, 5391 5392 [MV88E6240] = { 5393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5394 .family = MV88E6XXX_FAMILY_6352, 5395 .name = "Marvell 88E6240", 5396 .num_databases = 4096, 5397 .num_macs = 8192, 5398 .num_ports = 7, 5399 .num_internal_phys = 5, 5400 .num_gpio = 15, 5401 .max_vid = 4095, 5402 .port_base_addr = 0x10, 5403 .phy_base_addr = 0x0, 5404 .global1_addr = 0x1b, 5405 .global2_addr = 0x1c, 5406 .age_time_coeff = 15000, 5407 .g1_irqs = 9, 5408 .g2_irqs = 10, 5409 .atu_move_port_mask = 0xf, 5410 .pvt = true, 5411 .multi_chip = true, 5412 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5413 .ptp_support = true, 5414 .ops = &mv88e6240_ops, 5415 }, 5416 5417 [MV88E6250] = { 5418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5419 .family = MV88E6XXX_FAMILY_6250, 5420 .name = "Marvell 88E6250", 5421 .num_databases = 64, 5422 .num_ports = 7, 5423 .num_internal_phys = 5, 5424 .max_vid = 4095, 5425 .port_base_addr = 0x08, 5426 .phy_base_addr = 0x00, 5427 .global1_addr = 0x0f, 5428 .global2_addr = 0x07, 5429 .age_time_coeff = 15000, 5430 .g1_irqs = 9, 5431 .g2_irqs = 10, 5432 .atu_move_port_mask = 0xf, 5433 .dual_chip = true, 5434 .ptp_support = true, 5435 .ops = &mv88e6250_ops, 5436 }, 5437 5438 [MV88E6290] = { 5439 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5440 .family = MV88E6XXX_FAMILY_6390, 5441 .name = "Marvell 88E6290", 5442 .num_databases = 4096, 5443 .num_ports = 11, /* 10 + Z80 */ 5444 .num_internal_phys = 9, 5445 .num_gpio = 16, 5446 .max_vid = 8191, 5447 .port_base_addr = 0x0, 5448 .phy_base_addr = 0x0, 5449 .global1_addr = 0x1b, 5450 .global2_addr = 0x1c, 5451 .age_time_coeff = 3750, 5452 .g1_irqs = 9, 5453 .g2_irqs = 14, 5454 .atu_move_port_mask = 0x1f, 5455 .pvt = true, 5456 .multi_chip = true, 5457 .ptp_support = true, 5458 .ops = &mv88e6290_ops, 5459 }, 5460 5461 [MV88E6320] = { 5462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5463 .family = MV88E6XXX_FAMILY_6320, 5464 .name = "Marvell 88E6320", 5465 .num_databases = 4096, 5466 .num_macs = 8192, 5467 .num_ports = 7, 5468 .num_internal_phys = 5, 5469 .num_gpio = 15, 5470 .max_vid = 4095, 5471 .port_base_addr = 0x10, 5472 .phy_base_addr = 0x0, 5473 .global1_addr = 0x1b, 5474 .global2_addr = 0x1c, 5475 .age_time_coeff = 15000, 5476 .g1_irqs = 8, 5477 .g2_irqs = 10, 5478 .atu_move_port_mask = 0xf, 5479 .pvt = true, 5480 .multi_chip = true, 5481 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5482 .ptp_support = true, 5483 .ops = &mv88e6320_ops, 5484 }, 5485 5486 [MV88E6321] = { 5487 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5488 .family = MV88E6XXX_FAMILY_6320, 5489 .name = "Marvell 88E6321", 5490 .num_databases = 4096, 5491 .num_macs = 8192, 5492 .num_ports = 7, 5493 .num_internal_phys = 5, 5494 .num_gpio = 15, 5495 .max_vid = 4095, 5496 .port_base_addr = 0x10, 5497 .phy_base_addr = 0x0, 5498 .global1_addr = 0x1b, 5499 .global2_addr = 0x1c, 5500 .age_time_coeff = 15000, 5501 .g1_irqs = 8, 5502 .g2_irqs = 10, 5503 .atu_move_port_mask = 0xf, 5504 .multi_chip = true, 5505 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5506 .ptp_support = true, 5507 .ops = &mv88e6321_ops, 5508 }, 5509 5510 [MV88E6341] = { 5511 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5512 .family = MV88E6XXX_FAMILY_6341, 5513 .name = "Marvell 88E6341", 5514 .num_databases = 4096, 5515 .num_macs = 2048, 5516 .num_internal_phys = 5, 5517 .num_ports = 6, 5518 .num_gpio = 11, 5519 .max_vid = 4095, 5520 .port_base_addr = 0x10, 5521 .phy_base_addr = 0x10, 5522 .global1_addr = 0x1b, 5523 .global2_addr = 0x1c, 5524 .age_time_coeff = 3750, 5525 .atu_move_port_mask = 0x1f, 5526 .g1_irqs = 9, 5527 .g2_irqs = 10, 5528 .pvt = true, 5529 .multi_chip = true, 5530 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5531 .ptp_support = true, 5532 .ops = &mv88e6341_ops, 5533 }, 5534 5535 [MV88E6350] = { 5536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5537 .family = MV88E6XXX_FAMILY_6351, 5538 .name = "Marvell 88E6350", 5539 .num_databases = 4096, 5540 .num_macs = 8192, 5541 .num_ports = 7, 5542 .num_internal_phys = 5, 5543 .max_vid = 4095, 5544 .port_base_addr = 0x10, 5545 .phy_base_addr = 0x0, 5546 .global1_addr = 0x1b, 5547 .global2_addr = 0x1c, 5548 .age_time_coeff = 15000, 5549 .g1_irqs = 9, 5550 .g2_irqs = 10, 5551 .atu_move_port_mask = 0xf, 5552 .pvt = true, 5553 .multi_chip = true, 5554 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5555 .ops = &mv88e6350_ops, 5556 }, 5557 5558 [MV88E6351] = { 5559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5560 .family = MV88E6XXX_FAMILY_6351, 5561 .name = "Marvell 88E6351", 5562 .num_databases = 4096, 5563 .num_macs = 8192, 5564 .num_ports = 7, 5565 .num_internal_phys = 5, 5566 .max_vid = 4095, 5567 .port_base_addr = 0x10, 5568 .phy_base_addr = 0x0, 5569 .global1_addr = 0x1b, 5570 .global2_addr = 0x1c, 5571 .age_time_coeff = 15000, 5572 .g1_irqs = 9, 5573 .g2_irqs = 10, 5574 .atu_move_port_mask = 0xf, 5575 .pvt = true, 5576 .multi_chip = true, 5577 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5578 .ops = &mv88e6351_ops, 5579 }, 5580 5581 [MV88E6352] = { 5582 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5583 .family = MV88E6XXX_FAMILY_6352, 5584 .name = "Marvell 88E6352", 5585 .num_databases = 4096, 5586 .num_macs = 8192, 5587 .num_ports = 7, 5588 .num_internal_phys = 5, 5589 .num_gpio = 15, 5590 .max_vid = 4095, 5591 .port_base_addr = 0x10, 5592 .phy_base_addr = 0x0, 5593 .global1_addr = 0x1b, 5594 .global2_addr = 0x1c, 5595 .age_time_coeff = 15000, 5596 .g1_irqs = 9, 5597 .g2_irqs = 10, 5598 .atu_move_port_mask = 0xf, 5599 .pvt = true, 5600 .multi_chip = true, 5601 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5602 .ptp_support = true, 5603 .ops = &mv88e6352_ops, 5604 }, 5605 [MV88E6390] = { 5606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5607 .family = MV88E6XXX_FAMILY_6390, 5608 .name = "Marvell 88E6390", 5609 .num_databases = 4096, 5610 .num_macs = 16384, 5611 .num_ports = 11, /* 10 + Z80 */ 5612 .num_internal_phys = 9, 5613 .num_gpio = 16, 5614 .max_vid = 8191, 5615 .port_base_addr = 0x0, 5616 .phy_base_addr = 0x0, 5617 .global1_addr = 0x1b, 5618 .global2_addr = 0x1c, 5619 .age_time_coeff = 3750, 5620 .g1_irqs = 9, 5621 .g2_irqs = 14, 5622 .atu_move_port_mask = 0x1f, 5623 .pvt = true, 5624 .multi_chip = true, 5625 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5626 .ptp_support = true, 5627 .ops = &mv88e6390_ops, 5628 }, 5629 [MV88E6390X] = { 5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5631 .family = MV88E6XXX_FAMILY_6390, 5632 .name = "Marvell 88E6390X", 5633 .num_databases = 4096, 5634 .num_macs = 16384, 5635 .num_ports = 11, /* 10 + Z80 */ 5636 .num_internal_phys = 9, 5637 .num_gpio = 16, 5638 .max_vid = 8191, 5639 .port_base_addr = 0x0, 5640 .phy_base_addr = 0x0, 5641 .global1_addr = 0x1b, 5642 .global2_addr = 0x1c, 5643 .age_time_coeff = 3750, 5644 .g1_irqs = 9, 5645 .g2_irqs = 14, 5646 .atu_move_port_mask = 0x1f, 5647 .pvt = true, 5648 .multi_chip = true, 5649 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5650 .ptp_support = true, 5651 .ops = &mv88e6390x_ops, 5652 }, 5653 5654 [MV88E6393X] = { 5655 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5656 .family = MV88E6XXX_FAMILY_6393, 5657 .name = "Marvell 88E6393X", 5658 .num_databases = 4096, 5659 .num_ports = 11, /* 10 + Z80 */ 5660 .num_internal_phys = 9, 5661 .max_vid = 8191, 5662 .port_base_addr = 0x0, 5663 .phy_base_addr = 0x0, 5664 .global1_addr = 0x1b, 5665 .global2_addr = 0x1c, 5666 .age_time_coeff = 3750, 5667 .g1_irqs = 10, 5668 .g2_irqs = 14, 5669 .atu_move_port_mask = 0x1f, 5670 .pvt = true, 5671 .multi_chip = true, 5672 .ptp_support = true, 5673 .ops = &mv88e6393x_ops, 5674 }, 5675 }; 5676 5677 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5678 { 5679 int i; 5680 5681 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5682 if (mv88e6xxx_table[i].prod_num == prod_num) 5683 return &mv88e6xxx_table[i]; 5684 5685 return NULL; 5686 } 5687 5688 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5689 { 5690 const struct mv88e6xxx_info *info; 5691 unsigned int prod_num, rev; 5692 u16 id; 5693 int err; 5694 5695 mv88e6xxx_reg_lock(chip); 5696 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5697 mv88e6xxx_reg_unlock(chip); 5698 if (err) 5699 return err; 5700 5701 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5702 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5703 5704 info = mv88e6xxx_lookup_info(prod_num); 5705 if (!info) 5706 return -ENODEV; 5707 5708 /* Update the compatible info with the probed one */ 5709 chip->info = info; 5710 5711 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5712 chip->info->prod_num, chip->info->name, rev); 5713 5714 return 0; 5715 } 5716 5717 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5718 { 5719 struct mv88e6xxx_chip *chip; 5720 5721 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5722 if (!chip) 5723 return NULL; 5724 5725 chip->dev = dev; 5726 5727 mutex_init(&chip->reg_lock); 5728 INIT_LIST_HEAD(&chip->mdios); 5729 idr_init(&chip->policies); 5730 5731 return chip; 5732 } 5733 5734 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5735 int port, 5736 enum dsa_tag_protocol m) 5737 { 5738 struct mv88e6xxx_chip *chip = ds->priv; 5739 5740 return chip->tag_protocol; 5741 } 5742 5743 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5744 enum dsa_tag_protocol proto) 5745 { 5746 struct mv88e6xxx_chip *chip = ds->priv; 5747 enum dsa_tag_protocol old_protocol; 5748 int err; 5749 5750 switch (proto) { 5751 case DSA_TAG_PROTO_EDSA: 5752 switch (chip->info->edsa_support) { 5753 case MV88E6XXX_EDSA_UNSUPPORTED: 5754 return -EPROTONOSUPPORT; 5755 case MV88E6XXX_EDSA_UNDOCUMENTED: 5756 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5757 fallthrough; 5758 case MV88E6XXX_EDSA_SUPPORTED: 5759 break; 5760 } 5761 break; 5762 case DSA_TAG_PROTO_DSA: 5763 break; 5764 default: 5765 return -EPROTONOSUPPORT; 5766 } 5767 5768 old_protocol = chip->tag_protocol; 5769 chip->tag_protocol = proto; 5770 5771 mv88e6xxx_reg_lock(chip); 5772 err = mv88e6xxx_setup_port_mode(chip, port); 5773 mv88e6xxx_reg_unlock(chip); 5774 5775 if (err) 5776 chip->tag_protocol = old_protocol; 5777 5778 return err; 5779 } 5780 5781 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5782 const struct switchdev_obj_port_mdb *mdb) 5783 { 5784 struct mv88e6xxx_chip *chip = ds->priv; 5785 int err; 5786 5787 mv88e6xxx_reg_lock(chip); 5788 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5789 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5790 mv88e6xxx_reg_unlock(chip); 5791 5792 return err; 5793 } 5794 5795 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5796 const struct switchdev_obj_port_mdb *mdb) 5797 { 5798 struct mv88e6xxx_chip *chip = ds->priv; 5799 int err; 5800 5801 mv88e6xxx_reg_lock(chip); 5802 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5803 mv88e6xxx_reg_unlock(chip); 5804 5805 return err; 5806 } 5807 5808 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5809 struct dsa_mall_mirror_tc_entry *mirror, 5810 bool ingress) 5811 { 5812 enum mv88e6xxx_egress_direction direction = ingress ? 5813 MV88E6XXX_EGRESS_DIR_INGRESS : 5814 MV88E6XXX_EGRESS_DIR_EGRESS; 5815 struct mv88e6xxx_chip *chip = ds->priv; 5816 bool other_mirrors = false; 5817 int i; 5818 int err; 5819 5820 mutex_lock(&chip->reg_lock); 5821 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5822 mirror->to_local_port) { 5823 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5824 other_mirrors |= ingress ? 5825 chip->ports[i].mirror_ingress : 5826 chip->ports[i].mirror_egress; 5827 5828 /* Can't change egress port when other mirror is active */ 5829 if (other_mirrors) { 5830 err = -EBUSY; 5831 goto out; 5832 } 5833 5834 err = mv88e6xxx_set_egress_port(chip, direction, 5835 mirror->to_local_port); 5836 if (err) 5837 goto out; 5838 } 5839 5840 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5841 out: 5842 mutex_unlock(&chip->reg_lock); 5843 5844 return err; 5845 } 5846 5847 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5848 struct dsa_mall_mirror_tc_entry *mirror) 5849 { 5850 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5851 MV88E6XXX_EGRESS_DIR_INGRESS : 5852 MV88E6XXX_EGRESS_DIR_EGRESS; 5853 struct mv88e6xxx_chip *chip = ds->priv; 5854 bool other_mirrors = false; 5855 int i; 5856 5857 mutex_lock(&chip->reg_lock); 5858 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5859 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5860 5861 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5862 other_mirrors |= mirror->ingress ? 5863 chip->ports[i].mirror_ingress : 5864 chip->ports[i].mirror_egress; 5865 5866 /* Reset egress port when no other mirror is active */ 5867 if (!other_mirrors) { 5868 if (mv88e6xxx_set_egress_port(chip, direction, 5869 dsa_upstream_port(ds, port))) 5870 dev_err(ds->dev, "failed to set egress port\n"); 5871 } 5872 5873 mutex_unlock(&chip->reg_lock); 5874 } 5875 5876 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5877 struct switchdev_brport_flags flags, 5878 struct netlink_ext_ack *extack) 5879 { 5880 struct mv88e6xxx_chip *chip = ds->priv; 5881 const struct mv88e6xxx_ops *ops; 5882 5883 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5884 BR_BCAST_FLOOD)) 5885 return -EINVAL; 5886 5887 ops = chip->info->ops; 5888 5889 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5890 return -EINVAL; 5891 5892 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5893 return -EINVAL; 5894 5895 return 0; 5896 } 5897 5898 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5899 struct switchdev_brport_flags flags, 5900 struct netlink_ext_ack *extack) 5901 { 5902 struct mv88e6xxx_chip *chip = ds->priv; 5903 int err = -EOPNOTSUPP; 5904 5905 mv88e6xxx_reg_lock(chip); 5906 5907 if (flags.mask & BR_LEARNING) { 5908 bool learning = !!(flags.val & BR_LEARNING); 5909 u16 pav = learning ? (1 << port) : 0; 5910 5911 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5912 if (err) 5913 goto out; 5914 } 5915 5916 if (flags.mask & BR_FLOOD) { 5917 bool unicast = !!(flags.val & BR_FLOOD); 5918 5919 err = chip->info->ops->port_set_ucast_flood(chip, port, 5920 unicast); 5921 if (err) 5922 goto out; 5923 } 5924 5925 if (flags.mask & BR_MCAST_FLOOD) { 5926 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5927 5928 err = chip->info->ops->port_set_mcast_flood(chip, port, 5929 multicast); 5930 if (err) 5931 goto out; 5932 } 5933 5934 if (flags.mask & BR_BCAST_FLOOD) { 5935 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5936 5937 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5938 if (err) 5939 goto out; 5940 } 5941 5942 out: 5943 mv88e6xxx_reg_unlock(chip); 5944 5945 return err; 5946 } 5947 5948 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5949 struct net_device *lag, 5950 struct netdev_lag_upper_info *info) 5951 { 5952 struct mv88e6xxx_chip *chip = ds->priv; 5953 struct dsa_port *dp; 5954 int id, members = 0; 5955 5956 if (!mv88e6xxx_has_lag(chip)) 5957 return false; 5958 5959 id = dsa_lag_id(ds->dst, lag); 5960 if (id < 0 || id >= ds->num_lag_ids) 5961 return false; 5962 5963 dsa_lag_foreach_port(dp, ds->dst, lag) 5964 /* Includes the port joining the LAG */ 5965 members++; 5966 5967 if (members > 8) 5968 return false; 5969 5970 /* We could potentially relax this to include active 5971 * backup in the future. 5972 */ 5973 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5974 return false; 5975 5976 /* Ideally we would also validate that the hash type matches 5977 * the hardware. Alas, this is always set to unknown on team 5978 * interfaces. 5979 */ 5980 return true; 5981 } 5982 5983 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5984 { 5985 struct mv88e6xxx_chip *chip = ds->priv; 5986 struct dsa_port *dp; 5987 u16 map = 0; 5988 int id; 5989 5990 id = dsa_lag_id(ds->dst, lag); 5991 5992 /* Build the map of all ports to distribute flows destined for 5993 * this LAG. This can be either a local user port, or a DSA 5994 * port if the LAG port is on a remote chip. 5995 */ 5996 dsa_lag_foreach_port(dp, ds->dst, lag) 5997 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5998 5999 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6000 } 6001 6002 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6003 /* Row number corresponds to the number of active members in a 6004 * LAG. Each column states which of the eight hash buckets are 6005 * mapped to the column:th port in the LAG. 6006 * 6007 * Example: In a LAG with three active ports, the second port 6008 * ([2][1]) would be selected for traffic mapped to buckets 6009 * 3,4,5 (0x38). 6010 */ 6011 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6012 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6013 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6014 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6015 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6016 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6017 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6018 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6019 }; 6020 6021 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6022 int num_tx, int nth) 6023 { 6024 u8 active = 0; 6025 int i; 6026 6027 num_tx = num_tx <= 8 ? num_tx : 8; 6028 if (nth < num_tx) 6029 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6030 6031 for (i = 0; i < 8; i++) { 6032 if (BIT(i) & active) 6033 mask[i] |= BIT(port); 6034 } 6035 } 6036 6037 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6038 { 6039 struct mv88e6xxx_chip *chip = ds->priv; 6040 unsigned int id, num_tx; 6041 struct net_device *lag; 6042 struct dsa_port *dp; 6043 int i, err, nth; 6044 u16 mask[8]; 6045 u16 ivec; 6046 6047 /* Assume no port is a member of any LAG. */ 6048 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6049 6050 /* Disable all masks for ports that _are_ members of a LAG. */ 6051 list_for_each_entry(dp, &ds->dst->ports, list) { 6052 if (!dp->lag_dev || dp->ds != ds) 6053 continue; 6054 6055 ivec &= ~BIT(dp->index); 6056 } 6057 6058 for (i = 0; i < 8; i++) 6059 mask[i] = ivec; 6060 6061 /* Enable the correct subset of masks for all LAG ports that 6062 * are in the Tx set. 6063 */ 6064 dsa_lags_foreach_id(id, ds->dst) { 6065 lag = dsa_lag_dev(ds->dst, id); 6066 if (!lag) 6067 continue; 6068 6069 num_tx = 0; 6070 dsa_lag_foreach_port(dp, ds->dst, lag) { 6071 if (dp->lag_tx_enabled) 6072 num_tx++; 6073 } 6074 6075 if (!num_tx) 6076 continue; 6077 6078 nth = 0; 6079 dsa_lag_foreach_port(dp, ds->dst, lag) { 6080 if (!dp->lag_tx_enabled) 6081 continue; 6082 6083 if (dp->ds == ds) 6084 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6085 num_tx, nth); 6086 6087 nth++; 6088 } 6089 } 6090 6091 for (i = 0; i < 8; i++) { 6092 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6093 if (err) 6094 return err; 6095 } 6096 6097 return 0; 6098 } 6099 6100 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6101 struct net_device *lag) 6102 { 6103 int err; 6104 6105 err = mv88e6xxx_lag_sync_masks(ds); 6106 6107 if (!err) 6108 err = mv88e6xxx_lag_sync_map(ds, lag); 6109 6110 return err; 6111 } 6112 6113 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6114 { 6115 struct mv88e6xxx_chip *chip = ds->priv; 6116 int err; 6117 6118 mv88e6xxx_reg_lock(chip); 6119 err = mv88e6xxx_lag_sync_masks(ds); 6120 mv88e6xxx_reg_unlock(chip); 6121 return err; 6122 } 6123 6124 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6125 struct net_device *lag, 6126 struct netdev_lag_upper_info *info) 6127 { 6128 struct mv88e6xxx_chip *chip = ds->priv; 6129 int err, id; 6130 6131 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6132 return -EOPNOTSUPP; 6133 6134 id = dsa_lag_id(ds->dst, lag); 6135 6136 mv88e6xxx_reg_lock(chip); 6137 6138 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6139 if (err) 6140 goto err_unlock; 6141 6142 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6143 if (err) 6144 goto err_clear_trunk; 6145 6146 mv88e6xxx_reg_unlock(chip); 6147 return 0; 6148 6149 err_clear_trunk: 6150 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6151 err_unlock: 6152 mv88e6xxx_reg_unlock(chip); 6153 return err; 6154 } 6155 6156 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6157 struct net_device *lag) 6158 { 6159 struct mv88e6xxx_chip *chip = ds->priv; 6160 int err_sync, err_trunk; 6161 6162 mv88e6xxx_reg_lock(chip); 6163 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6164 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6165 mv88e6xxx_reg_unlock(chip); 6166 return err_sync ? : err_trunk; 6167 } 6168 6169 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6170 int port) 6171 { 6172 struct mv88e6xxx_chip *chip = ds->priv; 6173 int err; 6174 6175 mv88e6xxx_reg_lock(chip); 6176 err = mv88e6xxx_lag_sync_masks(ds); 6177 mv88e6xxx_reg_unlock(chip); 6178 return err; 6179 } 6180 6181 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6182 int port, struct net_device *lag, 6183 struct netdev_lag_upper_info *info) 6184 { 6185 struct mv88e6xxx_chip *chip = ds->priv; 6186 int err; 6187 6188 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6189 return -EOPNOTSUPP; 6190 6191 mv88e6xxx_reg_lock(chip); 6192 6193 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6194 if (err) 6195 goto unlock; 6196 6197 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6198 6199 unlock: 6200 mv88e6xxx_reg_unlock(chip); 6201 return err; 6202 } 6203 6204 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6205 int port, struct net_device *lag) 6206 { 6207 struct mv88e6xxx_chip *chip = ds->priv; 6208 int err_sync, err_pvt; 6209 6210 mv88e6xxx_reg_lock(chip); 6211 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6212 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6213 mv88e6xxx_reg_unlock(chip); 6214 return err_sync ? : err_pvt; 6215 } 6216 6217 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6218 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6219 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6220 .setup = mv88e6xxx_setup, 6221 .teardown = mv88e6xxx_teardown, 6222 .port_setup = mv88e6xxx_port_setup, 6223 .port_teardown = mv88e6xxx_port_teardown, 6224 .phylink_validate = mv88e6xxx_validate, 6225 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6226 .phylink_mac_config = mv88e6xxx_mac_config, 6227 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6228 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6229 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6230 .get_strings = mv88e6xxx_get_strings, 6231 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6232 .get_sset_count = mv88e6xxx_get_sset_count, 6233 .port_enable = mv88e6xxx_port_enable, 6234 .port_disable = mv88e6xxx_port_disable, 6235 .port_max_mtu = mv88e6xxx_get_max_mtu, 6236 .port_change_mtu = mv88e6xxx_change_mtu, 6237 .get_mac_eee = mv88e6xxx_get_mac_eee, 6238 .set_mac_eee = mv88e6xxx_set_mac_eee, 6239 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6240 .get_eeprom = mv88e6xxx_get_eeprom, 6241 .set_eeprom = mv88e6xxx_set_eeprom, 6242 .get_regs_len = mv88e6xxx_get_regs_len, 6243 .get_regs = mv88e6xxx_get_regs, 6244 .get_rxnfc = mv88e6xxx_get_rxnfc, 6245 .set_rxnfc = mv88e6xxx_set_rxnfc, 6246 .set_ageing_time = mv88e6xxx_set_ageing_time, 6247 .port_bridge_join = mv88e6xxx_port_bridge_join, 6248 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6249 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6250 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6251 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6252 .port_fast_age = mv88e6xxx_port_fast_age, 6253 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6254 .port_vlan_add = mv88e6xxx_port_vlan_add, 6255 .port_vlan_del = mv88e6xxx_port_vlan_del, 6256 .port_fdb_add = mv88e6xxx_port_fdb_add, 6257 .port_fdb_del = mv88e6xxx_port_fdb_del, 6258 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6259 .port_mdb_add = mv88e6xxx_port_mdb_add, 6260 .port_mdb_del = mv88e6xxx_port_mdb_del, 6261 .port_mirror_add = mv88e6xxx_port_mirror_add, 6262 .port_mirror_del = mv88e6xxx_port_mirror_del, 6263 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6264 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6265 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6266 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6267 .port_txtstamp = mv88e6xxx_port_txtstamp, 6268 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6269 .get_ts_info = mv88e6xxx_get_ts_info, 6270 .devlink_param_get = mv88e6xxx_devlink_param_get, 6271 .devlink_param_set = mv88e6xxx_devlink_param_set, 6272 .devlink_info_get = mv88e6xxx_devlink_info_get, 6273 .port_lag_change = mv88e6xxx_port_lag_change, 6274 .port_lag_join = mv88e6xxx_port_lag_join, 6275 .port_lag_leave = mv88e6xxx_port_lag_leave, 6276 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6277 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6278 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6279 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6280 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6281 }; 6282 6283 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6284 { 6285 struct device *dev = chip->dev; 6286 struct dsa_switch *ds; 6287 6288 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6289 if (!ds) 6290 return -ENOMEM; 6291 6292 ds->dev = dev; 6293 ds->num_ports = mv88e6xxx_num_ports(chip); 6294 ds->priv = chip; 6295 ds->dev = dev; 6296 ds->ops = &mv88e6xxx_switch_ops; 6297 ds->ageing_time_min = chip->info->age_time_coeff; 6298 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6299 6300 /* Some chips support up to 32, but that requires enabling the 6301 * 5-bit port mode, which we do not support. 640k^W16 ought to 6302 * be enough for anyone. 6303 */ 6304 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6305 6306 dev_set_drvdata(dev, ds); 6307 6308 return dsa_register_switch(ds); 6309 } 6310 6311 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6312 { 6313 dsa_unregister_switch(chip->ds); 6314 } 6315 6316 static const void *pdata_device_get_match_data(struct device *dev) 6317 { 6318 const struct of_device_id *matches = dev->driver->of_match_table; 6319 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6320 6321 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6322 matches++) { 6323 if (!strcmp(pdata->compatible, matches->compatible)) 6324 return matches->data; 6325 } 6326 return NULL; 6327 } 6328 6329 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6330 * would be lost after a power cycle so prevent it to be suspended. 6331 */ 6332 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6333 { 6334 return -EOPNOTSUPP; 6335 } 6336 6337 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6338 { 6339 return 0; 6340 } 6341 6342 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6343 6344 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6345 { 6346 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6347 const struct mv88e6xxx_info *compat_info = NULL; 6348 struct device *dev = &mdiodev->dev; 6349 struct device_node *np = dev->of_node; 6350 struct mv88e6xxx_chip *chip; 6351 int port; 6352 int err; 6353 6354 if (!np && !pdata) 6355 return -EINVAL; 6356 6357 if (np) 6358 compat_info = of_device_get_match_data(dev); 6359 6360 if (pdata) { 6361 compat_info = pdata_device_get_match_data(dev); 6362 6363 if (!pdata->netdev) 6364 return -EINVAL; 6365 6366 for (port = 0; port < DSA_MAX_PORTS; port++) { 6367 if (!(pdata->enabled_ports & (1 << port))) 6368 continue; 6369 if (strcmp(pdata->cd.port_names[port], "cpu")) 6370 continue; 6371 pdata->cd.netdev[port] = &pdata->netdev->dev; 6372 break; 6373 } 6374 } 6375 6376 if (!compat_info) 6377 return -EINVAL; 6378 6379 chip = mv88e6xxx_alloc_chip(dev); 6380 if (!chip) { 6381 err = -ENOMEM; 6382 goto out; 6383 } 6384 6385 chip->info = compat_info; 6386 6387 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6388 if (err) 6389 goto out; 6390 6391 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6392 if (IS_ERR(chip->reset)) { 6393 err = PTR_ERR(chip->reset); 6394 goto out; 6395 } 6396 if (chip->reset) 6397 usleep_range(1000, 2000); 6398 6399 err = mv88e6xxx_detect(chip); 6400 if (err) 6401 goto out; 6402 6403 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6404 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6405 else 6406 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6407 6408 mv88e6xxx_phy_init(chip); 6409 6410 if (chip->info->ops->get_eeprom) { 6411 if (np) 6412 of_property_read_u32(np, "eeprom-length", 6413 &chip->eeprom_len); 6414 else 6415 chip->eeprom_len = pdata->eeprom_len; 6416 } 6417 6418 mv88e6xxx_reg_lock(chip); 6419 err = mv88e6xxx_switch_reset(chip); 6420 mv88e6xxx_reg_unlock(chip); 6421 if (err) 6422 goto out; 6423 6424 if (np) { 6425 chip->irq = of_irq_get(np, 0); 6426 if (chip->irq == -EPROBE_DEFER) { 6427 err = chip->irq; 6428 goto out; 6429 } 6430 } 6431 6432 if (pdata) 6433 chip->irq = pdata->irq; 6434 6435 /* Has to be performed before the MDIO bus is created, because 6436 * the PHYs will link their interrupts to these interrupt 6437 * controllers 6438 */ 6439 mv88e6xxx_reg_lock(chip); 6440 if (chip->irq > 0) 6441 err = mv88e6xxx_g1_irq_setup(chip); 6442 else 6443 err = mv88e6xxx_irq_poll_setup(chip); 6444 mv88e6xxx_reg_unlock(chip); 6445 6446 if (err) 6447 goto out; 6448 6449 if (chip->info->g2_irqs > 0) { 6450 err = mv88e6xxx_g2_irq_setup(chip); 6451 if (err) 6452 goto out_g1_irq; 6453 } 6454 6455 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6456 if (err) 6457 goto out_g2_irq; 6458 6459 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6460 if (err) 6461 goto out_g1_atu_prob_irq; 6462 6463 err = mv88e6xxx_mdios_register(chip, np); 6464 if (err) 6465 goto out_g1_vtu_prob_irq; 6466 6467 err = mv88e6xxx_register_switch(chip); 6468 if (err) 6469 goto out_mdio; 6470 6471 return 0; 6472 6473 out_mdio: 6474 mv88e6xxx_mdios_unregister(chip); 6475 out_g1_vtu_prob_irq: 6476 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6477 out_g1_atu_prob_irq: 6478 mv88e6xxx_g1_atu_prob_irq_free(chip); 6479 out_g2_irq: 6480 if (chip->info->g2_irqs > 0) 6481 mv88e6xxx_g2_irq_free(chip); 6482 out_g1_irq: 6483 if (chip->irq > 0) 6484 mv88e6xxx_g1_irq_free(chip); 6485 else 6486 mv88e6xxx_irq_poll_free(chip); 6487 out: 6488 if (pdata) 6489 dev_put(pdata->netdev); 6490 6491 return err; 6492 } 6493 6494 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6495 { 6496 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6497 struct mv88e6xxx_chip *chip; 6498 6499 if (!ds) 6500 return; 6501 6502 chip = ds->priv; 6503 6504 if (chip->info->ptp_support) { 6505 mv88e6xxx_hwtstamp_free(chip); 6506 mv88e6xxx_ptp_free(chip); 6507 } 6508 6509 mv88e6xxx_phy_destroy(chip); 6510 mv88e6xxx_unregister_switch(chip); 6511 mv88e6xxx_mdios_unregister(chip); 6512 6513 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6514 mv88e6xxx_g1_atu_prob_irq_free(chip); 6515 6516 if (chip->info->g2_irqs > 0) 6517 mv88e6xxx_g2_irq_free(chip); 6518 6519 if (chip->irq > 0) 6520 mv88e6xxx_g1_irq_free(chip); 6521 else 6522 mv88e6xxx_irq_poll_free(chip); 6523 6524 dev_set_drvdata(&mdiodev->dev, NULL); 6525 } 6526 6527 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6528 { 6529 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6530 6531 if (!ds) 6532 return; 6533 6534 dsa_switch_shutdown(ds); 6535 6536 dev_set_drvdata(&mdiodev->dev, NULL); 6537 } 6538 6539 static const struct of_device_id mv88e6xxx_of_match[] = { 6540 { 6541 .compatible = "marvell,mv88e6085", 6542 .data = &mv88e6xxx_table[MV88E6085], 6543 }, 6544 { 6545 .compatible = "marvell,mv88e6190", 6546 .data = &mv88e6xxx_table[MV88E6190], 6547 }, 6548 { 6549 .compatible = "marvell,mv88e6250", 6550 .data = &mv88e6xxx_table[MV88E6250], 6551 }, 6552 { /* sentinel */ }, 6553 }; 6554 6555 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6556 6557 static struct mdio_driver mv88e6xxx_driver = { 6558 .probe = mv88e6xxx_probe, 6559 .remove = mv88e6xxx_remove, 6560 .shutdown = mv88e6xxx_shutdown, 6561 .mdiodrv.driver = { 6562 .name = "mv88e6085", 6563 .of_match_table = mv88e6xxx_of_match, 6564 .pm = &mv88e6xxx_pm_ops, 6565 }, 6566 }; 6567 6568 mdio_module_driver(mv88e6xxx_driver); 6569 6570 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6571 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6572 MODULE_LICENSE("GPL"); 6573