1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 467 { 468 return port >= chip->info->internal_phys_offset && 469 port < chip->info->num_internal_phys + 470 chip->info->internal_phys_offset; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return mv88e6xxx_phy_is_internal(chip, port); 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 693 if (err < 0) 694 dev_err(chip->dev, "p%d: failed to read scratch\n", 695 port); 696 if (err <= 0) 697 return; 698 699 cmode = mv88e6352_get_port4_serdes_cmode(chip); 700 if (cmode < 0) 701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 702 port); 703 else 704 mv88e6xxx_translate_cmode(cmode, supported); 705 } 706 } 707 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 709 struct phylink_config *config) 710 { 711 unsigned long *supported = config->supported_interfaces; 712 713 /* Translate the default cmode */ 714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 715 716 /* No ethtool bits for 200Mbps */ 717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 718 MAC_1000FD; 719 720 /* The C_Mode field is programmable on port 5 */ 721 if (port == 5) { 722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 725 726 config->mac_capabilities |= MAC_2500FD; 727 } 728 } 729 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 731 struct phylink_config *config) 732 { 733 unsigned long *supported = config->supported_interfaces; 734 735 /* Translate the default cmode */ 736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 737 738 /* No ethtool bits for 200Mbps */ 739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 740 MAC_1000FD; 741 742 /* The C_Mode field is programmable on ports 9 and 10 */ 743 if (port == 9 || port == 10) { 744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 747 748 config->mac_capabilities |= MAC_2500FD; 749 } 750 } 751 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 753 struct phylink_config *config) 754 { 755 unsigned long *supported = config->supported_interfaces; 756 757 mv88e6390_phylink_get_caps(chip, port, config); 758 759 /* For the 6x90X, ports 2-7 can be in automedia mode. 760 * (Note that 6x90 doesn't support RXAUI nor XAUI). 761 * 762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 763 * configured for 1000BASE-X, SGMII or 2500BASE-X. 764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 766 * 767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 768 * configured for 1000BASE-X, SGMII or 2500BASE-X. 769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 771 * 772 * For now, be permissive (as the old code was) and allow 1000BASE-X 773 * on ports 2..7. 774 */ 775 if (port >= 2 && port <= 7) 776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 777 778 /* The C_Mode field can also be programmed for 10G speeds */ 779 if (port == 9 || port == 10) { 780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 782 783 config->mac_capabilities |= MAC_10000FD; 784 } 785 } 786 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 788 struct phylink_config *config) 789 { 790 unsigned long *supported = config->supported_interfaces; 791 bool is_6191x = 792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 793 bool is_6361 = 794 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 795 796 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 797 798 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 799 MAC_1000FD; 800 801 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 802 if (port == 0 || port == 9 || port == 10) { 803 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 804 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 805 806 /* 6191X supports >1G modes only on port 10 */ 807 if (!is_6191x || port == 10) { 808 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 809 config->mac_capabilities |= MAC_2500FD; 810 811 /* 6361 only supports up to 2500BaseX */ 812 if (!is_6361) { 813 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 814 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 815 config->mac_capabilities |= MAC_5000FD | 816 MAC_10000FD; 817 } 818 /* FIXME: USXGMII is not supported yet */ 819 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 820 } 821 } 822 823 if (port == 0) { 824 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 825 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 826 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 827 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 828 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 829 } 830 } 831 832 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 833 struct phylink_config *config) 834 { 835 struct mv88e6xxx_chip *chip = ds->priv; 836 837 mv88e6xxx_reg_lock(chip); 838 chip->info->ops->phylink_get_caps(chip, port, config); 839 mv88e6xxx_reg_unlock(chip); 840 841 if (mv88e6xxx_phy_is_internal(chip, port)) { 842 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 843 config->supported_interfaces); 844 /* Internal ports with no phy-mode need GMII for PHYLIB */ 845 __set_bit(PHY_INTERFACE_MODE_GMII, 846 config->supported_interfaces); 847 } 848 } 849 850 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 851 unsigned int mode, phy_interface_t interface) 852 { 853 struct mv88e6xxx_chip *chip = ds->priv; 854 int err = 0; 855 856 /* In inband mode, the link may come up at any time while the link 857 * is not forced down. Force the link down while we reconfigure the 858 * interface mode. 859 */ 860 if (mode == MLO_AN_INBAND && 861 chip->ports[port].interface != interface && 862 chip->info->ops->port_set_link) { 863 mv88e6xxx_reg_lock(chip); 864 err = chip->info->ops->port_set_link(chip, port, 865 LINK_FORCED_DOWN); 866 mv88e6xxx_reg_unlock(chip); 867 } 868 869 return err; 870 } 871 872 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 873 unsigned int mode, 874 const struct phylink_link_state *state) 875 { 876 struct mv88e6xxx_chip *chip = ds->priv; 877 int err = 0; 878 879 mv88e6xxx_reg_lock(chip); 880 881 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 882 err = mv88e6xxx_port_config_interface(chip, port, 883 state->interface); 884 if (err && err != -EOPNOTSUPP) 885 goto err_unlock; 886 887 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 888 state->interface, 889 state->advertising); 890 /* FIXME: we should restart negotiation if something changed - 891 * which is something we get if we convert to using phylinks 892 * PCS operations. 893 */ 894 if (err > 0) 895 err = 0; 896 } 897 898 err_unlock: 899 mv88e6xxx_reg_unlock(chip); 900 901 if (err && err != -EOPNOTSUPP) 902 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 903 } 904 905 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 906 unsigned int mode, phy_interface_t interface) 907 { 908 struct mv88e6xxx_chip *chip = ds->priv; 909 int err = 0; 910 911 /* Undo the forced down state above after completing configuration 912 * irrespective of its state on entry, which allows the link to come 913 * up in the in-band case where there is no separate SERDES. Also 914 * ensure that the link can come up if the PPU is in use and we are 915 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 916 */ 917 mv88e6xxx_reg_lock(chip); 918 919 if (chip->info->ops->port_set_link && 920 ((mode == MLO_AN_INBAND && 921 chip->ports[port].interface != interface) || 922 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 923 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 924 925 mv88e6xxx_reg_unlock(chip); 926 927 chip->ports[port].interface = interface; 928 929 return err; 930 } 931 932 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 933 unsigned int mode, 934 phy_interface_t interface) 935 { 936 struct mv88e6xxx_chip *chip = ds->priv; 937 const struct mv88e6xxx_ops *ops; 938 int err = 0; 939 940 ops = chip->info->ops; 941 942 mv88e6xxx_reg_lock(chip); 943 /* Force the link down if we know the port may not be automatically 944 * updated by the switch or if we are using fixed-link mode. 945 */ 946 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 947 mode == MLO_AN_FIXED) && ops->port_sync_link) 948 err = ops->port_sync_link(chip, port, mode, false); 949 950 if (!err && ops->port_set_speed_duplex) 951 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 952 DUPLEX_UNFORCED); 953 mv88e6xxx_reg_unlock(chip); 954 955 if (err) 956 dev_err(chip->dev, 957 "p%d: failed to force MAC link down\n", port); 958 } 959 960 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 961 unsigned int mode, phy_interface_t interface, 962 struct phy_device *phydev, 963 int speed, int duplex, 964 bool tx_pause, bool rx_pause) 965 { 966 struct mv88e6xxx_chip *chip = ds->priv; 967 const struct mv88e6xxx_ops *ops; 968 int err = 0; 969 970 ops = chip->info->ops; 971 972 mv88e6xxx_reg_lock(chip); 973 /* Configure and force the link up if we know that the port may not 974 * automatically updated by the switch or if we are using fixed-link 975 * mode. 976 */ 977 if (!mv88e6xxx_port_ppu_updates(chip, port) || 978 mode == MLO_AN_FIXED) { 979 /* FIXME: for an automedia port, should we force the link 980 * down here - what if the link comes up due to "other" media 981 * while we're bringing the port up, how is the exclusivity 982 * handled in the Marvell hardware? E.g. port 2 on 88E6390 983 * shared between internal PHY and Serdes. 984 */ 985 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 986 duplex); 987 if (err) 988 goto error; 989 990 if (ops->port_set_speed_duplex) { 991 err = ops->port_set_speed_duplex(chip, port, 992 speed, duplex); 993 if (err && err != -EOPNOTSUPP) 994 goto error; 995 } 996 997 if (ops->port_sync_link) 998 err = ops->port_sync_link(chip, port, mode, true); 999 } 1000 error: 1001 mv88e6xxx_reg_unlock(chip); 1002 1003 if (err && err != -EOPNOTSUPP) 1004 dev_err(ds->dev, 1005 "p%d: failed to configure MAC link up\n", port); 1006 } 1007 1008 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1009 { 1010 if (!chip->info->ops->stats_snapshot) 1011 return -EOPNOTSUPP; 1012 1013 return chip->info->ops->stats_snapshot(chip, port); 1014 } 1015 1016 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1017 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1018 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1019 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1020 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1021 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1022 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1023 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1024 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1025 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1026 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1027 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1028 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1029 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1030 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1031 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1032 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1033 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1034 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1035 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1036 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1037 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1038 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1039 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1040 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1041 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1042 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1043 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1044 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1045 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1046 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1047 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1048 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1049 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1050 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1051 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1052 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1053 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1054 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1055 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1056 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1057 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1058 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1059 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1060 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1061 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1062 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1063 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1064 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1065 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1066 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1067 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1068 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1069 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1070 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1071 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1072 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1073 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1074 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1075 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1076 }; 1077 1078 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1079 struct mv88e6xxx_hw_stat *s, 1080 int port, u16 bank1_select, 1081 u16 histogram) 1082 { 1083 u32 low; 1084 u32 high = 0; 1085 u16 reg = 0; 1086 int err; 1087 u64 value; 1088 1089 switch (s->type) { 1090 case STATS_TYPE_PORT: 1091 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1092 if (err) 1093 return U64_MAX; 1094 1095 low = reg; 1096 if (s->size == 4) { 1097 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1098 if (err) 1099 return U64_MAX; 1100 low |= ((u32)reg) << 16; 1101 } 1102 break; 1103 case STATS_TYPE_BANK1: 1104 reg = bank1_select; 1105 fallthrough; 1106 case STATS_TYPE_BANK0: 1107 reg |= s->reg | histogram; 1108 mv88e6xxx_g1_stats_read(chip, reg, &low); 1109 if (s->size == 8) 1110 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1111 break; 1112 default: 1113 return U64_MAX; 1114 } 1115 value = (((u64)high) << 32) | low; 1116 return value; 1117 } 1118 1119 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1120 uint8_t *data, int types) 1121 { 1122 struct mv88e6xxx_hw_stat *stat; 1123 int i, j; 1124 1125 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1126 stat = &mv88e6xxx_hw_stats[i]; 1127 if (stat->type & types) { 1128 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1129 ETH_GSTRING_LEN); 1130 j++; 1131 } 1132 } 1133 1134 return j; 1135 } 1136 1137 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1138 uint8_t *data) 1139 { 1140 return mv88e6xxx_stats_get_strings(chip, data, 1141 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1142 } 1143 1144 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1145 uint8_t *data) 1146 { 1147 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1148 } 1149 1150 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1151 uint8_t *data) 1152 { 1153 return mv88e6xxx_stats_get_strings(chip, data, 1154 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1155 } 1156 1157 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1158 "atu_member_violation", 1159 "atu_miss_violation", 1160 "atu_full_violation", 1161 "vtu_member_violation", 1162 "vtu_miss_violation", 1163 }; 1164 1165 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1166 { 1167 unsigned int i; 1168 1169 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1170 strscpy(data + i * ETH_GSTRING_LEN, 1171 mv88e6xxx_atu_vtu_stats_strings[i], 1172 ETH_GSTRING_LEN); 1173 } 1174 1175 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1176 u32 stringset, uint8_t *data) 1177 { 1178 struct mv88e6xxx_chip *chip = ds->priv; 1179 int count = 0; 1180 1181 if (stringset != ETH_SS_STATS) 1182 return; 1183 1184 mv88e6xxx_reg_lock(chip); 1185 1186 if (chip->info->ops->stats_get_strings) 1187 count = chip->info->ops->stats_get_strings(chip, data); 1188 1189 if (chip->info->ops->serdes_get_strings) { 1190 data += count * ETH_GSTRING_LEN; 1191 count = chip->info->ops->serdes_get_strings(chip, port, data); 1192 } 1193 1194 data += count * ETH_GSTRING_LEN; 1195 mv88e6xxx_atu_vtu_get_strings(data); 1196 1197 mv88e6xxx_reg_unlock(chip); 1198 } 1199 1200 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1201 int types) 1202 { 1203 struct mv88e6xxx_hw_stat *stat; 1204 int i, j; 1205 1206 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1207 stat = &mv88e6xxx_hw_stats[i]; 1208 if (stat->type & types) 1209 j++; 1210 } 1211 return j; 1212 } 1213 1214 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1215 { 1216 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1217 STATS_TYPE_PORT); 1218 } 1219 1220 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1221 { 1222 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1223 } 1224 1225 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1226 { 1227 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1228 STATS_TYPE_BANK1); 1229 } 1230 1231 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1232 { 1233 struct mv88e6xxx_chip *chip = ds->priv; 1234 int serdes_count = 0; 1235 int count = 0; 1236 1237 if (sset != ETH_SS_STATS) 1238 return 0; 1239 1240 mv88e6xxx_reg_lock(chip); 1241 if (chip->info->ops->stats_get_sset_count) 1242 count = chip->info->ops->stats_get_sset_count(chip); 1243 if (count < 0) 1244 goto out; 1245 1246 if (chip->info->ops->serdes_get_sset_count) 1247 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1248 port); 1249 if (serdes_count < 0) { 1250 count = serdes_count; 1251 goto out; 1252 } 1253 count += serdes_count; 1254 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1255 1256 out: 1257 mv88e6xxx_reg_unlock(chip); 1258 1259 return count; 1260 } 1261 1262 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1263 uint64_t *data, int types, 1264 u16 bank1_select, u16 histogram) 1265 { 1266 struct mv88e6xxx_hw_stat *stat; 1267 int i, j; 1268 1269 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1270 stat = &mv88e6xxx_hw_stats[i]; 1271 if (stat->type & types) { 1272 mv88e6xxx_reg_lock(chip); 1273 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1274 bank1_select, 1275 histogram); 1276 mv88e6xxx_reg_unlock(chip); 1277 1278 j++; 1279 } 1280 } 1281 return j; 1282 } 1283 1284 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1285 uint64_t *data) 1286 { 1287 return mv88e6xxx_stats_get_stats(chip, port, data, 1288 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1289 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1290 } 1291 1292 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1293 uint64_t *data) 1294 { 1295 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1296 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1297 } 1298 1299 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1300 uint64_t *data) 1301 { 1302 return mv88e6xxx_stats_get_stats(chip, port, data, 1303 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1304 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1305 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1306 } 1307 1308 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1309 uint64_t *data) 1310 { 1311 return mv88e6xxx_stats_get_stats(chip, port, data, 1312 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1313 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1314 0); 1315 } 1316 1317 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1318 uint64_t *data) 1319 { 1320 *data++ = chip->ports[port].atu_member_violation; 1321 *data++ = chip->ports[port].atu_miss_violation; 1322 *data++ = chip->ports[port].atu_full_violation; 1323 *data++ = chip->ports[port].vtu_member_violation; 1324 *data++ = chip->ports[port].vtu_miss_violation; 1325 } 1326 1327 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1328 uint64_t *data) 1329 { 1330 int count = 0; 1331 1332 if (chip->info->ops->stats_get_stats) 1333 count = chip->info->ops->stats_get_stats(chip, port, data); 1334 1335 mv88e6xxx_reg_lock(chip); 1336 if (chip->info->ops->serdes_get_stats) { 1337 data += count; 1338 count = chip->info->ops->serdes_get_stats(chip, port, data); 1339 } 1340 data += count; 1341 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1342 mv88e6xxx_reg_unlock(chip); 1343 } 1344 1345 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1346 uint64_t *data) 1347 { 1348 struct mv88e6xxx_chip *chip = ds->priv; 1349 int ret; 1350 1351 mv88e6xxx_reg_lock(chip); 1352 1353 ret = mv88e6xxx_stats_snapshot(chip, port); 1354 mv88e6xxx_reg_unlock(chip); 1355 1356 if (ret < 0) 1357 return; 1358 1359 mv88e6xxx_get_stats(chip, port, data); 1360 1361 } 1362 1363 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1364 { 1365 struct mv88e6xxx_chip *chip = ds->priv; 1366 int len; 1367 1368 len = 32 * sizeof(u16); 1369 if (chip->info->ops->serdes_get_regs_len) 1370 len += chip->info->ops->serdes_get_regs_len(chip, port); 1371 1372 return len; 1373 } 1374 1375 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1376 struct ethtool_regs *regs, void *_p) 1377 { 1378 struct mv88e6xxx_chip *chip = ds->priv; 1379 int err; 1380 u16 reg; 1381 u16 *p = _p; 1382 int i; 1383 1384 regs->version = chip->info->prod_num; 1385 1386 memset(p, 0xff, 32 * sizeof(u16)); 1387 1388 mv88e6xxx_reg_lock(chip); 1389 1390 for (i = 0; i < 32; i++) { 1391 1392 err = mv88e6xxx_port_read(chip, port, i, ®); 1393 if (!err) 1394 p[i] = reg; 1395 } 1396 1397 if (chip->info->ops->serdes_get_regs) 1398 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1399 1400 mv88e6xxx_reg_unlock(chip); 1401 } 1402 1403 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1404 struct ethtool_eee *e) 1405 { 1406 /* Nothing to do on the port's MAC */ 1407 return 0; 1408 } 1409 1410 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1411 struct ethtool_eee *e) 1412 { 1413 /* Nothing to do on the port's MAC */ 1414 return 0; 1415 } 1416 1417 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1418 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1419 { 1420 struct dsa_switch *ds = chip->ds; 1421 struct dsa_switch_tree *dst = ds->dst; 1422 struct dsa_port *dp, *other_dp; 1423 bool found = false; 1424 u16 pvlan; 1425 1426 /* dev is a physical switch */ 1427 if (dev <= dst->last_switch) { 1428 list_for_each_entry(dp, &dst->ports, list) { 1429 if (dp->ds->index == dev && dp->index == port) { 1430 /* dp might be a DSA link or a user port, so it 1431 * might or might not have a bridge. 1432 * Use the "found" variable for both cases. 1433 */ 1434 found = true; 1435 break; 1436 } 1437 } 1438 /* dev is a virtual bridge */ 1439 } else { 1440 list_for_each_entry(dp, &dst->ports, list) { 1441 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1442 1443 if (!bridge_num) 1444 continue; 1445 1446 if (bridge_num + dst->last_switch != dev) 1447 continue; 1448 1449 found = true; 1450 break; 1451 } 1452 } 1453 1454 /* Prevent frames from unknown switch or virtual bridge */ 1455 if (!found) 1456 return 0; 1457 1458 /* Frames from DSA links and CPU ports can egress any local port */ 1459 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1460 return mv88e6xxx_port_mask(chip); 1461 1462 pvlan = 0; 1463 1464 /* Frames from standalone user ports can only egress on the 1465 * upstream port. 1466 */ 1467 if (!dsa_port_bridge_dev_get(dp)) 1468 return BIT(dsa_switch_upstream_port(ds)); 1469 1470 /* Frames from bridged user ports can egress any local DSA 1471 * links and CPU ports, as well as any local member of their 1472 * bridge group. 1473 */ 1474 dsa_switch_for_each_port(other_dp, ds) 1475 if (other_dp->type == DSA_PORT_TYPE_CPU || 1476 other_dp->type == DSA_PORT_TYPE_DSA || 1477 dsa_port_bridge_same(dp, other_dp)) 1478 pvlan |= BIT(other_dp->index); 1479 1480 return pvlan; 1481 } 1482 1483 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1484 { 1485 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1486 1487 /* prevent frames from going back out of the port they came in on */ 1488 output_ports &= ~BIT(port); 1489 1490 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1491 } 1492 1493 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1494 u8 state) 1495 { 1496 struct mv88e6xxx_chip *chip = ds->priv; 1497 int err; 1498 1499 mv88e6xxx_reg_lock(chip); 1500 err = mv88e6xxx_port_set_state(chip, port, state); 1501 mv88e6xxx_reg_unlock(chip); 1502 1503 if (err) 1504 dev_err(ds->dev, "p%d: failed to update state\n", port); 1505 } 1506 1507 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1508 { 1509 int err; 1510 1511 if (chip->info->ops->ieee_pri_map) { 1512 err = chip->info->ops->ieee_pri_map(chip); 1513 if (err) 1514 return err; 1515 } 1516 1517 if (chip->info->ops->ip_pri_map) { 1518 err = chip->info->ops->ip_pri_map(chip); 1519 if (err) 1520 return err; 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1527 { 1528 struct dsa_switch *ds = chip->ds; 1529 int target, port; 1530 int err; 1531 1532 if (!chip->info->global2_addr) 1533 return 0; 1534 1535 /* Initialize the routing port to the 32 possible target devices */ 1536 for (target = 0; target < 32; target++) { 1537 port = dsa_routing_port(ds, target); 1538 if (port == ds->num_ports) 1539 port = 0x1f; 1540 1541 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1542 if (err) 1543 return err; 1544 } 1545 1546 if (chip->info->ops->set_cascade_port) { 1547 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1548 err = chip->info->ops->set_cascade_port(chip, port); 1549 if (err) 1550 return err; 1551 } 1552 1553 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1554 if (err) 1555 return err; 1556 1557 return 0; 1558 } 1559 1560 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1561 { 1562 /* Clear all trunk masks and mapping */ 1563 if (chip->info->global2_addr) 1564 return mv88e6xxx_g2_trunk_clear(chip); 1565 1566 return 0; 1567 } 1568 1569 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1570 { 1571 if (chip->info->ops->rmu_disable) 1572 return chip->info->ops->rmu_disable(chip); 1573 1574 return 0; 1575 } 1576 1577 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1578 { 1579 if (chip->info->ops->pot_clear) 1580 return chip->info->ops->pot_clear(chip); 1581 1582 return 0; 1583 } 1584 1585 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1586 { 1587 if (chip->info->ops->mgmt_rsvd2cpu) 1588 return chip->info->ops->mgmt_rsvd2cpu(chip); 1589 1590 return 0; 1591 } 1592 1593 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1594 { 1595 int err; 1596 1597 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1598 if (err) 1599 return err; 1600 1601 /* The chips that have a "learn2all" bit in Global1, ATU 1602 * Control are precisely those whose port registers have a 1603 * Message Port bit in Port Control 1 and hence implement 1604 * ->port_setup_message_port. 1605 */ 1606 if (chip->info->ops->port_setup_message_port) { 1607 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1608 if (err) 1609 return err; 1610 } 1611 1612 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1613 } 1614 1615 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1616 { 1617 int port; 1618 int err; 1619 1620 if (!chip->info->ops->irl_init_all) 1621 return 0; 1622 1623 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1624 /* Disable ingress rate limiting by resetting all per port 1625 * ingress rate limit resources to their initial state. 1626 */ 1627 err = chip->info->ops->irl_init_all(chip, port); 1628 if (err) 1629 return err; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1636 { 1637 if (chip->info->ops->set_switch_mac) { 1638 u8 addr[ETH_ALEN]; 1639 1640 eth_random_addr(addr); 1641 1642 return chip->info->ops->set_switch_mac(chip, addr); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1649 { 1650 struct dsa_switch_tree *dst = chip->ds->dst; 1651 struct dsa_switch *ds; 1652 struct dsa_port *dp; 1653 u16 pvlan = 0; 1654 1655 if (!mv88e6xxx_has_pvt(chip)) 1656 return 0; 1657 1658 /* Skip the local source device, which uses in-chip port VLAN */ 1659 if (dev != chip->ds->index) { 1660 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1661 1662 ds = dsa_switch_find(dst->index, dev); 1663 dp = ds ? dsa_to_port(ds, port) : NULL; 1664 if (dp && dp->lag) { 1665 /* As the PVT is used to limit flooding of 1666 * FORWARD frames, which use the LAG ID as the 1667 * source port, we must translate dev/port to 1668 * the special "LAG device" in the PVT, using 1669 * the LAG ID (one-based) as the port number 1670 * (zero-based). 1671 */ 1672 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1673 port = dsa_port_lag_id_get(dp) - 1; 1674 } 1675 } 1676 1677 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1678 } 1679 1680 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1681 { 1682 int dev, port; 1683 int err; 1684 1685 if (!mv88e6xxx_has_pvt(chip)) 1686 return 0; 1687 1688 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1689 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1690 */ 1691 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1692 if (err) 1693 return err; 1694 1695 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1696 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1697 err = mv88e6xxx_pvt_map(chip, dev, port); 1698 if (err) 1699 return err; 1700 } 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1707 u16 fid) 1708 { 1709 if (dsa_to_port(chip->ds, port)->lag) 1710 /* Hardware is incapable of fast-aging a LAG through a 1711 * regular ATU move operation. Until we have something 1712 * more fancy in place this is a no-op. 1713 */ 1714 return -EOPNOTSUPP; 1715 1716 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1717 } 1718 1719 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1720 { 1721 struct mv88e6xxx_chip *chip = ds->priv; 1722 int err; 1723 1724 mv88e6xxx_reg_lock(chip); 1725 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1726 mv88e6xxx_reg_unlock(chip); 1727 1728 if (err) 1729 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1730 port, err); 1731 } 1732 1733 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1734 { 1735 if (!mv88e6xxx_max_vid(chip)) 1736 return 0; 1737 1738 return mv88e6xxx_g1_vtu_flush(chip); 1739 } 1740 1741 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1742 struct mv88e6xxx_vtu_entry *entry) 1743 { 1744 int err; 1745 1746 if (!chip->info->ops->vtu_getnext) 1747 return -EOPNOTSUPP; 1748 1749 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1750 entry->valid = false; 1751 1752 err = chip->info->ops->vtu_getnext(chip, entry); 1753 1754 if (entry->vid != vid) 1755 entry->valid = false; 1756 1757 return err; 1758 } 1759 1760 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1761 int (*cb)(struct mv88e6xxx_chip *chip, 1762 const struct mv88e6xxx_vtu_entry *entry, 1763 void *priv), 1764 void *priv) 1765 { 1766 struct mv88e6xxx_vtu_entry entry = { 1767 .vid = mv88e6xxx_max_vid(chip), 1768 .valid = false, 1769 }; 1770 int err; 1771 1772 if (!chip->info->ops->vtu_getnext) 1773 return -EOPNOTSUPP; 1774 1775 do { 1776 err = chip->info->ops->vtu_getnext(chip, &entry); 1777 if (err) 1778 return err; 1779 1780 if (!entry.valid) 1781 break; 1782 1783 err = cb(chip, &entry, priv); 1784 if (err) 1785 return err; 1786 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1787 1788 return 0; 1789 } 1790 1791 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1792 struct mv88e6xxx_vtu_entry *entry) 1793 { 1794 if (!chip->info->ops->vtu_loadpurge) 1795 return -EOPNOTSUPP; 1796 1797 return chip->info->ops->vtu_loadpurge(chip, entry); 1798 } 1799 1800 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1801 const struct mv88e6xxx_vtu_entry *entry, 1802 void *_fid_bitmap) 1803 { 1804 unsigned long *fid_bitmap = _fid_bitmap; 1805 1806 set_bit(entry->fid, fid_bitmap); 1807 return 0; 1808 } 1809 1810 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1811 { 1812 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1813 1814 /* Every FID has an associated VID, so walking the VTU 1815 * will discover the full set of FIDs in use. 1816 */ 1817 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1818 } 1819 1820 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1821 { 1822 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1823 int err; 1824 1825 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1826 if (err) 1827 return err; 1828 1829 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1830 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1831 return -ENOSPC; 1832 1833 /* Clear the database */ 1834 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1835 } 1836 1837 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1838 struct mv88e6xxx_stu_entry *entry) 1839 { 1840 if (!chip->info->ops->stu_loadpurge) 1841 return -EOPNOTSUPP; 1842 1843 return chip->info->ops->stu_loadpurge(chip, entry); 1844 } 1845 1846 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1847 { 1848 struct mv88e6xxx_stu_entry stu = { 1849 .valid = true, 1850 .sid = 0 1851 }; 1852 1853 if (!mv88e6xxx_has_stu(chip)) 1854 return 0; 1855 1856 /* Make sure that SID 0 is always valid. This is used by VTU 1857 * entries that do not make use of the STU, e.g. when creating 1858 * a VLAN upper on a port that is also part of a VLAN 1859 * filtering bridge. 1860 */ 1861 return mv88e6xxx_stu_loadpurge(chip, &stu); 1862 } 1863 1864 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1865 { 1866 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1867 struct mv88e6xxx_mst *mst; 1868 1869 __set_bit(0, busy); 1870 1871 list_for_each_entry(mst, &chip->msts, node) 1872 __set_bit(mst->stu.sid, busy); 1873 1874 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1875 1876 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1877 } 1878 1879 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1880 { 1881 struct mv88e6xxx_mst *mst, *tmp; 1882 int err; 1883 1884 if (!sid) 1885 return 0; 1886 1887 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1888 if (mst->stu.sid != sid) 1889 continue; 1890 1891 if (!refcount_dec_and_test(&mst->refcnt)) 1892 return 0; 1893 1894 mst->stu.valid = false; 1895 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1896 if (err) { 1897 refcount_set(&mst->refcnt, 1); 1898 return err; 1899 } 1900 1901 list_del(&mst->node); 1902 kfree(mst); 1903 return 0; 1904 } 1905 1906 return -ENOENT; 1907 } 1908 1909 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1910 u16 msti, u8 *sid) 1911 { 1912 struct mv88e6xxx_mst *mst; 1913 int err, i; 1914 1915 if (!mv88e6xxx_has_stu(chip)) { 1916 err = -EOPNOTSUPP; 1917 goto err; 1918 } 1919 1920 if (!msti) { 1921 *sid = 0; 1922 return 0; 1923 } 1924 1925 list_for_each_entry(mst, &chip->msts, node) { 1926 if (mst->br == br && mst->msti == msti) { 1927 refcount_inc(&mst->refcnt); 1928 *sid = mst->stu.sid; 1929 return 0; 1930 } 1931 } 1932 1933 err = mv88e6xxx_sid_get(chip, sid); 1934 if (err) 1935 goto err; 1936 1937 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1938 if (!mst) { 1939 err = -ENOMEM; 1940 goto err; 1941 } 1942 1943 INIT_LIST_HEAD(&mst->node); 1944 refcount_set(&mst->refcnt, 1); 1945 mst->br = br; 1946 mst->msti = msti; 1947 mst->stu.valid = true; 1948 mst->stu.sid = *sid; 1949 1950 /* The bridge starts out all ports in the disabled state. But 1951 * a STU state of disabled means to go by the port-global 1952 * state. So we set all user port's initial state to blocking, 1953 * to match the bridge's behavior. 1954 */ 1955 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1956 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1957 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1958 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1959 1960 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1961 if (err) 1962 goto err_free; 1963 1964 list_add_tail(&mst->node, &chip->msts); 1965 return 0; 1966 1967 err_free: 1968 kfree(mst); 1969 err: 1970 return err; 1971 } 1972 1973 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1974 const struct switchdev_mst_state *st) 1975 { 1976 struct dsa_port *dp = dsa_to_port(ds, port); 1977 struct mv88e6xxx_chip *chip = ds->priv; 1978 struct mv88e6xxx_mst *mst; 1979 u8 state; 1980 int err; 1981 1982 if (!mv88e6xxx_has_stu(chip)) 1983 return -EOPNOTSUPP; 1984 1985 switch (st->state) { 1986 case BR_STATE_DISABLED: 1987 case BR_STATE_BLOCKING: 1988 case BR_STATE_LISTENING: 1989 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1990 break; 1991 case BR_STATE_LEARNING: 1992 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1993 break; 1994 case BR_STATE_FORWARDING: 1995 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1996 break; 1997 default: 1998 return -EINVAL; 1999 } 2000 2001 list_for_each_entry(mst, &chip->msts, node) { 2002 if (mst->br == dsa_port_bridge_dev_get(dp) && 2003 mst->msti == st->msti) { 2004 if (mst->stu.state[port] == state) 2005 return 0; 2006 2007 mst->stu.state[port] = state; 2008 mv88e6xxx_reg_lock(chip); 2009 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2010 mv88e6xxx_reg_unlock(chip); 2011 return err; 2012 } 2013 } 2014 2015 return -ENOENT; 2016 } 2017 2018 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2019 u16 vid) 2020 { 2021 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2022 struct mv88e6xxx_chip *chip = ds->priv; 2023 struct mv88e6xxx_vtu_entry vlan; 2024 int err; 2025 2026 /* DSA and CPU ports have to be members of multiple vlans */ 2027 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2028 return 0; 2029 2030 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2031 if (err) 2032 return err; 2033 2034 if (!vlan.valid) 2035 return 0; 2036 2037 dsa_switch_for_each_user_port(other_dp, ds) { 2038 struct net_device *other_br; 2039 2040 if (vlan.member[other_dp->index] == 2041 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2042 continue; 2043 2044 if (dsa_port_bridge_same(dp, other_dp)) 2045 break; /* same bridge, check next VLAN */ 2046 2047 other_br = dsa_port_bridge_dev_get(other_dp); 2048 if (!other_br) 2049 continue; 2050 2051 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2052 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2053 return -EOPNOTSUPP; 2054 } 2055 2056 return 0; 2057 } 2058 2059 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2060 { 2061 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2062 struct net_device *br = dsa_port_bridge_dev_get(dp); 2063 struct mv88e6xxx_port *p = &chip->ports[port]; 2064 u16 pvid = MV88E6XXX_VID_STANDALONE; 2065 bool drop_untagged = false; 2066 int err; 2067 2068 if (br) { 2069 if (br_vlan_enabled(br)) { 2070 pvid = p->bridge_pvid.vid; 2071 drop_untagged = !p->bridge_pvid.valid; 2072 } else { 2073 pvid = MV88E6XXX_VID_BRIDGED; 2074 } 2075 } 2076 2077 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2078 if (err) 2079 return err; 2080 2081 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2082 } 2083 2084 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2085 bool vlan_filtering, 2086 struct netlink_ext_ack *extack) 2087 { 2088 struct mv88e6xxx_chip *chip = ds->priv; 2089 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2090 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2091 int err; 2092 2093 if (!mv88e6xxx_max_vid(chip)) 2094 return -EOPNOTSUPP; 2095 2096 mv88e6xxx_reg_lock(chip); 2097 2098 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2099 if (err) 2100 goto unlock; 2101 2102 err = mv88e6xxx_port_commit_pvid(chip, port); 2103 if (err) 2104 goto unlock; 2105 2106 unlock: 2107 mv88e6xxx_reg_unlock(chip); 2108 2109 return err; 2110 } 2111 2112 static int 2113 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2114 const struct switchdev_obj_port_vlan *vlan) 2115 { 2116 struct mv88e6xxx_chip *chip = ds->priv; 2117 int err; 2118 2119 if (!mv88e6xxx_max_vid(chip)) 2120 return -EOPNOTSUPP; 2121 2122 /* If the requested port doesn't belong to the same bridge as the VLAN 2123 * members, do not support it (yet) and fallback to software VLAN. 2124 */ 2125 mv88e6xxx_reg_lock(chip); 2126 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2127 mv88e6xxx_reg_unlock(chip); 2128 2129 return err; 2130 } 2131 2132 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2133 const unsigned char *addr, u16 vid, 2134 u8 state) 2135 { 2136 struct mv88e6xxx_atu_entry entry; 2137 struct mv88e6xxx_vtu_entry vlan; 2138 u16 fid; 2139 int err; 2140 2141 /* Ports have two private address databases: one for when the port is 2142 * standalone and one for when the port is under a bridge and the 2143 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2144 * address database to remain 100% empty, so we never load an ATU entry 2145 * into a standalone port's database. Therefore, translate the null 2146 * VLAN ID into the port's database used for VLAN-unaware bridging. 2147 */ 2148 if (vid == 0) { 2149 fid = MV88E6XXX_FID_BRIDGED; 2150 } else { 2151 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2152 if (err) 2153 return err; 2154 2155 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2156 if (!vlan.valid) 2157 return -EOPNOTSUPP; 2158 2159 fid = vlan.fid; 2160 } 2161 2162 entry.state = 0; 2163 ether_addr_copy(entry.mac, addr); 2164 eth_addr_dec(entry.mac); 2165 2166 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2167 if (err) 2168 return err; 2169 2170 /* Initialize a fresh ATU entry if it isn't found */ 2171 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2172 memset(&entry, 0, sizeof(entry)); 2173 ether_addr_copy(entry.mac, addr); 2174 } 2175 2176 /* Purge the ATU entry only if no port is using it anymore */ 2177 if (!state) { 2178 entry.portvec &= ~BIT(port); 2179 if (!entry.portvec) 2180 entry.state = 0; 2181 } else { 2182 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2183 entry.portvec = BIT(port); 2184 else 2185 entry.portvec |= BIT(port); 2186 2187 entry.state = state; 2188 } 2189 2190 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2191 } 2192 2193 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2194 const struct mv88e6xxx_policy *policy) 2195 { 2196 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2197 enum mv88e6xxx_policy_action action = policy->action; 2198 const u8 *addr = policy->addr; 2199 u16 vid = policy->vid; 2200 u8 state; 2201 int err; 2202 int id; 2203 2204 if (!chip->info->ops->port_set_policy) 2205 return -EOPNOTSUPP; 2206 2207 switch (mapping) { 2208 case MV88E6XXX_POLICY_MAPPING_DA: 2209 case MV88E6XXX_POLICY_MAPPING_SA: 2210 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2211 state = 0; /* Dissociate the port and address */ 2212 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2213 is_multicast_ether_addr(addr)) 2214 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2215 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2216 is_unicast_ether_addr(addr)) 2217 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2218 else 2219 return -EOPNOTSUPP; 2220 2221 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2222 state); 2223 if (err) 2224 return err; 2225 break; 2226 default: 2227 return -EOPNOTSUPP; 2228 } 2229 2230 /* Skip the port's policy clearing if the mapping is still in use */ 2231 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2232 idr_for_each_entry(&chip->policies, policy, id) 2233 if (policy->port == port && 2234 policy->mapping == mapping && 2235 policy->action != action) 2236 return 0; 2237 2238 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2239 } 2240 2241 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2242 struct ethtool_rx_flow_spec *fs) 2243 { 2244 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2245 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2246 enum mv88e6xxx_policy_mapping mapping; 2247 enum mv88e6xxx_policy_action action; 2248 struct mv88e6xxx_policy *policy; 2249 u16 vid = 0; 2250 u8 *addr; 2251 int err; 2252 int id; 2253 2254 if (fs->location != RX_CLS_LOC_ANY) 2255 return -EINVAL; 2256 2257 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2258 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2259 else 2260 return -EOPNOTSUPP; 2261 2262 switch (fs->flow_type & ~FLOW_EXT) { 2263 case ETHER_FLOW: 2264 if (!is_zero_ether_addr(mac_mask->h_dest) && 2265 is_zero_ether_addr(mac_mask->h_source)) { 2266 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2267 addr = mac_entry->h_dest; 2268 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2269 !is_zero_ether_addr(mac_mask->h_source)) { 2270 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2271 addr = mac_entry->h_source; 2272 } else { 2273 /* Cannot support DA and SA mapping in the same rule */ 2274 return -EOPNOTSUPP; 2275 } 2276 break; 2277 default: 2278 return -EOPNOTSUPP; 2279 } 2280 2281 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2282 if (fs->m_ext.vlan_tci != htons(0xffff)) 2283 return -EOPNOTSUPP; 2284 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2285 } 2286 2287 idr_for_each_entry(&chip->policies, policy, id) { 2288 if (policy->port == port && policy->mapping == mapping && 2289 policy->action == action && policy->vid == vid && 2290 ether_addr_equal(policy->addr, addr)) 2291 return -EEXIST; 2292 } 2293 2294 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2295 if (!policy) 2296 return -ENOMEM; 2297 2298 fs->location = 0; 2299 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2300 GFP_KERNEL); 2301 if (err) { 2302 devm_kfree(chip->dev, policy); 2303 return err; 2304 } 2305 2306 memcpy(&policy->fs, fs, sizeof(*fs)); 2307 ether_addr_copy(policy->addr, addr); 2308 policy->mapping = mapping; 2309 policy->action = action; 2310 policy->port = port; 2311 policy->vid = vid; 2312 2313 err = mv88e6xxx_policy_apply(chip, port, policy); 2314 if (err) { 2315 idr_remove(&chip->policies, fs->location); 2316 devm_kfree(chip->dev, policy); 2317 return err; 2318 } 2319 2320 return 0; 2321 } 2322 2323 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2324 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2325 { 2326 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2327 struct mv88e6xxx_chip *chip = ds->priv; 2328 struct mv88e6xxx_policy *policy; 2329 int err; 2330 int id; 2331 2332 mv88e6xxx_reg_lock(chip); 2333 2334 switch (rxnfc->cmd) { 2335 case ETHTOOL_GRXCLSRLCNT: 2336 rxnfc->data = 0; 2337 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2338 rxnfc->rule_cnt = 0; 2339 idr_for_each_entry(&chip->policies, policy, id) 2340 if (policy->port == port) 2341 rxnfc->rule_cnt++; 2342 err = 0; 2343 break; 2344 case ETHTOOL_GRXCLSRULE: 2345 err = -ENOENT; 2346 policy = idr_find(&chip->policies, fs->location); 2347 if (policy) { 2348 memcpy(fs, &policy->fs, sizeof(*fs)); 2349 err = 0; 2350 } 2351 break; 2352 case ETHTOOL_GRXCLSRLALL: 2353 rxnfc->data = 0; 2354 rxnfc->rule_cnt = 0; 2355 idr_for_each_entry(&chip->policies, policy, id) 2356 if (policy->port == port) 2357 rule_locs[rxnfc->rule_cnt++] = id; 2358 err = 0; 2359 break; 2360 default: 2361 err = -EOPNOTSUPP; 2362 break; 2363 } 2364 2365 mv88e6xxx_reg_unlock(chip); 2366 2367 return err; 2368 } 2369 2370 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2371 struct ethtool_rxnfc *rxnfc) 2372 { 2373 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2374 struct mv88e6xxx_chip *chip = ds->priv; 2375 struct mv88e6xxx_policy *policy; 2376 int err; 2377 2378 mv88e6xxx_reg_lock(chip); 2379 2380 switch (rxnfc->cmd) { 2381 case ETHTOOL_SRXCLSRLINS: 2382 err = mv88e6xxx_policy_insert(chip, port, fs); 2383 break; 2384 case ETHTOOL_SRXCLSRLDEL: 2385 err = -ENOENT; 2386 policy = idr_remove(&chip->policies, fs->location); 2387 if (policy) { 2388 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2389 err = mv88e6xxx_policy_apply(chip, port, policy); 2390 devm_kfree(chip->dev, policy); 2391 } 2392 break; 2393 default: 2394 err = -EOPNOTSUPP; 2395 break; 2396 } 2397 2398 mv88e6xxx_reg_unlock(chip); 2399 2400 return err; 2401 } 2402 2403 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2404 u16 vid) 2405 { 2406 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2407 u8 broadcast[ETH_ALEN]; 2408 2409 eth_broadcast_addr(broadcast); 2410 2411 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2412 } 2413 2414 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2415 { 2416 int port; 2417 int err; 2418 2419 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2420 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2421 struct net_device *brport; 2422 2423 if (dsa_is_unused_port(chip->ds, port)) 2424 continue; 2425 2426 brport = dsa_port_to_bridge_port(dp); 2427 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2428 /* Skip bridged user ports where broadcast 2429 * flooding is disabled. 2430 */ 2431 continue; 2432 2433 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2434 if (err) 2435 return err; 2436 } 2437 2438 return 0; 2439 } 2440 2441 struct mv88e6xxx_port_broadcast_sync_ctx { 2442 int port; 2443 bool flood; 2444 }; 2445 2446 static int 2447 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2448 const struct mv88e6xxx_vtu_entry *vlan, 2449 void *_ctx) 2450 { 2451 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2452 u8 broadcast[ETH_ALEN]; 2453 u8 state; 2454 2455 if (ctx->flood) 2456 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2457 else 2458 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2459 2460 eth_broadcast_addr(broadcast); 2461 2462 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2463 vlan->vid, state); 2464 } 2465 2466 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2467 bool flood) 2468 { 2469 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2470 .port = port, 2471 .flood = flood, 2472 }; 2473 struct mv88e6xxx_vtu_entry vid0 = { 2474 .vid = 0, 2475 }; 2476 int err; 2477 2478 /* Update the port's private database... */ 2479 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2480 if (err) 2481 return err; 2482 2483 /* ...and the database for all VLANs. */ 2484 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2485 &ctx); 2486 } 2487 2488 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2489 u16 vid, u8 member, bool warn) 2490 { 2491 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2492 struct mv88e6xxx_vtu_entry vlan; 2493 int i, err; 2494 2495 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2496 if (err) 2497 return err; 2498 2499 if (!vlan.valid) { 2500 memset(&vlan, 0, sizeof(vlan)); 2501 2502 if (vid == MV88E6XXX_VID_STANDALONE) 2503 vlan.policy = true; 2504 2505 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2506 if (err) 2507 return err; 2508 2509 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2510 if (i == port) 2511 vlan.member[i] = member; 2512 else 2513 vlan.member[i] = non_member; 2514 2515 vlan.vid = vid; 2516 vlan.valid = true; 2517 2518 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2519 if (err) 2520 return err; 2521 2522 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2523 if (err) 2524 return err; 2525 } else if (vlan.member[port] != member) { 2526 vlan.member[port] = member; 2527 2528 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2529 if (err) 2530 return err; 2531 } else if (warn) { 2532 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2533 port, vid); 2534 } 2535 2536 return 0; 2537 } 2538 2539 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2540 const struct switchdev_obj_port_vlan *vlan, 2541 struct netlink_ext_ack *extack) 2542 { 2543 struct mv88e6xxx_chip *chip = ds->priv; 2544 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2545 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2546 struct mv88e6xxx_port *p = &chip->ports[port]; 2547 bool warn; 2548 u8 member; 2549 int err; 2550 2551 if (!vlan->vid) 2552 return 0; 2553 2554 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2555 if (err) 2556 return err; 2557 2558 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2559 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2560 else if (untagged) 2561 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2562 else 2563 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2564 2565 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2566 * and then the CPU port. Do not warn for duplicates for the CPU port. 2567 */ 2568 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2569 2570 mv88e6xxx_reg_lock(chip); 2571 2572 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2573 if (err) { 2574 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2575 vlan->vid, untagged ? 'u' : 't'); 2576 goto out; 2577 } 2578 2579 if (pvid) { 2580 p->bridge_pvid.vid = vlan->vid; 2581 p->bridge_pvid.valid = true; 2582 2583 err = mv88e6xxx_port_commit_pvid(chip, port); 2584 if (err) 2585 goto out; 2586 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2587 /* The old pvid was reinstalled as a non-pvid VLAN */ 2588 p->bridge_pvid.valid = false; 2589 2590 err = mv88e6xxx_port_commit_pvid(chip, port); 2591 if (err) 2592 goto out; 2593 } 2594 2595 out: 2596 mv88e6xxx_reg_unlock(chip); 2597 2598 return err; 2599 } 2600 2601 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2602 int port, u16 vid) 2603 { 2604 struct mv88e6xxx_vtu_entry vlan; 2605 int i, err; 2606 2607 if (!vid) 2608 return 0; 2609 2610 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2611 if (err) 2612 return err; 2613 2614 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2615 * tell switchdev that this VLAN is likely handled in software. 2616 */ 2617 if (!vlan.valid || 2618 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2619 return -EOPNOTSUPP; 2620 2621 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2622 2623 /* keep the VLAN unless all ports are excluded */ 2624 vlan.valid = false; 2625 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2626 if (vlan.member[i] != 2627 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2628 vlan.valid = true; 2629 break; 2630 } 2631 } 2632 2633 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2634 if (err) 2635 return err; 2636 2637 if (!vlan.valid) { 2638 err = mv88e6xxx_mst_put(chip, vlan.sid); 2639 if (err) 2640 return err; 2641 } 2642 2643 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2644 } 2645 2646 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2647 const struct switchdev_obj_port_vlan *vlan) 2648 { 2649 struct mv88e6xxx_chip *chip = ds->priv; 2650 struct mv88e6xxx_port *p = &chip->ports[port]; 2651 int err = 0; 2652 u16 pvid; 2653 2654 if (!mv88e6xxx_max_vid(chip)) 2655 return -EOPNOTSUPP; 2656 2657 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2658 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2659 * switchdev workqueue to ensure that all FDB entries are deleted 2660 * before we remove the VLAN. 2661 */ 2662 dsa_flush_workqueue(); 2663 2664 mv88e6xxx_reg_lock(chip); 2665 2666 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2667 if (err) 2668 goto unlock; 2669 2670 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2671 if (err) 2672 goto unlock; 2673 2674 if (vlan->vid == pvid) { 2675 p->bridge_pvid.valid = false; 2676 2677 err = mv88e6xxx_port_commit_pvid(chip, port); 2678 if (err) 2679 goto unlock; 2680 } 2681 2682 unlock: 2683 mv88e6xxx_reg_unlock(chip); 2684 2685 return err; 2686 } 2687 2688 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2689 { 2690 struct mv88e6xxx_chip *chip = ds->priv; 2691 struct mv88e6xxx_vtu_entry vlan; 2692 int err; 2693 2694 mv88e6xxx_reg_lock(chip); 2695 2696 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2697 if (err) 2698 goto unlock; 2699 2700 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2701 2702 unlock: 2703 mv88e6xxx_reg_unlock(chip); 2704 2705 return err; 2706 } 2707 2708 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2709 struct dsa_bridge bridge, 2710 const struct switchdev_vlan_msti *msti) 2711 { 2712 struct mv88e6xxx_chip *chip = ds->priv; 2713 struct mv88e6xxx_vtu_entry vlan; 2714 u8 old_sid, new_sid; 2715 int err; 2716 2717 if (!mv88e6xxx_has_stu(chip)) 2718 return -EOPNOTSUPP; 2719 2720 mv88e6xxx_reg_lock(chip); 2721 2722 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2723 if (err) 2724 goto unlock; 2725 2726 if (!vlan.valid) { 2727 err = -EINVAL; 2728 goto unlock; 2729 } 2730 2731 old_sid = vlan.sid; 2732 2733 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2734 if (err) 2735 goto unlock; 2736 2737 if (new_sid != old_sid) { 2738 vlan.sid = new_sid; 2739 2740 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2741 if (err) { 2742 mv88e6xxx_mst_put(chip, new_sid); 2743 goto unlock; 2744 } 2745 } 2746 2747 err = mv88e6xxx_mst_put(chip, old_sid); 2748 2749 unlock: 2750 mv88e6xxx_reg_unlock(chip); 2751 return err; 2752 } 2753 2754 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2755 const unsigned char *addr, u16 vid, 2756 struct dsa_db db) 2757 { 2758 struct mv88e6xxx_chip *chip = ds->priv; 2759 int err; 2760 2761 mv88e6xxx_reg_lock(chip); 2762 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2763 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2764 mv88e6xxx_reg_unlock(chip); 2765 2766 return err; 2767 } 2768 2769 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2770 const unsigned char *addr, u16 vid, 2771 struct dsa_db db) 2772 { 2773 struct mv88e6xxx_chip *chip = ds->priv; 2774 int err; 2775 2776 mv88e6xxx_reg_lock(chip); 2777 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2778 mv88e6xxx_reg_unlock(chip); 2779 2780 return err; 2781 } 2782 2783 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2784 u16 fid, u16 vid, int port, 2785 dsa_fdb_dump_cb_t *cb, void *data) 2786 { 2787 struct mv88e6xxx_atu_entry addr; 2788 bool is_static; 2789 int err; 2790 2791 addr.state = 0; 2792 eth_broadcast_addr(addr.mac); 2793 2794 do { 2795 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2796 if (err) 2797 return err; 2798 2799 if (!addr.state) 2800 break; 2801 2802 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2803 continue; 2804 2805 if (!is_unicast_ether_addr(addr.mac)) 2806 continue; 2807 2808 is_static = (addr.state == 2809 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2810 err = cb(addr.mac, vid, is_static, data); 2811 if (err) 2812 return err; 2813 } while (!is_broadcast_ether_addr(addr.mac)); 2814 2815 return err; 2816 } 2817 2818 struct mv88e6xxx_port_db_dump_vlan_ctx { 2819 int port; 2820 dsa_fdb_dump_cb_t *cb; 2821 void *data; 2822 }; 2823 2824 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2825 const struct mv88e6xxx_vtu_entry *entry, 2826 void *_data) 2827 { 2828 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2829 2830 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2831 ctx->port, ctx->cb, ctx->data); 2832 } 2833 2834 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2835 dsa_fdb_dump_cb_t *cb, void *data) 2836 { 2837 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2838 .port = port, 2839 .cb = cb, 2840 .data = data, 2841 }; 2842 u16 fid; 2843 int err; 2844 2845 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2846 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2847 if (err) 2848 return err; 2849 2850 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2851 if (err) 2852 return err; 2853 2854 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2855 } 2856 2857 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2858 dsa_fdb_dump_cb_t *cb, void *data) 2859 { 2860 struct mv88e6xxx_chip *chip = ds->priv; 2861 int err; 2862 2863 mv88e6xxx_reg_lock(chip); 2864 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2865 mv88e6xxx_reg_unlock(chip); 2866 2867 return err; 2868 } 2869 2870 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2871 struct dsa_bridge bridge) 2872 { 2873 struct dsa_switch *ds = chip->ds; 2874 struct dsa_switch_tree *dst = ds->dst; 2875 struct dsa_port *dp; 2876 int err; 2877 2878 list_for_each_entry(dp, &dst->ports, list) { 2879 if (dsa_port_offloads_bridge(dp, &bridge)) { 2880 if (dp->ds == ds) { 2881 /* This is a local bridge group member, 2882 * remap its Port VLAN Map. 2883 */ 2884 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2885 if (err) 2886 return err; 2887 } else { 2888 /* This is an external bridge group member, 2889 * remap its cross-chip Port VLAN Table entry. 2890 */ 2891 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2892 dp->index); 2893 if (err) 2894 return err; 2895 } 2896 } 2897 } 2898 2899 return 0; 2900 } 2901 2902 /* Treat the software bridge as a virtual single-port switch behind the 2903 * CPU and map in the PVT. First dst->last_switch elements are taken by 2904 * physical switches, so start from beyond that range. 2905 */ 2906 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2907 unsigned int bridge_num) 2908 { 2909 u8 dev = bridge_num + ds->dst->last_switch; 2910 struct mv88e6xxx_chip *chip = ds->priv; 2911 2912 return mv88e6xxx_pvt_map(chip, dev, 0); 2913 } 2914 2915 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2916 struct dsa_bridge bridge, 2917 bool *tx_fwd_offload, 2918 struct netlink_ext_ack *extack) 2919 { 2920 struct mv88e6xxx_chip *chip = ds->priv; 2921 int err; 2922 2923 mv88e6xxx_reg_lock(chip); 2924 2925 err = mv88e6xxx_bridge_map(chip, bridge); 2926 if (err) 2927 goto unlock; 2928 2929 err = mv88e6xxx_port_set_map_da(chip, port, true); 2930 if (err) 2931 goto unlock; 2932 2933 err = mv88e6xxx_port_commit_pvid(chip, port); 2934 if (err) 2935 goto unlock; 2936 2937 if (mv88e6xxx_has_pvt(chip)) { 2938 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2939 if (err) 2940 goto unlock; 2941 2942 *tx_fwd_offload = true; 2943 } 2944 2945 unlock: 2946 mv88e6xxx_reg_unlock(chip); 2947 2948 return err; 2949 } 2950 2951 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2952 struct dsa_bridge bridge) 2953 { 2954 struct mv88e6xxx_chip *chip = ds->priv; 2955 int err; 2956 2957 mv88e6xxx_reg_lock(chip); 2958 2959 if (bridge.tx_fwd_offload && 2960 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2961 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2962 2963 if (mv88e6xxx_bridge_map(chip, bridge) || 2964 mv88e6xxx_port_vlan_map(chip, port)) 2965 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2966 2967 err = mv88e6xxx_port_set_map_da(chip, port, false); 2968 if (err) 2969 dev_err(ds->dev, 2970 "port %d failed to restore map-DA: %pe\n", 2971 port, ERR_PTR(err)); 2972 2973 err = mv88e6xxx_port_commit_pvid(chip, port); 2974 if (err) 2975 dev_err(ds->dev, 2976 "port %d failed to restore standalone pvid: %pe\n", 2977 port, ERR_PTR(err)); 2978 2979 mv88e6xxx_reg_unlock(chip); 2980 } 2981 2982 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2983 int tree_index, int sw_index, 2984 int port, struct dsa_bridge bridge, 2985 struct netlink_ext_ack *extack) 2986 { 2987 struct mv88e6xxx_chip *chip = ds->priv; 2988 int err; 2989 2990 if (tree_index != ds->dst->index) 2991 return 0; 2992 2993 mv88e6xxx_reg_lock(chip); 2994 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2995 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2996 mv88e6xxx_reg_unlock(chip); 2997 2998 return err; 2999 } 3000 3001 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3002 int tree_index, int sw_index, 3003 int port, struct dsa_bridge bridge) 3004 { 3005 struct mv88e6xxx_chip *chip = ds->priv; 3006 3007 if (tree_index != ds->dst->index) 3008 return; 3009 3010 mv88e6xxx_reg_lock(chip); 3011 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3012 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3013 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3014 mv88e6xxx_reg_unlock(chip); 3015 } 3016 3017 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3018 { 3019 if (chip->info->ops->reset) 3020 return chip->info->ops->reset(chip); 3021 3022 return 0; 3023 } 3024 3025 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3026 { 3027 struct gpio_desc *gpiod = chip->reset; 3028 3029 /* If there is a GPIO connected to the reset pin, toggle it */ 3030 if (gpiod) { 3031 gpiod_set_value_cansleep(gpiod, 1); 3032 usleep_range(10000, 20000); 3033 gpiod_set_value_cansleep(gpiod, 0); 3034 usleep_range(10000, 20000); 3035 3036 mv88e6xxx_g1_wait_eeprom_done(chip); 3037 } 3038 } 3039 3040 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3041 { 3042 int i, err; 3043 3044 /* Set all ports to the Disabled state */ 3045 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3046 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3047 if (err) 3048 return err; 3049 } 3050 3051 /* Wait for transmit queues to drain, 3052 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3053 */ 3054 usleep_range(2000, 4000); 3055 3056 return 0; 3057 } 3058 3059 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3060 { 3061 int err; 3062 3063 err = mv88e6xxx_disable_ports(chip); 3064 if (err) 3065 return err; 3066 3067 mv88e6xxx_hardware_reset(chip); 3068 3069 return mv88e6xxx_software_reset(chip); 3070 } 3071 3072 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3073 enum mv88e6xxx_frame_mode frame, 3074 enum mv88e6xxx_egress_mode egress, u16 etype) 3075 { 3076 int err; 3077 3078 if (!chip->info->ops->port_set_frame_mode) 3079 return -EOPNOTSUPP; 3080 3081 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3082 if (err) 3083 return err; 3084 3085 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3086 if (err) 3087 return err; 3088 3089 if (chip->info->ops->port_set_ether_type) 3090 return chip->info->ops->port_set_ether_type(chip, port, etype); 3091 3092 return 0; 3093 } 3094 3095 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3096 { 3097 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3098 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3099 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3100 } 3101 3102 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3103 { 3104 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3105 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3106 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3107 } 3108 3109 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3110 { 3111 return mv88e6xxx_set_port_mode(chip, port, 3112 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3113 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3114 ETH_P_EDSA); 3115 } 3116 3117 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3118 { 3119 if (dsa_is_dsa_port(chip->ds, port)) 3120 return mv88e6xxx_set_port_mode_dsa(chip, port); 3121 3122 if (dsa_is_user_port(chip->ds, port)) 3123 return mv88e6xxx_set_port_mode_normal(chip, port); 3124 3125 /* Setup CPU port mode depending on its supported tag format */ 3126 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3127 return mv88e6xxx_set_port_mode_dsa(chip, port); 3128 3129 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3130 return mv88e6xxx_set_port_mode_edsa(chip, port); 3131 3132 return -EINVAL; 3133 } 3134 3135 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3136 { 3137 bool message = dsa_is_dsa_port(chip->ds, port); 3138 3139 return mv88e6xxx_port_set_message_port(chip, port, message); 3140 } 3141 3142 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3143 { 3144 int err; 3145 3146 if (chip->info->ops->port_set_ucast_flood) { 3147 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3148 if (err) 3149 return err; 3150 } 3151 if (chip->info->ops->port_set_mcast_flood) { 3152 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3153 if (err) 3154 return err; 3155 } 3156 3157 return 0; 3158 } 3159 3160 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3161 { 3162 struct mv88e6xxx_port *mvp = dev_id; 3163 struct mv88e6xxx_chip *chip = mvp->chip; 3164 irqreturn_t ret = IRQ_NONE; 3165 int port = mvp->port; 3166 int lane; 3167 3168 mv88e6xxx_reg_lock(chip); 3169 lane = mv88e6xxx_serdes_get_lane(chip, port); 3170 if (lane >= 0) 3171 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3172 mv88e6xxx_reg_unlock(chip); 3173 3174 return ret; 3175 } 3176 3177 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3178 int lane) 3179 { 3180 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3181 unsigned int irq; 3182 int err; 3183 3184 /* Nothing to request if this SERDES port has no IRQ */ 3185 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3186 if (!irq) 3187 return 0; 3188 3189 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3190 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3191 3192 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3193 mv88e6xxx_reg_unlock(chip); 3194 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3195 IRQF_ONESHOT, dev_id->serdes_irq_name, 3196 dev_id); 3197 mv88e6xxx_reg_lock(chip); 3198 if (err) 3199 return err; 3200 3201 dev_id->serdes_irq = irq; 3202 3203 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3204 } 3205 3206 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3207 int lane) 3208 { 3209 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3210 unsigned int irq = dev_id->serdes_irq; 3211 int err; 3212 3213 /* Nothing to free if no IRQ has been requested */ 3214 if (!irq) 3215 return 0; 3216 3217 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3218 3219 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3220 mv88e6xxx_reg_unlock(chip); 3221 free_irq(irq, dev_id); 3222 mv88e6xxx_reg_lock(chip); 3223 3224 dev_id->serdes_irq = 0; 3225 3226 return err; 3227 } 3228 3229 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3230 bool on) 3231 { 3232 int lane; 3233 int err; 3234 3235 lane = mv88e6xxx_serdes_get_lane(chip, port); 3236 if (lane < 0) 3237 return 0; 3238 3239 if (on) { 3240 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3241 if (err) 3242 return err; 3243 3244 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3245 } else { 3246 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3247 if (err) 3248 return err; 3249 3250 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3251 } 3252 3253 return err; 3254 } 3255 3256 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3257 enum mv88e6xxx_egress_direction direction, 3258 int port) 3259 { 3260 int err; 3261 3262 if (!chip->info->ops->set_egress_port) 3263 return -EOPNOTSUPP; 3264 3265 err = chip->info->ops->set_egress_port(chip, direction, port); 3266 if (err) 3267 return err; 3268 3269 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3270 chip->ingress_dest_port = port; 3271 else 3272 chip->egress_dest_port = port; 3273 3274 return 0; 3275 } 3276 3277 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3278 { 3279 struct dsa_switch *ds = chip->ds; 3280 int upstream_port; 3281 int err; 3282 3283 upstream_port = dsa_upstream_port(ds, port); 3284 if (chip->info->ops->port_set_upstream_port) { 3285 err = chip->info->ops->port_set_upstream_port(chip, port, 3286 upstream_port); 3287 if (err) 3288 return err; 3289 } 3290 3291 if (port == upstream_port) { 3292 if (chip->info->ops->set_cpu_port) { 3293 err = chip->info->ops->set_cpu_port(chip, 3294 upstream_port); 3295 if (err) 3296 return err; 3297 } 3298 3299 err = mv88e6xxx_set_egress_port(chip, 3300 MV88E6XXX_EGRESS_DIR_INGRESS, 3301 upstream_port); 3302 if (err && err != -EOPNOTSUPP) 3303 return err; 3304 3305 err = mv88e6xxx_set_egress_port(chip, 3306 MV88E6XXX_EGRESS_DIR_EGRESS, 3307 upstream_port); 3308 if (err && err != -EOPNOTSUPP) 3309 return err; 3310 } 3311 3312 return 0; 3313 } 3314 3315 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3316 { 3317 struct device_node *phy_handle = NULL; 3318 struct dsa_switch *ds = chip->ds; 3319 phy_interface_t mode; 3320 struct dsa_port *dp; 3321 int tx_amp, speed; 3322 int err; 3323 u16 reg; 3324 3325 chip->ports[port].chip = chip; 3326 chip->ports[port].port = port; 3327 3328 dp = dsa_to_port(ds, port); 3329 3330 /* MAC Forcing register: don't force link, speed, duplex or flow control 3331 * state to any particular values on physical ports, but force the CPU 3332 * port and all DSA ports to their maximum bandwidth and full duplex. 3333 */ 3334 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3335 struct phylink_config pl_config = {}; 3336 unsigned long caps; 3337 3338 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3339 3340 caps = pl_config.mac_capabilities; 3341 3342 if (chip->info->ops->port_max_speed_mode) 3343 mode = chip->info->ops->port_max_speed_mode(chip, port); 3344 else 3345 mode = PHY_INTERFACE_MODE_NA; 3346 3347 if (caps & MAC_10000FD) 3348 speed = SPEED_10000; 3349 else if (caps & MAC_5000FD) 3350 speed = SPEED_5000; 3351 else if (caps & MAC_2500FD) 3352 speed = SPEED_2500; 3353 else if (caps & MAC_1000) 3354 speed = SPEED_1000; 3355 else if (caps & MAC_100) 3356 speed = SPEED_100; 3357 else 3358 speed = SPEED_10; 3359 3360 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3361 speed, DUPLEX_FULL, 3362 PAUSE_OFF, mode); 3363 } else { 3364 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3365 SPEED_UNFORCED, DUPLEX_UNFORCED, 3366 PAUSE_ON, 3367 PHY_INTERFACE_MODE_NA); 3368 } 3369 if (err) 3370 return err; 3371 3372 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3373 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3374 * tunneling, determine priority by looking at 802.1p and IP 3375 * priority fields (IP prio has precedence), and set STP state 3376 * to Forwarding. 3377 * 3378 * If this is the CPU link, use DSA or EDSA tagging depending 3379 * on which tagging mode was configured. 3380 * 3381 * If this is a link to another switch, use DSA tagging mode. 3382 * 3383 * If this is the upstream port for this switch, enable 3384 * forwarding of unknown unicasts and multicasts. 3385 */ 3386 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3387 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3388 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3389 * by a USER port to the CPU port to allow snooping. 3390 */ 3391 if (dsa_is_user_port(ds, port)) 3392 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3393 3394 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3395 if (err) 3396 return err; 3397 3398 err = mv88e6xxx_setup_port_mode(chip, port); 3399 if (err) 3400 return err; 3401 3402 err = mv88e6xxx_setup_egress_floods(chip, port); 3403 if (err) 3404 return err; 3405 3406 /* Port Control 2: don't force a good FCS, set the MTU size to 3407 * 10222 bytes, disable 802.1q tags checking, don't discard 3408 * tagged or untagged frames on this port, skip destination 3409 * address lookup on user ports, disable ARP mirroring and don't 3410 * send a copy of all transmitted/received frames on this port 3411 * to the CPU. 3412 */ 3413 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3414 if (err) 3415 return err; 3416 3417 err = mv88e6xxx_setup_upstream_port(chip, port); 3418 if (err) 3419 return err; 3420 3421 /* On chips that support it, set all downstream DSA ports' 3422 * VLAN policy to TRAP. In combination with loading 3423 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3424 * provides a better isolation barrier between standalone 3425 * ports, as the ATU is bypassed on any intermediate switches 3426 * between the incoming port and the CPU. 3427 */ 3428 if (dsa_is_downstream_port(ds, port) && 3429 chip->info->ops->port_set_policy) { 3430 err = chip->info->ops->port_set_policy(chip, port, 3431 MV88E6XXX_POLICY_MAPPING_VTU, 3432 MV88E6XXX_POLICY_ACTION_TRAP); 3433 if (err) 3434 return err; 3435 } 3436 3437 /* User ports start out in standalone mode and 802.1Q is 3438 * therefore disabled. On DSA ports, all valid VIDs are always 3439 * loaded in the VTU - therefore, enable 802.1Q in order to take 3440 * advantage of VLAN policy on chips that supports it. 3441 */ 3442 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3443 dsa_is_user_port(ds, port) ? 3444 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3445 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3446 if (err) 3447 return err; 3448 3449 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3450 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3451 * the first free FID. This will be used as the private PVID for 3452 * unbridged ports. Shared (DSA and CPU) ports must also be 3453 * members of this VID, in order to trap all frames assigned to 3454 * it to the CPU. 3455 */ 3456 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3457 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3458 false); 3459 if (err) 3460 return err; 3461 3462 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3463 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3464 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3465 * as the private PVID on ports under a VLAN-unaware bridge. 3466 * Shared (DSA and CPU) ports must also be members of it, to translate 3467 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3468 * relying on their port default FID. 3469 */ 3470 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3471 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3472 false); 3473 if (err) 3474 return err; 3475 3476 if (chip->info->ops->port_set_jumbo_size) { 3477 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3478 if (err) 3479 return err; 3480 } 3481 3482 /* Port Association Vector: disable automatic address learning 3483 * on all user ports since they start out in standalone 3484 * mode. When joining a bridge, learning will be configured to 3485 * match the bridge port settings. Enable learning on all 3486 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3487 * learning process. 3488 * 3489 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3490 * and RefreshLocked. I.e. setup standard automatic learning. 3491 */ 3492 if (dsa_is_user_port(ds, port)) 3493 reg = 0; 3494 else 3495 reg = 1 << port; 3496 3497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3498 reg); 3499 if (err) 3500 return err; 3501 3502 /* Egress rate control 2: disable egress rate control. */ 3503 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3504 0x0000); 3505 if (err) 3506 return err; 3507 3508 if (chip->info->ops->port_pause_limit) { 3509 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3510 if (err) 3511 return err; 3512 } 3513 3514 if (chip->info->ops->port_disable_learn_limit) { 3515 err = chip->info->ops->port_disable_learn_limit(chip, port); 3516 if (err) 3517 return err; 3518 } 3519 3520 if (chip->info->ops->port_disable_pri_override) { 3521 err = chip->info->ops->port_disable_pri_override(chip, port); 3522 if (err) 3523 return err; 3524 } 3525 3526 if (chip->info->ops->port_tag_remap) { 3527 err = chip->info->ops->port_tag_remap(chip, port); 3528 if (err) 3529 return err; 3530 } 3531 3532 if (chip->info->ops->port_egress_rate_limiting) { 3533 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3534 if (err) 3535 return err; 3536 } 3537 3538 if (chip->info->ops->port_setup_message_port) { 3539 err = chip->info->ops->port_setup_message_port(chip, port); 3540 if (err) 3541 return err; 3542 } 3543 3544 if (chip->info->ops->serdes_set_tx_amplitude) { 3545 if (dp) 3546 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3547 3548 if (phy_handle && !of_property_read_u32(phy_handle, 3549 "tx-p2p-microvolt", 3550 &tx_amp)) 3551 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3552 port, tx_amp); 3553 if (phy_handle) { 3554 of_node_put(phy_handle); 3555 if (err) 3556 return err; 3557 } 3558 } 3559 3560 /* Port based VLAN map: give each port the same default address 3561 * database, and allow bidirectional communication between the 3562 * CPU and DSA port(s), and the other ports. 3563 */ 3564 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3565 if (err) 3566 return err; 3567 3568 err = mv88e6xxx_port_vlan_map(chip, port); 3569 if (err) 3570 return err; 3571 3572 /* Default VLAN ID and priority: don't set a default VLAN 3573 * ID, and set the default packet priority to zero. 3574 */ 3575 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3576 } 3577 3578 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3579 { 3580 struct mv88e6xxx_chip *chip = ds->priv; 3581 3582 if (chip->info->ops->port_set_jumbo_size) 3583 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3584 else if (chip->info->ops->set_max_frame_size) 3585 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3586 return ETH_DATA_LEN; 3587 } 3588 3589 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3590 { 3591 struct mv88e6xxx_chip *chip = ds->priv; 3592 int ret = 0; 3593 3594 /* For families where we don't know how to alter the MTU, 3595 * just accept any value up to ETH_DATA_LEN 3596 */ 3597 if (!chip->info->ops->port_set_jumbo_size && 3598 !chip->info->ops->set_max_frame_size) { 3599 if (new_mtu > ETH_DATA_LEN) 3600 return -EINVAL; 3601 3602 return 0; 3603 } 3604 3605 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3606 new_mtu += EDSA_HLEN; 3607 3608 mv88e6xxx_reg_lock(chip); 3609 if (chip->info->ops->port_set_jumbo_size) 3610 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3611 else if (chip->info->ops->set_max_frame_size) 3612 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3613 mv88e6xxx_reg_unlock(chip); 3614 3615 return ret; 3616 } 3617 3618 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3619 struct phy_device *phydev) 3620 { 3621 struct mv88e6xxx_chip *chip = ds->priv; 3622 int err; 3623 3624 mv88e6xxx_reg_lock(chip); 3625 err = mv88e6xxx_serdes_power(chip, port, true); 3626 mv88e6xxx_reg_unlock(chip); 3627 3628 return err; 3629 } 3630 3631 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3632 { 3633 struct mv88e6xxx_chip *chip = ds->priv; 3634 3635 mv88e6xxx_reg_lock(chip); 3636 if (mv88e6xxx_serdes_power(chip, port, false)) 3637 dev_err(chip->dev, "failed to power off SERDES\n"); 3638 mv88e6xxx_reg_unlock(chip); 3639 } 3640 3641 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3642 unsigned int ageing_time) 3643 { 3644 struct mv88e6xxx_chip *chip = ds->priv; 3645 int err; 3646 3647 mv88e6xxx_reg_lock(chip); 3648 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3649 mv88e6xxx_reg_unlock(chip); 3650 3651 return err; 3652 } 3653 3654 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3655 { 3656 int err; 3657 3658 /* Initialize the statistics unit */ 3659 if (chip->info->ops->stats_set_histogram) { 3660 err = chip->info->ops->stats_set_histogram(chip); 3661 if (err) 3662 return err; 3663 } 3664 3665 return mv88e6xxx_g1_stats_clear(chip); 3666 } 3667 3668 /* Check if the errata has already been applied. */ 3669 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3670 { 3671 int port; 3672 int err; 3673 u16 val; 3674 3675 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3676 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3677 if (err) { 3678 dev_err(chip->dev, 3679 "Error reading hidden register: %d\n", err); 3680 return false; 3681 } 3682 if (val != 0x01c0) 3683 return false; 3684 } 3685 3686 return true; 3687 } 3688 3689 /* The 6390 copper ports have an errata which require poking magic 3690 * values into undocumented hidden registers and then performing a 3691 * software reset. 3692 */ 3693 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3694 { 3695 int port; 3696 int err; 3697 3698 if (mv88e6390_setup_errata_applied(chip)) 3699 return 0; 3700 3701 /* Set the ports into blocking mode */ 3702 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3703 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3704 if (err) 3705 return err; 3706 } 3707 3708 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3709 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3710 if (err) 3711 return err; 3712 } 3713 3714 return mv88e6xxx_software_reset(chip); 3715 } 3716 3717 /* prod_id for switch families which do not have a PHY model number */ 3718 static const u16 family_prod_id_table[] = { 3719 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3720 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3721 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3722 }; 3723 3724 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3725 { 3726 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3727 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3728 u16 prod_id; 3729 u16 val; 3730 int err; 3731 3732 if (!chip->info->ops->phy_read) 3733 return -EOPNOTSUPP; 3734 3735 mv88e6xxx_reg_lock(chip); 3736 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3737 mv88e6xxx_reg_unlock(chip); 3738 3739 /* Some internal PHYs don't have a model number. */ 3740 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3741 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3742 prod_id = family_prod_id_table[chip->info->family]; 3743 if (prod_id) 3744 val |= prod_id >> 4; 3745 } 3746 3747 return err ? err : val; 3748 } 3749 3750 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3751 int reg) 3752 { 3753 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3754 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3755 u16 val; 3756 int err; 3757 3758 if (!chip->info->ops->phy_read_c45) 3759 return -EOPNOTSUPP; 3760 3761 mv88e6xxx_reg_lock(chip); 3762 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3763 mv88e6xxx_reg_unlock(chip); 3764 3765 return err ? err : val; 3766 } 3767 3768 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3769 { 3770 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3771 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3772 int err; 3773 3774 if (!chip->info->ops->phy_write) 3775 return -EOPNOTSUPP; 3776 3777 mv88e6xxx_reg_lock(chip); 3778 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3779 mv88e6xxx_reg_unlock(chip); 3780 3781 return err; 3782 } 3783 3784 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3785 int reg, u16 val) 3786 { 3787 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3788 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3789 int err; 3790 3791 if (!chip->info->ops->phy_write_c45) 3792 return -EOPNOTSUPP; 3793 3794 mv88e6xxx_reg_lock(chip); 3795 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3796 mv88e6xxx_reg_unlock(chip); 3797 3798 return err; 3799 } 3800 3801 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3802 struct device_node *np, 3803 bool external) 3804 { 3805 static int index; 3806 struct mv88e6xxx_mdio_bus *mdio_bus; 3807 struct mii_bus *bus; 3808 int err; 3809 3810 if (external) { 3811 mv88e6xxx_reg_lock(chip); 3812 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3813 mv88e6xxx_reg_unlock(chip); 3814 3815 if (err) 3816 return err; 3817 } 3818 3819 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3820 if (!bus) 3821 return -ENOMEM; 3822 3823 mdio_bus = bus->priv; 3824 mdio_bus->bus = bus; 3825 mdio_bus->chip = chip; 3826 INIT_LIST_HEAD(&mdio_bus->list); 3827 mdio_bus->external = external; 3828 3829 if (np) { 3830 bus->name = np->full_name; 3831 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3832 } else { 3833 bus->name = "mv88e6xxx SMI"; 3834 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3835 } 3836 3837 bus->read = mv88e6xxx_mdio_read; 3838 bus->write = mv88e6xxx_mdio_write; 3839 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3840 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3841 bus->parent = chip->dev; 3842 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3843 mv88e6xxx_num_ports(chip) - 1, 3844 chip->info->phy_base_addr); 3845 3846 if (!external) { 3847 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3848 if (err) 3849 goto out; 3850 } 3851 3852 err = of_mdiobus_register(bus, np); 3853 if (err) { 3854 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3855 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3856 goto out; 3857 } 3858 3859 if (external) 3860 list_add_tail(&mdio_bus->list, &chip->mdios); 3861 else 3862 list_add(&mdio_bus->list, &chip->mdios); 3863 3864 return 0; 3865 3866 out: 3867 mdiobus_free(bus); 3868 return err; 3869 } 3870 3871 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3872 3873 { 3874 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3875 struct mii_bus *bus; 3876 3877 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3878 bus = mdio_bus->bus; 3879 3880 if (!mdio_bus->external) 3881 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3882 3883 mdiobus_unregister(bus); 3884 mdiobus_free(bus); 3885 } 3886 } 3887 3888 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3889 { 3890 struct device_node *np = chip->dev->of_node; 3891 struct device_node *child; 3892 int err; 3893 3894 /* Always register one mdio bus for the internal/default mdio 3895 * bus. This maybe represented in the device tree, but is 3896 * optional. 3897 */ 3898 child = of_get_child_by_name(np, "mdio"); 3899 err = mv88e6xxx_mdio_register(chip, child, false); 3900 of_node_put(child); 3901 if (err) 3902 return err; 3903 3904 /* Walk the device tree, and see if there are any other nodes 3905 * which say they are compatible with the external mdio 3906 * bus. 3907 */ 3908 for_each_available_child_of_node(np, child) { 3909 if (of_device_is_compatible( 3910 child, "marvell,mv88e6xxx-mdio-external")) { 3911 err = mv88e6xxx_mdio_register(chip, child, true); 3912 if (err) { 3913 mv88e6xxx_mdios_unregister(chip); 3914 of_node_put(child); 3915 return err; 3916 } 3917 } 3918 } 3919 3920 return 0; 3921 } 3922 3923 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3924 { 3925 struct mv88e6xxx_chip *chip = ds->priv; 3926 3927 mv88e6xxx_teardown_devlink_params(ds); 3928 dsa_devlink_resources_unregister(ds); 3929 mv88e6xxx_teardown_devlink_regions_global(ds); 3930 mv88e6xxx_mdios_unregister(chip); 3931 } 3932 3933 static int mv88e6xxx_setup(struct dsa_switch *ds) 3934 { 3935 struct mv88e6xxx_chip *chip = ds->priv; 3936 u8 cmode; 3937 int err; 3938 int i; 3939 3940 err = mv88e6xxx_mdios_register(chip); 3941 if (err) 3942 return err; 3943 3944 chip->ds = ds; 3945 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3946 3947 /* Since virtual bridges are mapped in the PVT, the number we support 3948 * depends on the physical switch topology. We need to let DSA figure 3949 * that out and therefore we cannot set this at dsa_register_switch() 3950 * time. 3951 */ 3952 if (mv88e6xxx_has_pvt(chip)) 3953 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3954 ds->dst->last_switch - 1; 3955 3956 mv88e6xxx_reg_lock(chip); 3957 3958 if (chip->info->ops->setup_errata) { 3959 err = chip->info->ops->setup_errata(chip); 3960 if (err) 3961 goto unlock; 3962 } 3963 3964 /* Cache the cmode of each port. */ 3965 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3966 if (chip->info->ops->port_get_cmode) { 3967 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3968 if (err) 3969 goto unlock; 3970 3971 chip->ports[i].cmode = cmode; 3972 } 3973 } 3974 3975 err = mv88e6xxx_vtu_setup(chip); 3976 if (err) 3977 goto unlock; 3978 3979 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3980 * VTU, thereby also flushing the STU). 3981 */ 3982 err = mv88e6xxx_stu_setup(chip); 3983 if (err) 3984 goto unlock; 3985 3986 /* Setup Switch Port Registers */ 3987 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3988 if (dsa_is_unused_port(ds, i)) 3989 continue; 3990 3991 /* Prevent the use of an invalid port. */ 3992 if (mv88e6xxx_is_invalid_port(chip, i)) { 3993 dev_err(chip->dev, "port %d is invalid\n", i); 3994 err = -EINVAL; 3995 goto unlock; 3996 } 3997 3998 err = mv88e6xxx_setup_port(chip, i); 3999 if (err) 4000 goto unlock; 4001 } 4002 4003 err = mv88e6xxx_irl_setup(chip); 4004 if (err) 4005 goto unlock; 4006 4007 err = mv88e6xxx_mac_setup(chip); 4008 if (err) 4009 goto unlock; 4010 4011 err = mv88e6xxx_phy_setup(chip); 4012 if (err) 4013 goto unlock; 4014 4015 err = mv88e6xxx_pvt_setup(chip); 4016 if (err) 4017 goto unlock; 4018 4019 err = mv88e6xxx_atu_setup(chip); 4020 if (err) 4021 goto unlock; 4022 4023 err = mv88e6xxx_broadcast_setup(chip, 0); 4024 if (err) 4025 goto unlock; 4026 4027 err = mv88e6xxx_pot_setup(chip); 4028 if (err) 4029 goto unlock; 4030 4031 err = mv88e6xxx_rmu_setup(chip); 4032 if (err) 4033 goto unlock; 4034 4035 err = mv88e6xxx_rsvd2cpu_setup(chip); 4036 if (err) 4037 goto unlock; 4038 4039 err = mv88e6xxx_trunk_setup(chip); 4040 if (err) 4041 goto unlock; 4042 4043 err = mv88e6xxx_devmap_setup(chip); 4044 if (err) 4045 goto unlock; 4046 4047 err = mv88e6xxx_pri_setup(chip); 4048 if (err) 4049 goto unlock; 4050 4051 /* Setup PTP Hardware Clock and timestamping */ 4052 if (chip->info->ptp_support) { 4053 err = mv88e6xxx_ptp_setup(chip); 4054 if (err) 4055 goto unlock; 4056 4057 err = mv88e6xxx_hwtstamp_setup(chip); 4058 if (err) 4059 goto unlock; 4060 } 4061 4062 err = mv88e6xxx_stats_setup(chip); 4063 if (err) 4064 goto unlock; 4065 4066 unlock: 4067 mv88e6xxx_reg_unlock(chip); 4068 4069 if (err) 4070 goto out_mdios; 4071 4072 /* Have to be called without holding the register lock, since 4073 * they take the devlink lock, and we later take the locks in 4074 * the reverse order when getting/setting parameters or 4075 * resource occupancy. 4076 */ 4077 err = mv88e6xxx_setup_devlink_resources(ds); 4078 if (err) 4079 goto out_mdios; 4080 4081 err = mv88e6xxx_setup_devlink_params(ds); 4082 if (err) 4083 goto out_resources; 4084 4085 err = mv88e6xxx_setup_devlink_regions_global(ds); 4086 if (err) 4087 goto out_params; 4088 4089 return 0; 4090 4091 out_params: 4092 mv88e6xxx_teardown_devlink_params(ds); 4093 out_resources: 4094 dsa_devlink_resources_unregister(ds); 4095 out_mdios: 4096 mv88e6xxx_mdios_unregister(chip); 4097 4098 return err; 4099 } 4100 4101 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4102 { 4103 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4104 } 4105 4106 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4107 { 4108 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4109 } 4110 4111 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4112 { 4113 struct mv88e6xxx_chip *chip = ds->priv; 4114 4115 return chip->eeprom_len; 4116 } 4117 4118 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4119 struct ethtool_eeprom *eeprom, u8 *data) 4120 { 4121 struct mv88e6xxx_chip *chip = ds->priv; 4122 int err; 4123 4124 if (!chip->info->ops->get_eeprom) 4125 return -EOPNOTSUPP; 4126 4127 mv88e6xxx_reg_lock(chip); 4128 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4129 mv88e6xxx_reg_unlock(chip); 4130 4131 if (err) 4132 return err; 4133 4134 eeprom->magic = 0xc3ec4951; 4135 4136 return 0; 4137 } 4138 4139 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4140 struct ethtool_eeprom *eeprom, u8 *data) 4141 { 4142 struct mv88e6xxx_chip *chip = ds->priv; 4143 int err; 4144 4145 if (!chip->info->ops->set_eeprom) 4146 return -EOPNOTSUPP; 4147 4148 if (eeprom->magic != 0xc3ec4951) 4149 return -EINVAL; 4150 4151 mv88e6xxx_reg_lock(chip); 4152 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4153 mv88e6xxx_reg_unlock(chip); 4154 4155 return err; 4156 } 4157 4158 static const struct mv88e6xxx_ops mv88e6085_ops = { 4159 /* MV88E6XXX_FAMILY_6097 */ 4160 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4161 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4162 .irl_init_all = mv88e6352_g2_irl_init_all, 4163 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4164 .phy_read = mv88e6185_phy_ppu_read, 4165 .phy_write = mv88e6185_phy_ppu_write, 4166 .port_set_link = mv88e6xxx_port_set_link, 4167 .port_sync_link = mv88e6xxx_port_sync_link, 4168 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4169 .port_tag_remap = mv88e6095_port_tag_remap, 4170 .port_set_policy = mv88e6352_port_set_policy, 4171 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4172 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4173 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4174 .port_set_ether_type = mv88e6351_port_set_ether_type, 4175 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4176 .port_pause_limit = mv88e6097_port_pause_limit, 4177 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4178 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4179 .port_get_cmode = mv88e6185_port_get_cmode, 4180 .port_setup_message_port = mv88e6xxx_setup_message_port, 4181 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4182 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4183 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4184 .stats_get_strings = mv88e6095_stats_get_strings, 4185 .stats_get_stats = mv88e6095_stats_get_stats, 4186 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4187 .set_egress_port = mv88e6095_g1_set_egress_port, 4188 .watchdog_ops = &mv88e6097_watchdog_ops, 4189 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4190 .pot_clear = mv88e6xxx_g2_pot_clear, 4191 .ppu_enable = mv88e6185_g1_ppu_enable, 4192 .ppu_disable = mv88e6185_g1_ppu_disable, 4193 .reset = mv88e6185_g1_reset, 4194 .rmu_disable = mv88e6085_g1_rmu_disable, 4195 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4196 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4197 .stu_getnext = mv88e6352_g1_stu_getnext, 4198 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4199 .phylink_get_caps = mv88e6185_phylink_get_caps, 4200 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4201 }; 4202 4203 static const struct mv88e6xxx_ops mv88e6095_ops = { 4204 /* MV88E6XXX_FAMILY_6095 */ 4205 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4206 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4207 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4208 .phy_read = mv88e6185_phy_ppu_read, 4209 .phy_write = mv88e6185_phy_ppu_write, 4210 .port_set_link = mv88e6xxx_port_set_link, 4211 .port_sync_link = mv88e6185_port_sync_link, 4212 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4213 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4214 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4215 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4216 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4217 .port_get_cmode = mv88e6185_port_get_cmode, 4218 .port_setup_message_port = mv88e6xxx_setup_message_port, 4219 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4220 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4221 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4222 .stats_get_strings = mv88e6095_stats_get_strings, 4223 .stats_get_stats = mv88e6095_stats_get_stats, 4224 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4225 .serdes_power = mv88e6185_serdes_power, 4226 .serdes_get_lane = mv88e6185_serdes_get_lane, 4227 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4228 .ppu_enable = mv88e6185_g1_ppu_enable, 4229 .ppu_disable = mv88e6185_g1_ppu_disable, 4230 .reset = mv88e6185_g1_reset, 4231 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4232 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4233 .phylink_get_caps = mv88e6095_phylink_get_caps, 4234 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4235 }; 4236 4237 static const struct mv88e6xxx_ops mv88e6097_ops = { 4238 /* MV88E6XXX_FAMILY_6097 */ 4239 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4240 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4241 .irl_init_all = mv88e6352_g2_irl_init_all, 4242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4243 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4244 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4245 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4246 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4247 .port_set_link = mv88e6xxx_port_set_link, 4248 .port_sync_link = mv88e6185_port_sync_link, 4249 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4250 .port_tag_remap = mv88e6095_port_tag_remap, 4251 .port_set_policy = mv88e6352_port_set_policy, 4252 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4253 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4254 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4255 .port_set_ether_type = mv88e6351_port_set_ether_type, 4256 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4257 .port_pause_limit = mv88e6097_port_pause_limit, 4258 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4259 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4260 .port_get_cmode = mv88e6185_port_get_cmode, 4261 .port_setup_message_port = mv88e6xxx_setup_message_port, 4262 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4263 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4264 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4265 .stats_get_strings = mv88e6095_stats_get_strings, 4266 .stats_get_stats = mv88e6095_stats_get_stats, 4267 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4268 .set_egress_port = mv88e6095_g1_set_egress_port, 4269 .watchdog_ops = &mv88e6097_watchdog_ops, 4270 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4271 .serdes_power = mv88e6185_serdes_power, 4272 .serdes_get_lane = mv88e6185_serdes_get_lane, 4273 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4274 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4275 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4276 .serdes_irq_status = mv88e6097_serdes_irq_status, 4277 .pot_clear = mv88e6xxx_g2_pot_clear, 4278 .reset = mv88e6352_g1_reset, 4279 .rmu_disable = mv88e6085_g1_rmu_disable, 4280 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4281 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4282 .phylink_get_caps = mv88e6095_phylink_get_caps, 4283 .stu_getnext = mv88e6352_g1_stu_getnext, 4284 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4285 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4286 }; 4287 4288 static const struct mv88e6xxx_ops mv88e6123_ops = { 4289 /* MV88E6XXX_FAMILY_6165 */ 4290 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4291 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4292 .irl_init_all = mv88e6352_g2_irl_init_all, 4293 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4294 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4295 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4296 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4297 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4298 .port_set_link = mv88e6xxx_port_set_link, 4299 .port_sync_link = mv88e6xxx_port_sync_link, 4300 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4301 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4302 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4303 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4304 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4305 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4306 .port_get_cmode = mv88e6185_port_get_cmode, 4307 .port_setup_message_port = mv88e6xxx_setup_message_port, 4308 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4309 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4310 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4311 .stats_get_strings = mv88e6095_stats_get_strings, 4312 .stats_get_stats = mv88e6095_stats_get_stats, 4313 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4314 .set_egress_port = mv88e6095_g1_set_egress_port, 4315 .watchdog_ops = &mv88e6097_watchdog_ops, 4316 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4317 .pot_clear = mv88e6xxx_g2_pot_clear, 4318 .reset = mv88e6352_g1_reset, 4319 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4320 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4321 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4322 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4323 .stu_getnext = mv88e6352_g1_stu_getnext, 4324 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4325 .phylink_get_caps = mv88e6185_phylink_get_caps, 4326 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4327 }; 4328 4329 static const struct mv88e6xxx_ops mv88e6131_ops = { 4330 /* MV88E6XXX_FAMILY_6185 */ 4331 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4332 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4333 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4334 .phy_read = mv88e6185_phy_ppu_read, 4335 .phy_write = mv88e6185_phy_ppu_write, 4336 .port_set_link = mv88e6xxx_port_set_link, 4337 .port_sync_link = mv88e6xxx_port_sync_link, 4338 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4339 .port_tag_remap = mv88e6095_port_tag_remap, 4340 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4341 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4342 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4343 .port_set_ether_type = mv88e6351_port_set_ether_type, 4344 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4345 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4346 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4347 .port_pause_limit = mv88e6097_port_pause_limit, 4348 .port_set_pause = mv88e6185_port_set_pause, 4349 .port_get_cmode = mv88e6185_port_get_cmode, 4350 .port_setup_message_port = mv88e6xxx_setup_message_port, 4351 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4352 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4353 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4354 .stats_get_strings = mv88e6095_stats_get_strings, 4355 .stats_get_stats = mv88e6095_stats_get_stats, 4356 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4357 .set_egress_port = mv88e6095_g1_set_egress_port, 4358 .watchdog_ops = &mv88e6097_watchdog_ops, 4359 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4360 .ppu_enable = mv88e6185_g1_ppu_enable, 4361 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4362 .ppu_disable = mv88e6185_g1_ppu_disable, 4363 .reset = mv88e6185_g1_reset, 4364 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4365 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4366 .phylink_get_caps = mv88e6185_phylink_get_caps, 4367 }; 4368 4369 static const struct mv88e6xxx_ops mv88e6141_ops = { 4370 /* MV88E6XXX_FAMILY_6341 */ 4371 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4372 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4373 .irl_init_all = mv88e6352_g2_irl_init_all, 4374 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4375 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4376 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4377 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4378 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4379 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4380 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4381 .port_set_link = mv88e6xxx_port_set_link, 4382 .port_sync_link = mv88e6xxx_port_sync_link, 4383 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4384 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4385 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4386 .port_tag_remap = mv88e6095_port_tag_remap, 4387 .port_set_policy = mv88e6352_port_set_policy, 4388 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4389 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4390 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4391 .port_set_ether_type = mv88e6351_port_set_ether_type, 4392 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4393 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4394 .port_pause_limit = mv88e6097_port_pause_limit, 4395 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4396 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4397 .port_get_cmode = mv88e6352_port_get_cmode, 4398 .port_set_cmode = mv88e6341_port_set_cmode, 4399 .port_setup_message_port = mv88e6xxx_setup_message_port, 4400 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4401 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4402 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4403 .stats_get_strings = mv88e6320_stats_get_strings, 4404 .stats_get_stats = mv88e6390_stats_get_stats, 4405 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4406 .set_egress_port = mv88e6390_g1_set_egress_port, 4407 .watchdog_ops = &mv88e6390_watchdog_ops, 4408 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4409 .pot_clear = mv88e6xxx_g2_pot_clear, 4410 .reset = mv88e6352_g1_reset, 4411 .rmu_disable = mv88e6390_g1_rmu_disable, 4412 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4413 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4414 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4415 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4416 .stu_getnext = mv88e6352_g1_stu_getnext, 4417 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4418 .serdes_power = mv88e6390_serdes_power, 4419 .serdes_get_lane = mv88e6341_serdes_get_lane, 4420 /* Check status register pause & lpa register */ 4421 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4422 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4423 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4424 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4425 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4426 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4427 .serdes_irq_status = mv88e6390_serdes_irq_status, 4428 .gpio_ops = &mv88e6352_gpio_ops, 4429 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4430 .serdes_get_strings = mv88e6390_serdes_get_strings, 4431 .serdes_get_stats = mv88e6390_serdes_get_stats, 4432 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4433 .serdes_get_regs = mv88e6390_serdes_get_regs, 4434 .phylink_get_caps = mv88e6341_phylink_get_caps, 4435 }; 4436 4437 static const struct mv88e6xxx_ops mv88e6161_ops = { 4438 /* MV88E6XXX_FAMILY_6165 */ 4439 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4440 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4441 .irl_init_all = mv88e6352_g2_irl_init_all, 4442 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4443 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4444 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4445 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4446 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4447 .port_set_link = mv88e6xxx_port_set_link, 4448 .port_sync_link = mv88e6xxx_port_sync_link, 4449 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4450 .port_tag_remap = mv88e6095_port_tag_remap, 4451 .port_set_policy = mv88e6352_port_set_policy, 4452 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4453 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4454 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4455 .port_set_ether_type = mv88e6351_port_set_ether_type, 4456 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4457 .port_pause_limit = mv88e6097_port_pause_limit, 4458 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4459 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4460 .port_get_cmode = mv88e6185_port_get_cmode, 4461 .port_setup_message_port = mv88e6xxx_setup_message_port, 4462 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4463 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4464 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4465 .stats_get_strings = mv88e6095_stats_get_strings, 4466 .stats_get_stats = mv88e6095_stats_get_stats, 4467 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4468 .set_egress_port = mv88e6095_g1_set_egress_port, 4469 .watchdog_ops = &mv88e6097_watchdog_ops, 4470 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4471 .pot_clear = mv88e6xxx_g2_pot_clear, 4472 .reset = mv88e6352_g1_reset, 4473 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4474 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4475 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4476 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4477 .stu_getnext = mv88e6352_g1_stu_getnext, 4478 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4479 .avb_ops = &mv88e6165_avb_ops, 4480 .ptp_ops = &mv88e6165_ptp_ops, 4481 .phylink_get_caps = mv88e6185_phylink_get_caps, 4482 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4483 }; 4484 4485 static const struct mv88e6xxx_ops mv88e6165_ops = { 4486 /* MV88E6XXX_FAMILY_6165 */ 4487 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4488 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4489 .irl_init_all = mv88e6352_g2_irl_init_all, 4490 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4491 .phy_read = mv88e6165_phy_read, 4492 .phy_write = mv88e6165_phy_write, 4493 .port_set_link = mv88e6xxx_port_set_link, 4494 .port_sync_link = mv88e6xxx_port_sync_link, 4495 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4496 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4497 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4498 .port_get_cmode = mv88e6185_port_get_cmode, 4499 .port_setup_message_port = mv88e6xxx_setup_message_port, 4500 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4501 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4502 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4503 .stats_get_strings = mv88e6095_stats_get_strings, 4504 .stats_get_stats = mv88e6095_stats_get_stats, 4505 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4506 .set_egress_port = mv88e6095_g1_set_egress_port, 4507 .watchdog_ops = &mv88e6097_watchdog_ops, 4508 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4509 .pot_clear = mv88e6xxx_g2_pot_clear, 4510 .reset = mv88e6352_g1_reset, 4511 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4512 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4513 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4514 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4515 .stu_getnext = mv88e6352_g1_stu_getnext, 4516 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4517 .avb_ops = &mv88e6165_avb_ops, 4518 .ptp_ops = &mv88e6165_ptp_ops, 4519 .phylink_get_caps = mv88e6185_phylink_get_caps, 4520 }; 4521 4522 static const struct mv88e6xxx_ops mv88e6171_ops = { 4523 /* MV88E6XXX_FAMILY_6351 */ 4524 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4525 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4526 .irl_init_all = mv88e6352_g2_irl_init_all, 4527 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4528 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4529 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4530 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4531 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4532 .port_set_link = mv88e6xxx_port_set_link, 4533 .port_sync_link = mv88e6xxx_port_sync_link, 4534 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4535 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4536 .port_tag_remap = mv88e6095_port_tag_remap, 4537 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4538 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4539 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4540 .port_set_ether_type = mv88e6351_port_set_ether_type, 4541 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4542 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4543 .port_pause_limit = mv88e6097_port_pause_limit, 4544 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4545 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4546 .port_get_cmode = mv88e6352_port_get_cmode, 4547 .port_setup_message_port = mv88e6xxx_setup_message_port, 4548 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4549 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4550 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4551 .stats_get_strings = mv88e6095_stats_get_strings, 4552 .stats_get_stats = mv88e6095_stats_get_stats, 4553 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4554 .set_egress_port = mv88e6095_g1_set_egress_port, 4555 .watchdog_ops = &mv88e6097_watchdog_ops, 4556 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4557 .pot_clear = mv88e6xxx_g2_pot_clear, 4558 .reset = mv88e6352_g1_reset, 4559 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4560 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4561 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4562 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4563 .stu_getnext = mv88e6352_g1_stu_getnext, 4564 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4565 .phylink_get_caps = mv88e6185_phylink_get_caps, 4566 }; 4567 4568 static const struct mv88e6xxx_ops mv88e6172_ops = { 4569 /* MV88E6XXX_FAMILY_6352 */ 4570 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4571 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4572 .irl_init_all = mv88e6352_g2_irl_init_all, 4573 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4574 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4576 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4577 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4578 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4579 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4580 .port_set_link = mv88e6xxx_port_set_link, 4581 .port_sync_link = mv88e6xxx_port_sync_link, 4582 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4583 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4584 .port_tag_remap = mv88e6095_port_tag_remap, 4585 .port_set_policy = mv88e6352_port_set_policy, 4586 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4587 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4588 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4589 .port_set_ether_type = mv88e6351_port_set_ether_type, 4590 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4592 .port_pause_limit = mv88e6097_port_pause_limit, 4593 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4594 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4595 .port_get_cmode = mv88e6352_port_get_cmode, 4596 .port_setup_message_port = mv88e6xxx_setup_message_port, 4597 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4598 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4599 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4600 .stats_get_strings = mv88e6095_stats_get_strings, 4601 .stats_get_stats = mv88e6095_stats_get_stats, 4602 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4603 .set_egress_port = mv88e6095_g1_set_egress_port, 4604 .watchdog_ops = &mv88e6097_watchdog_ops, 4605 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4606 .pot_clear = mv88e6xxx_g2_pot_clear, 4607 .reset = mv88e6352_g1_reset, 4608 .rmu_disable = mv88e6352_g1_rmu_disable, 4609 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4610 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4611 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4612 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4613 .stu_getnext = mv88e6352_g1_stu_getnext, 4614 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4615 .serdes_get_lane = mv88e6352_serdes_get_lane, 4616 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4617 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4618 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4619 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4620 .serdes_power = mv88e6352_serdes_power, 4621 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4622 .serdes_get_regs = mv88e6352_serdes_get_regs, 4623 .gpio_ops = &mv88e6352_gpio_ops, 4624 .phylink_get_caps = mv88e6352_phylink_get_caps, 4625 }; 4626 4627 static const struct mv88e6xxx_ops mv88e6175_ops = { 4628 /* MV88E6XXX_FAMILY_6351 */ 4629 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4630 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4631 .irl_init_all = mv88e6352_g2_irl_init_all, 4632 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4633 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4634 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4635 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4636 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4637 .port_set_link = mv88e6xxx_port_set_link, 4638 .port_sync_link = mv88e6xxx_port_sync_link, 4639 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4640 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4641 .port_tag_remap = mv88e6095_port_tag_remap, 4642 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4643 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4644 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4645 .port_set_ether_type = mv88e6351_port_set_ether_type, 4646 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4647 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4648 .port_pause_limit = mv88e6097_port_pause_limit, 4649 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4650 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4651 .port_get_cmode = mv88e6352_port_get_cmode, 4652 .port_setup_message_port = mv88e6xxx_setup_message_port, 4653 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4654 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4655 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4656 .stats_get_strings = mv88e6095_stats_get_strings, 4657 .stats_get_stats = mv88e6095_stats_get_stats, 4658 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4659 .set_egress_port = mv88e6095_g1_set_egress_port, 4660 .watchdog_ops = &mv88e6097_watchdog_ops, 4661 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4662 .pot_clear = mv88e6xxx_g2_pot_clear, 4663 .reset = mv88e6352_g1_reset, 4664 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4665 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4666 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4667 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4668 .stu_getnext = mv88e6352_g1_stu_getnext, 4669 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4670 .phylink_get_caps = mv88e6185_phylink_get_caps, 4671 }; 4672 4673 static const struct mv88e6xxx_ops mv88e6176_ops = { 4674 /* MV88E6XXX_FAMILY_6352 */ 4675 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4676 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4677 .irl_init_all = mv88e6352_g2_irl_init_all, 4678 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4679 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4680 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4681 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4682 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4683 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4684 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4685 .port_set_link = mv88e6xxx_port_set_link, 4686 .port_sync_link = mv88e6xxx_port_sync_link, 4687 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4688 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4689 .port_tag_remap = mv88e6095_port_tag_remap, 4690 .port_set_policy = mv88e6352_port_set_policy, 4691 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4692 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4693 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4694 .port_set_ether_type = mv88e6351_port_set_ether_type, 4695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4697 .port_pause_limit = mv88e6097_port_pause_limit, 4698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4700 .port_get_cmode = mv88e6352_port_get_cmode, 4701 .port_setup_message_port = mv88e6xxx_setup_message_port, 4702 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4703 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4704 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4705 .stats_get_strings = mv88e6095_stats_get_strings, 4706 .stats_get_stats = mv88e6095_stats_get_stats, 4707 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4708 .set_egress_port = mv88e6095_g1_set_egress_port, 4709 .watchdog_ops = &mv88e6097_watchdog_ops, 4710 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4711 .pot_clear = mv88e6xxx_g2_pot_clear, 4712 .reset = mv88e6352_g1_reset, 4713 .rmu_disable = mv88e6352_g1_rmu_disable, 4714 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4715 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4716 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4717 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4718 .stu_getnext = mv88e6352_g1_stu_getnext, 4719 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4720 .serdes_get_lane = mv88e6352_serdes_get_lane, 4721 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4722 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4723 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4724 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4725 .serdes_power = mv88e6352_serdes_power, 4726 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4727 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4728 .serdes_irq_status = mv88e6352_serdes_irq_status, 4729 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4730 .serdes_get_regs = mv88e6352_serdes_get_regs, 4731 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4732 .gpio_ops = &mv88e6352_gpio_ops, 4733 .phylink_get_caps = mv88e6352_phylink_get_caps, 4734 }; 4735 4736 static const struct mv88e6xxx_ops mv88e6185_ops = { 4737 /* MV88E6XXX_FAMILY_6185 */ 4738 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4739 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4740 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4741 .phy_read = mv88e6185_phy_ppu_read, 4742 .phy_write = mv88e6185_phy_ppu_write, 4743 .port_set_link = mv88e6xxx_port_set_link, 4744 .port_sync_link = mv88e6185_port_sync_link, 4745 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4746 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4747 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4748 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4749 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4750 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4751 .port_set_pause = mv88e6185_port_set_pause, 4752 .port_get_cmode = mv88e6185_port_get_cmode, 4753 .port_setup_message_port = mv88e6xxx_setup_message_port, 4754 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4755 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4756 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4757 .stats_get_strings = mv88e6095_stats_get_strings, 4758 .stats_get_stats = mv88e6095_stats_get_stats, 4759 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4760 .set_egress_port = mv88e6095_g1_set_egress_port, 4761 .watchdog_ops = &mv88e6097_watchdog_ops, 4762 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4763 .serdes_power = mv88e6185_serdes_power, 4764 .serdes_get_lane = mv88e6185_serdes_get_lane, 4765 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4766 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4767 .ppu_enable = mv88e6185_g1_ppu_enable, 4768 .ppu_disable = mv88e6185_g1_ppu_disable, 4769 .reset = mv88e6185_g1_reset, 4770 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4771 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4772 .phylink_get_caps = mv88e6185_phylink_get_caps, 4773 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4774 }; 4775 4776 static const struct mv88e6xxx_ops mv88e6190_ops = { 4777 /* MV88E6XXX_FAMILY_6390 */ 4778 .setup_errata = mv88e6390_setup_errata, 4779 .irl_init_all = mv88e6390_g2_irl_init_all, 4780 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4781 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4782 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4783 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4784 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4785 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4786 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4787 .port_set_link = mv88e6xxx_port_set_link, 4788 .port_sync_link = mv88e6xxx_port_sync_link, 4789 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4790 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4791 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4792 .port_tag_remap = mv88e6390_port_tag_remap, 4793 .port_set_policy = mv88e6352_port_set_policy, 4794 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4795 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4796 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4797 .port_set_ether_type = mv88e6351_port_set_ether_type, 4798 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4799 .port_pause_limit = mv88e6390_port_pause_limit, 4800 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4801 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4802 .port_get_cmode = mv88e6352_port_get_cmode, 4803 .port_set_cmode = mv88e6390_port_set_cmode, 4804 .port_setup_message_port = mv88e6xxx_setup_message_port, 4805 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4806 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4807 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4808 .stats_get_strings = mv88e6320_stats_get_strings, 4809 .stats_get_stats = mv88e6390_stats_get_stats, 4810 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4811 .set_egress_port = mv88e6390_g1_set_egress_port, 4812 .watchdog_ops = &mv88e6390_watchdog_ops, 4813 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4814 .pot_clear = mv88e6xxx_g2_pot_clear, 4815 .reset = mv88e6352_g1_reset, 4816 .rmu_disable = mv88e6390_g1_rmu_disable, 4817 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4818 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4819 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4820 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4821 .stu_getnext = mv88e6390_g1_stu_getnext, 4822 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4823 .serdes_power = mv88e6390_serdes_power, 4824 .serdes_get_lane = mv88e6390_serdes_get_lane, 4825 /* Check status register pause & lpa register */ 4826 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4827 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4828 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4829 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4830 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4831 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4832 .serdes_irq_status = mv88e6390_serdes_irq_status, 4833 .serdes_get_strings = mv88e6390_serdes_get_strings, 4834 .serdes_get_stats = mv88e6390_serdes_get_stats, 4835 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4836 .serdes_get_regs = mv88e6390_serdes_get_regs, 4837 .gpio_ops = &mv88e6352_gpio_ops, 4838 .phylink_get_caps = mv88e6390_phylink_get_caps, 4839 }; 4840 4841 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4842 /* MV88E6XXX_FAMILY_6390 */ 4843 .setup_errata = mv88e6390_setup_errata, 4844 .irl_init_all = mv88e6390_g2_irl_init_all, 4845 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4846 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4847 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4848 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4849 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4850 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4851 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4852 .port_set_link = mv88e6xxx_port_set_link, 4853 .port_sync_link = mv88e6xxx_port_sync_link, 4854 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4855 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4856 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4857 .port_tag_remap = mv88e6390_port_tag_remap, 4858 .port_set_policy = mv88e6352_port_set_policy, 4859 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4860 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4861 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4862 .port_set_ether_type = mv88e6351_port_set_ether_type, 4863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4864 .port_pause_limit = mv88e6390_port_pause_limit, 4865 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4866 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4867 .port_get_cmode = mv88e6352_port_get_cmode, 4868 .port_set_cmode = mv88e6390x_port_set_cmode, 4869 .port_setup_message_port = mv88e6xxx_setup_message_port, 4870 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4871 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4872 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4873 .stats_get_strings = mv88e6320_stats_get_strings, 4874 .stats_get_stats = mv88e6390_stats_get_stats, 4875 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4876 .set_egress_port = mv88e6390_g1_set_egress_port, 4877 .watchdog_ops = &mv88e6390_watchdog_ops, 4878 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4879 .pot_clear = mv88e6xxx_g2_pot_clear, 4880 .reset = mv88e6352_g1_reset, 4881 .rmu_disable = mv88e6390_g1_rmu_disable, 4882 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4883 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4884 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4885 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4886 .stu_getnext = mv88e6390_g1_stu_getnext, 4887 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4888 .serdes_power = mv88e6390_serdes_power, 4889 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4890 /* Check status register pause & lpa register */ 4891 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4892 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4893 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4894 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4895 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4896 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4897 .serdes_irq_status = mv88e6390_serdes_irq_status, 4898 .serdes_get_strings = mv88e6390_serdes_get_strings, 4899 .serdes_get_stats = mv88e6390_serdes_get_stats, 4900 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4901 .serdes_get_regs = mv88e6390_serdes_get_regs, 4902 .gpio_ops = &mv88e6352_gpio_ops, 4903 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4904 }; 4905 4906 static const struct mv88e6xxx_ops mv88e6191_ops = { 4907 /* MV88E6XXX_FAMILY_6390 */ 4908 .setup_errata = mv88e6390_setup_errata, 4909 .irl_init_all = mv88e6390_g2_irl_init_all, 4910 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4911 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4912 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4913 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4914 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4915 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4916 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4917 .port_set_link = mv88e6xxx_port_set_link, 4918 .port_sync_link = mv88e6xxx_port_sync_link, 4919 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4920 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4921 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4922 .port_tag_remap = mv88e6390_port_tag_remap, 4923 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4924 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4925 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4926 .port_set_ether_type = mv88e6351_port_set_ether_type, 4927 .port_pause_limit = mv88e6390_port_pause_limit, 4928 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4929 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4930 .port_get_cmode = mv88e6352_port_get_cmode, 4931 .port_set_cmode = mv88e6390_port_set_cmode, 4932 .port_setup_message_port = mv88e6xxx_setup_message_port, 4933 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4934 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4935 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4936 .stats_get_strings = mv88e6320_stats_get_strings, 4937 .stats_get_stats = mv88e6390_stats_get_stats, 4938 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4939 .set_egress_port = mv88e6390_g1_set_egress_port, 4940 .watchdog_ops = &mv88e6390_watchdog_ops, 4941 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4942 .pot_clear = mv88e6xxx_g2_pot_clear, 4943 .reset = mv88e6352_g1_reset, 4944 .rmu_disable = mv88e6390_g1_rmu_disable, 4945 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4946 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4947 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4948 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4949 .stu_getnext = mv88e6390_g1_stu_getnext, 4950 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4951 .serdes_power = mv88e6390_serdes_power, 4952 .serdes_get_lane = mv88e6390_serdes_get_lane, 4953 /* Check status register pause & lpa register */ 4954 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4955 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4956 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4957 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4958 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4959 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4960 .serdes_irq_status = mv88e6390_serdes_irq_status, 4961 .serdes_get_strings = mv88e6390_serdes_get_strings, 4962 .serdes_get_stats = mv88e6390_serdes_get_stats, 4963 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4964 .serdes_get_regs = mv88e6390_serdes_get_regs, 4965 .avb_ops = &mv88e6390_avb_ops, 4966 .ptp_ops = &mv88e6352_ptp_ops, 4967 .phylink_get_caps = mv88e6390_phylink_get_caps, 4968 }; 4969 4970 static const struct mv88e6xxx_ops mv88e6240_ops = { 4971 /* MV88E6XXX_FAMILY_6352 */ 4972 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4973 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4974 .irl_init_all = mv88e6352_g2_irl_init_all, 4975 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4976 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4977 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4978 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4979 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4980 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4981 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4982 .port_set_link = mv88e6xxx_port_set_link, 4983 .port_sync_link = mv88e6xxx_port_sync_link, 4984 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4985 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4986 .port_tag_remap = mv88e6095_port_tag_remap, 4987 .port_set_policy = mv88e6352_port_set_policy, 4988 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4989 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4990 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4991 .port_set_ether_type = mv88e6351_port_set_ether_type, 4992 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4993 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4994 .port_pause_limit = mv88e6097_port_pause_limit, 4995 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4997 .port_get_cmode = mv88e6352_port_get_cmode, 4998 .port_setup_message_port = mv88e6xxx_setup_message_port, 4999 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5000 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5001 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5002 .stats_get_strings = mv88e6095_stats_get_strings, 5003 .stats_get_stats = mv88e6095_stats_get_stats, 5004 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5005 .set_egress_port = mv88e6095_g1_set_egress_port, 5006 .watchdog_ops = &mv88e6097_watchdog_ops, 5007 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5008 .pot_clear = mv88e6xxx_g2_pot_clear, 5009 .reset = mv88e6352_g1_reset, 5010 .rmu_disable = mv88e6352_g1_rmu_disable, 5011 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5012 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5013 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5014 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5015 .stu_getnext = mv88e6352_g1_stu_getnext, 5016 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5017 .serdes_get_lane = mv88e6352_serdes_get_lane, 5018 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5019 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5020 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5021 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5022 .serdes_power = mv88e6352_serdes_power, 5023 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5024 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5025 .serdes_irq_status = mv88e6352_serdes_irq_status, 5026 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5027 .serdes_get_regs = mv88e6352_serdes_get_regs, 5028 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5029 .gpio_ops = &mv88e6352_gpio_ops, 5030 .avb_ops = &mv88e6352_avb_ops, 5031 .ptp_ops = &mv88e6352_ptp_ops, 5032 .phylink_get_caps = mv88e6352_phylink_get_caps, 5033 }; 5034 5035 static const struct mv88e6xxx_ops mv88e6250_ops = { 5036 /* MV88E6XXX_FAMILY_6250 */ 5037 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5038 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5039 .irl_init_all = mv88e6352_g2_irl_init_all, 5040 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5041 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5042 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5043 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5044 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5045 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5046 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5047 .port_set_link = mv88e6xxx_port_set_link, 5048 .port_sync_link = mv88e6xxx_port_sync_link, 5049 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5050 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5051 .port_tag_remap = mv88e6095_port_tag_remap, 5052 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5053 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5054 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5055 .port_set_ether_type = mv88e6351_port_set_ether_type, 5056 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5057 .port_pause_limit = mv88e6097_port_pause_limit, 5058 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5059 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5060 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5061 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5062 .stats_get_strings = mv88e6250_stats_get_strings, 5063 .stats_get_stats = mv88e6250_stats_get_stats, 5064 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5065 .set_egress_port = mv88e6095_g1_set_egress_port, 5066 .watchdog_ops = &mv88e6250_watchdog_ops, 5067 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5068 .pot_clear = mv88e6xxx_g2_pot_clear, 5069 .reset = mv88e6250_g1_reset, 5070 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5071 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5072 .avb_ops = &mv88e6352_avb_ops, 5073 .ptp_ops = &mv88e6250_ptp_ops, 5074 .phylink_get_caps = mv88e6250_phylink_get_caps, 5075 }; 5076 5077 static const struct mv88e6xxx_ops mv88e6290_ops = { 5078 /* MV88E6XXX_FAMILY_6390 */ 5079 .setup_errata = mv88e6390_setup_errata, 5080 .irl_init_all = mv88e6390_g2_irl_init_all, 5081 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5082 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5083 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5084 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5085 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5086 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5087 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5088 .port_set_link = mv88e6xxx_port_set_link, 5089 .port_sync_link = mv88e6xxx_port_sync_link, 5090 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5091 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5092 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5093 .port_tag_remap = mv88e6390_port_tag_remap, 5094 .port_set_policy = mv88e6352_port_set_policy, 5095 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5096 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5097 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5098 .port_set_ether_type = mv88e6351_port_set_ether_type, 5099 .port_pause_limit = mv88e6390_port_pause_limit, 5100 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5101 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5102 .port_get_cmode = mv88e6352_port_get_cmode, 5103 .port_set_cmode = mv88e6390_port_set_cmode, 5104 .port_setup_message_port = mv88e6xxx_setup_message_port, 5105 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5106 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5107 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5108 .stats_get_strings = mv88e6320_stats_get_strings, 5109 .stats_get_stats = mv88e6390_stats_get_stats, 5110 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5111 .set_egress_port = mv88e6390_g1_set_egress_port, 5112 .watchdog_ops = &mv88e6390_watchdog_ops, 5113 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5114 .pot_clear = mv88e6xxx_g2_pot_clear, 5115 .reset = mv88e6352_g1_reset, 5116 .rmu_disable = mv88e6390_g1_rmu_disable, 5117 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5118 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5119 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5120 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5121 .stu_getnext = mv88e6390_g1_stu_getnext, 5122 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5123 .serdes_power = mv88e6390_serdes_power, 5124 .serdes_get_lane = mv88e6390_serdes_get_lane, 5125 /* Check status register pause & lpa register */ 5126 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5127 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5128 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5129 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5130 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5131 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5132 .serdes_irq_status = mv88e6390_serdes_irq_status, 5133 .serdes_get_strings = mv88e6390_serdes_get_strings, 5134 .serdes_get_stats = mv88e6390_serdes_get_stats, 5135 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5136 .serdes_get_regs = mv88e6390_serdes_get_regs, 5137 .gpio_ops = &mv88e6352_gpio_ops, 5138 .avb_ops = &mv88e6390_avb_ops, 5139 .ptp_ops = &mv88e6390_ptp_ops, 5140 .phylink_get_caps = mv88e6390_phylink_get_caps, 5141 }; 5142 5143 static const struct mv88e6xxx_ops mv88e6320_ops = { 5144 /* MV88E6XXX_FAMILY_6320 */ 5145 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5146 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5147 .irl_init_all = mv88e6352_g2_irl_init_all, 5148 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5149 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5150 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5151 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5152 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5153 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5154 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5155 .port_set_link = mv88e6xxx_port_set_link, 5156 .port_sync_link = mv88e6xxx_port_sync_link, 5157 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5158 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5159 .port_tag_remap = mv88e6095_port_tag_remap, 5160 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5161 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5162 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5163 .port_set_ether_type = mv88e6351_port_set_ether_type, 5164 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5165 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5166 .port_pause_limit = mv88e6097_port_pause_limit, 5167 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5168 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5169 .port_get_cmode = mv88e6352_port_get_cmode, 5170 .port_setup_message_port = mv88e6xxx_setup_message_port, 5171 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5172 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5173 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5174 .stats_get_strings = mv88e6320_stats_get_strings, 5175 .stats_get_stats = mv88e6320_stats_get_stats, 5176 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5177 .set_egress_port = mv88e6095_g1_set_egress_port, 5178 .watchdog_ops = &mv88e6390_watchdog_ops, 5179 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5180 .pot_clear = mv88e6xxx_g2_pot_clear, 5181 .reset = mv88e6352_g1_reset, 5182 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5183 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5184 .gpio_ops = &mv88e6352_gpio_ops, 5185 .avb_ops = &mv88e6352_avb_ops, 5186 .ptp_ops = &mv88e6352_ptp_ops, 5187 .phylink_get_caps = mv88e6185_phylink_get_caps, 5188 }; 5189 5190 static const struct mv88e6xxx_ops mv88e6321_ops = { 5191 /* MV88E6XXX_FAMILY_6320 */ 5192 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5193 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5194 .irl_init_all = mv88e6352_g2_irl_init_all, 5195 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5196 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5197 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5198 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5199 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5200 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5201 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5202 .port_set_link = mv88e6xxx_port_set_link, 5203 .port_sync_link = mv88e6xxx_port_sync_link, 5204 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5205 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5206 .port_tag_remap = mv88e6095_port_tag_remap, 5207 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5208 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5209 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5210 .port_set_ether_type = mv88e6351_port_set_ether_type, 5211 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5212 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5213 .port_pause_limit = mv88e6097_port_pause_limit, 5214 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5215 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5216 .port_get_cmode = mv88e6352_port_get_cmode, 5217 .port_setup_message_port = mv88e6xxx_setup_message_port, 5218 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5219 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5220 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5221 .stats_get_strings = mv88e6320_stats_get_strings, 5222 .stats_get_stats = mv88e6320_stats_get_stats, 5223 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5224 .set_egress_port = mv88e6095_g1_set_egress_port, 5225 .watchdog_ops = &mv88e6390_watchdog_ops, 5226 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5227 .reset = mv88e6352_g1_reset, 5228 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5229 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5230 .gpio_ops = &mv88e6352_gpio_ops, 5231 .avb_ops = &mv88e6352_avb_ops, 5232 .ptp_ops = &mv88e6352_ptp_ops, 5233 .phylink_get_caps = mv88e6185_phylink_get_caps, 5234 }; 5235 5236 static const struct mv88e6xxx_ops mv88e6341_ops = { 5237 /* MV88E6XXX_FAMILY_6341 */ 5238 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5239 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5240 .irl_init_all = mv88e6352_g2_irl_init_all, 5241 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5242 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5243 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5244 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5245 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5246 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5247 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5248 .port_set_link = mv88e6xxx_port_set_link, 5249 .port_sync_link = mv88e6xxx_port_sync_link, 5250 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5251 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5252 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5253 .port_tag_remap = mv88e6095_port_tag_remap, 5254 .port_set_policy = mv88e6352_port_set_policy, 5255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5256 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5257 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5258 .port_set_ether_type = mv88e6351_port_set_ether_type, 5259 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5260 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5261 .port_pause_limit = mv88e6097_port_pause_limit, 5262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5264 .port_get_cmode = mv88e6352_port_get_cmode, 5265 .port_set_cmode = mv88e6341_port_set_cmode, 5266 .port_setup_message_port = mv88e6xxx_setup_message_port, 5267 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5268 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5269 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5270 .stats_get_strings = mv88e6320_stats_get_strings, 5271 .stats_get_stats = mv88e6390_stats_get_stats, 5272 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5273 .set_egress_port = mv88e6390_g1_set_egress_port, 5274 .watchdog_ops = &mv88e6390_watchdog_ops, 5275 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5276 .pot_clear = mv88e6xxx_g2_pot_clear, 5277 .reset = mv88e6352_g1_reset, 5278 .rmu_disable = mv88e6390_g1_rmu_disable, 5279 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5280 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5281 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5282 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5283 .stu_getnext = mv88e6352_g1_stu_getnext, 5284 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5285 .serdes_power = mv88e6390_serdes_power, 5286 .serdes_get_lane = mv88e6341_serdes_get_lane, 5287 /* Check status register pause & lpa register */ 5288 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5289 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5290 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5291 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5292 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5293 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5294 .serdes_irq_status = mv88e6390_serdes_irq_status, 5295 .gpio_ops = &mv88e6352_gpio_ops, 5296 .avb_ops = &mv88e6390_avb_ops, 5297 .ptp_ops = &mv88e6352_ptp_ops, 5298 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5299 .serdes_get_strings = mv88e6390_serdes_get_strings, 5300 .serdes_get_stats = mv88e6390_serdes_get_stats, 5301 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5302 .serdes_get_regs = mv88e6390_serdes_get_regs, 5303 .phylink_get_caps = mv88e6341_phylink_get_caps, 5304 }; 5305 5306 static const struct mv88e6xxx_ops mv88e6350_ops = { 5307 /* MV88E6XXX_FAMILY_6351 */ 5308 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5309 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5310 .irl_init_all = mv88e6352_g2_irl_init_all, 5311 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5312 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5313 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5314 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5315 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5316 .port_set_link = mv88e6xxx_port_set_link, 5317 .port_sync_link = mv88e6xxx_port_sync_link, 5318 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5319 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5320 .port_tag_remap = mv88e6095_port_tag_remap, 5321 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5322 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5323 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5324 .port_set_ether_type = mv88e6351_port_set_ether_type, 5325 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5326 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5327 .port_pause_limit = mv88e6097_port_pause_limit, 5328 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5329 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5330 .port_get_cmode = mv88e6352_port_get_cmode, 5331 .port_setup_message_port = mv88e6xxx_setup_message_port, 5332 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5333 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5334 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5335 .stats_get_strings = mv88e6095_stats_get_strings, 5336 .stats_get_stats = mv88e6095_stats_get_stats, 5337 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5338 .set_egress_port = mv88e6095_g1_set_egress_port, 5339 .watchdog_ops = &mv88e6097_watchdog_ops, 5340 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5341 .pot_clear = mv88e6xxx_g2_pot_clear, 5342 .reset = mv88e6352_g1_reset, 5343 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5344 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5345 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5346 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5347 .stu_getnext = mv88e6352_g1_stu_getnext, 5348 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5349 .phylink_get_caps = mv88e6185_phylink_get_caps, 5350 }; 5351 5352 static const struct mv88e6xxx_ops mv88e6351_ops = { 5353 /* MV88E6XXX_FAMILY_6351 */ 5354 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5355 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5356 .irl_init_all = mv88e6352_g2_irl_init_all, 5357 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5358 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5359 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5360 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5361 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5362 .port_set_link = mv88e6xxx_port_set_link, 5363 .port_sync_link = mv88e6xxx_port_sync_link, 5364 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5365 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5366 .port_tag_remap = mv88e6095_port_tag_remap, 5367 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5368 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5369 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5370 .port_set_ether_type = mv88e6351_port_set_ether_type, 5371 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5372 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5373 .port_pause_limit = mv88e6097_port_pause_limit, 5374 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5375 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5376 .port_get_cmode = mv88e6352_port_get_cmode, 5377 .port_setup_message_port = mv88e6xxx_setup_message_port, 5378 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5379 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5380 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5381 .stats_get_strings = mv88e6095_stats_get_strings, 5382 .stats_get_stats = mv88e6095_stats_get_stats, 5383 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5384 .set_egress_port = mv88e6095_g1_set_egress_port, 5385 .watchdog_ops = &mv88e6097_watchdog_ops, 5386 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5387 .pot_clear = mv88e6xxx_g2_pot_clear, 5388 .reset = mv88e6352_g1_reset, 5389 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5390 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5391 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5392 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5393 .stu_getnext = mv88e6352_g1_stu_getnext, 5394 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5395 .avb_ops = &mv88e6352_avb_ops, 5396 .ptp_ops = &mv88e6352_ptp_ops, 5397 .phylink_get_caps = mv88e6185_phylink_get_caps, 5398 }; 5399 5400 static const struct mv88e6xxx_ops mv88e6352_ops = { 5401 /* MV88E6XXX_FAMILY_6352 */ 5402 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5403 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5404 .irl_init_all = mv88e6352_g2_irl_init_all, 5405 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5406 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5407 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5408 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5409 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5410 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5411 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5412 .port_set_link = mv88e6xxx_port_set_link, 5413 .port_sync_link = mv88e6xxx_port_sync_link, 5414 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5415 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5416 .port_tag_remap = mv88e6095_port_tag_remap, 5417 .port_set_policy = mv88e6352_port_set_policy, 5418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5419 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5420 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5421 .port_set_ether_type = mv88e6351_port_set_ether_type, 5422 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5423 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5424 .port_pause_limit = mv88e6097_port_pause_limit, 5425 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5426 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5427 .port_get_cmode = mv88e6352_port_get_cmode, 5428 .port_setup_message_port = mv88e6xxx_setup_message_port, 5429 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5431 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5432 .stats_get_strings = mv88e6095_stats_get_strings, 5433 .stats_get_stats = mv88e6095_stats_get_stats, 5434 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5435 .set_egress_port = mv88e6095_g1_set_egress_port, 5436 .watchdog_ops = &mv88e6097_watchdog_ops, 5437 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5438 .pot_clear = mv88e6xxx_g2_pot_clear, 5439 .reset = mv88e6352_g1_reset, 5440 .rmu_disable = mv88e6352_g1_rmu_disable, 5441 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5442 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5443 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5444 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5445 .stu_getnext = mv88e6352_g1_stu_getnext, 5446 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5447 .serdes_get_lane = mv88e6352_serdes_get_lane, 5448 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5449 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5450 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5451 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5452 .serdes_power = mv88e6352_serdes_power, 5453 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5454 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5455 .serdes_irq_status = mv88e6352_serdes_irq_status, 5456 .gpio_ops = &mv88e6352_gpio_ops, 5457 .avb_ops = &mv88e6352_avb_ops, 5458 .ptp_ops = &mv88e6352_ptp_ops, 5459 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5460 .serdes_get_strings = mv88e6352_serdes_get_strings, 5461 .serdes_get_stats = mv88e6352_serdes_get_stats, 5462 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5463 .serdes_get_regs = mv88e6352_serdes_get_regs, 5464 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5465 .phylink_get_caps = mv88e6352_phylink_get_caps, 5466 }; 5467 5468 static const struct mv88e6xxx_ops mv88e6390_ops = { 5469 /* MV88E6XXX_FAMILY_6390 */ 5470 .setup_errata = mv88e6390_setup_errata, 5471 .irl_init_all = mv88e6390_g2_irl_init_all, 5472 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5473 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5475 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5476 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5477 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5478 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5479 .port_set_link = mv88e6xxx_port_set_link, 5480 .port_sync_link = mv88e6xxx_port_sync_link, 5481 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5482 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5483 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5484 .port_tag_remap = mv88e6390_port_tag_remap, 5485 .port_set_policy = mv88e6352_port_set_policy, 5486 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5487 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5488 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5489 .port_set_ether_type = mv88e6351_port_set_ether_type, 5490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5492 .port_pause_limit = mv88e6390_port_pause_limit, 5493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5495 .port_get_cmode = mv88e6352_port_get_cmode, 5496 .port_set_cmode = mv88e6390_port_set_cmode, 5497 .port_setup_message_port = mv88e6xxx_setup_message_port, 5498 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5499 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5500 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5501 .stats_get_strings = mv88e6320_stats_get_strings, 5502 .stats_get_stats = mv88e6390_stats_get_stats, 5503 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5504 .set_egress_port = mv88e6390_g1_set_egress_port, 5505 .watchdog_ops = &mv88e6390_watchdog_ops, 5506 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5507 .pot_clear = mv88e6xxx_g2_pot_clear, 5508 .reset = mv88e6352_g1_reset, 5509 .rmu_disable = mv88e6390_g1_rmu_disable, 5510 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5511 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5512 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5513 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5514 .stu_getnext = mv88e6390_g1_stu_getnext, 5515 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5516 .serdes_power = mv88e6390_serdes_power, 5517 .serdes_get_lane = mv88e6390_serdes_get_lane, 5518 /* Check status register pause & lpa register */ 5519 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5520 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5521 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5522 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5523 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5524 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5525 .serdes_irq_status = mv88e6390_serdes_irq_status, 5526 .gpio_ops = &mv88e6352_gpio_ops, 5527 .avb_ops = &mv88e6390_avb_ops, 5528 .ptp_ops = &mv88e6390_ptp_ops, 5529 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5530 .serdes_get_strings = mv88e6390_serdes_get_strings, 5531 .serdes_get_stats = mv88e6390_serdes_get_stats, 5532 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5533 .serdes_get_regs = mv88e6390_serdes_get_regs, 5534 .phylink_get_caps = mv88e6390_phylink_get_caps, 5535 }; 5536 5537 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5538 /* MV88E6XXX_FAMILY_6390 */ 5539 .setup_errata = mv88e6390_setup_errata, 5540 .irl_init_all = mv88e6390_g2_irl_init_all, 5541 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5542 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5543 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5544 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5545 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5546 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5547 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5548 .port_set_link = mv88e6xxx_port_set_link, 5549 .port_sync_link = mv88e6xxx_port_sync_link, 5550 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5551 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5552 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5553 .port_tag_remap = mv88e6390_port_tag_remap, 5554 .port_set_policy = mv88e6352_port_set_policy, 5555 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5556 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5557 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5558 .port_set_ether_type = mv88e6351_port_set_ether_type, 5559 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5560 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5561 .port_pause_limit = mv88e6390_port_pause_limit, 5562 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5563 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5564 .port_get_cmode = mv88e6352_port_get_cmode, 5565 .port_set_cmode = mv88e6390x_port_set_cmode, 5566 .port_setup_message_port = mv88e6xxx_setup_message_port, 5567 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5568 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5569 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5570 .stats_get_strings = mv88e6320_stats_get_strings, 5571 .stats_get_stats = mv88e6390_stats_get_stats, 5572 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5573 .set_egress_port = mv88e6390_g1_set_egress_port, 5574 .watchdog_ops = &mv88e6390_watchdog_ops, 5575 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5576 .pot_clear = mv88e6xxx_g2_pot_clear, 5577 .reset = mv88e6352_g1_reset, 5578 .rmu_disable = mv88e6390_g1_rmu_disable, 5579 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5580 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5581 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5582 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5583 .stu_getnext = mv88e6390_g1_stu_getnext, 5584 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5585 .serdes_power = mv88e6390_serdes_power, 5586 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5587 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5588 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5589 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5590 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5591 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5592 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5593 .serdes_irq_status = mv88e6390_serdes_irq_status, 5594 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5595 .serdes_get_strings = mv88e6390_serdes_get_strings, 5596 .serdes_get_stats = mv88e6390_serdes_get_stats, 5597 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5598 .serdes_get_regs = mv88e6390_serdes_get_regs, 5599 .gpio_ops = &mv88e6352_gpio_ops, 5600 .avb_ops = &mv88e6390_avb_ops, 5601 .ptp_ops = &mv88e6390_ptp_ops, 5602 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5603 }; 5604 5605 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5606 /* MV88E6XXX_FAMILY_6393 */ 5607 .setup_errata = mv88e6393x_serdes_setup_errata, 5608 .irl_init_all = mv88e6390_g2_irl_init_all, 5609 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5610 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5611 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5612 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5613 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5614 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5615 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5616 .port_set_link = mv88e6xxx_port_set_link, 5617 .port_sync_link = mv88e6xxx_port_sync_link, 5618 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5619 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5620 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5621 .port_tag_remap = mv88e6390_port_tag_remap, 5622 .port_set_policy = mv88e6393x_port_set_policy, 5623 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5624 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5625 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5626 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5629 .port_pause_limit = mv88e6390_port_pause_limit, 5630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5632 .port_get_cmode = mv88e6352_port_get_cmode, 5633 .port_set_cmode = mv88e6393x_port_set_cmode, 5634 .port_setup_message_port = mv88e6xxx_setup_message_port, 5635 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5636 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5637 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5638 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5639 .stats_get_strings = mv88e6320_stats_get_strings, 5640 .stats_get_stats = mv88e6390_stats_get_stats, 5641 /* .set_cpu_port is missing because this family does not support a global 5642 * CPU port, only per port CPU port which is set via 5643 * .port_set_upstream_port method. 5644 */ 5645 .set_egress_port = mv88e6393x_set_egress_port, 5646 .watchdog_ops = &mv88e6393x_watchdog_ops, 5647 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5648 .pot_clear = mv88e6xxx_g2_pot_clear, 5649 .reset = mv88e6352_g1_reset, 5650 .rmu_disable = mv88e6390_g1_rmu_disable, 5651 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5652 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5653 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5654 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5655 .stu_getnext = mv88e6390_g1_stu_getnext, 5656 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5657 .serdes_power = mv88e6393x_serdes_power, 5658 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5659 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5660 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5661 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5662 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5663 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5664 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5665 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5666 /* TODO: serdes stats */ 5667 .gpio_ops = &mv88e6352_gpio_ops, 5668 .avb_ops = &mv88e6390_avb_ops, 5669 .ptp_ops = &mv88e6352_ptp_ops, 5670 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5671 }; 5672 5673 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5674 [MV88E6085] = { 5675 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5676 .family = MV88E6XXX_FAMILY_6097, 5677 .name = "Marvell 88E6085", 5678 .num_databases = 4096, 5679 .num_macs = 8192, 5680 .num_ports = 10, 5681 .num_internal_phys = 5, 5682 .max_vid = 4095, 5683 .max_sid = 63, 5684 .port_base_addr = 0x10, 5685 .phy_base_addr = 0x0, 5686 .global1_addr = 0x1b, 5687 .global2_addr = 0x1c, 5688 .age_time_coeff = 15000, 5689 .g1_irqs = 8, 5690 .g2_irqs = 10, 5691 .atu_move_port_mask = 0xf, 5692 .pvt = true, 5693 .multi_chip = true, 5694 .ops = &mv88e6085_ops, 5695 }, 5696 5697 [MV88E6095] = { 5698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5699 .family = MV88E6XXX_FAMILY_6095, 5700 .name = "Marvell 88E6095/88E6095F", 5701 .num_databases = 256, 5702 .num_macs = 8192, 5703 .num_ports = 11, 5704 .num_internal_phys = 0, 5705 .max_vid = 4095, 5706 .port_base_addr = 0x10, 5707 .phy_base_addr = 0x0, 5708 .global1_addr = 0x1b, 5709 .global2_addr = 0x1c, 5710 .age_time_coeff = 15000, 5711 .g1_irqs = 8, 5712 .atu_move_port_mask = 0xf, 5713 .multi_chip = true, 5714 .ops = &mv88e6095_ops, 5715 }, 5716 5717 [MV88E6097] = { 5718 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5719 .family = MV88E6XXX_FAMILY_6097, 5720 .name = "Marvell 88E6097/88E6097F", 5721 .num_databases = 4096, 5722 .num_macs = 8192, 5723 .num_ports = 11, 5724 .num_internal_phys = 8, 5725 .max_vid = 4095, 5726 .max_sid = 63, 5727 .port_base_addr = 0x10, 5728 .phy_base_addr = 0x0, 5729 .global1_addr = 0x1b, 5730 .global2_addr = 0x1c, 5731 .age_time_coeff = 15000, 5732 .g1_irqs = 8, 5733 .g2_irqs = 10, 5734 .atu_move_port_mask = 0xf, 5735 .pvt = true, 5736 .multi_chip = true, 5737 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5738 .ops = &mv88e6097_ops, 5739 }, 5740 5741 [MV88E6123] = { 5742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5743 .family = MV88E6XXX_FAMILY_6165, 5744 .name = "Marvell 88E6123", 5745 .num_databases = 4096, 5746 .num_macs = 1024, 5747 .num_ports = 3, 5748 .num_internal_phys = 5, 5749 .max_vid = 4095, 5750 .max_sid = 63, 5751 .port_base_addr = 0x10, 5752 .phy_base_addr = 0x0, 5753 .global1_addr = 0x1b, 5754 .global2_addr = 0x1c, 5755 .age_time_coeff = 15000, 5756 .g1_irqs = 9, 5757 .g2_irqs = 10, 5758 .atu_move_port_mask = 0xf, 5759 .pvt = true, 5760 .multi_chip = true, 5761 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5762 .ops = &mv88e6123_ops, 5763 }, 5764 5765 [MV88E6131] = { 5766 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5767 .family = MV88E6XXX_FAMILY_6185, 5768 .name = "Marvell 88E6131", 5769 .num_databases = 256, 5770 .num_macs = 8192, 5771 .num_ports = 8, 5772 .num_internal_phys = 0, 5773 .max_vid = 4095, 5774 .port_base_addr = 0x10, 5775 .phy_base_addr = 0x0, 5776 .global1_addr = 0x1b, 5777 .global2_addr = 0x1c, 5778 .age_time_coeff = 15000, 5779 .g1_irqs = 9, 5780 .atu_move_port_mask = 0xf, 5781 .multi_chip = true, 5782 .ops = &mv88e6131_ops, 5783 }, 5784 5785 [MV88E6141] = { 5786 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5787 .family = MV88E6XXX_FAMILY_6341, 5788 .name = "Marvell 88E6141", 5789 .num_databases = 4096, 5790 .num_macs = 2048, 5791 .num_ports = 6, 5792 .num_internal_phys = 5, 5793 .num_gpio = 11, 5794 .max_vid = 4095, 5795 .max_sid = 63, 5796 .port_base_addr = 0x10, 5797 .phy_base_addr = 0x10, 5798 .global1_addr = 0x1b, 5799 .global2_addr = 0x1c, 5800 .age_time_coeff = 3750, 5801 .atu_move_port_mask = 0x1f, 5802 .g1_irqs = 9, 5803 .g2_irqs = 10, 5804 .pvt = true, 5805 .multi_chip = true, 5806 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5807 .ops = &mv88e6141_ops, 5808 }, 5809 5810 [MV88E6161] = { 5811 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5812 .family = MV88E6XXX_FAMILY_6165, 5813 .name = "Marvell 88E6161", 5814 .num_databases = 4096, 5815 .num_macs = 1024, 5816 .num_ports = 6, 5817 .num_internal_phys = 5, 5818 .max_vid = 4095, 5819 .max_sid = 63, 5820 .port_base_addr = 0x10, 5821 .phy_base_addr = 0x0, 5822 .global1_addr = 0x1b, 5823 .global2_addr = 0x1c, 5824 .age_time_coeff = 15000, 5825 .g1_irqs = 9, 5826 .g2_irqs = 10, 5827 .atu_move_port_mask = 0xf, 5828 .pvt = true, 5829 .multi_chip = true, 5830 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5831 .ptp_support = true, 5832 .ops = &mv88e6161_ops, 5833 }, 5834 5835 [MV88E6165] = { 5836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5837 .family = MV88E6XXX_FAMILY_6165, 5838 .name = "Marvell 88E6165", 5839 .num_databases = 4096, 5840 .num_macs = 8192, 5841 .num_ports = 6, 5842 .num_internal_phys = 0, 5843 .max_vid = 4095, 5844 .max_sid = 63, 5845 .port_base_addr = 0x10, 5846 .phy_base_addr = 0x0, 5847 .global1_addr = 0x1b, 5848 .global2_addr = 0x1c, 5849 .age_time_coeff = 15000, 5850 .g1_irqs = 9, 5851 .g2_irqs = 10, 5852 .atu_move_port_mask = 0xf, 5853 .pvt = true, 5854 .multi_chip = true, 5855 .ptp_support = true, 5856 .ops = &mv88e6165_ops, 5857 }, 5858 5859 [MV88E6171] = { 5860 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5861 .family = MV88E6XXX_FAMILY_6351, 5862 .name = "Marvell 88E6171", 5863 .num_databases = 4096, 5864 .num_macs = 8192, 5865 .num_ports = 7, 5866 .num_internal_phys = 5, 5867 .max_vid = 4095, 5868 .max_sid = 63, 5869 .port_base_addr = 0x10, 5870 .phy_base_addr = 0x0, 5871 .global1_addr = 0x1b, 5872 .global2_addr = 0x1c, 5873 .age_time_coeff = 15000, 5874 .g1_irqs = 9, 5875 .g2_irqs = 10, 5876 .atu_move_port_mask = 0xf, 5877 .pvt = true, 5878 .multi_chip = true, 5879 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5880 .ops = &mv88e6171_ops, 5881 }, 5882 5883 [MV88E6172] = { 5884 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5885 .family = MV88E6XXX_FAMILY_6352, 5886 .name = "Marvell 88E6172", 5887 .num_databases = 4096, 5888 .num_macs = 8192, 5889 .num_ports = 7, 5890 .num_internal_phys = 5, 5891 .num_gpio = 15, 5892 .max_vid = 4095, 5893 .max_sid = 63, 5894 .port_base_addr = 0x10, 5895 .phy_base_addr = 0x0, 5896 .global1_addr = 0x1b, 5897 .global2_addr = 0x1c, 5898 .age_time_coeff = 15000, 5899 .g1_irqs = 9, 5900 .g2_irqs = 10, 5901 .atu_move_port_mask = 0xf, 5902 .pvt = true, 5903 .multi_chip = true, 5904 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5905 .ops = &mv88e6172_ops, 5906 }, 5907 5908 [MV88E6175] = { 5909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5910 .family = MV88E6XXX_FAMILY_6351, 5911 .name = "Marvell 88E6175", 5912 .num_databases = 4096, 5913 .num_macs = 8192, 5914 .num_ports = 7, 5915 .num_internal_phys = 5, 5916 .max_vid = 4095, 5917 .max_sid = 63, 5918 .port_base_addr = 0x10, 5919 .phy_base_addr = 0x0, 5920 .global1_addr = 0x1b, 5921 .global2_addr = 0x1c, 5922 .age_time_coeff = 15000, 5923 .g1_irqs = 9, 5924 .g2_irqs = 10, 5925 .atu_move_port_mask = 0xf, 5926 .pvt = true, 5927 .multi_chip = true, 5928 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5929 .ops = &mv88e6175_ops, 5930 }, 5931 5932 [MV88E6176] = { 5933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5934 .family = MV88E6XXX_FAMILY_6352, 5935 .name = "Marvell 88E6176", 5936 .num_databases = 4096, 5937 .num_macs = 8192, 5938 .num_ports = 7, 5939 .num_internal_phys = 5, 5940 .num_gpio = 15, 5941 .max_vid = 4095, 5942 .max_sid = 63, 5943 .port_base_addr = 0x10, 5944 .phy_base_addr = 0x0, 5945 .global1_addr = 0x1b, 5946 .global2_addr = 0x1c, 5947 .age_time_coeff = 15000, 5948 .g1_irqs = 9, 5949 .g2_irqs = 10, 5950 .atu_move_port_mask = 0xf, 5951 .pvt = true, 5952 .multi_chip = true, 5953 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5954 .ops = &mv88e6176_ops, 5955 }, 5956 5957 [MV88E6185] = { 5958 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5959 .family = MV88E6XXX_FAMILY_6185, 5960 .name = "Marvell 88E6185", 5961 .num_databases = 256, 5962 .num_macs = 8192, 5963 .num_ports = 10, 5964 .num_internal_phys = 0, 5965 .max_vid = 4095, 5966 .port_base_addr = 0x10, 5967 .phy_base_addr = 0x0, 5968 .global1_addr = 0x1b, 5969 .global2_addr = 0x1c, 5970 .age_time_coeff = 15000, 5971 .g1_irqs = 8, 5972 .atu_move_port_mask = 0xf, 5973 .multi_chip = true, 5974 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5975 .ops = &mv88e6185_ops, 5976 }, 5977 5978 [MV88E6190] = { 5979 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5980 .family = MV88E6XXX_FAMILY_6390, 5981 .name = "Marvell 88E6190", 5982 .num_databases = 4096, 5983 .num_macs = 16384, 5984 .num_ports = 11, /* 10 + Z80 */ 5985 .num_internal_phys = 9, 5986 .num_gpio = 16, 5987 .max_vid = 8191, 5988 .max_sid = 63, 5989 .port_base_addr = 0x0, 5990 .phy_base_addr = 0x0, 5991 .global1_addr = 0x1b, 5992 .global2_addr = 0x1c, 5993 .age_time_coeff = 3750, 5994 .g1_irqs = 9, 5995 .g2_irqs = 14, 5996 .pvt = true, 5997 .multi_chip = true, 5998 .atu_move_port_mask = 0x1f, 5999 .ops = &mv88e6190_ops, 6000 }, 6001 6002 [MV88E6190X] = { 6003 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6004 .family = MV88E6XXX_FAMILY_6390, 6005 .name = "Marvell 88E6190X", 6006 .num_databases = 4096, 6007 .num_macs = 16384, 6008 .num_ports = 11, /* 10 + Z80 */ 6009 .num_internal_phys = 9, 6010 .num_gpio = 16, 6011 .max_vid = 8191, 6012 .max_sid = 63, 6013 .port_base_addr = 0x0, 6014 .phy_base_addr = 0x0, 6015 .global1_addr = 0x1b, 6016 .global2_addr = 0x1c, 6017 .age_time_coeff = 3750, 6018 .g1_irqs = 9, 6019 .g2_irqs = 14, 6020 .atu_move_port_mask = 0x1f, 6021 .pvt = true, 6022 .multi_chip = true, 6023 .ops = &mv88e6190x_ops, 6024 }, 6025 6026 [MV88E6191] = { 6027 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6028 .family = MV88E6XXX_FAMILY_6390, 6029 .name = "Marvell 88E6191", 6030 .num_databases = 4096, 6031 .num_macs = 16384, 6032 .num_ports = 11, /* 10 + Z80 */ 6033 .num_internal_phys = 9, 6034 .max_vid = 8191, 6035 .max_sid = 63, 6036 .port_base_addr = 0x0, 6037 .phy_base_addr = 0x0, 6038 .global1_addr = 0x1b, 6039 .global2_addr = 0x1c, 6040 .age_time_coeff = 3750, 6041 .g1_irqs = 9, 6042 .g2_irqs = 14, 6043 .atu_move_port_mask = 0x1f, 6044 .pvt = true, 6045 .multi_chip = true, 6046 .ptp_support = true, 6047 .ops = &mv88e6191_ops, 6048 }, 6049 6050 [MV88E6191X] = { 6051 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6052 .family = MV88E6XXX_FAMILY_6393, 6053 .name = "Marvell 88E6191X", 6054 .num_databases = 4096, 6055 .num_ports = 11, /* 10 + Z80 */ 6056 .num_internal_phys = 8, 6057 .internal_phys_offset = 1, 6058 .max_vid = 8191, 6059 .max_sid = 63, 6060 .port_base_addr = 0x0, 6061 .phy_base_addr = 0x0, 6062 .global1_addr = 0x1b, 6063 .global2_addr = 0x1c, 6064 .age_time_coeff = 3750, 6065 .g1_irqs = 10, 6066 .g2_irqs = 14, 6067 .atu_move_port_mask = 0x1f, 6068 .pvt = true, 6069 .multi_chip = true, 6070 .ptp_support = true, 6071 .ops = &mv88e6393x_ops, 6072 }, 6073 6074 [MV88E6193X] = { 6075 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6076 .family = MV88E6XXX_FAMILY_6393, 6077 .name = "Marvell 88E6193X", 6078 .num_databases = 4096, 6079 .num_ports = 11, /* 10 + Z80 */ 6080 .num_internal_phys = 8, 6081 .internal_phys_offset = 1, 6082 .max_vid = 8191, 6083 .max_sid = 63, 6084 .port_base_addr = 0x0, 6085 .phy_base_addr = 0x0, 6086 .global1_addr = 0x1b, 6087 .global2_addr = 0x1c, 6088 .age_time_coeff = 3750, 6089 .g1_irqs = 10, 6090 .g2_irqs = 14, 6091 .atu_move_port_mask = 0x1f, 6092 .pvt = true, 6093 .multi_chip = true, 6094 .ptp_support = true, 6095 .ops = &mv88e6393x_ops, 6096 }, 6097 6098 [MV88E6220] = { 6099 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6100 .family = MV88E6XXX_FAMILY_6250, 6101 .name = "Marvell 88E6220", 6102 .num_databases = 64, 6103 6104 /* Ports 2-4 are not routed to pins 6105 * => usable ports 0, 1, 5, 6 6106 */ 6107 .num_ports = 7, 6108 .num_internal_phys = 2, 6109 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6110 .max_vid = 4095, 6111 .port_base_addr = 0x08, 6112 .phy_base_addr = 0x00, 6113 .global1_addr = 0x0f, 6114 .global2_addr = 0x07, 6115 .age_time_coeff = 15000, 6116 .g1_irqs = 9, 6117 .g2_irqs = 10, 6118 .atu_move_port_mask = 0xf, 6119 .dual_chip = true, 6120 .ptp_support = true, 6121 .ops = &mv88e6250_ops, 6122 }, 6123 6124 [MV88E6240] = { 6125 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6126 .family = MV88E6XXX_FAMILY_6352, 6127 .name = "Marvell 88E6240", 6128 .num_databases = 4096, 6129 .num_macs = 8192, 6130 .num_ports = 7, 6131 .num_internal_phys = 5, 6132 .num_gpio = 15, 6133 .max_vid = 4095, 6134 .max_sid = 63, 6135 .port_base_addr = 0x10, 6136 .phy_base_addr = 0x0, 6137 .global1_addr = 0x1b, 6138 .global2_addr = 0x1c, 6139 .age_time_coeff = 15000, 6140 .g1_irqs = 9, 6141 .g2_irqs = 10, 6142 .atu_move_port_mask = 0xf, 6143 .pvt = true, 6144 .multi_chip = true, 6145 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6146 .ptp_support = true, 6147 .ops = &mv88e6240_ops, 6148 }, 6149 6150 [MV88E6250] = { 6151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6152 .family = MV88E6XXX_FAMILY_6250, 6153 .name = "Marvell 88E6250", 6154 .num_databases = 64, 6155 .num_ports = 7, 6156 .num_internal_phys = 5, 6157 .max_vid = 4095, 6158 .port_base_addr = 0x08, 6159 .phy_base_addr = 0x00, 6160 .global1_addr = 0x0f, 6161 .global2_addr = 0x07, 6162 .age_time_coeff = 15000, 6163 .g1_irqs = 9, 6164 .g2_irqs = 10, 6165 .atu_move_port_mask = 0xf, 6166 .dual_chip = true, 6167 .ptp_support = true, 6168 .ops = &mv88e6250_ops, 6169 }, 6170 6171 [MV88E6290] = { 6172 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6173 .family = MV88E6XXX_FAMILY_6390, 6174 .name = "Marvell 88E6290", 6175 .num_databases = 4096, 6176 .num_ports = 11, /* 10 + Z80 */ 6177 .num_internal_phys = 9, 6178 .num_gpio = 16, 6179 .max_vid = 8191, 6180 .max_sid = 63, 6181 .port_base_addr = 0x0, 6182 .phy_base_addr = 0x0, 6183 .global1_addr = 0x1b, 6184 .global2_addr = 0x1c, 6185 .age_time_coeff = 3750, 6186 .g1_irqs = 9, 6187 .g2_irqs = 14, 6188 .atu_move_port_mask = 0x1f, 6189 .pvt = true, 6190 .multi_chip = true, 6191 .ptp_support = true, 6192 .ops = &mv88e6290_ops, 6193 }, 6194 6195 [MV88E6320] = { 6196 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6197 .family = MV88E6XXX_FAMILY_6320, 6198 .name = "Marvell 88E6320", 6199 .num_databases = 4096, 6200 .num_macs = 8192, 6201 .num_ports = 7, 6202 .num_internal_phys = 5, 6203 .num_gpio = 15, 6204 .max_vid = 4095, 6205 .port_base_addr = 0x10, 6206 .phy_base_addr = 0x0, 6207 .global1_addr = 0x1b, 6208 .global2_addr = 0x1c, 6209 .age_time_coeff = 15000, 6210 .g1_irqs = 8, 6211 .g2_irqs = 10, 6212 .atu_move_port_mask = 0xf, 6213 .pvt = true, 6214 .multi_chip = true, 6215 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6216 .ptp_support = true, 6217 .ops = &mv88e6320_ops, 6218 }, 6219 6220 [MV88E6321] = { 6221 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6222 .family = MV88E6XXX_FAMILY_6320, 6223 .name = "Marvell 88E6321", 6224 .num_databases = 4096, 6225 .num_macs = 8192, 6226 .num_ports = 7, 6227 .num_internal_phys = 5, 6228 .num_gpio = 15, 6229 .max_vid = 4095, 6230 .port_base_addr = 0x10, 6231 .phy_base_addr = 0x0, 6232 .global1_addr = 0x1b, 6233 .global2_addr = 0x1c, 6234 .age_time_coeff = 15000, 6235 .g1_irqs = 8, 6236 .g2_irqs = 10, 6237 .atu_move_port_mask = 0xf, 6238 .multi_chip = true, 6239 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6240 .ptp_support = true, 6241 .ops = &mv88e6321_ops, 6242 }, 6243 6244 [MV88E6341] = { 6245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6246 .family = MV88E6XXX_FAMILY_6341, 6247 .name = "Marvell 88E6341", 6248 .num_databases = 4096, 6249 .num_macs = 2048, 6250 .num_internal_phys = 5, 6251 .num_ports = 6, 6252 .num_gpio = 11, 6253 .max_vid = 4095, 6254 .max_sid = 63, 6255 .port_base_addr = 0x10, 6256 .phy_base_addr = 0x10, 6257 .global1_addr = 0x1b, 6258 .global2_addr = 0x1c, 6259 .age_time_coeff = 3750, 6260 .atu_move_port_mask = 0x1f, 6261 .g1_irqs = 9, 6262 .g2_irqs = 10, 6263 .pvt = true, 6264 .multi_chip = true, 6265 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6266 .ptp_support = true, 6267 .ops = &mv88e6341_ops, 6268 }, 6269 6270 [MV88E6350] = { 6271 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6272 .family = MV88E6XXX_FAMILY_6351, 6273 .name = "Marvell 88E6350", 6274 .num_databases = 4096, 6275 .num_macs = 8192, 6276 .num_ports = 7, 6277 .num_internal_phys = 5, 6278 .max_vid = 4095, 6279 .max_sid = 63, 6280 .port_base_addr = 0x10, 6281 .phy_base_addr = 0x0, 6282 .global1_addr = 0x1b, 6283 .global2_addr = 0x1c, 6284 .age_time_coeff = 15000, 6285 .g1_irqs = 9, 6286 .g2_irqs = 10, 6287 .atu_move_port_mask = 0xf, 6288 .pvt = true, 6289 .multi_chip = true, 6290 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6291 .ops = &mv88e6350_ops, 6292 }, 6293 6294 [MV88E6351] = { 6295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6296 .family = MV88E6XXX_FAMILY_6351, 6297 .name = "Marvell 88E6351", 6298 .num_databases = 4096, 6299 .num_macs = 8192, 6300 .num_ports = 7, 6301 .num_internal_phys = 5, 6302 .max_vid = 4095, 6303 .max_sid = 63, 6304 .port_base_addr = 0x10, 6305 .phy_base_addr = 0x0, 6306 .global1_addr = 0x1b, 6307 .global2_addr = 0x1c, 6308 .age_time_coeff = 15000, 6309 .g1_irqs = 9, 6310 .g2_irqs = 10, 6311 .atu_move_port_mask = 0xf, 6312 .pvt = true, 6313 .multi_chip = true, 6314 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6315 .ops = &mv88e6351_ops, 6316 }, 6317 6318 [MV88E6352] = { 6319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6320 .family = MV88E6XXX_FAMILY_6352, 6321 .name = "Marvell 88E6352", 6322 .num_databases = 4096, 6323 .num_macs = 8192, 6324 .num_ports = 7, 6325 .num_internal_phys = 5, 6326 .num_gpio = 15, 6327 .max_vid = 4095, 6328 .max_sid = 63, 6329 .port_base_addr = 0x10, 6330 .phy_base_addr = 0x0, 6331 .global1_addr = 0x1b, 6332 .global2_addr = 0x1c, 6333 .age_time_coeff = 15000, 6334 .g1_irqs = 9, 6335 .g2_irqs = 10, 6336 .atu_move_port_mask = 0xf, 6337 .pvt = true, 6338 .multi_chip = true, 6339 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6340 .ptp_support = true, 6341 .ops = &mv88e6352_ops, 6342 }, 6343 [MV88E6361] = { 6344 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6345 .family = MV88E6XXX_FAMILY_6393, 6346 .name = "Marvell 88E6361", 6347 .num_databases = 4096, 6348 .num_macs = 16384, 6349 .num_ports = 11, 6350 /* Ports 1, 2 and 8 are not routed */ 6351 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6352 .num_internal_phys = 5, 6353 .internal_phys_offset = 3, 6354 .max_vid = 4095, 6355 .max_sid = 63, 6356 .port_base_addr = 0x0, 6357 .phy_base_addr = 0x0, 6358 .global1_addr = 0x1b, 6359 .global2_addr = 0x1c, 6360 .age_time_coeff = 3750, 6361 .g1_irqs = 10, 6362 .g2_irqs = 14, 6363 .atu_move_port_mask = 0x1f, 6364 .pvt = true, 6365 .multi_chip = true, 6366 .ptp_support = true, 6367 .ops = &mv88e6393x_ops, 6368 }, 6369 [MV88E6390] = { 6370 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6371 .family = MV88E6XXX_FAMILY_6390, 6372 .name = "Marvell 88E6390", 6373 .num_databases = 4096, 6374 .num_macs = 16384, 6375 .num_ports = 11, /* 10 + Z80 */ 6376 .num_internal_phys = 9, 6377 .num_gpio = 16, 6378 .max_vid = 8191, 6379 .max_sid = 63, 6380 .port_base_addr = 0x0, 6381 .phy_base_addr = 0x0, 6382 .global1_addr = 0x1b, 6383 .global2_addr = 0x1c, 6384 .age_time_coeff = 3750, 6385 .g1_irqs = 9, 6386 .g2_irqs = 14, 6387 .atu_move_port_mask = 0x1f, 6388 .pvt = true, 6389 .multi_chip = true, 6390 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6391 .ptp_support = true, 6392 .ops = &mv88e6390_ops, 6393 }, 6394 [MV88E6390X] = { 6395 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6396 .family = MV88E6XXX_FAMILY_6390, 6397 .name = "Marvell 88E6390X", 6398 .num_databases = 4096, 6399 .num_macs = 16384, 6400 .num_ports = 11, /* 10 + Z80 */ 6401 .num_internal_phys = 9, 6402 .num_gpio = 16, 6403 .max_vid = 8191, 6404 .max_sid = 63, 6405 .port_base_addr = 0x0, 6406 .phy_base_addr = 0x0, 6407 .global1_addr = 0x1b, 6408 .global2_addr = 0x1c, 6409 .age_time_coeff = 3750, 6410 .g1_irqs = 9, 6411 .g2_irqs = 14, 6412 .atu_move_port_mask = 0x1f, 6413 .pvt = true, 6414 .multi_chip = true, 6415 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6416 .ptp_support = true, 6417 .ops = &mv88e6390x_ops, 6418 }, 6419 6420 [MV88E6393X] = { 6421 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6422 .family = MV88E6XXX_FAMILY_6393, 6423 .name = "Marvell 88E6393X", 6424 .num_databases = 4096, 6425 .num_ports = 11, /* 10 + Z80 */ 6426 .num_internal_phys = 8, 6427 .internal_phys_offset = 1, 6428 .max_vid = 8191, 6429 .max_sid = 63, 6430 .port_base_addr = 0x0, 6431 .phy_base_addr = 0x0, 6432 .global1_addr = 0x1b, 6433 .global2_addr = 0x1c, 6434 .age_time_coeff = 3750, 6435 .g1_irqs = 10, 6436 .g2_irqs = 14, 6437 .atu_move_port_mask = 0x1f, 6438 .pvt = true, 6439 .multi_chip = true, 6440 .ptp_support = true, 6441 .ops = &mv88e6393x_ops, 6442 }, 6443 }; 6444 6445 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6446 { 6447 int i; 6448 6449 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6450 if (mv88e6xxx_table[i].prod_num == prod_num) 6451 return &mv88e6xxx_table[i]; 6452 6453 return NULL; 6454 } 6455 6456 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6457 { 6458 const struct mv88e6xxx_info *info; 6459 unsigned int prod_num, rev; 6460 u16 id; 6461 int err; 6462 6463 mv88e6xxx_reg_lock(chip); 6464 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6465 mv88e6xxx_reg_unlock(chip); 6466 if (err) 6467 return err; 6468 6469 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6470 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6471 6472 info = mv88e6xxx_lookup_info(prod_num); 6473 if (!info) 6474 return -ENODEV; 6475 6476 /* Update the compatible info with the probed one */ 6477 chip->info = info; 6478 6479 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6480 chip->info->prod_num, chip->info->name, rev); 6481 6482 return 0; 6483 } 6484 6485 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6486 struct mdio_device *mdiodev) 6487 { 6488 int err; 6489 6490 /* dual_chip takes precedence over single/multi-chip modes */ 6491 if (chip->info->dual_chip) 6492 return -EINVAL; 6493 6494 /* If the mdio addr is 16 indicating the first port address of a switch 6495 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6496 * configured in single chip addressing mode. Setup the smi access as 6497 * single chip addressing mode and attempt to detect the model of the 6498 * switch, if this fails the device is not configured in single chip 6499 * addressing mode. 6500 */ 6501 if (mdiodev->addr != 16) 6502 return -EINVAL; 6503 6504 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6505 if (err) 6506 return err; 6507 6508 return mv88e6xxx_detect(chip); 6509 } 6510 6511 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6512 { 6513 struct mv88e6xxx_chip *chip; 6514 6515 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6516 if (!chip) 6517 return NULL; 6518 6519 chip->dev = dev; 6520 6521 mutex_init(&chip->reg_lock); 6522 INIT_LIST_HEAD(&chip->mdios); 6523 idr_init(&chip->policies); 6524 INIT_LIST_HEAD(&chip->msts); 6525 6526 return chip; 6527 } 6528 6529 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6530 int port, 6531 enum dsa_tag_protocol m) 6532 { 6533 struct mv88e6xxx_chip *chip = ds->priv; 6534 6535 return chip->tag_protocol; 6536 } 6537 6538 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6539 enum dsa_tag_protocol proto) 6540 { 6541 struct mv88e6xxx_chip *chip = ds->priv; 6542 enum dsa_tag_protocol old_protocol; 6543 struct dsa_port *cpu_dp; 6544 int err; 6545 6546 switch (proto) { 6547 case DSA_TAG_PROTO_EDSA: 6548 switch (chip->info->edsa_support) { 6549 case MV88E6XXX_EDSA_UNSUPPORTED: 6550 return -EPROTONOSUPPORT; 6551 case MV88E6XXX_EDSA_UNDOCUMENTED: 6552 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6553 fallthrough; 6554 case MV88E6XXX_EDSA_SUPPORTED: 6555 break; 6556 } 6557 break; 6558 case DSA_TAG_PROTO_DSA: 6559 break; 6560 default: 6561 return -EPROTONOSUPPORT; 6562 } 6563 6564 old_protocol = chip->tag_protocol; 6565 chip->tag_protocol = proto; 6566 6567 mv88e6xxx_reg_lock(chip); 6568 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6569 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6570 if (err) { 6571 mv88e6xxx_reg_unlock(chip); 6572 goto unwind; 6573 } 6574 } 6575 mv88e6xxx_reg_unlock(chip); 6576 6577 return 0; 6578 6579 unwind: 6580 chip->tag_protocol = old_protocol; 6581 6582 mv88e6xxx_reg_lock(chip); 6583 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6584 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6585 mv88e6xxx_reg_unlock(chip); 6586 6587 return err; 6588 } 6589 6590 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6591 const struct switchdev_obj_port_mdb *mdb, 6592 struct dsa_db db) 6593 { 6594 struct mv88e6xxx_chip *chip = ds->priv; 6595 int err; 6596 6597 mv88e6xxx_reg_lock(chip); 6598 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6599 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6600 mv88e6xxx_reg_unlock(chip); 6601 6602 return err; 6603 } 6604 6605 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6606 const struct switchdev_obj_port_mdb *mdb, 6607 struct dsa_db db) 6608 { 6609 struct mv88e6xxx_chip *chip = ds->priv; 6610 int err; 6611 6612 mv88e6xxx_reg_lock(chip); 6613 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6614 mv88e6xxx_reg_unlock(chip); 6615 6616 return err; 6617 } 6618 6619 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6620 struct dsa_mall_mirror_tc_entry *mirror, 6621 bool ingress, 6622 struct netlink_ext_ack *extack) 6623 { 6624 enum mv88e6xxx_egress_direction direction = ingress ? 6625 MV88E6XXX_EGRESS_DIR_INGRESS : 6626 MV88E6XXX_EGRESS_DIR_EGRESS; 6627 struct mv88e6xxx_chip *chip = ds->priv; 6628 bool other_mirrors = false; 6629 int i; 6630 int err; 6631 6632 mutex_lock(&chip->reg_lock); 6633 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6634 mirror->to_local_port) { 6635 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6636 other_mirrors |= ingress ? 6637 chip->ports[i].mirror_ingress : 6638 chip->ports[i].mirror_egress; 6639 6640 /* Can't change egress port when other mirror is active */ 6641 if (other_mirrors) { 6642 err = -EBUSY; 6643 goto out; 6644 } 6645 6646 err = mv88e6xxx_set_egress_port(chip, direction, 6647 mirror->to_local_port); 6648 if (err) 6649 goto out; 6650 } 6651 6652 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6653 out: 6654 mutex_unlock(&chip->reg_lock); 6655 6656 return err; 6657 } 6658 6659 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6660 struct dsa_mall_mirror_tc_entry *mirror) 6661 { 6662 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6663 MV88E6XXX_EGRESS_DIR_INGRESS : 6664 MV88E6XXX_EGRESS_DIR_EGRESS; 6665 struct mv88e6xxx_chip *chip = ds->priv; 6666 bool other_mirrors = false; 6667 int i; 6668 6669 mutex_lock(&chip->reg_lock); 6670 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6671 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6672 6673 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6674 other_mirrors |= mirror->ingress ? 6675 chip->ports[i].mirror_ingress : 6676 chip->ports[i].mirror_egress; 6677 6678 /* Reset egress port when no other mirror is active */ 6679 if (!other_mirrors) { 6680 if (mv88e6xxx_set_egress_port(chip, direction, 6681 dsa_upstream_port(ds, port))) 6682 dev_err(ds->dev, "failed to set egress port\n"); 6683 } 6684 6685 mutex_unlock(&chip->reg_lock); 6686 } 6687 6688 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6689 struct switchdev_brport_flags flags, 6690 struct netlink_ext_ack *extack) 6691 { 6692 struct mv88e6xxx_chip *chip = ds->priv; 6693 const struct mv88e6xxx_ops *ops; 6694 6695 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6696 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6697 return -EINVAL; 6698 6699 ops = chip->info->ops; 6700 6701 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6702 return -EINVAL; 6703 6704 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6705 return -EINVAL; 6706 6707 return 0; 6708 } 6709 6710 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6711 struct switchdev_brport_flags flags, 6712 struct netlink_ext_ack *extack) 6713 { 6714 struct mv88e6xxx_chip *chip = ds->priv; 6715 int err = 0; 6716 6717 mv88e6xxx_reg_lock(chip); 6718 6719 if (flags.mask & BR_LEARNING) { 6720 bool learning = !!(flags.val & BR_LEARNING); 6721 u16 pav = learning ? (1 << port) : 0; 6722 6723 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6724 if (err) 6725 goto out; 6726 } 6727 6728 if (flags.mask & BR_FLOOD) { 6729 bool unicast = !!(flags.val & BR_FLOOD); 6730 6731 err = chip->info->ops->port_set_ucast_flood(chip, port, 6732 unicast); 6733 if (err) 6734 goto out; 6735 } 6736 6737 if (flags.mask & BR_MCAST_FLOOD) { 6738 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6739 6740 err = chip->info->ops->port_set_mcast_flood(chip, port, 6741 multicast); 6742 if (err) 6743 goto out; 6744 } 6745 6746 if (flags.mask & BR_BCAST_FLOOD) { 6747 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6748 6749 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6750 if (err) 6751 goto out; 6752 } 6753 6754 if (flags.mask & BR_PORT_MAB) { 6755 bool mab = !!(flags.val & BR_PORT_MAB); 6756 6757 mv88e6xxx_port_set_mab(chip, port, mab); 6758 } 6759 6760 if (flags.mask & BR_PORT_LOCKED) { 6761 bool locked = !!(flags.val & BR_PORT_LOCKED); 6762 6763 err = mv88e6xxx_port_set_lock(chip, port, locked); 6764 if (err) 6765 goto out; 6766 } 6767 out: 6768 mv88e6xxx_reg_unlock(chip); 6769 6770 return err; 6771 } 6772 6773 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6774 struct dsa_lag lag, 6775 struct netdev_lag_upper_info *info, 6776 struct netlink_ext_ack *extack) 6777 { 6778 struct mv88e6xxx_chip *chip = ds->priv; 6779 struct dsa_port *dp; 6780 int members = 0; 6781 6782 if (!mv88e6xxx_has_lag(chip)) { 6783 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6784 return false; 6785 } 6786 6787 if (!lag.id) 6788 return false; 6789 6790 dsa_lag_foreach_port(dp, ds->dst, &lag) 6791 /* Includes the port joining the LAG */ 6792 members++; 6793 6794 if (members > 8) { 6795 NL_SET_ERR_MSG_MOD(extack, 6796 "Cannot offload more than 8 LAG ports"); 6797 return false; 6798 } 6799 6800 /* We could potentially relax this to include active 6801 * backup in the future. 6802 */ 6803 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6804 NL_SET_ERR_MSG_MOD(extack, 6805 "Can only offload LAG using hash TX type"); 6806 return false; 6807 } 6808 6809 /* Ideally we would also validate that the hash type matches 6810 * the hardware. Alas, this is always set to unknown on team 6811 * interfaces. 6812 */ 6813 return true; 6814 } 6815 6816 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6817 { 6818 struct mv88e6xxx_chip *chip = ds->priv; 6819 struct dsa_port *dp; 6820 u16 map = 0; 6821 int id; 6822 6823 /* DSA LAG IDs are one-based, hardware is zero-based */ 6824 id = lag.id - 1; 6825 6826 /* Build the map of all ports to distribute flows destined for 6827 * this LAG. This can be either a local user port, or a DSA 6828 * port if the LAG port is on a remote chip. 6829 */ 6830 dsa_lag_foreach_port(dp, ds->dst, &lag) 6831 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6832 6833 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6834 } 6835 6836 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6837 /* Row number corresponds to the number of active members in a 6838 * LAG. Each column states which of the eight hash buckets are 6839 * mapped to the column:th port in the LAG. 6840 * 6841 * Example: In a LAG with three active ports, the second port 6842 * ([2][1]) would be selected for traffic mapped to buckets 6843 * 3,4,5 (0x38). 6844 */ 6845 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6846 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6847 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6848 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6849 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6850 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6851 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6852 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6853 }; 6854 6855 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6856 int num_tx, int nth) 6857 { 6858 u8 active = 0; 6859 int i; 6860 6861 num_tx = num_tx <= 8 ? num_tx : 8; 6862 if (nth < num_tx) 6863 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6864 6865 for (i = 0; i < 8; i++) { 6866 if (BIT(i) & active) 6867 mask[i] |= BIT(port); 6868 } 6869 } 6870 6871 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6872 { 6873 struct mv88e6xxx_chip *chip = ds->priv; 6874 unsigned int id, num_tx; 6875 struct dsa_port *dp; 6876 struct dsa_lag *lag; 6877 int i, err, nth; 6878 u16 mask[8]; 6879 u16 ivec; 6880 6881 /* Assume no port is a member of any LAG. */ 6882 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6883 6884 /* Disable all masks for ports that _are_ members of a LAG. */ 6885 dsa_switch_for_each_port(dp, ds) { 6886 if (!dp->lag) 6887 continue; 6888 6889 ivec &= ~BIT(dp->index); 6890 } 6891 6892 for (i = 0; i < 8; i++) 6893 mask[i] = ivec; 6894 6895 /* Enable the correct subset of masks for all LAG ports that 6896 * are in the Tx set. 6897 */ 6898 dsa_lags_foreach_id(id, ds->dst) { 6899 lag = dsa_lag_by_id(ds->dst, id); 6900 if (!lag) 6901 continue; 6902 6903 num_tx = 0; 6904 dsa_lag_foreach_port(dp, ds->dst, lag) { 6905 if (dp->lag_tx_enabled) 6906 num_tx++; 6907 } 6908 6909 if (!num_tx) 6910 continue; 6911 6912 nth = 0; 6913 dsa_lag_foreach_port(dp, ds->dst, lag) { 6914 if (!dp->lag_tx_enabled) 6915 continue; 6916 6917 if (dp->ds == ds) 6918 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6919 num_tx, nth); 6920 6921 nth++; 6922 } 6923 } 6924 6925 for (i = 0; i < 8; i++) { 6926 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6927 if (err) 6928 return err; 6929 } 6930 6931 return 0; 6932 } 6933 6934 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6935 struct dsa_lag lag) 6936 { 6937 int err; 6938 6939 err = mv88e6xxx_lag_sync_masks(ds); 6940 6941 if (!err) 6942 err = mv88e6xxx_lag_sync_map(ds, lag); 6943 6944 return err; 6945 } 6946 6947 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6948 { 6949 struct mv88e6xxx_chip *chip = ds->priv; 6950 int err; 6951 6952 mv88e6xxx_reg_lock(chip); 6953 err = mv88e6xxx_lag_sync_masks(ds); 6954 mv88e6xxx_reg_unlock(chip); 6955 return err; 6956 } 6957 6958 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6959 struct dsa_lag lag, 6960 struct netdev_lag_upper_info *info, 6961 struct netlink_ext_ack *extack) 6962 { 6963 struct mv88e6xxx_chip *chip = ds->priv; 6964 int err, id; 6965 6966 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6967 return -EOPNOTSUPP; 6968 6969 /* DSA LAG IDs are one-based */ 6970 id = lag.id - 1; 6971 6972 mv88e6xxx_reg_lock(chip); 6973 6974 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6975 if (err) 6976 goto err_unlock; 6977 6978 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6979 if (err) 6980 goto err_clear_trunk; 6981 6982 mv88e6xxx_reg_unlock(chip); 6983 return 0; 6984 6985 err_clear_trunk: 6986 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6987 err_unlock: 6988 mv88e6xxx_reg_unlock(chip); 6989 return err; 6990 } 6991 6992 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6993 struct dsa_lag lag) 6994 { 6995 struct mv88e6xxx_chip *chip = ds->priv; 6996 int err_sync, err_trunk; 6997 6998 mv88e6xxx_reg_lock(chip); 6999 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7000 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7001 mv88e6xxx_reg_unlock(chip); 7002 return err_sync ? : err_trunk; 7003 } 7004 7005 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7006 int port) 7007 { 7008 struct mv88e6xxx_chip *chip = ds->priv; 7009 int err; 7010 7011 mv88e6xxx_reg_lock(chip); 7012 err = mv88e6xxx_lag_sync_masks(ds); 7013 mv88e6xxx_reg_unlock(chip); 7014 return err; 7015 } 7016 7017 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7018 int port, struct dsa_lag lag, 7019 struct netdev_lag_upper_info *info, 7020 struct netlink_ext_ack *extack) 7021 { 7022 struct mv88e6xxx_chip *chip = ds->priv; 7023 int err; 7024 7025 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7026 return -EOPNOTSUPP; 7027 7028 mv88e6xxx_reg_lock(chip); 7029 7030 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7031 if (err) 7032 goto unlock; 7033 7034 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7035 7036 unlock: 7037 mv88e6xxx_reg_unlock(chip); 7038 return err; 7039 } 7040 7041 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7042 int port, struct dsa_lag lag) 7043 { 7044 struct mv88e6xxx_chip *chip = ds->priv; 7045 int err_sync, err_pvt; 7046 7047 mv88e6xxx_reg_lock(chip); 7048 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7049 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7050 mv88e6xxx_reg_unlock(chip); 7051 return err_sync ? : err_pvt; 7052 } 7053 7054 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7055 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7056 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7057 .setup = mv88e6xxx_setup, 7058 .teardown = mv88e6xxx_teardown, 7059 .port_setup = mv88e6xxx_port_setup, 7060 .port_teardown = mv88e6xxx_port_teardown, 7061 .phylink_get_caps = mv88e6xxx_get_caps, 7062 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 7063 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 7064 .phylink_mac_config = mv88e6xxx_mac_config, 7065 .phylink_mac_finish = mv88e6xxx_mac_finish, 7066 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 7067 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7068 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7069 .get_strings = mv88e6xxx_get_strings, 7070 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7071 .get_sset_count = mv88e6xxx_get_sset_count, 7072 .port_enable = mv88e6xxx_port_enable, 7073 .port_disable = mv88e6xxx_port_disable, 7074 .port_max_mtu = mv88e6xxx_get_max_mtu, 7075 .port_change_mtu = mv88e6xxx_change_mtu, 7076 .get_mac_eee = mv88e6xxx_get_mac_eee, 7077 .set_mac_eee = mv88e6xxx_set_mac_eee, 7078 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7079 .get_eeprom = mv88e6xxx_get_eeprom, 7080 .set_eeprom = mv88e6xxx_set_eeprom, 7081 .get_regs_len = mv88e6xxx_get_regs_len, 7082 .get_regs = mv88e6xxx_get_regs, 7083 .get_rxnfc = mv88e6xxx_get_rxnfc, 7084 .set_rxnfc = mv88e6xxx_set_rxnfc, 7085 .set_ageing_time = mv88e6xxx_set_ageing_time, 7086 .port_bridge_join = mv88e6xxx_port_bridge_join, 7087 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7088 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7089 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7090 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7091 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7092 .port_fast_age = mv88e6xxx_port_fast_age, 7093 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7094 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7095 .port_vlan_add = mv88e6xxx_port_vlan_add, 7096 .port_vlan_del = mv88e6xxx_port_vlan_del, 7097 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7098 .port_fdb_add = mv88e6xxx_port_fdb_add, 7099 .port_fdb_del = mv88e6xxx_port_fdb_del, 7100 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7101 .port_mdb_add = mv88e6xxx_port_mdb_add, 7102 .port_mdb_del = mv88e6xxx_port_mdb_del, 7103 .port_mirror_add = mv88e6xxx_port_mirror_add, 7104 .port_mirror_del = mv88e6xxx_port_mirror_del, 7105 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7106 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7107 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7108 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7109 .port_txtstamp = mv88e6xxx_port_txtstamp, 7110 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7111 .get_ts_info = mv88e6xxx_get_ts_info, 7112 .devlink_param_get = mv88e6xxx_devlink_param_get, 7113 .devlink_param_set = mv88e6xxx_devlink_param_set, 7114 .devlink_info_get = mv88e6xxx_devlink_info_get, 7115 .port_lag_change = mv88e6xxx_port_lag_change, 7116 .port_lag_join = mv88e6xxx_port_lag_join, 7117 .port_lag_leave = mv88e6xxx_port_lag_leave, 7118 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7119 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7120 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7121 }; 7122 7123 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7124 { 7125 struct device *dev = chip->dev; 7126 struct dsa_switch *ds; 7127 7128 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7129 if (!ds) 7130 return -ENOMEM; 7131 7132 ds->dev = dev; 7133 ds->num_ports = mv88e6xxx_num_ports(chip); 7134 ds->priv = chip; 7135 ds->dev = dev; 7136 ds->ops = &mv88e6xxx_switch_ops; 7137 ds->ageing_time_min = chip->info->age_time_coeff; 7138 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7139 7140 /* Some chips support up to 32, but that requires enabling the 7141 * 5-bit port mode, which we do not support. 640k^W16 ought to 7142 * be enough for anyone. 7143 */ 7144 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7145 7146 dev_set_drvdata(dev, ds); 7147 7148 return dsa_register_switch(ds); 7149 } 7150 7151 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7152 { 7153 dsa_unregister_switch(chip->ds); 7154 } 7155 7156 static const void *pdata_device_get_match_data(struct device *dev) 7157 { 7158 const struct of_device_id *matches = dev->driver->of_match_table; 7159 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7160 7161 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7162 matches++) { 7163 if (!strcmp(pdata->compatible, matches->compatible)) 7164 return matches->data; 7165 } 7166 return NULL; 7167 } 7168 7169 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7170 * would be lost after a power cycle so prevent it to be suspended. 7171 */ 7172 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7173 { 7174 return -EOPNOTSUPP; 7175 } 7176 7177 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7178 { 7179 return 0; 7180 } 7181 7182 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7183 7184 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7185 { 7186 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7187 const struct mv88e6xxx_info *compat_info = NULL; 7188 struct device *dev = &mdiodev->dev; 7189 struct device_node *np = dev->of_node; 7190 struct mv88e6xxx_chip *chip; 7191 int port; 7192 int err; 7193 7194 if (!np && !pdata) 7195 return -EINVAL; 7196 7197 if (np) 7198 compat_info = of_device_get_match_data(dev); 7199 7200 if (pdata) { 7201 compat_info = pdata_device_get_match_data(dev); 7202 7203 if (!pdata->netdev) 7204 return -EINVAL; 7205 7206 for (port = 0; port < DSA_MAX_PORTS; port++) { 7207 if (!(pdata->enabled_ports & (1 << port))) 7208 continue; 7209 if (strcmp(pdata->cd.port_names[port], "cpu")) 7210 continue; 7211 pdata->cd.netdev[port] = &pdata->netdev->dev; 7212 break; 7213 } 7214 } 7215 7216 if (!compat_info) 7217 return -EINVAL; 7218 7219 chip = mv88e6xxx_alloc_chip(dev); 7220 if (!chip) { 7221 err = -ENOMEM; 7222 goto out; 7223 } 7224 7225 chip->info = compat_info; 7226 7227 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7228 if (IS_ERR(chip->reset)) { 7229 err = PTR_ERR(chip->reset); 7230 goto out; 7231 } 7232 if (chip->reset) 7233 usleep_range(1000, 2000); 7234 7235 /* Detect if the device is configured in single chip addressing mode, 7236 * otherwise continue with address specific smi init/detection. 7237 */ 7238 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7239 if (err) { 7240 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7241 if (err) 7242 goto out; 7243 7244 err = mv88e6xxx_detect(chip); 7245 if (err) 7246 goto out; 7247 } 7248 7249 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7250 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7251 else 7252 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7253 7254 mv88e6xxx_phy_init(chip); 7255 7256 if (chip->info->ops->get_eeprom) { 7257 if (np) 7258 of_property_read_u32(np, "eeprom-length", 7259 &chip->eeprom_len); 7260 else 7261 chip->eeprom_len = pdata->eeprom_len; 7262 } 7263 7264 mv88e6xxx_reg_lock(chip); 7265 err = mv88e6xxx_switch_reset(chip); 7266 mv88e6xxx_reg_unlock(chip); 7267 if (err) 7268 goto out; 7269 7270 if (np) { 7271 chip->irq = of_irq_get(np, 0); 7272 if (chip->irq == -EPROBE_DEFER) { 7273 err = chip->irq; 7274 goto out; 7275 } 7276 } 7277 7278 if (pdata) 7279 chip->irq = pdata->irq; 7280 7281 /* Has to be performed before the MDIO bus is created, because 7282 * the PHYs will link their interrupts to these interrupt 7283 * controllers 7284 */ 7285 mv88e6xxx_reg_lock(chip); 7286 if (chip->irq > 0) 7287 err = mv88e6xxx_g1_irq_setup(chip); 7288 else 7289 err = mv88e6xxx_irq_poll_setup(chip); 7290 mv88e6xxx_reg_unlock(chip); 7291 7292 if (err) 7293 goto out; 7294 7295 if (chip->info->g2_irqs > 0) { 7296 err = mv88e6xxx_g2_irq_setup(chip); 7297 if (err) 7298 goto out_g1_irq; 7299 } 7300 7301 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7302 if (err) 7303 goto out_g2_irq; 7304 7305 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7306 if (err) 7307 goto out_g1_atu_prob_irq; 7308 7309 err = mv88e6xxx_register_switch(chip); 7310 if (err) 7311 goto out_g1_vtu_prob_irq; 7312 7313 return 0; 7314 7315 out_g1_vtu_prob_irq: 7316 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7317 out_g1_atu_prob_irq: 7318 mv88e6xxx_g1_atu_prob_irq_free(chip); 7319 out_g2_irq: 7320 if (chip->info->g2_irqs > 0) 7321 mv88e6xxx_g2_irq_free(chip); 7322 out_g1_irq: 7323 if (chip->irq > 0) 7324 mv88e6xxx_g1_irq_free(chip); 7325 else 7326 mv88e6xxx_irq_poll_free(chip); 7327 out: 7328 if (pdata) 7329 dev_put(pdata->netdev); 7330 7331 return err; 7332 } 7333 7334 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7335 { 7336 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7337 struct mv88e6xxx_chip *chip; 7338 7339 if (!ds) 7340 return; 7341 7342 chip = ds->priv; 7343 7344 if (chip->info->ptp_support) { 7345 mv88e6xxx_hwtstamp_free(chip); 7346 mv88e6xxx_ptp_free(chip); 7347 } 7348 7349 mv88e6xxx_phy_destroy(chip); 7350 mv88e6xxx_unregister_switch(chip); 7351 7352 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7353 mv88e6xxx_g1_atu_prob_irq_free(chip); 7354 7355 if (chip->info->g2_irqs > 0) 7356 mv88e6xxx_g2_irq_free(chip); 7357 7358 if (chip->irq > 0) 7359 mv88e6xxx_g1_irq_free(chip); 7360 else 7361 mv88e6xxx_irq_poll_free(chip); 7362 } 7363 7364 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7365 { 7366 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7367 7368 if (!ds) 7369 return; 7370 7371 dsa_switch_shutdown(ds); 7372 7373 dev_set_drvdata(&mdiodev->dev, NULL); 7374 } 7375 7376 static const struct of_device_id mv88e6xxx_of_match[] = { 7377 { 7378 .compatible = "marvell,mv88e6085", 7379 .data = &mv88e6xxx_table[MV88E6085], 7380 }, 7381 { 7382 .compatible = "marvell,mv88e6190", 7383 .data = &mv88e6xxx_table[MV88E6190], 7384 }, 7385 { 7386 .compatible = "marvell,mv88e6250", 7387 .data = &mv88e6xxx_table[MV88E6250], 7388 }, 7389 { /* sentinel */ }, 7390 }; 7391 7392 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7393 7394 static struct mdio_driver mv88e6xxx_driver = { 7395 .probe = mv88e6xxx_probe, 7396 .remove = mv88e6xxx_remove, 7397 .shutdown = mv88e6xxx_shutdown, 7398 .mdiodrv.driver = { 7399 .name = "mv88e6085", 7400 .of_match_table = mv88e6xxx_of_match, 7401 .pm = &mv88e6xxx_pm_ops, 7402 }, 7403 }; 7404 7405 mdio_module_driver(mv88e6xxx_driver); 7406 7407 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7408 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7409 MODULE_LICENSE("GPL"); 7410