1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 401 int speed, int duplex, int pause, 402 phy_interface_t mode) 403 { 404 struct phylink_link_state state; 405 int err; 406 407 if (!chip->info->ops->port_set_link) 408 return 0; 409 410 if (!chip->info->ops->port_link_state) 411 return 0; 412 413 err = chip->info->ops->port_link_state(chip, port, &state); 414 if (err) 415 return err; 416 417 /* Has anything actually changed? We don't expect the 418 * interface mode to change without one of the other 419 * parameters also changing 420 */ 421 if (state.link == link && 422 state.speed == speed && 423 state.duplex == duplex && 424 (state.interface == mode || 425 state.interface == PHY_INTERFACE_MODE_NA)) 426 return 0; 427 428 /* Port's MAC control must not be changed unless the link is down */ 429 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 430 if (err) 431 return err; 432 433 if (chip->info->ops->port_set_speed) { 434 err = chip->info->ops->port_set_speed(chip, port, speed); 435 if (err && err != -EOPNOTSUPP) 436 goto restore_link; 437 } 438 439 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 440 mode = chip->info->ops->port_max_speed_mode(port); 441 442 if (chip->info->ops->port_set_pause) { 443 err = chip->info->ops->port_set_pause(chip, port, pause); 444 if (err) 445 goto restore_link; 446 } 447 448 if (chip->info->ops->port_set_duplex) { 449 err = chip->info->ops->port_set_duplex(chip, port, duplex); 450 if (err && err != -EOPNOTSUPP) 451 goto restore_link; 452 } 453 454 if (chip->info->ops->port_set_rgmii_delay) { 455 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_cmode) { 461 err = chip->info->ops->port_set_cmode(chip, port, mode); 462 if (err && err != -EOPNOTSUPP) 463 goto restore_link; 464 } 465 466 err = 0; 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 475 { 476 struct mv88e6xxx_chip *chip = ds->priv; 477 478 return port < chip->info->num_internal_phys; 479 } 480 481 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 482 unsigned long *mask, 483 struct phylink_link_state *state) 484 { 485 if (!phy_interface_mode_is_8023z(state->interface)) { 486 /* 10M and 100M are only supported in non-802.3z mode */ 487 phylink_set(mask, 10baseT_Half); 488 phylink_set(mask, 10baseT_Full); 489 phylink_set(mask, 100baseT_Half); 490 phylink_set(mask, 100baseT_Full); 491 } 492 } 493 494 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 495 unsigned long *mask, 496 struct phylink_link_state *state) 497 { 498 /* FIXME: if the port is in 1000Base-X mode, then it only supports 499 * 1000M FD speeds. In this case, CMODE will indicate 5. 500 */ 501 phylink_set(mask, 1000baseT_Full); 502 phylink_set(mask, 1000baseX_Full); 503 504 mv88e6065_phylink_validate(chip, port, mask, state); 505 } 506 507 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 508 unsigned long *mask, 509 struct phylink_link_state *state) 510 { 511 if (port >= 5) 512 phylink_set(mask, 2500baseX_Full); 513 514 /* No ethtool bits for 200Mbps */ 515 phylink_set(mask, 1000baseT_Full); 516 phylink_set(mask, 1000baseX_Full); 517 518 mv88e6065_phylink_validate(chip, port, mask, state); 519 } 520 521 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 522 unsigned long *mask, 523 struct phylink_link_state *state) 524 { 525 /* No ethtool bits for 200Mbps */ 526 phylink_set(mask, 1000baseT_Full); 527 phylink_set(mask, 1000baseX_Full); 528 529 mv88e6065_phylink_validate(chip, port, mask, state); 530 } 531 532 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 533 unsigned long *mask, 534 struct phylink_link_state *state) 535 { 536 if (port >= 9) { 537 phylink_set(mask, 2500baseX_Full); 538 phylink_set(mask, 2500baseT_Full); 539 } 540 541 /* No ethtool bits for 200Mbps */ 542 phylink_set(mask, 1000baseT_Full); 543 phylink_set(mask, 1000baseX_Full); 544 545 mv88e6065_phylink_validate(chip, port, mask, state); 546 } 547 548 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 549 unsigned long *mask, 550 struct phylink_link_state *state) 551 { 552 if (port >= 9) { 553 phylink_set(mask, 10000baseT_Full); 554 phylink_set(mask, 10000baseKR_Full); 555 } 556 557 mv88e6390_phylink_validate(chip, port, mask, state); 558 } 559 560 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 561 unsigned long *supported, 562 struct phylink_link_state *state) 563 { 564 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 565 struct mv88e6xxx_chip *chip = ds->priv; 566 567 /* Allow all the expected bits */ 568 phylink_set(mask, Autoneg); 569 phylink_set(mask, Pause); 570 phylink_set_port_modes(mask); 571 572 if (chip->info->ops->phylink_validate) 573 chip->info->ops->phylink_validate(chip, port, mask, state); 574 575 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 576 bitmap_and(state->advertising, state->advertising, mask, 577 __ETHTOOL_LINK_MODE_MASK_NBITS); 578 579 /* We can only operate at 2500BaseX or 1000BaseX. If requested 580 * to advertise both, only report advertising at 2500BaseX. 581 */ 582 phylink_helper_basex_speed(state); 583 } 584 585 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 586 struct phylink_link_state *state) 587 { 588 struct mv88e6xxx_chip *chip = ds->priv; 589 int err; 590 591 mv88e6xxx_reg_lock(chip); 592 if (chip->info->ops->port_link_state) 593 err = chip->info->ops->port_link_state(chip, port, state); 594 else 595 err = -EOPNOTSUPP; 596 mv88e6xxx_reg_unlock(chip); 597 598 return err; 599 } 600 601 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 602 unsigned int mode, 603 const struct phylink_link_state *state) 604 { 605 struct mv88e6xxx_chip *chip = ds->priv; 606 int speed, duplex, link, pause, err; 607 608 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 609 return; 610 611 if (mode == MLO_AN_FIXED) { 612 link = LINK_FORCED_UP; 613 speed = state->speed; 614 duplex = state->duplex; 615 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 616 link = state->link; 617 speed = state->speed; 618 duplex = state->duplex; 619 } else { 620 speed = SPEED_UNFORCED; 621 duplex = DUPLEX_UNFORCED; 622 link = LINK_UNFORCED; 623 } 624 pause = !!phylink_test(state->advertising, Pause); 625 626 mv88e6xxx_reg_lock(chip); 627 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 628 state->interface); 629 mv88e6xxx_reg_unlock(chip); 630 631 if (err && err != -EOPNOTSUPP) 632 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 633 } 634 635 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 636 unsigned int mode, 637 phy_interface_t interface) 638 { 639 struct mv88e6xxx_chip *chip = ds->priv; 640 const struct mv88e6xxx_ops *ops; 641 int err = 0; 642 643 ops = chip->info->ops; 644 645 /* Internal PHYs propagate their configuration directly to the MAC. 646 * External PHYs depend on whether the PPU is enabled for this port. 647 * FIXME: we should be using the PPU enable state here. What about 648 * an automedia port? 649 */ 650 if (!mv88e6xxx_phy_is_internal(ds, port) && ops->port_set_link) { 651 mv88e6xxx_reg_lock(chip); 652 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 653 mv88e6xxx_reg_unlock(chip); 654 655 if (err) 656 dev_err(chip->dev, 657 "p%d: failed to force MAC link down\n", port); 658 } 659 } 660 661 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 662 unsigned int mode, phy_interface_t interface, 663 struct phy_device *phydev, 664 int speed, int duplex, 665 bool tx_pause, bool rx_pause) 666 { 667 struct mv88e6xxx_chip *chip = ds->priv; 668 const struct mv88e6xxx_ops *ops; 669 int err = 0; 670 671 ops = chip->info->ops; 672 673 /* Internal PHYs propagate their configuration directly to the MAC. 674 * External PHYs depend on whether the PPU is enabled for this port. 675 * FIXME: we should be using the PPU enable state here. What about 676 * an automedia port? 677 */ 678 if (!mv88e6xxx_phy_is_internal(ds, port)) { 679 mv88e6xxx_reg_lock(chip); 680 /* FIXME: for an automedia port, should we force the link 681 * down here - what if the link comes up due to "other" media 682 * while we're bringing the port up, how is the exclusivity 683 * handled in the Marvell hardware? E.g. port 4 on 88E6532 684 * shared between internal PHY and Serdes. 685 */ 686 if (ops->port_set_speed) { 687 err = ops->port_set_speed(chip, port, speed); 688 if (err && err != -EOPNOTSUPP) 689 goto error; 690 } 691 692 if (ops->port_set_duplex) { 693 err = ops->port_set_duplex(chip, port, duplex); 694 if (err && err != -EOPNOTSUPP) 695 goto error; 696 } 697 698 if (ops->port_set_link) 699 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 700 error: 701 mv88e6xxx_reg_unlock(chip); 702 703 if (err && err != -EOPNOTSUPP) 704 dev_err(ds->dev, 705 "p%d: failed to configure MAC link up\n", port); 706 } 707 } 708 709 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 710 { 711 if (!chip->info->ops->stats_snapshot) 712 return -EOPNOTSUPP; 713 714 return chip->info->ops->stats_snapshot(chip, port); 715 } 716 717 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 718 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 719 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 720 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 721 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 722 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 723 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 724 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 725 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 726 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 727 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 728 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 729 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 730 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 731 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 732 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 733 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 734 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 735 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 736 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 737 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 738 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 739 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 740 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 741 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 742 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 743 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 744 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 745 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 746 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 747 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 748 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 749 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 750 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 751 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 752 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 753 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 754 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 755 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 756 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 757 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 758 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 759 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 760 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 761 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 762 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 763 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 764 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 765 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 766 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 767 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 768 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 769 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 770 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 771 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 772 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 773 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 774 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 775 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 776 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 777 }; 778 779 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 780 struct mv88e6xxx_hw_stat *s, 781 int port, u16 bank1_select, 782 u16 histogram) 783 { 784 u32 low; 785 u32 high = 0; 786 u16 reg = 0; 787 int err; 788 u64 value; 789 790 switch (s->type) { 791 case STATS_TYPE_PORT: 792 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 793 if (err) 794 return U64_MAX; 795 796 low = reg; 797 if (s->size == 4) { 798 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 799 if (err) 800 return U64_MAX; 801 low |= ((u32)reg) << 16; 802 } 803 break; 804 case STATS_TYPE_BANK1: 805 reg = bank1_select; 806 /* fall through */ 807 case STATS_TYPE_BANK0: 808 reg |= s->reg | histogram; 809 mv88e6xxx_g1_stats_read(chip, reg, &low); 810 if (s->size == 8) 811 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 812 break; 813 default: 814 return U64_MAX; 815 } 816 value = (((u64)high) << 32) | low; 817 return value; 818 } 819 820 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 821 uint8_t *data, int types) 822 { 823 struct mv88e6xxx_hw_stat *stat; 824 int i, j; 825 826 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 827 stat = &mv88e6xxx_hw_stats[i]; 828 if (stat->type & types) { 829 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 830 ETH_GSTRING_LEN); 831 j++; 832 } 833 } 834 835 return j; 836 } 837 838 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 839 uint8_t *data) 840 { 841 return mv88e6xxx_stats_get_strings(chip, data, 842 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 843 } 844 845 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 846 uint8_t *data) 847 { 848 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 849 } 850 851 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 852 uint8_t *data) 853 { 854 return mv88e6xxx_stats_get_strings(chip, data, 855 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 856 } 857 858 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 859 "atu_member_violation", 860 "atu_miss_violation", 861 "atu_full_violation", 862 "vtu_member_violation", 863 "vtu_miss_violation", 864 }; 865 866 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 867 { 868 unsigned int i; 869 870 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 871 strlcpy(data + i * ETH_GSTRING_LEN, 872 mv88e6xxx_atu_vtu_stats_strings[i], 873 ETH_GSTRING_LEN); 874 } 875 876 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 877 u32 stringset, uint8_t *data) 878 { 879 struct mv88e6xxx_chip *chip = ds->priv; 880 int count = 0; 881 882 if (stringset != ETH_SS_STATS) 883 return; 884 885 mv88e6xxx_reg_lock(chip); 886 887 if (chip->info->ops->stats_get_strings) 888 count = chip->info->ops->stats_get_strings(chip, data); 889 890 if (chip->info->ops->serdes_get_strings) { 891 data += count * ETH_GSTRING_LEN; 892 count = chip->info->ops->serdes_get_strings(chip, port, data); 893 } 894 895 data += count * ETH_GSTRING_LEN; 896 mv88e6xxx_atu_vtu_get_strings(data); 897 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 902 int types) 903 { 904 struct mv88e6xxx_hw_stat *stat; 905 int i, j; 906 907 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 908 stat = &mv88e6xxx_hw_stats[i]; 909 if (stat->type & types) 910 j++; 911 } 912 return j; 913 } 914 915 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 916 { 917 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 918 STATS_TYPE_PORT); 919 } 920 921 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 922 { 923 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 924 } 925 926 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 927 { 928 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 929 STATS_TYPE_BANK1); 930 } 931 932 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 933 { 934 struct mv88e6xxx_chip *chip = ds->priv; 935 int serdes_count = 0; 936 int count = 0; 937 938 if (sset != ETH_SS_STATS) 939 return 0; 940 941 mv88e6xxx_reg_lock(chip); 942 if (chip->info->ops->stats_get_sset_count) 943 count = chip->info->ops->stats_get_sset_count(chip); 944 if (count < 0) 945 goto out; 946 947 if (chip->info->ops->serdes_get_sset_count) 948 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 949 port); 950 if (serdes_count < 0) { 951 count = serdes_count; 952 goto out; 953 } 954 count += serdes_count; 955 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 956 957 out: 958 mv88e6xxx_reg_unlock(chip); 959 960 return count; 961 } 962 963 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 964 uint64_t *data, int types, 965 u16 bank1_select, u16 histogram) 966 { 967 struct mv88e6xxx_hw_stat *stat; 968 int i, j; 969 970 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 971 stat = &mv88e6xxx_hw_stats[i]; 972 if (stat->type & types) { 973 mv88e6xxx_reg_lock(chip); 974 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 975 bank1_select, 976 histogram); 977 mv88e6xxx_reg_unlock(chip); 978 979 j++; 980 } 981 } 982 return j; 983 } 984 985 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 986 uint64_t *data) 987 { 988 return mv88e6xxx_stats_get_stats(chip, port, data, 989 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 990 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 991 } 992 993 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 994 uint64_t *data) 995 { 996 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 997 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 998 } 999 1000 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1001 uint64_t *data) 1002 { 1003 return mv88e6xxx_stats_get_stats(chip, port, data, 1004 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1005 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1006 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1007 } 1008 1009 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1010 uint64_t *data) 1011 { 1012 return mv88e6xxx_stats_get_stats(chip, port, data, 1013 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1014 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1015 0); 1016 } 1017 1018 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1019 uint64_t *data) 1020 { 1021 *data++ = chip->ports[port].atu_member_violation; 1022 *data++ = chip->ports[port].atu_miss_violation; 1023 *data++ = chip->ports[port].atu_full_violation; 1024 *data++ = chip->ports[port].vtu_member_violation; 1025 *data++ = chip->ports[port].vtu_miss_violation; 1026 } 1027 1028 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1029 uint64_t *data) 1030 { 1031 int count = 0; 1032 1033 if (chip->info->ops->stats_get_stats) 1034 count = chip->info->ops->stats_get_stats(chip, port, data); 1035 1036 mv88e6xxx_reg_lock(chip); 1037 if (chip->info->ops->serdes_get_stats) { 1038 data += count; 1039 count = chip->info->ops->serdes_get_stats(chip, port, data); 1040 } 1041 data += count; 1042 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1043 mv88e6xxx_reg_unlock(chip); 1044 } 1045 1046 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1047 uint64_t *data) 1048 { 1049 struct mv88e6xxx_chip *chip = ds->priv; 1050 int ret; 1051 1052 mv88e6xxx_reg_lock(chip); 1053 1054 ret = mv88e6xxx_stats_snapshot(chip, port); 1055 mv88e6xxx_reg_unlock(chip); 1056 1057 if (ret < 0) 1058 return; 1059 1060 mv88e6xxx_get_stats(chip, port, data); 1061 1062 } 1063 1064 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1065 { 1066 struct mv88e6xxx_chip *chip = ds->priv; 1067 int len; 1068 1069 len = 32 * sizeof(u16); 1070 if (chip->info->ops->serdes_get_regs_len) 1071 len += chip->info->ops->serdes_get_regs_len(chip, port); 1072 1073 return len; 1074 } 1075 1076 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1077 struct ethtool_regs *regs, void *_p) 1078 { 1079 struct mv88e6xxx_chip *chip = ds->priv; 1080 int err; 1081 u16 reg; 1082 u16 *p = _p; 1083 int i; 1084 1085 regs->version = chip->info->prod_num; 1086 1087 memset(p, 0xff, 32 * sizeof(u16)); 1088 1089 mv88e6xxx_reg_lock(chip); 1090 1091 for (i = 0; i < 32; i++) { 1092 1093 err = mv88e6xxx_port_read(chip, port, i, ®); 1094 if (!err) 1095 p[i] = reg; 1096 } 1097 1098 if (chip->info->ops->serdes_get_regs) 1099 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1100 1101 mv88e6xxx_reg_unlock(chip); 1102 } 1103 1104 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1105 struct ethtool_eee *e) 1106 { 1107 /* Nothing to do on the port's MAC */ 1108 return 0; 1109 } 1110 1111 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1112 struct ethtool_eee *e) 1113 { 1114 /* Nothing to do on the port's MAC */ 1115 return 0; 1116 } 1117 1118 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1119 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1120 { 1121 struct dsa_switch *ds = chip->ds; 1122 struct dsa_switch_tree *dst = ds->dst; 1123 struct net_device *br; 1124 struct dsa_port *dp; 1125 bool found = false; 1126 u16 pvlan; 1127 1128 list_for_each_entry(dp, &dst->ports, list) { 1129 if (dp->ds->index == dev && dp->index == port) { 1130 found = true; 1131 break; 1132 } 1133 } 1134 1135 /* Prevent frames from unknown switch or port */ 1136 if (!found) 1137 return 0; 1138 1139 /* Frames from DSA links and CPU ports can egress any local port */ 1140 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1141 return mv88e6xxx_port_mask(chip); 1142 1143 br = dp->bridge_dev; 1144 pvlan = 0; 1145 1146 /* Frames from user ports can egress any local DSA links and CPU ports, 1147 * as well as any local member of their bridge group. 1148 */ 1149 list_for_each_entry(dp, &dst->ports, list) 1150 if (dp->ds == ds && 1151 (dp->type == DSA_PORT_TYPE_CPU || 1152 dp->type == DSA_PORT_TYPE_DSA || 1153 (br && dp->bridge_dev == br))) 1154 pvlan |= BIT(dp->index); 1155 1156 return pvlan; 1157 } 1158 1159 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1160 { 1161 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1162 1163 /* prevent frames from going back out of the port they came in on */ 1164 output_ports &= ~BIT(port); 1165 1166 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1167 } 1168 1169 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1170 u8 state) 1171 { 1172 struct mv88e6xxx_chip *chip = ds->priv; 1173 int err; 1174 1175 mv88e6xxx_reg_lock(chip); 1176 err = mv88e6xxx_port_set_state(chip, port, state); 1177 mv88e6xxx_reg_unlock(chip); 1178 1179 if (err) 1180 dev_err(ds->dev, "p%d: failed to update state\n", port); 1181 } 1182 1183 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1184 { 1185 int err; 1186 1187 if (chip->info->ops->ieee_pri_map) { 1188 err = chip->info->ops->ieee_pri_map(chip); 1189 if (err) 1190 return err; 1191 } 1192 1193 if (chip->info->ops->ip_pri_map) { 1194 err = chip->info->ops->ip_pri_map(chip); 1195 if (err) 1196 return err; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1203 { 1204 struct dsa_switch *ds = chip->ds; 1205 int target, port; 1206 int err; 1207 1208 if (!chip->info->global2_addr) 1209 return 0; 1210 1211 /* Initialize the routing port to the 32 possible target devices */ 1212 for (target = 0; target < 32; target++) { 1213 port = dsa_routing_port(ds, target); 1214 if (port == ds->num_ports) 1215 port = 0x1f; 1216 1217 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1218 if (err) 1219 return err; 1220 } 1221 1222 if (chip->info->ops->set_cascade_port) { 1223 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1224 err = chip->info->ops->set_cascade_port(chip, port); 1225 if (err) 1226 return err; 1227 } 1228 1229 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1230 if (err) 1231 return err; 1232 1233 return 0; 1234 } 1235 1236 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1237 { 1238 /* Clear all trunk masks and mapping */ 1239 if (chip->info->global2_addr) 1240 return mv88e6xxx_g2_trunk_clear(chip); 1241 1242 return 0; 1243 } 1244 1245 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1246 { 1247 if (chip->info->ops->rmu_disable) 1248 return chip->info->ops->rmu_disable(chip); 1249 1250 return 0; 1251 } 1252 1253 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1254 { 1255 if (chip->info->ops->pot_clear) 1256 return chip->info->ops->pot_clear(chip); 1257 1258 return 0; 1259 } 1260 1261 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1262 { 1263 if (chip->info->ops->mgmt_rsvd2cpu) 1264 return chip->info->ops->mgmt_rsvd2cpu(chip); 1265 1266 return 0; 1267 } 1268 1269 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1270 { 1271 int err; 1272 1273 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1274 if (err) 1275 return err; 1276 1277 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1278 if (err) 1279 return err; 1280 1281 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1282 } 1283 1284 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1285 { 1286 int port; 1287 int err; 1288 1289 if (!chip->info->ops->irl_init_all) 1290 return 0; 1291 1292 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1293 /* Disable ingress rate limiting by resetting all per port 1294 * ingress rate limit resources to their initial state. 1295 */ 1296 err = chip->info->ops->irl_init_all(chip, port); 1297 if (err) 1298 return err; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1305 { 1306 if (chip->info->ops->set_switch_mac) { 1307 u8 addr[ETH_ALEN]; 1308 1309 eth_random_addr(addr); 1310 1311 return chip->info->ops->set_switch_mac(chip, addr); 1312 } 1313 1314 return 0; 1315 } 1316 1317 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1318 { 1319 u16 pvlan = 0; 1320 1321 if (!mv88e6xxx_has_pvt(chip)) 1322 return 0; 1323 1324 /* Skip the local source device, which uses in-chip port VLAN */ 1325 if (dev != chip->ds->index) 1326 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1327 1328 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1329 } 1330 1331 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1332 { 1333 int dev, port; 1334 int err; 1335 1336 if (!mv88e6xxx_has_pvt(chip)) 1337 return 0; 1338 1339 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1340 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1341 */ 1342 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1343 if (err) 1344 return err; 1345 1346 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1347 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1348 err = mv88e6xxx_pvt_map(chip, dev, port); 1349 if (err) 1350 return err; 1351 } 1352 } 1353 1354 return 0; 1355 } 1356 1357 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1358 { 1359 struct mv88e6xxx_chip *chip = ds->priv; 1360 int err; 1361 1362 mv88e6xxx_reg_lock(chip); 1363 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1364 mv88e6xxx_reg_unlock(chip); 1365 1366 if (err) 1367 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1368 } 1369 1370 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1371 { 1372 if (!chip->info->max_vid) 1373 return 0; 1374 1375 return mv88e6xxx_g1_vtu_flush(chip); 1376 } 1377 1378 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1379 struct mv88e6xxx_vtu_entry *entry) 1380 { 1381 if (!chip->info->ops->vtu_getnext) 1382 return -EOPNOTSUPP; 1383 1384 return chip->info->ops->vtu_getnext(chip, entry); 1385 } 1386 1387 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1388 struct mv88e6xxx_vtu_entry *entry) 1389 { 1390 if (!chip->info->ops->vtu_loadpurge) 1391 return -EOPNOTSUPP; 1392 1393 return chip->info->ops->vtu_loadpurge(chip, entry); 1394 } 1395 1396 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1397 { 1398 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1399 struct mv88e6xxx_vtu_entry vlan; 1400 int i, err; 1401 1402 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1403 1404 /* Set every FID bit used by the (un)bridged ports */ 1405 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1406 err = mv88e6xxx_port_get_fid(chip, i, fid); 1407 if (err) 1408 return err; 1409 1410 set_bit(*fid, fid_bitmap); 1411 } 1412 1413 /* Set every FID bit used by the VLAN entries */ 1414 vlan.vid = chip->info->max_vid; 1415 vlan.valid = false; 1416 1417 do { 1418 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1419 if (err) 1420 return err; 1421 1422 if (!vlan.valid) 1423 break; 1424 1425 set_bit(vlan.fid, fid_bitmap); 1426 } while (vlan.vid < chip->info->max_vid); 1427 1428 /* The reset value 0x000 is used to indicate that multiple address 1429 * databases are not needed. Return the next positive available. 1430 */ 1431 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1432 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1433 return -ENOSPC; 1434 1435 /* Clear the database */ 1436 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1437 } 1438 1439 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1440 { 1441 if (chip->info->ops->atu_get_hash) 1442 return chip->info->ops->atu_get_hash(chip, hash); 1443 1444 return -EOPNOTSUPP; 1445 } 1446 1447 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1448 { 1449 if (chip->info->ops->atu_set_hash) 1450 return chip->info->ops->atu_set_hash(chip, hash); 1451 1452 return -EOPNOTSUPP; 1453 } 1454 1455 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1456 u16 vid_begin, u16 vid_end) 1457 { 1458 struct mv88e6xxx_chip *chip = ds->priv; 1459 struct mv88e6xxx_vtu_entry vlan; 1460 int i, err; 1461 1462 /* DSA and CPU ports have to be members of multiple vlans */ 1463 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1464 return 0; 1465 1466 if (!vid_begin) 1467 return -EOPNOTSUPP; 1468 1469 vlan.vid = vid_begin - 1; 1470 vlan.valid = false; 1471 1472 do { 1473 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1474 if (err) 1475 return err; 1476 1477 if (!vlan.valid) 1478 break; 1479 1480 if (vlan.vid > vid_end) 1481 break; 1482 1483 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1484 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1485 continue; 1486 1487 if (!dsa_to_port(ds, i)->slave) 1488 continue; 1489 1490 if (vlan.member[i] == 1491 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1492 continue; 1493 1494 if (dsa_to_port(ds, i)->bridge_dev == 1495 dsa_to_port(ds, port)->bridge_dev) 1496 break; /* same bridge, check next VLAN */ 1497 1498 if (!dsa_to_port(ds, i)->bridge_dev) 1499 continue; 1500 1501 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1502 port, vlan.vid, i, 1503 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1504 return -EOPNOTSUPP; 1505 } 1506 } while (vlan.vid < vid_end); 1507 1508 return 0; 1509 } 1510 1511 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1512 bool vlan_filtering) 1513 { 1514 struct mv88e6xxx_chip *chip = ds->priv; 1515 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1516 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1517 int err; 1518 1519 if (!chip->info->max_vid) 1520 return -EOPNOTSUPP; 1521 1522 mv88e6xxx_reg_lock(chip); 1523 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1524 mv88e6xxx_reg_unlock(chip); 1525 1526 return err; 1527 } 1528 1529 static int 1530 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1531 const struct switchdev_obj_port_vlan *vlan) 1532 { 1533 struct mv88e6xxx_chip *chip = ds->priv; 1534 int err; 1535 1536 if (!chip->info->max_vid) 1537 return -EOPNOTSUPP; 1538 1539 /* If the requested port doesn't belong to the same bridge as the VLAN 1540 * members, do not support it (yet) and fallback to software VLAN. 1541 */ 1542 mv88e6xxx_reg_lock(chip); 1543 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1544 vlan->vid_end); 1545 mv88e6xxx_reg_unlock(chip); 1546 1547 /* We don't need any dynamic resource from the kernel (yet), 1548 * so skip the prepare phase. 1549 */ 1550 return err; 1551 } 1552 1553 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1554 const unsigned char *addr, u16 vid, 1555 u8 state) 1556 { 1557 struct mv88e6xxx_atu_entry entry; 1558 struct mv88e6xxx_vtu_entry vlan; 1559 u16 fid; 1560 int err; 1561 1562 /* Null VLAN ID corresponds to the port private database */ 1563 if (vid == 0) { 1564 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1565 if (err) 1566 return err; 1567 } else { 1568 vlan.vid = vid - 1; 1569 vlan.valid = false; 1570 1571 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1572 if (err) 1573 return err; 1574 1575 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1576 if (vlan.vid != vid || !vlan.valid) 1577 return -EOPNOTSUPP; 1578 1579 fid = vlan.fid; 1580 } 1581 1582 entry.state = 0; 1583 ether_addr_copy(entry.mac, addr); 1584 eth_addr_dec(entry.mac); 1585 1586 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1587 if (err) 1588 return err; 1589 1590 /* Initialize a fresh ATU entry if it isn't found */ 1591 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1592 memset(&entry, 0, sizeof(entry)); 1593 ether_addr_copy(entry.mac, addr); 1594 } 1595 1596 /* Purge the ATU entry only if no port is using it anymore */ 1597 if (!state) { 1598 entry.portvec &= ~BIT(port); 1599 if (!entry.portvec) 1600 entry.state = 0; 1601 } else { 1602 entry.portvec |= BIT(port); 1603 entry.state = state; 1604 } 1605 1606 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1607 } 1608 1609 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1610 const struct mv88e6xxx_policy *policy) 1611 { 1612 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1613 enum mv88e6xxx_policy_action action = policy->action; 1614 const u8 *addr = policy->addr; 1615 u16 vid = policy->vid; 1616 u8 state; 1617 int err; 1618 int id; 1619 1620 if (!chip->info->ops->port_set_policy) 1621 return -EOPNOTSUPP; 1622 1623 switch (mapping) { 1624 case MV88E6XXX_POLICY_MAPPING_DA: 1625 case MV88E6XXX_POLICY_MAPPING_SA: 1626 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1627 state = 0; /* Dissociate the port and address */ 1628 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1629 is_multicast_ether_addr(addr)) 1630 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1631 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1632 is_unicast_ether_addr(addr)) 1633 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1634 else 1635 return -EOPNOTSUPP; 1636 1637 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1638 state); 1639 if (err) 1640 return err; 1641 break; 1642 default: 1643 return -EOPNOTSUPP; 1644 } 1645 1646 /* Skip the port's policy clearing if the mapping is still in use */ 1647 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1648 idr_for_each_entry(&chip->policies, policy, id) 1649 if (policy->port == port && 1650 policy->mapping == mapping && 1651 policy->action != action) 1652 return 0; 1653 1654 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1655 } 1656 1657 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1658 struct ethtool_rx_flow_spec *fs) 1659 { 1660 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1661 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1662 enum mv88e6xxx_policy_mapping mapping; 1663 enum mv88e6xxx_policy_action action; 1664 struct mv88e6xxx_policy *policy; 1665 u16 vid = 0; 1666 u8 *addr; 1667 int err; 1668 int id; 1669 1670 if (fs->location != RX_CLS_LOC_ANY) 1671 return -EINVAL; 1672 1673 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1674 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1675 else 1676 return -EOPNOTSUPP; 1677 1678 switch (fs->flow_type & ~FLOW_EXT) { 1679 case ETHER_FLOW: 1680 if (!is_zero_ether_addr(mac_mask->h_dest) && 1681 is_zero_ether_addr(mac_mask->h_source)) { 1682 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1683 addr = mac_entry->h_dest; 1684 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1685 !is_zero_ether_addr(mac_mask->h_source)) { 1686 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1687 addr = mac_entry->h_source; 1688 } else { 1689 /* Cannot support DA and SA mapping in the same rule */ 1690 return -EOPNOTSUPP; 1691 } 1692 break; 1693 default: 1694 return -EOPNOTSUPP; 1695 } 1696 1697 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1698 if (fs->m_ext.vlan_tci != 0xffff) 1699 return -EOPNOTSUPP; 1700 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1701 } 1702 1703 idr_for_each_entry(&chip->policies, policy, id) { 1704 if (policy->port == port && policy->mapping == mapping && 1705 policy->action == action && policy->vid == vid && 1706 ether_addr_equal(policy->addr, addr)) 1707 return -EEXIST; 1708 } 1709 1710 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1711 if (!policy) 1712 return -ENOMEM; 1713 1714 fs->location = 0; 1715 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1716 GFP_KERNEL); 1717 if (err) { 1718 devm_kfree(chip->dev, policy); 1719 return err; 1720 } 1721 1722 memcpy(&policy->fs, fs, sizeof(*fs)); 1723 ether_addr_copy(policy->addr, addr); 1724 policy->mapping = mapping; 1725 policy->action = action; 1726 policy->port = port; 1727 policy->vid = vid; 1728 1729 err = mv88e6xxx_policy_apply(chip, port, policy); 1730 if (err) { 1731 idr_remove(&chip->policies, fs->location); 1732 devm_kfree(chip->dev, policy); 1733 return err; 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1740 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1741 { 1742 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1743 struct mv88e6xxx_chip *chip = ds->priv; 1744 struct mv88e6xxx_policy *policy; 1745 int err; 1746 int id; 1747 1748 mv88e6xxx_reg_lock(chip); 1749 1750 switch (rxnfc->cmd) { 1751 case ETHTOOL_GRXCLSRLCNT: 1752 rxnfc->data = 0; 1753 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1754 rxnfc->rule_cnt = 0; 1755 idr_for_each_entry(&chip->policies, policy, id) 1756 if (policy->port == port) 1757 rxnfc->rule_cnt++; 1758 err = 0; 1759 break; 1760 case ETHTOOL_GRXCLSRULE: 1761 err = -ENOENT; 1762 policy = idr_find(&chip->policies, fs->location); 1763 if (policy) { 1764 memcpy(fs, &policy->fs, sizeof(*fs)); 1765 err = 0; 1766 } 1767 break; 1768 case ETHTOOL_GRXCLSRLALL: 1769 rxnfc->data = 0; 1770 rxnfc->rule_cnt = 0; 1771 idr_for_each_entry(&chip->policies, policy, id) 1772 if (policy->port == port) 1773 rule_locs[rxnfc->rule_cnt++] = id; 1774 err = 0; 1775 break; 1776 default: 1777 err = -EOPNOTSUPP; 1778 break; 1779 } 1780 1781 mv88e6xxx_reg_unlock(chip); 1782 1783 return err; 1784 } 1785 1786 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1787 struct ethtool_rxnfc *rxnfc) 1788 { 1789 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1790 struct mv88e6xxx_chip *chip = ds->priv; 1791 struct mv88e6xxx_policy *policy; 1792 int err; 1793 1794 mv88e6xxx_reg_lock(chip); 1795 1796 switch (rxnfc->cmd) { 1797 case ETHTOOL_SRXCLSRLINS: 1798 err = mv88e6xxx_policy_insert(chip, port, fs); 1799 break; 1800 case ETHTOOL_SRXCLSRLDEL: 1801 err = -ENOENT; 1802 policy = idr_remove(&chip->policies, fs->location); 1803 if (policy) { 1804 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1805 err = mv88e6xxx_policy_apply(chip, port, policy); 1806 devm_kfree(chip->dev, policy); 1807 } 1808 break; 1809 default: 1810 err = -EOPNOTSUPP; 1811 break; 1812 } 1813 1814 mv88e6xxx_reg_unlock(chip); 1815 1816 return err; 1817 } 1818 1819 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1820 u16 vid) 1821 { 1822 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1823 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1824 1825 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1826 } 1827 1828 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1829 { 1830 int port; 1831 int err; 1832 1833 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1834 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1835 if (err) 1836 return err; 1837 } 1838 1839 return 0; 1840 } 1841 1842 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1843 u16 vid, u8 member, bool warn) 1844 { 1845 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1846 struct mv88e6xxx_vtu_entry vlan; 1847 int i, err; 1848 1849 if (!vid) 1850 return -EOPNOTSUPP; 1851 1852 vlan.vid = vid - 1; 1853 vlan.valid = false; 1854 1855 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1856 if (err) 1857 return err; 1858 1859 if (vlan.vid != vid || !vlan.valid) { 1860 memset(&vlan, 0, sizeof(vlan)); 1861 1862 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1863 if (err) 1864 return err; 1865 1866 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1867 if (i == port) 1868 vlan.member[i] = member; 1869 else 1870 vlan.member[i] = non_member; 1871 1872 vlan.vid = vid; 1873 vlan.valid = true; 1874 1875 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1876 if (err) 1877 return err; 1878 1879 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1880 if (err) 1881 return err; 1882 } else if (vlan.member[port] != member) { 1883 vlan.member[port] = member; 1884 1885 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1886 if (err) 1887 return err; 1888 } else if (warn) { 1889 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1890 port, vid); 1891 } 1892 1893 return 0; 1894 } 1895 1896 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1897 const struct switchdev_obj_port_vlan *vlan) 1898 { 1899 struct mv88e6xxx_chip *chip = ds->priv; 1900 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1901 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1902 bool warn; 1903 u8 member; 1904 u16 vid; 1905 1906 if (!chip->info->max_vid) 1907 return; 1908 1909 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1910 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1911 else if (untagged) 1912 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1913 else 1914 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1915 1916 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1917 * and then the CPU port. Do not warn for duplicates for the CPU port. 1918 */ 1919 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1920 1921 mv88e6xxx_reg_lock(chip); 1922 1923 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1924 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1925 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1926 vid, untagged ? 'u' : 't'); 1927 1928 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1929 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1930 vlan->vid_end); 1931 1932 mv88e6xxx_reg_unlock(chip); 1933 } 1934 1935 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1936 int port, u16 vid) 1937 { 1938 struct mv88e6xxx_vtu_entry vlan; 1939 int i, err; 1940 1941 if (!vid) 1942 return -EOPNOTSUPP; 1943 1944 vlan.vid = vid - 1; 1945 vlan.valid = false; 1946 1947 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1948 if (err) 1949 return err; 1950 1951 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1952 * tell switchdev that this VLAN is likely handled in software. 1953 */ 1954 if (vlan.vid != vid || !vlan.valid || 1955 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1956 return -EOPNOTSUPP; 1957 1958 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1959 1960 /* keep the VLAN unless all ports are excluded */ 1961 vlan.valid = false; 1962 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1963 if (vlan.member[i] != 1964 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1965 vlan.valid = true; 1966 break; 1967 } 1968 } 1969 1970 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1971 if (err) 1972 return err; 1973 1974 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1975 } 1976 1977 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1978 const struct switchdev_obj_port_vlan *vlan) 1979 { 1980 struct mv88e6xxx_chip *chip = ds->priv; 1981 u16 pvid, vid; 1982 int err = 0; 1983 1984 if (!chip->info->max_vid) 1985 return -EOPNOTSUPP; 1986 1987 mv88e6xxx_reg_lock(chip); 1988 1989 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1990 if (err) 1991 goto unlock; 1992 1993 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1994 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1995 if (err) 1996 goto unlock; 1997 1998 if (vid == pvid) { 1999 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2000 if (err) 2001 goto unlock; 2002 } 2003 } 2004 2005 unlock: 2006 mv88e6xxx_reg_unlock(chip); 2007 2008 return err; 2009 } 2010 2011 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2012 const unsigned char *addr, u16 vid) 2013 { 2014 struct mv88e6xxx_chip *chip = ds->priv; 2015 int err; 2016 2017 mv88e6xxx_reg_lock(chip); 2018 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2019 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2020 mv88e6xxx_reg_unlock(chip); 2021 2022 return err; 2023 } 2024 2025 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2026 const unsigned char *addr, u16 vid) 2027 { 2028 struct mv88e6xxx_chip *chip = ds->priv; 2029 int err; 2030 2031 mv88e6xxx_reg_lock(chip); 2032 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2033 mv88e6xxx_reg_unlock(chip); 2034 2035 return err; 2036 } 2037 2038 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2039 u16 fid, u16 vid, int port, 2040 dsa_fdb_dump_cb_t *cb, void *data) 2041 { 2042 struct mv88e6xxx_atu_entry addr; 2043 bool is_static; 2044 int err; 2045 2046 addr.state = 0; 2047 eth_broadcast_addr(addr.mac); 2048 2049 do { 2050 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2051 if (err) 2052 return err; 2053 2054 if (!addr.state) 2055 break; 2056 2057 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2058 continue; 2059 2060 if (!is_unicast_ether_addr(addr.mac)) 2061 continue; 2062 2063 is_static = (addr.state == 2064 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2065 err = cb(addr.mac, vid, is_static, data); 2066 if (err) 2067 return err; 2068 } while (!is_broadcast_ether_addr(addr.mac)); 2069 2070 return err; 2071 } 2072 2073 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2074 dsa_fdb_dump_cb_t *cb, void *data) 2075 { 2076 struct mv88e6xxx_vtu_entry vlan; 2077 u16 fid; 2078 int err; 2079 2080 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2081 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2082 if (err) 2083 return err; 2084 2085 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2086 if (err) 2087 return err; 2088 2089 /* Dump VLANs' Filtering Information Databases */ 2090 vlan.vid = chip->info->max_vid; 2091 vlan.valid = false; 2092 2093 do { 2094 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2095 if (err) 2096 return err; 2097 2098 if (!vlan.valid) 2099 break; 2100 2101 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2102 cb, data); 2103 if (err) 2104 return err; 2105 } while (vlan.vid < chip->info->max_vid); 2106 2107 return err; 2108 } 2109 2110 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2111 dsa_fdb_dump_cb_t *cb, void *data) 2112 { 2113 struct mv88e6xxx_chip *chip = ds->priv; 2114 int err; 2115 2116 mv88e6xxx_reg_lock(chip); 2117 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2118 mv88e6xxx_reg_unlock(chip); 2119 2120 return err; 2121 } 2122 2123 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2124 struct net_device *br) 2125 { 2126 struct dsa_switch *ds = chip->ds; 2127 struct dsa_switch_tree *dst = ds->dst; 2128 struct dsa_port *dp; 2129 int err; 2130 2131 list_for_each_entry(dp, &dst->ports, list) { 2132 if (dp->bridge_dev == br) { 2133 if (dp->ds == ds) { 2134 /* This is a local bridge group member, 2135 * remap its Port VLAN Map. 2136 */ 2137 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2138 if (err) 2139 return err; 2140 } else { 2141 /* This is an external bridge group member, 2142 * remap its cross-chip Port VLAN Table entry. 2143 */ 2144 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2145 dp->index); 2146 if (err) 2147 return err; 2148 } 2149 } 2150 } 2151 2152 return 0; 2153 } 2154 2155 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2156 struct net_device *br) 2157 { 2158 struct mv88e6xxx_chip *chip = ds->priv; 2159 int err; 2160 2161 mv88e6xxx_reg_lock(chip); 2162 err = mv88e6xxx_bridge_map(chip, br); 2163 mv88e6xxx_reg_unlock(chip); 2164 2165 return err; 2166 } 2167 2168 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2169 struct net_device *br) 2170 { 2171 struct mv88e6xxx_chip *chip = ds->priv; 2172 2173 mv88e6xxx_reg_lock(chip); 2174 if (mv88e6xxx_bridge_map(chip, br) || 2175 mv88e6xxx_port_vlan_map(chip, port)) 2176 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2177 mv88e6xxx_reg_unlock(chip); 2178 } 2179 2180 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2181 int port, struct net_device *br) 2182 { 2183 struct mv88e6xxx_chip *chip = ds->priv; 2184 int err; 2185 2186 mv88e6xxx_reg_lock(chip); 2187 err = mv88e6xxx_pvt_map(chip, dev, port); 2188 mv88e6xxx_reg_unlock(chip); 2189 2190 return err; 2191 } 2192 2193 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2194 int port, struct net_device *br) 2195 { 2196 struct mv88e6xxx_chip *chip = ds->priv; 2197 2198 mv88e6xxx_reg_lock(chip); 2199 if (mv88e6xxx_pvt_map(chip, dev, port)) 2200 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2201 mv88e6xxx_reg_unlock(chip); 2202 } 2203 2204 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2205 { 2206 if (chip->info->ops->reset) 2207 return chip->info->ops->reset(chip); 2208 2209 return 0; 2210 } 2211 2212 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2213 { 2214 struct gpio_desc *gpiod = chip->reset; 2215 2216 /* If there is a GPIO connected to the reset pin, toggle it */ 2217 if (gpiod) { 2218 gpiod_set_value_cansleep(gpiod, 1); 2219 usleep_range(10000, 20000); 2220 gpiod_set_value_cansleep(gpiod, 0); 2221 usleep_range(10000, 20000); 2222 } 2223 } 2224 2225 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2226 { 2227 int i, err; 2228 2229 /* Set all ports to the Disabled state */ 2230 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2231 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2232 if (err) 2233 return err; 2234 } 2235 2236 /* Wait for transmit queues to drain, 2237 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2238 */ 2239 usleep_range(2000, 4000); 2240 2241 return 0; 2242 } 2243 2244 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2245 { 2246 int err; 2247 2248 err = mv88e6xxx_disable_ports(chip); 2249 if (err) 2250 return err; 2251 2252 mv88e6xxx_hardware_reset(chip); 2253 2254 return mv88e6xxx_software_reset(chip); 2255 } 2256 2257 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2258 enum mv88e6xxx_frame_mode frame, 2259 enum mv88e6xxx_egress_mode egress, u16 etype) 2260 { 2261 int err; 2262 2263 if (!chip->info->ops->port_set_frame_mode) 2264 return -EOPNOTSUPP; 2265 2266 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2267 if (err) 2268 return err; 2269 2270 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2271 if (err) 2272 return err; 2273 2274 if (chip->info->ops->port_set_ether_type) 2275 return chip->info->ops->port_set_ether_type(chip, port, etype); 2276 2277 return 0; 2278 } 2279 2280 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2281 { 2282 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2283 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2284 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2285 } 2286 2287 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2288 { 2289 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2290 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2291 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2292 } 2293 2294 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2295 { 2296 return mv88e6xxx_set_port_mode(chip, port, 2297 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2298 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2299 ETH_P_EDSA); 2300 } 2301 2302 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2303 { 2304 if (dsa_is_dsa_port(chip->ds, port)) 2305 return mv88e6xxx_set_port_mode_dsa(chip, port); 2306 2307 if (dsa_is_user_port(chip->ds, port)) 2308 return mv88e6xxx_set_port_mode_normal(chip, port); 2309 2310 /* Setup CPU port mode depending on its supported tag format */ 2311 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2312 return mv88e6xxx_set_port_mode_dsa(chip, port); 2313 2314 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2315 return mv88e6xxx_set_port_mode_edsa(chip, port); 2316 2317 return -EINVAL; 2318 } 2319 2320 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2321 { 2322 bool message = dsa_is_dsa_port(chip->ds, port); 2323 2324 return mv88e6xxx_port_set_message_port(chip, port, message); 2325 } 2326 2327 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2328 { 2329 struct dsa_switch *ds = chip->ds; 2330 bool flood; 2331 2332 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2333 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2334 if (chip->info->ops->port_set_egress_floods) 2335 return chip->info->ops->port_set_egress_floods(chip, port, 2336 flood, flood); 2337 2338 return 0; 2339 } 2340 2341 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2342 { 2343 struct mv88e6xxx_port *mvp = dev_id; 2344 struct mv88e6xxx_chip *chip = mvp->chip; 2345 irqreturn_t ret = IRQ_NONE; 2346 int port = mvp->port; 2347 u8 lane; 2348 2349 mv88e6xxx_reg_lock(chip); 2350 lane = mv88e6xxx_serdes_get_lane(chip, port); 2351 if (lane) 2352 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2353 mv88e6xxx_reg_unlock(chip); 2354 2355 return ret; 2356 } 2357 2358 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2359 u8 lane) 2360 { 2361 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2362 unsigned int irq; 2363 int err; 2364 2365 /* Nothing to request if this SERDES port has no IRQ */ 2366 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2367 if (!irq) 2368 return 0; 2369 2370 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2371 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2372 2373 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2374 mv88e6xxx_reg_unlock(chip); 2375 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2376 IRQF_ONESHOT, dev_id->serdes_irq_name, 2377 dev_id); 2378 mv88e6xxx_reg_lock(chip); 2379 if (err) 2380 return err; 2381 2382 dev_id->serdes_irq = irq; 2383 2384 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2385 } 2386 2387 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2388 u8 lane) 2389 { 2390 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2391 unsigned int irq = dev_id->serdes_irq; 2392 int err; 2393 2394 /* Nothing to free if no IRQ has been requested */ 2395 if (!irq) 2396 return 0; 2397 2398 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2399 2400 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2401 mv88e6xxx_reg_unlock(chip); 2402 free_irq(irq, dev_id); 2403 mv88e6xxx_reg_lock(chip); 2404 2405 dev_id->serdes_irq = 0; 2406 2407 return err; 2408 } 2409 2410 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2411 bool on) 2412 { 2413 u8 lane; 2414 int err; 2415 2416 lane = mv88e6xxx_serdes_get_lane(chip, port); 2417 if (!lane) 2418 return 0; 2419 2420 if (on) { 2421 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2422 if (err) 2423 return err; 2424 2425 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2426 } else { 2427 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2428 if (err) 2429 return err; 2430 2431 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2432 } 2433 2434 return err; 2435 } 2436 2437 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2438 { 2439 struct dsa_switch *ds = chip->ds; 2440 int upstream_port; 2441 int err; 2442 2443 upstream_port = dsa_upstream_port(ds, port); 2444 if (chip->info->ops->port_set_upstream_port) { 2445 err = chip->info->ops->port_set_upstream_port(chip, port, 2446 upstream_port); 2447 if (err) 2448 return err; 2449 } 2450 2451 if (port == upstream_port) { 2452 if (chip->info->ops->set_cpu_port) { 2453 err = chip->info->ops->set_cpu_port(chip, 2454 upstream_port); 2455 if (err) 2456 return err; 2457 } 2458 2459 if (chip->info->ops->set_egress_port) { 2460 err = chip->info->ops->set_egress_port(chip, 2461 MV88E6XXX_EGRESS_DIR_INGRESS, 2462 upstream_port); 2463 if (err) 2464 return err; 2465 2466 err = chip->info->ops->set_egress_port(chip, 2467 MV88E6XXX_EGRESS_DIR_EGRESS, 2468 upstream_port); 2469 if (err) 2470 return err; 2471 } 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2478 { 2479 struct dsa_switch *ds = chip->ds; 2480 int err; 2481 u16 reg; 2482 2483 chip->ports[port].chip = chip; 2484 chip->ports[port].port = port; 2485 2486 /* MAC Forcing register: don't force link, speed, duplex or flow control 2487 * state to any particular values on physical ports, but force the CPU 2488 * port and all DSA ports to their maximum bandwidth and full duplex. 2489 */ 2490 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2491 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2492 SPEED_MAX, DUPLEX_FULL, 2493 PAUSE_OFF, 2494 PHY_INTERFACE_MODE_NA); 2495 else 2496 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2497 SPEED_UNFORCED, DUPLEX_UNFORCED, 2498 PAUSE_ON, 2499 PHY_INTERFACE_MODE_NA); 2500 if (err) 2501 return err; 2502 2503 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2504 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2505 * tunneling, determine priority by looking at 802.1p and IP 2506 * priority fields (IP prio has precedence), and set STP state 2507 * to Forwarding. 2508 * 2509 * If this is the CPU link, use DSA or EDSA tagging depending 2510 * on which tagging mode was configured. 2511 * 2512 * If this is a link to another switch, use DSA tagging mode. 2513 * 2514 * If this is the upstream port for this switch, enable 2515 * forwarding of unknown unicasts and multicasts. 2516 */ 2517 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2518 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2519 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2520 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2521 if (err) 2522 return err; 2523 2524 err = mv88e6xxx_setup_port_mode(chip, port); 2525 if (err) 2526 return err; 2527 2528 err = mv88e6xxx_setup_egress_floods(chip, port); 2529 if (err) 2530 return err; 2531 2532 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2533 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2534 * untagged frames on this port, do a destination address lookup on all 2535 * received packets as usual, disable ARP mirroring and don't send a 2536 * copy of all transmitted/received frames on this port to the CPU. 2537 */ 2538 err = mv88e6xxx_port_set_map_da(chip, port); 2539 if (err) 2540 return err; 2541 2542 err = mv88e6xxx_setup_upstream_port(chip, port); 2543 if (err) 2544 return err; 2545 2546 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2547 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2548 if (err) 2549 return err; 2550 2551 if (chip->info->ops->port_set_jumbo_size) { 2552 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2553 if (err) 2554 return err; 2555 } 2556 2557 /* Port Association Vector: when learning source addresses 2558 * of packets, add the address to the address database using 2559 * a port bitmap that has only the bit for this port set and 2560 * the other bits clear. 2561 */ 2562 reg = 1 << port; 2563 /* Disable learning for CPU port */ 2564 if (dsa_is_cpu_port(ds, port)) 2565 reg = 0; 2566 2567 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2568 reg); 2569 if (err) 2570 return err; 2571 2572 /* Egress rate control 2: disable egress rate control. */ 2573 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2574 0x0000); 2575 if (err) 2576 return err; 2577 2578 if (chip->info->ops->port_pause_limit) { 2579 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2580 if (err) 2581 return err; 2582 } 2583 2584 if (chip->info->ops->port_disable_learn_limit) { 2585 err = chip->info->ops->port_disable_learn_limit(chip, port); 2586 if (err) 2587 return err; 2588 } 2589 2590 if (chip->info->ops->port_disable_pri_override) { 2591 err = chip->info->ops->port_disable_pri_override(chip, port); 2592 if (err) 2593 return err; 2594 } 2595 2596 if (chip->info->ops->port_tag_remap) { 2597 err = chip->info->ops->port_tag_remap(chip, port); 2598 if (err) 2599 return err; 2600 } 2601 2602 if (chip->info->ops->port_egress_rate_limiting) { 2603 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2604 if (err) 2605 return err; 2606 } 2607 2608 if (chip->info->ops->port_setup_message_port) { 2609 err = chip->info->ops->port_setup_message_port(chip, port); 2610 if (err) 2611 return err; 2612 } 2613 2614 /* Port based VLAN map: give each port the same default address 2615 * database, and allow bidirectional communication between the 2616 * CPU and DSA port(s), and the other ports. 2617 */ 2618 err = mv88e6xxx_port_set_fid(chip, port, 0); 2619 if (err) 2620 return err; 2621 2622 err = mv88e6xxx_port_vlan_map(chip, port); 2623 if (err) 2624 return err; 2625 2626 /* Default VLAN ID and priority: don't set a default VLAN 2627 * ID, and set the default packet priority to zero. 2628 */ 2629 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2630 } 2631 2632 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2633 struct phy_device *phydev) 2634 { 2635 struct mv88e6xxx_chip *chip = ds->priv; 2636 int err; 2637 2638 mv88e6xxx_reg_lock(chip); 2639 err = mv88e6xxx_serdes_power(chip, port, true); 2640 mv88e6xxx_reg_unlock(chip); 2641 2642 return err; 2643 } 2644 2645 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2646 { 2647 struct mv88e6xxx_chip *chip = ds->priv; 2648 2649 mv88e6xxx_reg_lock(chip); 2650 if (mv88e6xxx_serdes_power(chip, port, false)) 2651 dev_err(chip->dev, "failed to power off SERDES\n"); 2652 mv88e6xxx_reg_unlock(chip); 2653 } 2654 2655 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2656 unsigned int ageing_time) 2657 { 2658 struct mv88e6xxx_chip *chip = ds->priv; 2659 int err; 2660 2661 mv88e6xxx_reg_lock(chip); 2662 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2663 mv88e6xxx_reg_unlock(chip); 2664 2665 return err; 2666 } 2667 2668 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2669 { 2670 int err; 2671 2672 /* Initialize the statistics unit */ 2673 if (chip->info->ops->stats_set_histogram) { 2674 err = chip->info->ops->stats_set_histogram(chip); 2675 if (err) 2676 return err; 2677 } 2678 2679 return mv88e6xxx_g1_stats_clear(chip); 2680 } 2681 2682 /* Check if the errata has already been applied. */ 2683 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2684 { 2685 int port; 2686 int err; 2687 u16 val; 2688 2689 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2690 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2691 if (err) { 2692 dev_err(chip->dev, 2693 "Error reading hidden register: %d\n", err); 2694 return false; 2695 } 2696 if (val != 0x01c0) 2697 return false; 2698 } 2699 2700 return true; 2701 } 2702 2703 /* The 6390 copper ports have an errata which require poking magic 2704 * values into undocumented hidden registers and then performing a 2705 * software reset. 2706 */ 2707 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2708 { 2709 int port; 2710 int err; 2711 2712 if (mv88e6390_setup_errata_applied(chip)) 2713 return 0; 2714 2715 /* Set the ports into blocking mode */ 2716 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2717 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2718 if (err) 2719 return err; 2720 } 2721 2722 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2723 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2724 if (err) 2725 return err; 2726 } 2727 2728 return mv88e6xxx_software_reset(chip); 2729 } 2730 2731 enum mv88e6xxx_devlink_param_id { 2732 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2733 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2734 }; 2735 2736 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2737 struct devlink_param_gset_ctx *ctx) 2738 { 2739 struct mv88e6xxx_chip *chip = ds->priv; 2740 int err; 2741 2742 mv88e6xxx_reg_lock(chip); 2743 2744 switch (id) { 2745 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2746 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2747 break; 2748 default: 2749 err = -EOPNOTSUPP; 2750 break; 2751 } 2752 2753 mv88e6xxx_reg_unlock(chip); 2754 2755 return err; 2756 } 2757 2758 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2759 struct devlink_param_gset_ctx *ctx) 2760 { 2761 struct mv88e6xxx_chip *chip = ds->priv; 2762 int err; 2763 2764 mv88e6xxx_reg_lock(chip); 2765 2766 switch (id) { 2767 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2768 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2769 break; 2770 default: 2771 err = -EOPNOTSUPP; 2772 break; 2773 } 2774 2775 mv88e6xxx_reg_unlock(chip); 2776 2777 return err; 2778 } 2779 2780 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2781 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2782 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2783 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2784 }; 2785 2786 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2787 { 2788 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2789 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2790 } 2791 2792 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2793 { 2794 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2795 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2796 } 2797 2798 enum mv88e6xxx_devlink_resource_id { 2799 MV88E6XXX_RESOURCE_ID_ATU, 2800 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2801 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2802 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2803 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2804 }; 2805 2806 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2807 u16 bin) 2808 { 2809 u16 occupancy = 0; 2810 int err; 2811 2812 mv88e6xxx_reg_lock(chip); 2813 2814 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2815 bin); 2816 if (err) { 2817 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2818 goto unlock; 2819 } 2820 2821 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2822 if (err) { 2823 dev_err(chip->dev, "failed to perform ATU get next\n"); 2824 goto unlock; 2825 } 2826 2827 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2828 if (err) { 2829 dev_err(chip->dev, "failed to get ATU stats\n"); 2830 goto unlock; 2831 } 2832 2833 unlock: 2834 mv88e6xxx_reg_unlock(chip); 2835 2836 return occupancy; 2837 } 2838 2839 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2840 { 2841 struct mv88e6xxx_chip *chip = priv; 2842 2843 return mv88e6xxx_devlink_atu_bin_get(chip, 2844 MV88E6XXX_G2_ATU_STATS_BIN_0); 2845 } 2846 2847 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2848 { 2849 struct mv88e6xxx_chip *chip = priv; 2850 2851 return mv88e6xxx_devlink_atu_bin_get(chip, 2852 MV88E6XXX_G2_ATU_STATS_BIN_1); 2853 } 2854 2855 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2856 { 2857 struct mv88e6xxx_chip *chip = priv; 2858 2859 return mv88e6xxx_devlink_atu_bin_get(chip, 2860 MV88E6XXX_G2_ATU_STATS_BIN_2); 2861 } 2862 2863 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2864 { 2865 struct mv88e6xxx_chip *chip = priv; 2866 2867 return mv88e6xxx_devlink_atu_bin_get(chip, 2868 MV88E6XXX_G2_ATU_STATS_BIN_3); 2869 } 2870 2871 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2872 { 2873 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2874 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2875 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2876 mv88e6xxx_devlink_atu_bin_3_get(priv); 2877 } 2878 2879 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2880 { 2881 struct devlink_resource_size_params size_params; 2882 struct mv88e6xxx_chip *chip = ds->priv; 2883 int err; 2884 2885 devlink_resource_size_params_init(&size_params, 2886 mv88e6xxx_num_macs(chip), 2887 mv88e6xxx_num_macs(chip), 2888 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2889 2890 err = dsa_devlink_resource_register(ds, "ATU", 2891 mv88e6xxx_num_macs(chip), 2892 MV88E6XXX_RESOURCE_ID_ATU, 2893 DEVLINK_RESOURCE_ID_PARENT_TOP, 2894 &size_params); 2895 if (err) 2896 goto out; 2897 2898 devlink_resource_size_params_init(&size_params, 2899 mv88e6xxx_num_macs(chip) / 4, 2900 mv88e6xxx_num_macs(chip) / 4, 2901 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2902 2903 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2904 mv88e6xxx_num_macs(chip) / 4, 2905 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2906 MV88E6XXX_RESOURCE_ID_ATU, 2907 &size_params); 2908 if (err) 2909 goto out; 2910 2911 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 2912 mv88e6xxx_num_macs(chip) / 4, 2913 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2914 MV88E6XXX_RESOURCE_ID_ATU, 2915 &size_params); 2916 if (err) 2917 goto out; 2918 2919 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 2920 mv88e6xxx_num_macs(chip) / 4, 2921 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2922 MV88E6XXX_RESOURCE_ID_ATU, 2923 &size_params); 2924 if (err) 2925 goto out; 2926 2927 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 2928 mv88e6xxx_num_macs(chip) / 4, 2929 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2930 MV88E6XXX_RESOURCE_ID_ATU, 2931 &size_params); 2932 if (err) 2933 goto out; 2934 2935 dsa_devlink_resource_occ_get_register(ds, 2936 MV88E6XXX_RESOURCE_ID_ATU, 2937 mv88e6xxx_devlink_atu_get, 2938 chip); 2939 2940 dsa_devlink_resource_occ_get_register(ds, 2941 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2942 mv88e6xxx_devlink_atu_bin_0_get, 2943 chip); 2944 2945 dsa_devlink_resource_occ_get_register(ds, 2946 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2947 mv88e6xxx_devlink_atu_bin_1_get, 2948 chip); 2949 2950 dsa_devlink_resource_occ_get_register(ds, 2951 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2952 mv88e6xxx_devlink_atu_bin_2_get, 2953 chip); 2954 2955 dsa_devlink_resource_occ_get_register(ds, 2956 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2957 mv88e6xxx_devlink_atu_bin_3_get, 2958 chip); 2959 2960 return 0; 2961 2962 out: 2963 dsa_devlink_resources_unregister(ds); 2964 return err; 2965 } 2966 2967 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2968 { 2969 mv88e6xxx_teardown_devlink_params(ds); 2970 dsa_devlink_resources_unregister(ds); 2971 } 2972 2973 static int mv88e6xxx_setup(struct dsa_switch *ds) 2974 { 2975 struct mv88e6xxx_chip *chip = ds->priv; 2976 u8 cmode; 2977 int err; 2978 int i; 2979 2980 chip->ds = ds; 2981 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2982 2983 mv88e6xxx_reg_lock(chip); 2984 2985 if (chip->info->ops->setup_errata) { 2986 err = chip->info->ops->setup_errata(chip); 2987 if (err) 2988 goto unlock; 2989 } 2990 2991 /* Cache the cmode of each port. */ 2992 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2993 if (chip->info->ops->port_get_cmode) { 2994 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2995 if (err) 2996 goto unlock; 2997 2998 chip->ports[i].cmode = cmode; 2999 } 3000 } 3001 3002 /* Setup Switch Port Registers */ 3003 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3004 if (dsa_is_unused_port(ds, i)) 3005 continue; 3006 3007 /* Prevent the use of an invalid port. */ 3008 if (mv88e6xxx_is_invalid_port(chip, i)) { 3009 dev_err(chip->dev, "port %d is invalid\n", i); 3010 err = -EINVAL; 3011 goto unlock; 3012 } 3013 3014 err = mv88e6xxx_setup_port(chip, i); 3015 if (err) 3016 goto unlock; 3017 } 3018 3019 err = mv88e6xxx_irl_setup(chip); 3020 if (err) 3021 goto unlock; 3022 3023 err = mv88e6xxx_mac_setup(chip); 3024 if (err) 3025 goto unlock; 3026 3027 err = mv88e6xxx_phy_setup(chip); 3028 if (err) 3029 goto unlock; 3030 3031 err = mv88e6xxx_vtu_setup(chip); 3032 if (err) 3033 goto unlock; 3034 3035 err = mv88e6xxx_pvt_setup(chip); 3036 if (err) 3037 goto unlock; 3038 3039 err = mv88e6xxx_atu_setup(chip); 3040 if (err) 3041 goto unlock; 3042 3043 err = mv88e6xxx_broadcast_setup(chip, 0); 3044 if (err) 3045 goto unlock; 3046 3047 err = mv88e6xxx_pot_setup(chip); 3048 if (err) 3049 goto unlock; 3050 3051 err = mv88e6xxx_rmu_setup(chip); 3052 if (err) 3053 goto unlock; 3054 3055 err = mv88e6xxx_rsvd2cpu_setup(chip); 3056 if (err) 3057 goto unlock; 3058 3059 err = mv88e6xxx_trunk_setup(chip); 3060 if (err) 3061 goto unlock; 3062 3063 err = mv88e6xxx_devmap_setup(chip); 3064 if (err) 3065 goto unlock; 3066 3067 err = mv88e6xxx_pri_setup(chip); 3068 if (err) 3069 goto unlock; 3070 3071 /* Setup PTP Hardware Clock and timestamping */ 3072 if (chip->info->ptp_support) { 3073 err = mv88e6xxx_ptp_setup(chip); 3074 if (err) 3075 goto unlock; 3076 3077 err = mv88e6xxx_hwtstamp_setup(chip); 3078 if (err) 3079 goto unlock; 3080 } 3081 3082 err = mv88e6xxx_stats_setup(chip); 3083 if (err) 3084 goto unlock; 3085 3086 unlock: 3087 mv88e6xxx_reg_unlock(chip); 3088 3089 if (err) 3090 return err; 3091 3092 /* Have to be called without holding the register lock, since 3093 * they take the devlink lock, and we later take the locks in 3094 * the reverse order when getting/setting parameters or 3095 * resource occupancy. 3096 */ 3097 err = mv88e6xxx_setup_devlink_resources(ds); 3098 if (err) 3099 return err; 3100 3101 err = mv88e6xxx_setup_devlink_params(ds); 3102 if (err) 3103 dsa_devlink_resources_unregister(ds); 3104 3105 return err; 3106 } 3107 3108 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3109 { 3110 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3111 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3112 u16 val; 3113 int err; 3114 3115 if (!chip->info->ops->phy_read) 3116 return -EOPNOTSUPP; 3117 3118 mv88e6xxx_reg_lock(chip); 3119 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3120 mv88e6xxx_reg_unlock(chip); 3121 3122 if (reg == MII_PHYSID2) { 3123 /* Some internal PHYs don't have a model number. */ 3124 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3125 /* Then there is the 6165 family. It gets is 3126 * PHYs correct. But it can also have two 3127 * SERDES interfaces in the PHY address 3128 * space. And these don't have a model 3129 * number. But they are not PHYs, so we don't 3130 * want to give them something a PHY driver 3131 * will recognise. 3132 * 3133 * Use the mv88e6390 family model number 3134 * instead, for anything which really could be 3135 * a PHY, 3136 */ 3137 if (!(val & 0x3f0)) 3138 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3139 } 3140 3141 return err ? err : val; 3142 } 3143 3144 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3145 { 3146 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3147 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3148 int err; 3149 3150 if (!chip->info->ops->phy_write) 3151 return -EOPNOTSUPP; 3152 3153 mv88e6xxx_reg_lock(chip); 3154 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3155 mv88e6xxx_reg_unlock(chip); 3156 3157 return err; 3158 } 3159 3160 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3161 struct device_node *np, 3162 bool external) 3163 { 3164 static int index; 3165 struct mv88e6xxx_mdio_bus *mdio_bus; 3166 struct mii_bus *bus; 3167 int err; 3168 3169 if (external) { 3170 mv88e6xxx_reg_lock(chip); 3171 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3172 mv88e6xxx_reg_unlock(chip); 3173 3174 if (err) 3175 return err; 3176 } 3177 3178 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3179 if (!bus) 3180 return -ENOMEM; 3181 3182 mdio_bus = bus->priv; 3183 mdio_bus->bus = bus; 3184 mdio_bus->chip = chip; 3185 INIT_LIST_HEAD(&mdio_bus->list); 3186 mdio_bus->external = external; 3187 3188 if (np) { 3189 bus->name = np->full_name; 3190 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3191 } else { 3192 bus->name = "mv88e6xxx SMI"; 3193 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3194 } 3195 3196 bus->read = mv88e6xxx_mdio_read; 3197 bus->write = mv88e6xxx_mdio_write; 3198 bus->parent = chip->dev; 3199 3200 if (!external) { 3201 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3202 if (err) 3203 return err; 3204 } 3205 3206 err = of_mdiobus_register(bus, np); 3207 if (err) { 3208 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3209 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3210 return err; 3211 } 3212 3213 if (external) 3214 list_add_tail(&mdio_bus->list, &chip->mdios); 3215 else 3216 list_add(&mdio_bus->list, &chip->mdios); 3217 3218 return 0; 3219 } 3220 3221 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3222 { .compatible = "marvell,mv88e6xxx-mdio-external", 3223 .data = (void *)true }, 3224 { }, 3225 }; 3226 3227 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3228 3229 { 3230 struct mv88e6xxx_mdio_bus *mdio_bus; 3231 struct mii_bus *bus; 3232 3233 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3234 bus = mdio_bus->bus; 3235 3236 if (!mdio_bus->external) 3237 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3238 3239 mdiobus_unregister(bus); 3240 } 3241 } 3242 3243 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3244 struct device_node *np) 3245 { 3246 const struct of_device_id *match; 3247 struct device_node *child; 3248 int err; 3249 3250 /* Always register one mdio bus for the internal/default mdio 3251 * bus. This maybe represented in the device tree, but is 3252 * optional. 3253 */ 3254 child = of_get_child_by_name(np, "mdio"); 3255 err = mv88e6xxx_mdio_register(chip, child, false); 3256 if (err) 3257 return err; 3258 3259 /* Walk the device tree, and see if there are any other nodes 3260 * which say they are compatible with the external mdio 3261 * bus. 3262 */ 3263 for_each_available_child_of_node(np, child) { 3264 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3265 if (match) { 3266 err = mv88e6xxx_mdio_register(chip, child, true); 3267 if (err) { 3268 mv88e6xxx_mdios_unregister(chip); 3269 of_node_put(child); 3270 return err; 3271 } 3272 } 3273 } 3274 3275 return 0; 3276 } 3277 3278 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3279 { 3280 struct mv88e6xxx_chip *chip = ds->priv; 3281 3282 return chip->eeprom_len; 3283 } 3284 3285 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3286 struct ethtool_eeprom *eeprom, u8 *data) 3287 { 3288 struct mv88e6xxx_chip *chip = ds->priv; 3289 int err; 3290 3291 if (!chip->info->ops->get_eeprom) 3292 return -EOPNOTSUPP; 3293 3294 mv88e6xxx_reg_lock(chip); 3295 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3296 mv88e6xxx_reg_unlock(chip); 3297 3298 if (err) 3299 return err; 3300 3301 eeprom->magic = 0xc3ec4951; 3302 3303 return 0; 3304 } 3305 3306 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3307 struct ethtool_eeprom *eeprom, u8 *data) 3308 { 3309 struct mv88e6xxx_chip *chip = ds->priv; 3310 int err; 3311 3312 if (!chip->info->ops->set_eeprom) 3313 return -EOPNOTSUPP; 3314 3315 if (eeprom->magic != 0xc3ec4951) 3316 return -EINVAL; 3317 3318 mv88e6xxx_reg_lock(chip); 3319 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3320 mv88e6xxx_reg_unlock(chip); 3321 3322 return err; 3323 } 3324 3325 static const struct mv88e6xxx_ops mv88e6085_ops = { 3326 /* MV88E6XXX_FAMILY_6097 */ 3327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3328 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3329 .irl_init_all = mv88e6352_g2_irl_init_all, 3330 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3331 .phy_read = mv88e6185_phy_ppu_read, 3332 .phy_write = mv88e6185_phy_ppu_write, 3333 .port_set_link = mv88e6xxx_port_set_link, 3334 .port_set_duplex = mv88e6xxx_port_set_duplex, 3335 .port_set_speed = mv88e6185_port_set_speed, 3336 .port_tag_remap = mv88e6095_port_tag_remap, 3337 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3338 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3339 .port_set_ether_type = mv88e6351_port_set_ether_type, 3340 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3341 .port_pause_limit = mv88e6097_port_pause_limit, 3342 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3343 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3344 .port_link_state = mv88e6352_port_link_state, 3345 .port_get_cmode = mv88e6185_port_get_cmode, 3346 .port_setup_message_port = mv88e6xxx_setup_message_port, 3347 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3348 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3349 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3350 .stats_get_strings = mv88e6095_stats_get_strings, 3351 .stats_get_stats = mv88e6095_stats_get_stats, 3352 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3353 .set_egress_port = mv88e6095_g1_set_egress_port, 3354 .watchdog_ops = &mv88e6097_watchdog_ops, 3355 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3356 .pot_clear = mv88e6xxx_g2_pot_clear, 3357 .ppu_enable = mv88e6185_g1_ppu_enable, 3358 .ppu_disable = mv88e6185_g1_ppu_disable, 3359 .reset = mv88e6185_g1_reset, 3360 .rmu_disable = mv88e6085_g1_rmu_disable, 3361 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3362 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3363 .phylink_validate = mv88e6185_phylink_validate, 3364 }; 3365 3366 static const struct mv88e6xxx_ops mv88e6095_ops = { 3367 /* MV88E6XXX_FAMILY_6095 */ 3368 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3369 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3370 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3371 .phy_read = mv88e6185_phy_ppu_read, 3372 .phy_write = mv88e6185_phy_ppu_write, 3373 .port_set_link = mv88e6xxx_port_set_link, 3374 .port_set_duplex = mv88e6xxx_port_set_duplex, 3375 .port_set_speed = mv88e6185_port_set_speed, 3376 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3377 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3378 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3379 .port_link_state = mv88e6185_port_link_state, 3380 .port_get_cmode = mv88e6185_port_get_cmode, 3381 .port_setup_message_port = mv88e6xxx_setup_message_port, 3382 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3383 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3384 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3385 .stats_get_strings = mv88e6095_stats_get_strings, 3386 .stats_get_stats = mv88e6095_stats_get_stats, 3387 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3388 .ppu_enable = mv88e6185_g1_ppu_enable, 3389 .ppu_disable = mv88e6185_g1_ppu_disable, 3390 .reset = mv88e6185_g1_reset, 3391 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3392 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3393 .phylink_validate = mv88e6185_phylink_validate, 3394 }; 3395 3396 static const struct mv88e6xxx_ops mv88e6097_ops = { 3397 /* MV88E6XXX_FAMILY_6097 */ 3398 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3399 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3400 .irl_init_all = mv88e6352_g2_irl_init_all, 3401 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3402 .phy_read = mv88e6xxx_g2_smi_phy_read, 3403 .phy_write = mv88e6xxx_g2_smi_phy_write, 3404 .port_set_link = mv88e6xxx_port_set_link, 3405 .port_set_duplex = mv88e6xxx_port_set_duplex, 3406 .port_set_speed = mv88e6185_port_set_speed, 3407 .port_tag_remap = mv88e6095_port_tag_remap, 3408 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3409 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3410 .port_set_ether_type = mv88e6351_port_set_ether_type, 3411 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3412 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3413 .port_pause_limit = mv88e6097_port_pause_limit, 3414 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3415 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3416 .port_link_state = mv88e6352_port_link_state, 3417 .port_get_cmode = mv88e6185_port_get_cmode, 3418 .port_setup_message_port = mv88e6xxx_setup_message_port, 3419 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3420 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3421 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3422 .stats_get_strings = mv88e6095_stats_get_strings, 3423 .stats_get_stats = mv88e6095_stats_get_stats, 3424 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3425 .set_egress_port = mv88e6095_g1_set_egress_port, 3426 .watchdog_ops = &mv88e6097_watchdog_ops, 3427 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3428 .pot_clear = mv88e6xxx_g2_pot_clear, 3429 .reset = mv88e6352_g1_reset, 3430 .rmu_disable = mv88e6085_g1_rmu_disable, 3431 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3432 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3433 .phylink_validate = mv88e6185_phylink_validate, 3434 }; 3435 3436 static const struct mv88e6xxx_ops mv88e6123_ops = { 3437 /* MV88E6XXX_FAMILY_6165 */ 3438 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3439 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3440 .irl_init_all = mv88e6352_g2_irl_init_all, 3441 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3442 .phy_read = mv88e6xxx_g2_smi_phy_read, 3443 .phy_write = mv88e6xxx_g2_smi_phy_write, 3444 .port_set_link = mv88e6xxx_port_set_link, 3445 .port_set_duplex = mv88e6xxx_port_set_duplex, 3446 .port_set_speed = mv88e6185_port_set_speed, 3447 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3448 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3449 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3450 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3451 .port_link_state = mv88e6352_port_link_state, 3452 .port_get_cmode = mv88e6185_port_get_cmode, 3453 .port_setup_message_port = mv88e6xxx_setup_message_port, 3454 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3455 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3456 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3457 .stats_get_strings = mv88e6095_stats_get_strings, 3458 .stats_get_stats = mv88e6095_stats_get_stats, 3459 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3460 .set_egress_port = mv88e6095_g1_set_egress_port, 3461 .watchdog_ops = &mv88e6097_watchdog_ops, 3462 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3463 .pot_clear = mv88e6xxx_g2_pot_clear, 3464 .reset = mv88e6352_g1_reset, 3465 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3466 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3467 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3468 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3469 .phylink_validate = mv88e6185_phylink_validate, 3470 }; 3471 3472 static const struct mv88e6xxx_ops mv88e6131_ops = { 3473 /* MV88E6XXX_FAMILY_6185 */ 3474 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3475 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3476 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3477 .phy_read = mv88e6185_phy_ppu_read, 3478 .phy_write = mv88e6185_phy_ppu_write, 3479 .port_set_link = mv88e6xxx_port_set_link, 3480 .port_set_duplex = mv88e6xxx_port_set_duplex, 3481 .port_set_speed = mv88e6185_port_set_speed, 3482 .port_tag_remap = mv88e6095_port_tag_remap, 3483 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3484 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3485 .port_set_ether_type = mv88e6351_port_set_ether_type, 3486 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3487 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3489 .port_pause_limit = mv88e6097_port_pause_limit, 3490 .port_set_pause = mv88e6185_port_set_pause, 3491 .port_link_state = mv88e6352_port_link_state, 3492 .port_get_cmode = mv88e6185_port_get_cmode, 3493 .port_setup_message_port = mv88e6xxx_setup_message_port, 3494 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3496 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3497 .stats_get_strings = mv88e6095_stats_get_strings, 3498 .stats_get_stats = mv88e6095_stats_get_stats, 3499 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3500 .set_egress_port = mv88e6095_g1_set_egress_port, 3501 .watchdog_ops = &mv88e6097_watchdog_ops, 3502 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3503 .ppu_enable = mv88e6185_g1_ppu_enable, 3504 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3505 .ppu_disable = mv88e6185_g1_ppu_disable, 3506 .reset = mv88e6185_g1_reset, 3507 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3508 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3509 .phylink_validate = mv88e6185_phylink_validate, 3510 }; 3511 3512 static const struct mv88e6xxx_ops mv88e6141_ops = { 3513 /* MV88E6XXX_FAMILY_6341 */ 3514 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3515 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3516 .irl_init_all = mv88e6352_g2_irl_init_all, 3517 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3518 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3519 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3520 .phy_read = mv88e6xxx_g2_smi_phy_read, 3521 .phy_write = mv88e6xxx_g2_smi_phy_write, 3522 .port_set_link = mv88e6xxx_port_set_link, 3523 .port_set_duplex = mv88e6xxx_port_set_duplex, 3524 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3525 .port_set_speed = mv88e6341_port_set_speed, 3526 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3527 .port_tag_remap = mv88e6095_port_tag_remap, 3528 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3529 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3530 .port_set_ether_type = mv88e6351_port_set_ether_type, 3531 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3532 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3533 .port_pause_limit = mv88e6097_port_pause_limit, 3534 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3535 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3536 .port_link_state = mv88e6352_port_link_state, 3537 .port_get_cmode = mv88e6352_port_get_cmode, 3538 .port_set_cmode = mv88e6341_port_set_cmode, 3539 .port_setup_message_port = mv88e6xxx_setup_message_port, 3540 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3541 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3542 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3543 .stats_get_strings = mv88e6320_stats_get_strings, 3544 .stats_get_stats = mv88e6390_stats_get_stats, 3545 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3546 .set_egress_port = mv88e6390_g1_set_egress_port, 3547 .watchdog_ops = &mv88e6390_watchdog_ops, 3548 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3549 .pot_clear = mv88e6xxx_g2_pot_clear, 3550 .reset = mv88e6352_g1_reset, 3551 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3552 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3553 .serdes_power = mv88e6390_serdes_power, 3554 .serdes_get_lane = mv88e6341_serdes_get_lane, 3555 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3556 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3557 .serdes_irq_status = mv88e6390_serdes_irq_status, 3558 .gpio_ops = &mv88e6352_gpio_ops, 3559 .phylink_validate = mv88e6341_phylink_validate, 3560 }; 3561 3562 static const struct mv88e6xxx_ops mv88e6161_ops = { 3563 /* MV88E6XXX_FAMILY_6165 */ 3564 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3565 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3566 .irl_init_all = mv88e6352_g2_irl_init_all, 3567 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3568 .phy_read = mv88e6xxx_g2_smi_phy_read, 3569 .phy_write = mv88e6xxx_g2_smi_phy_write, 3570 .port_set_link = mv88e6xxx_port_set_link, 3571 .port_set_duplex = mv88e6xxx_port_set_duplex, 3572 .port_set_speed = mv88e6185_port_set_speed, 3573 .port_tag_remap = mv88e6095_port_tag_remap, 3574 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3575 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3576 .port_set_ether_type = mv88e6351_port_set_ether_type, 3577 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3578 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3579 .port_pause_limit = mv88e6097_port_pause_limit, 3580 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3581 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3582 .port_link_state = mv88e6352_port_link_state, 3583 .port_get_cmode = mv88e6185_port_get_cmode, 3584 .port_setup_message_port = mv88e6xxx_setup_message_port, 3585 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3586 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3587 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3588 .stats_get_strings = mv88e6095_stats_get_strings, 3589 .stats_get_stats = mv88e6095_stats_get_stats, 3590 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3591 .set_egress_port = mv88e6095_g1_set_egress_port, 3592 .watchdog_ops = &mv88e6097_watchdog_ops, 3593 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3594 .pot_clear = mv88e6xxx_g2_pot_clear, 3595 .reset = mv88e6352_g1_reset, 3596 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3597 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3598 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3599 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3600 .avb_ops = &mv88e6165_avb_ops, 3601 .ptp_ops = &mv88e6165_ptp_ops, 3602 .phylink_validate = mv88e6185_phylink_validate, 3603 }; 3604 3605 static const struct mv88e6xxx_ops mv88e6165_ops = { 3606 /* MV88E6XXX_FAMILY_6165 */ 3607 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3608 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3609 .irl_init_all = mv88e6352_g2_irl_init_all, 3610 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3611 .phy_read = mv88e6165_phy_read, 3612 .phy_write = mv88e6165_phy_write, 3613 .port_set_link = mv88e6xxx_port_set_link, 3614 .port_set_duplex = mv88e6xxx_port_set_duplex, 3615 .port_set_speed = mv88e6185_port_set_speed, 3616 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3617 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3618 .port_link_state = mv88e6352_port_link_state, 3619 .port_get_cmode = mv88e6185_port_get_cmode, 3620 .port_setup_message_port = mv88e6xxx_setup_message_port, 3621 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3622 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3623 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3624 .stats_get_strings = mv88e6095_stats_get_strings, 3625 .stats_get_stats = mv88e6095_stats_get_stats, 3626 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3627 .set_egress_port = mv88e6095_g1_set_egress_port, 3628 .watchdog_ops = &mv88e6097_watchdog_ops, 3629 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3630 .pot_clear = mv88e6xxx_g2_pot_clear, 3631 .reset = mv88e6352_g1_reset, 3632 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3633 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3634 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3635 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3636 .avb_ops = &mv88e6165_avb_ops, 3637 .ptp_ops = &mv88e6165_ptp_ops, 3638 .phylink_validate = mv88e6185_phylink_validate, 3639 }; 3640 3641 static const struct mv88e6xxx_ops mv88e6171_ops = { 3642 /* MV88E6XXX_FAMILY_6351 */ 3643 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3644 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3645 .irl_init_all = mv88e6352_g2_irl_init_all, 3646 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3647 .phy_read = mv88e6xxx_g2_smi_phy_read, 3648 .phy_write = mv88e6xxx_g2_smi_phy_write, 3649 .port_set_link = mv88e6xxx_port_set_link, 3650 .port_set_duplex = mv88e6xxx_port_set_duplex, 3651 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3652 .port_set_speed = mv88e6185_port_set_speed, 3653 .port_tag_remap = mv88e6095_port_tag_remap, 3654 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3655 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3656 .port_set_ether_type = mv88e6351_port_set_ether_type, 3657 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3658 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3659 .port_pause_limit = mv88e6097_port_pause_limit, 3660 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3661 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3662 .port_link_state = mv88e6352_port_link_state, 3663 .port_get_cmode = mv88e6352_port_get_cmode, 3664 .port_setup_message_port = mv88e6xxx_setup_message_port, 3665 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3666 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3667 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3668 .stats_get_strings = mv88e6095_stats_get_strings, 3669 .stats_get_stats = mv88e6095_stats_get_stats, 3670 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3671 .set_egress_port = mv88e6095_g1_set_egress_port, 3672 .watchdog_ops = &mv88e6097_watchdog_ops, 3673 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3674 .pot_clear = mv88e6xxx_g2_pot_clear, 3675 .reset = mv88e6352_g1_reset, 3676 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3677 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3678 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3679 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3680 .phylink_validate = mv88e6185_phylink_validate, 3681 }; 3682 3683 static const struct mv88e6xxx_ops mv88e6172_ops = { 3684 /* MV88E6XXX_FAMILY_6352 */ 3685 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3686 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3687 .irl_init_all = mv88e6352_g2_irl_init_all, 3688 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3689 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3690 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3691 .phy_read = mv88e6xxx_g2_smi_phy_read, 3692 .phy_write = mv88e6xxx_g2_smi_phy_write, 3693 .port_set_link = mv88e6xxx_port_set_link, 3694 .port_set_duplex = mv88e6xxx_port_set_duplex, 3695 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3696 .port_set_speed = mv88e6352_port_set_speed, 3697 .port_tag_remap = mv88e6095_port_tag_remap, 3698 .port_set_policy = mv88e6352_port_set_policy, 3699 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3700 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3701 .port_set_ether_type = mv88e6351_port_set_ether_type, 3702 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3703 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3704 .port_pause_limit = mv88e6097_port_pause_limit, 3705 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3706 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3707 .port_link_state = mv88e6352_port_link_state, 3708 .port_get_cmode = mv88e6352_port_get_cmode, 3709 .port_setup_message_port = mv88e6xxx_setup_message_port, 3710 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3711 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3712 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3713 .stats_get_strings = mv88e6095_stats_get_strings, 3714 .stats_get_stats = mv88e6095_stats_get_stats, 3715 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3716 .set_egress_port = mv88e6095_g1_set_egress_port, 3717 .watchdog_ops = &mv88e6097_watchdog_ops, 3718 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3719 .pot_clear = mv88e6xxx_g2_pot_clear, 3720 .reset = mv88e6352_g1_reset, 3721 .rmu_disable = mv88e6352_g1_rmu_disable, 3722 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3723 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3724 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3725 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3726 .serdes_get_lane = mv88e6352_serdes_get_lane, 3727 .serdes_power = mv88e6352_serdes_power, 3728 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3729 .serdes_get_regs = mv88e6352_serdes_get_regs, 3730 .gpio_ops = &mv88e6352_gpio_ops, 3731 .phylink_validate = mv88e6352_phylink_validate, 3732 }; 3733 3734 static const struct mv88e6xxx_ops mv88e6175_ops = { 3735 /* MV88E6XXX_FAMILY_6351 */ 3736 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3737 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3738 .irl_init_all = mv88e6352_g2_irl_init_all, 3739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3740 .phy_read = mv88e6xxx_g2_smi_phy_read, 3741 .phy_write = mv88e6xxx_g2_smi_phy_write, 3742 .port_set_link = mv88e6xxx_port_set_link, 3743 .port_set_duplex = mv88e6xxx_port_set_duplex, 3744 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3745 .port_set_speed = mv88e6185_port_set_speed, 3746 .port_tag_remap = mv88e6095_port_tag_remap, 3747 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3748 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3749 .port_set_ether_type = mv88e6351_port_set_ether_type, 3750 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3751 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3752 .port_pause_limit = mv88e6097_port_pause_limit, 3753 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3754 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3755 .port_link_state = mv88e6352_port_link_state, 3756 .port_get_cmode = mv88e6352_port_get_cmode, 3757 .port_setup_message_port = mv88e6xxx_setup_message_port, 3758 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3759 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3760 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3761 .stats_get_strings = mv88e6095_stats_get_strings, 3762 .stats_get_stats = mv88e6095_stats_get_stats, 3763 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3764 .set_egress_port = mv88e6095_g1_set_egress_port, 3765 .watchdog_ops = &mv88e6097_watchdog_ops, 3766 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3767 .pot_clear = mv88e6xxx_g2_pot_clear, 3768 .reset = mv88e6352_g1_reset, 3769 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3770 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3771 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3772 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3773 .phylink_validate = mv88e6185_phylink_validate, 3774 }; 3775 3776 static const struct mv88e6xxx_ops mv88e6176_ops = { 3777 /* MV88E6XXX_FAMILY_6352 */ 3778 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3779 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3780 .irl_init_all = mv88e6352_g2_irl_init_all, 3781 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3782 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3784 .phy_read = mv88e6xxx_g2_smi_phy_read, 3785 .phy_write = mv88e6xxx_g2_smi_phy_write, 3786 .port_set_link = mv88e6xxx_port_set_link, 3787 .port_set_duplex = mv88e6xxx_port_set_duplex, 3788 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3789 .port_set_speed = mv88e6352_port_set_speed, 3790 .port_tag_remap = mv88e6095_port_tag_remap, 3791 .port_set_policy = mv88e6352_port_set_policy, 3792 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3793 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3794 .port_set_ether_type = mv88e6351_port_set_ether_type, 3795 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3796 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3797 .port_pause_limit = mv88e6097_port_pause_limit, 3798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3800 .port_link_state = mv88e6352_port_link_state, 3801 .port_get_cmode = mv88e6352_port_get_cmode, 3802 .port_setup_message_port = mv88e6xxx_setup_message_port, 3803 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3804 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3805 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3806 .stats_get_strings = mv88e6095_stats_get_strings, 3807 .stats_get_stats = mv88e6095_stats_get_stats, 3808 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3809 .set_egress_port = mv88e6095_g1_set_egress_port, 3810 .watchdog_ops = &mv88e6097_watchdog_ops, 3811 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3812 .pot_clear = mv88e6xxx_g2_pot_clear, 3813 .reset = mv88e6352_g1_reset, 3814 .rmu_disable = mv88e6352_g1_rmu_disable, 3815 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3816 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3817 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3818 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3819 .serdes_get_lane = mv88e6352_serdes_get_lane, 3820 .serdes_power = mv88e6352_serdes_power, 3821 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3822 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3823 .serdes_irq_status = mv88e6352_serdes_irq_status, 3824 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3825 .serdes_get_regs = mv88e6352_serdes_get_regs, 3826 .gpio_ops = &mv88e6352_gpio_ops, 3827 .phylink_validate = mv88e6352_phylink_validate, 3828 }; 3829 3830 static const struct mv88e6xxx_ops mv88e6185_ops = { 3831 /* MV88E6XXX_FAMILY_6185 */ 3832 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3833 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3834 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3835 .phy_read = mv88e6185_phy_ppu_read, 3836 .phy_write = mv88e6185_phy_ppu_write, 3837 .port_set_link = mv88e6xxx_port_set_link, 3838 .port_set_duplex = mv88e6xxx_port_set_duplex, 3839 .port_set_speed = mv88e6185_port_set_speed, 3840 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3841 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3842 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3843 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3844 .port_set_pause = mv88e6185_port_set_pause, 3845 .port_link_state = mv88e6185_port_link_state, 3846 .port_get_cmode = mv88e6185_port_get_cmode, 3847 .port_setup_message_port = mv88e6xxx_setup_message_port, 3848 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3849 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3850 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3851 .stats_get_strings = mv88e6095_stats_get_strings, 3852 .stats_get_stats = mv88e6095_stats_get_stats, 3853 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3854 .set_egress_port = mv88e6095_g1_set_egress_port, 3855 .watchdog_ops = &mv88e6097_watchdog_ops, 3856 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3857 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3858 .ppu_enable = mv88e6185_g1_ppu_enable, 3859 .ppu_disable = mv88e6185_g1_ppu_disable, 3860 .reset = mv88e6185_g1_reset, 3861 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3862 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3863 .phylink_validate = mv88e6185_phylink_validate, 3864 }; 3865 3866 static const struct mv88e6xxx_ops mv88e6190_ops = { 3867 /* MV88E6XXX_FAMILY_6390 */ 3868 .setup_errata = mv88e6390_setup_errata, 3869 .irl_init_all = mv88e6390_g2_irl_init_all, 3870 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3871 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3872 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3873 .phy_read = mv88e6xxx_g2_smi_phy_read, 3874 .phy_write = mv88e6xxx_g2_smi_phy_write, 3875 .port_set_link = mv88e6xxx_port_set_link, 3876 .port_set_duplex = mv88e6xxx_port_set_duplex, 3877 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3878 .port_set_speed = mv88e6390_port_set_speed, 3879 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3880 .port_tag_remap = mv88e6390_port_tag_remap, 3881 .port_set_policy = mv88e6352_port_set_policy, 3882 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3883 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3884 .port_set_ether_type = mv88e6351_port_set_ether_type, 3885 .port_pause_limit = mv88e6390_port_pause_limit, 3886 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3887 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3888 .port_link_state = mv88e6352_port_link_state, 3889 .port_get_cmode = mv88e6352_port_get_cmode, 3890 .port_set_cmode = mv88e6390_port_set_cmode, 3891 .port_setup_message_port = mv88e6xxx_setup_message_port, 3892 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3893 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3894 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3895 .stats_get_strings = mv88e6320_stats_get_strings, 3896 .stats_get_stats = mv88e6390_stats_get_stats, 3897 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3898 .set_egress_port = mv88e6390_g1_set_egress_port, 3899 .watchdog_ops = &mv88e6390_watchdog_ops, 3900 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3901 .pot_clear = mv88e6xxx_g2_pot_clear, 3902 .reset = mv88e6352_g1_reset, 3903 .rmu_disable = mv88e6390_g1_rmu_disable, 3904 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3905 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3906 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3907 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3908 .serdes_power = mv88e6390_serdes_power, 3909 .serdes_get_lane = mv88e6390_serdes_get_lane, 3910 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3911 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3912 .serdes_irq_status = mv88e6390_serdes_irq_status, 3913 .serdes_get_strings = mv88e6390_serdes_get_strings, 3914 .serdes_get_stats = mv88e6390_serdes_get_stats, 3915 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3916 .serdes_get_regs = mv88e6390_serdes_get_regs, 3917 .phylink_validate = mv88e6390_phylink_validate, 3918 .gpio_ops = &mv88e6352_gpio_ops, 3919 .phylink_validate = mv88e6390_phylink_validate, 3920 }; 3921 3922 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3923 /* MV88E6XXX_FAMILY_6390 */ 3924 .setup_errata = mv88e6390_setup_errata, 3925 .irl_init_all = mv88e6390_g2_irl_init_all, 3926 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3927 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3928 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3929 .phy_read = mv88e6xxx_g2_smi_phy_read, 3930 .phy_write = mv88e6xxx_g2_smi_phy_write, 3931 .port_set_link = mv88e6xxx_port_set_link, 3932 .port_set_duplex = mv88e6xxx_port_set_duplex, 3933 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3934 .port_set_speed = mv88e6390x_port_set_speed, 3935 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3936 .port_tag_remap = mv88e6390_port_tag_remap, 3937 .port_set_policy = mv88e6352_port_set_policy, 3938 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3939 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3940 .port_set_ether_type = mv88e6351_port_set_ether_type, 3941 .port_pause_limit = mv88e6390_port_pause_limit, 3942 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3943 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3944 .port_link_state = mv88e6352_port_link_state, 3945 .port_get_cmode = mv88e6352_port_get_cmode, 3946 .port_set_cmode = mv88e6390x_port_set_cmode, 3947 .port_setup_message_port = mv88e6xxx_setup_message_port, 3948 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3949 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3950 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3951 .stats_get_strings = mv88e6320_stats_get_strings, 3952 .stats_get_stats = mv88e6390_stats_get_stats, 3953 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3954 .set_egress_port = mv88e6390_g1_set_egress_port, 3955 .watchdog_ops = &mv88e6390_watchdog_ops, 3956 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3957 .pot_clear = mv88e6xxx_g2_pot_clear, 3958 .reset = mv88e6352_g1_reset, 3959 .rmu_disable = mv88e6390_g1_rmu_disable, 3960 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3961 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3962 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3963 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3964 .serdes_power = mv88e6390_serdes_power, 3965 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3966 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3967 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3968 .serdes_irq_status = mv88e6390_serdes_irq_status, 3969 .serdes_get_strings = mv88e6390_serdes_get_strings, 3970 .serdes_get_stats = mv88e6390_serdes_get_stats, 3971 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3972 .serdes_get_regs = mv88e6390_serdes_get_regs, 3973 .phylink_validate = mv88e6390_phylink_validate, 3974 .gpio_ops = &mv88e6352_gpio_ops, 3975 .phylink_validate = mv88e6390x_phylink_validate, 3976 }; 3977 3978 static const struct mv88e6xxx_ops mv88e6191_ops = { 3979 /* MV88E6XXX_FAMILY_6390 */ 3980 .setup_errata = mv88e6390_setup_errata, 3981 .irl_init_all = mv88e6390_g2_irl_init_all, 3982 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3983 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3984 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3985 .phy_read = mv88e6xxx_g2_smi_phy_read, 3986 .phy_write = mv88e6xxx_g2_smi_phy_write, 3987 .port_set_link = mv88e6xxx_port_set_link, 3988 .port_set_duplex = mv88e6xxx_port_set_duplex, 3989 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3990 .port_set_speed = mv88e6390_port_set_speed, 3991 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3992 .port_tag_remap = mv88e6390_port_tag_remap, 3993 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3994 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3995 .port_set_ether_type = mv88e6351_port_set_ether_type, 3996 .port_pause_limit = mv88e6390_port_pause_limit, 3997 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3998 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3999 .port_link_state = mv88e6352_port_link_state, 4000 .port_get_cmode = mv88e6352_port_get_cmode, 4001 .port_set_cmode = mv88e6390_port_set_cmode, 4002 .port_setup_message_port = mv88e6xxx_setup_message_port, 4003 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4004 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4005 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4006 .stats_get_strings = mv88e6320_stats_get_strings, 4007 .stats_get_stats = mv88e6390_stats_get_stats, 4008 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4009 .set_egress_port = mv88e6390_g1_set_egress_port, 4010 .watchdog_ops = &mv88e6390_watchdog_ops, 4011 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4012 .pot_clear = mv88e6xxx_g2_pot_clear, 4013 .reset = mv88e6352_g1_reset, 4014 .rmu_disable = mv88e6390_g1_rmu_disable, 4015 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4016 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4017 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4018 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4019 .serdes_power = mv88e6390_serdes_power, 4020 .serdes_get_lane = mv88e6390_serdes_get_lane, 4021 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4022 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4023 .serdes_irq_status = mv88e6390_serdes_irq_status, 4024 .serdes_get_strings = mv88e6390_serdes_get_strings, 4025 .serdes_get_stats = mv88e6390_serdes_get_stats, 4026 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4027 .serdes_get_regs = mv88e6390_serdes_get_regs, 4028 .phylink_validate = mv88e6390_phylink_validate, 4029 .avb_ops = &mv88e6390_avb_ops, 4030 .ptp_ops = &mv88e6352_ptp_ops, 4031 .phylink_validate = mv88e6390_phylink_validate, 4032 }; 4033 4034 static const struct mv88e6xxx_ops mv88e6240_ops = { 4035 /* MV88E6XXX_FAMILY_6352 */ 4036 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4037 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4038 .irl_init_all = mv88e6352_g2_irl_init_all, 4039 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4040 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4042 .phy_read = mv88e6xxx_g2_smi_phy_read, 4043 .phy_write = mv88e6xxx_g2_smi_phy_write, 4044 .port_set_link = mv88e6xxx_port_set_link, 4045 .port_set_duplex = mv88e6xxx_port_set_duplex, 4046 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4047 .port_set_speed = mv88e6352_port_set_speed, 4048 .port_tag_remap = mv88e6095_port_tag_remap, 4049 .port_set_policy = mv88e6352_port_set_policy, 4050 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4051 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4052 .port_set_ether_type = mv88e6351_port_set_ether_type, 4053 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4054 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4055 .port_pause_limit = mv88e6097_port_pause_limit, 4056 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4057 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4058 .port_link_state = mv88e6352_port_link_state, 4059 .port_get_cmode = mv88e6352_port_get_cmode, 4060 .port_setup_message_port = mv88e6xxx_setup_message_port, 4061 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4062 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4063 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4064 .stats_get_strings = mv88e6095_stats_get_strings, 4065 .stats_get_stats = mv88e6095_stats_get_stats, 4066 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4067 .set_egress_port = mv88e6095_g1_set_egress_port, 4068 .watchdog_ops = &mv88e6097_watchdog_ops, 4069 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4070 .pot_clear = mv88e6xxx_g2_pot_clear, 4071 .reset = mv88e6352_g1_reset, 4072 .rmu_disable = mv88e6352_g1_rmu_disable, 4073 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4074 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4075 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4076 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4077 .serdes_get_lane = mv88e6352_serdes_get_lane, 4078 .serdes_power = mv88e6352_serdes_power, 4079 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4080 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4081 .serdes_irq_status = mv88e6352_serdes_irq_status, 4082 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4083 .serdes_get_regs = mv88e6352_serdes_get_regs, 4084 .gpio_ops = &mv88e6352_gpio_ops, 4085 .avb_ops = &mv88e6352_avb_ops, 4086 .ptp_ops = &mv88e6352_ptp_ops, 4087 .phylink_validate = mv88e6352_phylink_validate, 4088 }; 4089 4090 static const struct mv88e6xxx_ops mv88e6250_ops = { 4091 /* MV88E6XXX_FAMILY_6250 */ 4092 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4093 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4094 .irl_init_all = mv88e6352_g2_irl_init_all, 4095 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4096 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4097 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4098 .phy_read = mv88e6xxx_g2_smi_phy_read, 4099 .phy_write = mv88e6xxx_g2_smi_phy_write, 4100 .port_set_link = mv88e6xxx_port_set_link, 4101 .port_set_duplex = mv88e6xxx_port_set_duplex, 4102 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4103 .port_set_speed = mv88e6250_port_set_speed, 4104 .port_tag_remap = mv88e6095_port_tag_remap, 4105 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4106 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4107 .port_set_ether_type = mv88e6351_port_set_ether_type, 4108 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4109 .port_pause_limit = mv88e6097_port_pause_limit, 4110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4111 .port_link_state = mv88e6250_port_link_state, 4112 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4113 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4114 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4115 .stats_get_strings = mv88e6250_stats_get_strings, 4116 .stats_get_stats = mv88e6250_stats_get_stats, 4117 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4118 .set_egress_port = mv88e6095_g1_set_egress_port, 4119 .watchdog_ops = &mv88e6250_watchdog_ops, 4120 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4121 .pot_clear = mv88e6xxx_g2_pot_clear, 4122 .reset = mv88e6250_g1_reset, 4123 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4124 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4125 .avb_ops = &mv88e6352_avb_ops, 4126 .ptp_ops = &mv88e6250_ptp_ops, 4127 .phylink_validate = mv88e6065_phylink_validate, 4128 }; 4129 4130 static const struct mv88e6xxx_ops mv88e6290_ops = { 4131 /* MV88E6XXX_FAMILY_6390 */ 4132 .setup_errata = mv88e6390_setup_errata, 4133 .irl_init_all = mv88e6390_g2_irl_init_all, 4134 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4135 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4136 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4137 .phy_read = mv88e6xxx_g2_smi_phy_read, 4138 .phy_write = mv88e6xxx_g2_smi_phy_write, 4139 .port_set_link = mv88e6xxx_port_set_link, 4140 .port_set_duplex = mv88e6xxx_port_set_duplex, 4141 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4142 .port_set_speed = mv88e6390_port_set_speed, 4143 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4144 .port_tag_remap = mv88e6390_port_tag_remap, 4145 .port_set_policy = mv88e6352_port_set_policy, 4146 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4147 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4148 .port_set_ether_type = mv88e6351_port_set_ether_type, 4149 .port_pause_limit = mv88e6390_port_pause_limit, 4150 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4151 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4152 .port_link_state = mv88e6352_port_link_state, 4153 .port_get_cmode = mv88e6352_port_get_cmode, 4154 .port_set_cmode = mv88e6390_port_set_cmode, 4155 .port_setup_message_port = mv88e6xxx_setup_message_port, 4156 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4157 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4158 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4159 .stats_get_strings = mv88e6320_stats_get_strings, 4160 .stats_get_stats = mv88e6390_stats_get_stats, 4161 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4162 .set_egress_port = mv88e6390_g1_set_egress_port, 4163 .watchdog_ops = &mv88e6390_watchdog_ops, 4164 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4165 .pot_clear = mv88e6xxx_g2_pot_clear, 4166 .reset = mv88e6352_g1_reset, 4167 .rmu_disable = mv88e6390_g1_rmu_disable, 4168 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4169 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4170 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4171 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4172 .serdes_power = mv88e6390_serdes_power, 4173 .serdes_get_lane = mv88e6390_serdes_get_lane, 4174 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4175 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4176 .serdes_irq_status = mv88e6390_serdes_irq_status, 4177 .serdes_get_strings = mv88e6390_serdes_get_strings, 4178 .serdes_get_stats = mv88e6390_serdes_get_stats, 4179 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4180 .serdes_get_regs = mv88e6390_serdes_get_regs, 4181 .phylink_validate = mv88e6390_phylink_validate, 4182 .gpio_ops = &mv88e6352_gpio_ops, 4183 .avb_ops = &mv88e6390_avb_ops, 4184 .ptp_ops = &mv88e6352_ptp_ops, 4185 .phylink_validate = mv88e6390_phylink_validate, 4186 }; 4187 4188 static const struct mv88e6xxx_ops mv88e6320_ops = { 4189 /* MV88E6XXX_FAMILY_6320 */ 4190 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4191 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4192 .irl_init_all = mv88e6352_g2_irl_init_all, 4193 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4194 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4195 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4196 .phy_read = mv88e6xxx_g2_smi_phy_read, 4197 .phy_write = mv88e6xxx_g2_smi_phy_write, 4198 .port_set_link = mv88e6xxx_port_set_link, 4199 .port_set_duplex = mv88e6xxx_port_set_duplex, 4200 .port_set_speed = mv88e6185_port_set_speed, 4201 .port_tag_remap = mv88e6095_port_tag_remap, 4202 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4203 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4204 .port_set_ether_type = mv88e6351_port_set_ether_type, 4205 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4206 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4207 .port_pause_limit = mv88e6097_port_pause_limit, 4208 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4209 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4210 .port_link_state = mv88e6352_port_link_state, 4211 .port_get_cmode = mv88e6352_port_get_cmode, 4212 .port_setup_message_port = mv88e6xxx_setup_message_port, 4213 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4214 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4215 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4216 .stats_get_strings = mv88e6320_stats_get_strings, 4217 .stats_get_stats = mv88e6320_stats_get_stats, 4218 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4219 .set_egress_port = mv88e6095_g1_set_egress_port, 4220 .watchdog_ops = &mv88e6390_watchdog_ops, 4221 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4222 .pot_clear = mv88e6xxx_g2_pot_clear, 4223 .reset = mv88e6352_g1_reset, 4224 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4225 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4226 .gpio_ops = &mv88e6352_gpio_ops, 4227 .avb_ops = &mv88e6352_avb_ops, 4228 .ptp_ops = &mv88e6352_ptp_ops, 4229 .phylink_validate = mv88e6185_phylink_validate, 4230 }; 4231 4232 static const struct mv88e6xxx_ops mv88e6321_ops = { 4233 /* MV88E6XXX_FAMILY_6320 */ 4234 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4235 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4236 .irl_init_all = mv88e6352_g2_irl_init_all, 4237 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4238 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4240 .phy_read = mv88e6xxx_g2_smi_phy_read, 4241 .phy_write = mv88e6xxx_g2_smi_phy_write, 4242 .port_set_link = mv88e6xxx_port_set_link, 4243 .port_set_duplex = mv88e6xxx_port_set_duplex, 4244 .port_set_speed = mv88e6185_port_set_speed, 4245 .port_tag_remap = mv88e6095_port_tag_remap, 4246 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4247 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4248 .port_set_ether_type = mv88e6351_port_set_ether_type, 4249 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4250 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4251 .port_pause_limit = mv88e6097_port_pause_limit, 4252 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4253 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4254 .port_link_state = mv88e6352_port_link_state, 4255 .port_get_cmode = mv88e6352_port_get_cmode, 4256 .port_setup_message_port = mv88e6xxx_setup_message_port, 4257 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4258 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4259 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4260 .stats_get_strings = mv88e6320_stats_get_strings, 4261 .stats_get_stats = mv88e6320_stats_get_stats, 4262 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4263 .set_egress_port = mv88e6095_g1_set_egress_port, 4264 .watchdog_ops = &mv88e6390_watchdog_ops, 4265 .reset = mv88e6352_g1_reset, 4266 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4267 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4268 .gpio_ops = &mv88e6352_gpio_ops, 4269 .avb_ops = &mv88e6352_avb_ops, 4270 .ptp_ops = &mv88e6352_ptp_ops, 4271 .phylink_validate = mv88e6185_phylink_validate, 4272 }; 4273 4274 static const struct mv88e6xxx_ops mv88e6341_ops = { 4275 /* MV88E6XXX_FAMILY_6341 */ 4276 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4277 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4278 .irl_init_all = mv88e6352_g2_irl_init_all, 4279 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4280 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4282 .phy_read = mv88e6xxx_g2_smi_phy_read, 4283 .phy_write = mv88e6xxx_g2_smi_phy_write, 4284 .port_set_link = mv88e6xxx_port_set_link, 4285 .port_set_duplex = mv88e6xxx_port_set_duplex, 4286 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4287 .port_set_speed = mv88e6341_port_set_speed, 4288 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4289 .port_tag_remap = mv88e6095_port_tag_remap, 4290 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4291 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4292 .port_set_ether_type = mv88e6351_port_set_ether_type, 4293 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4294 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4295 .port_pause_limit = mv88e6097_port_pause_limit, 4296 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4297 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4298 .port_link_state = mv88e6352_port_link_state, 4299 .port_get_cmode = mv88e6352_port_get_cmode, 4300 .port_set_cmode = mv88e6341_port_set_cmode, 4301 .port_setup_message_port = mv88e6xxx_setup_message_port, 4302 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4303 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4304 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4305 .stats_get_strings = mv88e6320_stats_get_strings, 4306 .stats_get_stats = mv88e6390_stats_get_stats, 4307 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4308 .set_egress_port = mv88e6390_g1_set_egress_port, 4309 .watchdog_ops = &mv88e6390_watchdog_ops, 4310 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4311 .pot_clear = mv88e6xxx_g2_pot_clear, 4312 .reset = mv88e6352_g1_reset, 4313 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4314 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4315 .serdes_power = mv88e6390_serdes_power, 4316 .serdes_get_lane = mv88e6341_serdes_get_lane, 4317 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4318 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4319 .serdes_irq_status = mv88e6390_serdes_irq_status, 4320 .gpio_ops = &mv88e6352_gpio_ops, 4321 .avb_ops = &mv88e6390_avb_ops, 4322 .ptp_ops = &mv88e6352_ptp_ops, 4323 .phylink_validate = mv88e6341_phylink_validate, 4324 }; 4325 4326 static const struct mv88e6xxx_ops mv88e6350_ops = { 4327 /* MV88E6XXX_FAMILY_6351 */ 4328 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4329 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4330 .irl_init_all = mv88e6352_g2_irl_init_all, 4331 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4332 .phy_read = mv88e6xxx_g2_smi_phy_read, 4333 .phy_write = mv88e6xxx_g2_smi_phy_write, 4334 .port_set_link = mv88e6xxx_port_set_link, 4335 .port_set_duplex = mv88e6xxx_port_set_duplex, 4336 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4337 .port_set_speed = mv88e6185_port_set_speed, 4338 .port_tag_remap = mv88e6095_port_tag_remap, 4339 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4340 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4341 .port_set_ether_type = mv88e6351_port_set_ether_type, 4342 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4343 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4344 .port_pause_limit = mv88e6097_port_pause_limit, 4345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4347 .port_link_state = mv88e6352_port_link_state, 4348 .port_get_cmode = mv88e6352_port_get_cmode, 4349 .port_setup_message_port = mv88e6xxx_setup_message_port, 4350 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4351 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4352 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4353 .stats_get_strings = mv88e6095_stats_get_strings, 4354 .stats_get_stats = mv88e6095_stats_get_stats, 4355 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4356 .set_egress_port = mv88e6095_g1_set_egress_port, 4357 .watchdog_ops = &mv88e6097_watchdog_ops, 4358 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4359 .pot_clear = mv88e6xxx_g2_pot_clear, 4360 .reset = mv88e6352_g1_reset, 4361 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4362 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4363 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4364 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4365 .phylink_validate = mv88e6185_phylink_validate, 4366 }; 4367 4368 static const struct mv88e6xxx_ops mv88e6351_ops = { 4369 /* MV88E6XXX_FAMILY_6351 */ 4370 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4371 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4372 .irl_init_all = mv88e6352_g2_irl_init_all, 4373 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4374 .phy_read = mv88e6xxx_g2_smi_phy_read, 4375 .phy_write = mv88e6xxx_g2_smi_phy_write, 4376 .port_set_link = mv88e6xxx_port_set_link, 4377 .port_set_duplex = mv88e6xxx_port_set_duplex, 4378 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4379 .port_set_speed = mv88e6185_port_set_speed, 4380 .port_tag_remap = mv88e6095_port_tag_remap, 4381 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4382 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4383 .port_set_ether_type = mv88e6351_port_set_ether_type, 4384 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4385 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4386 .port_pause_limit = mv88e6097_port_pause_limit, 4387 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4388 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4389 .port_link_state = mv88e6352_port_link_state, 4390 .port_get_cmode = mv88e6352_port_get_cmode, 4391 .port_setup_message_port = mv88e6xxx_setup_message_port, 4392 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4393 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4394 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4395 .stats_get_strings = mv88e6095_stats_get_strings, 4396 .stats_get_stats = mv88e6095_stats_get_stats, 4397 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4398 .set_egress_port = mv88e6095_g1_set_egress_port, 4399 .watchdog_ops = &mv88e6097_watchdog_ops, 4400 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4401 .pot_clear = mv88e6xxx_g2_pot_clear, 4402 .reset = mv88e6352_g1_reset, 4403 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4404 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4405 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4406 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4407 .avb_ops = &mv88e6352_avb_ops, 4408 .ptp_ops = &mv88e6352_ptp_ops, 4409 .phylink_validate = mv88e6185_phylink_validate, 4410 }; 4411 4412 static const struct mv88e6xxx_ops mv88e6352_ops = { 4413 /* MV88E6XXX_FAMILY_6352 */ 4414 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4415 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4416 .irl_init_all = mv88e6352_g2_irl_init_all, 4417 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4418 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4419 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4420 .phy_read = mv88e6xxx_g2_smi_phy_read, 4421 .phy_write = mv88e6xxx_g2_smi_phy_write, 4422 .port_set_link = mv88e6xxx_port_set_link, 4423 .port_set_duplex = mv88e6xxx_port_set_duplex, 4424 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4425 .port_set_speed = mv88e6352_port_set_speed, 4426 .port_tag_remap = mv88e6095_port_tag_remap, 4427 .port_set_policy = mv88e6352_port_set_policy, 4428 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4429 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4430 .port_set_ether_type = mv88e6351_port_set_ether_type, 4431 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4432 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4433 .port_pause_limit = mv88e6097_port_pause_limit, 4434 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4435 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4436 .port_link_state = mv88e6352_port_link_state, 4437 .port_get_cmode = mv88e6352_port_get_cmode, 4438 .port_setup_message_port = mv88e6xxx_setup_message_port, 4439 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4440 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4441 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4442 .stats_get_strings = mv88e6095_stats_get_strings, 4443 .stats_get_stats = mv88e6095_stats_get_stats, 4444 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4445 .set_egress_port = mv88e6095_g1_set_egress_port, 4446 .watchdog_ops = &mv88e6097_watchdog_ops, 4447 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4448 .pot_clear = mv88e6xxx_g2_pot_clear, 4449 .reset = mv88e6352_g1_reset, 4450 .rmu_disable = mv88e6352_g1_rmu_disable, 4451 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4452 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4453 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4454 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4455 .serdes_get_lane = mv88e6352_serdes_get_lane, 4456 .serdes_power = mv88e6352_serdes_power, 4457 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4458 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4459 .serdes_irq_status = mv88e6352_serdes_irq_status, 4460 .gpio_ops = &mv88e6352_gpio_ops, 4461 .avb_ops = &mv88e6352_avb_ops, 4462 .ptp_ops = &mv88e6352_ptp_ops, 4463 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4464 .serdes_get_strings = mv88e6352_serdes_get_strings, 4465 .serdes_get_stats = mv88e6352_serdes_get_stats, 4466 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4467 .serdes_get_regs = mv88e6352_serdes_get_regs, 4468 .phylink_validate = mv88e6352_phylink_validate, 4469 }; 4470 4471 static const struct mv88e6xxx_ops mv88e6390_ops = { 4472 /* MV88E6XXX_FAMILY_6390 */ 4473 .setup_errata = mv88e6390_setup_errata, 4474 .irl_init_all = mv88e6390_g2_irl_init_all, 4475 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4476 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4477 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4478 .phy_read = mv88e6xxx_g2_smi_phy_read, 4479 .phy_write = mv88e6xxx_g2_smi_phy_write, 4480 .port_set_link = mv88e6xxx_port_set_link, 4481 .port_set_duplex = mv88e6xxx_port_set_duplex, 4482 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4483 .port_set_speed = mv88e6390_port_set_speed, 4484 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4485 .port_tag_remap = mv88e6390_port_tag_remap, 4486 .port_set_policy = mv88e6352_port_set_policy, 4487 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4488 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4489 .port_set_ether_type = mv88e6351_port_set_ether_type, 4490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4492 .port_pause_limit = mv88e6390_port_pause_limit, 4493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4495 .port_link_state = mv88e6352_port_link_state, 4496 .port_get_cmode = mv88e6352_port_get_cmode, 4497 .port_set_cmode = mv88e6390_port_set_cmode, 4498 .port_setup_message_port = mv88e6xxx_setup_message_port, 4499 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4500 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4501 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4502 .stats_get_strings = mv88e6320_stats_get_strings, 4503 .stats_get_stats = mv88e6390_stats_get_stats, 4504 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4505 .set_egress_port = mv88e6390_g1_set_egress_port, 4506 .watchdog_ops = &mv88e6390_watchdog_ops, 4507 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4508 .pot_clear = mv88e6xxx_g2_pot_clear, 4509 .reset = mv88e6352_g1_reset, 4510 .rmu_disable = mv88e6390_g1_rmu_disable, 4511 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4512 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4513 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4514 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4515 .serdes_power = mv88e6390_serdes_power, 4516 .serdes_get_lane = mv88e6390_serdes_get_lane, 4517 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4518 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4519 .serdes_irq_status = mv88e6390_serdes_irq_status, 4520 .gpio_ops = &mv88e6352_gpio_ops, 4521 .avb_ops = &mv88e6390_avb_ops, 4522 .ptp_ops = &mv88e6352_ptp_ops, 4523 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4524 .serdes_get_strings = mv88e6390_serdes_get_strings, 4525 .serdes_get_stats = mv88e6390_serdes_get_stats, 4526 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4527 .serdes_get_regs = mv88e6390_serdes_get_regs, 4528 .phylink_validate = mv88e6390_phylink_validate, 4529 }; 4530 4531 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4532 /* MV88E6XXX_FAMILY_6390 */ 4533 .setup_errata = mv88e6390_setup_errata, 4534 .irl_init_all = mv88e6390_g2_irl_init_all, 4535 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4536 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4537 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4538 .phy_read = mv88e6xxx_g2_smi_phy_read, 4539 .phy_write = mv88e6xxx_g2_smi_phy_write, 4540 .port_set_link = mv88e6xxx_port_set_link, 4541 .port_set_duplex = mv88e6xxx_port_set_duplex, 4542 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4543 .port_set_speed = mv88e6390x_port_set_speed, 4544 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4545 .port_tag_remap = mv88e6390_port_tag_remap, 4546 .port_set_policy = mv88e6352_port_set_policy, 4547 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4548 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4549 .port_set_ether_type = mv88e6351_port_set_ether_type, 4550 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4552 .port_pause_limit = mv88e6390_port_pause_limit, 4553 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4554 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4555 .port_link_state = mv88e6352_port_link_state, 4556 .port_get_cmode = mv88e6352_port_get_cmode, 4557 .port_set_cmode = mv88e6390x_port_set_cmode, 4558 .port_setup_message_port = mv88e6xxx_setup_message_port, 4559 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4560 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4561 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4562 .stats_get_strings = mv88e6320_stats_get_strings, 4563 .stats_get_stats = mv88e6390_stats_get_stats, 4564 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4565 .set_egress_port = mv88e6390_g1_set_egress_port, 4566 .watchdog_ops = &mv88e6390_watchdog_ops, 4567 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4568 .pot_clear = mv88e6xxx_g2_pot_clear, 4569 .reset = mv88e6352_g1_reset, 4570 .rmu_disable = mv88e6390_g1_rmu_disable, 4571 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4572 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4573 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4574 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4575 .serdes_power = mv88e6390_serdes_power, 4576 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4577 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4578 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4579 .serdes_irq_status = mv88e6390_serdes_irq_status, 4580 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4581 .serdes_get_strings = mv88e6390_serdes_get_strings, 4582 .serdes_get_stats = mv88e6390_serdes_get_stats, 4583 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4584 .serdes_get_regs = mv88e6390_serdes_get_regs, 4585 .gpio_ops = &mv88e6352_gpio_ops, 4586 .avb_ops = &mv88e6390_avb_ops, 4587 .ptp_ops = &mv88e6352_ptp_ops, 4588 .phylink_validate = mv88e6390x_phylink_validate, 4589 }; 4590 4591 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4592 [MV88E6085] = { 4593 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4594 .family = MV88E6XXX_FAMILY_6097, 4595 .name = "Marvell 88E6085", 4596 .num_databases = 4096, 4597 .num_macs = 8192, 4598 .num_ports = 10, 4599 .num_internal_phys = 5, 4600 .max_vid = 4095, 4601 .port_base_addr = 0x10, 4602 .phy_base_addr = 0x0, 4603 .global1_addr = 0x1b, 4604 .global2_addr = 0x1c, 4605 .age_time_coeff = 15000, 4606 .g1_irqs = 8, 4607 .g2_irqs = 10, 4608 .atu_move_port_mask = 0xf, 4609 .pvt = true, 4610 .multi_chip = true, 4611 .tag_protocol = DSA_TAG_PROTO_DSA, 4612 .ops = &mv88e6085_ops, 4613 }, 4614 4615 [MV88E6095] = { 4616 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4617 .family = MV88E6XXX_FAMILY_6095, 4618 .name = "Marvell 88E6095/88E6095F", 4619 .num_databases = 256, 4620 .num_macs = 8192, 4621 .num_ports = 11, 4622 .num_internal_phys = 0, 4623 .max_vid = 4095, 4624 .port_base_addr = 0x10, 4625 .phy_base_addr = 0x0, 4626 .global1_addr = 0x1b, 4627 .global2_addr = 0x1c, 4628 .age_time_coeff = 15000, 4629 .g1_irqs = 8, 4630 .atu_move_port_mask = 0xf, 4631 .multi_chip = true, 4632 .tag_protocol = DSA_TAG_PROTO_DSA, 4633 .ops = &mv88e6095_ops, 4634 }, 4635 4636 [MV88E6097] = { 4637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4638 .family = MV88E6XXX_FAMILY_6097, 4639 .name = "Marvell 88E6097/88E6097F", 4640 .num_databases = 4096, 4641 .num_macs = 8192, 4642 .num_ports = 11, 4643 .num_internal_phys = 8, 4644 .max_vid = 4095, 4645 .port_base_addr = 0x10, 4646 .phy_base_addr = 0x0, 4647 .global1_addr = 0x1b, 4648 .global2_addr = 0x1c, 4649 .age_time_coeff = 15000, 4650 .g1_irqs = 8, 4651 .g2_irqs = 10, 4652 .atu_move_port_mask = 0xf, 4653 .pvt = true, 4654 .multi_chip = true, 4655 .tag_protocol = DSA_TAG_PROTO_EDSA, 4656 .ops = &mv88e6097_ops, 4657 }, 4658 4659 [MV88E6123] = { 4660 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4661 .family = MV88E6XXX_FAMILY_6165, 4662 .name = "Marvell 88E6123", 4663 .num_databases = 4096, 4664 .num_macs = 1024, 4665 .num_ports = 3, 4666 .num_internal_phys = 5, 4667 .max_vid = 4095, 4668 .port_base_addr = 0x10, 4669 .phy_base_addr = 0x0, 4670 .global1_addr = 0x1b, 4671 .global2_addr = 0x1c, 4672 .age_time_coeff = 15000, 4673 .g1_irqs = 9, 4674 .g2_irqs = 10, 4675 .atu_move_port_mask = 0xf, 4676 .pvt = true, 4677 .multi_chip = true, 4678 .tag_protocol = DSA_TAG_PROTO_EDSA, 4679 .ops = &mv88e6123_ops, 4680 }, 4681 4682 [MV88E6131] = { 4683 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4684 .family = MV88E6XXX_FAMILY_6185, 4685 .name = "Marvell 88E6131", 4686 .num_databases = 256, 4687 .num_macs = 8192, 4688 .num_ports = 8, 4689 .num_internal_phys = 0, 4690 .max_vid = 4095, 4691 .port_base_addr = 0x10, 4692 .phy_base_addr = 0x0, 4693 .global1_addr = 0x1b, 4694 .global2_addr = 0x1c, 4695 .age_time_coeff = 15000, 4696 .g1_irqs = 9, 4697 .atu_move_port_mask = 0xf, 4698 .multi_chip = true, 4699 .tag_protocol = DSA_TAG_PROTO_DSA, 4700 .ops = &mv88e6131_ops, 4701 }, 4702 4703 [MV88E6141] = { 4704 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4705 .family = MV88E6XXX_FAMILY_6341, 4706 .name = "Marvell 88E6141", 4707 .num_databases = 4096, 4708 .num_macs = 2048, 4709 .num_ports = 6, 4710 .num_internal_phys = 5, 4711 .num_gpio = 11, 4712 .max_vid = 4095, 4713 .port_base_addr = 0x10, 4714 .phy_base_addr = 0x10, 4715 .global1_addr = 0x1b, 4716 .global2_addr = 0x1c, 4717 .age_time_coeff = 3750, 4718 .atu_move_port_mask = 0x1f, 4719 .g1_irqs = 9, 4720 .g2_irqs = 10, 4721 .pvt = true, 4722 .multi_chip = true, 4723 .tag_protocol = DSA_TAG_PROTO_EDSA, 4724 .ops = &mv88e6141_ops, 4725 }, 4726 4727 [MV88E6161] = { 4728 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4729 .family = MV88E6XXX_FAMILY_6165, 4730 .name = "Marvell 88E6161", 4731 .num_databases = 4096, 4732 .num_macs = 1024, 4733 .num_ports = 6, 4734 .num_internal_phys = 5, 4735 .max_vid = 4095, 4736 .port_base_addr = 0x10, 4737 .phy_base_addr = 0x0, 4738 .global1_addr = 0x1b, 4739 .global2_addr = 0x1c, 4740 .age_time_coeff = 15000, 4741 .g1_irqs = 9, 4742 .g2_irqs = 10, 4743 .atu_move_port_mask = 0xf, 4744 .pvt = true, 4745 .multi_chip = true, 4746 .tag_protocol = DSA_TAG_PROTO_EDSA, 4747 .ptp_support = true, 4748 .ops = &mv88e6161_ops, 4749 }, 4750 4751 [MV88E6165] = { 4752 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4753 .family = MV88E6XXX_FAMILY_6165, 4754 .name = "Marvell 88E6165", 4755 .num_databases = 4096, 4756 .num_macs = 8192, 4757 .num_ports = 6, 4758 .num_internal_phys = 0, 4759 .max_vid = 4095, 4760 .port_base_addr = 0x10, 4761 .phy_base_addr = 0x0, 4762 .global1_addr = 0x1b, 4763 .global2_addr = 0x1c, 4764 .age_time_coeff = 15000, 4765 .g1_irqs = 9, 4766 .g2_irqs = 10, 4767 .atu_move_port_mask = 0xf, 4768 .pvt = true, 4769 .multi_chip = true, 4770 .tag_protocol = DSA_TAG_PROTO_DSA, 4771 .ptp_support = true, 4772 .ops = &mv88e6165_ops, 4773 }, 4774 4775 [MV88E6171] = { 4776 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4777 .family = MV88E6XXX_FAMILY_6351, 4778 .name = "Marvell 88E6171", 4779 .num_databases = 4096, 4780 .num_macs = 8192, 4781 .num_ports = 7, 4782 .num_internal_phys = 5, 4783 .max_vid = 4095, 4784 .port_base_addr = 0x10, 4785 .phy_base_addr = 0x0, 4786 .global1_addr = 0x1b, 4787 .global2_addr = 0x1c, 4788 .age_time_coeff = 15000, 4789 .g1_irqs = 9, 4790 .g2_irqs = 10, 4791 .atu_move_port_mask = 0xf, 4792 .pvt = true, 4793 .multi_chip = true, 4794 .tag_protocol = DSA_TAG_PROTO_EDSA, 4795 .ops = &mv88e6171_ops, 4796 }, 4797 4798 [MV88E6172] = { 4799 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4800 .family = MV88E6XXX_FAMILY_6352, 4801 .name = "Marvell 88E6172", 4802 .num_databases = 4096, 4803 .num_macs = 8192, 4804 .num_ports = 7, 4805 .num_internal_phys = 5, 4806 .num_gpio = 15, 4807 .max_vid = 4095, 4808 .port_base_addr = 0x10, 4809 .phy_base_addr = 0x0, 4810 .global1_addr = 0x1b, 4811 .global2_addr = 0x1c, 4812 .age_time_coeff = 15000, 4813 .g1_irqs = 9, 4814 .g2_irqs = 10, 4815 .atu_move_port_mask = 0xf, 4816 .pvt = true, 4817 .multi_chip = true, 4818 .tag_protocol = DSA_TAG_PROTO_EDSA, 4819 .ops = &mv88e6172_ops, 4820 }, 4821 4822 [MV88E6175] = { 4823 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4824 .family = MV88E6XXX_FAMILY_6351, 4825 .name = "Marvell 88E6175", 4826 .num_databases = 4096, 4827 .num_macs = 8192, 4828 .num_ports = 7, 4829 .num_internal_phys = 5, 4830 .max_vid = 4095, 4831 .port_base_addr = 0x10, 4832 .phy_base_addr = 0x0, 4833 .global1_addr = 0x1b, 4834 .global2_addr = 0x1c, 4835 .age_time_coeff = 15000, 4836 .g1_irqs = 9, 4837 .g2_irqs = 10, 4838 .atu_move_port_mask = 0xf, 4839 .pvt = true, 4840 .multi_chip = true, 4841 .tag_protocol = DSA_TAG_PROTO_EDSA, 4842 .ops = &mv88e6175_ops, 4843 }, 4844 4845 [MV88E6176] = { 4846 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4847 .family = MV88E6XXX_FAMILY_6352, 4848 .name = "Marvell 88E6176", 4849 .num_databases = 4096, 4850 .num_macs = 8192, 4851 .num_ports = 7, 4852 .num_internal_phys = 5, 4853 .num_gpio = 15, 4854 .max_vid = 4095, 4855 .port_base_addr = 0x10, 4856 .phy_base_addr = 0x0, 4857 .global1_addr = 0x1b, 4858 .global2_addr = 0x1c, 4859 .age_time_coeff = 15000, 4860 .g1_irqs = 9, 4861 .g2_irqs = 10, 4862 .atu_move_port_mask = 0xf, 4863 .pvt = true, 4864 .multi_chip = true, 4865 .tag_protocol = DSA_TAG_PROTO_EDSA, 4866 .ops = &mv88e6176_ops, 4867 }, 4868 4869 [MV88E6185] = { 4870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4871 .family = MV88E6XXX_FAMILY_6185, 4872 .name = "Marvell 88E6185", 4873 .num_databases = 256, 4874 .num_macs = 8192, 4875 .num_ports = 10, 4876 .num_internal_phys = 0, 4877 .max_vid = 4095, 4878 .port_base_addr = 0x10, 4879 .phy_base_addr = 0x0, 4880 .global1_addr = 0x1b, 4881 .global2_addr = 0x1c, 4882 .age_time_coeff = 15000, 4883 .g1_irqs = 8, 4884 .atu_move_port_mask = 0xf, 4885 .multi_chip = true, 4886 .tag_protocol = DSA_TAG_PROTO_EDSA, 4887 .ops = &mv88e6185_ops, 4888 }, 4889 4890 [MV88E6190] = { 4891 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4892 .family = MV88E6XXX_FAMILY_6390, 4893 .name = "Marvell 88E6190", 4894 .num_databases = 4096, 4895 .num_macs = 16384, 4896 .num_ports = 11, /* 10 + Z80 */ 4897 .num_internal_phys = 9, 4898 .num_gpio = 16, 4899 .max_vid = 8191, 4900 .port_base_addr = 0x0, 4901 .phy_base_addr = 0x0, 4902 .global1_addr = 0x1b, 4903 .global2_addr = 0x1c, 4904 .tag_protocol = DSA_TAG_PROTO_DSA, 4905 .age_time_coeff = 3750, 4906 .g1_irqs = 9, 4907 .g2_irqs = 14, 4908 .pvt = true, 4909 .multi_chip = true, 4910 .atu_move_port_mask = 0x1f, 4911 .ops = &mv88e6190_ops, 4912 }, 4913 4914 [MV88E6190X] = { 4915 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4916 .family = MV88E6XXX_FAMILY_6390, 4917 .name = "Marvell 88E6190X", 4918 .num_databases = 4096, 4919 .num_macs = 16384, 4920 .num_ports = 11, /* 10 + Z80 */ 4921 .num_internal_phys = 9, 4922 .num_gpio = 16, 4923 .max_vid = 8191, 4924 .port_base_addr = 0x0, 4925 .phy_base_addr = 0x0, 4926 .global1_addr = 0x1b, 4927 .global2_addr = 0x1c, 4928 .age_time_coeff = 3750, 4929 .g1_irqs = 9, 4930 .g2_irqs = 14, 4931 .atu_move_port_mask = 0x1f, 4932 .pvt = true, 4933 .multi_chip = true, 4934 .tag_protocol = DSA_TAG_PROTO_DSA, 4935 .ops = &mv88e6190x_ops, 4936 }, 4937 4938 [MV88E6191] = { 4939 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4940 .family = MV88E6XXX_FAMILY_6390, 4941 .name = "Marvell 88E6191", 4942 .num_databases = 4096, 4943 .num_macs = 16384, 4944 .num_ports = 11, /* 10 + Z80 */ 4945 .num_internal_phys = 9, 4946 .max_vid = 8191, 4947 .port_base_addr = 0x0, 4948 .phy_base_addr = 0x0, 4949 .global1_addr = 0x1b, 4950 .global2_addr = 0x1c, 4951 .age_time_coeff = 3750, 4952 .g1_irqs = 9, 4953 .g2_irqs = 14, 4954 .atu_move_port_mask = 0x1f, 4955 .pvt = true, 4956 .multi_chip = true, 4957 .tag_protocol = DSA_TAG_PROTO_DSA, 4958 .ptp_support = true, 4959 .ops = &mv88e6191_ops, 4960 }, 4961 4962 [MV88E6220] = { 4963 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4964 .family = MV88E6XXX_FAMILY_6250, 4965 .name = "Marvell 88E6220", 4966 .num_databases = 64, 4967 4968 /* Ports 2-4 are not routed to pins 4969 * => usable ports 0, 1, 5, 6 4970 */ 4971 .num_ports = 7, 4972 .num_internal_phys = 2, 4973 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4974 .max_vid = 4095, 4975 .port_base_addr = 0x08, 4976 .phy_base_addr = 0x00, 4977 .global1_addr = 0x0f, 4978 .global2_addr = 0x07, 4979 .age_time_coeff = 15000, 4980 .g1_irqs = 9, 4981 .g2_irqs = 10, 4982 .atu_move_port_mask = 0xf, 4983 .dual_chip = true, 4984 .tag_protocol = DSA_TAG_PROTO_DSA, 4985 .ptp_support = true, 4986 .ops = &mv88e6250_ops, 4987 }, 4988 4989 [MV88E6240] = { 4990 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4991 .family = MV88E6XXX_FAMILY_6352, 4992 .name = "Marvell 88E6240", 4993 .num_databases = 4096, 4994 .num_macs = 8192, 4995 .num_ports = 7, 4996 .num_internal_phys = 5, 4997 .num_gpio = 15, 4998 .max_vid = 4095, 4999 .port_base_addr = 0x10, 5000 .phy_base_addr = 0x0, 5001 .global1_addr = 0x1b, 5002 .global2_addr = 0x1c, 5003 .age_time_coeff = 15000, 5004 .g1_irqs = 9, 5005 .g2_irqs = 10, 5006 .atu_move_port_mask = 0xf, 5007 .pvt = true, 5008 .multi_chip = true, 5009 .tag_protocol = DSA_TAG_PROTO_EDSA, 5010 .ptp_support = true, 5011 .ops = &mv88e6240_ops, 5012 }, 5013 5014 [MV88E6250] = { 5015 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5016 .family = MV88E6XXX_FAMILY_6250, 5017 .name = "Marvell 88E6250", 5018 .num_databases = 64, 5019 .num_ports = 7, 5020 .num_internal_phys = 5, 5021 .max_vid = 4095, 5022 .port_base_addr = 0x08, 5023 .phy_base_addr = 0x00, 5024 .global1_addr = 0x0f, 5025 .global2_addr = 0x07, 5026 .age_time_coeff = 15000, 5027 .g1_irqs = 9, 5028 .g2_irqs = 10, 5029 .atu_move_port_mask = 0xf, 5030 .dual_chip = true, 5031 .tag_protocol = DSA_TAG_PROTO_DSA, 5032 .ptp_support = true, 5033 .ops = &mv88e6250_ops, 5034 }, 5035 5036 [MV88E6290] = { 5037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5038 .family = MV88E6XXX_FAMILY_6390, 5039 .name = "Marvell 88E6290", 5040 .num_databases = 4096, 5041 .num_ports = 11, /* 10 + Z80 */ 5042 .num_internal_phys = 9, 5043 .num_gpio = 16, 5044 .max_vid = 8191, 5045 .port_base_addr = 0x0, 5046 .phy_base_addr = 0x0, 5047 .global1_addr = 0x1b, 5048 .global2_addr = 0x1c, 5049 .age_time_coeff = 3750, 5050 .g1_irqs = 9, 5051 .g2_irqs = 14, 5052 .atu_move_port_mask = 0x1f, 5053 .pvt = true, 5054 .multi_chip = true, 5055 .tag_protocol = DSA_TAG_PROTO_DSA, 5056 .ptp_support = true, 5057 .ops = &mv88e6290_ops, 5058 }, 5059 5060 [MV88E6320] = { 5061 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5062 .family = MV88E6XXX_FAMILY_6320, 5063 .name = "Marvell 88E6320", 5064 .num_databases = 4096, 5065 .num_macs = 8192, 5066 .num_ports = 7, 5067 .num_internal_phys = 5, 5068 .num_gpio = 15, 5069 .max_vid = 4095, 5070 .port_base_addr = 0x10, 5071 .phy_base_addr = 0x0, 5072 .global1_addr = 0x1b, 5073 .global2_addr = 0x1c, 5074 .age_time_coeff = 15000, 5075 .g1_irqs = 8, 5076 .g2_irqs = 10, 5077 .atu_move_port_mask = 0xf, 5078 .pvt = true, 5079 .multi_chip = true, 5080 .tag_protocol = DSA_TAG_PROTO_EDSA, 5081 .ptp_support = true, 5082 .ops = &mv88e6320_ops, 5083 }, 5084 5085 [MV88E6321] = { 5086 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5087 .family = MV88E6XXX_FAMILY_6320, 5088 .name = "Marvell 88E6321", 5089 .num_databases = 4096, 5090 .num_macs = 8192, 5091 .num_ports = 7, 5092 .num_internal_phys = 5, 5093 .num_gpio = 15, 5094 .max_vid = 4095, 5095 .port_base_addr = 0x10, 5096 .phy_base_addr = 0x0, 5097 .global1_addr = 0x1b, 5098 .global2_addr = 0x1c, 5099 .age_time_coeff = 15000, 5100 .g1_irqs = 8, 5101 .g2_irqs = 10, 5102 .atu_move_port_mask = 0xf, 5103 .multi_chip = true, 5104 .tag_protocol = DSA_TAG_PROTO_EDSA, 5105 .ptp_support = true, 5106 .ops = &mv88e6321_ops, 5107 }, 5108 5109 [MV88E6341] = { 5110 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5111 .family = MV88E6XXX_FAMILY_6341, 5112 .name = "Marvell 88E6341", 5113 .num_databases = 4096, 5114 .num_macs = 2048, 5115 .num_internal_phys = 5, 5116 .num_ports = 6, 5117 .num_gpio = 11, 5118 .max_vid = 4095, 5119 .port_base_addr = 0x10, 5120 .phy_base_addr = 0x10, 5121 .global1_addr = 0x1b, 5122 .global2_addr = 0x1c, 5123 .age_time_coeff = 3750, 5124 .atu_move_port_mask = 0x1f, 5125 .g1_irqs = 9, 5126 .g2_irqs = 10, 5127 .pvt = true, 5128 .multi_chip = true, 5129 .tag_protocol = DSA_TAG_PROTO_EDSA, 5130 .ptp_support = true, 5131 .ops = &mv88e6341_ops, 5132 }, 5133 5134 [MV88E6350] = { 5135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5136 .family = MV88E6XXX_FAMILY_6351, 5137 .name = "Marvell 88E6350", 5138 .num_databases = 4096, 5139 .num_macs = 8192, 5140 .num_ports = 7, 5141 .num_internal_phys = 5, 5142 .max_vid = 4095, 5143 .port_base_addr = 0x10, 5144 .phy_base_addr = 0x0, 5145 .global1_addr = 0x1b, 5146 .global2_addr = 0x1c, 5147 .age_time_coeff = 15000, 5148 .g1_irqs = 9, 5149 .g2_irqs = 10, 5150 .atu_move_port_mask = 0xf, 5151 .pvt = true, 5152 .multi_chip = true, 5153 .tag_protocol = DSA_TAG_PROTO_EDSA, 5154 .ops = &mv88e6350_ops, 5155 }, 5156 5157 [MV88E6351] = { 5158 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5159 .family = MV88E6XXX_FAMILY_6351, 5160 .name = "Marvell 88E6351", 5161 .num_databases = 4096, 5162 .num_macs = 8192, 5163 .num_ports = 7, 5164 .num_internal_phys = 5, 5165 .max_vid = 4095, 5166 .port_base_addr = 0x10, 5167 .phy_base_addr = 0x0, 5168 .global1_addr = 0x1b, 5169 .global2_addr = 0x1c, 5170 .age_time_coeff = 15000, 5171 .g1_irqs = 9, 5172 .g2_irqs = 10, 5173 .atu_move_port_mask = 0xf, 5174 .pvt = true, 5175 .multi_chip = true, 5176 .tag_protocol = DSA_TAG_PROTO_EDSA, 5177 .ops = &mv88e6351_ops, 5178 }, 5179 5180 [MV88E6352] = { 5181 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5182 .family = MV88E6XXX_FAMILY_6352, 5183 .name = "Marvell 88E6352", 5184 .num_databases = 4096, 5185 .num_macs = 8192, 5186 .num_ports = 7, 5187 .num_internal_phys = 5, 5188 .num_gpio = 15, 5189 .max_vid = 4095, 5190 .port_base_addr = 0x10, 5191 .phy_base_addr = 0x0, 5192 .global1_addr = 0x1b, 5193 .global2_addr = 0x1c, 5194 .age_time_coeff = 15000, 5195 .g1_irqs = 9, 5196 .g2_irqs = 10, 5197 .atu_move_port_mask = 0xf, 5198 .pvt = true, 5199 .multi_chip = true, 5200 .tag_protocol = DSA_TAG_PROTO_EDSA, 5201 .ptp_support = true, 5202 .ops = &mv88e6352_ops, 5203 }, 5204 [MV88E6390] = { 5205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5206 .family = MV88E6XXX_FAMILY_6390, 5207 .name = "Marvell 88E6390", 5208 .num_databases = 4096, 5209 .num_macs = 16384, 5210 .num_ports = 11, /* 10 + Z80 */ 5211 .num_internal_phys = 9, 5212 .num_gpio = 16, 5213 .max_vid = 8191, 5214 .port_base_addr = 0x0, 5215 .phy_base_addr = 0x0, 5216 .global1_addr = 0x1b, 5217 .global2_addr = 0x1c, 5218 .age_time_coeff = 3750, 5219 .g1_irqs = 9, 5220 .g2_irqs = 14, 5221 .atu_move_port_mask = 0x1f, 5222 .pvt = true, 5223 .multi_chip = true, 5224 .tag_protocol = DSA_TAG_PROTO_DSA, 5225 .ptp_support = true, 5226 .ops = &mv88e6390_ops, 5227 }, 5228 [MV88E6390X] = { 5229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5230 .family = MV88E6XXX_FAMILY_6390, 5231 .name = "Marvell 88E6390X", 5232 .num_databases = 4096, 5233 .num_macs = 16384, 5234 .num_ports = 11, /* 10 + Z80 */ 5235 .num_internal_phys = 9, 5236 .num_gpio = 16, 5237 .max_vid = 8191, 5238 .port_base_addr = 0x0, 5239 .phy_base_addr = 0x0, 5240 .global1_addr = 0x1b, 5241 .global2_addr = 0x1c, 5242 .age_time_coeff = 3750, 5243 .g1_irqs = 9, 5244 .g2_irqs = 14, 5245 .atu_move_port_mask = 0x1f, 5246 .pvt = true, 5247 .multi_chip = true, 5248 .tag_protocol = DSA_TAG_PROTO_DSA, 5249 .ptp_support = true, 5250 .ops = &mv88e6390x_ops, 5251 }, 5252 }; 5253 5254 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5255 { 5256 int i; 5257 5258 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5259 if (mv88e6xxx_table[i].prod_num == prod_num) 5260 return &mv88e6xxx_table[i]; 5261 5262 return NULL; 5263 } 5264 5265 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5266 { 5267 const struct mv88e6xxx_info *info; 5268 unsigned int prod_num, rev; 5269 u16 id; 5270 int err; 5271 5272 mv88e6xxx_reg_lock(chip); 5273 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5274 mv88e6xxx_reg_unlock(chip); 5275 if (err) 5276 return err; 5277 5278 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5279 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5280 5281 info = mv88e6xxx_lookup_info(prod_num); 5282 if (!info) 5283 return -ENODEV; 5284 5285 /* Update the compatible info with the probed one */ 5286 chip->info = info; 5287 5288 err = mv88e6xxx_g2_require(chip); 5289 if (err) 5290 return err; 5291 5292 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5293 chip->info->prod_num, chip->info->name, rev); 5294 5295 return 0; 5296 } 5297 5298 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5299 { 5300 struct mv88e6xxx_chip *chip; 5301 5302 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5303 if (!chip) 5304 return NULL; 5305 5306 chip->dev = dev; 5307 5308 mutex_init(&chip->reg_lock); 5309 INIT_LIST_HEAD(&chip->mdios); 5310 idr_init(&chip->policies); 5311 5312 return chip; 5313 } 5314 5315 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5316 int port, 5317 enum dsa_tag_protocol m) 5318 { 5319 struct mv88e6xxx_chip *chip = ds->priv; 5320 5321 return chip->info->tag_protocol; 5322 } 5323 5324 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5325 const struct switchdev_obj_port_mdb *mdb) 5326 { 5327 /* We don't need any dynamic resource from the kernel (yet), 5328 * so skip the prepare phase. 5329 */ 5330 5331 return 0; 5332 } 5333 5334 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5335 const struct switchdev_obj_port_mdb *mdb) 5336 { 5337 struct mv88e6xxx_chip *chip = ds->priv; 5338 5339 mv88e6xxx_reg_lock(chip); 5340 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5341 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5342 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5343 port); 5344 mv88e6xxx_reg_unlock(chip); 5345 } 5346 5347 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5348 const struct switchdev_obj_port_mdb *mdb) 5349 { 5350 struct mv88e6xxx_chip *chip = ds->priv; 5351 int err; 5352 5353 mv88e6xxx_reg_lock(chip); 5354 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5355 mv88e6xxx_reg_unlock(chip); 5356 5357 return err; 5358 } 5359 5360 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5361 struct dsa_mall_mirror_tc_entry *mirror, 5362 bool ingress) 5363 { 5364 enum mv88e6xxx_egress_direction direction = ingress ? 5365 MV88E6XXX_EGRESS_DIR_INGRESS : 5366 MV88E6XXX_EGRESS_DIR_EGRESS; 5367 struct mv88e6xxx_chip *chip = ds->priv; 5368 bool other_mirrors = false; 5369 int i; 5370 int err; 5371 5372 if (!chip->info->ops->set_egress_port) 5373 return -EOPNOTSUPP; 5374 5375 mutex_lock(&chip->reg_lock); 5376 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5377 mirror->to_local_port) { 5378 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5379 other_mirrors |= ingress ? 5380 chip->ports[i].mirror_ingress : 5381 chip->ports[i].mirror_egress; 5382 5383 /* Can't change egress port when other mirror is active */ 5384 if (other_mirrors) { 5385 err = -EBUSY; 5386 goto out; 5387 } 5388 5389 err = chip->info->ops->set_egress_port(chip, 5390 direction, 5391 mirror->to_local_port); 5392 if (err) 5393 goto out; 5394 } 5395 5396 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5397 out: 5398 mutex_unlock(&chip->reg_lock); 5399 5400 return err; 5401 } 5402 5403 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5404 struct dsa_mall_mirror_tc_entry *mirror) 5405 { 5406 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5407 MV88E6XXX_EGRESS_DIR_INGRESS : 5408 MV88E6XXX_EGRESS_DIR_EGRESS; 5409 struct mv88e6xxx_chip *chip = ds->priv; 5410 bool other_mirrors = false; 5411 int i; 5412 5413 mutex_lock(&chip->reg_lock); 5414 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5415 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5416 5417 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5418 other_mirrors |= mirror->ingress ? 5419 chip->ports[i].mirror_ingress : 5420 chip->ports[i].mirror_egress; 5421 5422 /* Reset egress port when no other mirror is active */ 5423 if (!other_mirrors) { 5424 if (chip->info->ops->set_egress_port(chip, 5425 direction, 5426 dsa_upstream_port(ds, 5427 port))) 5428 dev_err(ds->dev, "failed to set egress port\n"); 5429 } 5430 5431 mutex_unlock(&chip->reg_lock); 5432 } 5433 5434 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5435 bool unicast, bool multicast) 5436 { 5437 struct mv88e6xxx_chip *chip = ds->priv; 5438 int err = -EOPNOTSUPP; 5439 5440 mv88e6xxx_reg_lock(chip); 5441 if (chip->info->ops->port_set_egress_floods) 5442 err = chip->info->ops->port_set_egress_floods(chip, port, 5443 unicast, 5444 multicast); 5445 mv88e6xxx_reg_unlock(chip); 5446 5447 return err; 5448 } 5449 5450 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5451 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5452 .setup = mv88e6xxx_setup, 5453 .teardown = mv88e6xxx_teardown, 5454 .phylink_validate = mv88e6xxx_validate, 5455 .phylink_mac_link_state = mv88e6xxx_link_state, 5456 .phylink_mac_config = mv88e6xxx_mac_config, 5457 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5458 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5459 .get_strings = mv88e6xxx_get_strings, 5460 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5461 .get_sset_count = mv88e6xxx_get_sset_count, 5462 .port_enable = mv88e6xxx_port_enable, 5463 .port_disable = mv88e6xxx_port_disable, 5464 .get_mac_eee = mv88e6xxx_get_mac_eee, 5465 .set_mac_eee = mv88e6xxx_set_mac_eee, 5466 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5467 .get_eeprom = mv88e6xxx_get_eeprom, 5468 .set_eeprom = mv88e6xxx_set_eeprom, 5469 .get_regs_len = mv88e6xxx_get_regs_len, 5470 .get_regs = mv88e6xxx_get_regs, 5471 .get_rxnfc = mv88e6xxx_get_rxnfc, 5472 .set_rxnfc = mv88e6xxx_set_rxnfc, 5473 .set_ageing_time = mv88e6xxx_set_ageing_time, 5474 .port_bridge_join = mv88e6xxx_port_bridge_join, 5475 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5476 .port_egress_floods = mv88e6xxx_port_egress_floods, 5477 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5478 .port_fast_age = mv88e6xxx_port_fast_age, 5479 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5480 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5481 .port_vlan_add = mv88e6xxx_port_vlan_add, 5482 .port_vlan_del = mv88e6xxx_port_vlan_del, 5483 .port_fdb_add = mv88e6xxx_port_fdb_add, 5484 .port_fdb_del = mv88e6xxx_port_fdb_del, 5485 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5486 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5487 .port_mdb_add = mv88e6xxx_port_mdb_add, 5488 .port_mdb_del = mv88e6xxx_port_mdb_del, 5489 .port_mirror_add = mv88e6xxx_port_mirror_add, 5490 .port_mirror_del = mv88e6xxx_port_mirror_del, 5491 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5492 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5493 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5494 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5495 .port_txtstamp = mv88e6xxx_port_txtstamp, 5496 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5497 .get_ts_info = mv88e6xxx_get_ts_info, 5498 .devlink_param_get = mv88e6xxx_devlink_param_get, 5499 .devlink_param_set = mv88e6xxx_devlink_param_set, 5500 }; 5501 5502 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5503 { 5504 struct device *dev = chip->dev; 5505 struct dsa_switch *ds; 5506 5507 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5508 if (!ds) 5509 return -ENOMEM; 5510 5511 ds->dev = dev; 5512 ds->num_ports = mv88e6xxx_num_ports(chip); 5513 ds->priv = chip; 5514 ds->dev = dev; 5515 ds->ops = &mv88e6xxx_switch_ops; 5516 ds->ageing_time_min = chip->info->age_time_coeff; 5517 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5518 5519 dev_set_drvdata(dev, ds); 5520 5521 return dsa_register_switch(ds); 5522 } 5523 5524 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5525 { 5526 dsa_unregister_switch(chip->ds); 5527 } 5528 5529 static const void *pdata_device_get_match_data(struct device *dev) 5530 { 5531 const struct of_device_id *matches = dev->driver->of_match_table; 5532 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5533 5534 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5535 matches++) { 5536 if (!strcmp(pdata->compatible, matches->compatible)) 5537 return matches->data; 5538 } 5539 return NULL; 5540 } 5541 5542 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5543 * would be lost after a power cycle so prevent it to be suspended. 5544 */ 5545 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5546 { 5547 return -EOPNOTSUPP; 5548 } 5549 5550 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5551 { 5552 return 0; 5553 } 5554 5555 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5556 5557 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5558 { 5559 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5560 const struct mv88e6xxx_info *compat_info = NULL; 5561 struct device *dev = &mdiodev->dev; 5562 struct device_node *np = dev->of_node; 5563 struct mv88e6xxx_chip *chip; 5564 int port; 5565 int err; 5566 5567 if (!np && !pdata) 5568 return -EINVAL; 5569 5570 if (np) 5571 compat_info = of_device_get_match_data(dev); 5572 5573 if (pdata) { 5574 compat_info = pdata_device_get_match_data(dev); 5575 5576 if (!pdata->netdev) 5577 return -EINVAL; 5578 5579 for (port = 0; port < DSA_MAX_PORTS; port++) { 5580 if (!(pdata->enabled_ports & (1 << port))) 5581 continue; 5582 if (strcmp(pdata->cd.port_names[port], "cpu")) 5583 continue; 5584 pdata->cd.netdev[port] = &pdata->netdev->dev; 5585 break; 5586 } 5587 } 5588 5589 if (!compat_info) 5590 return -EINVAL; 5591 5592 chip = mv88e6xxx_alloc_chip(dev); 5593 if (!chip) { 5594 err = -ENOMEM; 5595 goto out; 5596 } 5597 5598 chip->info = compat_info; 5599 5600 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5601 if (err) 5602 goto out; 5603 5604 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5605 if (IS_ERR(chip->reset)) { 5606 err = PTR_ERR(chip->reset); 5607 goto out; 5608 } 5609 if (chip->reset) 5610 usleep_range(1000, 2000); 5611 5612 err = mv88e6xxx_detect(chip); 5613 if (err) 5614 goto out; 5615 5616 mv88e6xxx_phy_init(chip); 5617 5618 if (chip->info->ops->get_eeprom) { 5619 if (np) 5620 of_property_read_u32(np, "eeprom-length", 5621 &chip->eeprom_len); 5622 else 5623 chip->eeprom_len = pdata->eeprom_len; 5624 } 5625 5626 mv88e6xxx_reg_lock(chip); 5627 err = mv88e6xxx_switch_reset(chip); 5628 mv88e6xxx_reg_unlock(chip); 5629 if (err) 5630 goto out; 5631 5632 if (np) { 5633 chip->irq = of_irq_get(np, 0); 5634 if (chip->irq == -EPROBE_DEFER) { 5635 err = chip->irq; 5636 goto out; 5637 } 5638 } 5639 5640 if (pdata) 5641 chip->irq = pdata->irq; 5642 5643 /* Has to be performed before the MDIO bus is created, because 5644 * the PHYs will link their interrupts to these interrupt 5645 * controllers 5646 */ 5647 mv88e6xxx_reg_lock(chip); 5648 if (chip->irq > 0) 5649 err = mv88e6xxx_g1_irq_setup(chip); 5650 else 5651 err = mv88e6xxx_irq_poll_setup(chip); 5652 mv88e6xxx_reg_unlock(chip); 5653 5654 if (err) 5655 goto out; 5656 5657 if (chip->info->g2_irqs > 0) { 5658 err = mv88e6xxx_g2_irq_setup(chip); 5659 if (err) 5660 goto out_g1_irq; 5661 } 5662 5663 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5664 if (err) 5665 goto out_g2_irq; 5666 5667 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5668 if (err) 5669 goto out_g1_atu_prob_irq; 5670 5671 err = mv88e6xxx_mdios_register(chip, np); 5672 if (err) 5673 goto out_g1_vtu_prob_irq; 5674 5675 err = mv88e6xxx_register_switch(chip); 5676 if (err) 5677 goto out_mdio; 5678 5679 return 0; 5680 5681 out_mdio: 5682 mv88e6xxx_mdios_unregister(chip); 5683 out_g1_vtu_prob_irq: 5684 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5685 out_g1_atu_prob_irq: 5686 mv88e6xxx_g1_atu_prob_irq_free(chip); 5687 out_g2_irq: 5688 if (chip->info->g2_irqs > 0) 5689 mv88e6xxx_g2_irq_free(chip); 5690 out_g1_irq: 5691 if (chip->irq > 0) 5692 mv88e6xxx_g1_irq_free(chip); 5693 else 5694 mv88e6xxx_irq_poll_free(chip); 5695 out: 5696 if (pdata) 5697 dev_put(pdata->netdev); 5698 5699 return err; 5700 } 5701 5702 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5703 { 5704 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5705 struct mv88e6xxx_chip *chip = ds->priv; 5706 5707 if (chip->info->ptp_support) { 5708 mv88e6xxx_hwtstamp_free(chip); 5709 mv88e6xxx_ptp_free(chip); 5710 } 5711 5712 mv88e6xxx_phy_destroy(chip); 5713 mv88e6xxx_unregister_switch(chip); 5714 mv88e6xxx_mdios_unregister(chip); 5715 5716 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5717 mv88e6xxx_g1_atu_prob_irq_free(chip); 5718 5719 if (chip->info->g2_irqs > 0) 5720 mv88e6xxx_g2_irq_free(chip); 5721 5722 if (chip->irq > 0) 5723 mv88e6xxx_g1_irq_free(chip); 5724 else 5725 mv88e6xxx_irq_poll_free(chip); 5726 } 5727 5728 static const struct of_device_id mv88e6xxx_of_match[] = { 5729 { 5730 .compatible = "marvell,mv88e6085", 5731 .data = &mv88e6xxx_table[MV88E6085], 5732 }, 5733 { 5734 .compatible = "marvell,mv88e6190", 5735 .data = &mv88e6xxx_table[MV88E6190], 5736 }, 5737 { 5738 .compatible = "marvell,mv88e6250", 5739 .data = &mv88e6xxx_table[MV88E6250], 5740 }, 5741 { /* sentinel */ }, 5742 }; 5743 5744 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5745 5746 static struct mdio_driver mv88e6xxx_driver = { 5747 .probe = mv88e6xxx_probe, 5748 .remove = mv88e6xxx_remove, 5749 .mdiodrv.driver = { 5750 .name = "mv88e6085", 5751 .of_match_table = mv88e6xxx_of_match, 5752 .pm = &mv88e6xxx_pm_ops, 5753 }, 5754 }; 5755 5756 mdio_module_driver(mv88e6xxx_driver); 5757 5758 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5759 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5760 MODULE_LICENSE("GPL"); 5761