1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 401 int speed, int duplex, int pause, 402 phy_interface_t mode) 403 { 404 struct phylink_link_state state; 405 int err; 406 407 if (!chip->info->ops->port_set_link) 408 return 0; 409 410 if (!chip->info->ops->port_link_state) 411 return 0; 412 413 err = chip->info->ops->port_link_state(chip, port, &state); 414 if (err) 415 return err; 416 417 /* Has anything actually changed? We don't expect the 418 * interface mode to change without one of the other 419 * parameters also changing 420 */ 421 if (state.link == link && 422 state.speed == speed && 423 state.duplex == duplex && 424 (state.interface == mode || 425 state.interface == PHY_INTERFACE_MODE_NA)) 426 return 0; 427 428 /* Port's MAC control must not be changed unless the link is down */ 429 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 430 if (err) 431 return err; 432 433 if (chip->info->ops->port_set_speed) { 434 err = chip->info->ops->port_set_speed(chip, port, speed); 435 if (err && err != -EOPNOTSUPP) 436 goto restore_link; 437 } 438 439 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 440 mode = chip->info->ops->port_max_speed_mode(port); 441 442 if (chip->info->ops->port_set_pause) { 443 err = chip->info->ops->port_set_pause(chip, port, pause); 444 if (err) 445 goto restore_link; 446 } 447 448 if (chip->info->ops->port_set_duplex) { 449 err = chip->info->ops->port_set_duplex(chip, port, duplex); 450 if (err && err != -EOPNOTSUPP) 451 goto restore_link; 452 } 453 454 if (chip->info->ops->port_set_rgmii_delay) { 455 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_cmode) { 461 err = chip->info->ops->port_set_cmode(chip, port, mode); 462 if (err && err != -EOPNOTSUPP) 463 goto restore_link; 464 } 465 466 err = 0; 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 475 { 476 struct mv88e6xxx_chip *chip = ds->priv; 477 478 return port < chip->info->num_internal_phys; 479 } 480 481 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 482 unsigned long *mask, 483 struct phylink_link_state *state) 484 { 485 if (!phy_interface_mode_is_8023z(state->interface)) { 486 /* 10M and 100M are only supported in non-802.3z mode */ 487 phylink_set(mask, 10baseT_Half); 488 phylink_set(mask, 10baseT_Full); 489 phylink_set(mask, 100baseT_Half); 490 phylink_set(mask, 100baseT_Full); 491 } 492 } 493 494 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 495 unsigned long *mask, 496 struct phylink_link_state *state) 497 { 498 /* FIXME: if the port is in 1000Base-X mode, then it only supports 499 * 1000M FD speeds. In this case, CMODE will indicate 5. 500 */ 501 phylink_set(mask, 1000baseT_Full); 502 phylink_set(mask, 1000baseX_Full); 503 504 mv88e6065_phylink_validate(chip, port, mask, state); 505 } 506 507 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 508 unsigned long *mask, 509 struct phylink_link_state *state) 510 { 511 if (port >= 5) 512 phylink_set(mask, 2500baseX_Full); 513 514 /* No ethtool bits for 200Mbps */ 515 phylink_set(mask, 1000baseT_Full); 516 phylink_set(mask, 1000baseX_Full); 517 518 mv88e6065_phylink_validate(chip, port, mask, state); 519 } 520 521 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 522 unsigned long *mask, 523 struct phylink_link_state *state) 524 { 525 /* No ethtool bits for 200Mbps */ 526 phylink_set(mask, 1000baseT_Full); 527 phylink_set(mask, 1000baseX_Full); 528 529 mv88e6065_phylink_validate(chip, port, mask, state); 530 } 531 532 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 533 unsigned long *mask, 534 struct phylink_link_state *state) 535 { 536 if (port >= 9) { 537 phylink_set(mask, 2500baseX_Full); 538 phylink_set(mask, 2500baseT_Full); 539 } 540 541 /* No ethtool bits for 200Mbps */ 542 phylink_set(mask, 1000baseT_Full); 543 phylink_set(mask, 1000baseX_Full); 544 545 mv88e6065_phylink_validate(chip, port, mask, state); 546 } 547 548 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 549 unsigned long *mask, 550 struct phylink_link_state *state) 551 { 552 if (port >= 9) { 553 phylink_set(mask, 10000baseT_Full); 554 phylink_set(mask, 10000baseKR_Full); 555 } 556 557 mv88e6390_phylink_validate(chip, port, mask, state); 558 } 559 560 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 561 unsigned long *supported, 562 struct phylink_link_state *state) 563 { 564 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 565 struct mv88e6xxx_chip *chip = ds->priv; 566 567 /* Allow all the expected bits */ 568 phylink_set(mask, Autoneg); 569 phylink_set(mask, Pause); 570 phylink_set_port_modes(mask); 571 572 if (chip->info->ops->phylink_validate) 573 chip->info->ops->phylink_validate(chip, port, mask, state); 574 575 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 576 bitmap_and(state->advertising, state->advertising, mask, 577 __ETHTOOL_LINK_MODE_MASK_NBITS); 578 579 /* We can only operate at 2500BaseX or 1000BaseX. If requested 580 * to advertise both, only report advertising at 2500BaseX. 581 */ 582 phylink_helper_basex_speed(state); 583 } 584 585 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 586 struct phylink_link_state *state) 587 { 588 struct mv88e6xxx_chip *chip = ds->priv; 589 int err; 590 591 mv88e6xxx_reg_lock(chip); 592 if (chip->info->ops->port_link_state) 593 err = chip->info->ops->port_link_state(chip, port, state); 594 else 595 err = -EOPNOTSUPP; 596 mv88e6xxx_reg_unlock(chip); 597 598 return err; 599 } 600 601 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 602 unsigned int mode, 603 const struct phylink_link_state *state) 604 { 605 struct mv88e6xxx_chip *chip = ds->priv; 606 int speed, duplex, link, pause, err; 607 608 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 609 return; 610 611 if (mode == MLO_AN_FIXED) { 612 link = LINK_FORCED_UP; 613 speed = state->speed; 614 duplex = state->duplex; 615 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 616 link = state->link; 617 speed = state->speed; 618 duplex = state->duplex; 619 } else { 620 speed = SPEED_UNFORCED; 621 duplex = DUPLEX_UNFORCED; 622 link = LINK_UNFORCED; 623 } 624 pause = !!phylink_test(state->advertising, Pause); 625 626 mv88e6xxx_reg_lock(chip); 627 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 628 state->interface); 629 mv88e6xxx_reg_unlock(chip); 630 631 if (err && err != -EOPNOTSUPP) 632 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 633 } 634 635 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 636 { 637 struct mv88e6xxx_chip *chip = ds->priv; 638 int err; 639 640 mv88e6xxx_reg_lock(chip); 641 err = chip->info->ops->port_set_link(chip, port, link); 642 mv88e6xxx_reg_unlock(chip); 643 644 if (err) 645 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 646 } 647 648 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 649 unsigned int mode, 650 phy_interface_t interface) 651 { 652 if (mode == MLO_AN_FIXED) 653 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 654 } 655 656 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 657 unsigned int mode, phy_interface_t interface, 658 struct phy_device *phydev) 659 { 660 if (mode == MLO_AN_FIXED) 661 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 662 } 663 664 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 665 { 666 if (!chip->info->ops->stats_snapshot) 667 return -EOPNOTSUPP; 668 669 return chip->info->ops->stats_snapshot(chip, port); 670 } 671 672 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 673 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 674 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 675 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 676 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 677 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 678 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 679 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 680 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 681 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 682 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 683 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 684 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 685 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 686 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 687 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 688 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 689 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 690 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 691 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 692 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 693 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 694 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 695 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 696 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 697 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 698 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 699 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 700 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 701 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 702 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 703 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 704 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 705 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 706 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 707 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 708 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 709 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 710 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 711 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 712 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 713 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 714 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 715 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 716 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 717 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 718 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 719 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 720 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 721 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 722 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 723 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 724 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 725 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 726 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 727 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 728 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 729 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 730 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 731 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 732 }; 733 734 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 735 struct mv88e6xxx_hw_stat *s, 736 int port, u16 bank1_select, 737 u16 histogram) 738 { 739 u32 low; 740 u32 high = 0; 741 u16 reg = 0; 742 int err; 743 u64 value; 744 745 switch (s->type) { 746 case STATS_TYPE_PORT: 747 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 748 if (err) 749 return U64_MAX; 750 751 low = reg; 752 if (s->size == 4) { 753 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 754 if (err) 755 return U64_MAX; 756 low |= ((u32)reg) << 16; 757 } 758 break; 759 case STATS_TYPE_BANK1: 760 reg = bank1_select; 761 /* fall through */ 762 case STATS_TYPE_BANK0: 763 reg |= s->reg | histogram; 764 mv88e6xxx_g1_stats_read(chip, reg, &low); 765 if (s->size == 8) 766 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 767 break; 768 default: 769 return U64_MAX; 770 } 771 value = (((u64)high) << 32) | low; 772 return value; 773 } 774 775 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 776 uint8_t *data, int types) 777 { 778 struct mv88e6xxx_hw_stat *stat; 779 int i, j; 780 781 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 782 stat = &mv88e6xxx_hw_stats[i]; 783 if (stat->type & types) { 784 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 785 ETH_GSTRING_LEN); 786 j++; 787 } 788 } 789 790 return j; 791 } 792 793 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 794 uint8_t *data) 795 { 796 return mv88e6xxx_stats_get_strings(chip, data, 797 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 798 } 799 800 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 801 uint8_t *data) 802 { 803 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 804 } 805 806 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 807 uint8_t *data) 808 { 809 return mv88e6xxx_stats_get_strings(chip, data, 810 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 811 } 812 813 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 814 "atu_member_violation", 815 "atu_miss_violation", 816 "atu_full_violation", 817 "vtu_member_violation", 818 "vtu_miss_violation", 819 }; 820 821 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 822 { 823 unsigned int i; 824 825 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 826 strlcpy(data + i * ETH_GSTRING_LEN, 827 mv88e6xxx_atu_vtu_stats_strings[i], 828 ETH_GSTRING_LEN); 829 } 830 831 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 832 u32 stringset, uint8_t *data) 833 { 834 struct mv88e6xxx_chip *chip = ds->priv; 835 int count = 0; 836 837 if (stringset != ETH_SS_STATS) 838 return; 839 840 mv88e6xxx_reg_lock(chip); 841 842 if (chip->info->ops->stats_get_strings) 843 count = chip->info->ops->stats_get_strings(chip, data); 844 845 if (chip->info->ops->serdes_get_strings) { 846 data += count * ETH_GSTRING_LEN; 847 count = chip->info->ops->serdes_get_strings(chip, port, data); 848 } 849 850 data += count * ETH_GSTRING_LEN; 851 mv88e6xxx_atu_vtu_get_strings(data); 852 853 mv88e6xxx_reg_unlock(chip); 854 } 855 856 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 857 int types) 858 { 859 struct mv88e6xxx_hw_stat *stat; 860 int i, j; 861 862 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 863 stat = &mv88e6xxx_hw_stats[i]; 864 if (stat->type & types) 865 j++; 866 } 867 return j; 868 } 869 870 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 871 { 872 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 873 STATS_TYPE_PORT); 874 } 875 876 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 877 { 878 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 879 } 880 881 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 882 { 883 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 884 STATS_TYPE_BANK1); 885 } 886 887 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 888 { 889 struct mv88e6xxx_chip *chip = ds->priv; 890 int serdes_count = 0; 891 int count = 0; 892 893 if (sset != ETH_SS_STATS) 894 return 0; 895 896 mv88e6xxx_reg_lock(chip); 897 if (chip->info->ops->stats_get_sset_count) 898 count = chip->info->ops->stats_get_sset_count(chip); 899 if (count < 0) 900 goto out; 901 902 if (chip->info->ops->serdes_get_sset_count) 903 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 904 port); 905 if (serdes_count < 0) { 906 count = serdes_count; 907 goto out; 908 } 909 count += serdes_count; 910 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 911 912 out: 913 mv88e6xxx_reg_unlock(chip); 914 915 return count; 916 } 917 918 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 919 uint64_t *data, int types, 920 u16 bank1_select, u16 histogram) 921 { 922 struct mv88e6xxx_hw_stat *stat; 923 int i, j; 924 925 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 926 stat = &mv88e6xxx_hw_stats[i]; 927 if (stat->type & types) { 928 mv88e6xxx_reg_lock(chip); 929 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 930 bank1_select, 931 histogram); 932 mv88e6xxx_reg_unlock(chip); 933 934 j++; 935 } 936 } 937 return j; 938 } 939 940 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 941 uint64_t *data) 942 { 943 return mv88e6xxx_stats_get_stats(chip, port, data, 944 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 945 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 946 } 947 948 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 949 uint64_t *data) 950 { 951 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 952 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 953 } 954 955 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 956 uint64_t *data) 957 { 958 return mv88e6xxx_stats_get_stats(chip, port, data, 959 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 960 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 961 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 962 } 963 964 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 965 uint64_t *data) 966 { 967 return mv88e6xxx_stats_get_stats(chip, port, data, 968 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 969 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 970 0); 971 } 972 973 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 974 uint64_t *data) 975 { 976 *data++ = chip->ports[port].atu_member_violation; 977 *data++ = chip->ports[port].atu_miss_violation; 978 *data++ = chip->ports[port].atu_full_violation; 979 *data++ = chip->ports[port].vtu_member_violation; 980 *data++ = chip->ports[port].vtu_miss_violation; 981 } 982 983 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 984 uint64_t *data) 985 { 986 int count = 0; 987 988 if (chip->info->ops->stats_get_stats) 989 count = chip->info->ops->stats_get_stats(chip, port, data); 990 991 mv88e6xxx_reg_lock(chip); 992 if (chip->info->ops->serdes_get_stats) { 993 data += count; 994 count = chip->info->ops->serdes_get_stats(chip, port, data); 995 } 996 data += count; 997 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 998 mv88e6xxx_reg_unlock(chip); 999 } 1000 1001 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1002 uint64_t *data) 1003 { 1004 struct mv88e6xxx_chip *chip = ds->priv; 1005 int ret; 1006 1007 mv88e6xxx_reg_lock(chip); 1008 1009 ret = mv88e6xxx_stats_snapshot(chip, port); 1010 mv88e6xxx_reg_unlock(chip); 1011 1012 if (ret < 0) 1013 return; 1014 1015 mv88e6xxx_get_stats(chip, port, data); 1016 1017 } 1018 1019 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1020 { 1021 struct mv88e6xxx_chip *chip = ds->priv; 1022 int len; 1023 1024 len = 32 * sizeof(u16); 1025 if (chip->info->ops->serdes_get_regs_len) 1026 len += chip->info->ops->serdes_get_regs_len(chip, port); 1027 1028 return len; 1029 } 1030 1031 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1032 struct ethtool_regs *regs, void *_p) 1033 { 1034 struct mv88e6xxx_chip *chip = ds->priv; 1035 int err; 1036 u16 reg; 1037 u16 *p = _p; 1038 int i; 1039 1040 regs->version = chip->info->prod_num; 1041 1042 memset(p, 0xff, 32 * sizeof(u16)); 1043 1044 mv88e6xxx_reg_lock(chip); 1045 1046 for (i = 0; i < 32; i++) { 1047 1048 err = mv88e6xxx_port_read(chip, port, i, ®); 1049 if (!err) 1050 p[i] = reg; 1051 } 1052 1053 if (chip->info->ops->serdes_get_regs) 1054 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1055 1056 mv88e6xxx_reg_unlock(chip); 1057 } 1058 1059 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1060 struct ethtool_eee *e) 1061 { 1062 /* Nothing to do on the port's MAC */ 1063 return 0; 1064 } 1065 1066 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1067 struct ethtool_eee *e) 1068 { 1069 /* Nothing to do on the port's MAC */ 1070 return 0; 1071 } 1072 1073 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1074 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1075 { 1076 struct dsa_switch *ds = chip->ds; 1077 struct dsa_switch_tree *dst = ds->dst; 1078 struct net_device *br; 1079 struct dsa_port *dp; 1080 bool found = false; 1081 u16 pvlan; 1082 1083 list_for_each_entry(dp, &dst->ports, list) { 1084 if (dp->ds->index == dev && dp->index == port) { 1085 found = true; 1086 break; 1087 } 1088 } 1089 1090 /* Prevent frames from unknown switch or port */ 1091 if (!found) 1092 return 0; 1093 1094 /* Frames from DSA links and CPU ports can egress any local port */ 1095 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1096 return mv88e6xxx_port_mask(chip); 1097 1098 br = dp->bridge_dev; 1099 pvlan = 0; 1100 1101 /* Frames from user ports can egress any local DSA links and CPU ports, 1102 * as well as any local member of their bridge group. 1103 */ 1104 list_for_each_entry(dp, &dst->ports, list) 1105 if (dp->ds == ds && 1106 (dp->type == DSA_PORT_TYPE_CPU || 1107 dp->type == DSA_PORT_TYPE_DSA || 1108 (br && dp->bridge_dev == br))) 1109 pvlan |= BIT(dp->index); 1110 1111 return pvlan; 1112 } 1113 1114 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1115 { 1116 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1117 1118 /* prevent frames from going back out of the port they came in on */ 1119 output_ports &= ~BIT(port); 1120 1121 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1122 } 1123 1124 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1125 u8 state) 1126 { 1127 struct mv88e6xxx_chip *chip = ds->priv; 1128 int err; 1129 1130 mv88e6xxx_reg_lock(chip); 1131 err = mv88e6xxx_port_set_state(chip, port, state); 1132 mv88e6xxx_reg_unlock(chip); 1133 1134 if (err) 1135 dev_err(ds->dev, "p%d: failed to update state\n", port); 1136 } 1137 1138 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1139 { 1140 int err; 1141 1142 if (chip->info->ops->ieee_pri_map) { 1143 err = chip->info->ops->ieee_pri_map(chip); 1144 if (err) 1145 return err; 1146 } 1147 1148 if (chip->info->ops->ip_pri_map) { 1149 err = chip->info->ops->ip_pri_map(chip); 1150 if (err) 1151 return err; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1158 { 1159 struct dsa_switch *ds = chip->ds; 1160 int target, port; 1161 int err; 1162 1163 if (!chip->info->global2_addr) 1164 return 0; 1165 1166 /* Initialize the routing port to the 32 possible target devices */ 1167 for (target = 0; target < 32; target++) { 1168 port = dsa_routing_port(ds, target); 1169 if (port == ds->num_ports) 1170 port = 0x1f; 1171 1172 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1173 if (err) 1174 return err; 1175 } 1176 1177 if (chip->info->ops->set_cascade_port) { 1178 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1179 err = chip->info->ops->set_cascade_port(chip, port); 1180 if (err) 1181 return err; 1182 } 1183 1184 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1185 if (err) 1186 return err; 1187 1188 return 0; 1189 } 1190 1191 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1192 { 1193 /* Clear all trunk masks and mapping */ 1194 if (chip->info->global2_addr) 1195 return mv88e6xxx_g2_trunk_clear(chip); 1196 1197 return 0; 1198 } 1199 1200 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1201 { 1202 if (chip->info->ops->rmu_disable) 1203 return chip->info->ops->rmu_disable(chip); 1204 1205 return 0; 1206 } 1207 1208 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1209 { 1210 if (chip->info->ops->pot_clear) 1211 return chip->info->ops->pot_clear(chip); 1212 1213 return 0; 1214 } 1215 1216 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1217 { 1218 if (chip->info->ops->mgmt_rsvd2cpu) 1219 return chip->info->ops->mgmt_rsvd2cpu(chip); 1220 1221 return 0; 1222 } 1223 1224 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1225 { 1226 int err; 1227 1228 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1229 if (err) 1230 return err; 1231 1232 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1233 if (err) 1234 return err; 1235 1236 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1237 } 1238 1239 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1240 { 1241 int port; 1242 int err; 1243 1244 if (!chip->info->ops->irl_init_all) 1245 return 0; 1246 1247 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1248 /* Disable ingress rate limiting by resetting all per port 1249 * ingress rate limit resources to their initial state. 1250 */ 1251 err = chip->info->ops->irl_init_all(chip, port); 1252 if (err) 1253 return err; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1260 { 1261 if (chip->info->ops->set_switch_mac) { 1262 u8 addr[ETH_ALEN]; 1263 1264 eth_random_addr(addr); 1265 1266 return chip->info->ops->set_switch_mac(chip, addr); 1267 } 1268 1269 return 0; 1270 } 1271 1272 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1273 { 1274 u16 pvlan = 0; 1275 1276 if (!mv88e6xxx_has_pvt(chip)) 1277 return 0; 1278 1279 /* Skip the local source device, which uses in-chip port VLAN */ 1280 if (dev != chip->ds->index) 1281 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1282 1283 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1284 } 1285 1286 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1287 { 1288 int dev, port; 1289 int err; 1290 1291 if (!mv88e6xxx_has_pvt(chip)) 1292 return 0; 1293 1294 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1295 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1296 */ 1297 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1298 if (err) 1299 return err; 1300 1301 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1302 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1303 err = mv88e6xxx_pvt_map(chip, dev, port); 1304 if (err) 1305 return err; 1306 } 1307 } 1308 1309 return 0; 1310 } 1311 1312 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1313 { 1314 struct mv88e6xxx_chip *chip = ds->priv; 1315 int err; 1316 1317 mv88e6xxx_reg_lock(chip); 1318 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1319 mv88e6xxx_reg_unlock(chip); 1320 1321 if (err) 1322 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1323 } 1324 1325 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1326 { 1327 if (!chip->info->max_vid) 1328 return 0; 1329 1330 return mv88e6xxx_g1_vtu_flush(chip); 1331 } 1332 1333 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1334 struct mv88e6xxx_vtu_entry *entry) 1335 { 1336 if (!chip->info->ops->vtu_getnext) 1337 return -EOPNOTSUPP; 1338 1339 return chip->info->ops->vtu_getnext(chip, entry); 1340 } 1341 1342 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1343 struct mv88e6xxx_vtu_entry *entry) 1344 { 1345 if (!chip->info->ops->vtu_loadpurge) 1346 return -EOPNOTSUPP; 1347 1348 return chip->info->ops->vtu_loadpurge(chip, entry); 1349 } 1350 1351 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1352 { 1353 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1354 struct mv88e6xxx_vtu_entry vlan; 1355 int i, err; 1356 1357 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1358 1359 /* Set every FID bit used by the (un)bridged ports */ 1360 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1361 err = mv88e6xxx_port_get_fid(chip, i, fid); 1362 if (err) 1363 return err; 1364 1365 set_bit(*fid, fid_bitmap); 1366 } 1367 1368 /* Set every FID bit used by the VLAN entries */ 1369 vlan.vid = chip->info->max_vid; 1370 vlan.valid = false; 1371 1372 do { 1373 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1374 if (err) 1375 return err; 1376 1377 if (!vlan.valid) 1378 break; 1379 1380 set_bit(vlan.fid, fid_bitmap); 1381 } while (vlan.vid < chip->info->max_vid); 1382 1383 /* The reset value 0x000 is used to indicate that multiple address 1384 * databases are not needed. Return the next positive available. 1385 */ 1386 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1387 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1388 return -ENOSPC; 1389 1390 /* Clear the database */ 1391 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1392 } 1393 1394 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1395 { 1396 if (chip->info->ops->atu_get_hash) 1397 return chip->info->ops->atu_get_hash(chip, hash); 1398 1399 return -EOPNOTSUPP; 1400 } 1401 1402 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1403 { 1404 if (chip->info->ops->atu_set_hash) 1405 return chip->info->ops->atu_set_hash(chip, hash); 1406 1407 return -EOPNOTSUPP; 1408 } 1409 1410 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1411 u16 vid_begin, u16 vid_end) 1412 { 1413 struct mv88e6xxx_chip *chip = ds->priv; 1414 struct mv88e6xxx_vtu_entry vlan; 1415 int i, err; 1416 1417 /* DSA and CPU ports have to be members of multiple vlans */ 1418 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1419 return 0; 1420 1421 if (!vid_begin) 1422 return -EOPNOTSUPP; 1423 1424 vlan.vid = vid_begin - 1; 1425 vlan.valid = false; 1426 1427 do { 1428 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1429 if (err) 1430 return err; 1431 1432 if (!vlan.valid) 1433 break; 1434 1435 if (vlan.vid > vid_end) 1436 break; 1437 1438 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1439 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1440 continue; 1441 1442 if (!dsa_to_port(ds, i)->slave) 1443 continue; 1444 1445 if (vlan.member[i] == 1446 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1447 continue; 1448 1449 if (dsa_to_port(ds, i)->bridge_dev == 1450 dsa_to_port(ds, port)->bridge_dev) 1451 break; /* same bridge, check next VLAN */ 1452 1453 if (!dsa_to_port(ds, i)->bridge_dev) 1454 continue; 1455 1456 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1457 port, vlan.vid, i, 1458 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1459 return -EOPNOTSUPP; 1460 } 1461 } while (vlan.vid < vid_end); 1462 1463 return 0; 1464 } 1465 1466 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1467 bool vlan_filtering) 1468 { 1469 struct mv88e6xxx_chip *chip = ds->priv; 1470 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1471 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1472 int err; 1473 1474 if (!chip->info->max_vid) 1475 return -EOPNOTSUPP; 1476 1477 mv88e6xxx_reg_lock(chip); 1478 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1479 mv88e6xxx_reg_unlock(chip); 1480 1481 return err; 1482 } 1483 1484 static int 1485 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1486 const struct switchdev_obj_port_vlan *vlan) 1487 { 1488 struct mv88e6xxx_chip *chip = ds->priv; 1489 int err; 1490 1491 if (!chip->info->max_vid) 1492 return -EOPNOTSUPP; 1493 1494 /* If the requested port doesn't belong to the same bridge as the VLAN 1495 * members, do not support it (yet) and fallback to software VLAN. 1496 */ 1497 mv88e6xxx_reg_lock(chip); 1498 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1499 vlan->vid_end); 1500 mv88e6xxx_reg_unlock(chip); 1501 1502 /* We don't need any dynamic resource from the kernel (yet), 1503 * so skip the prepare phase. 1504 */ 1505 return err; 1506 } 1507 1508 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1509 const unsigned char *addr, u16 vid, 1510 u8 state) 1511 { 1512 struct mv88e6xxx_atu_entry entry; 1513 struct mv88e6xxx_vtu_entry vlan; 1514 u16 fid; 1515 int err; 1516 1517 /* Null VLAN ID corresponds to the port private database */ 1518 if (vid == 0) { 1519 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1520 if (err) 1521 return err; 1522 } else { 1523 vlan.vid = vid - 1; 1524 vlan.valid = false; 1525 1526 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1527 if (err) 1528 return err; 1529 1530 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1531 if (vlan.vid != vid || !vlan.valid) 1532 return -EOPNOTSUPP; 1533 1534 fid = vlan.fid; 1535 } 1536 1537 entry.state = 0; 1538 ether_addr_copy(entry.mac, addr); 1539 eth_addr_dec(entry.mac); 1540 1541 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1542 if (err) 1543 return err; 1544 1545 /* Initialize a fresh ATU entry if it isn't found */ 1546 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1547 memset(&entry, 0, sizeof(entry)); 1548 ether_addr_copy(entry.mac, addr); 1549 } 1550 1551 /* Purge the ATU entry only if no port is using it anymore */ 1552 if (!state) { 1553 entry.portvec &= ~BIT(port); 1554 if (!entry.portvec) 1555 entry.state = 0; 1556 } else { 1557 entry.portvec |= BIT(port); 1558 entry.state = state; 1559 } 1560 1561 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1562 } 1563 1564 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1565 const struct mv88e6xxx_policy *policy) 1566 { 1567 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1568 enum mv88e6xxx_policy_action action = policy->action; 1569 const u8 *addr = policy->addr; 1570 u16 vid = policy->vid; 1571 u8 state; 1572 int err; 1573 int id; 1574 1575 if (!chip->info->ops->port_set_policy) 1576 return -EOPNOTSUPP; 1577 1578 switch (mapping) { 1579 case MV88E6XXX_POLICY_MAPPING_DA: 1580 case MV88E6XXX_POLICY_MAPPING_SA: 1581 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1582 state = 0; /* Dissociate the port and address */ 1583 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1584 is_multicast_ether_addr(addr)) 1585 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1586 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1587 is_unicast_ether_addr(addr)) 1588 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1589 else 1590 return -EOPNOTSUPP; 1591 1592 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1593 state); 1594 if (err) 1595 return err; 1596 break; 1597 default: 1598 return -EOPNOTSUPP; 1599 } 1600 1601 /* Skip the port's policy clearing if the mapping is still in use */ 1602 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1603 idr_for_each_entry(&chip->policies, policy, id) 1604 if (policy->port == port && 1605 policy->mapping == mapping && 1606 policy->action != action) 1607 return 0; 1608 1609 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1610 } 1611 1612 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1613 struct ethtool_rx_flow_spec *fs) 1614 { 1615 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1616 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1617 enum mv88e6xxx_policy_mapping mapping; 1618 enum mv88e6xxx_policy_action action; 1619 struct mv88e6xxx_policy *policy; 1620 u16 vid = 0; 1621 u8 *addr; 1622 int err; 1623 int id; 1624 1625 if (fs->location != RX_CLS_LOC_ANY) 1626 return -EINVAL; 1627 1628 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1629 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1630 else 1631 return -EOPNOTSUPP; 1632 1633 switch (fs->flow_type & ~FLOW_EXT) { 1634 case ETHER_FLOW: 1635 if (!is_zero_ether_addr(mac_mask->h_dest) && 1636 is_zero_ether_addr(mac_mask->h_source)) { 1637 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1638 addr = mac_entry->h_dest; 1639 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1640 !is_zero_ether_addr(mac_mask->h_source)) { 1641 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1642 addr = mac_entry->h_source; 1643 } else { 1644 /* Cannot support DA and SA mapping in the same rule */ 1645 return -EOPNOTSUPP; 1646 } 1647 break; 1648 default: 1649 return -EOPNOTSUPP; 1650 } 1651 1652 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1653 if (fs->m_ext.vlan_tci != 0xffff) 1654 return -EOPNOTSUPP; 1655 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1656 } 1657 1658 idr_for_each_entry(&chip->policies, policy, id) { 1659 if (policy->port == port && policy->mapping == mapping && 1660 policy->action == action && policy->vid == vid && 1661 ether_addr_equal(policy->addr, addr)) 1662 return -EEXIST; 1663 } 1664 1665 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1666 if (!policy) 1667 return -ENOMEM; 1668 1669 fs->location = 0; 1670 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1671 GFP_KERNEL); 1672 if (err) { 1673 devm_kfree(chip->dev, policy); 1674 return err; 1675 } 1676 1677 memcpy(&policy->fs, fs, sizeof(*fs)); 1678 ether_addr_copy(policy->addr, addr); 1679 policy->mapping = mapping; 1680 policy->action = action; 1681 policy->port = port; 1682 policy->vid = vid; 1683 1684 err = mv88e6xxx_policy_apply(chip, port, policy); 1685 if (err) { 1686 idr_remove(&chip->policies, fs->location); 1687 devm_kfree(chip->dev, policy); 1688 return err; 1689 } 1690 1691 return 0; 1692 } 1693 1694 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1695 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1696 { 1697 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1698 struct mv88e6xxx_chip *chip = ds->priv; 1699 struct mv88e6xxx_policy *policy; 1700 int err; 1701 int id; 1702 1703 mv88e6xxx_reg_lock(chip); 1704 1705 switch (rxnfc->cmd) { 1706 case ETHTOOL_GRXCLSRLCNT: 1707 rxnfc->data = 0; 1708 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1709 rxnfc->rule_cnt = 0; 1710 idr_for_each_entry(&chip->policies, policy, id) 1711 if (policy->port == port) 1712 rxnfc->rule_cnt++; 1713 err = 0; 1714 break; 1715 case ETHTOOL_GRXCLSRULE: 1716 err = -ENOENT; 1717 policy = idr_find(&chip->policies, fs->location); 1718 if (policy) { 1719 memcpy(fs, &policy->fs, sizeof(*fs)); 1720 err = 0; 1721 } 1722 break; 1723 case ETHTOOL_GRXCLSRLALL: 1724 rxnfc->data = 0; 1725 rxnfc->rule_cnt = 0; 1726 idr_for_each_entry(&chip->policies, policy, id) 1727 if (policy->port == port) 1728 rule_locs[rxnfc->rule_cnt++] = id; 1729 err = 0; 1730 break; 1731 default: 1732 err = -EOPNOTSUPP; 1733 break; 1734 } 1735 1736 mv88e6xxx_reg_unlock(chip); 1737 1738 return err; 1739 } 1740 1741 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1742 struct ethtool_rxnfc *rxnfc) 1743 { 1744 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1745 struct mv88e6xxx_chip *chip = ds->priv; 1746 struct mv88e6xxx_policy *policy; 1747 int err; 1748 1749 mv88e6xxx_reg_lock(chip); 1750 1751 switch (rxnfc->cmd) { 1752 case ETHTOOL_SRXCLSRLINS: 1753 err = mv88e6xxx_policy_insert(chip, port, fs); 1754 break; 1755 case ETHTOOL_SRXCLSRLDEL: 1756 err = -ENOENT; 1757 policy = idr_remove(&chip->policies, fs->location); 1758 if (policy) { 1759 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1760 err = mv88e6xxx_policy_apply(chip, port, policy); 1761 devm_kfree(chip->dev, policy); 1762 } 1763 break; 1764 default: 1765 err = -EOPNOTSUPP; 1766 break; 1767 } 1768 1769 mv88e6xxx_reg_unlock(chip); 1770 1771 return err; 1772 } 1773 1774 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1775 u16 vid) 1776 { 1777 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1778 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1779 1780 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1781 } 1782 1783 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1784 { 1785 int port; 1786 int err; 1787 1788 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1789 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1790 if (err) 1791 return err; 1792 } 1793 1794 return 0; 1795 } 1796 1797 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1798 u16 vid, u8 member) 1799 { 1800 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1801 struct mv88e6xxx_vtu_entry vlan; 1802 int i, err; 1803 1804 if (!vid) 1805 return -EOPNOTSUPP; 1806 1807 vlan.vid = vid - 1; 1808 vlan.valid = false; 1809 1810 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1811 if (err) 1812 return err; 1813 1814 if (vlan.vid != vid || !vlan.valid) { 1815 memset(&vlan, 0, sizeof(vlan)); 1816 1817 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1818 if (err) 1819 return err; 1820 1821 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1822 if (i == port) 1823 vlan.member[i] = member; 1824 else 1825 vlan.member[i] = non_member; 1826 1827 vlan.vid = vid; 1828 vlan.valid = true; 1829 1830 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1831 if (err) 1832 return err; 1833 1834 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1835 if (err) 1836 return err; 1837 } else if (vlan.member[port] != member) { 1838 vlan.member[port] = member; 1839 1840 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1841 if (err) 1842 return err; 1843 } else { 1844 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1845 port, vid); 1846 } 1847 1848 return 0; 1849 } 1850 1851 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1852 const struct switchdev_obj_port_vlan *vlan) 1853 { 1854 struct mv88e6xxx_chip *chip = ds->priv; 1855 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1856 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1857 u8 member; 1858 u16 vid; 1859 1860 if (!chip->info->max_vid) 1861 return; 1862 1863 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1864 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1865 else if (untagged) 1866 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1867 else 1868 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1869 1870 mv88e6xxx_reg_lock(chip); 1871 1872 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1873 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1874 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1875 vid, untagged ? 'u' : 't'); 1876 1877 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1878 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1879 vlan->vid_end); 1880 1881 mv88e6xxx_reg_unlock(chip); 1882 } 1883 1884 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1885 int port, u16 vid) 1886 { 1887 struct mv88e6xxx_vtu_entry vlan; 1888 int i, err; 1889 1890 if (!vid) 1891 return -EOPNOTSUPP; 1892 1893 vlan.vid = vid - 1; 1894 vlan.valid = false; 1895 1896 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1897 if (err) 1898 return err; 1899 1900 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1901 * tell switchdev that this VLAN is likely handled in software. 1902 */ 1903 if (vlan.vid != vid || !vlan.valid || 1904 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1905 return -EOPNOTSUPP; 1906 1907 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1908 1909 /* keep the VLAN unless all ports are excluded */ 1910 vlan.valid = false; 1911 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1912 if (vlan.member[i] != 1913 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1914 vlan.valid = true; 1915 break; 1916 } 1917 } 1918 1919 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1920 if (err) 1921 return err; 1922 1923 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1924 } 1925 1926 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1927 const struct switchdev_obj_port_vlan *vlan) 1928 { 1929 struct mv88e6xxx_chip *chip = ds->priv; 1930 u16 pvid, vid; 1931 int err = 0; 1932 1933 if (!chip->info->max_vid) 1934 return -EOPNOTSUPP; 1935 1936 mv88e6xxx_reg_lock(chip); 1937 1938 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1939 if (err) 1940 goto unlock; 1941 1942 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1943 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1944 if (err) 1945 goto unlock; 1946 1947 if (vid == pvid) { 1948 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1949 if (err) 1950 goto unlock; 1951 } 1952 } 1953 1954 unlock: 1955 mv88e6xxx_reg_unlock(chip); 1956 1957 return err; 1958 } 1959 1960 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1961 const unsigned char *addr, u16 vid) 1962 { 1963 struct mv88e6xxx_chip *chip = ds->priv; 1964 int err; 1965 1966 mv88e6xxx_reg_lock(chip); 1967 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1968 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1969 mv88e6xxx_reg_unlock(chip); 1970 1971 return err; 1972 } 1973 1974 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1975 const unsigned char *addr, u16 vid) 1976 { 1977 struct mv88e6xxx_chip *chip = ds->priv; 1978 int err; 1979 1980 mv88e6xxx_reg_lock(chip); 1981 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 1982 mv88e6xxx_reg_unlock(chip); 1983 1984 return err; 1985 } 1986 1987 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1988 u16 fid, u16 vid, int port, 1989 dsa_fdb_dump_cb_t *cb, void *data) 1990 { 1991 struct mv88e6xxx_atu_entry addr; 1992 bool is_static; 1993 int err; 1994 1995 addr.state = 0; 1996 eth_broadcast_addr(addr.mac); 1997 1998 do { 1999 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2000 if (err) 2001 return err; 2002 2003 if (!addr.state) 2004 break; 2005 2006 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2007 continue; 2008 2009 if (!is_unicast_ether_addr(addr.mac)) 2010 continue; 2011 2012 is_static = (addr.state == 2013 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2014 err = cb(addr.mac, vid, is_static, data); 2015 if (err) 2016 return err; 2017 } while (!is_broadcast_ether_addr(addr.mac)); 2018 2019 return err; 2020 } 2021 2022 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2023 dsa_fdb_dump_cb_t *cb, void *data) 2024 { 2025 struct mv88e6xxx_vtu_entry vlan; 2026 u16 fid; 2027 int err; 2028 2029 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2030 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2031 if (err) 2032 return err; 2033 2034 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2035 if (err) 2036 return err; 2037 2038 /* Dump VLANs' Filtering Information Databases */ 2039 vlan.vid = chip->info->max_vid; 2040 vlan.valid = false; 2041 2042 do { 2043 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2044 if (err) 2045 return err; 2046 2047 if (!vlan.valid) 2048 break; 2049 2050 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2051 cb, data); 2052 if (err) 2053 return err; 2054 } while (vlan.vid < chip->info->max_vid); 2055 2056 return err; 2057 } 2058 2059 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2060 dsa_fdb_dump_cb_t *cb, void *data) 2061 { 2062 struct mv88e6xxx_chip *chip = ds->priv; 2063 int err; 2064 2065 mv88e6xxx_reg_lock(chip); 2066 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2067 mv88e6xxx_reg_unlock(chip); 2068 2069 return err; 2070 } 2071 2072 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2073 struct net_device *br) 2074 { 2075 struct dsa_switch *ds = chip->ds; 2076 struct dsa_switch_tree *dst = ds->dst; 2077 struct dsa_port *dp; 2078 int err; 2079 2080 list_for_each_entry(dp, &dst->ports, list) { 2081 if (dp->bridge_dev == br) { 2082 if (dp->ds == ds) { 2083 /* This is a local bridge group member, 2084 * remap its Port VLAN Map. 2085 */ 2086 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2087 if (err) 2088 return err; 2089 } else { 2090 /* This is an external bridge group member, 2091 * remap its cross-chip Port VLAN Table entry. 2092 */ 2093 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2094 dp->index); 2095 if (err) 2096 return err; 2097 } 2098 } 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2105 struct net_device *br) 2106 { 2107 struct mv88e6xxx_chip *chip = ds->priv; 2108 int err; 2109 2110 mv88e6xxx_reg_lock(chip); 2111 err = mv88e6xxx_bridge_map(chip, br); 2112 mv88e6xxx_reg_unlock(chip); 2113 2114 return err; 2115 } 2116 2117 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2118 struct net_device *br) 2119 { 2120 struct mv88e6xxx_chip *chip = ds->priv; 2121 2122 mv88e6xxx_reg_lock(chip); 2123 if (mv88e6xxx_bridge_map(chip, br) || 2124 mv88e6xxx_port_vlan_map(chip, port)) 2125 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2126 mv88e6xxx_reg_unlock(chip); 2127 } 2128 2129 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2130 int port, struct net_device *br) 2131 { 2132 struct mv88e6xxx_chip *chip = ds->priv; 2133 int err; 2134 2135 mv88e6xxx_reg_lock(chip); 2136 err = mv88e6xxx_pvt_map(chip, dev, port); 2137 mv88e6xxx_reg_unlock(chip); 2138 2139 return err; 2140 } 2141 2142 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2143 int port, struct net_device *br) 2144 { 2145 struct mv88e6xxx_chip *chip = ds->priv; 2146 2147 mv88e6xxx_reg_lock(chip); 2148 if (mv88e6xxx_pvt_map(chip, dev, port)) 2149 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2150 mv88e6xxx_reg_unlock(chip); 2151 } 2152 2153 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2154 { 2155 if (chip->info->ops->reset) 2156 return chip->info->ops->reset(chip); 2157 2158 return 0; 2159 } 2160 2161 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2162 { 2163 struct gpio_desc *gpiod = chip->reset; 2164 2165 /* If there is a GPIO connected to the reset pin, toggle it */ 2166 if (gpiod) { 2167 gpiod_set_value_cansleep(gpiod, 1); 2168 usleep_range(10000, 20000); 2169 gpiod_set_value_cansleep(gpiod, 0); 2170 usleep_range(10000, 20000); 2171 } 2172 } 2173 2174 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2175 { 2176 int i, err; 2177 2178 /* Set all ports to the Disabled state */ 2179 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2180 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2181 if (err) 2182 return err; 2183 } 2184 2185 /* Wait for transmit queues to drain, 2186 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2187 */ 2188 usleep_range(2000, 4000); 2189 2190 return 0; 2191 } 2192 2193 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2194 { 2195 int err; 2196 2197 err = mv88e6xxx_disable_ports(chip); 2198 if (err) 2199 return err; 2200 2201 mv88e6xxx_hardware_reset(chip); 2202 2203 return mv88e6xxx_software_reset(chip); 2204 } 2205 2206 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2207 enum mv88e6xxx_frame_mode frame, 2208 enum mv88e6xxx_egress_mode egress, u16 etype) 2209 { 2210 int err; 2211 2212 if (!chip->info->ops->port_set_frame_mode) 2213 return -EOPNOTSUPP; 2214 2215 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2216 if (err) 2217 return err; 2218 2219 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2220 if (err) 2221 return err; 2222 2223 if (chip->info->ops->port_set_ether_type) 2224 return chip->info->ops->port_set_ether_type(chip, port, etype); 2225 2226 return 0; 2227 } 2228 2229 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2230 { 2231 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2232 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2233 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2234 } 2235 2236 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2237 { 2238 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2239 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2240 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2241 } 2242 2243 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2244 { 2245 return mv88e6xxx_set_port_mode(chip, port, 2246 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2247 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2248 ETH_P_EDSA); 2249 } 2250 2251 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2252 { 2253 if (dsa_is_dsa_port(chip->ds, port)) 2254 return mv88e6xxx_set_port_mode_dsa(chip, port); 2255 2256 if (dsa_is_user_port(chip->ds, port)) 2257 return mv88e6xxx_set_port_mode_normal(chip, port); 2258 2259 /* Setup CPU port mode depending on its supported tag format */ 2260 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2261 return mv88e6xxx_set_port_mode_dsa(chip, port); 2262 2263 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2264 return mv88e6xxx_set_port_mode_edsa(chip, port); 2265 2266 return -EINVAL; 2267 } 2268 2269 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2270 { 2271 bool message = dsa_is_dsa_port(chip->ds, port); 2272 2273 return mv88e6xxx_port_set_message_port(chip, port, message); 2274 } 2275 2276 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2277 { 2278 struct dsa_switch *ds = chip->ds; 2279 bool flood; 2280 2281 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2282 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2283 if (chip->info->ops->port_set_egress_floods) 2284 return chip->info->ops->port_set_egress_floods(chip, port, 2285 flood, flood); 2286 2287 return 0; 2288 } 2289 2290 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2291 { 2292 struct mv88e6xxx_port *mvp = dev_id; 2293 struct mv88e6xxx_chip *chip = mvp->chip; 2294 irqreturn_t ret = IRQ_NONE; 2295 int port = mvp->port; 2296 u8 lane; 2297 2298 mv88e6xxx_reg_lock(chip); 2299 lane = mv88e6xxx_serdes_get_lane(chip, port); 2300 if (lane) 2301 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2302 mv88e6xxx_reg_unlock(chip); 2303 2304 return ret; 2305 } 2306 2307 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2308 u8 lane) 2309 { 2310 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2311 unsigned int irq; 2312 int err; 2313 2314 /* Nothing to request if this SERDES port has no IRQ */ 2315 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2316 if (!irq) 2317 return 0; 2318 2319 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2320 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2321 2322 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2323 mv88e6xxx_reg_unlock(chip); 2324 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2325 IRQF_ONESHOT, dev_id->serdes_irq_name, 2326 dev_id); 2327 mv88e6xxx_reg_lock(chip); 2328 if (err) 2329 return err; 2330 2331 dev_id->serdes_irq = irq; 2332 2333 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2334 } 2335 2336 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2337 u8 lane) 2338 { 2339 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2340 unsigned int irq = dev_id->serdes_irq; 2341 int err; 2342 2343 /* Nothing to free if no IRQ has been requested */ 2344 if (!irq) 2345 return 0; 2346 2347 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2348 2349 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2350 mv88e6xxx_reg_unlock(chip); 2351 free_irq(irq, dev_id); 2352 mv88e6xxx_reg_lock(chip); 2353 2354 dev_id->serdes_irq = 0; 2355 2356 return err; 2357 } 2358 2359 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2360 bool on) 2361 { 2362 u8 lane; 2363 int err; 2364 2365 lane = mv88e6xxx_serdes_get_lane(chip, port); 2366 if (!lane) 2367 return 0; 2368 2369 if (on) { 2370 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2371 if (err) 2372 return err; 2373 2374 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2375 } else { 2376 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2377 if (err) 2378 return err; 2379 2380 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2381 } 2382 2383 return err; 2384 } 2385 2386 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2387 { 2388 struct dsa_switch *ds = chip->ds; 2389 int upstream_port; 2390 int err; 2391 2392 upstream_port = dsa_upstream_port(ds, port); 2393 if (chip->info->ops->port_set_upstream_port) { 2394 err = chip->info->ops->port_set_upstream_port(chip, port, 2395 upstream_port); 2396 if (err) 2397 return err; 2398 } 2399 2400 if (port == upstream_port) { 2401 if (chip->info->ops->set_cpu_port) { 2402 err = chip->info->ops->set_cpu_port(chip, 2403 upstream_port); 2404 if (err) 2405 return err; 2406 } 2407 2408 if (chip->info->ops->set_egress_port) { 2409 err = chip->info->ops->set_egress_port(chip, 2410 MV88E6XXX_EGRESS_DIR_INGRESS, 2411 upstream_port); 2412 if (err) 2413 return err; 2414 2415 err = chip->info->ops->set_egress_port(chip, 2416 MV88E6XXX_EGRESS_DIR_EGRESS, 2417 upstream_port); 2418 if (err) 2419 return err; 2420 } 2421 } 2422 2423 return 0; 2424 } 2425 2426 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2427 { 2428 struct dsa_switch *ds = chip->ds; 2429 int err; 2430 u16 reg; 2431 2432 chip->ports[port].chip = chip; 2433 chip->ports[port].port = port; 2434 2435 /* MAC Forcing register: don't force link, speed, duplex or flow control 2436 * state to any particular values on physical ports, but force the CPU 2437 * port and all DSA ports to their maximum bandwidth and full duplex. 2438 */ 2439 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2440 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2441 SPEED_MAX, DUPLEX_FULL, 2442 PAUSE_OFF, 2443 PHY_INTERFACE_MODE_NA); 2444 else 2445 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2446 SPEED_UNFORCED, DUPLEX_UNFORCED, 2447 PAUSE_ON, 2448 PHY_INTERFACE_MODE_NA); 2449 if (err) 2450 return err; 2451 2452 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2453 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2454 * tunneling, determine priority by looking at 802.1p and IP 2455 * priority fields (IP prio has precedence), and set STP state 2456 * to Forwarding. 2457 * 2458 * If this is the CPU link, use DSA or EDSA tagging depending 2459 * on which tagging mode was configured. 2460 * 2461 * If this is a link to another switch, use DSA tagging mode. 2462 * 2463 * If this is the upstream port for this switch, enable 2464 * forwarding of unknown unicasts and multicasts. 2465 */ 2466 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2467 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2468 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2469 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2470 if (err) 2471 return err; 2472 2473 err = mv88e6xxx_setup_port_mode(chip, port); 2474 if (err) 2475 return err; 2476 2477 err = mv88e6xxx_setup_egress_floods(chip, port); 2478 if (err) 2479 return err; 2480 2481 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2482 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2483 * untagged frames on this port, do a destination address lookup on all 2484 * received packets as usual, disable ARP mirroring and don't send a 2485 * copy of all transmitted/received frames on this port to the CPU. 2486 */ 2487 err = mv88e6xxx_port_set_map_da(chip, port); 2488 if (err) 2489 return err; 2490 2491 err = mv88e6xxx_setup_upstream_port(chip, port); 2492 if (err) 2493 return err; 2494 2495 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2496 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2497 if (err) 2498 return err; 2499 2500 if (chip->info->ops->port_set_jumbo_size) { 2501 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2502 if (err) 2503 return err; 2504 } 2505 2506 /* Port Association Vector: when learning source addresses 2507 * of packets, add the address to the address database using 2508 * a port bitmap that has only the bit for this port set and 2509 * the other bits clear. 2510 */ 2511 reg = 1 << port; 2512 /* Disable learning for CPU port */ 2513 if (dsa_is_cpu_port(ds, port)) 2514 reg = 0; 2515 2516 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2517 reg); 2518 if (err) 2519 return err; 2520 2521 /* Egress rate control 2: disable egress rate control. */ 2522 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2523 0x0000); 2524 if (err) 2525 return err; 2526 2527 if (chip->info->ops->port_pause_limit) { 2528 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2529 if (err) 2530 return err; 2531 } 2532 2533 if (chip->info->ops->port_disable_learn_limit) { 2534 err = chip->info->ops->port_disable_learn_limit(chip, port); 2535 if (err) 2536 return err; 2537 } 2538 2539 if (chip->info->ops->port_disable_pri_override) { 2540 err = chip->info->ops->port_disable_pri_override(chip, port); 2541 if (err) 2542 return err; 2543 } 2544 2545 if (chip->info->ops->port_tag_remap) { 2546 err = chip->info->ops->port_tag_remap(chip, port); 2547 if (err) 2548 return err; 2549 } 2550 2551 if (chip->info->ops->port_egress_rate_limiting) { 2552 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2553 if (err) 2554 return err; 2555 } 2556 2557 if (chip->info->ops->port_setup_message_port) { 2558 err = chip->info->ops->port_setup_message_port(chip, port); 2559 if (err) 2560 return err; 2561 } 2562 2563 /* Port based VLAN map: give each port the same default address 2564 * database, and allow bidirectional communication between the 2565 * CPU and DSA port(s), and the other ports. 2566 */ 2567 err = mv88e6xxx_port_set_fid(chip, port, 0); 2568 if (err) 2569 return err; 2570 2571 err = mv88e6xxx_port_vlan_map(chip, port); 2572 if (err) 2573 return err; 2574 2575 /* Default VLAN ID and priority: don't set a default VLAN 2576 * ID, and set the default packet priority to zero. 2577 */ 2578 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2579 } 2580 2581 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2582 struct phy_device *phydev) 2583 { 2584 struct mv88e6xxx_chip *chip = ds->priv; 2585 int err; 2586 2587 mv88e6xxx_reg_lock(chip); 2588 err = mv88e6xxx_serdes_power(chip, port, true); 2589 mv88e6xxx_reg_unlock(chip); 2590 2591 return err; 2592 } 2593 2594 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2595 { 2596 struct mv88e6xxx_chip *chip = ds->priv; 2597 2598 mv88e6xxx_reg_lock(chip); 2599 if (mv88e6xxx_serdes_power(chip, port, false)) 2600 dev_err(chip->dev, "failed to power off SERDES\n"); 2601 mv88e6xxx_reg_unlock(chip); 2602 } 2603 2604 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2605 unsigned int ageing_time) 2606 { 2607 struct mv88e6xxx_chip *chip = ds->priv; 2608 int err; 2609 2610 mv88e6xxx_reg_lock(chip); 2611 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2612 mv88e6xxx_reg_unlock(chip); 2613 2614 return err; 2615 } 2616 2617 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2618 { 2619 int err; 2620 2621 /* Initialize the statistics unit */ 2622 if (chip->info->ops->stats_set_histogram) { 2623 err = chip->info->ops->stats_set_histogram(chip); 2624 if (err) 2625 return err; 2626 } 2627 2628 return mv88e6xxx_g1_stats_clear(chip); 2629 } 2630 2631 /* Check if the errata has already been applied. */ 2632 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2633 { 2634 int port; 2635 int err; 2636 u16 val; 2637 2638 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2639 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2640 if (err) { 2641 dev_err(chip->dev, 2642 "Error reading hidden register: %d\n", err); 2643 return false; 2644 } 2645 if (val != 0x01c0) 2646 return false; 2647 } 2648 2649 return true; 2650 } 2651 2652 /* The 6390 copper ports have an errata which require poking magic 2653 * values into undocumented hidden registers and then performing a 2654 * software reset. 2655 */ 2656 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2657 { 2658 int port; 2659 int err; 2660 2661 if (mv88e6390_setup_errata_applied(chip)) 2662 return 0; 2663 2664 /* Set the ports into blocking mode */ 2665 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2666 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2667 if (err) 2668 return err; 2669 } 2670 2671 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2672 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2673 if (err) 2674 return err; 2675 } 2676 2677 return mv88e6xxx_software_reset(chip); 2678 } 2679 2680 enum mv88e6xxx_devlink_param_id { 2681 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2682 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2683 }; 2684 2685 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2686 struct devlink_param_gset_ctx *ctx) 2687 { 2688 struct mv88e6xxx_chip *chip = ds->priv; 2689 int err; 2690 2691 mv88e6xxx_reg_lock(chip); 2692 2693 switch (id) { 2694 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2695 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2696 break; 2697 default: 2698 err = -EOPNOTSUPP; 2699 break; 2700 } 2701 2702 mv88e6xxx_reg_unlock(chip); 2703 2704 return err; 2705 } 2706 2707 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2708 struct devlink_param_gset_ctx *ctx) 2709 { 2710 struct mv88e6xxx_chip *chip = ds->priv; 2711 int err; 2712 2713 mv88e6xxx_reg_lock(chip); 2714 2715 switch (id) { 2716 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2717 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2718 break; 2719 default: 2720 err = -EOPNOTSUPP; 2721 break; 2722 } 2723 2724 mv88e6xxx_reg_unlock(chip); 2725 2726 return err; 2727 } 2728 2729 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2730 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2731 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2732 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2733 }; 2734 2735 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2736 { 2737 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2738 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2739 } 2740 2741 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2742 { 2743 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2744 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2745 } 2746 2747 enum mv88e6xxx_devlink_resource_id { 2748 MV88E6XXX_RESOURCE_ID_ATU, 2749 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2750 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2751 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2752 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2753 }; 2754 2755 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2756 u16 bin) 2757 { 2758 u16 occupancy = 0; 2759 int err; 2760 2761 mv88e6xxx_reg_lock(chip); 2762 2763 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2764 bin); 2765 if (err) { 2766 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2767 goto unlock; 2768 } 2769 2770 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2771 if (err) { 2772 dev_err(chip->dev, "failed to perform ATU get next\n"); 2773 goto unlock; 2774 } 2775 2776 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2777 if (err) { 2778 dev_err(chip->dev, "failed to get ATU stats\n"); 2779 goto unlock; 2780 } 2781 2782 unlock: 2783 mv88e6xxx_reg_unlock(chip); 2784 2785 return occupancy; 2786 } 2787 2788 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2789 { 2790 struct mv88e6xxx_chip *chip = priv; 2791 2792 return mv88e6xxx_devlink_atu_bin_get(chip, 2793 MV88E6XXX_G2_ATU_STATS_BIN_0); 2794 } 2795 2796 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2797 { 2798 struct mv88e6xxx_chip *chip = priv; 2799 2800 return mv88e6xxx_devlink_atu_bin_get(chip, 2801 MV88E6XXX_G2_ATU_STATS_BIN_1); 2802 } 2803 2804 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2805 { 2806 struct mv88e6xxx_chip *chip = priv; 2807 2808 return mv88e6xxx_devlink_atu_bin_get(chip, 2809 MV88E6XXX_G2_ATU_STATS_BIN_2); 2810 } 2811 2812 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2813 { 2814 struct mv88e6xxx_chip *chip = priv; 2815 2816 return mv88e6xxx_devlink_atu_bin_get(chip, 2817 MV88E6XXX_G2_ATU_STATS_BIN_3); 2818 } 2819 2820 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2821 { 2822 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2823 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2824 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2825 mv88e6xxx_devlink_atu_bin_3_get(priv); 2826 } 2827 2828 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2829 { 2830 struct devlink_resource_size_params size_params; 2831 struct mv88e6xxx_chip *chip = ds->priv; 2832 int err; 2833 2834 devlink_resource_size_params_init(&size_params, 2835 mv88e6xxx_num_macs(chip), 2836 mv88e6xxx_num_macs(chip), 2837 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2838 2839 err = dsa_devlink_resource_register(ds, "ATU", 2840 mv88e6xxx_num_macs(chip), 2841 MV88E6XXX_RESOURCE_ID_ATU, 2842 DEVLINK_RESOURCE_ID_PARENT_TOP, 2843 &size_params); 2844 if (err) 2845 goto out; 2846 2847 devlink_resource_size_params_init(&size_params, 2848 mv88e6xxx_num_macs(chip) / 4, 2849 mv88e6xxx_num_macs(chip) / 4, 2850 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2851 2852 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2853 mv88e6xxx_num_macs(chip) / 4, 2854 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2855 MV88E6XXX_RESOURCE_ID_ATU, 2856 &size_params); 2857 if (err) 2858 goto out; 2859 2860 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 2861 mv88e6xxx_num_macs(chip) / 4, 2862 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2863 MV88E6XXX_RESOURCE_ID_ATU, 2864 &size_params); 2865 if (err) 2866 goto out; 2867 2868 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 2869 mv88e6xxx_num_macs(chip) / 4, 2870 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2871 MV88E6XXX_RESOURCE_ID_ATU, 2872 &size_params); 2873 if (err) 2874 goto out; 2875 2876 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 2877 mv88e6xxx_num_macs(chip) / 4, 2878 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2879 MV88E6XXX_RESOURCE_ID_ATU, 2880 &size_params); 2881 if (err) 2882 goto out; 2883 2884 dsa_devlink_resource_occ_get_register(ds, 2885 MV88E6XXX_RESOURCE_ID_ATU, 2886 mv88e6xxx_devlink_atu_get, 2887 chip); 2888 2889 dsa_devlink_resource_occ_get_register(ds, 2890 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2891 mv88e6xxx_devlink_atu_bin_0_get, 2892 chip); 2893 2894 dsa_devlink_resource_occ_get_register(ds, 2895 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2896 mv88e6xxx_devlink_atu_bin_1_get, 2897 chip); 2898 2899 dsa_devlink_resource_occ_get_register(ds, 2900 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2901 mv88e6xxx_devlink_atu_bin_2_get, 2902 chip); 2903 2904 dsa_devlink_resource_occ_get_register(ds, 2905 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2906 mv88e6xxx_devlink_atu_bin_3_get, 2907 chip); 2908 2909 return 0; 2910 2911 out: 2912 dsa_devlink_resources_unregister(ds); 2913 return err; 2914 } 2915 2916 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2917 { 2918 mv88e6xxx_teardown_devlink_params(ds); 2919 dsa_devlink_resources_unregister(ds); 2920 } 2921 2922 static int mv88e6xxx_setup(struct dsa_switch *ds) 2923 { 2924 struct mv88e6xxx_chip *chip = ds->priv; 2925 u8 cmode; 2926 int err; 2927 int i; 2928 2929 chip->ds = ds; 2930 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2931 2932 mv88e6xxx_reg_lock(chip); 2933 2934 if (chip->info->ops->setup_errata) { 2935 err = chip->info->ops->setup_errata(chip); 2936 if (err) 2937 goto unlock; 2938 } 2939 2940 /* Cache the cmode of each port. */ 2941 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2942 if (chip->info->ops->port_get_cmode) { 2943 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2944 if (err) 2945 goto unlock; 2946 2947 chip->ports[i].cmode = cmode; 2948 } 2949 } 2950 2951 /* Setup Switch Port Registers */ 2952 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2953 if (dsa_is_unused_port(ds, i)) 2954 continue; 2955 2956 /* Prevent the use of an invalid port. */ 2957 if (mv88e6xxx_is_invalid_port(chip, i)) { 2958 dev_err(chip->dev, "port %d is invalid\n", i); 2959 err = -EINVAL; 2960 goto unlock; 2961 } 2962 2963 err = mv88e6xxx_setup_port(chip, i); 2964 if (err) 2965 goto unlock; 2966 } 2967 2968 err = mv88e6xxx_irl_setup(chip); 2969 if (err) 2970 goto unlock; 2971 2972 err = mv88e6xxx_mac_setup(chip); 2973 if (err) 2974 goto unlock; 2975 2976 err = mv88e6xxx_phy_setup(chip); 2977 if (err) 2978 goto unlock; 2979 2980 err = mv88e6xxx_vtu_setup(chip); 2981 if (err) 2982 goto unlock; 2983 2984 err = mv88e6xxx_pvt_setup(chip); 2985 if (err) 2986 goto unlock; 2987 2988 err = mv88e6xxx_atu_setup(chip); 2989 if (err) 2990 goto unlock; 2991 2992 err = mv88e6xxx_broadcast_setup(chip, 0); 2993 if (err) 2994 goto unlock; 2995 2996 err = mv88e6xxx_pot_setup(chip); 2997 if (err) 2998 goto unlock; 2999 3000 err = mv88e6xxx_rmu_setup(chip); 3001 if (err) 3002 goto unlock; 3003 3004 err = mv88e6xxx_rsvd2cpu_setup(chip); 3005 if (err) 3006 goto unlock; 3007 3008 err = mv88e6xxx_trunk_setup(chip); 3009 if (err) 3010 goto unlock; 3011 3012 err = mv88e6xxx_devmap_setup(chip); 3013 if (err) 3014 goto unlock; 3015 3016 err = mv88e6xxx_pri_setup(chip); 3017 if (err) 3018 goto unlock; 3019 3020 /* Setup PTP Hardware Clock and timestamping */ 3021 if (chip->info->ptp_support) { 3022 err = mv88e6xxx_ptp_setup(chip); 3023 if (err) 3024 goto unlock; 3025 3026 err = mv88e6xxx_hwtstamp_setup(chip); 3027 if (err) 3028 goto unlock; 3029 } 3030 3031 err = mv88e6xxx_stats_setup(chip); 3032 if (err) 3033 goto unlock; 3034 3035 unlock: 3036 mv88e6xxx_reg_unlock(chip); 3037 3038 if (err) 3039 return err; 3040 3041 /* Have to be called without holding the register lock, since 3042 * they take the devlink lock, and we later take the locks in 3043 * the reverse order when getting/setting parameters or 3044 * resource occupancy. 3045 */ 3046 err = mv88e6xxx_setup_devlink_resources(ds); 3047 if (err) 3048 return err; 3049 3050 err = mv88e6xxx_setup_devlink_params(ds); 3051 if (err) 3052 dsa_devlink_resources_unregister(ds); 3053 3054 return err; 3055 } 3056 3057 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3058 { 3059 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3060 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3061 u16 val; 3062 int err; 3063 3064 if (!chip->info->ops->phy_read) 3065 return -EOPNOTSUPP; 3066 3067 mv88e6xxx_reg_lock(chip); 3068 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3069 mv88e6xxx_reg_unlock(chip); 3070 3071 if (reg == MII_PHYSID2) { 3072 /* Some internal PHYs don't have a model number. */ 3073 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3074 /* Then there is the 6165 family. It gets is 3075 * PHYs correct. But it can also have two 3076 * SERDES interfaces in the PHY address 3077 * space. And these don't have a model 3078 * number. But they are not PHYs, so we don't 3079 * want to give them something a PHY driver 3080 * will recognise. 3081 * 3082 * Use the mv88e6390 family model number 3083 * instead, for anything which really could be 3084 * a PHY, 3085 */ 3086 if (!(val & 0x3f0)) 3087 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3088 } 3089 3090 return err ? err : val; 3091 } 3092 3093 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3094 { 3095 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3096 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3097 int err; 3098 3099 if (!chip->info->ops->phy_write) 3100 return -EOPNOTSUPP; 3101 3102 mv88e6xxx_reg_lock(chip); 3103 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3104 mv88e6xxx_reg_unlock(chip); 3105 3106 return err; 3107 } 3108 3109 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3110 struct device_node *np, 3111 bool external) 3112 { 3113 static int index; 3114 struct mv88e6xxx_mdio_bus *mdio_bus; 3115 struct mii_bus *bus; 3116 int err; 3117 3118 if (external) { 3119 mv88e6xxx_reg_lock(chip); 3120 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3121 mv88e6xxx_reg_unlock(chip); 3122 3123 if (err) 3124 return err; 3125 } 3126 3127 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3128 if (!bus) 3129 return -ENOMEM; 3130 3131 mdio_bus = bus->priv; 3132 mdio_bus->bus = bus; 3133 mdio_bus->chip = chip; 3134 INIT_LIST_HEAD(&mdio_bus->list); 3135 mdio_bus->external = external; 3136 3137 if (np) { 3138 bus->name = np->full_name; 3139 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3140 } else { 3141 bus->name = "mv88e6xxx SMI"; 3142 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3143 } 3144 3145 bus->read = mv88e6xxx_mdio_read; 3146 bus->write = mv88e6xxx_mdio_write; 3147 bus->parent = chip->dev; 3148 3149 if (!external) { 3150 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3151 if (err) 3152 return err; 3153 } 3154 3155 err = of_mdiobus_register(bus, np); 3156 if (err) { 3157 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3158 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3159 return err; 3160 } 3161 3162 if (external) 3163 list_add_tail(&mdio_bus->list, &chip->mdios); 3164 else 3165 list_add(&mdio_bus->list, &chip->mdios); 3166 3167 return 0; 3168 } 3169 3170 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3171 { .compatible = "marvell,mv88e6xxx-mdio-external", 3172 .data = (void *)true }, 3173 { }, 3174 }; 3175 3176 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3177 3178 { 3179 struct mv88e6xxx_mdio_bus *mdio_bus; 3180 struct mii_bus *bus; 3181 3182 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3183 bus = mdio_bus->bus; 3184 3185 if (!mdio_bus->external) 3186 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3187 3188 mdiobus_unregister(bus); 3189 } 3190 } 3191 3192 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3193 struct device_node *np) 3194 { 3195 const struct of_device_id *match; 3196 struct device_node *child; 3197 int err; 3198 3199 /* Always register one mdio bus for the internal/default mdio 3200 * bus. This maybe represented in the device tree, but is 3201 * optional. 3202 */ 3203 child = of_get_child_by_name(np, "mdio"); 3204 err = mv88e6xxx_mdio_register(chip, child, false); 3205 if (err) 3206 return err; 3207 3208 /* Walk the device tree, and see if there are any other nodes 3209 * which say they are compatible with the external mdio 3210 * bus. 3211 */ 3212 for_each_available_child_of_node(np, child) { 3213 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3214 if (match) { 3215 err = mv88e6xxx_mdio_register(chip, child, true); 3216 if (err) { 3217 mv88e6xxx_mdios_unregister(chip); 3218 of_node_put(child); 3219 return err; 3220 } 3221 } 3222 } 3223 3224 return 0; 3225 } 3226 3227 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3228 { 3229 struct mv88e6xxx_chip *chip = ds->priv; 3230 3231 return chip->eeprom_len; 3232 } 3233 3234 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3235 struct ethtool_eeprom *eeprom, u8 *data) 3236 { 3237 struct mv88e6xxx_chip *chip = ds->priv; 3238 int err; 3239 3240 if (!chip->info->ops->get_eeprom) 3241 return -EOPNOTSUPP; 3242 3243 mv88e6xxx_reg_lock(chip); 3244 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3245 mv88e6xxx_reg_unlock(chip); 3246 3247 if (err) 3248 return err; 3249 3250 eeprom->magic = 0xc3ec4951; 3251 3252 return 0; 3253 } 3254 3255 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3256 struct ethtool_eeprom *eeprom, u8 *data) 3257 { 3258 struct mv88e6xxx_chip *chip = ds->priv; 3259 int err; 3260 3261 if (!chip->info->ops->set_eeprom) 3262 return -EOPNOTSUPP; 3263 3264 if (eeprom->magic != 0xc3ec4951) 3265 return -EINVAL; 3266 3267 mv88e6xxx_reg_lock(chip); 3268 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3269 mv88e6xxx_reg_unlock(chip); 3270 3271 return err; 3272 } 3273 3274 static const struct mv88e6xxx_ops mv88e6085_ops = { 3275 /* MV88E6XXX_FAMILY_6097 */ 3276 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3277 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3278 .irl_init_all = mv88e6352_g2_irl_init_all, 3279 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3280 .phy_read = mv88e6185_phy_ppu_read, 3281 .phy_write = mv88e6185_phy_ppu_write, 3282 .port_set_link = mv88e6xxx_port_set_link, 3283 .port_set_duplex = mv88e6xxx_port_set_duplex, 3284 .port_set_speed = mv88e6185_port_set_speed, 3285 .port_tag_remap = mv88e6095_port_tag_remap, 3286 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3287 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3288 .port_set_ether_type = mv88e6351_port_set_ether_type, 3289 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3290 .port_pause_limit = mv88e6097_port_pause_limit, 3291 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3292 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3293 .port_link_state = mv88e6352_port_link_state, 3294 .port_get_cmode = mv88e6185_port_get_cmode, 3295 .port_setup_message_port = mv88e6xxx_setup_message_port, 3296 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3297 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3298 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3299 .stats_get_strings = mv88e6095_stats_get_strings, 3300 .stats_get_stats = mv88e6095_stats_get_stats, 3301 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3302 .set_egress_port = mv88e6095_g1_set_egress_port, 3303 .watchdog_ops = &mv88e6097_watchdog_ops, 3304 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3305 .pot_clear = mv88e6xxx_g2_pot_clear, 3306 .ppu_enable = mv88e6185_g1_ppu_enable, 3307 .ppu_disable = mv88e6185_g1_ppu_disable, 3308 .reset = mv88e6185_g1_reset, 3309 .rmu_disable = mv88e6085_g1_rmu_disable, 3310 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3311 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3312 .phylink_validate = mv88e6185_phylink_validate, 3313 }; 3314 3315 static const struct mv88e6xxx_ops mv88e6095_ops = { 3316 /* MV88E6XXX_FAMILY_6095 */ 3317 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3318 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3319 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3320 .phy_read = mv88e6185_phy_ppu_read, 3321 .phy_write = mv88e6185_phy_ppu_write, 3322 .port_set_link = mv88e6xxx_port_set_link, 3323 .port_set_duplex = mv88e6xxx_port_set_duplex, 3324 .port_set_speed = mv88e6185_port_set_speed, 3325 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3326 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3327 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3328 .port_link_state = mv88e6185_port_link_state, 3329 .port_get_cmode = mv88e6185_port_get_cmode, 3330 .port_setup_message_port = mv88e6xxx_setup_message_port, 3331 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3332 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3333 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3334 .stats_get_strings = mv88e6095_stats_get_strings, 3335 .stats_get_stats = mv88e6095_stats_get_stats, 3336 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3337 .ppu_enable = mv88e6185_g1_ppu_enable, 3338 .ppu_disable = mv88e6185_g1_ppu_disable, 3339 .reset = mv88e6185_g1_reset, 3340 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3341 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3342 .phylink_validate = mv88e6185_phylink_validate, 3343 }; 3344 3345 static const struct mv88e6xxx_ops mv88e6097_ops = { 3346 /* MV88E6XXX_FAMILY_6097 */ 3347 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3348 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3349 .irl_init_all = mv88e6352_g2_irl_init_all, 3350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3351 .phy_read = mv88e6xxx_g2_smi_phy_read, 3352 .phy_write = mv88e6xxx_g2_smi_phy_write, 3353 .port_set_link = mv88e6xxx_port_set_link, 3354 .port_set_duplex = mv88e6xxx_port_set_duplex, 3355 .port_set_speed = mv88e6185_port_set_speed, 3356 .port_tag_remap = mv88e6095_port_tag_remap, 3357 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3358 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3359 .port_set_ether_type = mv88e6351_port_set_ether_type, 3360 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3361 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3362 .port_pause_limit = mv88e6097_port_pause_limit, 3363 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3364 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3365 .port_link_state = mv88e6352_port_link_state, 3366 .port_get_cmode = mv88e6185_port_get_cmode, 3367 .port_setup_message_port = mv88e6xxx_setup_message_port, 3368 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3369 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3370 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3371 .stats_get_strings = mv88e6095_stats_get_strings, 3372 .stats_get_stats = mv88e6095_stats_get_stats, 3373 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3374 .set_egress_port = mv88e6095_g1_set_egress_port, 3375 .watchdog_ops = &mv88e6097_watchdog_ops, 3376 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3377 .pot_clear = mv88e6xxx_g2_pot_clear, 3378 .reset = mv88e6352_g1_reset, 3379 .rmu_disable = mv88e6085_g1_rmu_disable, 3380 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3381 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3382 .phylink_validate = mv88e6185_phylink_validate, 3383 }; 3384 3385 static const struct mv88e6xxx_ops mv88e6123_ops = { 3386 /* MV88E6XXX_FAMILY_6165 */ 3387 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3388 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3389 .irl_init_all = mv88e6352_g2_irl_init_all, 3390 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3391 .phy_read = mv88e6xxx_g2_smi_phy_read, 3392 .phy_write = mv88e6xxx_g2_smi_phy_write, 3393 .port_set_link = mv88e6xxx_port_set_link, 3394 .port_set_duplex = mv88e6xxx_port_set_duplex, 3395 .port_set_speed = mv88e6185_port_set_speed, 3396 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3397 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3400 .port_link_state = mv88e6352_port_link_state, 3401 .port_get_cmode = mv88e6185_port_get_cmode, 3402 .port_setup_message_port = mv88e6xxx_setup_message_port, 3403 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3405 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3406 .stats_get_strings = mv88e6095_stats_get_strings, 3407 .stats_get_stats = mv88e6095_stats_get_stats, 3408 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3409 .set_egress_port = mv88e6095_g1_set_egress_port, 3410 .watchdog_ops = &mv88e6097_watchdog_ops, 3411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3412 .pot_clear = mv88e6xxx_g2_pot_clear, 3413 .reset = mv88e6352_g1_reset, 3414 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3415 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3416 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3417 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3418 .phylink_validate = mv88e6185_phylink_validate, 3419 }; 3420 3421 static const struct mv88e6xxx_ops mv88e6131_ops = { 3422 /* MV88E6XXX_FAMILY_6185 */ 3423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3424 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3425 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3426 .phy_read = mv88e6185_phy_ppu_read, 3427 .phy_write = mv88e6185_phy_ppu_write, 3428 .port_set_link = mv88e6xxx_port_set_link, 3429 .port_set_duplex = mv88e6xxx_port_set_duplex, 3430 .port_set_speed = mv88e6185_port_set_speed, 3431 .port_tag_remap = mv88e6095_port_tag_remap, 3432 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3433 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3434 .port_set_ether_type = mv88e6351_port_set_ether_type, 3435 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3436 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3437 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3438 .port_pause_limit = mv88e6097_port_pause_limit, 3439 .port_set_pause = mv88e6185_port_set_pause, 3440 .port_link_state = mv88e6352_port_link_state, 3441 .port_get_cmode = mv88e6185_port_get_cmode, 3442 .port_setup_message_port = mv88e6xxx_setup_message_port, 3443 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3444 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3445 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3446 .stats_get_strings = mv88e6095_stats_get_strings, 3447 .stats_get_stats = mv88e6095_stats_get_stats, 3448 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3449 .set_egress_port = mv88e6095_g1_set_egress_port, 3450 .watchdog_ops = &mv88e6097_watchdog_ops, 3451 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3452 .ppu_enable = mv88e6185_g1_ppu_enable, 3453 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3454 .ppu_disable = mv88e6185_g1_ppu_disable, 3455 .reset = mv88e6185_g1_reset, 3456 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3457 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3458 .phylink_validate = mv88e6185_phylink_validate, 3459 }; 3460 3461 static const struct mv88e6xxx_ops mv88e6141_ops = { 3462 /* MV88E6XXX_FAMILY_6341 */ 3463 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3464 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3465 .irl_init_all = mv88e6352_g2_irl_init_all, 3466 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3467 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3468 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3469 .phy_read = mv88e6xxx_g2_smi_phy_read, 3470 .phy_write = mv88e6xxx_g2_smi_phy_write, 3471 .port_set_link = mv88e6xxx_port_set_link, 3472 .port_set_duplex = mv88e6xxx_port_set_duplex, 3473 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3474 .port_set_speed = mv88e6341_port_set_speed, 3475 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3476 .port_tag_remap = mv88e6095_port_tag_remap, 3477 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3478 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3479 .port_set_ether_type = mv88e6351_port_set_ether_type, 3480 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3481 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3482 .port_pause_limit = mv88e6097_port_pause_limit, 3483 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3484 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3485 .port_link_state = mv88e6352_port_link_state, 3486 .port_get_cmode = mv88e6352_port_get_cmode, 3487 .port_set_cmode = mv88e6341_port_set_cmode, 3488 .port_setup_message_port = mv88e6xxx_setup_message_port, 3489 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3491 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3492 .stats_get_strings = mv88e6320_stats_get_strings, 3493 .stats_get_stats = mv88e6390_stats_get_stats, 3494 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3495 .set_egress_port = mv88e6390_g1_set_egress_port, 3496 .watchdog_ops = &mv88e6390_watchdog_ops, 3497 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3498 .pot_clear = mv88e6xxx_g2_pot_clear, 3499 .reset = mv88e6352_g1_reset, 3500 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3501 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3502 .serdes_power = mv88e6390_serdes_power, 3503 .serdes_get_lane = mv88e6341_serdes_get_lane, 3504 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3505 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3506 .serdes_irq_status = mv88e6390_serdes_irq_status, 3507 .gpio_ops = &mv88e6352_gpio_ops, 3508 .phylink_validate = mv88e6341_phylink_validate, 3509 }; 3510 3511 static const struct mv88e6xxx_ops mv88e6161_ops = { 3512 /* MV88E6XXX_FAMILY_6165 */ 3513 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3514 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3515 .irl_init_all = mv88e6352_g2_irl_init_all, 3516 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3517 .phy_read = mv88e6xxx_g2_smi_phy_read, 3518 .phy_write = mv88e6xxx_g2_smi_phy_write, 3519 .port_set_link = mv88e6xxx_port_set_link, 3520 .port_set_duplex = mv88e6xxx_port_set_duplex, 3521 .port_set_speed = mv88e6185_port_set_speed, 3522 .port_tag_remap = mv88e6095_port_tag_remap, 3523 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3524 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3525 .port_set_ether_type = mv88e6351_port_set_ether_type, 3526 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3527 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3528 .port_pause_limit = mv88e6097_port_pause_limit, 3529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3531 .port_link_state = mv88e6352_port_link_state, 3532 .port_get_cmode = mv88e6185_port_get_cmode, 3533 .port_setup_message_port = mv88e6xxx_setup_message_port, 3534 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3535 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3536 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3537 .stats_get_strings = mv88e6095_stats_get_strings, 3538 .stats_get_stats = mv88e6095_stats_get_stats, 3539 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3540 .set_egress_port = mv88e6095_g1_set_egress_port, 3541 .watchdog_ops = &mv88e6097_watchdog_ops, 3542 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3543 .pot_clear = mv88e6xxx_g2_pot_clear, 3544 .reset = mv88e6352_g1_reset, 3545 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3546 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3547 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3548 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3549 .avb_ops = &mv88e6165_avb_ops, 3550 .ptp_ops = &mv88e6165_ptp_ops, 3551 .phylink_validate = mv88e6185_phylink_validate, 3552 }; 3553 3554 static const struct mv88e6xxx_ops mv88e6165_ops = { 3555 /* MV88E6XXX_FAMILY_6165 */ 3556 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3557 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3558 .irl_init_all = mv88e6352_g2_irl_init_all, 3559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3560 .phy_read = mv88e6165_phy_read, 3561 .phy_write = mv88e6165_phy_write, 3562 .port_set_link = mv88e6xxx_port_set_link, 3563 .port_set_duplex = mv88e6xxx_port_set_duplex, 3564 .port_set_speed = mv88e6185_port_set_speed, 3565 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3566 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3567 .port_link_state = mv88e6352_port_link_state, 3568 .port_get_cmode = mv88e6185_port_get_cmode, 3569 .port_setup_message_port = mv88e6xxx_setup_message_port, 3570 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3571 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3572 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3573 .stats_get_strings = mv88e6095_stats_get_strings, 3574 .stats_get_stats = mv88e6095_stats_get_stats, 3575 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3576 .set_egress_port = mv88e6095_g1_set_egress_port, 3577 .watchdog_ops = &mv88e6097_watchdog_ops, 3578 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3579 .pot_clear = mv88e6xxx_g2_pot_clear, 3580 .reset = mv88e6352_g1_reset, 3581 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3582 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3583 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3584 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3585 .avb_ops = &mv88e6165_avb_ops, 3586 .ptp_ops = &mv88e6165_ptp_ops, 3587 .phylink_validate = mv88e6185_phylink_validate, 3588 }; 3589 3590 static const struct mv88e6xxx_ops mv88e6171_ops = { 3591 /* MV88E6XXX_FAMILY_6351 */ 3592 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3593 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3594 .irl_init_all = mv88e6352_g2_irl_init_all, 3595 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3596 .phy_read = mv88e6xxx_g2_smi_phy_read, 3597 .phy_write = mv88e6xxx_g2_smi_phy_write, 3598 .port_set_link = mv88e6xxx_port_set_link, 3599 .port_set_duplex = mv88e6xxx_port_set_duplex, 3600 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3601 .port_set_speed = mv88e6185_port_set_speed, 3602 .port_tag_remap = mv88e6095_port_tag_remap, 3603 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3604 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3605 .port_set_ether_type = mv88e6351_port_set_ether_type, 3606 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3607 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3608 .port_pause_limit = mv88e6097_port_pause_limit, 3609 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3610 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3611 .port_link_state = mv88e6352_port_link_state, 3612 .port_get_cmode = mv88e6352_port_get_cmode, 3613 .port_setup_message_port = mv88e6xxx_setup_message_port, 3614 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3615 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3616 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3617 .stats_get_strings = mv88e6095_stats_get_strings, 3618 .stats_get_stats = mv88e6095_stats_get_stats, 3619 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3620 .set_egress_port = mv88e6095_g1_set_egress_port, 3621 .watchdog_ops = &mv88e6097_watchdog_ops, 3622 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3623 .pot_clear = mv88e6xxx_g2_pot_clear, 3624 .reset = mv88e6352_g1_reset, 3625 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3626 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3627 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3628 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3629 .phylink_validate = mv88e6185_phylink_validate, 3630 }; 3631 3632 static const struct mv88e6xxx_ops mv88e6172_ops = { 3633 /* MV88E6XXX_FAMILY_6352 */ 3634 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3635 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3636 .irl_init_all = mv88e6352_g2_irl_init_all, 3637 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3638 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3639 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3640 .phy_read = mv88e6xxx_g2_smi_phy_read, 3641 .phy_write = mv88e6xxx_g2_smi_phy_write, 3642 .port_set_link = mv88e6xxx_port_set_link, 3643 .port_set_duplex = mv88e6xxx_port_set_duplex, 3644 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3645 .port_set_speed = mv88e6352_port_set_speed, 3646 .port_tag_remap = mv88e6095_port_tag_remap, 3647 .port_set_policy = mv88e6352_port_set_policy, 3648 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3649 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3650 .port_set_ether_type = mv88e6351_port_set_ether_type, 3651 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3652 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3653 .port_pause_limit = mv88e6097_port_pause_limit, 3654 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3655 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3656 .port_link_state = mv88e6352_port_link_state, 3657 .port_get_cmode = mv88e6352_port_get_cmode, 3658 .port_setup_message_port = mv88e6xxx_setup_message_port, 3659 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3660 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3661 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3662 .stats_get_strings = mv88e6095_stats_get_strings, 3663 .stats_get_stats = mv88e6095_stats_get_stats, 3664 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3665 .set_egress_port = mv88e6095_g1_set_egress_port, 3666 .watchdog_ops = &mv88e6097_watchdog_ops, 3667 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3668 .pot_clear = mv88e6xxx_g2_pot_clear, 3669 .reset = mv88e6352_g1_reset, 3670 .rmu_disable = mv88e6352_g1_rmu_disable, 3671 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3672 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3673 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3674 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3675 .serdes_get_lane = mv88e6352_serdes_get_lane, 3676 .serdes_power = mv88e6352_serdes_power, 3677 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3678 .serdes_get_regs = mv88e6352_serdes_get_regs, 3679 .gpio_ops = &mv88e6352_gpio_ops, 3680 .phylink_validate = mv88e6352_phylink_validate, 3681 }; 3682 3683 static const struct mv88e6xxx_ops mv88e6175_ops = { 3684 /* MV88E6XXX_FAMILY_6351 */ 3685 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3686 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3687 .irl_init_all = mv88e6352_g2_irl_init_all, 3688 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3689 .phy_read = mv88e6xxx_g2_smi_phy_read, 3690 .phy_write = mv88e6xxx_g2_smi_phy_write, 3691 .port_set_link = mv88e6xxx_port_set_link, 3692 .port_set_duplex = mv88e6xxx_port_set_duplex, 3693 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3694 .port_set_speed = mv88e6185_port_set_speed, 3695 .port_tag_remap = mv88e6095_port_tag_remap, 3696 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3697 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3698 .port_set_ether_type = mv88e6351_port_set_ether_type, 3699 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3700 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3701 .port_pause_limit = mv88e6097_port_pause_limit, 3702 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3703 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3704 .port_link_state = mv88e6352_port_link_state, 3705 .port_get_cmode = mv88e6352_port_get_cmode, 3706 .port_setup_message_port = mv88e6xxx_setup_message_port, 3707 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3708 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3709 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3710 .stats_get_strings = mv88e6095_stats_get_strings, 3711 .stats_get_stats = mv88e6095_stats_get_stats, 3712 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3713 .set_egress_port = mv88e6095_g1_set_egress_port, 3714 .watchdog_ops = &mv88e6097_watchdog_ops, 3715 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3716 .pot_clear = mv88e6xxx_g2_pot_clear, 3717 .reset = mv88e6352_g1_reset, 3718 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3719 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3720 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3721 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3722 .phylink_validate = mv88e6185_phylink_validate, 3723 }; 3724 3725 static const struct mv88e6xxx_ops mv88e6176_ops = { 3726 /* MV88E6XXX_FAMILY_6352 */ 3727 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3728 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3729 .irl_init_all = mv88e6352_g2_irl_init_all, 3730 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3731 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3732 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3733 .phy_read = mv88e6xxx_g2_smi_phy_read, 3734 .phy_write = mv88e6xxx_g2_smi_phy_write, 3735 .port_set_link = mv88e6xxx_port_set_link, 3736 .port_set_duplex = mv88e6xxx_port_set_duplex, 3737 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3738 .port_set_speed = mv88e6352_port_set_speed, 3739 .port_tag_remap = mv88e6095_port_tag_remap, 3740 .port_set_policy = mv88e6352_port_set_policy, 3741 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3742 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3743 .port_set_ether_type = mv88e6351_port_set_ether_type, 3744 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3745 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3746 .port_pause_limit = mv88e6097_port_pause_limit, 3747 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3748 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3749 .port_link_state = mv88e6352_port_link_state, 3750 .port_get_cmode = mv88e6352_port_get_cmode, 3751 .port_setup_message_port = mv88e6xxx_setup_message_port, 3752 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3753 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3754 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3755 .stats_get_strings = mv88e6095_stats_get_strings, 3756 .stats_get_stats = mv88e6095_stats_get_stats, 3757 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3758 .set_egress_port = mv88e6095_g1_set_egress_port, 3759 .watchdog_ops = &mv88e6097_watchdog_ops, 3760 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3761 .pot_clear = mv88e6xxx_g2_pot_clear, 3762 .reset = mv88e6352_g1_reset, 3763 .rmu_disable = mv88e6352_g1_rmu_disable, 3764 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3765 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3766 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3767 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3768 .serdes_get_lane = mv88e6352_serdes_get_lane, 3769 .serdes_power = mv88e6352_serdes_power, 3770 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3771 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3772 .serdes_irq_status = mv88e6352_serdes_irq_status, 3773 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3774 .serdes_get_regs = mv88e6352_serdes_get_regs, 3775 .gpio_ops = &mv88e6352_gpio_ops, 3776 .phylink_validate = mv88e6352_phylink_validate, 3777 }; 3778 3779 static const struct mv88e6xxx_ops mv88e6185_ops = { 3780 /* MV88E6XXX_FAMILY_6185 */ 3781 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3782 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3783 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3784 .phy_read = mv88e6185_phy_ppu_read, 3785 .phy_write = mv88e6185_phy_ppu_write, 3786 .port_set_link = mv88e6xxx_port_set_link, 3787 .port_set_duplex = mv88e6xxx_port_set_duplex, 3788 .port_set_speed = mv88e6185_port_set_speed, 3789 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3790 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3791 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3792 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3793 .port_set_pause = mv88e6185_port_set_pause, 3794 .port_link_state = mv88e6185_port_link_state, 3795 .port_get_cmode = mv88e6185_port_get_cmode, 3796 .port_setup_message_port = mv88e6xxx_setup_message_port, 3797 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3798 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3799 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3800 .stats_get_strings = mv88e6095_stats_get_strings, 3801 .stats_get_stats = mv88e6095_stats_get_stats, 3802 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3803 .set_egress_port = mv88e6095_g1_set_egress_port, 3804 .watchdog_ops = &mv88e6097_watchdog_ops, 3805 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3806 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3807 .ppu_enable = mv88e6185_g1_ppu_enable, 3808 .ppu_disable = mv88e6185_g1_ppu_disable, 3809 .reset = mv88e6185_g1_reset, 3810 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3811 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3812 .phylink_validate = mv88e6185_phylink_validate, 3813 }; 3814 3815 static const struct mv88e6xxx_ops mv88e6190_ops = { 3816 /* MV88E6XXX_FAMILY_6390 */ 3817 .setup_errata = mv88e6390_setup_errata, 3818 .irl_init_all = mv88e6390_g2_irl_init_all, 3819 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3820 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3822 .phy_read = mv88e6xxx_g2_smi_phy_read, 3823 .phy_write = mv88e6xxx_g2_smi_phy_write, 3824 .port_set_link = mv88e6xxx_port_set_link, 3825 .port_set_duplex = mv88e6xxx_port_set_duplex, 3826 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3827 .port_set_speed = mv88e6390_port_set_speed, 3828 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3829 .port_tag_remap = mv88e6390_port_tag_remap, 3830 .port_set_policy = mv88e6352_port_set_policy, 3831 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3832 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3833 .port_set_ether_type = mv88e6351_port_set_ether_type, 3834 .port_pause_limit = mv88e6390_port_pause_limit, 3835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3837 .port_link_state = mv88e6352_port_link_state, 3838 .port_get_cmode = mv88e6352_port_get_cmode, 3839 .port_set_cmode = mv88e6390_port_set_cmode, 3840 .port_setup_message_port = mv88e6xxx_setup_message_port, 3841 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3842 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3843 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3844 .stats_get_strings = mv88e6320_stats_get_strings, 3845 .stats_get_stats = mv88e6390_stats_get_stats, 3846 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3847 .set_egress_port = mv88e6390_g1_set_egress_port, 3848 .watchdog_ops = &mv88e6390_watchdog_ops, 3849 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3850 .pot_clear = mv88e6xxx_g2_pot_clear, 3851 .reset = mv88e6352_g1_reset, 3852 .rmu_disable = mv88e6390_g1_rmu_disable, 3853 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3854 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3855 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3856 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3857 .serdes_power = mv88e6390_serdes_power, 3858 .serdes_get_lane = mv88e6390_serdes_get_lane, 3859 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3860 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3861 .serdes_irq_status = mv88e6390_serdes_irq_status, 3862 .serdes_get_strings = mv88e6390_serdes_get_strings, 3863 .serdes_get_stats = mv88e6390_serdes_get_stats, 3864 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3865 .serdes_get_regs = mv88e6390_serdes_get_regs, 3866 .phylink_validate = mv88e6390_phylink_validate, 3867 .gpio_ops = &mv88e6352_gpio_ops, 3868 .phylink_validate = mv88e6390_phylink_validate, 3869 }; 3870 3871 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3872 /* MV88E6XXX_FAMILY_6390 */ 3873 .setup_errata = mv88e6390_setup_errata, 3874 .irl_init_all = mv88e6390_g2_irl_init_all, 3875 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3876 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3877 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3878 .phy_read = mv88e6xxx_g2_smi_phy_read, 3879 .phy_write = mv88e6xxx_g2_smi_phy_write, 3880 .port_set_link = mv88e6xxx_port_set_link, 3881 .port_set_duplex = mv88e6xxx_port_set_duplex, 3882 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3883 .port_set_speed = mv88e6390x_port_set_speed, 3884 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3885 .port_tag_remap = mv88e6390_port_tag_remap, 3886 .port_set_policy = mv88e6352_port_set_policy, 3887 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3888 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3889 .port_set_ether_type = mv88e6351_port_set_ether_type, 3890 .port_pause_limit = mv88e6390_port_pause_limit, 3891 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3892 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3893 .port_link_state = mv88e6352_port_link_state, 3894 .port_get_cmode = mv88e6352_port_get_cmode, 3895 .port_set_cmode = mv88e6390x_port_set_cmode, 3896 .port_setup_message_port = mv88e6xxx_setup_message_port, 3897 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3898 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3899 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3900 .stats_get_strings = mv88e6320_stats_get_strings, 3901 .stats_get_stats = mv88e6390_stats_get_stats, 3902 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3903 .set_egress_port = mv88e6390_g1_set_egress_port, 3904 .watchdog_ops = &mv88e6390_watchdog_ops, 3905 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3906 .pot_clear = mv88e6xxx_g2_pot_clear, 3907 .reset = mv88e6352_g1_reset, 3908 .rmu_disable = mv88e6390_g1_rmu_disable, 3909 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3910 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3911 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3912 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3913 .serdes_power = mv88e6390_serdes_power, 3914 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3915 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3916 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3917 .serdes_irq_status = mv88e6390_serdes_irq_status, 3918 .serdes_get_strings = mv88e6390_serdes_get_strings, 3919 .serdes_get_stats = mv88e6390_serdes_get_stats, 3920 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3921 .serdes_get_regs = mv88e6390_serdes_get_regs, 3922 .phylink_validate = mv88e6390_phylink_validate, 3923 .gpio_ops = &mv88e6352_gpio_ops, 3924 .phylink_validate = mv88e6390x_phylink_validate, 3925 }; 3926 3927 static const struct mv88e6xxx_ops mv88e6191_ops = { 3928 /* MV88E6XXX_FAMILY_6390 */ 3929 .setup_errata = mv88e6390_setup_errata, 3930 .irl_init_all = mv88e6390_g2_irl_init_all, 3931 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3932 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3934 .phy_read = mv88e6xxx_g2_smi_phy_read, 3935 .phy_write = mv88e6xxx_g2_smi_phy_write, 3936 .port_set_link = mv88e6xxx_port_set_link, 3937 .port_set_duplex = mv88e6xxx_port_set_duplex, 3938 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3939 .port_set_speed = mv88e6390_port_set_speed, 3940 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3941 .port_tag_remap = mv88e6390_port_tag_remap, 3942 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3943 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3944 .port_set_ether_type = mv88e6351_port_set_ether_type, 3945 .port_pause_limit = mv88e6390_port_pause_limit, 3946 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3947 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3948 .port_link_state = mv88e6352_port_link_state, 3949 .port_get_cmode = mv88e6352_port_get_cmode, 3950 .port_set_cmode = mv88e6390_port_set_cmode, 3951 .port_setup_message_port = mv88e6xxx_setup_message_port, 3952 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3953 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3954 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3955 .stats_get_strings = mv88e6320_stats_get_strings, 3956 .stats_get_stats = mv88e6390_stats_get_stats, 3957 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3958 .set_egress_port = mv88e6390_g1_set_egress_port, 3959 .watchdog_ops = &mv88e6390_watchdog_ops, 3960 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3961 .pot_clear = mv88e6xxx_g2_pot_clear, 3962 .reset = mv88e6352_g1_reset, 3963 .rmu_disable = mv88e6390_g1_rmu_disable, 3964 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3965 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3966 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3967 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3968 .serdes_power = mv88e6390_serdes_power, 3969 .serdes_get_lane = mv88e6390_serdes_get_lane, 3970 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3971 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3972 .serdes_irq_status = mv88e6390_serdes_irq_status, 3973 .serdes_get_strings = mv88e6390_serdes_get_strings, 3974 .serdes_get_stats = mv88e6390_serdes_get_stats, 3975 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3976 .serdes_get_regs = mv88e6390_serdes_get_regs, 3977 .phylink_validate = mv88e6390_phylink_validate, 3978 .avb_ops = &mv88e6390_avb_ops, 3979 .ptp_ops = &mv88e6352_ptp_ops, 3980 .phylink_validate = mv88e6390_phylink_validate, 3981 }; 3982 3983 static const struct mv88e6xxx_ops mv88e6240_ops = { 3984 /* MV88E6XXX_FAMILY_6352 */ 3985 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3986 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3987 .irl_init_all = mv88e6352_g2_irl_init_all, 3988 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3989 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3990 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3991 .phy_read = mv88e6xxx_g2_smi_phy_read, 3992 .phy_write = mv88e6xxx_g2_smi_phy_write, 3993 .port_set_link = mv88e6xxx_port_set_link, 3994 .port_set_duplex = mv88e6xxx_port_set_duplex, 3995 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3996 .port_set_speed = mv88e6352_port_set_speed, 3997 .port_tag_remap = mv88e6095_port_tag_remap, 3998 .port_set_policy = mv88e6352_port_set_policy, 3999 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4000 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4001 .port_set_ether_type = mv88e6351_port_set_ether_type, 4002 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4003 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4004 .port_pause_limit = mv88e6097_port_pause_limit, 4005 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4006 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4007 .port_link_state = mv88e6352_port_link_state, 4008 .port_get_cmode = mv88e6352_port_get_cmode, 4009 .port_setup_message_port = mv88e6xxx_setup_message_port, 4010 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4011 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4012 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4013 .stats_get_strings = mv88e6095_stats_get_strings, 4014 .stats_get_stats = mv88e6095_stats_get_stats, 4015 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4016 .set_egress_port = mv88e6095_g1_set_egress_port, 4017 .watchdog_ops = &mv88e6097_watchdog_ops, 4018 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4019 .pot_clear = mv88e6xxx_g2_pot_clear, 4020 .reset = mv88e6352_g1_reset, 4021 .rmu_disable = mv88e6352_g1_rmu_disable, 4022 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4023 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4024 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4025 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4026 .serdes_get_lane = mv88e6352_serdes_get_lane, 4027 .serdes_power = mv88e6352_serdes_power, 4028 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4029 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4030 .serdes_irq_status = mv88e6352_serdes_irq_status, 4031 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4032 .serdes_get_regs = mv88e6352_serdes_get_regs, 4033 .gpio_ops = &mv88e6352_gpio_ops, 4034 .avb_ops = &mv88e6352_avb_ops, 4035 .ptp_ops = &mv88e6352_ptp_ops, 4036 .phylink_validate = mv88e6352_phylink_validate, 4037 }; 4038 4039 static const struct mv88e6xxx_ops mv88e6250_ops = { 4040 /* MV88E6XXX_FAMILY_6250 */ 4041 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4042 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4043 .irl_init_all = mv88e6352_g2_irl_init_all, 4044 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4045 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4046 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4047 .phy_read = mv88e6xxx_g2_smi_phy_read, 4048 .phy_write = mv88e6xxx_g2_smi_phy_write, 4049 .port_set_link = mv88e6xxx_port_set_link, 4050 .port_set_duplex = mv88e6xxx_port_set_duplex, 4051 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4052 .port_set_speed = mv88e6250_port_set_speed, 4053 .port_tag_remap = mv88e6095_port_tag_remap, 4054 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4055 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4056 .port_set_ether_type = mv88e6351_port_set_ether_type, 4057 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4058 .port_pause_limit = mv88e6097_port_pause_limit, 4059 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4060 .port_link_state = mv88e6250_port_link_state, 4061 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4062 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4063 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4064 .stats_get_strings = mv88e6250_stats_get_strings, 4065 .stats_get_stats = mv88e6250_stats_get_stats, 4066 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4067 .set_egress_port = mv88e6095_g1_set_egress_port, 4068 .watchdog_ops = &mv88e6250_watchdog_ops, 4069 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4070 .pot_clear = mv88e6xxx_g2_pot_clear, 4071 .reset = mv88e6250_g1_reset, 4072 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4073 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4074 .avb_ops = &mv88e6352_avb_ops, 4075 .ptp_ops = &mv88e6250_ptp_ops, 4076 .phylink_validate = mv88e6065_phylink_validate, 4077 }; 4078 4079 static const struct mv88e6xxx_ops mv88e6290_ops = { 4080 /* MV88E6XXX_FAMILY_6390 */ 4081 .setup_errata = mv88e6390_setup_errata, 4082 .irl_init_all = mv88e6390_g2_irl_init_all, 4083 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4084 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4085 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4086 .phy_read = mv88e6xxx_g2_smi_phy_read, 4087 .phy_write = mv88e6xxx_g2_smi_phy_write, 4088 .port_set_link = mv88e6xxx_port_set_link, 4089 .port_set_duplex = mv88e6xxx_port_set_duplex, 4090 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4091 .port_set_speed = mv88e6390_port_set_speed, 4092 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4093 .port_tag_remap = mv88e6390_port_tag_remap, 4094 .port_set_policy = mv88e6352_port_set_policy, 4095 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4096 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4097 .port_set_ether_type = mv88e6351_port_set_ether_type, 4098 .port_pause_limit = mv88e6390_port_pause_limit, 4099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4101 .port_link_state = mv88e6352_port_link_state, 4102 .port_get_cmode = mv88e6352_port_get_cmode, 4103 .port_set_cmode = mv88e6390_port_set_cmode, 4104 .port_setup_message_port = mv88e6xxx_setup_message_port, 4105 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4106 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4107 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4108 .stats_get_strings = mv88e6320_stats_get_strings, 4109 .stats_get_stats = mv88e6390_stats_get_stats, 4110 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4111 .set_egress_port = mv88e6390_g1_set_egress_port, 4112 .watchdog_ops = &mv88e6390_watchdog_ops, 4113 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4114 .pot_clear = mv88e6xxx_g2_pot_clear, 4115 .reset = mv88e6352_g1_reset, 4116 .rmu_disable = mv88e6390_g1_rmu_disable, 4117 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4118 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4119 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4120 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4121 .serdes_power = mv88e6390_serdes_power, 4122 .serdes_get_lane = mv88e6390_serdes_get_lane, 4123 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4124 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4125 .serdes_irq_status = mv88e6390_serdes_irq_status, 4126 .serdes_get_strings = mv88e6390_serdes_get_strings, 4127 .serdes_get_stats = mv88e6390_serdes_get_stats, 4128 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4129 .serdes_get_regs = mv88e6390_serdes_get_regs, 4130 .phylink_validate = mv88e6390_phylink_validate, 4131 .gpio_ops = &mv88e6352_gpio_ops, 4132 .avb_ops = &mv88e6390_avb_ops, 4133 .ptp_ops = &mv88e6352_ptp_ops, 4134 .phylink_validate = mv88e6390_phylink_validate, 4135 }; 4136 4137 static const struct mv88e6xxx_ops mv88e6320_ops = { 4138 /* MV88E6XXX_FAMILY_6320 */ 4139 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4140 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4141 .irl_init_all = mv88e6352_g2_irl_init_all, 4142 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4143 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4145 .phy_read = mv88e6xxx_g2_smi_phy_read, 4146 .phy_write = mv88e6xxx_g2_smi_phy_write, 4147 .port_set_link = mv88e6xxx_port_set_link, 4148 .port_set_duplex = mv88e6xxx_port_set_duplex, 4149 .port_set_speed = mv88e6185_port_set_speed, 4150 .port_tag_remap = mv88e6095_port_tag_remap, 4151 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4152 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4153 .port_set_ether_type = mv88e6351_port_set_ether_type, 4154 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4155 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4156 .port_pause_limit = mv88e6097_port_pause_limit, 4157 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4158 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4159 .port_link_state = mv88e6352_port_link_state, 4160 .port_get_cmode = mv88e6352_port_get_cmode, 4161 .port_setup_message_port = mv88e6xxx_setup_message_port, 4162 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4163 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4164 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4165 .stats_get_strings = mv88e6320_stats_get_strings, 4166 .stats_get_stats = mv88e6320_stats_get_stats, 4167 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4168 .set_egress_port = mv88e6095_g1_set_egress_port, 4169 .watchdog_ops = &mv88e6390_watchdog_ops, 4170 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4171 .pot_clear = mv88e6xxx_g2_pot_clear, 4172 .reset = mv88e6352_g1_reset, 4173 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4174 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4175 .gpio_ops = &mv88e6352_gpio_ops, 4176 .avb_ops = &mv88e6352_avb_ops, 4177 .ptp_ops = &mv88e6352_ptp_ops, 4178 .phylink_validate = mv88e6185_phylink_validate, 4179 }; 4180 4181 static const struct mv88e6xxx_ops mv88e6321_ops = { 4182 /* MV88E6XXX_FAMILY_6320 */ 4183 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4184 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4185 .irl_init_all = mv88e6352_g2_irl_init_all, 4186 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4187 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4188 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4189 .phy_read = mv88e6xxx_g2_smi_phy_read, 4190 .phy_write = mv88e6xxx_g2_smi_phy_write, 4191 .port_set_link = mv88e6xxx_port_set_link, 4192 .port_set_duplex = mv88e6xxx_port_set_duplex, 4193 .port_set_speed = mv88e6185_port_set_speed, 4194 .port_tag_remap = mv88e6095_port_tag_remap, 4195 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4196 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4197 .port_set_ether_type = mv88e6351_port_set_ether_type, 4198 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4199 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4200 .port_pause_limit = mv88e6097_port_pause_limit, 4201 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4202 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4203 .port_link_state = mv88e6352_port_link_state, 4204 .port_get_cmode = mv88e6352_port_get_cmode, 4205 .port_setup_message_port = mv88e6xxx_setup_message_port, 4206 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4207 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4208 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4209 .stats_get_strings = mv88e6320_stats_get_strings, 4210 .stats_get_stats = mv88e6320_stats_get_stats, 4211 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4212 .set_egress_port = mv88e6095_g1_set_egress_port, 4213 .watchdog_ops = &mv88e6390_watchdog_ops, 4214 .reset = mv88e6352_g1_reset, 4215 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4216 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4217 .gpio_ops = &mv88e6352_gpio_ops, 4218 .avb_ops = &mv88e6352_avb_ops, 4219 .ptp_ops = &mv88e6352_ptp_ops, 4220 .phylink_validate = mv88e6185_phylink_validate, 4221 }; 4222 4223 static const struct mv88e6xxx_ops mv88e6341_ops = { 4224 /* MV88E6XXX_FAMILY_6341 */ 4225 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4226 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4227 .irl_init_all = mv88e6352_g2_irl_init_all, 4228 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4229 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4230 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4231 .phy_read = mv88e6xxx_g2_smi_phy_read, 4232 .phy_write = mv88e6xxx_g2_smi_phy_write, 4233 .port_set_link = mv88e6xxx_port_set_link, 4234 .port_set_duplex = mv88e6xxx_port_set_duplex, 4235 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4236 .port_set_speed = mv88e6341_port_set_speed, 4237 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4238 .port_tag_remap = mv88e6095_port_tag_remap, 4239 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4240 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4241 .port_set_ether_type = mv88e6351_port_set_ether_type, 4242 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4243 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4244 .port_pause_limit = mv88e6097_port_pause_limit, 4245 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4246 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4247 .port_link_state = mv88e6352_port_link_state, 4248 .port_get_cmode = mv88e6352_port_get_cmode, 4249 .port_set_cmode = mv88e6341_port_set_cmode, 4250 .port_setup_message_port = mv88e6xxx_setup_message_port, 4251 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4252 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4253 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4254 .stats_get_strings = mv88e6320_stats_get_strings, 4255 .stats_get_stats = mv88e6390_stats_get_stats, 4256 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4257 .set_egress_port = mv88e6390_g1_set_egress_port, 4258 .watchdog_ops = &mv88e6390_watchdog_ops, 4259 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4260 .pot_clear = mv88e6xxx_g2_pot_clear, 4261 .reset = mv88e6352_g1_reset, 4262 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4263 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4264 .serdes_power = mv88e6390_serdes_power, 4265 .serdes_get_lane = mv88e6341_serdes_get_lane, 4266 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4267 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4268 .serdes_irq_status = mv88e6390_serdes_irq_status, 4269 .gpio_ops = &mv88e6352_gpio_ops, 4270 .avb_ops = &mv88e6390_avb_ops, 4271 .ptp_ops = &mv88e6352_ptp_ops, 4272 .phylink_validate = mv88e6341_phylink_validate, 4273 }; 4274 4275 static const struct mv88e6xxx_ops mv88e6350_ops = { 4276 /* MV88E6XXX_FAMILY_6351 */ 4277 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4278 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4279 .irl_init_all = mv88e6352_g2_irl_init_all, 4280 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4281 .phy_read = mv88e6xxx_g2_smi_phy_read, 4282 .phy_write = mv88e6xxx_g2_smi_phy_write, 4283 .port_set_link = mv88e6xxx_port_set_link, 4284 .port_set_duplex = mv88e6xxx_port_set_duplex, 4285 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4286 .port_set_speed = mv88e6185_port_set_speed, 4287 .port_tag_remap = mv88e6095_port_tag_remap, 4288 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4289 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4290 .port_set_ether_type = mv88e6351_port_set_ether_type, 4291 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4292 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4293 .port_pause_limit = mv88e6097_port_pause_limit, 4294 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4295 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4296 .port_link_state = mv88e6352_port_link_state, 4297 .port_get_cmode = mv88e6352_port_get_cmode, 4298 .port_setup_message_port = mv88e6xxx_setup_message_port, 4299 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4300 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4301 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4302 .stats_get_strings = mv88e6095_stats_get_strings, 4303 .stats_get_stats = mv88e6095_stats_get_stats, 4304 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4305 .set_egress_port = mv88e6095_g1_set_egress_port, 4306 .watchdog_ops = &mv88e6097_watchdog_ops, 4307 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4308 .pot_clear = mv88e6xxx_g2_pot_clear, 4309 .reset = mv88e6352_g1_reset, 4310 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4311 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4312 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4313 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4314 .phylink_validate = mv88e6185_phylink_validate, 4315 }; 4316 4317 static const struct mv88e6xxx_ops mv88e6351_ops = { 4318 /* MV88E6XXX_FAMILY_6351 */ 4319 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4320 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4321 .irl_init_all = mv88e6352_g2_irl_init_all, 4322 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4323 .phy_read = mv88e6xxx_g2_smi_phy_read, 4324 .phy_write = mv88e6xxx_g2_smi_phy_write, 4325 .port_set_link = mv88e6xxx_port_set_link, 4326 .port_set_duplex = mv88e6xxx_port_set_duplex, 4327 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4328 .port_set_speed = mv88e6185_port_set_speed, 4329 .port_tag_remap = mv88e6095_port_tag_remap, 4330 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4331 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4332 .port_set_ether_type = mv88e6351_port_set_ether_type, 4333 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4334 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4335 .port_pause_limit = mv88e6097_port_pause_limit, 4336 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4337 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4338 .port_link_state = mv88e6352_port_link_state, 4339 .port_get_cmode = mv88e6352_port_get_cmode, 4340 .port_setup_message_port = mv88e6xxx_setup_message_port, 4341 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4342 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4343 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4344 .stats_get_strings = mv88e6095_stats_get_strings, 4345 .stats_get_stats = mv88e6095_stats_get_stats, 4346 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4347 .set_egress_port = mv88e6095_g1_set_egress_port, 4348 .watchdog_ops = &mv88e6097_watchdog_ops, 4349 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4350 .pot_clear = mv88e6xxx_g2_pot_clear, 4351 .reset = mv88e6352_g1_reset, 4352 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4353 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4354 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4355 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4356 .avb_ops = &mv88e6352_avb_ops, 4357 .ptp_ops = &mv88e6352_ptp_ops, 4358 .phylink_validate = mv88e6185_phylink_validate, 4359 }; 4360 4361 static const struct mv88e6xxx_ops mv88e6352_ops = { 4362 /* MV88E6XXX_FAMILY_6352 */ 4363 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4364 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4365 .irl_init_all = mv88e6352_g2_irl_init_all, 4366 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4367 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4368 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4369 .phy_read = mv88e6xxx_g2_smi_phy_read, 4370 .phy_write = mv88e6xxx_g2_smi_phy_write, 4371 .port_set_link = mv88e6xxx_port_set_link, 4372 .port_set_duplex = mv88e6xxx_port_set_duplex, 4373 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4374 .port_set_speed = mv88e6352_port_set_speed, 4375 .port_tag_remap = mv88e6095_port_tag_remap, 4376 .port_set_policy = mv88e6352_port_set_policy, 4377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4378 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4379 .port_set_ether_type = mv88e6351_port_set_ether_type, 4380 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4381 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4382 .port_pause_limit = mv88e6097_port_pause_limit, 4383 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4384 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4385 .port_link_state = mv88e6352_port_link_state, 4386 .port_get_cmode = mv88e6352_port_get_cmode, 4387 .port_setup_message_port = mv88e6xxx_setup_message_port, 4388 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4389 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4390 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4391 .stats_get_strings = mv88e6095_stats_get_strings, 4392 .stats_get_stats = mv88e6095_stats_get_stats, 4393 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4394 .set_egress_port = mv88e6095_g1_set_egress_port, 4395 .watchdog_ops = &mv88e6097_watchdog_ops, 4396 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4397 .pot_clear = mv88e6xxx_g2_pot_clear, 4398 .reset = mv88e6352_g1_reset, 4399 .rmu_disable = mv88e6352_g1_rmu_disable, 4400 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4401 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4402 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4403 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4404 .serdes_get_lane = mv88e6352_serdes_get_lane, 4405 .serdes_power = mv88e6352_serdes_power, 4406 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4407 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4408 .serdes_irq_status = mv88e6352_serdes_irq_status, 4409 .gpio_ops = &mv88e6352_gpio_ops, 4410 .avb_ops = &mv88e6352_avb_ops, 4411 .ptp_ops = &mv88e6352_ptp_ops, 4412 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4413 .serdes_get_strings = mv88e6352_serdes_get_strings, 4414 .serdes_get_stats = mv88e6352_serdes_get_stats, 4415 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4416 .serdes_get_regs = mv88e6352_serdes_get_regs, 4417 .phylink_validate = mv88e6352_phylink_validate, 4418 }; 4419 4420 static const struct mv88e6xxx_ops mv88e6390_ops = { 4421 /* MV88E6XXX_FAMILY_6390 */ 4422 .setup_errata = mv88e6390_setup_errata, 4423 .irl_init_all = mv88e6390_g2_irl_init_all, 4424 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4425 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4427 .phy_read = mv88e6xxx_g2_smi_phy_read, 4428 .phy_write = mv88e6xxx_g2_smi_phy_write, 4429 .port_set_link = mv88e6xxx_port_set_link, 4430 .port_set_duplex = mv88e6xxx_port_set_duplex, 4431 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4432 .port_set_speed = mv88e6390_port_set_speed, 4433 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4434 .port_tag_remap = mv88e6390_port_tag_remap, 4435 .port_set_policy = mv88e6352_port_set_policy, 4436 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4437 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4438 .port_set_ether_type = mv88e6351_port_set_ether_type, 4439 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4440 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4441 .port_pause_limit = mv88e6390_port_pause_limit, 4442 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4443 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4444 .port_link_state = mv88e6352_port_link_state, 4445 .port_get_cmode = mv88e6352_port_get_cmode, 4446 .port_set_cmode = mv88e6390_port_set_cmode, 4447 .port_setup_message_port = mv88e6xxx_setup_message_port, 4448 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4449 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4450 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4451 .stats_get_strings = mv88e6320_stats_get_strings, 4452 .stats_get_stats = mv88e6390_stats_get_stats, 4453 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4454 .set_egress_port = mv88e6390_g1_set_egress_port, 4455 .watchdog_ops = &mv88e6390_watchdog_ops, 4456 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4457 .pot_clear = mv88e6xxx_g2_pot_clear, 4458 .reset = mv88e6352_g1_reset, 4459 .rmu_disable = mv88e6390_g1_rmu_disable, 4460 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4461 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4462 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4463 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4464 .serdes_power = mv88e6390_serdes_power, 4465 .serdes_get_lane = mv88e6390_serdes_get_lane, 4466 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4467 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4468 .serdes_irq_status = mv88e6390_serdes_irq_status, 4469 .gpio_ops = &mv88e6352_gpio_ops, 4470 .avb_ops = &mv88e6390_avb_ops, 4471 .ptp_ops = &mv88e6352_ptp_ops, 4472 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4473 .serdes_get_strings = mv88e6390_serdes_get_strings, 4474 .serdes_get_stats = mv88e6390_serdes_get_stats, 4475 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4476 .serdes_get_regs = mv88e6390_serdes_get_regs, 4477 .phylink_validate = mv88e6390_phylink_validate, 4478 }; 4479 4480 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4481 /* MV88E6XXX_FAMILY_6390 */ 4482 .setup_errata = mv88e6390_setup_errata, 4483 .irl_init_all = mv88e6390_g2_irl_init_all, 4484 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4485 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4486 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4487 .phy_read = mv88e6xxx_g2_smi_phy_read, 4488 .phy_write = mv88e6xxx_g2_smi_phy_write, 4489 .port_set_link = mv88e6xxx_port_set_link, 4490 .port_set_duplex = mv88e6xxx_port_set_duplex, 4491 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4492 .port_set_speed = mv88e6390x_port_set_speed, 4493 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4494 .port_tag_remap = mv88e6390_port_tag_remap, 4495 .port_set_policy = mv88e6352_port_set_policy, 4496 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4497 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4498 .port_set_ether_type = mv88e6351_port_set_ether_type, 4499 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4500 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4501 .port_pause_limit = mv88e6390_port_pause_limit, 4502 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4503 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4504 .port_link_state = mv88e6352_port_link_state, 4505 .port_get_cmode = mv88e6352_port_get_cmode, 4506 .port_set_cmode = mv88e6390x_port_set_cmode, 4507 .port_setup_message_port = mv88e6xxx_setup_message_port, 4508 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4509 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4510 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4511 .stats_get_strings = mv88e6320_stats_get_strings, 4512 .stats_get_stats = mv88e6390_stats_get_stats, 4513 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4514 .set_egress_port = mv88e6390_g1_set_egress_port, 4515 .watchdog_ops = &mv88e6390_watchdog_ops, 4516 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4517 .pot_clear = mv88e6xxx_g2_pot_clear, 4518 .reset = mv88e6352_g1_reset, 4519 .rmu_disable = mv88e6390_g1_rmu_disable, 4520 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4521 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4522 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4523 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4524 .serdes_power = mv88e6390_serdes_power, 4525 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4526 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4527 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4528 .serdes_irq_status = mv88e6390_serdes_irq_status, 4529 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4530 .serdes_get_strings = mv88e6390_serdes_get_strings, 4531 .serdes_get_stats = mv88e6390_serdes_get_stats, 4532 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4533 .serdes_get_regs = mv88e6390_serdes_get_regs, 4534 .gpio_ops = &mv88e6352_gpio_ops, 4535 .avb_ops = &mv88e6390_avb_ops, 4536 .ptp_ops = &mv88e6352_ptp_ops, 4537 .phylink_validate = mv88e6390x_phylink_validate, 4538 }; 4539 4540 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4541 [MV88E6085] = { 4542 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4543 .family = MV88E6XXX_FAMILY_6097, 4544 .name = "Marvell 88E6085", 4545 .num_databases = 4096, 4546 .num_macs = 8192, 4547 .num_ports = 10, 4548 .num_internal_phys = 5, 4549 .max_vid = 4095, 4550 .port_base_addr = 0x10, 4551 .phy_base_addr = 0x0, 4552 .global1_addr = 0x1b, 4553 .global2_addr = 0x1c, 4554 .age_time_coeff = 15000, 4555 .g1_irqs = 8, 4556 .g2_irqs = 10, 4557 .atu_move_port_mask = 0xf, 4558 .pvt = true, 4559 .multi_chip = true, 4560 .tag_protocol = DSA_TAG_PROTO_DSA, 4561 .ops = &mv88e6085_ops, 4562 }, 4563 4564 [MV88E6095] = { 4565 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4566 .family = MV88E6XXX_FAMILY_6095, 4567 .name = "Marvell 88E6095/88E6095F", 4568 .num_databases = 256, 4569 .num_macs = 8192, 4570 .num_ports = 11, 4571 .num_internal_phys = 0, 4572 .max_vid = 4095, 4573 .port_base_addr = 0x10, 4574 .phy_base_addr = 0x0, 4575 .global1_addr = 0x1b, 4576 .global2_addr = 0x1c, 4577 .age_time_coeff = 15000, 4578 .g1_irqs = 8, 4579 .atu_move_port_mask = 0xf, 4580 .multi_chip = true, 4581 .tag_protocol = DSA_TAG_PROTO_DSA, 4582 .ops = &mv88e6095_ops, 4583 }, 4584 4585 [MV88E6097] = { 4586 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4587 .family = MV88E6XXX_FAMILY_6097, 4588 .name = "Marvell 88E6097/88E6097F", 4589 .num_databases = 4096, 4590 .num_macs = 8192, 4591 .num_ports = 11, 4592 .num_internal_phys = 8, 4593 .max_vid = 4095, 4594 .port_base_addr = 0x10, 4595 .phy_base_addr = 0x0, 4596 .global1_addr = 0x1b, 4597 .global2_addr = 0x1c, 4598 .age_time_coeff = 15000, 4599 .g1_irqs = 8, 4600 .g2_irqs = 10, 4601 .atu_move_port_mask = 0xf, 4602 .pvt = true, 4603 .multi_chip = true, 4604 .tag_protocol = DSA_TAG_PROTO_EDSA, 4605 .ops = &mv88e6097_ops, 4606 }, 4607 4608 [MV88E6123] = { 4609 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4610 .family = MV88E6XXX_FAMILY_6165, 4611 .name = "Marvell 88E6123", 4612 .num_databases = 4096, 4613 .num_macs = 1024, 4614 .num_ports = 3, 4615 .num_internal_phys = 5, 4616 .max_vid = 4095, 4617 .port_base_addr = 0x10, 4618 .phy_base_addr = 0x0, 4619 .global1_addr = 0x1b, 4620 .global2_addr = 0x1c, 4621 .age_time_coeff = 15000, 4622 .g1_irqs = 9, 4623 .g2_irqs = 10, 4624 .atu_move_port_mask = 0xf, 4625 .pvt = true, 4626 .multi_chip = true, 4627 .tag_protocol = DSA_TAG_PROTO_EDSA, 4628 .ops = &mv88e6123_ops, 4629 }, 4630 4631 [MV88E6131] = { 4632 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4633 .family = MV88E6XXX_FAMILY_6185, 4634 .name = "Marvell 88E6131", 4635 .num_databases = 256, 4636 .num_macs = 8192, 4637 .num_ports = 8, 4638 .num_internal_phys = 0, 4639 .max_vid = 4095, 4640 .port_base_addr = 0x10, 4641 .phy_base_addr = 0x0, 4642 .global1_addr = 0x1b, 4643 .global2_addr = 0x1c, 4644 .age_time_coeff = 15000, 4645 .g1_irqs = 9, 4646 .atu_move_port_mask = 0xf, 4647 .multi_chip = true, 4648 .tag_protocol = DSA_TAG_PROTO_DSA, 4649 .ops = &mv88e6131_ops, 4650 }, 4651 4652 [MV88E6141] = { 4653 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4654 .family = MV88E6XXX_FAMILY_6341, 4655 .name = "Marvell 88E6141", 4656 .num_databases = 4096, 4657 .num_macs = 2048, 4658 .num_ports = 6, 4659 .num_internal_phys = 5, 4660 .num_gpio = 11, 4661 .max_vid = 4095, 4662 .port_base_addr = 0x10, 4663 .phy_base_addr = 0x10, 4664 .global1_addr = 0x1b, 4665 .global2_addr = 0x1c, 4666 .age_time_coeff = 3750, 4667 .atu_move_port_mask = 0x1f, 4668 .g1_irqs = 9, 4669 .g2_irqs = 10, 4670 .pvt = true, 4671 .multi_chip = true, 4672 .tag_protocol = DSA_TAG_PROTO_EDSA, 4673 .ops = &mv88e6141_ops, 4674 }, 4675 4676 [MV88E6161] = { 4677 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4678 .family = MV88E6XXX_FAMILY_6165, 4679 .name = "Marvell 88E6161", 4680 .num_databases = 4096, 4681 .num_macs = 1024, 4682 .num_ports = 6, 4683 .num_internal_phys = 5, 4684 .max_vid = 4095, 4685 .port_base_addr = 0x10, 4686 .phy_base_addr = 0x0, 4687 .global1_addr = 0x1b, 4688 .global2_addr = 0x1c, 4689 .age_time_coeff = 15000, 4690 .g1_irqs = 9, 4691 .g2_irqs = 10, 4692 .atu_move_port_mask = 0xf, 4693 .pvt = true, 4694 .multi_chip = true, 4695 .tag_protocol = DSA_TAG_PROTO_EDSA, 4696 .ptp_support = true, 4697 .ops = &mv88e6161_ops, 4698 }, 4699 4700 [MV88E6165] = { 4701 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4702 .family = MV88E6XXX_FAMILY_6165, 4703 .name = "Marvell 88E6165", 4704 .num_databases = 4096, 4705 .num_macs = 8192, 4706 .num_ports = 6, 4707 .num_internal_phys = 0, 4708 .max_vid = 4095, 4709 .port_base_addr = 0x10, 4710 .phy_base_addr = 0x0, 4711 .global1_addr = 0x1b, 4712 .global2_addr = 0x1c, 4713 .age_time_coeff = 15000, 4714 .g1_irqs = 9, 4715 .g2_irqs = 10, 4716 .atu_move_port_mask = 0xf, 4717 .pvt = true, 4718 .multi_chip = true, 4719 .tag_protocol = DSA_TAG_PROTO_DSA, 4720 .ptp_support = true, 4721 .ops = &mv88e6165_ops, 4722 }, 4723 4724 [MV88E6171] = { 4725 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4726 .family = MV88E6XXX_FAMILY_6351, 4727 .name = "Marvell 88E6171", 4728 .num_databases = 4096, 4729 .num_macs = 8192, 4730 .num_ports = 7, 4731 .num_internal_phys = 5, 4732 .max_vid = 4095, 4733 .port_base_addr = 0x10, 4734 .phy_base_addr = 0x0, 4735 .global1_addr = 0x1b, 4736 .global2_addr = 0x1c, 4737 .age_time_coeff = 15000, 4738 .g1_irqs = 9, 4739 .g2_irqs = 10, 4740 .atu_move_port_mask = 0xf, 4741 .pvt = true, 4742 .multi_chip = true, 4743 .tag_protocol = DSA_TAG_PROTO_EDSA, 4744 .ops = &mv88e6171_ops, 4745 }, 4746 4747 [MV88E6172] = { 4748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4749 .family = MV88E6XXX_FAMILY_6352, 4750 .name = "Marvell 88E6172", 4751 .num_databases = 4096, 4752 .num_macs = 8192, 4753 .num_ports = 7, 4754 .num_internal_phys = 5, 4755 .num_gpio = 15, 4756 .max_vid = 4095, 4757 .port_base_addr = 0x10, 4758 .phy_base_addr = 0x0, 4759 .global1_addr = 0x1b, 4760 .global2_addr = 0x1c, 4761 .age_time_coeff = 15000, 4762 .g1_irqs = 9, 4763 .g2_irqs = 10, 4764 .atu_move_port_mask = 0xf, 4765 .pvt = true, 4766 .multi_chip = true, 4767 .tag_protocol = DSA_TAG_PROTO_EDSA, 4768 .ops = &mv88e6172_ops, 4769 }, 4770 4771 [MV88E6175] = { 4772 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4773 .family = MV88E6XXX_FAMILY_6351, 4774 .name = "Marvell 88E6175", 4775 .num_databases = 4096, 4776 .num_macs = 8192, 4777 .num_ports = 7, 4778 .num_internal_phys = 5, 4779 .max_vid = 4095, 4780 .port_base_addr = 0x10, 4781 .phy_base_addr = 0x0, 4782 .global1_addr = 0x1b, 4783 .global2_addr = 0x1c, 4784 .age_time_coeff = 15000, 4785 .g1_irqs = 9, 4786 .g2_irqs = 10, 4787 .atu_move_port_mask = 0xf, 4788 .pvt = true, 4789 .multi_chip = true, 4790 .tag_protocol = DSA_TAG_PROTO_EDSA, 4791 .ops = &mv88e6175_ops, 4792 }, 4793 4794 [MV88E6176] = { 4795 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4796 .family = MV88E6XXX_FAMILY_6352, 4797 .name = "Marvell 88E6176", 4798 .num_databases = 4096, 4799 .num_macs = 8192, 4800 .num_ports = 7, 4801 .num_internal_phys = 5, 4802 .num_gpio = 15, 4803 .max_vid = 4095, 4804 .port_base_addr = 0x10, 4805 .phy_base_addr = 0x0, 4806 .global1_addr = 0x1b, 4807 .global2_addr = 0x1c, 4808 .age_time_coeff = 15000, 4809 .g1_irqs = 9, 4810 .g2_irqs = 10, 4811 .atu_move_port_mask = 0xf, 4812 .pvt = true, 4813 .multi_chip = true, 4814 .tag_protocol = DSA_TAG_PROTO_EDSA, 4815 .ops = &mv88e6176_ops, 4816 }, 4817 4818 [MV88E6185] = { 4819 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4820 .family = MV88E6XXX_FAMILY_6185, 4821 .name = "Marvell 88E6185", 4822 .num_databases = 256, 4823 .num_macs = 8192, 4824 .num_ports = 10, 4825 .num_internal_phys = 0, 4826 .max_vid = 4095, 4827 .port_base_addr = 0x10, 4828 .phy_base_addr = 0x0, 4829 .global1_addr = 0x1b, 4830 .global2_addr = 0x1c, 4831 .age_time_coeff = 15000, 4832 .g1_irqs = 8, 4833 .atu_move_port_mask = 0xf, 4834 .multi_chip = true, 4835 .tag_protocol = DSA_TAG_PROTO_EDSA, 4836 .ops = &mv88e6185_ops, 4837 }, 4838 4839 [MV88E6190] = { 4840 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4841 .family = MV88E6XXX_FAMILY_6390, 4842 .name = "Marvell 88E6190", 4843 .num_databases = 4096, 4844 .num_macs = 16384, 4845 .num_ports = 11, /* 10 + Z80 */ 4846 .num_internal_phys = 9, 4847 .num_gpio = 16, 4848 .max_vid = 8191, 4849 .port_base_addr = 0x0, 4850 .phy_base_addr = 0x0, 4851 .global1_addr = 0x1b, 4852 .global2_addr = 0x1c, 4853 .tag_protocol = DSA_TAG_PROTO_DSA, 4854 .age_time_coeff = 3750, 4855 .g1_irqs = 9, 4856 .g2_irqs = 14, 4857 .pvt = true, 4858 .multi_chip = true, 4859 .atu_move_port_mask = 0x1f, 4860 .ops = &mv88e6190_ops, 4861 }, 4862 4863 [MV88E6190X] = { 4864 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4865 .family = MV88E6XXX_FAMILY_6390, 4866 .name = "Marvell 88E6190X", 4867 .num_databases = 4096, 4868 .num_macs = 16384, 4869 .num_ports = 11, /* 10 + Z80 */ 4870 .num_internal_phys = 9, 4871 .num_gpio = 16, 4872 .max_vid = 8191, 4873 .port_base_addr = 0x0, 4874 .phy_base_addr = 0x0, 4875 .global1_addr = 0x1b, 4876 .global2_addr = 0x1c, 4877 .age_time_coeff = 3750, 4878 .g1_irqs = 9, 4879 .g2_irqs = 14, 4880 .atu_move_port_mask = 0x1f, 4881 .pvt = true, 4882 .multi_chip = true, 4883 .tag_protocol = DSA_TAG_PROTO_DSA, 4884 .ops = &mv88e6190x_ops, 4885 }, 4886 4887 [MV88E6191] = { 4888 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4889 .family = MV88E6XXX_FAMILY_6390, 4890 .name = "Marvell 88E6191", 4891 .num_databases = 4096, 4892 .num_macs = 16384, 4893 .num_ports = 11, /* 10 + Z80 */ 4894 .num_internal_phys = 9, 4895 .max_vid = 8191, 4896 .port_base_addr = 0x0, 4897 .phy_base_addr = 0x0, 4898 .global1_addr = 0x1b, 4899 .global2_addr = 0x1c, 4900 .age_time_coeff = 3750, 4901 .g1_irqs = 9, 4902 .g2_irqs = 14, 4903 .atu_move_port_mask = 0x1f, 4904 .pvt = true, 4905 .multi_chip = true, 4906 .tag_protocol = DSA_TAG_PROTO_DSA, 4907 .ptp_support = true, 4908 .ops = &mv88e6191_ops, 4909 }, 4910 4911 [MV88E6220] = { 4912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4913 .family = MV88E6XXX_FAMILY_6250, 4914 .name = "Marvell 88E6220", 4915 .num_databases = 64, 4916 4917 /* Ports 2-4 are not routed to pins 4918 * => usable ports 0, 1, 5, 6 4919 */ 4920 .num_ports = 7, 4921 .num_internal_phys = 2, 4922 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4923 .max_vid = 4095, 4924 .port_base_addr = 0x08, 4925 .phy_base_addr = 0x00, 4926 .global1_addr = 0x0f, 4927 .global2_addr = 0x07, 4928 .age_time_coeff = 15000, 4929 .g1_irqs = 9, 4930 .g2_irqs = 10, 4931 .atu_move_port_mask = 0xf, 4932 .dual_chip = true, 4933 .tag_protocol = DSA_TAG_PROTO_DSA, 4934 .ptp_support = true, 4935 .ops = &mv88e6250_ops, 4936 }, 4937 4938 [MV88E6240] = { 4939 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4940 .family = MV88E6XXX_FAMILY_6352, 4941 .name = "Marvell 88E6240", 4942 .num_databases = 4096, 4943 .num_macs = 8192, 4944 .num_ports = 7, 4945 .num_internal_phys = 5, 4946 .num_gpio = 15, 4947 .max_vid = 4095, 4948 .port_base_addr = 0x10, 4949 .phy_base_addr = 0x0, 4950 .global1_addr = 0x1b, 4951 .global2_addr = 0x1c, 4952 .age_time_coeff = 15000, 4953 .g1_irqs = 9, 4954 .g2_irqs = 10, 4955 .atu_move_port_mask = 0xf, 4956 .pvt = true, 4957 .multi_chip = true, 4958 .tag_protocol = DSA_TAG_PROTO_EDSA, 4959 .ptp_support = true, 4960 .ops = &mv88e6240_ops, 4961 }, 4962 4963 [MV88E6250] = { 4964 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4965 .family = MV88E6XXX_FAMILY_6250, 4966 .name = "Marvell 88E6250", 4967 .num_databases = 64, 4968 .num_ports = 7, 4969 .num_internal_phys = 5, 4970 .max_vid = 4095, 4971 .port_base_addr = 0x08, 4972 .phy_base_addr = 0x00, 4973 .global1_addr = 0x0f, 4974 .global2_addr = 0x07, 4975 .age_time_coeff = 15000, 4976 .g1_irqs = 9, 4977 .g2_irqs = 10, 4978 .atu_move_port_mask = 0xf, 4979 .dual_chip = true, 4980 .tag_protocol = DSA_TAG_PROTO_DSA, 4981 .ptp_support = true, 4982 .ops = &mv88e6250_ops, 4983 }, 4984 4985 [MV88E6290] = { 4986 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4987 .family = MV88E6XXX_FAMILY_6390, 4988 .name = "Marvell 88E6290", 4989 .num_databases = 4096, 4990 .num_ports = 11, /* 10 + Z80 */ 4991 .num_internal_phys = 9, 4992 .num_gpio = 16, 4993 .max_vid = 8191, 4994 .port_base_addr = 0x0, 4995 .phy_base_addr = 0x0, 4996 .global1_addr = 0x1b, 4997 .global2_addr = 0x1c, 4998 .age_time_coeff = 3750, 4999 .g1_irqs = 9, 5000 .g2_irqs = 14, 5001 .atu_move_port_mask = 0x1f, 5002 .pvt = true, 5003 .multi_chip = true, 5004 .tag_protocol = DSA_TAG_PROTO_DSA, 5005 .ptp_support = true, 5006 .ops = &mv88e6290_ops, 5007 }, 5008 5009 [MV88E6320] = { 5010 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5011 .family = MV88E6XXX_FAMILY_6320, 5012 .name = "Marvell 88E6320", 5013 .num_databases = 4096, 5014 .num_macs = 8192, 5015 .num_ports = 7, 5016 .num_internal_phys = 5, 5017 .num_gpio = 15, 5018 .max_vid = 4095, 5019 .port_base_addr = 0x10, 5020 .phy_base_addr = 0x0, 5021 .global1_addr = 0x1b, 5022 .global2_addr = 0x1c, 5023 .age_time_coeff = 15000, 5024 .g1_irqs = 8, 5025 .g2_irqs = 10, 5026 .atu_move_port_mask = 0xf, 5027 .pvt = true, 5028 .multi_chip = true, 5029 .tag_protocol = DSA_TAG_PROTO_EDSA, 5030 .ptp_support = true, 5031 .ops = &mv88e6320_ops, 5032 }, 5033 5034 [MV88E6321] = { 5035 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5036 .family = MV88E6XXX_FAMILY_6320, 5037 .name = "Marvell 88E6321", 5038 .num_databases = 4096, 5039 .num_macs = 8192, 5040 .num_ports = 7, 5041 .num_internal_phys = 5, 5042 .num_gpio = 15, 5043 .max_vid = 4095, 5044 .port_base_addr = 0x10, 5045 .phy_base_addr = 0x0, 5046 .global1_addr = 0x1b, 5047 .global2_addr = 0x1c, 5048 .age_time_coeff = 15000, 5049 .g1_irqs = 8, 5050 .g2_irqs = 10, 5051 .atu_move_port_mask = 0xf, 5052 .multi_chip = true, 5053 .tag_protocol = DSA_TAG_PROTO_EDSA, 5054 .ptp_support = true, 5055 .ops = &mv88e6321_ops, 5056 }, 5057 5058 [MV88E6341] = { 5059 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5060 .family = MV88E6XXX_FAMILY_6341, 5061 .name = "Marvell 88E6341", 5062 .num_databases = 4096, 5063 .num_macs = 2048, 5064 .num_internal_phys = 5, 5065 .num_ports = 6, 5066 .num_gpio = 11, 5067 .max_vid = 4095, 5068 .port_base_addr = 0x10, 5069 .phy_base_addr = 0x10, 5070 .global1_addr = 0x1b, 5071 .global2_addr = 0x1c, 5072 .age_time_coeff = 3750, 5073 .atu_move_port_mask = 0x1f, 5074 .g1_irqs = 9, 5075 .g2_irqs = 10, 5076 .pvt = true, 5077 .multi_chip = true, 5078 .tag_protocol = DSA_TAG_PROTO_EDSA, 5079 .ptp_support = true, 5080 .ops = &mv88e6341_ops, 5081 }, 5082 5083 [MV88E6350] = { 5084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5085 .family = MV88E6XXX_FAMILY_6351, 5086 .name = "Marvell 88E6350", 5087 .num_databases = 4096, 5088 .num_macs = 8192, 5089 .num_ports = 7, 5090 .num_internal_phys = 5, 5091 .max_vid = 4095, 5092 .port_base_addr = 0x10, 5093 .phy_base_addr = 0x0, 5094 .global1_addr = 0x1b, 5095 .global2_addr = 0x1c, 5096 .age_time_coeff = 15000, 5097 .g1_irqs = 9, 5098 .g2_irqs = 10, 5099 .atu_move_port_mask = 0xf, 5100 .pvt = true, 5101 .multi_chip = true, 5102 .tag_protocol = DSA_TAG_PROTO_EDSA, 5103 .ops = &mv88e6350_ops, 5104 }, 5105 5106 [MV88E6351] = { 5107 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5108 .family = MV88E6XXX_FAMILY_6351, 5109 .name = "Marvell 88E6351", 5110 .num_databases = 4096, 5111 .num_macs = 8192, 5112 .num_ports = 7, 5113 .num_internal_phys = 5, 5114 .max_vid = 4095, 5115 .port_base_addr = 0x10, 5116 .phy_base_addr = 0x0, 5117 .global1_addr = 0x1b, 5118 .global2_addr = 0x1c, 5119 .age_time_coeff = 15000, 5120 .g1_irqs = 9, 5121 .g2_irqs = 10, 5122 .atu_move_port_mask = 0xf, 5123 .pvt = true, 5124 .multi_chip = true, 5125 .tag_protocol = DSA_TAG_PROTO_EDSA, 5126 .ops = &mv88e6351_ops, 5127 }, 5128 5129 [MV88E6352] = { 5130 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5131 .family = MV88E6XXX_FAMILY_6352, 5132 .name = "Marvell 88E6352", 5133 .num_databases = 4096, 5134 .num_macs = 8192, 5135 .num_ports = 7, 5136 .num_internal_phys = 5, 5137 .num_gpio = 15, 5138 .max_vid = 4095, 5139 .port_base_addr = 0x10, 5140 .phy_base_addr = 0x0, 5141 .global1_addr = 0x1b, 5142 .global2_addr = 0x1c, 5143 .age_time_coeff = 15000, 5144 .g1_irqs = 9, 5145 .g2_irqs = 10, 5146 .atu_move_port_mask = 0xf, 5147 .pvt = true, 5148 .multi_chip = true, 5149 .tag_protocol = DSA_TAG_PROTO_EDSA, 5150 .ptp_support = true, 5151 .ops = &mv88e6352_ops, 5152 }, 5153 [MV88E6390] = { 5154 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5155 .family = MV88E6XXX_FAMILY_6390, 5156 .name = "Marvell 88E6390", 5157 .num_databases = 4096, 5158 .num_macs = 16384, 5159 .num_ports = 11, /* 10 + Z80 */ 5160 .num_internal_phys = 9, 5161 .num_gpio = 16, 5162 .max_vid = 8191, 5163 .port_base_addr = 0x0, 5164 .phy_base_addr = 0x0, 5165 .global1_addr = 0x1b, 5166 .global2_addr = 0x1c, 5167 .age_time_coeff = 3750, 5168 .g1_irqs = 9, 5169 .g2_irqs = 14, 5170 .atu_move_port_mask = 0x1f, 5171 .pvt = true, 5172 .multi_chip = true, 5173 .tag_protocol = DSA_TAG_PROTO_DSA, 5174 .ptp_support = true, 5175 .ops = &mv88e6390_ops, 5176 }, 5177 [MV88E6390X] = { 5178 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5179 .family = MV88E6XXX_FAMILY_6390, 5180 .name = "Marvell 88E6390X", 5181 .num_databases = 4096, 5182 .num_macs = 16384, 5183 .num_ports = 11, /* 10 + Z80 */ 5184 .num_internal_phys = 9, 5185 .num_gpio = 16, 5186 .max_vid = 8191, 5187 .port_base_addr = 0x0, 5188 .phy_base_addr = 0x0, 5189 .global1_addr = 0x1b, 5190 .global2_addr = 0x1c, 5191 .age_time_coeff = 3750, 5192 .g1_irqs = 9, 5193 .g2_irqs = 14, 5194 .atu_move_port_mask = 0x1f, 5195 .pvt = true, 5196 .multi_chip = true, 5197 .tag_protocol = DSA_TAG_PROTO_DSA, 5198 .ptp_support = true, 5199 .ops = &mv88e6390x_ops, 5200 }, 5201 }; 5202 5203 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5204 { 5205 int i; 5206 5207 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5208 if (mv88e6xxx_table[i].prod_num == prod_num) 5209 return &mv88e6xxx_table[i]; 5210 5211 return NULL; 5212 } 5213 5214 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5215 { 5216 const struct mv88e6xxx_info *info; 5217 unsigned int prod_num, rev; 5218 u16 id; 5219 int err; 5220 5221 mv88e6xxx_reg_lock(chip); 5222 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5223 mv88e6xxx_reg_unlock(chip); 5224 if (err) 5225 return err; 5226 5227 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5228 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5229 5230 info = mv88e6xxx_lookup_info(prod_num); 5231 if (!info) 5232 return -ENODEV; 5233 5234 /* Update the compatible info with the probed one */ 5235 chip->info = info; 5236 5237 err = mv88e6xxx_g2_require(chip); 5238 if (err) 5239 return err; 5240 5241 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5242 chip->info->prod_num, chip->info->name, rev); 5243 5244 return 0; 5245 } 5246 5247 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5248 { 5249 struct mv88e6xxx_chip *chip; 5250 5251 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5252 if (!chip) 5253 return NULL; 5254 5255 chip->dev = dev; 5256 5257 mutex_init(&chip->reg_lock); 5258 INIT_LIST_HEAD(&chip->mdios); 5259 idr_init(&chip->policies); 5260 5261 return chip; 5262 } 5263 5264 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5265 int port, 5266 enum dsa_tag_protocol m) 5267 { 5268 struct mv88e6xxx_chip *chip = ds->priv; 5269 5270 return chip->info->tag_protocol; 5271 } 5272 5273 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5274 const struct switchdev_obj_port_mdb *mdb) 5275 { 5276 /* We don't need any dynamic resource from the kernel (yet), 5277 * so skip the prepare phase. 5278 */ 5279 5280 return 0; 5281 } 5282 5283 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5284 const struct switchdev_obj_port_mdb *mdb) 5285 { 5286 struct mv88e6xxx_chip *chip = ds->priv; 5287 5288 mv88e6xxx_reg_lock(chip); 5289 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5290 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5291 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5292 port); 5293 mv88e6xxx_reg_unlock(chip); 5294 } 5295 5296 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5297 const struct switchdev_obj_port_mdb *mdb) 5298 { 5299 struct mv88e6xxx_chip *chip = ds->priv; 5300 int err; 5301 5302 mv88e6xxx_reg_lock(chip); 5303 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5304 mv88e6xxx_reg_unlock(chip); 5305 5306 return err; 5307 } 5308 5309 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5310 struct dsa_mall_mirror_tc_entry *mirror, 5311 bool ingress) 5312 { 5313 enum mv88e6xxx_egress_direction direction = ingress ? 5314 MV88E6XXX_EGRESS_DIR_INGRESS : 5315 MV88E6XXX_EGRESS_DIR_EGRESS; 5316 struct mv88e6xxx_chip *chip = ds->priv; 5317 bool other_mirrors = false; 5318 int i; 5319 int err; 5320 5321 if (!chip->info->ops->set_egress_port) 5322 return -EOPNOTSUPP; 5323 5324 mutex_lock(&chip->reg_lock); 5325 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5326 mirror->to_local_port) { 5327 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5328 other_mirrors |= ingress ? 5329 chip->ports[i].mirror_ingress : 5330 chip->ports[i].mirror_egress; 5331 5332 /* Can't change egress port when other mirror is active */ 5333 if (other_mirrors) { 5334 err = -EBUSY; 5335 goto out; 5336 } 5337 5338 err = chip->info->ops->set_egress_port(chip, 5339 direction, 5340 mirror->to_local_port); 5341 if (err) 5342 goto out; 5343 } 5344 5345 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5346 out: 5347 mutex_unlock(&chip->reg_lock); 5348 5349 return err; 5350 } 5351 5352 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5353 struct dsa_mall_mirror_tc_entry *mirror) 5354 { 5355 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5356 MV88E6XXX_EGRESS_DIR_INGRESS : 5357 MV88E6XXX_EGRESS_DIR_EGRESS; 5358 struct mv88e6xxx_chip *chip = ds->priv; 5359 bool other_mirrors = false; 5360 int i; 5361 5362 mutex_lock(&chip->reg_lock); 5363 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5364 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5365 5366 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5367 other_mirrors |= mirror->ingress ? 5368 chip->ports[i].mirror_ingress : 5369 chip->ports[i].mirror_egress; 5370 5371 /* Reset egress port when no other mirror is active */ 5372 if (!other_mirrors) { 5373 if (chip->info->ops->set_egress_port(chip, 5374 direction, 5375 dsa_upstream_port(ds, 5376 port))) 5377 dev_err(ds->dev, "failed to set egress port\n"); 5378 } 5379 5380 mutex_unlock(&chip->reg_lock); 5381 } 5382 5383 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5384 bool unicast, bool multicast) 5385 { 5386 struct mv88e6xxx_chip *chip = ds->priv; 5387 int err = -EOPNOTSUPP; 5388 5389 mv88e6xxx_reg_lock(chip); 5390 if (chip->info->ops->port_set_egress_floods) 5391 err = chip->info->ops->port_set_egress_floods(chip, port, 5392 unicast, 5393 multicast); 5394 mv88e6xxx_reg_unlock(chip); 5395 5396 return err; 5397 } 5398 5399 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5400 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5401 .setup = mv88e6xxx_setup, 5402 .teardown = mv88e6xxx_teardown, 5403 .phylink_validate = mv88e6xxx_validate, 5404 .phylink_mac_link_state = mv88e6xxx_link_state, 5405 .phylink_mac_config = mv88e6xxx_mac_config, 5406 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5407 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5408 .get_strings = mv88e6xxx_get_strings, 5409 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5410 .get_sset_count = mv88e6xxx_get_sset_count, 5411 .port_enable = mv88e6xxx_port_enable, 5412 .port_disable = mv88e6xxx_port_disable, 5413 .get_mac_eee = mv88e6xxx_get_mac_eee, 5414 .set_mac_eee = mv88e6xxx_set_mac_eee, 5415 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5416 .get_eeprom = mv88e6xxx_get_eeprom, 5417 .set_eeprom = mv88e6xxx_set_eeprom, 5418 .get_regs_len = mv88e6xxx_get_regs_len, 5419 .get_regs = mv88e6xxx_get_regs, 5420 .get_rxnfc = mv88e6xxx_get_rxnfc, 5421 .set_rxnfc = mv88e6xxx_set_rxnfc, 5422 .set_ageing_time = mv88e6xxx_set_ageing_time, 5423 .port_bridge_join = mv88e6xxx_port_bridge_join, 5424 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5425 .port_egress_floods = mv88e6xxx_port_egress_floods, 5426 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5427 .port_fast_age = mv88e6xxx_port_fast_age, 5428 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5429 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5430 .port_vlan_add = mv88e6xxx_port_vlan_add, 5431 .port_vlan_del = mv88e6xxx_port_vlan_del, 5432 .port_fdb_add = mv88e6xxx_port_fdb_add, 5433 .port_fdb_del = mv88e6xxx_port_fdb_del, 5434 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5435 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5436 .port_mdb_add = mv88e6xxx_port_mdb_add, 5437 .port_mdb_del = mv88e6xxx_port_mdb_del, 5438 .port_mirror_add = mv88e6xxx_port_mirror_add, 5439 .port_mirror_del = mv88e6xxx_port_mirror_del, 5440 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5441 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5442 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5443 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5444 .port_txtstamp = mv88e6xxx_port_txtstamp, 5445 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5446 .get_ts_info = mv88e6xxx_get_ts_info, 5447 .devlink_param_get = mv88e6xxx_devlink_param_get, 5448 .devlink_param_set = mv88e6xxx_devlink_param_set, 5449 }; 5450 5451 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5452 { 5453 struct device *dev = chip->dev; 5454 struct dsa_switch *ds; 5455 5456 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5457 if (!ds) 5458 return -ENOMEM; 5459 5460 ds->dev = dev; 5461 ds->num_ports = mv88e6xxx_num_ports(chip); 5462 ds->priv = chip; 5463 ds->dev = dev; 5464 ds->ops = &mv88e6xxx_switch_ops; 5465 ds->ageing_time_min = chip->info->age_time_coeff; 5466 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5467 5468 dev_set_drvdata(dev, ds); 5469 5470 return dsa_register_switch(ds); 5471 } 5472 5473 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5474 { 5475 dsa_unregister_switch(chip->ds); 5476 } 5477 5478 static const void *pdata_device_get_match_data(struct device *dev) 5479 { 5480 const struct of_device_id *matches = dev->driver->of_match_table; 5481 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5482 5483 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5484 matches++) { 5485 if (!strcmp(pdata->compatible, matches->compatible)) 5486 return matches->data; 5487 } 5488 return NULL; 5489 } 5490 5491 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5492 * would be lost after a power cycle so prevent it to be suspended. 5493 */ 5494 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5495 { 5496 return -EOPNOTSUPP; 5497 } 5498 5499 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5500 { 5501 return 0; 5502 } 5503 5504 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5505 5506 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5507 { 5508 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5509 const struct mv88e6xxx_info *compat_info = NULL; 5510 struct device *dev = &mdiodev->dev; 5511 struct device_node *np = dev->of_node; 5512 struct mv88e6xxx_chip *chip; 5513 int port; 5514 int err; 5515 5516 if (!np && !pdata) 5517 return -EINVAL; 5518 5519 if (np) 5520 compat_info = of_device_get_match_data(dev); 5521 5522 if (pdata) { 5523 compat_info = pdata_device_get_match_data(dev); 5524 5525 if (!pdata->netdev) 5526 return -EINVAL; 5527 5528 for (port = 0; port < DSA_MAX_PORTS; port++) { 5529 if (!(pdata->enabled_ports & (1 << port))) 5530 continue; 5531 if (strcmp(pdata->cd.port_names[port], "cpu")) 5532 continue; 5533 pdata->cd.netdev[port] = &pdata->netdev->dev; 5534 break; 5535 } 5536 } 5537 5538 if (!compat_info) 5539 return -EINVAL; 5540 5541 chip = mv88e6xxx_alloc_chip(dev); 5542 if (!chip) { 5543 err = -ENOMEM; 5544 goto out; 5545 } 5546 5547 chip->info = compat_info; 5548 5549 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5550 if (err) 5551 goto out; 5552 5553 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5554 if (IS_ERR(chip->reset)) { 5555 err = PTR_ERR(chip->reset); 5556 goto out; 5557 } 5558 if (chip->reset) 5559 usleep_range(1000, 2000); 5560 5561 err = mv88e6xxx_detect(chip); 5562 if (err) 5563 goto out; 5564 5565 mv88e6xxx_phy_init(chip); 5566 5567 if (chip->info->ops->get_eeprom) { 5568 if (np) 5569 of_property_read_u32(np, "eeprom-length", 5570 &chip->eeprom_len); 5571 else 5572 chip->eeprom_len = pdata->eeprom_len; 5573 } 5574 5575 mv88e6xxx_reg_lock(chip); 5576 err = mv88e6xxx_switch_reset(chip); 5577 mv88e6xxx_reg_unlock(chip); 5578 if (err) 5579 goto out; 5580 5581 if (np) { 5582 chip->irq = of_irq_get(np, 0); 5583 if (chip->irq == -EPROBE_DEFER) { 5584 err = chip->irq; 5585 goto out; 5586 } 5587 } 5588 5589 if (pdata) 5590 chip->irq = pdata->irq; 5591 5592 /* Has to be performed before the MDIO bus is created, because 5593 * the PHYs will link their interrupts to these interrupt 5594 * controllers 5595 */ 5596 mv88e6xxx_reg_lock(chip); 5597 if (chip->irq > 0) 5598 err = mv88e6xxx_g1_irq_setup(chip); 5599 else 5600 err = mv88e6xxx_irq_poll_setup(chip); 5601 mv88e6xxx_reg_unlock(chip); 5602 5603 if (err) 5604 goto out; 5605 5606 if (chip->info->g2_irqs > 0) { 5607 err = mv88e6xxx_g2_irq_setup(chip); 5608 if (err) 5609 goto out_g1_irq; 5610 } 5611 5612 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5613 if (err) 5614 goto out_g2_irq; 5615 5616 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5617 if (err) 5618 goto out_g1_atu_prob_irq; 5619 5620 err = mv88e6xxx_mdios_register(chip, np); 5621 if (err) 5622 goto out_g1_vtu_prob_irq; 5623 5624 err = mv88e6xxx_register_switch(chip); 5625 if (err) 5626 goto out_mdio; 5627 5628 return 0; 5629 5630 out_mdio: 5631 mv88e6xxx_mdios_unregister(chip); 5632 out_g1_vtu_prob_irq: 5633 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5634 out_g1_atu_prob_irq: 5635 mv88e6xxx_g1_atu_prob_irq_free(chip); 5636 out_g2_irq: 5637 if (chip->info->g2_irqs > 0) 5638 mv88e6xxx_g2_irq_free(chip); 5639 out_g1_irq: 5640 if (chip->irq > 0) 5641 mv88e6xxx_g1_irq_free(chip); 5642 else 5643 mv88e6xxx_irq_poll_free(chip); 5644 out: 5645 if (pdata) 5646 dev_put(pdata->netdev); 5647 5648 return err; 5649 } 5650 5651 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5652 { 5653 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5654 struct mv88e6xxx_chip *chip = ds->priv; 5655 5656 if (chip->info->ptp_support) { 5657 mv88e6xxx_hwtstamp_free(chip); 5658 mv88e6xxx_ptp_free(chip); 5659 } 5660 5661 mv88e6xxx_phy_destroy(chip); 5662 mv88e6xxx_unregister_switch(chip); 5663 mv88e6xxx_mdios_unregister(chip); 5664 5665 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5666 mv88e6xxx_g1_atu_prob_irq_free(chip); 5667 5668 if (chip->info->g2_irqs > 0) 5669 mv88e6xxx_g2_irq_free(chip); 5670 5671 if (chip->irq > 0) 5672 mv88e6xxx_g1_irq_free(chip); 5673 else 5674 mv88e6xxx_irq_poll_free(chip); 5675 } 5676 5677 static const struct of_device_id mv88e6xxx_of_match[] = { 5678 { 5679 .compatible = "marvell,mv88e6085", 5680 .data = &mv88e6xxx_table[MV88E6085], 5681 }, 5682 { 5683 .compatible = "marvell,mv88e6190", 5684 .data = &mv88e6xxx_table[MV88E6190], 5685 }, 5686 { 5687 .compatible = "marvell,mv88e6250", 5688 .data = &mv88e6xxx_table[MV88E6250], 5689 }, 5690 { /* sentinel */ }, 5691 }; 5692 5693 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5694 5695 static struct mdio_driver mv88e6xxx_driver = { 5696 .probe = mv88e6xxx_probe, 5697 .remove = mv88e6xxx_remove, 5698 .mdiodrv.driver = { 5699 .name = "mv88e6085", 5700 .of_match_table = mv88e6xxx_of_match, 5701 .pm = &mv88e6xxx_pm_ops, 5702 }, 5703 }; 5704 5705 mdio_module_driver(mv88e6xxx_driver); 5706 5707 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5708 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5709 MODULE_LICENSE("GPL"); 5710