1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 453 mode = chip->info->ops->port_max_speed_mode(port); 454 455 if (chip->info->ops->port_set_pause) { 456 err = chip->info->ops->port_set_pause(chip, port, pause); 457 if (err) 458 goto restore_link; 459 } 460 461 err = mv88e6xxx_port_config_interface(chip, port, mode); 462 restore_link: 463 if (chip->info->ops->port_set_link(chip, port, link)) 464 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 465 466 return err; 467 } 468 469 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 470 { 471 struct mv88e6xxx_chip *chip = ds->priv; 472 473 return port < chip->info->num_internal_phys; 474 } 475 476 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 477 { 478 u16 reg; 479 int err; 480 481 /* The 88e6250 family does not have the PHY detect bit. Instead, 482 * report whether the port is internal. 483 */ 484 if (chip->info->family == MV88E6XXX_FAMILY_6250) 485 return port < chip->info->num_internal_phys; 486 487 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 488 if (err) { 489 dev_err(chip->dev, 490 "p%d: %s: failed to read port status\n", 491 port, __func__); 492 return err; 493 } 494 495 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 496 } 497 498 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 499 struct phylink_link_state *state) 500 { 501 struct mv88e6xxx_chip *chip = ds->priv; 502 int lane; 503 int err; 504 505 mv88e6xxx_reg_lock(chip); 506 lane = mv88e6xxx_serdes_get_lane(chip, port); 507 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 508 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 509 state); 510 else 511 err = -EOPNOTSUPP; 512 mv88e6xxx_reg_unlock(chip); 513 514 return err; 515 } 516 517 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 518 unsigned int mode, 519 phy_interface_t interface, 520 const unsigned long *advertise) 521 { 522 const struct mv88e6xxx_ops *ops = chip->info->ops; 523 int lane; 524 525 if (ops->serdes_pcs_config) { 526 lane = mv88e6xxx_serdes_get_lane(chip, port); 527 if (lane >= 0) 528 return ops->serdes_pcs_config(chip, port, lane, mode, 529 interface, advertise); 530 } 531 532 return 0; 533 } 534 535 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 536 { 537 struct mv88e6xxx_chip *chip = ds->priv; 538 const struct mv88e6xxx_ops *ops; 539 int err = 0; 540 int lane; 541 542 ops = chip->info->ops; 543 544 if (ops->serdes_pcs_an_restart) { 545 mv88e6xxx_reg_lock(chip); 546 lane = mv88e6xxx_serdes_get_lane(chip, port); 547 if (lane >= 0) 548 err = ops->serdes_pcs_an_restart(chip, port, lane); 549 mv88e6xxx_reg_unlock(chip); 550 551 if (err) 552 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 553 } 554 } 555 556 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 557 unsigned int mode, 558 int speed, int duplex) 559 { 560 const struct mv88e6xxx_ops *ops = chip->info->ops; 561 int lane; 562 563 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 564 lane = mv88e6xxx_serdes_get_lane(chip, port); 565 if (lane >= 0) 566 return ops->serdes_pcs_link_up(chip, port, lane, 567 speed, duplex); 568 } 569 570 return 0; 571 } 572 573 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 574 unsigned long *mask, 575 struct phylink_link_state *state) 576 { 577 if (!phy_interface_mode_is_8023z(state->interface)) { 578 /* 10M and 100M are only supported in non-802.3z mode */ 579 phylink_set(mask, 10baseT_Half); 580 phylink_set(mask, 10baseT_Full); 581 phylink_set(mask, 100baseT_Half); 582 phylink_set(mask, 100baseT_Full); 583 } 584 } 585 586 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 587 unsigned long *mask, 588 struct phylink_link_state *state) 589 { 590 /* FIXME: if the port is in 1000Base-X mode, then it only supports 591 * 1000M FD speeds. In this case, CMODE will indicate 5. 592 */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 if (port >= 5) 604 phylink_set(mask, 2500baseX_Full); 605 606 /* No ethtool bits for 200Mbps */ 607 phylink_set(mask, 1000baseT_Full); 608 phylink_set(mask, 1000baseX_Full); 609 610 mv88e6065_phylink_validate(chip, port, mask, state); 611 } 612 613 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 614 unsigned long *mask, 615 struct phylink_link_state *state) 616 { 617 /* No ethtool bits for 200Mbps */ 618 phylink_set(mask, 1000baseT_Full); 619 phylink_set(mask, 1000baseX_Full); 620 621 mv88e6065_phylink_validate(chip, port, mask, state); 622 } 623 624 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 625 unsigned long *mask, 626 struct phylink_link_state *state) 627 { 628 if (port >= 9) { 629 phylink_set(mask, 2500baseX_Full); 630 phylink_set(mask, 2500baseT_Full); 631 } 632 633 /* No ethtool bits for 200Mbps */ 634 phylink_set(mask, 1000baseT_Full); 635 phylink_set(mask, 1000baseX_Full); 636 637 mv88e6065_phylink_validate(chip, port, mask, state); 638 } 639 640 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 641 unsigned long *mask, 642 struct phylink_link_state *state) 643 { 644 if (port >= 9) { 645 phylink_set(mask, 10000baseT_Full); 646 phylink_set(mask, 10000baseKR_Full); 647 } 648 649 mv88e6390_phylink_validate(chip, port, mask, state); 650 } 651 652 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 653 unsigned long *mask, 654 struct phylink_link_state *state) 655 { 656 bool is_6191x = 657 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 658 659 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 660 phylink_set(mask, 10000baseT_Full); 661 phylink_set(mask, 10000baseKR_Full); 662 phylink_set(mask, 10000baseCR_Full); 663 phylink_set(mask, 10000baseSR_Full); 664 phylink_set(mask, 10000baseLR_Full); 665 phylink_set(mask, 10000baseLRM_Full); 666 phylink_set(mask, 10000baseER_Full); 667 phylink_set(mask, 5000baseT_Full); 668 phylink_set(mask, 2500baseX_Full); 669 phylink_set(mask, 2500baseT_Full); 670 } 671 672 phylink_set(mask, 1000baseT_Full); 673 phylink_set(mask, 1000baseX_Full); 674 675 mv88e6065_phylink_validate(chip, port, mask, state); 676 } 677 678 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 679 unsigned long *supported, 680 struct phylink_link_state *state) 681 { 682 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 683 struct mv88e6xxx_chip *chip = ds->priv; 684 685 /* Allow all the expected bits */ 686 phylink_set(mask, Autoneg); 687 phylink_set(mask, Pause); 688 phylink_set_port_modes(mask); 689 690 if (chip->info->ops->phylink_validate) 691 chip->info->ops->phylink_validate(chip, port, mask, state); 692 693 linkmode_and(supported, supported, mask); 694 linkmode_and(state->advertising, state->advertising, mask); 695 696 /* We can only operate at 2500BaseX or 1000BaseX. If requested 697 * to advertise both, only report advertising at 2500BaseX. 698 */ 699 phylink_helper_basex_speed(state); 700 } 701 702 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 703 unsigned int mode, 704 const struct phylink_link_state *state) 705 { 706 struct mv88e6xxx_chip *chip = ds->priv; 707 struct mv88e6xxx_port *p; 708 int err = 0; 709 710 p = &chip->ports[port]; 711 712 mv88e6xxx_reg_lock(chip); 713 714 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 715 /* In inband mode, the link may come up at any time while the 716 * link is not forced down. Force the link down while we 717 * reconfigure the interface mode. 718 */ 719 if (mode == MLO_AN_INBAND && 720 p->interface != state->interface && 721 chip->info->ops->port_set_link) 722 chip->info->ops->port_set_link(chip, port, 723 LINK_FORCED_DOWN); 724 725 err = mv88e6xxx_port_config_interface(chip, port, 726 state->interface); 727 if (err && err != -EOPNOTSUPP) 728 goto err_unlock; 729 730 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 731 state->interface, 732 state->advertising); 733 /* FIXME: we should restart negotiation if something changed - 734 * which is something we get if we convert to using phylinks 735 * PCS operations. 736 */ 737 if (err > 0) 738 err = 0; 739 } 740 741 /* Undo the forced down state above after completing configuration 742 * irrespective of its state on entry, which allows the link to come 743 * up in the in-band case where there is no separate SERDES. Also 744 * ensure that the link can come up if the PPU is in use and we are 745 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 746 */ 747 if (chip->info->ops->port_set_link && 748 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 749 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 750 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 751 752 p->interface = state->interface; 753 754 err_unlock: 755 mv88e6xxx_reg_unlock(chip); 756 757 if (err && err != -EOPNOTSUPP) 758 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 759 } 760 761 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 762 unsigned int mode, 763 phy_interface_t interface) 764 { 765 struct mv88e6xxx_chip *chip = ds->priv; 766 const struct mv88e6xxx_ops *ops; 767 int err = 0; 768 769 ops = chip->info->ops; 770 771 mv88e6xxx_reg_lock(chip); 772 /* Force the link down if we know the port may not be automatically 773 * updated by the switch or if we are using fixed-link mode. 774 */ 775 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 776 mode == MLO_AN_FIXED) && ops->port_sync_link) 777 err = ops->port_sync_link(chip, port, mode, false); 778 779 if (!err && ops->port_set_speed_duplex) 780 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 781 DUPLEX_UNFORCED); 782 mv88e6xxx_reg_unlock(chip); 783 784 if (err) 785 dev_err(chip->dev, 786 "p%d: failed to force MAC link down\n", port); 787 } 788 789 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 790 unsigned int mode, phy_interface_t interface, 791 struct phy_device *phydev, 792 int speed, int duplex, 793 bool tx_pause, bool rx_pause) 794 { 795 struct mv88e6xxx_chip *chip = ds->priv; 796 const struct mv88e6xxx_ops *ops; 797 int err = 0; 798 799 ops = chip->info->ops; 800 801 mv88e6xxx_reg_lock(chip); 802 /* Configure and force the link up if we know that the port may not 803 * automatically updated by the switch or if we are using fixed-link 804 * mode. 805 */ 806 if (!mv88e6xxx_port_ppu_updates(chip, port) || 807 mode == MLO_AN_FIXED) { 808 /* FIXME: for an automedia port, should we force the link 809 * down here - what if the link comes up due to "other" media 810 * while we're bringing the port up, how is the exclusivity 811 * handled in the Marvell hardware? E.g. port 2 on 88E6390 812 * shared between internal PHY and Serdes. 813 */ 814 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 815 duplex); 816 if (err) 817 goto error; 818 819 if (ops->port_set_speed_duplex) { 820 err = ops->port_set_speed_duplex(chip, port, 821 speed, duplex); 822 if (err && err != -EOPNOTSUPP) 823 goto error; 824 } 825 826 if (ops->port_sync_link) 827 err = ops->port_sync_link(chip, port, mode, true); 828 } 829 error: 830 mv88e6xxx_reg_unlock(chip); 831 832 if (err && err != -EOPNOTSUPP) 833 dev_err(ds->dev, 834 "p%d: failed to configure MAC link up\n", port); 835 } 836 837 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 838 { 839 if (!chip->info->ops->stats_snapshot) 840 return -EOPNOTSUPP; 841 842 return chip->info->ops->stats_snapshot(chip, port); 843 } 844 845 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 846 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 847 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 848 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 849 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 850 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 851 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 852 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 853 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 854 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 855 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 856 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 857 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 858 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 859 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 860 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 861 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 862 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 863 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 864 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 865 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 866 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 867 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 868 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 869 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 870 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 871 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 872 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 873 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 874 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 875 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 876 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 877 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 878 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 879 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 880 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 881 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 882 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 883 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 884 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 885 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 886 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 887 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 888 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 889 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 890 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 891 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 892 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 893 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 894 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 895 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 896 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 897 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 898 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 899 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 900 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 901 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 902 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 903 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 904 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 905 }; 906 907 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 908 struct mv88e6xxx_hw_stat *s, 909 int port, u16 bank1_select, 910 u16 histogram) 911 { 912 u32 low; 913 u32 high = 0; 914 u16 reg = 0; 915 int err; 916 u64 value; 917 918 switch (s->type) { 919 case STATS_TYPE_PORT: 920 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 921 if (err) 922 return U64_MAX; 923 924 low = reg; 925 if (s->size == 4) { 926 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 927 if (err) 928 return U64_MAX; 929 low |= ((u32)reg) << 16; 930 } 931 break; 932 case STATS_TYPE_BANK1: 933 reg = bank1_select; 934 fallthrough; 935 case STATS_TYPE_BANK0: 936 reg |= s->reg | histogram; 937 mv88e6xxx_g1_stats_read(chip, reg, &low); 938 if (s->size == 8) 939 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 940 break; 941 default: 942 return U64_MAX; 943 } 944 value = (((u64)high) << 32) | low; 945 return value; 946 } 947 948 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 949 uint8_t *data, int types) 950 { 951 struct mv88e6xxx_hw_stat *stat; 952 int i, j; 953 954 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 955 stat = &mv88e6xxx_hw_stats[i]; 956 if (stat->type & types) { 957 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 958 ETH_GSTRING_LEN); 959 j++; 960 } 961 } 962 963 return j; 964 } 965 966 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 967 uint8_t *data) 968 { 969 return mv88e6xxx_stats_get_strings(chip, data, 970 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 971 } 972 973 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 974 uint8_t *data) 975 { 976 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 977 } 978 979 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 980 uint8_t *data) 981 { 982 return mv88e6xxx_stats_get_strings(chip, data, 983 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 984 } 985 986 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 987 "atu_member_violation", 988 "atu_miss_violation", 989 "atu_full_violation", 990 "vtu_member_violation", 991 "vtu_miss_violation", 992 }; 993 994 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 995 { 996 unsigned int i; 997 998 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 999 strlcpy(data + i * ETH_GSTRING_LEN, 1000 mv88e6xxx_atu_vtu_stats_strings[i], 1001 ETH_GSTRING_LEN); 1002 } 1003 1004 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1005 u32 stringset, uint8_t *data) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int count = 0; 1009 1010 if (stringset != ETH_SS_STATS) 1011 return; 1012 1013 mv88e6xxx_reg_lock(chip); 1014 1015 if (chip->info->ops->stats_get_strings) 1016 count = chip->info->ops->stats_get_strings(chip, data); 1017 1018 if (chip->info->ops->serdes_get_strings) { 1019 data += count * ETH_GSTRING_LEN; 1020 count = chip->info->ops->serdes_get_strings(chip, port, data); 1021 } 1022 1023 data += count * ETH_GSTRING_LEN; 1024 mv88e6xxx_atu_vtu_get_strings(data); 1025 1026 mv88e6xxx_reg_unlock(chip); 1027 } 1028 1029 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1030 int types) 1031 { 1032 struct mv88e6xxx_hw_stat *stat; 1033 int i, j; 1034 1035 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1036 stat = &mv88e6xxx_hw_stats[i]; 1037 if (stat->type & types) 1038 j++; 1039 } 1040 return j; 1041 } 1042 1043 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1044 { 1045 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1046 STATS_TYPE_PORT); 1047 } 1048 1049 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1050 { 1051 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1052 } 1053 1054 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1055 { 1056 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1057 STATS_TYPE_BANK1); 1058 } 1059 1060 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1061 { 1062 struct mv88e6xxx_chip *chip = ds->priv; 1063 int serdes_count = 0; 1064 int count = 0; 1065 1066 if (sset != ETH_SS_STATS) 1067 return 0; 1068 1069 mv88e6xxx_reg_lock(chip); 1070 if (chip->info->ops->stats_get_sset_count) 1071 count = chip->info->ops->stats_get_sset_count(chip); 1072 if (count < 0) 1073 goto out; 1074 1075 if (chip->info->ops->serdes_get_sset_count) 1076 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1077 port); 1078 if (serdes_count < 0) { 1079 count = serdes_count; 1080 goto out; 1081 } 1082 count += serdes_count; 1083 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1084 1085 out: 1086 mv88e6xxx_reg_unlock(chip); 1087 1088 return count; 1089 } 1090 1091 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data, int types, 1093 u16 bank1_select, u16 histogram) 1094 { 1095 struct mv88e6xxx_hw_stat *stat; 1096 int i, j; 1097 1098 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1099 stat = &mv88e6xxx_hw_stats[i]; 1100 if (stat->type & types) { 1101 mv88e6xxx_reg_lock(chip); 1102 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1103 bank1_select, 1104 histogram); 1105 mv88e6xxx_reg_unlock(chip); 1106 1107 j++; 1108 } 1109 } 1110 return j; 1111 } 1112 1113 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1114 uint64_t *data) 1115 { 1116 return mv88e6xxx_stats_get_stats(chip, port, data, 1117 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1118 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1119 } 1120 1121 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1122 uint64_t *data) 1123 { 1124 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1125 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1126 } 1127 1128 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1129 uint64_t *data) 1130 { 1131 return mv88e6xxx_stats_get_stats(chip, port, data, 1132 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1133 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1134 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1135 } 1136 1137 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1138 uint64_t *data) 1139 { 1140 return mv88e6xxx_stats_get_stats(chip, port, data, 1141 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1142 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1143 0); 1144 } 1145 1146 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1147 uint64_t *data) 1148 { 1149 *data++ = chip->ports[port].atu_member_violation; 1150 *data++ = chip->ports[port].atu_miss_violation; 1151 *data++ = chip->ports[port].atu_full_violation; 1152 *data++ = chip->ports[port].vtu_member_violation; 1153 *data++ = chip->ports[port].vtu_miss_violation; 1154 } 1155 1156 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1157 uint64_t *data) 1158 { 1159 int count = 0; 1160 1161 if (chip->info->ops->stats_get_stats) 1162 count = chip->info->ops->stats_get_stats(chip, port, data); 1163 1164 mv88e6xxx_reg_lock(chip); 1165 if (chip->info->ops->serdes_get_stats) { 1166 data += count; 1167 count = chip->info->ops->serdes_get_stats(chip, port, data); 1168 } 1169 data += count; 1170 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1171 mv88e6xxx_reg_unlock(chip); 1172 } 1173 1174 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1175 uint64_t *data) 1176 { 1177 struct mv88e6xxx_chip *chip = ds->priv; 1178 int ret; 1179 1180 mv88e6xxx_reg_lock(chip); 1181 1182 ret = mv88e6xxx_stats_snapshot(chip, port); 1183 mv88e6xxx_reg_unlock(chip); 1184 1185 if (ret < 0) 1186 return; 1187 1188 mv88e6xxx_get_stats(chip, port, data); 1189 1190 } 1191 1192 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1193 { 1194 struct mv88e6xxx_chip *chip = ds->priv; 1195 int len; 1196 1197 len = 32 * sizeof(u16); 1198 if (chip->info->ops->serdes_get_regs_len) 1199 len += chip->info->ops->serdes_get_regs_len(chip, port); 1200 1201 return len; 1202 } 1203 1204 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1205 struct ethtool_regs *regs, void *_p) 1206 { 1207 struct mv88e6xxx_chip *chip = ds->priv; 1208 int err; 1209 u16 reg; 1210 u16 *p = _p; 1211 int i; 1212 1213 regs->version = chip->info->prod_num; 1214 1215 memset(p, 0xff, 32 * sizeof(u16)); 1216 1217 mv88e6xxx_reg_lock(chip); 1218 1219 for (i = 0; i < 32; i++) { 1220 1221 err = mv88e6xxx_port_read(chip, port, i, ®); 1222 if (!err) 1223 p[i] = reg; 1224 } 1225 1226 if (chip->info->ops->serdes_get_regs) 1227 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1228 1229 mv88e6xxx_reg_unlock(chip); 1230 } 1231 1232 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1233 struct ethtool_eee *e) 1234 { 1235 /* Nothing to do on the port's MAC */ 1236 return 0; 1237 } 1238 1239 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1240 struct ethtool_eee *e) 1241 { 1242 /* Nothing to do on the port's MAC */ 1243 return 0; 1244 } 1245 1246 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1247 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1248 { 1249 struct dsa_switch *ds = chip->ds; 1250 struct dsa_switch_tree *dst = ds->dst; 1251 struct dsa_port *dp, *other_dp; 1252 bool found = false; 1253 u16 pvlan; 1254 1255 /* dev is a physical switch */ 1256 if (dev <= dst->last_switch) { 1257 list_for_each_entry(dp, &dst->ports, list) { 1258 if (dp->ds->index == dev && dp->index == port) { 1259 /* dp might be a DSA link or a user port, so it 1260 * might or might not have a bridge. 1261 * Use the "found" variable for both cases. 1262 */ 1263 found = true; 1264 break; 1265 } 1266 } 1267 /* dev is a virtual bridge */ 1268 } else { 1269 list_for_each_entry(dp, &dst->ports, list) { 1270 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1271 1272 if (!bridge_num) 1273 continue; 1274 1275 if (bridge_num + dst->last_switch != dev) 1276 continue; 1277 1278 found = true; 1279 break; 1280 } 1281 } 1282 1283 /* Prevent frames from unknown switch or virtual bridge */ 1284 if (!found) 1285 return 0; 1286 1287 /* Frames from DSA links and CPU ports can egress any local port */ 1288 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1289 return mv88e6xxx_port_mask(chip); 1290 1291 pvlan = 0; 1292 1293 /* Frames from user ports can egress any local DSA links and CPU ports, 1294 * as well as any local member of their bridge group. 1295 */ 1296 dsa_switch_for_each_port(other_dp, ds) 1297 if (other_dp->type == DSA_PORT_TYPE_CPU || 1298 other_dp->type == DSA_PORT_TYPE_DSA || 1299 dsa_port_bridge_same(dp, other_dp)) 1300 pvlan |= BIT(other_dp->index); 1301 1302 return pvlan; 1303 } 1304 1305 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1306 { 1307 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1308 1309 /* prevent frames from going back out of the port they came in on */ 1310 output_ports &= ~BIT(port); 1311 1312 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1313 } 1314 1315 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1316 u8 state) 1317 { 1318 struct mv88e6xxx_chip *chip = ds->priv; 1319 int err; 1320 1321 mv88e6xxx_reg_lock(chip); 1322 err = mv88e6xxx_port_set_state(chip, port, state); 1323 mv88e6xxx_reg_unlock(chip); 1324 1325 if (err) 1326 dev_err(ds->dev, "p%d: failed to update state\n", port); 1327 } 1328 1329 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1330 { 1331 int err; 1332 1333 if (chip->info->ops->ieee_pri_map) { 1334 err = chip->info->ops->ieee_pri_map(chip); 1335 if (err) 1336 return err; 1337 } 1338 1339 if (chip->info->ops->ip_pri_map) { 1340 err = chip->info->ops->ip_pri_map(chip); 1341 if (err) 1342 return err; 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1349 { 1350 struct dsa_switch *ds = chip->ds; 1351 int target, port; 1352 int err; 1353 1354 if (!chip->info->global2_addr) 1355 return 0; 1356 1357 /* Initialize the routing port to the 32 possible target devices */ 1358 for (target = 0; target < 32; target++) { 1359 port = dsa_routing_port(ds, target); 1360 if (port == ds->num_ports) 1361 port = 0x1f; 1362 1363 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1364 if (err) 1365 return err; 1366 } 1367 1368 if (chip->info->ops->set_cascade_port) { 1369 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1370 err = chip->info->ops->set_cascade_port(chip, port); 1371 if (err) 1372 return err; 1373 } 1374 1375 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1376 if (err) 1377 return err; 1378 1379 return 0; 1380 } 1381 1382 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1383 { 1384 /* Clear all trunk masks and mapping */ 1385 if (chip->info->global2_addr) 1386 return mv88e6xxx_g2_trunk_clear(chip); 1387 1388 return 0; 1389 } 1390 1391 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1392 { 1393 if (chip->info->ops->rmu_disable) 1394 return chip->info->ops->rmu_disable(chip); 1395 1396 return 0; 1397 } 1398 1399 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1400 { 1401 if (chip->info->ops->pot_clear) 1402 return chip->info->ops->pot_clear(chip); 1403 1404 return 0; 1405 } 1406 1407 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1408 { 1409 if (chip->info->ops->mgmt_rsvd2cpu) 1410 return chip->info->ops->mgmt_rsvd2cpu(chip); 1411 1412 return 0; 1413 } 1414 1415 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1416 { 1417 int err; 1418 1419 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1420 if (err) 1421 return err; 1422 1423 /* The chips that have a "learn2all" bit in Global1, ATU 1424 * Control are precisely those whose port registers have a 1425 * Message Port bit in Port Control 1 and hence implement 1426 * ->port_setup_message_port. 1427 */ 1428 if (chip->info->ops->port_setup_message_port) { 1429 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1430 if (err) 1431 return err; 1432 } 1433 1434 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1435 } 1436 1437 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1438 { 1439 int port; 1440 int err; 1441 1442 if (!chip->info->ops->irl_init_all) 1443 return 0; 1444 1445 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1446 /* Disable ingress rate limiting by resetting all per port 1447 * ingress rate limit resources to their initial state. 1448 */ 1449 err = chip->info->ops->irl_init_all(chip, port); 1450 if (err) 1451 return err; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1458 { 1459 if (chip->info->ops->set_switch_mac) { 1460 u8 addr[ETH_ALEN]; 1461 1462 eth_random_addr(addr); 1463 1464 return chip->info->ops->set_switch_mac(chip, addr); 1465 } 1466 1467 return 0; 1468 } 1469 1470 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1471 { 1472 struct dsa_switch_tree *dst = chip->ds->dst; 1473 struct dsa_switch *ds; 1474 struct dsa_port *dp; 1475 u16 pvlan = 0; 1476 1477 if (!mv88e6xxx_has_pvt(chip)) 1478 return 0; 1479 1480 /* Skip the local source device, which uses in-chip port VLAN */ 1481 if (dev != chip->ds->index) { 1482 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1483 1484 ds = dsa_switch_find(dst->index, dev); 1485 dp = ds ? dsa_to_port(ds, port) : NULL; 1486 if (dp && dp->lag_dev) { 1487 /* As the PVT is used to limit flooding of 1488 * FORWARD frames, which use the LAG ID as the 1489 * source port, we must translate dev/port to 1490 * the special "LAG device" in the PVT, using 1491 * the LAG ID as the port number. 1492 */ 1493 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1494 port = dsa_lag_id(dst, dp->lag_dev); 1495 } 1496 } 1497 1498 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1499 } 1500 1501 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1502 { 1503 int dev, port; 1504 int err; 1505 1506 if (!mv88e6xxx_has_pvt(chip)) 1507 return 0; 1508 1509 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1510 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1511 */ 1512 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1513 if (err) 1514 return err; 1515 1516 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1517 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1518 err = mv88e6xxx_pvt_map(chip, dev, port); 1519 if (err) 1520 return err; 1521 } 1522 } 1523 1524 return 0; 1525 } 1526 1527 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1528 { 1529 struct mv88e6xxx_chip *chip = ds->priv; 1530 int err; 1531 1532 if (dsa_to_port(ds, port)->lag_dev) 1533 /* Hardware is incapable of fast-aging a LAG through a 1534 * regular ATU move operation. Until we have something 1535 * more fancy in place this is a no-op. 1536 */ 1537 return; 1538 1539 mv88e6xxx_reg_lock(chip); 1540 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1541 mv88e6xxx_reg_unlock(chip); 1542 1543 if (err) 1544 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1545 } 1546 1547 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1548 { 1549 if (!mv88e6xxx_max_vid(chip)) 1550 return 0; 1551 1552 return mv88e6xxx_g1_vtu_flush(chip); 1553 } 1554 1555 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1556 struct mv88e6xxx_vtu_entry *entry) 1557 { 1558 int err; 1559 1560 if (!chip->info->ops->vtu_getnext) 1561 return -EOPNOTSUPP; 1562 1563 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1564 entry->valid = false; 1565 1566 err = chip->info->ops->vtu_getnext(chip, entry); 1567 1568 if (entry->vid != vid) 1569 entry->valid = false; 1570 1571 return err; 1572 } 1573 1574 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1575 int (*cb)(struct mv88e6xxx_chip *chip, 1576 const struct mv88e6xxx_vtu_entry *entry, 1577 void *priv), 1578 void *priv) 1579 { 1580 struct mv88e6xxx_vtu_entry entry = { 1581 .vid = mv88e6xxx_max_vid(chip), 1582 .valid = false, 1583 }; 1584 int err; 1585 1586 if (!chip->info->ops->vtu_getnext) 1587 return -EOPNOTSUPP; 1588 1589 do { 1590 err = chip->info->ops->vtu_getnext(chip, &entry); 1591 if (err) 1592 return err; 1593 1594 if (!entry.valid) 1595 break; 1596 1597 err = cb(chip, &entry, priv); 1598 if (err) 1599 return err; 1600 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1601 1602 return 0; 1603 } 1604 1605 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1606 struct mv88e6xxx_vtu_entry *entry) 1607 { 1608 if (!chip->info->ops->vtu_loadpurge) 1609 return -EOPNOTSUPP; 1610 1611 return chip->info->ops->vtu_loadpurge(chip, entry); 1612 } 1613 1614 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1615 const struct mv88e6xxx_vtu_entry *entry, 1616 void *_fid_bitmap) 1617 { 1618 unsigned long *fid_bitmap = _fid_bitmap; 1619 1620 set_bit(entry->fid, fid_bitmap); 1621 return 0; 1622 } 1623 1624 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1625 { 1626 int i, err; 1627 u16 fid; 1628 1629 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1630 1631 /* Set every FID bit used by the (un)bridged ports */ 1632 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1633 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1634 if (err) 1635 return err; 1636 1637 set_bit(fid, fid_bitmap); 1638 } 1639 1640 /* Set every FID bit used by the VLAN entries */ 1641 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1642 } 1643 1644 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1645 { 1646 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1647 int err; 1648 1649 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1650 if (err) 1651 return err; 1652 1653 /* The reset value 0x000 is used to indicate that multiple address 1654 * databases are not needed. Return the next positive available. 1655 */ 1656 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1657 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1658 return -ENOSPC; 1659 1660 /* Clear the database */ 1661 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1662 } 1663 1664 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1665 u16 vid) 1666 { 1667 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1668 struct mv88e6xxx_chip *chip = ds->priv; 1669 struct mv88e6xxx_vtu_entry vlan; 1670 int err; 1671 1672 /* DSA and CPU ports have to be members of multiple vlans */ 1673 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1674 return 0; 1675 1676 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1677 if (err) 1678 return err; 1679 1680 if (!vlan.valid) 1681 return 0; 1682 1683 dsa_switch_for_each_user_port(other_dp, ds) { 1684 struct net_device *other_br; 1685 1686 if (vlan.member[other_dp->index] == 1687 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1688 continue; 1689 1690 if (dsa_port_bridge_same(dp, other_dp)) 1691 break; /* same bridge, check next VLAN */ 1692 1693 other_br = dsa_port_bridge_dev_get(other_dp); 1694 if (!other_br) 1695 continue; 1696 1697 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1698 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1699 return -EOPNOTSUPP; 1700 } 1701 1702 return 0; 1703 } 1704 1705 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1706 { 1707 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1708 struct net_device *br = dsa_port_bridge_dev_get(dp); 1709 struct mv88e6xxx_port *p = &chip->ports[port]; 1710 u16 pvid = MV88E6XXX_VID_STANDALONE; 1711 bool drop_untagged = false; 1712 int err; 1713 1714 if (br) { 1715 if (br_vlan_enabled(br)) { 1716 pvid = p->bridge_pvid.vid; 1717 drop_untagged = !p->bridge_pvid.valid; 1718 } else { 1719 pvid = MV88E6XXX_VID_BRIDGED; 1720 } 1721 } 1722 1723 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1724 if (err) 1725 return err; 1726 1727 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1728 } 1729 1730 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1731 bool vlan_filtering, 1732 struct netlink_ext_ack *extack) 1733 { 1734 struct mv88e6xxx_chip *chip = ds->priv; 1735 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1736 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1737 int err; 1738 1739 if (!mv88e6xxx_max_vid(chip)) 1740 return -EOPNOTSUPP; 1741 1742 mv88e6xxx_reg_lock(chip); 1743 1744 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1745 if (err) 1746 goto unlock; 1747 1748 err = mv88e6xxx_port_commit_pvid(chip, port); 1749 if (err) 1750 goto unlock; 1751 1752 unlock: 1753 mv88e6xxx_reg_unlock(chip); 1754 1755 return err; 1756 } 1757 1758 static int 1759 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1760 const struct switchdev_obj_port_vlan *vlan) 1761 { 1762 struct mv88e6xxx_chip *chip = ds->priv; 1763 int err; 1764 1765 if (!mv88e6xxx_max_vid(chip)) 1766 return -EOPNOTSUPP; 1767 1768 /* If the requested port doesn't belong to the same bridge as the VLAN 1769 * members, do not support it (yet) and fallback to software VLAN. 1770 */ 1771 mv88e6xxx_reg_lock(chip); 1772 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1773 mv88e6xxx_reg_unlock(chip); 1774 1775 return err; 1776 } 1777 1778 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1779 const unsigned char *addr, u16 vid, 1780 u8 state) 1781 { 1782 struct mv88e6xxx_atu_entry entry; 1783 struct mv88e6xxx_vtu_entry vlan; 1784 u16 fid; 1785 int err; 1786 1787 /* Ports have two private address databases: one for when the port is 1788 * standalone and one for when the port is under a bridge and the 1789 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1790 * address database to remain 100% empty, so we never load an ATU entry 1791 * into a standalone port's database. Therefore, translate the null 1792 * VLAN ID into the port's database used for VLAN-unaware bridging. 1793 */ 1794 if (vid == 0) { 1795 fid = MV88E6XXX_FID_BRIDGED; 1796 } else { 1797 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1798 if (err) 1799 return err; 1800 1801 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1802 if (!vlan.valid) 1803 return -EOPNOTSUPP; 1804 1805 fid = vlan.fid; 1806 } 1807 1808 entry.state = 0; 1809 ether_addr_copy(entry.mac, addr); 1810 eth_addr_dec(entry.mac); 1811 1812 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1813 if (err) 1814 return err; 1815 1816 /* Initialize a fresh ATU entry if it isn't found */ 1817 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1818 memset(&entry, 0, sizeof(entry)); 1819 ether_addr_copy(entry.mac, addr); 1820 } 1821 1822 /* Purge the ATU entry only if no port is using it anymore */ 1823 if (!state) { 1824 entry.portvec &= ~BIT(port); 1825 if (!entry.portvec) 1826 entry.state = 0; 1827 } else { 1828 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1829 entry.portvec = BIT(port); 1830 else 1831 entry.portvec |= BIT(port); 1832 1833 entry.state = state; 1834 } 1835 1836 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1837 } 1838 1839 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1840 const struct mv88e6xxx_policy *policy) 1841 { 1842 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1843 enum mv88e6xxx_policy_action action = policy->action; 1844 const u8 *addr = policy->addr; 1845 u16 vid = policy->vid; 1846 u8 state; 1847 int err; 1848 int id; 1849 1850 if (!chip->info->ops->port_set_policy) 1851 return -EOPNOTSUPP; 1852 1853 switch (mapping) { 1854 case MV88E6XXX_POLICY_MAPPING_DA: 1855 case MV88E6XXX_POLICY_MAPPING_SA: 1856 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1857 state = 0; /* Dissociate the port and address */ 1858 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1859 is_multicast_ether_addr(addr)) 1860 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1861 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1862 is_unicast_ether_addr(addr)) 1863 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1864 else 1865 return -EOPNOTSUPP; 1866 1867 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1868 state); 1869 if (err) 1870 return err; 1871 break; 1872 default: 1873 return -EOPNOTSUPP; 1874 } 1875 1876 /* Skip the port's policy clearing if the mapping is still in use */ 1877 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1878 idr_for_each_entry(&chip->policies, policy, id) 1879 if (policy->port == port && 1880 policy->mapping == mapping && 1881 policy->action != action) 1882 return 0; 1883 1884 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1885 } 1886 1887 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1888 struct ethtool_rx_flow_spec *fs) 1889 { 1890 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1891 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1892 enum mv88e6xxx_policy_mapping mapping; 1893 enum mv88e6xxx_policy_action action; 1894 struct mv88e6xxx_policy *policy; 1895 u16 vid = 0; 1896 u8 *addr; 1897 int err; 1898 int id; 1899 1900 if (fs->location != RX_CLS_LOC_ANY) 1901 return -EINVAL; 1902 1903 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1904 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1905 else 1906 return -EOPNOTSUPP; 1907 1908 switch (fs->flow_type & ~FLOW_EXT) { 1909 case ETHER_FLOW: 1910 if (!is_zero_ether_addr(mac_mask->h_dest) && 1911 is_zero_ether_addr(mac_mask->h_source)) { 1912 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1913 addr = mac_entry->h_dest; 1914 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1915 !is_zero_ether_addr(mac_mask->h_source)) { 1916 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1917 addr = mac_entry->h_source; 1918 } else { 1919 /* Cannot support DA and SA mapping in the same rule */ 1920 return -EOPNOTSUPP; 1921 } 1922 break; 1923 default: 1924 return -EOPNOTSUPP; 1925 } 1926 1927 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1928 if (fs->m_ext.vlan_tci != htons(0xffff)) 1929 return -EOPNOTSUPP; 1930 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1931 } 1932 1933 idr_for_each_entry(&chip->policies, policy, id) { 1934 if (policy->port == port && policy->mapping == mapping && 1935 policy->action == action && policy->vid == vid && 1936 ether_addr_equal(policy->addr, addr)) 1937 return -EEXIST; 1938 } 1939 1940 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1941 if (!policy) 1942 return -ENOMEM; 1943 1944 fs->location = 0; 1945 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1946 GFP_KERNEL); 1947 if (err) { 1948 devm_kfree(chip->dev, policy); 1949 return err; 1950 } 1951 1952 memcpy(&policy->fs, fs, sizeof(*fs)); 1953 ether_addr_copy(policy->addr, addr); 1954 policy->mapping = mapping; 1955 policy->action = action; 1956 policy->port = port; 1957 policy->vid = vid; 1958 1959 err = mv88e6xxx_policy_apply(chip, port, policy); 1960 if (err) { 1961 idr_remove(&chip->policies, fs->location); 1962 devm_kfree(chip->dev, policy); 1963 return err; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1970 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1971 { 1972 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1973 struct mv88e6xxx_chip *chip = ds->priv; 1974 struct mv88e6xxx_policy *policy; 1975 int err; 1976 int id; 1977 1978 mv88e6xxx_reg_lock(chip); 1979 1980 switch (rxnfc->cmd) { 1981 case ETHTOOL_GRXCLSRLCNT: 1982 rxnfc->data = 0; 1983 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1984 rxnfc->rule_cnt = 0; 1985 idr_for_each_entry(&chip->policies, policy, id) 1986 if (policy->port == port) 1987 rxnfc->rule_cnt++; 1988 err = 0; 1989 break; 1990 case ETHTOOL_GRXCLSRULE: 1991 err = -ENOENT; 1992 policy = idr_find(&chip->policies, fs->location); 1993 if (policy) { 1994 memcpy(fs, &policy->fs, sizeof(*fs)); 1995 err = 0; 1996 } 1997 break; 1998 case ETHTOOL_GRXCLSRLALL: 1999 rxnfc->data = 0; 2000 rxnfc->rule_cnt = 0; 2001 idr_for_each_entry(&chip->policies, policy, id) 2002 if (policy->port == port) 2003 rule_locs[rxnfc->rule_cnt++] = id; 2004 err = 0; 2005 break; 2006 default: 2007 err = -EOPNOTSUPP; 2008 break; 2009 } 2010 2011 mv88e6xxx_reg_unlock(chip); 2012 2013 return err; 2014 } 2015 2016 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2017 struct ethtool_rxnfc *rxnfc) 2018 { 2019 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2020 struct mv88e6xxx_chip *chip = ds->priv; 2021 struct mv88e6xxx_policy *policy; 2022 int err; 2023 2024 mv88e6xxx_reg_lock(chip); 2025 2026 switch (rxnfc->cmd) { 2027 case ETHTOOL_SRXCLSRLINS: 2028 err = mv88e6xxx_policy_insert(chip, port, fs); 2029 break; 2030 case ETHTOOL_SRXCLSRLDEL: 2031 err = -ENOENT; 2032 policy = idr_remove(&chip->policies, fs->location); 2033 if (policy) { 2034 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2035 err = mv88e6xxx_policy_apply(chip, port, policy); 2036 devm_kfree(chip->dev, policy); 2037 } 2038 break; 2039 default: 2040 err = -EOPNOTSUPP; 2041 break; 2042 } 2043 2044 mv88e6xxx_reg_unlock(chip); 2045 2046 return err; 2047 } 2048 2049 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2050 u16 vid) 2051 { 2052 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2053 u8 broadcast[ETH_ALEN]; 2054 2055 eth_broadcast_addr(broadcast); 2056 2057 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2058 } 2059 2060 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2061 { 2062 int port; 2063 int err; 2064 2065 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2066 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2067 struct net_device *brport; 2068 2069 if (dsa_is_unused_port(chip->ds, port)) 2070 continue; 2071 2072 brport = dsa_port_to_bridge_port(dp); 2073 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2074 /* Skip bridged user ports where broadcast 2075 * flooding is disabled. 2076 */ 2077 continue; 2078 2079 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2080 if (err) 2081 return err; 2082 } 2083 2084 return 0; 2085 } 2086 2087 struct mv88e6xxx_port_broadcast_sync_ctx { 2088 int port; 2089 bool flood; 2090 }; 2091 2092 static int 2093 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2094 const struct mv88e6xxx_vtu_entry *vlan, 2095 void *_ctx) 2096 { 2097 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2098 u8 broadcast[ETH_ALEN]; 2099 u8 state; 2100 2101 if (ctx->flood) 2102 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2103 else 2104 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2105 2106 eth_broadcast_addr(broadcast); 2107 2108 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2109 vlan->vid, state); 2110 } 2111 2112 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2113 bool flood) 2114 { 2115 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2116 .port = port, 2117 .flood = flood, 2118 }; 2119 struct mv88e6xxx_vtu_entry vid0 = { 2120 .vid = 0, 2121 }; 2122 int err; 2123 2124 /* Update the port's private database... */ 2125 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2126 if (err) 2127 return err; 2128 2129 /* ...and the database for all VLANs. */ 2130 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2131 &ctx); 2132 } 2133 2134 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2135 u16 vid, u8 member, bool warn) 2136 { 2137 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2138 struct mv88e6xxx_vtu_entry vlan; 2139 int i, err; 2140 2141 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2142 if (err) 2143 return err; 2144 2145 if (!vlan.valid) { 2146 memset(&vlan, 0, sizeof(vlan)); 2147 2148 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2149 if (err) 2150 return err; 2151 2152 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2153 if (i == port) 2154 vlan.member[i] = member; 2155 else 2156 vlan.member[i] = non_member; 2157 2158 vlan.vid = vid; 2159 vlan.valid = true; 2160 2161 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2162 if (err) 2163 return err; 2164 2165 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2166 if (err) 2167 return err; 2168 } else if (vlan.member[port] != member) { 2169 vlan.member[port] = member; 2170 2171 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2172 if (err) 2173 return err; 2174 } else if (warn) { 2175 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2176 port, vid); 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2183 const struct switchdev_obj_port_vlan *vlan, 2184 struct netlink_ext_ack *extack) 2185 { 2186 struct mv88e6xxx_chip *chip = ds->priv; 2187 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2188 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2189 struct mv88e6xxx_port *p = &chip->ports[port]; 2190 bool warn; 2191 u8 member; 2192 int err; 2193 2194 if (!vlan->vid) 2195 return 0; 2196 2197 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2198 if (err) 2199 return err; 2200 2201 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2202 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2203 else if (untagged) 2204 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2205 else 2206 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2207 2208 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2209 * and then the CPU port. Do not warn for duplicates for the CPU port. 2210 */ 2211 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2212 2213 mv88e6xxx_reg_lock(chip); 2214 2215 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2216 if (err) { 2217 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2218 vlan->vid, untagged ? 'u' : 't'); 2219 goto out; 2220 } 2221 2222 if (pvid) { 2223 p->bridge_pvid.vid = vlan->vid; 2224 p->bridge_pvid.valid = true; 2225 2226 err = mv88e6xxx_port_commit_pvid(chip, port); 2227 if (err) 2228 goto out; 2229 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2230 /* The old pvid was reinstalled as a non-pvid VLAN */ 2231 p->bridge_pvid.valid = false; 2232 2233 err = mv88e6xxx_port_commit_pvid(chip, port); 2234 if (err) 2235 goto out; 2236 } 2237 2238 out: 2239 mv88e6xxx_reg_unlock(chip); 2240 2241 return err; 2242 } 2243 2244 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2245 int port, u16 vid) 2246 { 2247 struct mv88e6xxx_vtu_entry vlan; 2248 int i, err; 2249 2250 if (!vid) 2251 return 0; 2252 2253 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2254 if (err) 2255 return err; 2256 2257 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2258 * tell switchdev that this VLAN is likely handled in software. 2259 */ 2260 if (!vlan.valid || 2261 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2262 return -EOPNOTSUPP; 2263 2264 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2265 2266 /* keep the VLAN unless all ports are excluded */ 2267 vlan.valid = false; 2268 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2269 if (vlan.member[i] != 2270 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2271 vlan.valid = true; 2272 break; 2273 } 2274 } 2275 2276 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2277 if (err) 2278 return err; 2279 2280 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2281 } 2282 2283 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2284 const struct switchdev_obj_port_vlan *vlan) 2285 { 2286 struct mv88e6xxx_chip *chip = ds->priv; 2287 struct mv88e6xxx_port *p = &chip->ports[port]; 2288 int err = 0; 2289 u16 pvid; 2290 2291 if (!mv88e6xxx_max_vid(chip)) 2292 return -EOPNOTSUPP; 2293 2294 mv88e6xxx_reg_lock(chip); 2295 2296 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2297 if (err) 2298 goto unlock; 2299 2300 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2301 if (err) 2302 goto unlock; 2303 2304 if (vlan->vid == pvid) { 2305 p->bridge_pvid.valid = false; 2306 2307 err = mv88e6xxx_port_commit_pvid(chip, port); 2308 if (err) 2309 goto unlock; 2310 } 2311 2312 unlock: 2313 mv88e6xxx_reg_unlock(chip); 2314 2315 return err; 2316 } 2317 2318 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2319 const unsigned char *addr, u16 vid) 2320 { 2321 struct mv88e6xxx_chip *chip = ds->priv; 2322 int err; 2323 2324 mv88e6xxx_reg_lock(chip); 2325 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2326 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2327 mv88e6xxx_reg_unlock(chip); 2328 2329 return err; 2330 } 2331 2332 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2333 const unsigned char *addr, u16 vid) 2334 { 2335 struct mv88e6xxx_chip *chip = ds->priv; 2336 int err; 2337 2338 mv88e6xxx_reg_lock(chip); 2339 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2340 mv88e6xxx_reg_unlock(chip); 2341 2342 return err; 2343 } 2344 2345 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2346 u16 fid, u16 vid, int port, 2347 dsa_fdb_dump_cb_t *cb, void *data) 2348 { 2349 struct mv88e6xxx_atu_entry addr; 2350 bool is_static; 2351 int err; 2352 2353 addr.state = 0; 2354 eth_broadcast_addr(addr.mac); 2355 2356 do { 2357 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2358 if (err) 2359 return err; 2360 2361 if (!addr.state) 2362 break; 2363 2364 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2365 continue; 2366 2367 if (!is_unicast_ether_addr(addr.mac)) 2368 continue; 2369 2370 is_static = (addr.state == 2371 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2372 err = cb(addr.mac, vid, is_static, data); 2373 if (err) 2374 return err; 2375 } while (!is_broadcast_ether_addr(addr.mac)); 2376 2377 return err; 2378 } 2379 2380 struct mv88e6xxx_port_db_dump_vlan_ctx { 2381 int port; 2382 dsa_fdb_dump_cb_t *cb; 2383 void *data; 2384 }; 2385 2386 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2387 const struct mv88e6xxx_vtu_entry *entry, 2388 void *_data) 2389 { 2390 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2391 2392 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2393 ctx->port, ctx->cb, ctx->data); 2394 } 2395 2396 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2397 dsa_fdb_dump_cb_t *cb, void *data) 2398 { 2399 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2400 .port = port, 2401 .cb = cb, 2402 .data = data, 2403 }; 2404 u16 fid; 2405 int err; 2406 2407 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2408 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2409 if (err) 2410 return err; 2411 2412 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2413 if (err) 2414 return err; 2415 2416 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2417 } 2418 2419 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2420 dsa_fdb_dump_cb_t *cb, void *data) 2421 { 2422 struct mv88e6xxx_chip *chip = ds->priv; 2423 int err; 2424 2425 mv88e6xxx_reg_lock(chip); 2426 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2427 mv88e6xxx_reg_unlock(chip); 2428 2429 return err; 2430 } 2431 2432 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2433 struct dsa_bridge bridge) 2434 { 2435 struct dsa_switch *ds = chip->ds; 2436 struct dsa_switch_tree *dst = ds->dst; 2437 struct dsa_port *dp; 2438 int err; 2439 2440 list_for_each_entry(dp, &dst->ports, list) { 2441 if (dsa_port_offloads_bridge(dp, &bridge)) { 2442 if (dp->ds == ds) { 2443 /* This is a local bridge group member, 2444 * remap its Port VLAN Map. 2445 */ 2446 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2447 if (err) 2448 return err; 2449 } else { 2450 /* This is an external bridge group member, 2451 * remap its cross-chip Port VLAN Table entry. 2452 */ 2453 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2454 dp->index); 2455 if (err) 2456 return err; 2457 } 2458 } 2459 } 2460 2461 return 0; 2462 } 2463 2464 /* Treat the software bridge as a virtual single-port switch behind the 2465 * CPU and map in the PVT. First dst->last_switch elements are taken by 2466 * physical switches, so start from beyond that range. 2467 */ 2468 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2469 unsigned int bridge_num) 2470 { 2471 u8 dev = bridge_num + ds->dst->last_switch; 2472 struct mv88e6xxx_chip *chip = ds->priv; 2473 2474 return mv88e6xxx_pvt_map(chip, dev, 0); 2475 } 2476 2477 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2478 struct dsa_bridge bridge, 2479 bool *tx_fwd_offload) 2480 { 2481 struct mv88e6xxx_chip *chip = ds->priv; 2482 int err; 2483 2484 mv88e6xxx_reg_lock(chip); 2485 2486 err = mv88e6xxx_bridge_map(chip, bridge); 2487 if (err) 2488 goto unlock; 2489 2490 err = mv88e6xxx_port_commit_pvid(chip, port); 2491 if (err) 2492 goto unlock; 2493 2494 if (mv88e6xxx_has_pvt(chip)) { 2495 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2496 if (err) 2497 goto unlock; 2498 2499 *tx_fwd_offload = true; 2500 } 2501 2502 unlock: 2503 mv88e6xxx_reg_unlock(chip); 2504 2505 return err; 2506 } 2507 2508 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2509 struct dsa_bridge bridge) 2510 { 2511 struct mv88e6xxx_chip *chip = ds->priv; 2512 int err; 2513 2514 mv88e6xxx_reg_lock(chip); 2515 2516 if (bridge.tx_fwd_offload && 2517 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2518 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2519 2520 if (mv88e6xxx_bridge_map(chip, bridge) || 2521 mv88e6xxx_port_vlan_map(chip, port)) 2522 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2523 2524 err = mv88e6xxx_port_commit_pvid(chip, port); 2525 if (err) 2526 dev_err(ds->dev, 2527 "port %d failed to restore standalone pvid: %pe\n", 2528 port, ERR_PTR(err)); 2529 2530 mv88e6xxx_reg_unlock(chip); 2531 } 2532 2533 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2534 int tree_index, int sw_index, 2535 int port, struct dsa_bridge bridge) 2536 { 2537 struct mv88e6xxx_chip *chip = ds->priv; 2538 int err; 2539 2540 if (tree_index != ds->dst->index) 2541 return 0; 2542 2543 mv88e6xxx_reg_lock(chip); 2544 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2545 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2546 mv88e6xxx_reg_unlock(chip); 2547 2548 return err; 2549 } 2550 2551 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2552 int tree_index, int sw_index, 2553 int port, struct dsa_bridge bridge) 2554 { 2555 struct mv88e6xxx_chip *chip = ds->priv; 2556 2557 if (tree_index != ds->dst->index) 2558 return; 2559 2560 mv88e6xxx_reg_lock(chip); 2561 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2562 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2563 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2564 mv88e6xxx_reg_unlock(chip); 2565 } 2566 2567 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2568 { 2569 if (chip->info->ops->reset) 2570 return chip->info->ops->reset(chip); 2571 2572 return 0; 2573 } 2574 2575 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2576 { 2577 struct gpio_desc *gpiod = chip->reset; 2578 2579 /* If there is a GPIO connected to the reset pin, toggle it */ 2580 if (gpiod) { 2581 gpiod_set_value_cansleep(gpiod, 1); 2582 usleep_range(10000, 20000); 2583 gpiod_set_value_cansleep(gpiod, 0); 2584 usleep_range(10000, 20000); 2585 2586 mv88e6xxx_g1_wait_eeprom_done(chip); 2587 } 2588 } 2589 2590 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2591 { 2592 int i, err; 2593 2594 /* Set all ports to the Disabled state */ 2595 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2596 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2597 if (err) 2598 return err; 2599 } 2600 2601 /* Wait for transmit queues to drain, 2602 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2603 */ 2604 usleep_range(2000, 4000); 2605 2606 return 0; 2607 } 2608 2609 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2610 { 2611 int err; 2612 2613 err = mv88e6xxx_disable_ports(chip); 2614 if (err) 2615 return err; 2616 2617 mv88e6xxx_hardware_reset(chip); 2618 2619 return mv88e6xxx_software_reset(chip); 2620 } 2621 2622 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2623 enum mv88e6xxx_frame_mode frame, 2624 enum mv88e6xxx_egress_mode egress, u16 etype) 2625 { 2626 int err; 2627 2628 if (!chip->info->ops->port_set_frame_mode) 2629 return -EOPNOTSUPP; 2630 2631 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2632 if (err) 2633 return err; 2634 2635 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2636 if (err) 2637 return err; 2638 2639 if (chip->info->ops->port_set_ether_type) 2640 return chip->info->ops->port_set_ether_type(chip, port, etype); 2641 2642 return 0; 2643 } 2644 2645 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2646 { 2647 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2648 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2649 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2650 } 2651 2652 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2653 { 2654 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2655 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2656 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2657 } 2658 2659 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2660 { 2661 return mv88e6xxx_set_port_mode(chip, port, 2662 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2663 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2664 ETH_P_EDSA); 2665 } 2666 2667 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2668 { 2669 if (dsa_is_dsa_port(chip->ds, port)) 2670 return mv88e6xxx_set_port_mode_dsa(chip, port); 2671 2672 if (dsa_is_user_port(chip->ds, port)) 2673 return mv88e6xxx_set_port_mode_normal(chip, port); 2674 2675 /* Setup CPU port mode depending on its supported tag format */ 2676 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2677 return mv88e6xxx_set_port_mode_dsa(chip, port); 2678 2679 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2680 return mv88e6xxx_set_port_mode_edsa(chip, port); 2681 2682 return -EINVAL; 2683 } 2684 2685 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2686 { 2687 bool message = dsa_is_dsa_port(chip->ds, port); 2688 2689 return mv88e6xxx_port_set_message_port(chip, port, message); 2690 } 2691 2692 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2693 { 2694 int err; 2695 2696 if (chip->info->ops->port_set_ucast_flood) { 2697 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2698 if (err) 2699 return err; 2700 } 2701 if (chip->info->ops->port_set_mcast_flood) { 2702 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2703 if (err) 2704 return err; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2711 { 2712 struct mv88e6xxx_port *mvp = dev_id; 2713 struct mv88e6xxx_chip *chip = mvp->chip; 2714 irqreturn_t ret = IRQ_NONE; 2715 int port = mvp->port; 2716 int lane; 2717 2718 mv88e6xxx_reg_lock(chip); 2719 lane = mv88e6xxx_serdes_get_lane(chip, port); 2720 if (lane >= 0) 2721 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2722 mv88e6xxx_reg_unlock(chip); 2723 2724 return ret; 2725 } 2726 2727 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2728 int lane) 2729 { 2730 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2731 unsigned int irq; 2732 int err; 2733 2734 /* Nothing to request if this SERDES port has no IRQ */ 2735 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2736 if (!irq) 2737 return 0; 2738 2739 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2740 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2741 2742 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2743 mv88e6xxx_reg_unlock(chip); 2744 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2745 IRQF_ONESHOT, dev_id->serdes_irq_name, 2746 dev_id); 2747 mv88e6xxx_reg_lock(chip); 2748 if (err) 2749 return err; 2750 2751 dev_id->serdes_irq = irq; 2752 2753 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2754 } 2755 2756 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2757 int lane) 2758 { 2759 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2760 unsigned int irq = dev_id->serdes_irq; 2761 int err; 2762 2763 /* Nothing to free if no IRQ has been requested */ 2764 if (!irq) 2765 return 0; 2766 2767 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2768 2769 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2770 mv88e6xxx_reg_unlock(chip); 2771 free_irq(irq, dev_id); 2772 mv88e6xxx_reg_lock(chip); 2773 2774 dev_id->serdes_irq = 0; 2775 2776 return err; 2777 } 2778 2779 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2780 bool on) 2781 { 2782 int lane; 2783 int err; 2784 2785 lane = mv88e6xxx_serdes_get_lane(chip, port); 2786 if (lane < 0) 2787 return 0; 2788 2789 if (on) { 2790 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2791 if (err) 2792 return err; 2793 2794 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2795 } else { 2796 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2797 if (err) 2798 return err; 2799 2800 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2801 } 2802 2803 return err; 2804 } 2805 2806 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2807 enum mv88e6xxx_egress_direction direction, 2808 int port) 2809 { 2810 int err; 2811 2812 if (!chip->info->ops->set_egress_port) 2813 return -EOPNOTSUPP; 2814 2815 err = chip->info->ops->set_egress_port(chip, direction, port); 2816 if (err) 2817 return err; 2818 2819 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2820 chip->ingress_dest_port = port; 2821 else 2822 chip->egress_dest_port = port; 2823 2824 return 0; 2825 } 2826 2827 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2828 { 2829 struct dsa_switch *ds = chip->ds; 2830 int upstream_port; 2831 int err; 2832 2833 upstream_port = dsa_upstream_port(ds, port); 2834 if (chip->info->ops->port_set_upstream_port) { 2835 err = chip->info->ops->port_set_upstream_port(chip, port, 2836 upstream_port); 2837 if (err) 2838 return err; 2839 } 2840 2841 if (port == upstream_port) { 2842 if (chip->info->ops->set_cpu_port) { 2843 err = chip->info->ops->set_cpu_port(chip, 2844 upstream_port); 2845 if (err) 2846 return err; 2847 } 2848 2849 err = mv88e6xxx_set_egress_port(chip, 2850 MV88E6XXX_EGRESS_DIR_INGRESS, 2851 upstream_port); 2852 if (err && err != -EOPNOTSUPP) 2853 return err; 2854 2855 err = mv88e6xxx_set_egress_port(chip, 2856 MV88E6XXX_EGRESS_DIR_EGRESS, 2857 upstream_port); 2858 if (err && err != -EOPNOTSUPP) 2859 return err; 2860 } 2861 2862 return 0; 2863 } 2864 2865 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2866 { 2867 struct dsa_switch *ds = chip->ds; 2868 int err; 2869 u16 reg; 2870 2871 chip->ports[port].chip = chip; 2872 chip->ports[port].port = port; 2873 2874 /* MAC Forcing register: don't force link, speed, duplex or flow control 2875 * state to any particular values on physical ports, but force the CPU 2876 * port and all DSA ports to their maximum bandwidth and full duplex. 2877 */ 2878 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2879 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2880 SPEED_MAX, DUPLEX_FULL, 2881 PAUSE_OFF, 2882 PHY_INTERFACE_MODE_NA); 2883 else 2884 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2885 SPEED_UNFORCED, DUPLEX_UNFORCED, 2886 PAUSE_ON, 2887 PHY_INTERFACE_MODE_NA); 2888 if (err) 2889 return err; 2890 2891 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2892 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2893 * tunneling, determine priority by looking at 802.1p and IP 2894 * priority fields (IP prio has precedence), and set STP state 2895 * to Forwarding. 2896 * 2897 * If this is the CPU link, use DSA or EDSA tagging depending 2898 * on which tagging mode was configured. 2899 * 2900 * If this is a link to another switch, use DSA tagging mode. 2901 * 2902 * If this is the upstream port for this switch, enable 2903 * forwarding of unknown unicasts and multicasts. 2904 */ 2905 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2906 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2907 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2908 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2909 if (err) 2910 return err; 2911 2912 err = mv88e6xxx_setup_port_mode(chip, port); 2913 if (err) 2914 return err; 2915 2916 err = mv88e6xxx_setup_egress_floods(chip, port); 2917 if (err) 2918 return err; 2919 2920 /* Port Control 2: don't force a good FCS, set the MTU size to 2921 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2922 * untagged frames on this port, do a destination address lookup on all 2923 * received packets as usual, disable ARP mirroring and don't send a 2924 * copy of all transmitted/received frames on this port to the CPU. 2925 */ 2926 err = mv88e6xxx_port_set_map_da(chip, port); 2927 if (err) 2928 return err; 2929 2930 err = mv88e6xxx_setup_upstream_port(chip, port); 2931 if (err) 2932 return err; 2933 2934 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2935 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2936 if (err) 2937 return err; 2938 2939 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2940 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2941 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2942 * as the private PVID on ports under a VLAN-unaware bridge. 2943 * Shared (DSA and CPU) ports must also be members of it, to translate 2944 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2945 * relying on their port default FID. 2946 */ 2947 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2948 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2949 false); 2950 if (err) 2951 return err; 2952 2953 if (chip->info->ops->port_set_jumbo_size) { 2954 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2955 if (err) 2956 return err; 2957 } 2958 2959 /* Port Association Vector: disable automatic address learning 2960 * on all user ports since they start out in standalone 2961 * mode. When joining a bridge, learning will be configured to 2962 * match the bridge port settings. Enable learning on all 2963 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2964 * learning process. 2965 * 2966 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2967 * and RefreshLocked. I.e. setup standard automatic learning. 2968 */ 2969 if (dsa_is_user_port(ds, port)) 2970 reg = 0; 2971 else 2972 reg = 1 << port; 2973 2974 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2975 reg); 2976 if (err) 2977 return err; 2978 2979 /* Egress rate control 2: disable egress rate control. */ 2980 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2981 0x0000); 2982 if (err) 2983 return err; 2984 2985 if (chip->info->ops->port_pause_limit) { 2986 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2987 if (err) 2988 return err; 2989 } 2990 2991 if (chip->info->ops->port_disable_learn_limit) { 2992 err = chip->info->ops->port_disable_learn_limit(chip, port); 2993 if (err) 2994 return err; 2995 } 2996 2997 if (chip->info->ops->port_disable_pri_override) { 2998 err = chip->info->ops->port_disable_pri_override(chip, port); 2999 if (err) 3000 return err; 3001 } 3002 3003 if (chip->info->ops->port_tag_remap) { 3004 err = chip->info->ops->port_tag_remap(chip, port); 3005 if (err) 3006 return err; 3007 } 3008 3009 if (chip->info->ops->port_egress_rate_limiting) { 3010 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3011 if (err) 3012 return err; 3013 } 3014 3015 if (chip->info->ops->port_setup_message_port) { 3016 err = chip->info->ops->port_setup_message_port(chip, port); 3017 if (err) 3018 return err; 3019 } 3020 3021 /* Port based VLAN map: give each port the same default address 3022 * database, and allow bidirectional communication between the 3023 * CPU and DSA port(s), and the other ports. 3024 */ 3025 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3026 if (err) 3027 return err; 3028 3029 err = mv88e6xxx_port_vlan_map(chip, port); 3030 if (err) 3031 return err; 3032 3033 /* Default VLAN ID and priority: don't set a default VLAN 3034 * ID, and set the default packet priority to zero. 3035 */ 3036 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3037 } 3038 3039 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3040 { 3041 struct mv88e6xxx_chip *chip = ds->priv; 3042 3043 if (chip->info->ops->port_set_jumbo_size) 3044 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3045 else if (chip->info->ops->set_max_frame_size) 3046 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3047 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3048 } 3049 3050 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3051 { 3052 struct mv88e6xxx_chip *chip = ds->priv; 3053 int ret = 0; 3054 3055 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3056 new_mtu += EDSA_HLEN; 3057 3058 mv88e6xxx_reg_lock(chip); 3059 if (chip->info->ops->port_set_jumbo_size) 3060 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3061 else if (chip->info->ops->set_max_frame_size) 3062 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3063 else 3064 if (new_mtu > 1522) 3065 ret = -EINVAL; 3066 mv88e6xxx_reg_unlock(chip); 3067 3068 return ret; 3069 } 3070 3071 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3072 struct phy_device *phydev) 3073 { 3074 struct mv88e6xxx_chip *chip = ds->priv; 3075 int err; 3076 3077 mv88e6xxx_reg_lock(chip); 3078 err = mv88e6xxx_serdes_power(chip, port, true); 3079 mv88e6xxx_reg_unlock(chip); 3080 3081 return err; 3082 } 3083 3084 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3085 { 3086 struct mv88e6xxx_chip *chip = ds->priv; 3087 3088 mv88e6xxx_reg_lock(chip); 3089 if (mv88e6xxx_serdes_power(chip, port, false)) 3090 dev_err(chip->dev, "failed to power off SERDES\n"); 3091 mv88e6xxx_reg_unlock(chip); 3092 } 3093 3094 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3095 unsigned int ageing_time) 3096 { 3097 struct mv88e6xxx_chip *chip = ds->priv; 3098 int err; 3099 3100 mv88e6xxx_reg_lock(chip); 3101 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3102 mv88e6xxx_reg_unlock(chip); 3103 3104 return err; 3105 } 3106 3107 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3108 { 3109 int err; 3110 3111 /* Initialize the statistics unit */ 3112 if (chip->info->ops->stats_set_histogram) { 3113 err = chip->info->ops->stats_set_histogram(chip); 3114 if (err) 3115 return err; 3116 } 3117 3118 return mv88e6xxx_g1_stats_clear(chip); 3119 } 3120 3121 /* Check if the errata has already been applied. */ 3122 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3123 { 3124 int port; 3125 int err; 3126 u16 val; 3127 3128 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3129 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3130 if (err) { 3131 dev_err(chip->dev, 3132 "Error reading hidden register: %d\n", err); 3133 return false; 3134 } 3135 if (val != 0x01c0) 3136 return false; 3137 } 3138 3139 return true; 3140 } 3141 3142 /* The 6390 copper ports have an errata which require poking magic 3143 * values into undocumented hidden registers and then performing a 3144 * software reset. 3145 */ 3146 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3147 { 3148 int port; 3149 int err; 3150 3151 if (mv88e6390_setup_errata_applied(chip)) 3152 return 0; 3153 3154 /* Set the ports into blocking mode */ 3155 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3156 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3157 if (err) 3158 return err; 3159 } 3160 3161 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3162 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3163 if (err) 3164 return err; 3165 } 3166 3167 return mv88e6xxx_software_reset(chip); 3168 } 3169 3170 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3171 { 3172 mv88e6xxx_teardown_devlink_params(ds); 3173 dsa_devlink_resources_unregister(ds); 3174 mv88e6xxx_teardown_devlink_regions_global(ds); 3175 } 3176 3177 static int mv88e6xxx_setup(struct dsa_switch *ds) 3178 { 3179 struct mv88e6xxx_chip *chip = ds->priv; 3180 u8 cmode; 3181 int err; 3182 int i; 3183 3184 chip->ds = ds; 3185 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3186 3187 /* Since virtual bridges are mapped in the PVT, the number we support 3188 * depends on the physical switch topology. We need to let DSA figure 3189 * that out and therefore we cannot set this at dsa_register_switch() 3190 * time. 3191 */ 3192 if (mv88e6xxx_has_pvt(chip)) 3193 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3194 ds->dst->last_switch - 1; 3195 3196 mv88e6xxx_reg_lock(chip); 3197 3198 if (chip->info->ops->setup_errata) { 3199 err = chip->info->ops->setup_errata(chip); 3200 if (err) 3201 goto unlock; 3202 } 3203 3204 /* Cache the cmode of each port. */ 3205 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3206 if (chip->info->ops->port_get_cmode) { 3207 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3208 if (err) 3209 goto unlock; 3210 3211 chip->ports[i].cmode = cmode; 3212 } 3213 } 3214 3215 err = mv88e6xxx_vtu_setup(chip); 3216 if (err) 3217 goto unlock; 3218 3219 /* Setup Switch Port Registers */ 3220 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3221 if (dsa_is_unused_port(ds, i)) 3222 continue; 3223 3224 /* Prevent the use of an invalid port. */ 3225 if (mv88e6xxx_is_invalid_port(chip, i)) { 3226 dev_err(chip->dev, "port %d is invalid\n", i); 3227 err = -EINVAL; 3228 goto unlock; 3229 } 3230 3231 err = mv88e6xxx_setup_port(chip, i); 3232 if (err) 3233 goto unlock; 3234 } 3235 3236 err = mv88e6xxx_irl_setup(chip); 3237 if (err) 3238 goto unlock; 3239 3240 err = mv88e6xxx_mac_setup(chip); 3241 if (err) 3242 goto unlock; 3243 3244 err = mv88e6xxx_phy_setup(chip); 3245 if (err) 3246 goto unlock; 3247 3248 err = mv88e6xxx_pvt_setup(chip); 3249 if (err) 3250 goto unlock; 3251 3252 err = mv88e6xxx_atu_setup(chip); 3253 if (err) 3254 goto unlock; 3255 3256 err = mv88e6xxx_broadcast_setup(chip, 0); 3257 if (err) 3258 goto unlock; 3259 3260 err = mv88e6xxx_pot_setup(chip); 3261 if (err) 3262 goto unlock; 3263 3264 err = mv88e6xxx_rmu_setup(chip); 3265 if (err) 3266 goto unlock; 3267 3268 err = mv88e6xxx_rsvd2cpu_setup(chip); 3269 if (err) 3270 goto unlock; 3271 3272 err = mv88e6xxx_trunk_setup(chip); 3273 if (err) 3274 goto unlock; 3275 3276 err = mv88e6xxx_devmap_setup(chip); 3277 if (err) 3278 goto unlock; 3279 3280 err = mv88e6xxx_pri_setup(chip); 3281 if (err) 3282 goto unlock; 3283 3284 /* Setup PTP Hardware Clock and timestamping */ 3285 if (chip->info->ptp_support) { 3286 err = mv88e6xxx_ptp_setup(chip); 3287 if (err) 3288 goto unlock; 3289 3290 err = mv88e6xxx_hwtstamp_setup(chip); 3291 if (err) 3292 goto unlock; 3293 } 3294 3295 err = mv88e6xxx_stats_setup(chip); 3296 if (err) 3297 goto unlock; 3298 3299 unlock: 3300 mv88e6xxx_reg_unlock(chip); 3301 3302 if (err) 3303 return err; 3304 3305 /* Have to be called without holding the register lock, since 3306 * they take the devlink lock, and we later take the locks in 3307 * the reverse order when getting/setting parameters or 3308 * resource occupancy. 3309 */ 3310 err = mv88e6xxx_setup_devlink_resources(ds); 3311 if (err) 3312 return err; 3313 3314 err = mv88e6xxx_setup_devlink_params(ds); 3315 if (err) 3316 goto out_resources; 3317 3318 err = mv88e6xxx_setup_devlink_regions_global(ds); 3319 if (err) 3320 goto out_params; 3321 3322 return 0; 3323 3324 out_params: 3325 mv88e6xxx_teardown_devlink_params(ds); 3326 out_resources: 3327 dsa_devlink_resources_unregister(ds); 3328 3329 return err; 3330 } 3331 3332 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3333 { 3334 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3335 } 3336 3337 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3338 { 3339 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3340 } 3341 3342 /* prod_id for switch families which do not have a PHY model number */ 3343 static const u16 family_prod_id_table[] = { 3344 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3345 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3346 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3347 }; 3348 3349 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3350 { 3351 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3352 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3353 u16 prod_id; 3354 u16 val; 3355 int err; 3356 3357 if (!chip->info->ops->phy_read) 3358 return -EOPNOTSUPP; 3359 3360 mv88e6xxx_reg_lock(chip); 3361 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3362 mv88e6xxx_reg_unlock(chip); 3363 3364 /* Some internal PHYs don't have a model number. */ 3365 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3366 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3367 prod_id = family_prod_id_table[chip->info->family]; 3368 if (prod_id) 3369 val |= prod_id >> 4; 3370 } 3371 3372 return err ? err : val; 3373 } 3374 3375 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3376 { 3377 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3378 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3379 int err; 3380 3381 if (!chip->info->ops->phy_write) 3382 return -EOPNOTSUPP; 3383 3384 mv88e6xxx_reg_lock(chip); 3385 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3386 mv88e6xxx_reg_unlock(chip); 3387 3388 return err; 3389 } 3390 3391 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3392 struct device_node *np, 3393 bool external) 3394 { 3395 static int index; 3396 struct mv88e6xxx_mdio_bus *mdio_bus; 3397 struct mii_bus *bus; 3398 int err; 3399 3400 if (external) { 3401 mv88e6xxx_reg_lock(chip); 3402 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3403 mv88e6xxx_reg_unlock(chip); 3404 3405 if (err) 3406 return err; 3407 } 3408 3409 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3410 if (!bus) 3411 return -ENOMEM; 3412 3413 mdio_bus = bus->priv; 3414 mdio_bus->bus = bus; 3415 mdio_bus->chip = chip; 3416 INIT_LIST_HEAD(&mdio_bus->list); 3417 mdio_bus->external = external; 3418 3419 if (np) { 3420 bus->name = np->full_name; 3421 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3422 } else { 3423 bus->name = "mv88e6xxx SMI"; 3424 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3425 } 3426 3427 bus->read = mv88e6xxx_mdio_read; 3428 bus->write = mv88e6xxx_mdio_write; 3429 bus->parent = chip->dev; 3430 3431 if (!external) { 3432 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3433 if (err) 3434 return err; 3435 } 3436 3437 err = of_mdiobus_register(bus, np); 3438 if (err) { 3439 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3440 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3441 return err; 3442 } 3443 3444 if (external) 3445 list_add_tail(&mdio_bus->list, &chip->mdios); 3446 else 3447 list_add(&mdio_bus->list, &chip->mdios); 3448 3449 return 0; 3450 } 3451 3452 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3453 3454 { 3455 struct mv88e6xxx_mdio_bus *mdio_bus; 3456 struct mii_bus *bus; 3457 3458 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3459 bus = mdio_bus->bus; 3460 3461 if (!mdio_bus->external) 3462 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3463 3464 mdiobus_unregister(bus); 3465 } 3466 } 3467 3468 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3469 struct device_node *np) 3470 { 3471 struct device_node *child; 3472 int err; 3473 3474 /* Always register one mdio bus for the internal/default mdio 3475 * bus. This maybe represented in the device tree, but is 3476 * optional. 3477 */ 3478 child = of_get_child_by_name(np, "mdio"); 3479 err = mv88e6xxx_mdio_register(chip, child, false); 3480 if (err) 3481 return err; 3482 3483 /* Walk the device tree, and see if there are any other nodes 3484 * which say they are compatible with the external mdio 3485 * bus. 3486 */ 3487 for_each_available_child_of_node(np, child) { 3488 if (of_device_is_compatible( 3489 child, "marvell,mv88e6xxx-mdio-external")) { 3490 err = mv88e6xxx_mdio_register(chip, child, true); 3491 if (err) { 3492 mv88e6xxx_mdios_unregister(chip); 3493 of_node_put(child); 3494 return err; 3495 } 3496 } 3497 } 3498 3499 return 0; 3500 } 3501 3502 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3503 { 3504 struct mv88e6xxx_chip *chip = ds->priv; 3505 3506 return chip->eeprom_len; 3507 } 3508 3509 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3510 struct ethtool_eeprom *eeprom, u8 *data) 3511 { 3512 struct mv88e6xxx_chip *chip = ds->priv; 3513 int err; 3514 3515 if (!chip->info->ops->get_eeprom) 3516 return -EOPNOTSUPP; 3517 3518 mv88e6xxx_reg_lock(chip); 3519 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3520 mv88e6xxx_reg_unlock(chip); 3521 3522 if (err) 3523 return err; 3524 3525 eeprom->magic = 0xc3ec4951; 3526 3527 return 0; 3528 } 3529 3530 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3531 struct ethtool_eeprom *eeprom, u8 *data) 3532 { 3533 struct mv88e6xxx_chip *chip = ds->priv; 3534 int err; 3535 3536 if (!chip->info->ops->set_eeprom) 3537 return -EOPNOTSUPP; 3538 3539 if (eeprom->magic != 0xc3ec4951) 3540 return -EINVAL; 3541 3542 mv88e6xxx_reg_lock(chip); 3543 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3544 mv88e6xxx_reg_unlock(chip); 3545 3546 return err; 3547 } 3548 3549 static const struct mv88e6xxx_ops mv88e6085_ops = { 3550 /* MV88E6XXX_FAMILY_6097 */ 3551 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3552 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3553 .irl_init_all = mv88e6352_g2_irl_init_all, 3554 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3555 .phy_read = mv88e6185_phy_ppu_read, 3556 .phy_write = mv88e6185_phy_ppu_write, 3557 .port_set_link = mv88e6xxx_port_set_link, 3558 .port_sync_link = mv88e6xxx_port_sync_link, 3559 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3560 .port_tag_remap = mv88e6095_port_tag_remap, 3561 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3562 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3563 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3564 .port_set_ether_type = mv88e6351_port_set_ether_type, 3565 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3566 .port_pause_limit = mv88e6097_port_pause_limit, 3567 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3568 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3569 .port_get_cmode = mv88e6185_port_get_cmode, 3570 .port_setup_message_port = mv88e6xxx_setup_message_port, 3571 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3572 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3573 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3574 .stats_get_strings = mv88e6095_stats_get_strings, 3575 .stats_get_stats = mv88e6095_stats_get_stats, 3576 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3577 .set_egress_port = mv88e6095_g1_set_egress_port, 3578 .watchdog_ops = &mv88e6097_watchdog_ops, 3579 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3580 .pot_clear = mv88e6xxx_g2_pot_clear, 3581 .ppu_enable = mv88e6185_g1_ppu_enable, 3582 .ppu_disable = mv88e6185_g1_ppu_disable, 3583 .reset = mv88e6185_g1_reset, 3584 .rmu_disable = mv88e6085_g1_rmu_disable, 3585 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3586 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3587 .phylink_validate = mv88e6185_phylink_validate, 3588 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3589 }; 3590 3591 static const struct mv88e6xxx_ops mv88e6095_ops = { 3592 /* MV88E6XXX_FAMILY_6095 */ 3593 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3594 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3595 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3596 .phy_read = mv88e6185_phy_ppu_read, 3597 .phy_write = mv88e6185_phy_ppu_write, 3598 .port_set_link = mv88e6xxx_port_set_link, 3599 .port_sync_link = mv88e6185_port_sync_link, 3600 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3601 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3602 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3603 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3604 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3605 .port_get_cmode = mv88e6185_port_get_cmode, 3606 .port_setup_message_port = mv88e6xxx_setup_message_port, 3607 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3608 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3609 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3610 .stats_get_strings = mv88e6095_stats_get_strings, 3611 .stats_get_stats = mv88e6095_stats_get_stats, 3612 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3613 .serdes_power = mv88e6185_serdes_power, 3614 .serdes_get_lane = mv88e6185_serdes_get_lane, 3615 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3616 .ppu_enable = mv88e6185_g1_ppu_enable, 3617 .ppu_disable = mv88e6185_g1_ppu_disable, 3618 .reset = mv88e6185_g1_reset, 3619 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3620 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3621 .phylink_validate = mv88e6185_phylink_validate, 3622 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3623 }; 3624 3625 static const struct mv88e6xxx_ops mv88e6097_ops = { 3626 /* MV88E6XXX_FAMILY_6097 */ 3627 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3628 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3629 .irl_init_all = mv88e6352_g2_irl_init_all, 3630 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3631 .phy_read = mv88e6xxx_g2_smi_phy_read, 3632 .phy_write = mv88e6xxx_g2_smi_phy_write, 3633 .port_set_link = mv88e6xxx_port_set_link, 3634 .port_sync_link = mv88e6185_port_sync_link, 3635 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3636 .port_tag_remap = mv88e6095_port_tag_remap, 3637 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3638 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3639 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3640 .port_set_ether_type = mv88e6351_port_set_ether_type, 3641 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3642 .port_pause_limit = mv88e6097_port_pause_limit, 3643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3645 .port_get_cmode = mv88e6185_port_get_cmode, 3646 .port_setup_message_port = mv88e6xxx_setup_message_port, 3647 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3648 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3649 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3650 .stats_get_strings = mv88e6095_stats_get_strings, 3651 .stats_get_stats = mv88e6095_stats_get_stats, 3652 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3653 .set_egress_port = mv88e6095_g1_set_egress_port, 3654 .watchdog_ops = &mv88e6097_watchdog_ops, 3655 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3656 .serdes_power = mv88e6185_serdes_power, 3657 .serdes_get_lane = mv88e6185_serdes_get_lane, 3658 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3659 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3660 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3661 .serdes_irq_status = mv88e6097_serdes_irq_status, 3662 .pot_clear = mv88e6xxx_g2_pot_clear, 3663 .reset = mv88e6352_g1_reset, 3664 .rmu_disable = mv88e6085_g1_rmu_disable, 3665 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3666 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3667 .phylink_validate = mv88e6185_phylink_validate, 3668 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3669 }; 3670 3671 static const struct mv88e6xxx_ops mv88e6123_ops = { 3672 /* MV88E6XXX_FAMILY_6165 */ 3673 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3674 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3675 .irl_init_all = mv88e6352_g2_irl_init_all, 3676 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3677 .phy_read = mv88e6xxx_g2_smi_phy_read, 3678 .phy_write = mv88e6xxx_g2_smi_phy_write, 3679 .port_set_link = mv88e6xxx_port_set_link, 3680 .port_sync_link = mv88e6xxx_port_sync_link, 3681 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3682 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3683 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3684 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3685 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3686 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3687 .port_get_cmode = mv88e6185_port_get_cmode, 3688 .port_setup_message_port = mv88e6xxx_setup_message_port, 3689 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3690 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3691 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3692 .stats_get_strings = mv88e6095_stats_get_strings, 3693 .stats_get_stats = mv88e6095_stats_get_stats, 3694 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3695 .set_egress_port = mv88e6095_g1_set_egress_port, 3696 .watchdog_ops = &mv88e6097_watchdog_ops, 3697 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3698 .pot_clear = mv88e6xxx_g2_pot_clear, 3699 .reset = mv88e6352_g1_reset, 3700 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3701 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3702 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3703 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3704 .phylink_validate = mv88e6185_phylink_validate, 3705 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3706 }; 3707 3708 static const struct mv88e6xxx_ops mv88e6131_ops = { 3709 /* MV88E6XXX_FAMILY_6185 */ 3710 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3711 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3712 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3713 .phy_read = mv88e6185_phy_ppu_read, 3714 .phy_write = mv88e6185_phy_ppu_write, 3715 .port_set_link = mv88e6xxx_port_set_link, 3716 .port_sync_link = mv88e6xxx_port_sync_link, 3717 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3718 .port_tag_remap = mv88e6095_port_tag_remap, 3719 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3720 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3721 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3722 .port_set_ether_type = mv88e6351_port_set_ether_type, 3723 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3724 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3725 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3726 .port_pause_limit = mv88e6097_port_pause_limit, 3727 .port_set_pause = mv88e6185_port_set_pause, 3728 .port_get_cmode = mv88e6185_port_get_cmode, 3729 .port_setup_message_port = mv88e6xxx_setup_message_port, 3730 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3731 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3732 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3733 .stats_get_strings = mv88e6095_stats_get_strings, 3734 .stats_get_stats = mv88e6095_stats_get_stats, 3735 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3736 .set_egress_port = mv88e6095_g1_set_egress_port, 3737 .watchdog_ops = &mv88e6097_watchdog_ops, 3738 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3739 .ppu_enable = mv88e6185_g1_ppu_enable, 3740 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3741 .ppu_disable = mv88e6185_g1_ppu_disable, 3742 .reset = mv88e6185_g1_reset, 3743 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3744 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3745 .phylink_validate = mv88e6185_phylink_validate, 3746 }; 3747 3748 static const struct mv88e6xxx_ops mv88e6141_ops = { 3749 /* MV88E6XXX_FAMILY_6341 */ 3750 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3751 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3752 .irl_init_all = mv88e6352_g2_irl_init_all, 3753 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3754 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3755 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3756 .phy_read = mv88e6xxx_g2_smi_phy_read, 3757 .phy_write = mv88e6xxx_g2_smi_phy_write, 3758 .port_set_link = mv88e6xxx_port_set_link, 3759 .port_sync_link = mv88e6xxx_port_sync_link, 3760 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3761 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3762 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3763 .port_tag_remap = mv88e6095_port_tag_remap, 3764 .port_set_policy = mv88e6352_port_set_policy, 3765 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3766 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3767 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3768 .port_set_ether_type = mv88e6351_port_set_ether_type, 3769 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3770 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3771 .port_pause_limit = mv88e6097_port_pause_limit, 3772 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3773 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3774 .port_get_cmode = mv88e6352_port_get_cmode, 3775 .port_set_cmode = mv88e6341_port_set_cmode, 3776 .port_setup_message_port = mv88e6xxx_setup_message_port, 3777 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3778 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3779 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3780 .stats_get_strings = mv88e6320_stats_get_strings, 3781 .stats_get_stats = mv88e6390_stats_get_stats, 3782 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3783 .set_egress_port = mv88e6390_g1_set_egress_port, 3784 .watchdog_ops = &mv88e6390_watchdog_ops, 3785 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3786 .pot_clear = mv88e6xxx_g2_pot_clear, 3787 .reset = mv88e6352_g1_reset, 3788 .rmu_disable = mv88e6390_g1_rmu_disable, 3789 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3790 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3791 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3792 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3793 .serdes_power = mv88e6390_serdes_power, 3794 .serdes_get_lane = mv88e6341_serdes_get_lane, 3795 /* Check status register pause & lpa register */ 3796 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3797 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3798 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3799 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3800 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3801 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3802 .serdes_irq_status = mv88e6390_serdes_irq_status, 3803 .gpio_ops = &mv88e6352_gpio_ops, 3804 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3805 .serdes_get_strings = mv88e6390_serdes_get_strings, 3806 .serdes_get_stats = mv88e6390_serdes_get_stats, 3807 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3808 .serdes_get_regs = mv88e6390_serdes_get_regs, 3809 .phylink_validate = mv88e6341_phylink_validate, 3810 }; 3811 3812 static const struct mv88e6xxx_ops mv88e6161_ops = { 3813 /* MV88E6XXX_FAMILY_6165 */ 3814 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3815 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3816 .irl_init_all = mv88e6352_g2_irl_init_all, 3817 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3818 .phy_read = mv88e6xxx_g2_smi_phy_read, 3819 .phy_write = mv88e6xxx_g2_smi_phy_write, 3820 .port_set_link = mv88e6xxx_port_set_link, 3821 .port_sync_link = mv88e6xxx_port_sync_link, 3822 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3823 .port_tag_remap = mv88e6095_port_tag_remap, 3824 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3825 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3826 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3827 .port_set_ether_type = mv88e6351_port_set_ether_type, 3828 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3829 .port_pause_limit = mv88e6097_port_pause_limit, 3830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3832 .port_get_cmode = mv88e6185_port_get_cmode, 3833 .port_setup_message_port = mv88e6xxx_setup_message_port, 3834 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3835 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3836 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3837 .stats_get_strings = mv88e6095_stats_get_strings, 3838 .stats_get_stats = mv88e6095_stats_get_stats, 3839 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3840 .set_egress_port = mv88e6095_g1_set_egress_port, 3841 .watchdog_ops = &mv88e6097_watchdog_ops, 3842 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3843 .pot_clear = mv88e6xxx_g2_pot_clear, 3844 .reset = mv88e6352_g1_reset, 3845 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3846 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3847 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3848 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3849 .avb_ops = &mv88e6165_avb_ops, 3850 .ptp_ops = &mv88e6165_ptp_ops, 3851 .phylink_validate = mv88e6185_phylink_validate, 3852 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3853 }; 3854 3855 static const struct mv88e6xxx_ops mv88e6165_ops = { 3856 /* MV88E6XXX_FAMILY_6165 */ 3857 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3858 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3859 .irl_init_all = mv88e6352_g2_irl_init_all, 3860 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3861 .phy_read = mv88e6165_phy_read, 3862 .phy_write = mv88e6165_phy_write, 3863 .port_set_link = mv88e6xxx_port_set_link, 3864 .port_sync_link = mv88e6xxx_port_sync_link, 3865 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3868 .port_get_cmode = mv88e6185_port_get_cmode, 3869 .port_setup_message_port = mv88e6xxx_setup_message_port, 3870 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3871 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3872 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3873 .stats_get_strings = mv88e6095_stats_get_strings, 3874 .stats_get_stats = mv88e6095_stats_get_stats, 3875 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3876 .set_egress_port = mv88e6095_g1_set_egress_port, 3877 .watchdog_ops = &mv88e6097_watchdog_ops, 3878 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3879 .pot_clear = mv88e6xxx_g2_pot_clear, 3880 .reset = mv88e6352_g1_reset, 3881 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3882 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3883 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3884 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3885 .avb_ops = &mv88e6165_avb_ops, 3886 .ptp_ops = &mv88e6165_ptp_ops, 3887 .phylink_validate = mv88e6185_phylink_validate, 3888 }; 3889 3890 static const struct mv88e6xxx_ops mv88e6171_ops = { 3891 /* MV88E6XXX_FAMILY_6351 */ 3892 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3893 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3894 .irl_init_all = mv88e6352_g2_irl_init_all, 3895 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3896 .phy_read = mv88e6xxx_g2_smi_phy_read, 3897 .phy_write = mv88e6xxx_g2_smi_phy_write, 3898 .port_set_link = mv88e6xxx_port_set_link, 3899 .port_sync_link = mv88e6xxx_port_sync_link, 3900 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3901 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3902 .port_tag_remap = mv88e6095_port_tag_remap, 3903 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3904 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3905 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3906 .port_set_ether_type = mv88e6351_port_set_ether_type, 3907 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3908 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3909 .port_pause_limit = mv88e6097_port_pause_limit, 3910 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3911 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3912 .port_get_cmode = mv88e6352_port_get_cmode, 3913 .port_setup_message_port = mv88e6xxx_setup_message_port, 3914 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3915 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3916 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3917 .stats_get_strings = mv88e6095_stats_get_strings, 3918 .stats_get_stats = mv88e6095_stats_get_stats, 3919 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3920 .set_egress_port = mv88e6095_g1_set_egress_port, 3921 .watchdog_ops = &mv88e6097_watchdog_ops, 3922 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3923 .pot_clear = mv88e6xxx_g2_pot_clear, 3924 .reset = mv88e6352_g1_reset, 3925 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3926 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3927 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3928 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3929 .phylink_validate = mv88e6185_phylink_validate, 3930 }; 3931 3932 static const struct mv88e6xxx_ops mv88e6172_ops = { 3933 /* MV88E6XXX_FAMILY_6352 */ 3934 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3935 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3936 .irl_init_all = mv88e6352_g2_irl_init_all, 3937 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3938 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3939 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3940 .phy_read = mv88e6xxx_g2_smi_phy_read, 3941 .phy_write = mv88e6xxx_g2_smi_phy_write, 3942 .port_set_link = mv88e6xxx_port_set_link, 3943 .port_sync_link = mv88e6xxx_port_sync_link, 3944 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3945 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3946 .port_tag_remap = mv88e6095_port_tag_remap, 3947 .port_set_policy = mv88e6352_port_set_policy, 3948 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3949 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3950 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3951 .port_set_ether_type = mv88e6351_port_set_ether_type, 3952 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3953 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3954 .port_pause_limit = mv88e6097_port_pause_limit, 3955 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3956 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3957 .port_get_cmode = mv88e6352_port_get_cmode, 3958 .port_setup_message_port = mv88e6xxx_setup_message_port, 3959 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3960 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3961 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3962 .stats_get_strings = mv88e6095_stats_get_strings, 3963 .stats_get_stats = mv88e6095_stats_get_stats, 3964 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3965 .set_egress_port = mv88e6095_g1_set_egress_port, 3966 .watchdog_ops = &mv88e6097_watchdog_ops, 3967 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3968 .pot_clear = mv88e6xxx_g2_pot_clear, 3969 .reset = mv88e6352_g1_reset, 3970 .rmu_disable = mv88e6352_g1_rmu_disable, 3971 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3972 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3973 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3974 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3975 .serdes_get_lane = mv88e6352_serdes_get_lane, 3976 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3977 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3978 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3979 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3980 .serdes_power = mv88e6352_serdes_power, 3981 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3982 .serdes_get_regs = mv88e6352_serdes_get_regs, 3983 .gpio_ops = &mv88e6352_gpio_ops, 3984 .phylink_validate = mv88e6352_phylink_validate, 3985 }; 3986 3987 static const struct mv88e6xxx_ops mv88e6175_ops = { 3988 /* MV88E6XXX_FAMILY_6351 */ 3989 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3990 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3991 .irl_init_all = mv88e6352_g2_irl_init_all, 3992 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3993 .phy_read = mv88e6xxx_g2_smi_phy_read, 3994 .phy_write = mv88e6xxx_g2_smi_phy_write, 3995 .port_set_link = mv88e6xxx_port_set_link, 3996 .port_sync_link = mv88e6xxx_port_sync_link, 3997 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3998 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3999 .port_tag_remap = mv88e6095_port_tag_remap, 4000 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4001 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4002 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4003 .port_set_ether_type = mv88e6351_port_set_ether_type, 4004 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4005 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4006 .port_pause_limit = mv88e6097_port_pause_limit, 4007 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4008 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4009 .port_get_cmode = mv88e6352_port_get_cmode, 4010 .port_setup_message_port = mv88e6xxx_setup_message_port, 4011 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4012 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4013 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4014 .stats_get_strings = mv88e6095_stats_get_strings, 4015 .stats_get_stats = mv88e6095_stats_get_stats, 4016 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4017 .set_egress_port = mv88e6095_g1_set_egress_port, 4018 .watchdog_ops = &mv88e6097_watchdog_ops, 4019 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4020 .pot_clear = mv88e6xxx_g2_pot_clear, 4021 .reset = mv88e6352_g1_reset, 4022 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4023 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4024 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4025 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4026 .phylink_validate = mv88e6185_phylink_validate, 4027 }; 4028 4029 static const struct mv88e6xxx_ops mv88e6176_ops = { 4030 /* MV88E6XXX_FAMILY_6352 */ 4031 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4032 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4033 .irl_init_all = mv88e6352_g2_irl_init_all, 4034 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4035 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4037 .phy_read = mv88e6xxx_g2_smi_phy_read, 4038 .phy_write = mv88e6xxx_g2_smi_phy_write, 4039 .port_set_link = mv88e6xxx_port_set_link, 4040 .port_sync_link = mv88e6xxx_port_sync_link, 4041 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4042 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4043 .port_tag_remap = mv88e6095_port_tag_remap, 4044 .port_set_policy = mv88e6352_port_set_policy, 4045 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4046 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4047 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4048 .port_set_ether_type = mv88e6351_port_set_ether_type, 4049 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4050 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4051 .port_pause_limit = mv88e6097_port_pause_limit, 4052 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4053 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4054 .port_get_cmode = mv88e6352_port_get_cmode, 4055 .port_setup_message_port = mv88e6xxx_setup_message_port, 4056 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4057 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4058 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4059 .stats_get_strings = mv88e6095_stats_get_strings, 4060 .stats_get_stats = mv88e6095_stats_get_stats, 4061 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4062 .set_egress_port = mv88e6095_g1_set_egress_port, 4063 .watchdog_ops = &mv88e6097_watchdog_ops, 4064 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4065 .pot_clear = mv88e6xxx_g2_pot_clear, 4066 .reset = mv88e6352_g1_reset, 4067 .rmu_disable = mv88e6352_g1_rmu_disable, 4068 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4069 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4070 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4071 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4072 .serdes_get_lane = mv88e6352_serdes_get_lane, 4073 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4074 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4075 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4076 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4077 .serdes_power = mv88e6352_serdes_power, 4078 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4079 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4080 .serdes_irq_status = mv88e6352_serdes_irq_status, 4081 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4082 .serdes_get_regs = mv88e6352_serdes_get_regs, 4083 .gpio_ops = &mv88e6352_gpio_ops, 4084 .phylink_validate = mv88e6352_phylink_validate, 4085 }; 4086 4087 static const struct mv88e6xxx_ops mv88e6185_ops = { 4088 /* MV88E6XXX_FAMILY_6185 */ 4089 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4090 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4091 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4092 .phy_read = mv88e6185_phy_ppu_read, 4093 .phy_write = mv88e6185_phy_ppu_write, 4094 .port_set_link = mv88e6xxx_port_set_link, 4095 .port_sync_link = mv88e6185_port_sync_link, 4096 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4097 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4098 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4099 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4100 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4101 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4102 .port_set_pause = mv88e6185_port_set_pause, 4103 .port_get_cmode = mv88e6185_port_get_cmode, 4104 .port_setup_message_port = mv88e6xxx_setup_message_port, 4105 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4106 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4107 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4108 .stats_get_strings = mv88e6095_stats_get_strings, 4109 .stats_get_stats = mv88e6095_stats_get_stats, 4110 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4111 .set_egress_port = mv88e6095_g1_set_egress_port, 4112 .watchdog_ops = &mv88e6097_watchdog_ops, 4113 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4114 .serdes_power = mv88e6185_serdes_power, 4115 .serdes_get_lane = mv88e6185_serdes_get_lane, 4116 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4117 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4118 .ppu_enable = mv88e6185_g1_ppu_enable, 4119 .ppu_disable = mv88e6185_g1_ppu_disable, 4120 .reset = mv88e6185_g1_reset, 4121 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4122 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4123 .phylink_validate = mv88e6185_phylink_validate, 4124 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4125 }; 4126 4127 static const struct mv88e6xxx_ops mv88e6190_ops = { 4128 /* MV88E6XXX_FAMILY_6390 */ 4129 .setup_errata = mv88e6390_setup_errata, 4130 .irl_init_all = mv88e6390_g2_irl_init_all, 4131 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4132 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4133 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4134 .phy_read = mv88e6xxx_g2_smi_phy_read, 4135 .phy_write = mv88e6xxx_g2_smi_phy_write, 4136 .port_set_link = mv88e6xxx_port_set_link, 4137 .port_sync_link = mv88e6xxx_port_sync_link, 4138 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4139 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4140 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4141 .port_tag_remap = mv88e6390_port_tag_remap, 4142 .port_set_policy = mv88e6352_port_set_policy, 4143 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4144 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4145 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4146 .port_set_ether_type = mv88e6351_port_set_ether_type, 4147 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4148 .port_pause_limit = mv88e6390_port_pause_limit, 4149 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4150 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4151 .port_get_cmode = mv88e6352_port_get_cmode, 4152 .port_set_cmode = mv88e6390_port_set_cmode, 4153 .port_setup_message_port = mv88e6xxx_setup_message_port, 4154 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4155 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4156 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4157 .stats_get_strings = mv88e6320_stats_get_strings, 4158 .stats_get_stats = mv88e6390_stats_get_stats, 4159 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4160 .set_egress_port = mv88e6390_g1_set_egress_port, 4161 .watchdog_ops = &mv88e6390_watchdog_ops, 4162 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4163 .pot_clear = mv88e6xxx_g2_pot_clear, 4164 .reset = mv88e6352_g1_reset, 4165 .rmu_disable = mv88e6390_g1_rmu_disable, 4166 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4167 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4168 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4169 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4170 .serdes_power = mv88e6390_serdes_power, 4171 .serdes_get_lane = mv88e6390_serdes_get_lane, 4172 /* Check status register pause & lpa register */ 4173 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4174 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4175 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4176 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4177 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4178 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4179 .serdes_irq_status = mv88e6390_serdes_irq_status, 4180 .serdes_get_strings = mv88e6390_serdes_get_strings, 4181 .serdes_get_stats = mv88e6390_serdes_get_stats, 4182 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4183 .serdes_get_regs = mv88e6390_serdes_get_regs, 4184 .gpio_ops = &mv88e6352_gpio_ops, 4185 .phylink_validate = mv88e6390_phylink_validate, 4186 }; 4187 4188 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4189 /* MV88E6XXX_FAMILY_6390 */ 4190 .setup_errata = mv88e6390_setup_errata, 4191 .irl_init_all = mv88e6390_g2_irl_init_all, 4192 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4193 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4194 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4195 .phy_read = mv88e6xxx_g2_smi_phy_read, 4196 .phy_write = mv88e6xxx_g2_smi_phy_write, 4197 .port_set_link = mv88e6xxx_port_set_link, 4198 .port_sync_link = mv88e6xxx_port_sync_link, 4199 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4200 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4201 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4202 .port_tag_remap = mv88e6390_port_tag_remap, 4203 .port_set_policy = mv88e6352_port_set_policy, 4204 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4205 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4206 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4207 .port_set_ether_type = mv88e6351_port_set_ether_type, 4208 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4209 .port_pause_limit = mv88e6390_port_pause_limit, 4210 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4211 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4212 .port_get_cmode = mv88e6352_port_get_cmode, 4213 .port_set_cmode = mv88e6390x_port_set_cmode, 4214 .port_setup_message_port = mv88e6xxx_setup_message_port, 4215 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4216 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4217 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4218 .stats_get_strings = mv88e6320_stats_get_strings, 4219 .stats_get_stats = mv88e6390_stats_get_stats, 4220 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4221 .set_egress_port = mv88e6390_g1_set_egress_port, 4222 .watchdog_ops = &mv88e6390_watchdog_ops, 4223 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4224 .pot_clear = mv88e6xxx_g2_pot_clear, 4225 .reset = mv88e6352_g1_reset, 4226 .rmu_disable = mv88e6390_g1_rmu_disable, 4227 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4228 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4229 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4230 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4231 .serdes_power = mv88e6390_serdes_power, 4232 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4233 /* Check status register pause & lpa register */ 4234 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4235 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4236 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4237 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4238 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4239 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4240 .serdes_irq_status = mv88e6390_serdes_irq_status, 4241 .serdes_get_strings = mv88e6390_serdes_get_strings, 4242 .serdes_get_stats = mv88e6390_serdes_get_stats, 4243 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4244 .serdes_get_regs = mv88e6390_serdes_get_regs, 4245 .gpio_ops = &mv88e6352_gpio_ops, 4246 .phylink_validate = mv88e6390x_phylink_validate, 4247 }; 4248 4249 static const struct mv88e6xxx_ops mv88e6191_ops = { 4250 /* MV88E6XXX_FAMILY_6390 */ 4251 .setup_errata = mv88e6390_setup_errata, 4252 .irl_init_all = mv88e6390_g2_irl_init_all, 4253 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4254 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4255 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4256 .phy_read = mv88e6xxx_g2_smi_phy_read, 4257 .phy_write = mv88e6xxx_g2_smi_phy_write, 4258 .port_set_link = mv88e6xxx_port_set_link, 4259 .port_sync_link = mv88e6xxx_port_sync_link, 4260 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4261 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4262 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4263 .port_tag_remap = mv88e6390_port_tag_remap, 4264 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4265 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4266 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4267 .port_set_ether_type = mv88e6351_port_set_ether_type, 4268 .port_pause_limit = mv88e6390_port_pause_limit, 4269 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4270 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4271 .port_get_cmode = mv88e6352_port_get_cmode, 4272 .port_set_cmode = mv88e6390_port_set_cmode, 4273 .port_setup_message_port = mv88e6xxx_setup_message_port, 4274 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4275 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4276 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4277 .stats_get_strings = mv88e6320_stats_get_strings, 4278 .stats_get_stats = mv88e6390_stats_get_stats, 4279 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4280 .set_egress_port = mv88e6390_g1_set_egress_port, 4281 .watchdog_ops = &mv88e6390_watchdog_ops, 4282 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4283 .pot_clear = mv88e6xxx_g2_pot_clear, 4284 .reset = mv88e6352_g1_reset, 4285 .rmu_disable = mv88e6390_g1_rmu_disable, 4286 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4287 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4288 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4289 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4290 .serdes_power = mv88e6390_serdes_power, 4291 .serdes_get_lane = mv88e6390_serdes_get_lane, 4292 /* Check status register pause & lpa register */ 4293 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4294 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4295 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4296 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4297 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4298 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4299 .serdes_irq_status = mv88e6390_serdes_irq_status, 4300 .serdes_get_strings = mv88e6390_serdes_get_strings, 4301 .serdes_get_stats = mv88e6390_serdes_get_stats, 4302 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4303 .serdes_get_regs = mv88e6390_serdes_get_regs, 4304 .avb_ops = &mv88e6390_avb_ops, 4305 .ptp_ops = &mv88e6352_ptp_ops, 4306 .phylink_validate = mv88e6390_phylink_validate, 4307 }; 4308 4309 static const struct mv88e6xxx_ops mv88e6240_ops = { 4310 /* MV88E6XXX_FAMILY_6352 */ 4311 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4312 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4313 .irl_init_all = mv88e6352_g2_irl_init_all, 4314 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4315 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4316 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4317 .phy_read = mv88e6xxx_g2_smi_phy_read, 4318 .phy_write = mv88e6xxx_g2_smi_phy_write, 4319 .port_set_link = mv88e6xxx_port_set_link, 4320 .port_sync_link = mv88e6xxx_port_sync_link, 4321 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4322 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4323 .port_tag_remap = mv88e6095_port_tag_remap, 4324 .port_set_policy = mv88e6352_port_set_policy, 4325 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4326 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4327 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4328 .port_set_ether_type = mv88e6351_port_set_ether_type, 4329 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4330 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4331 .port_pause_limit = mv88e6097_port_pause_limit, 4332 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4333 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4334 .port_get_cmode = mv88e6352_port_get_cmode, 4335 .port_setup_message_port = mv88e6xxx_setup_message_port, 4336 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4337 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4338 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4339 .stats_get_strings = mv88e6095_stats_get_strings, 4340 .stats_get_stats = mv88e6095_stats_get_stats, 4341 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4342 .set_egress_port = mv88e6095_g1_set_egress_port, 4343 .watchdog_ops = &mv88e6097_watchdog_ops, 4344 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4345 .pot_clear = mv88e6xxx_g2_pot_clear, 4346 .reset = mv88e6352_g1_reset, 4347 .rmu_disable = mv88e6352_g1_rmu_disable, 4348 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4349 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4350 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4351 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4352 .serdes_get_lane = mv88e6352_serdes_get_lane, 4353 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4354 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4355 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4356 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4357 .serdes_power = mv88e6352_serdes_power, 4358 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4359 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4360 .serdes_irq_status = mv88e6352_serdes_irq_status, 4361 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4362 .serdes_get_regs = mv88e6352_serdes_get_regs, 4363 .gpio_ops = &mv88e6352_gpio_ops, 4364 .avb_ops = &mv88e6352_avb_ops, 4365 .ptp_ops = &mv88e6352_ptp_ops, 4366 .phylink_validate = mv88e6352_phylink_validate, 4367 }; 4368 4369 static const struct mv88e6xxx_ops mv88e6250_ops = { 4370 /* MV88E6XXX_FAMILY_6250 */ 4371 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4372 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4373 .irl_init_all = mv88e6352_g2_irl_init_all, 4374 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4375 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4376 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4377 .phy_read = mv88e6xxx_g2_smi_phy_read, 4378 .phy_write = mv88e6xxx_g2_smi_phy_write, 4379 .port_set_link = mv88e6xxx_port_set_link, 4380 .port_sync_link = mv88e6xxx_port_sync_link, 4381 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4382 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4383 .port_tag_remap = mv88e6095_port_tag_remap, 4384 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4385 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4386 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4387 .port_set_ether_type = mv88e6351_port_set_ether_type, 4388 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4389 .port_pause_limit = mv88e6097_port_pause_limit, 4390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4391 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4392 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4393 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4394 .stats_get_strings = mv88e6250_stats_get_strings, 4395 .stats_get_stats = mv88e6250_stats_get_stats, 4396 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4397 .set_egress_port = mv88e6095_g1_set_egress_port, 4398 .watchdog_ops = &mv88e6250_watchdog_ops, 4399 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4400 .pot_clear = mv88e6xxx_g2_pot_clear, 4401 .reset = mv88e6250_g1_reset, 4402 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4403 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4404 .avb_ops = &mv88e6352_avb_ops, 4405 .ptp_ops = &mv88e6250_ptp_ops, 4406 .phylink_validate = mv88e6065_phylink_validate, 4407 }; 4408 4409 static const struct mv88e6xxx_ops mv88e6290_ops = { 4410 /* MV88E6XXX_FAMILY_6390 */ 4411 .setup_errata = mv88e6390_setup_errata, 4412 .irl_init_all = mv88e6390_g2_irl_init_all, 4413 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4414 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4415 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4416 .phy_read = mv88e6xxx_g2_smi_phy_read, 4417 .phy_write = mv88e6xxx_g2_smi_phy_write, 4418 .port_set_link = mv88e6xxx_port_set_link, 4419 .port_sync_link = mv88e6xxx_port_sync_link, 4420 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4421 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4422 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4423 .port_tag_remap = mv88e6390_port_tag_remap, 4424 .port_set_policy = mv88e6352_port_set_policy, 4425 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4426 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4427 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4428 .port_set_ether_type = mv88e6351_port_set_ether_type, 4429 .port_pause_limit = mv88e6390_port_pause_limit, 4430 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4431 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4432 .port_get_cmode = mv88e6352_port_get_cmode, 4433 .port_set_cmode = mv88e6390_port_set_cmode, 4434 .port_setup_message_port = mv88e6xxx_setup_message_port, 4435 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4436 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4437 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4438 .stats_get_strings = mv88e6320_stats_get_strings, 4439 .stats_get_stats = mv88e6390_stats_get_stats, 4440 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4441 .set_egress_port = mv88e6390_g1_set_egress_port, 4442 .watchdog_ops = &mv88e6390_watchdog_ops, 4443 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4444 .pot_clear = mv88e6xxx_g2_pot_clear, 4445 .reset = mv88e6352_g1_reset, 4446 .rmu_disable = mv88e6390_g1_rmu_disable, 4447 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4448 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4449 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4450 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4451 .serdes_power = mv88e6390_serdes_power, 4452 .serdes_get_lane = mv88e6390_serdes_get_lane, 4453 /* Check status register pause & lpa register */ 4454 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4455 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4456 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4457 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4458 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4459 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4460 .serdes_irq_status = mv88e6390_serdes_irq_status, 4461 .serdes_get_strings = mv88e6390_serdes_get_strings, 4462 .serdes_get_stats = mv88e6390_serdes_get_stats, 4463 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4464 .serdes_get_regs = mv88e6390_serdes_get_regs, 4465 .gpio_ops = &mv88e6352_gpio_ops, 4466 .avb_ops = &mv88e6390_avb_ops, 4467 .ptp_ops = &mv88e6352_ptp_ops, 4468 .phylink_validate = mv88e6390_phylink_validate, 4469 }; 4470 4471 static const struct mv88e6xxx_ops mv88e6320_ops = { 4472 /* MV88E6XXX_FAMILY_6320 */ 4473 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4474 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4475 .irl_init_all = mv88e6352_g2_irl_init_all, 4476 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4477 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4478 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4479 .phy_read = mv88e6xxx_g2_smi_phy_read, 4480 .phy_write = mv88e6xxx_g2_smi_phy_write, 4481 .port_set_link = mv88e6xxx_port_set_link, 4482 .port_sync_link = mv88e6xxx_port_sync_link, 4483 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4484 .port_tag_remap = mv88e6095_port_tag_remap, 4485 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4486 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4487 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4488 .port_set_ether_type = mv88e6351_port_set_ether_type, 4489 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4491 .port_pause_limit = mv88e6097_port_pause_limit, 4492 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4493 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4494 .port_get_cmode = mv88e6352_port_get_cmode, 4495 .port_setup_message_port = mv88e6xxx_setup_message_port, 4496 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4497 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4498 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4499 .stats_get_strings = mv88e6320_stats_get_strings, 4500 .stats_get_stats = mv88e6320_stats_get_stats, 4501 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4502 .set_egress_port = mv88e6095_g1_set_egress_port, 4503 .watchdog_ops = &mv88e6390_watchdog_ops, 4504 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4505 .pot_clear = mv88e6xxx_g2_pot_clear, 4506 .reset = mv88e6352_g1_reset, 4507 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4509 .gpio_ops = &mv88e6352_gpio_ops, 4510 .avb_ops = &mv88e6352_avb_ops, 4511 .ptp_ops = &mv88e6352_ptp_ops, 4512 .phylink_validate = mv88e6185_phylink_validate, 4513 }; 4514 4515 static const struct mv88e6xxx_ops mv88e6321_ops = { 4516 /* MV88E6XXX_FAMILY_6320 */ 4517 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4518 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4519 .irl_init_all = mv88e6352_g2_irl_init_all, 4520 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4521 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4523 .phy_read = mv88e6xxx_g2_smi_phy_read, 4524 .phy_write = mv88e6xxx_g2_smi_phy_write, 4525 .port_set_link = mv88e6xxx_port_set_link, 4526 .port_sync_link = mv88e6xxx_port_sync_link, 4527 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4528 .port_tag_remap = mv88e6095_port_tag_remap, 4529 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4530 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4531 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4532 .port_set_ether_type = mv88e6351_port_set_ether_type, 4533 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4534 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4535 .port_pause_limit = mv88e6097_port_pause_limit, 4536 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4537 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4538 .port_get_cmode = mv88e6352_port_get_cmode, 4539 .port_setup_message_port = mv88e6xxx_setup_message_port, 4540 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4541 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4542 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4543 .stats_get_strings = mv88e6320_stats_get_strings, 4544 .stats_get_stats = mv88e6320_stats_get_stats, 4545 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4546 .set_egress_port = mv88e6095_g1_set_egress_port, 4547 .watchdog_ops = &mv88e6390_watchdog_ops, 4548 .reset = mv88e6352_g1_reset, 4549 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4550 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4551 .gpio_ops = &mv88e6352_gpio_ops, 4552 .avb_ops = &mv88e6352_avb_ops, 4553 .ptp_ops = &mv88e6352_ptp_ops, 4554 .phylink_validate = mv88e6185_phylink_validate, 4555 }; 4556 4557 static const struct mv88e6xxx_ops mv88e6341_ops = { 4558 /* MV88E6XXX_FAMILY_6341 */ 4559 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4560 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4561 .irl_init_all = mv88e6352_g2_irl_init_all, 4562 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4563 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4564 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4565 .phy_read = mv88e6xxx_g2_smi_phy_read, 4566 .phy_write = mv88e6xxx_g2_smi_phy_write, 4567 .port_set_link = mv88e6xxx_port_set_link, 4568 .port_sync_link = mv88e6xxx_port_sync_link, 4569 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4570 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4571 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4572 .port_tag_remap = mv88e6095_port_tag_remap, 4573 .port_set_policy = mv88e6352_port_set_policy, 4574 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4575 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4576 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4577 .port_set_ether_type = mv88e6351_port_set_ether_type, 4578 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4579 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4580 .port_pause_limit = mv88e6097_port_pause_limit, 4581 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4582 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4583 .port_get_cmode = mv88e6352_port_get_cmode, 4584 .port_set_cmode = mv88e6341_port_set_cmode, 4585 .port_setup_message_port = mv88e6xxx_setup_message_port, 4586 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4587 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4588 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4589 .stats_get_strings = mv88e6320_stats_get_strings, 4590 .stats_get_stats = mv88e6390_stats_get_stats, 4591 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4592 .set_egress_port = mv88e6390_g1_set_egress_port, 4593 .watchdog_ops = &mv88e6390_watchdog_ops, 4594 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4595 .pot_clear = mv88e6xxx_g2_pot_clear, 4596 .reset = mv88e6352_g1_reset, 4597 .rmu_disable = mv88e6390_g1_rmu_disable, 4598 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4599 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4600 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4601 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4602 .serdes_power = mv88e6390_serdes_power, 4603 .serdes_get_lane = mv88e6341_serdes_get_lane, 4604 /* Check status register pause & lpa register */ 4605 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4606 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4607 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4608 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4609 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4610 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4611 .serdes_irq_status = mv88e6390_serdes_irq_status, 4612 .gpio_ops = &mv88e6352_gpio_ops, 4613 .avb_ops = &mv88e6390_avb_ops, 4614 .ptp_ops = &mv88e6352_ptp_ops, 4615 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4616 .serdes_get_strings = mv88e6390_serdes_get_strings, 4617 .serdes_get_stats = mv88e6390_serdes_get_stats, 4618 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4619 .serdes_get_regs = mv88e6390_serdes_get_regs, 4620 .phylink_validate = mv88e6341_phylink_validate, 4621 }; 4622 4623 static const struct mv88e6xxx_ops mv88e6350_ops = { 4624 /* MV88E6XXX_FAMILY_6351 */ 4625 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4626 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4627 .irl_init_all = mv88e6352_g2_irl_init_all, 4628 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4629 .phy_read = mv88e6xxx_g2_smi_phy_read, 4630 .phy_write = mv88e6xxx_g2_smi_phy_write, 4631 .port_set_link = mv88e6xxx_port_set_link, 4632 .port_sync_link = mv88e6xxx_port_sync_link, 4633 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4634 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4635 .port_tag_remap = mv88e6095_port_tag_remap, 4636 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4637 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4638 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4639 .port_set_ether_type = mv88e6351_port_set_ether_type, 4640 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4641 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4642 .port_pause_limit = mv88e6097_port_pause_limit, 4643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4645 .port_get_cmode = mv88e6352_port_get_cmode, 4646 .port_setup_message_port = mv88e6xxx_setup_message_port, 4647 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4648 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4649 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4650 .stats_get_strings = mv88e6095_stats_get_strings, 4651 .stats_get_stats = mv88e6095_stats_get_stats, 4652 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4653 .set_egress_port = mv88e6095_g1_set_egress_port, 4654 .watchdog_ops = &mv88e6097_watchdog_ops, 4655 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4656 .pot_clear = mv88e6xxx_g2_pot_clear, 4657 .reset = mv88e6352_g1_reset, 4658 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4659 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4660 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4661 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4662 .phylink_validate = mv88e6185_phylink_validate, 4663 }; 4664 4665 static const struct mv88e6xxx_ops mv88e6351_ops = { 4666 /* MV88E6XXX_FAMILY_6351 */ 4667 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4668 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4669 .irl_init_all = mv88e6352_g2_irl_init_all, 4670 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4671 .phy_read = mv88e6xxx_g2_smi_phy_read, 4672 .phy_write = mv88e6xxx_g2_smi_phy_write, 4673 .port_set_link = mv88e6xxx_port_set_link, 4674 .port_sync_link = mv88e6xxx_port_sync_link, 4675 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4676 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4677 .port_tag_remap = mv88e6095_port_tag_remap, 4678 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4679 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4680 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4681 .port_set_ether_type = mv88e6351_port_set_ether_type, 4682 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4683 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4684 .port_pause_limit = mv88e6097_port_pause_limit, 4685 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4686 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4687 .port_get_cmode = mv88e6352_port_get_cmode, 4688 .port_setup_message_port = mv88e6xxx_setup_message_port, 4689 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4690 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4691 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4692 .stats_get_strings = mv88e6095_stats_get_strings, 4693 .stats_get_stats = mv88e6095_stats_get_stats, 4694 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4695 .set_egress_port = mv88e6095_g1_set_egress_port, 4696 .watchdog_ops = &mv88e6097_watchdog_ops, 4697 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4698 .pot_clear = mv88e6xxx_g2_pot_clear, 4699 .reset = mv88e6352_g1_reset, 4700 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4701 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4702 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4703 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4704 .avb_ops = &mv88e6352_avb_ops, 4705 .ptp_ops = &mv88e6352_ptp_ops, 4706 .phylink_validate = mv88e6185_phylink_validate, 4707 }; 4708 4709 static const struct mv88e6xxx_ops mv88e6352_ops = { 4710 /* MV88E6XXX_FAMILY_6352 */ 4711 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4712 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4713 .irl_init_all = mv88e6352_g2_irl_init_all, 4714 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4715 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4716 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4717 .phy_read = mv88e6xxx_g2_smi_phy_read, 4718 .phy_write = mv88e6xxx_g2_smi_phy_write, 4719 .port_set_link = mv88e6xxx_port_set_link, 4720 .port_sync_link = mv88e6xxx_port_sync_link, 4721 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4722 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4723 .port_tag_remap = mv88e6095_port_tag_remap, 4724 .port_set_policy = mv88e6352_port_set_policy, 4725 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4726 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4727 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4728 .port_set_ether_type = mv88e6351_port_set_ether_type, 4729 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4730 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4731 .port_pause_limit = mv88e6097_port_pause_limit, 4732 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4733 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4734 .port_get_cmode = mv88e6352_port_get_cmode, 4735 .port_setup_message_port = mv88e6xxx_setup_message_port, 4736 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4737 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4738 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4739 .stats_get_strings = mv88e6095_stats_get_strings, 4740 .stats_get_stats = mv88e6095_stats_get_stats, 4741 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4742 .set_egress_port = mv88e6095_g1_set_egress_port, 4743 .watchdog_ops = &mv88e6097_watchdog_ops, 4744 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4745 .pot_clear = mv88e6xxx_g2_pot_clear, 4746 .reset = mv88e6352_g1_reset, 4747 .rmu_disable = mv88e6352_g1_rmu_disable, 4748 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4749 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4750 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4751 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4752 .serdes_get_lane = mv88e6352_serdes_get_lane, 4753 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4754 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4755 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4756 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4757 .serdes_power = mv88e6352_serdes_power, 4758 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4759 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4760 .serdes_irq_status = mv88e6352_serdes_irq_status, 4761 .gpio_ops = &mv88e6352_gpio_ops, 4762 .avb_ops = &mv88e6352_avb_ops, 4763 .ptp_ops = &mv88e6352_ptp_ops, 4764 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4765 .serdes_get_strings = mv88e6352_serdes_get_strings, 4766 .serdes_get_stats = mv88e6352_serdes_get_stats, 4767 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4768 .serdes_get_regs = mv88e6352_serdes_get_regs, 4769 .phylink_validate = mv88e6352_phylink_validate, 4770 }; 4771 4772 static const struct mv88e6xxx_ops mv88e6390_ops = { 4773 /* MV88E6XXX_FAMILY_6390 */ 4774 .setup_errata = mv88e6390_setup_errata, 4775 .irl_init_all = mv88e6390_g2_irl_init_all, 4776 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4777 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4778 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4779 .phy_read = mv88e6xxx_g2_smi_phy_read, 4780 .phy_write = mv88e6xxx_g2_smi_phy_write, 4781 .port_set_link = mv88e6xxx_port_set_link, 4782 .port_sync_link = mv88e6xxx_port_sync_link, 4783 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4784 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4785 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4786 .port_tag_remap = mv88e6390_port_tag_remap, 4787 .port_set_policy = mv88e6352_port_set_policy, 4788 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4789 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4790 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4791 .port_set_ether_type = mv88e6351_port_set_ether_type, 4792 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4793 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4794 .port_pause_limit = mv88e6390_port_pause_limit, 4795 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4796 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4797 .port_get_cmode = mv88e6352_port_get_cmode, 4798 .port_set_cmode = mv88e6390_port_set_cmode, 4799 .port_setup_message_port = mv88e6xxx_setup_message_port, 4800 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4801 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4802 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4803 .stats_get_strings = mv88e6320_stats_get_strings, 4804 .stats_get_stats = mv88e6390_stats_get_stats, 4805 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4806 .set_egress_port = mv88e6390_g1_set_egress_port, 4807 .watchdog_ops = &mv88e6390_watchdog_ops, 4808 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4809 .pot_clear = mv88e6xxx_g2_pot_clear, 4810 .reset = mv88e6352_g1_reset, 4811 .rmu_disable = mv88e6390_g1_rmu_disable, 4812 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4813 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4814 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4815 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4816 .serdes_power = mv88e6390_serdes_power, 4817 .serdes_get_lane = mv88e6390_serdes_get_lane, 4818 /* Check status register pause & lpa register */ 4819 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4820 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4821 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4822 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4823 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4824 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4825 .serdes_irq_status = mv88e6390_serdes_irq_status, 4826 .gpio_ops = &mv88e6352_gpio_ops, 4827 .avb_ops = &mv88e6390_avb_ops, 4828 .ptp_ops = &mv88e6352_ptp_ops, 4829 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4830 .serdes_get_strings = mv88e6390_serdes_get_strings, 4831 .serdes_get_stats = mv88e6390_serdes_get_stats, 4832 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4833 .serdes_get_regs = mv88e6390_serdes_get_regs, 4834 .phylink_validate = mv88e6390_phylink_validate, 4835 }; 4836 4837 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4838 /* MV88E6XXX_FAMILY_6390 */ 4839 .setup_errata = mv88e6390_setup_errata, 4840 .irl_init_all = mv88e6390_g2_irl_init_all, 4841 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4842 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4843 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4844 .phy_read = mv88e6xxx_g2_smi_phy_read, 4845 .phy_write = mv88e6xxx_g2_smi_phy_write, 4846 .port_set_link = mv88e6xxx_port_set_link, 4847 .port_sync_link = mv88e6xxx_port_sync_link, 4848 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4849 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4850 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4851 .port_tag_remap = mv88e6390_port_tag_remap, 4852 .port_set_policy = mv88e6352_port_set_policy, 4853 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4854 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4855 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4856 .port_set_ether_type = mv88e6351_port_set_ether_type, 4857 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4858 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4859 .port_pause_limit = mv88e6390_port_pause_limit, 4860 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4861 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4862 .port_get_cmode = mv88e6352_port_get_cmode, 4863 .port_set_cmode = mv88e6390x_port_set_cmode, 4864 .port_setup_message_port = mv88e6xxx_setup_message_port, 4865 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4866 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4867 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4868 .stats_get_strings = mv88e6320_stats_get_strings, 4869 .stats_get_stats = mv88e6390_stats_get_stats, 4870 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4871 .set_egress_port = mv88e6390_g1_set_egress_port, 4872 .watchdog_ops = &mv88e6390_watchdog_ops, 4873 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4874 .pot_clear = mv88e6xxx_g2_pot_clear, 4875 .reset = mv88e6352_g1_reset, 4876 .rmu_disable = mv88e6390_g1_rmu_disable, 4877 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4878 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4879 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4880 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4881 .serdes_power = mv88e6390_serdes_power, 4882 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4883 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4884 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4885 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4886 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4887 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4888 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4889 .serdes_irq_status = mv88e6390_serdes_irq_status, 4890 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4891 .serdes_get_strings = mv88e6390_serdes_get_strings, 4892 .serdes_get_stats = mv88e6390_serdes_get_stats, 4893 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4894 .serdes_get_regs = mv88e6390_serdes_get_regs, 4895 .gpio_ops = &mv88e6352_gpio_ops, 4896 .avb_ops = &mv88e6390_avb_ops, 4897 .ptp_ops = &mv88e6352_ptp_ops, 4898 .phylink_validate = mv88e6390x_phylink_validate, 4899 }; 4900 4901 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4902 /* MV88E6XXX_FAMILY_6393 */ 4903 .setup_errata = mv88e6393x_serdes_setup_errata, 4904 .irl_init_all = mv88e6390_g2_irl_init_all, 4905 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4906 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4907 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4908 .phy_read = mv88e6xxx_g2_smi_phy_read, 4909 .phy_write = mv88e6xxx_g2_smi_phy_write, 4910 .port_set_link = mv88e6xxx_port_set_link, 4911 .port_sync_link = mv88e6xxx_port_sync_link, 4912 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4913 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4914 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4915 .port_tag_remap = mv88e6390_port_tag_remap, 4916 .port_set_policy = mv88e6393x_port_set_policy, 4917 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4918 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4919 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4920 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4921 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4922 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4923 .port_pause_limit = mv88e6390_port_pause_limit, 4924 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4925 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4926 .port_get_cmode = mv88e6352_port_get_cmode, 4927 .port_set_cmode = mv88e6393x_port_set_cmode, 4928 .port_setup_message_port = mv88e6xxx_setup_message_port, 4929 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4930 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4931 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4932 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4933 .stats_get_strings = mv88e6320_stats_get_strings, 4934 .stats_get_stats = mv88e6390_stats_get_stats, 4935 /* .set_cpu_port is missing because this family does not support a global 4936 * CPU port, only per port CPU port which is set via 4937 * .port_set_upstream_port method. 4938 */ 4939 .set_egress_port = mv88e6393x_set_egress_port, 4940 .watchdog_ops = &mv88e6390_watchdog_ops, 4941 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4942 .pot_clear = mv88e6xxx_g2_pot_clear, 4943 .reset = mv88e6352_g1_reset, 4944 .rmu_disable = mv88e6390_g1_rmu_disable, 4945 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4946 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4947 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4948 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4949 .serdes_power = mv88e6393x_serdes_power, 4950 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4951 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4952 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4953 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4954 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4955 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4956 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4957 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4958 /* TODO: serdes stats */ 4959 .gpio_ops = &mv88e6352_gpio_ops, 4960 .avb_ops = &mv88e6390_avb_ops, 4961 .ptp_ops = &mv88e6352_ptp_ops, 4962 .phylink_validate = mv88e6393x_phylink_validate, 4963 }; 4964 4965 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4966 [MV88E6085] = { 4967 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4968 .family = MV88E6XXX_FAMILY_6097, 4969 .name = "Marvell 88E6085", 4970 .num_databases = 4096, 4971 .num_macs = 8192, 4972 .num_ports = 10, 4973 .num_internal_phys = 5, 4974 .max_vid = 4095, 4975 .port_base_addr = 0x10, 4976 .phy_base_addr = 0x0, 4977 .global1_addr = 0x1b, 4978 .global2_addr = 0x1c, 4979 .age_time_coeff = 15000, 4980 .g1_irqs = 8, 4981 .g2_irqs = 10, 4982 .atu_move_port_mask = 0xf, 4983 .pvt = true, 4984 .multi_chip = true, 4985 .ops = &mv88e6085_ops, 4986 }, 4987 4988 [MV88E6095] = { 4989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4990 .family = MV88E6XXX_FAMILY_6095, 4991 .name = "Marvell 88E6095/88E6095F", 4992 .num_databases = 256, 4993 .num_macs = 8192, 4994 .num_ports = 11, 4995 .num_internal_phys = 0, 4996 .max_vid = 4095, 4997 .port_base_addr = 0x10, 4998 .phy_base_addr = 0x0, 4999 .global1_addr = 0x1b, 5000 .global2_addr = 0x1c, 5001 .age_time_coeff = 15000, 5002 .g1_irqs = 8, 5003 .atu_move_port_mask = 0xf, 5004 .multi_chip = true, 5005 .ops = &mv88e6095_ops, 5006 }, 5007 5008 [MV88E6097] = { 5009 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5010 .family = MV88E6XXX_FAMILY_6097, 5011 .name = "Marvell 88E6097/88E6097F", 5012 .num_databases = 4096, 5013 .num_macs = 8192, 5014 .num_ports = 11, 5015 .num_internal_phys = 8, 5016 .max_vid = 4095, 5017 .port_base_addr = 0x10, 5018 .phy_base_addr = 0x0, 5019 .global1_addr = 0x1b, 5020 .global2_addr = 0x1c, 5021 .age_time_coeff = 15000, 5022 .g1_irqs = 8, 5023 .g2_irqs = 10, 5024 .atu_move_port_mask = 0xf, 5025 .pvt = true, 5026 .multi_chip = true, 5027 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5028 .ops = &mv88e6097_ops, 5029 }, 5030 5031 [MV88E6123] = { 5032 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5033 .family = MV88E6XXX_FAMILY_6165, 5034 .name = "Marvell 88E6123", 5035 .num_databases = 4096, 5036 .num_macs = 1024, 5037 .num_ports = 3, 5038 .num_internal_phys = 5, 5039 .max_vid = 4095, 5040 .port_base_addr = 0x10, 5041 .phy_base_addr = 0x0, 5042 .global1_addr = 0x1b, 5043 .global2_addr = 0x1c, 5044 .age_time_coeff = 15000, 5045 .g1_irqs = 9, 5046 .g2_irqs = 10, 5047 .atu_move_port_mask = 0xf, 5048 .pvt = true, 5049 .multi_chip = true, 5050 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5051 .ops = &mv88e6123_ops, 5052 }, 5053 5054 [MV88E6131] = { 5055 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5056 .family = MV88E6XXX_FAMILY_6185, 5057 .name = "Marvell 88E6131", 5058 .num_databases = 256, 5059 .num_macs = 8192, 5060 .num_ports = 8, 5061 .num_internal_phys = 0, 5062 .max_vid = 4095, 5063 .port_base_addr = 0x10, 5064 .phy_base_addr = 0x0, 5065 .global1_addr = 0x1b, 5066 .global2_addr = 0x1c, 5067 .age_time_coeff = 15000, 5068 .g1_irqs = 9, 5069 .atu_move_port_mask = 0xf, 5070 .multi_chip = true, 5071 .ops = &mv88e6131_ops, 5072 }, 5073 5074 [MV88E6141] = { 5075 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5076 .family = MV88E6XXX_FAMILY_6341, 5077 .name = "Marvell 88E6141", 5078 .num_databases = 4096, 5079 .num_macs = 2048, 5080 .num_ports = 6, 5081 .num_internal_phys = 5, 5082 .num_gpio = 11, 5083 .max_vid = 4095, 5084 .port_base_addr = 0x10, 5085 .phy_base_addr = 0x10, 5086 .global1_addr = 0x1b, 5087 .global2_addr = 0x1c, 5088 .age_time_coeff = 3750, 5089 .atu_move_port_mask = 0x1f, 5090 .g1_irqs = 9, 5091 .g2_irqs = 10, 5092 .pvt = true, 5093 .multi_chip = true, 5094 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5095 .ops = &mv88e6141_ops, 5096 }, 5097 5098 [MV88E6161] = { 5099 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5100 .family = MV88E6XXX_FAMILY_6165, 5101 .name = "Marvell 88E6161", 5102 .num_databases = 4096, 5103 .num_macs = 1024, 5104 .num_ports = 6, 5105 .num_internal_phys = 5, 5106 .max_vid = 4095, 5107 .port_base_addr = 0x10, 5108 .phy_base_addr = 0x0, 5109 .global1_addr = 0x1b, 5110 .global2_addr = 0x1c, 5111 .age_time_coeff = 15000, 5112 .g1_irqs = 9, 5113 .g2_irqs = 10, 5114 .atu_move_port_mask = 0xf, 5115 .pvt = true, 5116 .multi_chip = true, 5117 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5118 .ptp_support = true, 5119 .ops = &mv88e6161_ops, 5120 }, 5121 5122 [MV88E6165] = { 5123 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5124 .family = MV88E6XXX_FAMILY_6165, 5125 .name = "Marvell 88E6165", 5126 .num_databases = 4096, 5127 .num_macs = 8192, 5128 .num_ports = 6, 5129 .num_internal_phys = 0, 5130 .max_vid = 4095, 5131 .port_base_addr = 0x10, 5132 .phy_base_addr = 0x0, 5133 .global1_addr = 0x1b, 5134 .global2_addr = 0x1c, 5135 .age_time_coeff = 15000, 5136 .g1_irqs = 9, 5137 .g2_irqs = 10, 5138 .atu_move_port_mask = 0xf, 5139 .pvt = true, 5140 .multi_chip = true, 5141 .ptp_support = true, 5142 .ops = &mv88e6165_ops, 5143 }, 5144 5145 [MV88E6171] = { 5146 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5147 .family = MV88E6XXX_FAMILY_6351, 5148 .name = "Marvell 88E6171", 5149 .num_databases = 4096, 5150 .num_macs = 8192, 5151 .num_ports = 7, 5152 .num_internal_phys = 5, 5153 .max_vid = 4095, 5154 .port_base_addr = 0x10, 5155 .phy_base_addr = 0x0, 5156 .global1_addr = 0x1b, 5157 .global2_addr = 0x1c, 5158 .age_time_coeff = 15000, 5159 .g1_irqs = 9, 5160 .g2_irqs = 10, 5161 .atu_move_port_mask = 0xf, 5162 .pvt = true, 5163 .multi_chip = true, 5164 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5165 .ops = &mv88e6171_ops, 5166 }, 5167 5168 [MV88E6172] = { 5169 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5170 .family = MV88E6XXX_FAMILY_6352, 5171 .name = "Marvell 88E6172", 5172 .num_databases = 4096, 5173 .num_macs = 8192, 5174 .num_ports = 7, 5175 .num_internal_phys = 5, 5176 .num_gpio = 15, 5177 .max_vid = 4095, 5178 .port_base_addr = 0x10, 5179 .phy_base_addr = 0x0, 5180 .global1_addr = 0x1b, 5181 .global2_addr = 0x1c, 5182 .age_time_coeff = 15000, 5183 .g1_irqs = 9, 5184 .g2_irqs = 10, 5185 .atu_move_port_mask = 0xf, 5186 .pvt = true, 5187 .multi_chip = true, 5188 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5189 .ops = &mv88e6172_ops, 5190 }, 5191 5192 [MV88E6175] = { 5193 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5194 .family = MV88E6XXX_FAMILY_6351, 5195 .name = "Marvell 88E6175", 5196 .num_databases = 4096, 5197 .num_macs = 8192, 5198 .num_ports = 7, 5199 .num_internal_phys = 5, 5200 .max_vid = 4095, 5201 .port_base_addr = 0x10, 5202 .phy_base_addr = 0x0, 5203 .global1_addr = 0x1b, 5204 .global2_addr = 0x1c, 5205 .age_time_coeff = 15000, 5206 .g1_irqs = 9, 5207 .g2_irqs = 10, 5208 .atu_move_port_mask = 0xf, 5209 .pvt = true, 5210 .multi_chip = true, 5211 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5212 .ops = &mv88e6175_ops, 5213 }, 5214 5215 [MV88E6176] = { 5216 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5217 .family = MV88E6XXX_FAMILY_6352, 5218 .name = "Marvell 88E6176", 5219 .num_databases = 4096, 5220 .num_macs = 8192, 5221 .num_ports = 7, 5222 .num_internal_phys = 5, 5223 .num_gpio = 15, 5224 .max_vid = 4095, 5225 .port_base_addr = 0x10, 5226 .phy_base_addr = 0x0, 5227 .global1_addr = 0x1b, 5228 .global2_addr = 0x1c, 5229 .age_time_coeff = 15000, 5230 .g1_irqs = 9, 5231 .g2_irqs = 10, 5232 .atu_move_port_mask = 0xf, 5233 .pvt = true, 5234 .multi_chip = true, 5235 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5236 .ops = &mv88e6176_ops, 5237 }, 5238 5239 [MV88E6185] = { 5240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5241 .family = MV88E6XXX_FAMILY_6185, 5242 .name = "Marvell 88E6185", 5243 .num_databases = 256, 5244 .num_macs = 8192, 5245 .num_ports = 10, 5246 .num_internal_phys = 0, 5247 .max_vid = 4095, 5248 .port_base_addr = 0x10, 5249 .phy_base_addr = 0x0, 5250 .global1_addr = 0x1b, 5251 .global2_addr = 0x1c, 5252 .age_time_coeff = 15000, 5253 .g1_irqs = 8, 5254 .atu_move_port_mask = 0xf, 5255 .multi_chip = true, 5256 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5257 .ops = &mv88e6185_ops, 5258 }, 5259 5260 [MV88E6190] = { 5261 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5262 .family = MV88E6XXX_FAMILY_6390, 5263 .name = "Marvell 88E6190", 5264 .num_databases = 4096, 5265 .num_macs = 16384, 5266 .num_ports = 11, /* 10 + Z80 */ 5267 .num_internal_phys = 9, 5268 .num_gpio = 16, 5269 .max_vid = 8191, 5270 .port_base_addr = 0x0, 5271 .phy_base_addr = 0x0, 5272 .global1_addr = 0x1b, 5273 .global2_addr = 0x1c, 5274 .age_time_coeff = 3750, 5275 .g1_irqs = 9, 5276 .g2_irqs = 14, 5277 .pvt = true, 5278 .multi_chip = true, 5279 .atu_move_port_mask = 0x1f, 5280 .ops = &mv88e6190_ops, 5281 }, 5282 5283 [MV88E6190X] = { 5284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5285 .family = MV88E6XXX_FAMILY_6390, 5286 .name = "Marvell 88E6190X", 5287 .num_databases = 4096, 5288 .num_macs = 16384, 5289 .num_ports = 11, /* 10 + Z80 */ 5290 .num_internal_phys = 9, 5291 .num_gpio = 16, 5292 .max_vid = 8191, 5293 .port_base_addr = 0x0, 5294 .phy_base_addr = 0x0, 5295 .global1_addr = 0x1b, 5296 .global2_addr = 0x1c, 5297 .age_time_coeff = 3750, 5298 .g1_irqs = 9, 5299 .g2_irqs = 14, 5300 .atu_move_port_mask = 0x1f, 5301 .pvt = true, 5302 .multi_chip = true, 5303 .ops = &mv88e6190x_ops, 5304 }, 5305 5306 [MV88E6191] = { 5307 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5308 .family = MV88E6XXX_FAMILY_6390, 5309 .name = "Marvell 88E6191", 5310 .num_databases = 4096, 5311 .num_macs = 16384, 5312 .num_ports = 11, /* 10 + Z80 */ 5313 .num_internal_phys = 9, 5314 .max_vid = 8191, 5315 .port_base_addr = 0x0, 5316 .phy_base_addr = 0x0, 5317 .global1_addr = 0x1b, 5318 .global2_addr = 0x1c, 5319 .age_time_coeff = 3750, 5320 .g1_irqs = 9, 5321 .g2_irqs = 14, 5322 .atu_move_port_mask = 0x1f, 5323 .pvt = true, 5324 .multi_chip = true, 5325 .ptp_support = true, 5326 .ops = &mv88e6191_ops, 5327 }, 5328 5329 [MV88E6191X] = { 5330 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5331 .family = MV88E6XXX_FAMILY_6393, 5332 .name = "Marvell 88E6191X", 5333 .num_databases = 4096, 5334 .num_ports = 11, /* 10 + Z80 */ 5335 .num_internal_phys = 9, 5336 .max_vid = 8191, 5337 .port_base_addr = 0x0, 5338 .phy_base_addr = 0x0, 5339 .global1_addr = 0x1b, 5340 .global2_addr = 0x1c, 5341 .age_time_coeff = 3750, 5342 .g1_irqs = 10, 5343 .g2_irqs = 14, 5344 .atu_move_port_mask = 0x1f, 5345 .pvt = true, 5346 .multi_chip = true, 5347 .ptp_support = true, 5348 .ops = &mv88e6393x_ops, 5349 }, 5350 5351 [MV88E6193X] = { 5352 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5353 .family = MV88E6XXX_FAMILY_6393, 5354 .name = "Marvell 88E6193X", 5355 .num_databases = 4096, 5356 .num_ports = 11, /* 10 + Z80 */ 5357 .num_internal_phys = 9, 5358 .max_vid = 8191, 5359 .port_base_addr = 0x0, 5360 .phy_base_addr = 0x0, 5361 .global1_addr = 0x1b, 5362 .global2_addr = 0x1c, 5363 .age_time_coeff = 3750, 5364 .g1_irqs = 10, 5365 .g2_irqs = 14, 5366 .atu_move_port_mask = 0x1f, 5367 .pvt = true, 5368 .multi_chip = true, 5369 .ptp_support = true, 5370 .ops = &mv88e6393x_ops, 5371 }, 5372 5373 [MV88E6220] = { 5374 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5375 .family = MV88E6XXX_FAMILY_6250, 5376 .name = "Marvell 88E6220", 5377 .num_databases = 64, 5378 5379 /* Ports 2-4 are not routed to pins 5380 * => usable ports 0, 1, 5, 6 5381 */ 5382 .num_ports = 7, 5383 .num_internal_phys = 2, 5384 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5385 .max_vid = 4095, 5386 .port_base_addr = 0x08, 5387 .phy_base_addr = 0x00, 5388 .global1_addr = 0x0f, 5389 .global2_addr = 0x07, 5390 .age_time_coeff = 15000, 5391 .g1_irqs = 9, 5392 .g2_irqs = 10, 5393 .atu_move_port_mask = 0xf, 5394 .dual_chip = true, 5395 .ptp_support = true, 5396 .ops = &mv88e6250_ops, 5397 }, 5398 5399 [MV88E6240] = { 5400 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5401 .family = MV88E6XXX_FAMILY_6352, 5402 .name = "Marvell 88E6240", 5403 .num_databases = 4096, 5404 .num_macs = 8192, 5405 .num_ports = 7, 5406 .num_internal_phys = 5, 5407 .num_gpio = 15, 5408 .max_vid = 4095, 5409 .port_base_addr = 0x10, 5410 .phy_base_addr = 0x0, 5411 .global1_addr = 0x1b, 5412 .global2_addr = 0x1c, 5413 .age_time_coeff = 15000, 5414 .g1_irqs = 9, 5415 .g2_irqs = 10, 5416 .atu_move_port_mask = 0xf, 5417 .pvt = true, 5418 .multi_chip = true, 5419 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5420 .ptp_support = true, 5421 .ops = &mv88e6240_ops, 5422 }, 5423 5424 [MV88E6250] = { 5425 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5426 .family = MV88E6XXX_FAMILY_6250, 5427 .name = "Marvell 88E6250", 5428 .num_databases = 64, 5429 .num_ports = 7, 5430 .num_internal_phys = 5, 5431 .max_vid = 4095, 5432 .port_base_addr = 0x08, 5433 .phy_base_addr = 0x00, 5434 .global1_addr = 0x0f, 5435 .global2_addr = 0x07, 5436 .age_time_coeff = 15000, 5437 .g1_irqs = 9, 5438 .g2_irqs = 10, 5439 .atu_move_port_mask = 0xf, 5440 .dual_chip = true, 5441 .ptp_support = true, 5442 .ops = &mv88e6250_ops, 5443 }, 5444 5445 [MV88E6290] = { 5446 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5447 .family = MV88E6XXX_FAMILY_6390, 5448 .name = "Marvell 88E6290", 5449 .num_databases = 4096, 5450 .num_ports = 11, /* 10 + Z80 */ 5451 .num_internal_phys = 9, 5452 .num_gpio = 16, 5453 .max_vid = 8191, 5454 .port_base_addr = 0x0, 5455 .phy_base_addr = 0x0, 5456 .global1_addr = 0x1b, 5457 .global2_addr = 0x1c, 5458 .age_time_coeff = 3750, 5459 .g1_irqs = 9, 5460 .g2_irqs = 14, 5461 .atu_move_port_mask = 0x1f, 5462 .pvt = true, 5463 .multi_chip = true, 5464 .ptp_support = true, 5465 .ops = &mv88e6290_ops, 5466 }, 5467 5468 [MV88E6320] = { 5469 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5470 .family = MV88E6XXX_FAMILY_6320, 5471 .name = "Marvell 88E6320", 5472 .num_databases = 4096, 5473 .num_macs = 8192, 5474 .num_ports = 7, 5475 .num_internal_phys = 5, 5476 .num_gpio = 15, 5477 .max_vid = 4095, 5478 .port_base_addr = 0x10, 5479 .phy_base_addr = 0x0, 5480 .global1_addr = 0x1b, 5481 .global2_addr = 0x1c, 5482 .age_time_coeff = 15000, 5483 .g1_irqs = 8, 5484 .g2_irqs = 10, 5485 .atu_move_port_mask = 0xf, 5486 .pvt = true, 5487 .multi_chip = true, 5488 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5489 .ptp_support = true, 5490 .ops = &mv88e6320_ops, 5491 }, 5492 5493 [MV88E6321] = { 5494 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5495 .family = MV88E6XXX_FAMILY_6320, 5496 .name = "Marvell 88E6321", 5497 .num_databases = 4096, 5498 .num_macs = 8192, 5499 .num_ports = 7, 5500 .num_internal_phys = 5, 5501 .num_gpio = 15, 5502 .max_vid = 4095, 5503 .port_base_addr = 0x10, 5504 .phy_base_addr = 0x0, 5505 .global1_addr = 0x1b, 5506 .global2_addr = 0x1c, 5507 .age_time_coeff = 15000, 5508 .g1_irqs = 8, 5509 .g2_irqs = 10, 5510 .atu_move_port_mask = 0xf, 5511 .multi_chip = true, 5512 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5513 .ptp_support = true, 5514 .ops = &mv88e6321_ops, 5515 }, 5516 5517 [MV88E6341] = { 5518 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5519 .family = MV88E6XXX_FAMILY_6341, 5520 .name = "Marvell 88E6341", 5521 .num_databases = 4096, 5522 .num_macs = 2048, 5523 .num_internal_phys = 5, 5524 .num_ports = 6, 5525 .num_gpio = 11, 5526 .max_vid = 4095, 5527 .port_base_addr = 0x10, 5528 .phy_base_addr = 0x10, 5529 .global1_addr = 0x1b, 5530 .global2_addr = 0x1c, 5531 .age_time_coeff = 3750, 5532 .atu_move_port_mask = 0x1f, 5533 .g1_irqs = 9, 5534 .g2_irqs = 10, 5535 .pvt = true, 5536 .multi_chip = true, 5537 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5538 .ptp_support = true, 5539 .ops = &mv88e6341_ops, 5540 }, 5541 5542 [MV88E6350] = { 5543 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5544 .family = MV88E6XXX_FAMILY_6351, 5545 .name = "Marvell 88E6350", 5546 .num_databases = 4096, 5547 .num_macs = 8192, 5548 .num_ports = 7, 5549 .num_internal_phys = 5, 5550 .max_vid = 4095, 5551 .port_base_addr = 0x10, 5552 .phy_base_addr = 0x0, 5553 .global1_addr = 0x1b, 5554 .global2_addr = 0x1c, 5555 .age_time_coeff = 15000, 5556 .g1_irqs = 9, 5557 .g2_irqs = 10, 5558 .atu_move_port_mask = 0xf, 5559 .pvt = true, 5560 .multi_chip = true, 5561 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5562 .ops = &mv88e6350_ops, 5563 }, 5564 5565 [MV88E6351] = { 5566 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5567 .family = MV88E6XXX_FAMILY_6351, 5568 .name = "Marvell 88E6351", 5569 .num_databases = 4096, 5570 .num_macs = 8192, 5571 .num_ports = 7, 5572 .num_internal_phys = 5, 5573 .max_vid = 4095, 5574 .port_base_addr = 0x10, 5575 .phy_base_addr = 0x0, 5576 .global1_addr = 0x1b, 5577 .global2_addr = 0x1c, 5578 .age_time_coeff = 15000, 5579 .g1_irqs = 9, 5580 .g2_irqs = 10, 5581 .atu_move_port_mask = 0xf, 5582 .pvt = true, 5583 .multi_chip = true, 5584 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5585 .ops = &mv88e6351_ops, 5586 }, 5587 5588 [MV88E6352] = { 5589 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5590 .family = MV88E6XXX_FAMILY_6352, 5591 .name = "Marvell 88E6352", 5592 .num_databases = 4096, 5593 .num_macs = 8192, 5594 .num_ports = 7, 5595 .num_internal_phys = 5, 5596 .num_gpio = 15, 5597 .max_vid = 4095, 5598 .port_base_addr = 0x10, 5599 .phy_base_addr = 0x0, 5600 .global1_addr = 0x1b, 5601 .global2_addr = 0x1c, 5602 .age_time_coeff = 15000, 5603 .g1_irqs = 9, 5604 .g2_irqs = 10, 5605 .atu_move_port_mask = 0xf, 5606 .pvt = true, 5607 .multi_chip = true, 5608 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5609 .ptp_support = true, 5610 .ops = &mv88e6352_ops, 5611 }, 5612 [MV88E6390] = { 5613 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5614 .family = MV88E6XXX_FAMILY_6390, 5615 .name = "Marvell 88E6390", 5616 .num_databases = 4096, 5617 .num_macs = 16384, 5618 .num_ports = 11, /* 10 + Z80 */ 5619 .num_internal_phys = 9, 5620 .num_gpio = 16, 5621 .max_vid = 8191, 5622 .port_base_addr = 0x0, 5623 .phy_base_addr = 0x0, 5624 .global1_addr = 0x1b, 5625 .global2_addr = 0x1c, 5626 .age_time_coeff = 3750, 5627 .g1_irqs = 9, 5628 .g2_irqs = 14, 5629 .atu_move_port_mask = 0x1f, 5630 .pvt = true, 5631 .multi_chip = true, 5632 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5633 .ptp_support = true, 5634 .ops = &mv88e6390_ops, 5635 }, 5636 [MV88E6390X] = { 5637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5638 .family = MV88E6XXX_FAMILY_6390, 5639 .name = "Marvell 88E6390X", 5640 .num_databases = 4096, 5641 .num_macs = 16384, 5642 .num_ports = 11, /* 10 + Z80 */ 5643 .num_internal_phys = 9, 5644 .num_gpio = 16, 5645 .max_vid = 8191, 5646 .port_base_addr = 0x0, 5647 .phy_base_addr = 0x0, 5648 .global1_addr = 0x1b, 5649 .global2_addr = 0x1c, 5650 .age_time_coeff = 3750, 5651 .g1_irqs = 9, 5652 .g2_irqs = 14, 5653 .atu_move_port_mask = 0x1f, 5654 .pvt = true, 5655 .multi_chip = true, 5656 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5657 .ptp_support = true, 5658 .ops = &mv88e6390x_ops, 5659 }, 5660 5661 [MV88E6393X] = { 5662 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5663 .family = MV88E6XXX_FAMILY_6393, 5664 .name = "Marvell 88E6393X", 5665 .num_databases = 4096, 5666 .num_ports = 11, /* 10 + Z80 */ 5667 .num_internal_phys = 9, 5668 .max_vid = 8191, 5669 .port_base_addr = 0x0, 5670 .phy_base_addr = 0x0, 5671 .global1_addr = 0x1b, 5672 .global2_addr = 0x1c, 5673 .age_time_coeff = 3750, 5674 .g1_irqs = 10, 5675 .g2_irqs = 14, 5676 .atu_move_port_mask = 0x1f, 5677 .pvt = true, 5678 .multi_chip = true, 5679 .ptp_support = true, 5680 .ops = &mv88e6393x_ops, 5681 }, 5682 }; 5683 5684 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5685 { 5686 int i; 5687 5688 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5689 if (mv88e6xxx_table[i].prod_num == prod_num) 5690 return &mv88e6xxx_table[i]; 5691 5692 return NULL; 5693 } 5694 5695 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5696 { 5697 const struct mv88e6xxx_info *info; 5698 unsigned int prod_num, rev; 5699 u16 id; 5700 int err; 5701 5702 mv88e6xxx_reg_lock(chip); 5703 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5704 mv88e6xxx_reg_unlock(chip); 5705 if (err) 5706 return err; 5707 5708 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5709 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5710 5711 info = mv88e6xxx_lookup_info(prod_num); 5712 if (!info) 5713 return -ENODEV; 5714 5715 /* Update the compatible info with the probed one */ 5716 chip->info = info; 5717 5718 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5719 chip->info->prod_num, chip->info->name, rev); 5720 5721 return 0; 5722 } 5723 5724 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5725 { 5726 struct mv88e6xxx_chip *chip; 5727 5728 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5729 if (!chip) 5730 return NULL; 5731 5732 chip->dev = dev; 5733 5734 mutex_init(&chip->reg_lock); 5735 INIT_LIST_HEAD(&chip->mdios); 5736 idr_init(&chip->policies); 5737 5738 return chip; 5739 } 5740 5741 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5742 int port, 5743 enum dsa_tag_protocol m) 5744 { 5745 struct mv88e6xxx_chip *chip = ds->priv; 5746 5747 return chip->tag_protocol; 5748 } 5749 5750 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5751 enum dsa_tag_protocol proto) 5752 { 5753 struct mv88e6xxx_chip *chip = ds->priv; 5754 enum dsa_tag_protocol old_protocol; 5755 int err; 5756 5757 switch (proto) { 5758 case DSA_TAG_PROTO_EDSA: 5759 switch (chip->info->edsa_support) { 5760 case MV88E6XXX_EDSA_UNSUPPORTED: 5761 return -EPROTONOSUPPORT; 5762 case MV88E6XXX_EDSA_UNDOCUMENTED: 5763 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5764 fallthrough; 5765 case MV88E6XXX_EDSA_SUPPORTED: 5766 break; 5767 } 5768 break; 5769 case DSA_TAG_PROTO_DSA: 5770 break; 5771 default: 5772 return -EPROTONOSUPPORT; 5773 } 5774 5775 old_protocol = chip->tag_protocol; 5776 chip->tag_protocol = proto; 5777 5778 mv88e6xxx_reg_lock(chip); 5779 err = mv88e6xxx_setup_port_mode(chip, port); 5780 mv88e6xxx_reg_unlock(chip); 5781 5782 if (err) 5783 chip->tag_protocol = old_protocol; 5784 5785 return err; 5786 } 5787 5788 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5789 const struct switchdev_obj_port_mdb *mdb) 5790 { 5791 struct mv88e6xxx_chip *chip = ds->priv; 5792 int err; 5793 5794 mv88e6xxx_reg_lock(chip); 5795 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5796 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5797 mv88e6xxx_reg_unlock(chip); 5798 5799 return err; 5800 } 5801 5802 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5803 const struct switchdev_obj_port_mdb *mdb) 5804 { 5805 struct mv88e6xxx_chip *chip = ds->priv; 5806 int err; 5807 5808 mv88e6xxx_reg_lock(chip); 5809 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5810 mv88e6xxx_reg_unlock(chip); 5811 5812 return err; 5813 } 5814 5815 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5816 struct dsa_mall_mirror_tc_entry *mirror, 5817 bool ingress) 5818 { 5819 enum mv88e6xxx_egress_direction direction = ingress ? 5820 MV88E6XXX_EGRESS_DIR_INGRESS : 5821 MV88E6XXX_EGRESS_DIR_EGRESS; 5822 struct mv88e6xxx_chip *chip = ds->priv; 5823 bool other_mirrors = false; 5824 int i; 5825 int err; 5826 5827 mutex_lock(&chip->reg_lock); 5828 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5829 mirror->to_local_port) { 5830 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5831 other_mirrors |= ingress ? 5832 chip->ports[i].mirror_ingress : 5833 chip->ports[i].mirror_egress; 5834 5835 /* Can't change egress port when other mirror is active */ 5836 if (other_mirrors) { 5837 err = -EBUSY; 5838 goto out; 5839 } 5840 5841 err = mv88e6xxx_set_egress_port(chip, direction, 5842 mirror->to_local_port); 5843 if (err) 5844 goto out; 5845 } 5846 5847 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5848 out: 5849 mutex_unlock(&chip->reg_lock); 5850 5851 return err; 5852 } 5853 5854 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5855 struct dsa_mall_mirror_tc_entry *mirror) 5856 { 5857 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5858 MV88E6XXX_EGRESS_DIR_INGRESS : 5859 MV88E6XXX_EGRESS_DIR_EGRESS; 5860 struct mv88e6xxx_chip *chip = ds->priv; 5861 bool other_mirrors = false; 5862 int i; 5863 5864 mutex_lock(&chip->reg_lock); 5865 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5866 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5867 5868 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5869 other_mirrors |= mirror->ingress ? 5870 chip->ports[i].mirror_ingress : 5871 chip->ports[i].mirror_egress; 5872 5873 /* Reset egress port when no other mirror is active */ 5874 if (!other_mirrors) { 5875 if (mv88e6xxx_set_egress_port(chip, direction, 5876 dsa_upstream_port(ds, port))) 5877 dev_err(ds->dev, "failed to set egress port\n"); 5878 } 5879 5880 mutex_unlock(&chip->reg_lock); 5881 } 5882 5883 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5884 struct switchdev_brport_flags flags, 5885 struct netlink_ext_ack *extack) 5886 { 5887 struct mv88e6xxx_chip *chip = ds->priv; 5888 const struct mv88e6xxx_ops *ops; 5889 5890 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5891 BR_BCAST_FLOOD)) 5892 return -EINVAL; 5893 5894 ops = chip->info->ops; 5895 5896 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5897 return -EINVAL; 5898 5899 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5900 return -EINVAL; 5901 5902 return 0; 5903 } 5904 5905 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5906 struct switchdev_brport_flags flags, 5907 struct netlink_ext_ack *extack) 5908 { 5909 struct mv88e6xxx_chip *chip = ds->priv; 5910 int err = -EOPNOTSUPP; 5911 5912 mv88e6xxx_reg_lock(chip); 5913 5914 if (flags.mask & BR_LEARNING) { 5915 bool learning = !!(flags.val & BR_LEARNING); 5916 u16 pav = learning ? (1 << port) : 0; 5917 5918 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5919 if (err) 5920 goto out; 5921 } 5922 5923 if (flags.mask & BR_FLOOD) { 5924 bool unicast = !!(flags.val & BR_FLOOD); 5925 5926 err = chip->info->ops->port_set_ucast_flood(chip, port, 5927 unicast); 5928 if (err) 5929 goto out; 5930 } 5931 5932 if (flags.mask & BR_MCAST_FLOOD) { 5933 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5934 5935 err = chip->info->ops->port_set_mcast_flood(chip, port, 5936 multicast); 5937 if (err) 5938 goto out; 5939 } 5940 5941 if (flags.mask & BR_BCAST_FLOOD) { 5942 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5943 5944 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5945 if (err) 5946 goto out; 5947 } 5948 5949 out: 5950 mv88e6xxx_reg_unlock(chip); 5951 5952 return err; 5953 } 5954 5955 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5956 struct net_device *lag, 5957 struct netdev_lag_upper_info *info) 5958 { 5959 struct mv88e6xxx_chip *chip = ds->priv; 5960 struct dsa_port *dp; 5961 int id, members = 0; 5962 5963 if (!mv88e6xxx_has_lag(chip)) 5964 return false; 5965 5966 id = dsa_lag_id(ds->dst, lag); 5967 if (id < 0 || id >= ds->num_lag_ids) 5968 return false; 5969 5970 dsa_lag_foreach_port(dp, ds->dst, lag) 5971 /* Includes the port joining the LAG */ 5972 members++; 5973 5974 if (members > 8) 5975 return false; 5976 5977 /* We could potentially relax this to include active 5978 * backup in the future. 5979 */ 5980 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5981 return false; 5982 5983 /* Ideally we would also validate that the hash type matches 5984 * the hardware. Alas, this is always set to unknown on team 5985 * interfaces. 5986 */ 5987 return true; 5988 } 5989 5990 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5991 { 5992 struct mv88e6xxx_chip *chip = ds->priv; 5993 struct dsa_port *dp; 5994 u16 map = 0; 5995 int id; 5996 5997 id = dsa_lag_id(ds->dst, lag); 5998 5999 /* Build the map of all ports to distribute flows destined for 6000 * this LAG. This can be either a local user port, or a DSA 6001 * port if the LAG port is on a remote chip. 6002 */ 6003 dsa_lag_foreach_port(dp, ds->dst, lag) 6004 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6005 6006 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6007 } 6008 6009 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6010 /* Row number corresponds to the number of active members in a 6011 * LAG. Each column states which of the eight hash buckets are 6012 * mapped to the column:th port in the LAG. 6013 * 6014 * Example: In a LAG with three active ports, the second port 6015 * ([2][1]) would be selected for traffic mapped to buckets 6016 * 3,4,5 (0x38). 6017 */ 6018 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6019 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6020 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6021 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6022 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6023 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6024 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6025 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6026 }; 6027 6028 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6029 int num_tx, int nth) 6030 { 6031 u8 active = 0; 6032 int i; 6033 6034 num_tx = num_tx <= 8 ? num_tx : 8; 6035 if (nth < num_tx) 6036 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6037 6038 for (i = 0; i < 8; i++) { 6039 if (BIT(i) & active) 6040 mask[i] |= BIT(port); 6041 } 6042 } 6043 6044 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6045 { 6046 struct mv88e6xxx_chip *chip = ds->priv; 6047 unsigned int id, num_tx; 6048 struct net_device *lag; 6049 struct dsa_port *dp; 6050 int i, err, nth; 6051 u16 mask[8]; 6052 u16 ivec; 6053 6054 /* Assume no port is a member of any LAG. */ 6055 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6056 6057 /* Disable all masks for ports that _are_ members of a LAG. */ 6058 list_for_each_entry(dp, &ds->dst->ports, list) { 6059 if (!dp->lag_dev || dp->ds != ds) 6060 continue; 6061 6062 ivec &= ~BIT(dp->index); 6063 } 6064 6065 for (i = 0; i < 8; i++) 6066 mask[i] = ivec; 6067 6068 /* Enable the correct subset of masks for all LAG ports that 6069 * are in the Tx set. 6070 */ 6071 dsa_lags_foreach_id(id, ds->dst) { 6072 lag = dsa_lag_dev(ds->dst, id); 6073 if (!lag) 6074 continue; 6075 6076 num_tx = 0; 6077 dsa_lag_foreach_port(dp, ds->dst, lag) { 6078 if (dp->lag_tx_enabled) 6079 num_tx++; 6080 } 6081 6082 if (!num_tx) 6083 continue; 6084 6085 nth = 0; 6086 dsa_lag_foreach_port(dp, ds->dst, lag) { 6087 if (!dp->lag_tx_enabled) 6088 continue; 6089 6090 if (dp->ds == ds) 6091 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6092 num_tx, nth); 6093 6094 nth++; 6095 } 6096 } 6097 6098 for (i = 0; i < 8; i++) { 6099 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6100 if (err) 6101 return err; 6102 } 6103 6104 return 0; 6105 } 6106 6107 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6108 struct net_device *lag) 6109 { 6110 int err; 6111 6112 err = mv88e6xxx_lag_sync_masks(ds); 6113 6114 if (!err) 6115 err = mv88e6xxx_lag_sync_map(ds, lag); 6116 6117 return err; 6118 } 6119 6120 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6121 { 6122 struct mv88e6xxx_chip *chip = ds->priv; 6123 int err; 6124 6125 mv88e6xxx_reg_lock(chip); 6126 err = mv88e6xxx_lag_sync_masks(ds); 6127 mv88e6xxx_reg_unlock(chip); 6128 return err; 6129 } 6130 6131 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6132 struct net_device *lag, 6133 struct netdev_lag_upper_info *info) 6134 { 6135 struct mv88e6xxx_chip *chip = ds->priv; 6136 int err, id; 6137 6138 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6139 return -EOPNOTSUPP; 6140 6141 id = dsa_lag_id(ds->dst, lag); 6142 6143 mv88e6xxx_reg_lock(chip); 6144 6145 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6146 if (err) 6147 goto err_unlock; 6148 6149 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6150 if (err) 6151 goto err_clear_trunk; 6152 6153 mv88e6xxx_reg_unlock(chip); 6154 return 0; 6155 6156 err_clear_trunk: 6157 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6158 err_unlock: 6159 mv88e6xxx_reg_unlock(chip); 6160 return err; 6161 } 6162 6163 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6164 struct net_device *lag) 6165 { 6166 struct mv88e6xxx_chip *chip = ds->priv; 6167 int err_sync, err_trunk; 6168 6169 mv88e6xxx_reg_lock(chip); 6170 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6171 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6172 mv88e6xxx_reg_unlock(chip); 6173 return err_sync ? : err_trunk; 6174 } 6175 6176 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6177 int port) 6178 { 6179 struct mv88e6xxx_chip *chip = ds->priv; 6180 int err; 6181 6182 mv88e6xxx_reg_lock(chip); 6183 err = mv88e6xxx_lag_sync_masks(ds); 6184 mv88e6xxx_reg_unlock(chip); 6185 return err; 6186 } 6187 6188 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6189 int port, struct net_device *lag, 6190 struct netdev_lag_upper_info *info) 6191 { 6192 struct mv88e6xxx_chip *chip = ds->priv; 6193 int err; 6194 6195 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6196 return -EOPNOTSUPP; 6197 6198 mv88e6xxx_reg_lock(chip); 6199 6200 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6201 if (err) 6202 goto unlock; 6203 6204 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6205 6206 unlock: 6207 mv88e6xxx_reg_unlock(chip); 6208 return err; 6209 } 6210 6211 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6212 int port, struct net_device *lag) 6213 { 6214 struct mv88e6xxx_chip *chip = ds->priv; 6215 int err_sync, err_pvt; 6216 6217 mv88e6xxx_reg_lock(chip); 6218 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6219 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6220 mv88e6xxx_reg_unlock(chip); 6221 return err_sync ? : err_pvt; 6222 } 6223 6224 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6225 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6226 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6227 .setup = mv88e6xxx_setup, 6228 .teardown = mv88e6xxx_teardown, 6229 .port_setup = mv88e6xxx_port_setup, 6230 .port_teardown = mv88e6xxx_port_teardown, 6231 .phylink_validate = mv88e6xxx_validate, 6232 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6233 .phylink_mac_config = mv88e6xxx_mac_config, 6234 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6235 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6236 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6237 .get_strings = mv88e6xxx_get_strings, 6238 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6239 .get_sset_count = mv88e6xxx_get_sset_count, 6240 .port_enable = mv88e6xxx_port_enable, 6241 .port_disable = mv88e6xxx_port_disable, 6242 .port_max_mtu = mv88e6xxx_get_max_mtu, 6243 .port_change_mtu = mv88e6xxx_change_mtu, 6244 .get_mac_eee = mv88e6xxx_get_mac_eee, 6245 .set_mac_eee = mv88e6xxx_set_mac_eee, 6246 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6247 .get_eeprom = mv88e6xxx_get_eeprom, 6248 .set_eeprom = mv88e6xxx_set_eeprom, 6249 .get_regs_len = mv88e6xxx_get_regs_len, 6250 .get_regs = mv88e6xxx_get_regs, 6251 .get_rxnfc = mv88e6xxx_get_rxnfc, 6252 .set_rxnfc = mv88e6xxx_set_rxnfc, 6253 .set_ageing_time = mv88e6xxx_set_ageing_time, 6254 .port_bridge_join = mv88e6xxx_port_bridge_join, 6255 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6256 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6257 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6258 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6259 .port_fast_age = mv88e6xxx_port_fast_age, 6260 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6261 .port_vlan_add = mv88e6xxx_port_vlan_add, 6262 .port_vlan_del = mv88e6xxx_port_vlan_del, 6263 .port_fdb_add = mv88e6xxx_port_fdb_add, 6264 .port_fdb_del = mv88e6xxx_port_fdb_del, 6265 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6266 .port_mdb_add = mv88e6xxx_port_mdb_add, 6267 .port_mdb_del = mv88e6xxx_port_mdb_del, 6268 .port_mirror_add = mv88e6xxx_port_mirror_add, 6269 .port_mirror_del = mv88e6xxx_port_mirror_del, 6270 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6271 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6272 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6273 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6274 .port_txtstamp = mv88e6xxx_port_txtstamp, 6275 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6276 .get_ts_info = mv88e6xxx_get_ts_info, 6277 .devlink_param_get = mv88e6xxx_devlink_param_get, 6278 .devlink_param_set = mv88e6xxx_devlink_param_set, 6279 .devlink_info_get = mv88e6xxx_devlink_info_get, 6280 .port_lag_change = mv88e6xxx_port_lag_change, 6281 .port_lag_join = mv88e6xxx_port_lag_join, 6282 .port_lag_leave = mv88e6xxx_port_lag_leave, 6283 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6284 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6285 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6286 }; 6287 6288 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6289 { 6290 struct device *dev = chip->dev; 6291 struct dsa_switch *ds; 6292 6293 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6294 if (!ds) 6295 return -ENOMEM; 6296 6297 ds->dev = dev; 6298 ds->num_ports = mv88e6xxx_num_ports(chip); 6299 ds->priv = chip; 6300 ds->dev = dev; 6301 ds->ops = &mv88e6xxx_switch_ops; 6302 ds->ageing_time_min = chip->info->age_time_coeff; 6303 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6304 6305 /* Some chips support up to 32, but that requires enabling the 6306 * 5-bit port mode, which we do not support. 640k^W16 ought to 6307 * be enough for anyone. 6308 */ 6309 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6310 6311 dev_set_drvdata(dev, ds); 6312 6313 return dsa_register_switch(ds); 6314 } 6315 6316 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6317 { 6318 dsa_unregister_switch(chip->ds); 6319 } 6320 6321 static const void *pdata_device_get_match_data(struct device *dev) 6322 { 6323 const struct of_device_id *matches = dev->driver->of_match_table; 6324 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6325 6326 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6327 matches++) { 6328 if (!strcmp(pdata->compatible, matches->compatible)) 6329 return matches->data; 6330 } 6331 return NULL; 6332 } 6333 6334 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6335 * would be lost after a power cycle so prevent it to be suspended. 6336 */ 6337 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6338 { 6339 return -EOPNOTSUPP; 6340 } 6341 6342 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6343 { 6344 return 0; 6345 } 6346 6347 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6348 6349 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6350 { 6351 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6352 const struct mv88e6xxx_info *compat_info = NULL; 6353 struct device *dev = &mdiodev->dev; 6354 struct device_node *np = dev->of_node; 6355 struct mv88e6xxx_chip *chip; 6356 int port; 6357 int err; 6358 6359 if (!np && !pdata) 6360 return -EINVAL; 6361 6362 if (np) 6363 compat_info = of_device_get_match_data(dev); 6364 6365 if (pdata) { 6366 compat_info = pdata_device_get_match_data(dev); 6367 6368 if (!pdata->netdev) 6369 return -EINVAL; 6370 6371 for (port = 0; port < DSA_MAX_PORTS; port++) { 6372 if (!(pdata->enabled_ports & (1 << port))) 6373 continue; 6374 if (strcmp(pdata->cd.port_names[port], "cpu")) 6375 continue; 6376 pdata->cd.netdev[port] = &pdata->netdev->dev; 6377 break; 6378 } 6379 } 6380 6381 if (!compat_info) 6382 return -EINVAL; 6383 6384 chip = mv88e6xxx_alloc_chip(dev); 6385 if (!chip) { 6386 err = -ENOMEM; 6387 goto out; 6388 } 6389 6390 chip->info = compat_info; 6391 6392 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6393 if (err) 6394 goto out; 6395 6396 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6397 if (IS_ERR(chip->reset)) { 6398 err = PTR_ERR(chip->reset); 6399 goto out; 6400 } 6401 if (chip->reset) 6402 usleep_range(1000, 2000); 6403 6404 err = mv88e6xxx_detect(chip); 6405 if (err) 6406 goto out; 6407 6408 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6409 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6410 else 6411 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6412 6413 mv88e6xxx_phy_init(chip); 6414 6415 if (chip->info->ops->get_eeprom) { 6416 if (np) 6417 of_property_read_u32(np, "eeprom-length", 6418 &chip->eeprom_len); 6419 else 6420 chip->eeprom_len = pdata->eeprom_len; 6421 } 6422 6423 mv88e6xxx_reg_lock(chip); 6424 err = mv88e6xxx_switch_reset(chip); 6425 mv88e6xxx_reg_unlock(chip); 6426 if (err) 6427 goto out; 6428 6429 if (np) { 6430 chip->irq = of_irq_get(np, 0); 6431 if (chip->irq == -EPROBE_DEFER) { 6432 err = chip->irq; 6433 goto out; 6434 } 6435 } 6436 6437 if (pdata) 6438 chip->irq = pdata->irq; 6439 6440 /* Has to be performed before the MDIO bus is created, because 6441 * the PHYs will link their interrupts to these interrupt 6442 * controllers 6443 */ 6444 mv88e6xxx_reg_lock(chip); 6445 if (chip->irq > 0) 6446 err = mv88e6xxx_g1_irq_setup(chip); 6447 else 6448 err = mv88e6xxx_irq_poll_setup(chip); 6449 mv88e6xxx_reg_unlock(chip); 6450 6451 if (err) 6452 goto out; 6453 6454 if (chip->info->g2_irqs > 0) { 6455 err = mv88e6xxx_g2_irq_setup(chip); 6456 if (err) 6457 goto out_g1_irq; 6458 } 6459 6460 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6461 if (err) 6462 goto out_g2_irq; 6463 6464 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6465 if (err) 6466 goto out_g1_atu_prob_irq; 6467 6468 err = mv88e6xxx_mdios_register(chip, np); 6469 if (err) 6470 goto out_g1_vtu_prob_irq; 6471 6472 err = mv88e6xxx_register_switch(chip); 6473 if (err) 6474 goto out_mdio; 6475 6476 return 0; 6477 6478 out_mdio: 6479 mv88e6xxx_mdios_unregister(chip); 6480 out_g1_vtu_prob_irq: 6481 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6482 out_g1_atu_prob_irq: 6483 mv88e6xxx_g1_atu_prob_irq_free(chip); 6484 out_g2_irq: 6485 if (chip->info->g2_irqs > 0) 6486 mv88e6xxx_g2_irq_free(chip); 6487 out_g1_irq: 6488 if (chip->irq > 0) 6489 mv88e6xxx_g1_irq_free(chip); 6490 else 6491 mv88e6xxx_irq_poll_free(chip); 6492 out: 6493 if (pdata) 6494 dev_put(pdata->netdev); 6495 6496 return err; 6497 } 6498 6499 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6500 { 6501 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6502 struct mv88e6xxx_chip *chip; 6503 6504 if (!ds) 6505 return; 6506 6507 chip = ds->priv; 6508 6509 if (chip->info->ptp_support) { 6510 mv88e6xxx_hwtstamp_free(chip); 6511 mv88e6xxx_ptp_free(chip); 6512 } 6513 6514 mv88e6xxx_phy_destroy(chip); 6515 mv88e6xxx_unregister_switch(chip); 6516 mv88e6xxx_mdios_unregister(chip); 6517 6518 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6519 mv88e6xxx_g1_atu_prob_irq_free(chip); 6520 6521 if (chip->info->g2_irqs > 0) 6522 mv88e6xxx_g2_irq_free(chip); 6523 6524 if (chip->irq > 0) 6525 mv88e6xxx_g1_irq_free(chip); 6526 else 6527 mv88e6xxx_irq_poll_free(chip); 6528 6529 dev_set_drvdata(&mdiodev->dev, NULL); 6530 } 6531 6532 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6533 { 6534 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6535 6536 if (!ds) 6537 return; 6538 6539 dsa_switch_shutdown(ds); 6540 6541 dev_set_drvdata(&mdiodev->dev, NULL); 6542 } 6543 6544 static const struct of_device_id mv88e6xxx_of_match[] = { 6545 { 6546 .compatible = "marvell,mv88e6085", 6547 .data = &mv88e6xxx_table[MV88E6085], 6548 }, 6549 { 6550 .compatible = "marvell,mv88e6190", 6551 .data = &mv88e6xxx_table[MV88E6190], 6552 }, 6553 { 6554 .compatible = "marvell,mv88e6250", 6555 .data = &mv88e6xxx_table[MV88E6250], 6556 }, 6557 { /* sentinel */ }, 6558 }; 6559 6560 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6561 6562 static struct mdio_driver mv88e6xxx_driver = { 6563 .probe = mv88e6xxx_probe, 6564 .remove = mv88e6xxx_remove, 6565 .shutdown = mv88e6xxx_shutdown, 6566 .mdiodrv.driver = { 6567 .name = "mv88e6085", 6568 .of_match_table = mv88e6xxx_of_match, 6569 .pm = &mv88e6xxx_pm_ops, 6570 }, 6571 }; 6572 6573 mdio_module_driver(mv88e6xxx_driver); 6574 6575 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6576 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6577 MODULE_LICENSE("GPL"); 6578