1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 mv88e6xxx_reg_unlock(chip); 344 err = request_threaded_irq(chip->irq, NULL, 345 mv88e6xxx_g1_irq_thread_fn, 346 IRQF_ONESHOT | IRQF_SHARED, 347 dev_name(chip->dev), chip); 348 mv88e6xxx_reg_lock(chip); 349 if (err) 350 mv88e6xxx_g1_irq_free_common(chip); 351 352 return err; 353 } 354 355 static void mv88e6xxx_irq_poll(struct kthread_work *work) 356 { 357 struct mv88e6xxx_chip *chip = container_of(work, 358 struct mv88e6xxx_chip, 359 irq_poll_work.work); 360 mv88e6xxx_g1_irq_thread_work(chip); 361 362 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 363 msecs_to_jiffies(100)); 364 } 365 366 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 367 { 368 int err; 369 370 err = mv88e6xxx_g1_irq_setup_common(chip); 371 if (err) 372 return err; 373 374 kthread_init_delayed_work(&chip->irq_poll_work, 375 mv88e6xxx_irq_poll); 376 377 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 378 if (IS_ERR(chip->kworker)) 379 return PTR_ERR(chip->kworker); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 384 return 0; 385 } 386 387 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 388 { 389 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 390 kthread_destroy_worker(chip->kworker); 391 392 mv88e6xxx_reg_lock(chip); 393 mv88e6xxx_g1_irq_free_common(chip); 394 mv88e6xxx_reg_unlock(chip); 395 } 396 397 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 398 int speed, int duplex, int pause, 399 phy_interface_t mode) 400 { 401 struct phylink_link_state state; 402 int err; 403 404 if (!chip->info->ops->port_set_link) 405 return 0; 406 407 if (!chip->info->ops->port_link_state) 408 return 0; 409 410 err = chip->info->ops->port_link_state(chip, port, &state); 411 if (err) 412 return err; 413 414 /* Has anything actually changed? We don't expect the 415 * interface mode to change without one of the other 416 * parameters also changing 417 */ 418 if (state.link == link && 419 state.speed == speed && 420 state.duplex == duplex) 421 return 0; 422 423 /* Port's MAC control must not be changed unless the link is down */ 424 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 425 if (err) 426 return err; 427 428 if (chip->info->ops->port_set_speed) { 429 err = chip->info->ops->port_set_speed(chip, port, speed); 430 if (err && err != -EOPNOTSUPP) 431 goto restore_link; 432 } 433 434 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 435 mode = chip->info->ops->port_max_speed_mode(port); 436 437 if (chip->info->ops->port_set_pause) { 438 err = chip->info->ops->port_set_pause(chip, port, pause); 439 if (err) 440 goto restore_link; 441 } 442 443 if (chip->info->ops->port_set_duplex) { 444 err = chip->info->ops->port_set_duplex(chip, port, duplex); 445 if (err && err != -EOPNOTSUPP) 446 goto restore_link; 447 } 448 449 if (chip->info->ops->port_set_rgmii_delay) { 450 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 451 if (err && err != -EOPNOTSUPP) 452 goto restore_link; 453 } 454 455 if (chip->info->ops->port_set_cmode) { 456 err = chip->info->ops->port_set_cmode(chip, port, mode); 457 if (err && err != -EOPNOTSUPP) 458 goto restore_link; 459 } 460 461 err = 0; 462 restore_link: 463 if (chip->info->ops->port_set_link(chip, port, link)) 464 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 465 466 return err; 467 } 468 469 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 470 { 471 struct mv88e6xxx_chip *chip = ds->priv; 472 473 return port < chip->info->num_internal_phys; 474 } 475 476 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 477 unsigned long *mask, 478 struct phylink_link_state *state) 479 { 480 if (!phy_interface_mode_is_8023z(state->interface)) { 481 /* 10M and 100M are only supported in non-802.3z mode */ 482 phylink_set(mask, 10baseT_Half); 483 phylink_set(mask, 10baseT_Full); 484 phylink_set(mask, 100baseT_Half); 485 phylink_set(mask, 100baseT_Full); 486 } 487 } 488 489 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 490 unsigned long *mask, 491 struct phylink_link_state *state) 492 { 493 /* FIXME: if the port is in 1000Base-X mode, then it only supports 494 * 1000M FD speeds. In this case, CMODE will indicate 5. 495 */ 496 phylink_set(mask, 1000baseT_Full); 497 phylink_set(mask, 1000baseX_Full); 498 499 mv88e6065_phylink_validate(chip, port, mask, state); 500 } 501 502 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 503 unsigned long *mask, 504 struct phylink_link_state *state) 505 { 506 if (port >= 5) 507 phylink_set(mask, 2500baseX_Full); 508 509 /* No ethtool bits for 200Mbps */ 510 phylink_set(mask, 1000baseT_Full); 511 phylink_set(mask, 1000baseX_Full); 512 513 mv88e6065_phylink_validate(chip, port, mask, state); 514 } 515 516 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 517 unsigned long *mask, 518 struct phylink_link_state *state) 519 { 520 /* No ethtool bits for 200Mbps */ 521 phylink_set(mask, 1000baseT_Full); 522 phylink_set(mask, 1000baseX_Full); 523 524 mv88e6065_phylink_validate(chip, port, mask, state); 525 } 526 527 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 528 unsigned long *mask, 529 struct phylink_link_state *state) 530 { 531 if (port >= 9) { 532 phylink_set(mask, 2500baseX_Full); 533 phylink_set(mask, 2500baseT_Full); 534 } 535 536 /* No ethtool bits for 200Mbps */ 537 phylink_set(mask, 1000baseT_Full); 538 phylink_set(mask, 1000baseX_Full); 539 540 mv88e6065_phylink_validate(chip, port, mask, state); 541 } 542 543 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 544 unsigned long *mask, 545 struct phylink_link_state *state) 546 { 547 if (port >= 9) { 548 phylink_set(mask, 10000baseT_Full); 549 phylink_set(mask, 10000baseKR_Full); 550 } 551 552 mv88e6390_phylink_validate(chip, port, mask, state); 553 } 554 555 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 556 unsigned long *supported, 557 struct phylink_link_state *state) 558 { 559 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 560 struct mv88e6xxx_chip *chip = ds->priv; 561 562 /* Allow all the expected bits */ 563 phylink_set(mask, Autoneg); 564 phylink_set(mask, Pause); 565 phylink_set_port_modes(mask); 566 567 if (chip->info->ops->phylink_validate) 568 chip->info->ops->phylink_validate(chip, port, mask, state); 569 570 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 571 bitmap_and(state->advertising, state->advertising, mask, 572 __ETHTOOL_LINK_MODE_MASK_NBITS); 573 574 /* We can only operate at 2500BaseX or 1000BaseX. If requested 575 * to advertise both, only report advertising at 2500BaseX. 576 */ 577 phylink_helper_basex_speed(state); 578 } 579 580 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 581 struct phylink_link_state *state) 582 { 583 struct mv88e6xxx_chip *chip = ds->priv; 584 int err; 585 586 mv88e6xxx_reg_lock(chip); 587 if (chip->info->ops->port_link_state) 588 err = chip->info->ops->port_link_state(chip, port, state); 589 else 590 err = -EOPNOTSUPP; 591 mv88e6xxx_reg_unlock(chip); 592 593 return err; 594 } 595 596 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 597 unsigned int mode, 598 const struct phylink_link_state *state) 599 { 600 struct mv88e6xxx_chip *chip = ds->priv; 601 int speed, duplex, link, pause, err; 602 603 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 604 return; 605 606 if (mode == MLO_AN_FIXED) { 607 link = LINK_FORCED_UP; 608 speed = state->speed; 609 duplex = state->duplex; 610 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 611 link = state->link; 612 speed = state->speed; 613 duplex = state->duplex; 614 } else { 615 speed = SPEED_UNFORCED; 616 duplex = DUPLEX_UNFORCED; 617 link = LINK_UNFORCED; 618 } 619 pause = !!phylink_test(state->advertising, Pause); 620 621 mv88e6xxx_reg_lock(chip); 622 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 623 state->interface); 624 mv88e6xxx_reg_unlock(chip); 625 626 if (err && err != -EOPNOTSUPP) 627 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 628 } 629 630 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 631 { 632 struct mv88e6xxx_chip *chip = ds->priv; 633 int err; 634 635 mv88e6xxx_reg_lock(chip); 636 err = chip->info->ops->port_set_link(chip, port, link); 637 mv88e6xxx_reg_unlock(chip); 638 639 if (err) 640 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 641 } 642 643 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 644 unsigned int mode, 645 phy_interface_t interface) 646 { 647 if (mode == MLO_AN_FIXED) 648 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 649 } 650 651 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 652 unsigned int mode, phy_interface_t interface, 653 struct phy_device *phydev) 654 { 655 if (mode == MLO_AN_FIXED) 656 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 657 } 658 659 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 660 { 661 if (!chip->info->ops->stats_snapshot) 662 return -EOPNOTSUPP; 663 664 return chip->info->ops->stats_snapshot(chip, port); 665 } 666 667 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 668 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 669 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 670 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 671 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 672 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 673 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 674 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 675 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 676 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 677 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 678 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 679 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 680 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 681 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 682 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 683 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 684 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 685 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 686 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 687 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 688 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 689 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 690 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 691 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 692 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 693 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 694 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 695 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 696 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 697 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 698 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 699 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 700 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 701 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 702 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 703 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 704 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 705 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 706 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 707 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 708 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 709 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 710 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 711 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 712 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 713 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 714 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 715 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 716 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 717 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 718 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 719 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 720 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 721 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 722 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 723 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 724 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 725 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 726 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 727 }; 728 729 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 730 struct mv88e6xxx_hw_stat *s, 731 int port, u16 bank1_select, 732 u16 histogram) 733 { 734 u32 low; 735 u32 high = 0; 736 u16 reg = 0; 737 int err; 738 u64 value; 739 740 switch (s->type) { 741 case STATS_TYPE_PORT: 742 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 743 if (err) 744 return U64_MAX; 745 746 low = reg; 747 if (s->size == 4) { 748 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 749 if (err) 750 return U64_MAX; 751 low |= ((u32)reg) << 16; 752 } 753 break; 754 case STATS_TYPE_BANK1: 755 reg = bank1_select; 756 /* fall through */ 757 case STATS_TYPE_BANK0: 758 reg |= s->reg | histogram; 759 mv88e6xxx_g1_stats_read(chip, reg, &low); 760 if (s->size == 8) 761 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 762 break; 763 default: 764 return U64_MAX; 765 } 766 value = (((u64)high) << 32) | low; 767 return value; 768 } 769 770 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 771 uint8_t *data, int types) 772 { 773 struct mv88e6xxx_hw_stat *stat; 774 int i, j; 775 776 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 777 stat = &mv88e6xxx_hw_stats[i]; 778 if (stat->type & types) { 779 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 780 ETH_GSTRING_LEN); 781 j++; 782 } 783 } 784 785 return j; 786 } 787 788 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 789 uint8_t *data) 790 { 791 return mv88e6xxx_stats_get_strings(chip, data, 792 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 793 } 794 795 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 796 uint8_t *data) 797 { 798 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 799 } 800 801 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 802 uint8_t *data) 803 { 804 return mv88e6xxx_stats_get_strings(chip, data, 805 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 806 } 807 808 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 809 "atu_member_violation", 810 "atu_miss_violation", 811 "atu_full_violation", 812 "vtu_member_violation", 813 "vtu_miss_violation", 814 }; 815 816 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 817 { 818 unsigned int i; 819 820 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 821 strlcpy(data + i * ETH_GSTRING_LEN, 822 mv88e6xxx_atu_vtu_stats_strings[i], 823 ETH_GSTRING_LEN); 824 } 825 826 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 827 u32 stringset, uint8_t *data) 828 { 829 struct mv88e6xxx_chip *chip = ds->priv; 830 int count = 0; 831 832 if (stringset != ETH_SS_STATS) 833 return; 834 835 mv88e6xxx_reg_lock(chip); 836 837 if (chip->info->ops->stats_get_strings) 838 count = chip->info->ops->stats_get_strings(chip, data); 839 840 if (chip->info->ops->serdes_get_strings) { 841 data += count * ETH_GSTRING_LEN; 842 count = chip->info->ops->serdes_get_strings(chip, port, data); 843 } 844 845 data += count * ETH_GSTRING_LEN; 846 mv88e6xxx_atu_vtu_get_strings(data); 847 848 mv88e6xxx_reg_unlock(chip); 849 } 850 851 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 852 int types) 853 { 854 struct mv88e6xxx_hw_stat *stat; 855 int i, j; 856 857 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 858 stat = &mv88e6xxx_hw_stats[i]; 859 if (stat->type & types) 860 j++; 861 } 862 return j; 863 } 864 865 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 866 { 867 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 868 STATS_TYPE_PORT); 869 } 870 871 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 872 { 873 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 874 } 875 876 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 877 { 878 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 879 STATS_TYPE_BANK1); 880 } 881 882 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 883 { 884 struct mv88e6xxx_chip *chip = ds->priv; 885 int serdes_count = 0; 886 int count = 0; 887 888 if (sset != ETH_SS_STATS) 889 return 0; 890 891 mv88e6xxx_reg_lock(chip); 892 if (chip->info->ops->stats_get_sset_count) 893 count = chip->info->ops->stats_get_sset_count(chip); 894 if (count < 0) 895 goto out; 896 897 if (chip->info->ops->serdes_get_sset_count) 898 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 899 port); 900 if (serdes_count < 0) { 901 count = serdes_count; 902 goto out; 903 } 904 count += serdes_count; 905 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 906 907 out: 908 mv88e6xxx_reg_unlock(chip); 909 910 return count; 911 } 912 913 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 914 uint64_t *data, int types, 915 u16 bank1_select, u16 histogram) 916 { 917 struct mv88e6xxx_hw_stat *stat; 918 int i, j; 919 920 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 921 stat = &mv88e6xxx_hw_stats[i]; 922 if (stat->type & types) { 923 mv88e6xxx_reg_lock(chip); 924 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 925 bank1_select, 926 histogram); 927 mv88e6xxx_reg_unlock(chip); 928 929 j++; 930 } 931 } 932 return j; 933 } 934 935 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 936 uint64_t *data) 937 { 938 return mv88e6xxx_stats_get_stats(chip, port, data, 939 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 940 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 941 } 942 943 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 944 uint64_t *data) 945 { 946 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 947 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 948 } 949 950 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 951 uint64_t *data) 952 { 953 return mv88e6xxx_stats_get_stats(chip, port, data, 954 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 955 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 956 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 957 } 958 959 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 960 uint64_t *data) 961 { 962 return mv88e6xxx_stats_get_stats(chip, port, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 964 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 965 0); 966 } 967 968 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 969 uint64_t *data) 970 { 971 *data++ = chip->ports[port].atu_member_violation; 972 *data++ = chip->ports[port].atu_miss_violation; 973 *data++ = chip->ports[port].atu_full_violation; 974 *data++ = chip->ports[port].vtu_member_violation; 975 *data++ = chip->ports[port].vtu_miss_violation; 976 } 977 978 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 979 uint64_t *data) 980 { 981 int count = 0; 982 983 if (chip->info->ops->stats_get_stats) 984 count = chip->info->ops->stats_get_stats(chip, port, data); 985 986 mv88e6xxx_reg_lock(chip); 987 if (chip->info->ops->serdes_get_stats) { 988 data += count; 989 count = chip->info->ops->serdes_get_stats(chip, port, data); 990 } 991 data += count; 992 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 993 mv88e6xxx_reg_unlock(chip); 994 } 995 996 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 997 uint64_t *data) 998 { 999 struct mv88e6xxx_chip *chip = ds->priv; 1000 int ret; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 1004 ret = mv88e6xxx_stats_snapshot(chip, port); 1005 mv88e6xxx_reg_unlock(chip); 1006 1007 if (ret < 0) 1008 return; 1009 1010 mv88e6xxx_get_stats(chip, port, data); 1011 1012 } 1013 1014 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1015 { 1016 return 32 * sizeof(u16); 1017 } 1018 1019 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1020 struct ethtool_regs *regs, void *_p) 1021 { 1022 struct mv88e6xxx_chip *chip = ds->priv; 1023 int err; 1024 u16 reg; 1025 u16 *p = _p; 1026 int i; 1027 1028 regs->version = chip->info->prod_num; 1029 1030 memset(p, 0xff, 32 * sizeof(u16)); 1031 1032 mv88e6xxx_reg_lock(chip); 1033 1034 for (i = 0; i < 32; i++) { 1035 1036 err = mv88e6xxx_port_read(chip, port, i, ®); 1037 if (!err) 1038 p[i] = reg; 1039 } 1040 1041 mv88e6xxx_reg_unlock(chip); 1042 } 1043 1044 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1045 struct ethtool_eee *e) 1046 { 1047 /* Nothing to do on the port's MAC */ 1048 return 0; 1049 } 1050 1051 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1052 struct ethtool_eee *e) 1053 { 1054 /* Nothing to do on the port's MAC */ 1055 return 0; 1056 } 1057 1058 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1059 { 1060 struct dsa_switch *ds = NULL; 1061 struct net_device *br; 1062 u16 pvlan; 1063 int i; 1064 1065 if (dev < DSA_MAX_SWITCHES) 1066 ds = chip->ds->dst->ds[dev]; 1067 1068 /* Prevent frames from unknown switch or port */ 1069 if (!ds || port >= ds->num_ports) 1070 return 0; 1071 1072 /* Frames from DSA links and CPU ports can egress any local port */ 1073 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1074 return mv88e6xxx_port_mask(chip); 1075 1076 br = ds->ports[port].bridge_dev; 1077 pvlan = 0; 1078 1079 /* Frames from user ports can egress any local DSA links and CPU ports, 1080 * as well as any local member of their bridge group. 1081 */ 1082 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1083 if (dsa_is_cpu_port(chip->ds, i) || 1084 dsa_is_dsa_port(chip->ds, i) || 1085 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1086 pvlan |= BIT(i); 1087 1088 return pvlan; 1089 } 1090 1091 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1092 { 1093 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1094 1095 /* prevent frames from going back out of the port they came in on */ 1096 output_ports &= ~BIT(port); 1097 1098 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1099 } 1100 1101 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1102 u8 state) 1103 { 1104 struct mv88e6xxx_chip *chip = ds->priv; 1105 int err; 1106 1107 mv88e6xxx_reg_lock(chip); 1108 err = mv88e6xxx_port_set_state(chip, port, state); 1109 mv88e6xxx_reg_unlock(chip); 1110 1111 if (err) 1112 dev_err(ds->dev, "p%d: failed to update state\n", port); 1113 } 1114 1115 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1116 { 1117 int err; 1118 1119 if (chip->info->ops->ieee_pri_map) { 1120 err = chip->info->ops->ieee_pri_map(chip); 1121 if (err) 1122 return err; 1123 } 1124 1125 if (chip->info->ops->ip_pri_map) { 1126 err = chip->info->ops->ip_pri_map(chip); 1127 if (err) 1128 return err; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1135 { 1136 int target, port; 1137 int err; 1138 1139 if (!chip->info->global2_addr) 1140 return 0; 1141 1142 /* Initialize the routing port to the 32 possible target devices */ 1143 for (target = 0; target < 32; target++) { 1144 port = 0x1f; 1145 if (target < DSA_MAX_SWITCHES) 1146 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1147 port = chip->ds->rtable[target]; 1148 1149 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1150 if (err) 1151 return err; 1152 } 1153 1154 if (chip->info->ops->set_cascade_port) { 1155 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1156 err = chip->info->ops->set_cascade_port(chip, port); 1157 if (err) 1158 return err; 1159 } 1160 1161 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1162 if (err) 1163 return err; 1164 1165 return 0; 1166 } 1167 1168 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1169 { 1170 /* Clear all trunk masks and mapping */ 1171 if (chip->info->global2_addr) 1172 return mv88e6xxx_g2_trunk_clear(chip); 1173 1174 return 0; 1175 } 1176 1177 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1178 { 1179 if (chip->info->ops->rmu_disable) 1180 return chip->info->ops->rmu_disable(chip); 1181 1182 return 0; 1183 } 1184 1185 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1186 { 1187 if (chip->info->ops->pot_clear) 1188 return chip->info->ops->pot_clear(chip); 1189 1190 return 0; 1191 } 1192 1193 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1194 { 1195 if (chip->info->ops->mgmt_rsvd2cpu) 1196 return chip->info->ops->mgmt_rsvd2cpu(chip); 1197 1198 return 0; 1199 } 1200 1201 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1202 { 1203 int err; 1204 1205 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1206 if (err) 1207 return err; 1208 1209 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1210 if (err) 1211 return err; 1212 1213 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1214 } 1215 1216 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1217 { 1218 int port; 1219 int err; 1220 1221 if (!chip->info->ops->irl_init_all) 1222 return 0; 1223 1224 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1225 /* Disable ingress rate limiting by resetting all per port 1226 * ingress rate limit resources to their initial state. 1227 */ 1228 err = chip->info->ops->irl_init_all(chip, port); 1229 if (err) 1230 return err; 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1237 { 1238 if (chip->info->ops->set_switch_mac) { 1239 u8 addr[ETH_ALEN]; 1240 1241 eth_random_addr(addr); 1242 1243 return chip->info->ops->set_switch_mac(chip, addr); 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1250 { 1251 u16 pvlan = 0; 1252 1253 if (!mv88e6xxx_has_pvt(chip)) 1254 return -EOPNOTSUPP; 1255 1256 /* Skip the local source device, which uses in-chip port VLAN */ 1257 if (dev != chip->ds->index) 1258 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1259 1260 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1261 } 1262 1263 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1264 { 1265 int dev, port; 1266 int err; 1267 1268 if (!mv88e6xxx_has_pvt(chip)) 1269 return 0; 1270 1271 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1272 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1273 */ 1274 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1275 if (err) 1276 return err; 1277 1278 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1279 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1280 err = mv88e6xxx_pvt_map(chip, dev, port); 1281 if (err) 1282 return err; 1283 } 1284 } 1285 1286 return 0; 1287 } 1288 1289 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1290 { 1291 struct mv88e6xxx_chip *chip = ds->priv; 1292 int err; 1293 1294 mv88e6xxx_reg_lock(chip); 1295 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1296 mv88e6xxx_reg_unlock(chip); 1297 1298 if (err) 1299 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1300 } 1301 1302 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1303 { 1304 if (!chip->info->max_vid) 1305 return 0; 1306 1307 return mv88e6xxx_g1_vtu_flush(chip); 1308 } 1309 1310 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1311 struct mv88e6xxx_vtu_entry *entry) 1312 { 1313 if (!chip->info->ops->vtu_getnext) 1314 return -EOPNOTSUPP; 1315 1316 return chip->info->ops->vtu_getnext(chip, entry); 1317 } 1318 1319 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1320 struct mv88e6xxx_vtu_entry *entry) 1321 { 1322 if (!chip->info->ops->vtu_loadpurge) 1323 return -EOPNOTSUPP; 1324 1325 return chip->info->ops->vtu_loadpurge(chip, entry); 1326 } 1327 1328 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1329 { 1330 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1331 struct mv88e6xxx_vtu_entry vlan; 1332 int i, err; 1333 1334 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1335 1336 /* Set every FID bit used by the (un)bridged ports */ 1337 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1338 err = mv88e6xxx_port_get_fid(chip, i, fid); 1339 if (err) 1340 return err; 1341 1342 set_bit(*fid, fid_bitmap); 1343 } 1344 1345 /* Set every FID bit used by the VLAN entries */ 1346 vlan.vid = chip->info->max_vid; 1347 vlan.valid = false; 1348 1349 do { 1350 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1351 if (err) 1352 return err; 1353 1354 if (!vlan.valid) 1355 break; 1356 1357 set_bit(vlan.fid, fid_bitmap); 1358 } while (vlan.vid < chip->info->max_vid); 1359 1360 /* The reset value 0x000 is used to indicate that multiple address 1361 * databases are not needed. Return the next positive available. 1362 */ 1363 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1364 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1365 return -ENOSPC; 1366 1367 /* Clear the database */ 1368 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1369 } 1370 1371 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1372 u16 vid_begin, u16 vid_end) 1373 { 1374 struct mv88e6xxx_chip *chip = ds->priv; 1375 struct mv88e6xxx_vtu_entry vlan; 1376 int i, err; 1377 1378 /* DSA and CPU ports have to be members of multiple vlans */ 1379 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1380 return 0; 1381 1382 if (!vid_begin) 1383 return -EOPNOTSUPP; 1384 1385 vlan.vid = vid_begin - 1; 1386 vlan.valid = false; 1387 1388 do { 1389 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1390 if (err) 1391 return err; 1392 1393 if (!vlan.valid) 1394 break; 1395 1396 if (vlan.vid > vid_end) 1397 break; 1398 1399 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1400 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1401 continue; 1402 1403 if (!ds->ports[i].slave) 1404 continue; 1405 1406 if (vlan.member[i] == 1407 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1408 continue; 1409 1410 if (dsa_to_port(ds, i)->bridge_dev == 1411 ds->ports[port].bridge_dev) 1412 break; /* same bridge, check next VLAN */ 1413 1414 if (!dsa_to_port(ds, i)->bridge_dev) 1415 continue; 1416 1417 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1418 port, vlan.vid, i, 1419 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1420 return -EOPNOTSUPP; 1421 } 1422 } while (vlan.vid < vid_end); 1423 1424 return 0; 1425 } 1426 1427 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1428 bool vlan_filtering) 1429 { 1430 struct mv88e6xxx_chip *chip = ds->priv; 1431 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1432 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1433 int err; 1434 1435 if (!chip->info->max_vid) 1436 return -EOPNOTSUPP; 1437 1438 mv88e6xxx_reg_lock(chip); 1439 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1440 mv88e6xxx_reg_unlock(chip); 1441 1442 return err; 1443 } 1444 1445 static int 1446 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1447 const struct switchdev_obj_port_vlan *vlan) 1448 { 1449 struct mv88e6xxx_chip *chip = ds->priv; 1450 int err; 1451 1452 if (!chip->info->max_vid) 1453 return -EOPNOTSUPP; 1454 1455 /* If the requested port doesn't belong to the same bridge as the VLAN 1456 * members, do not support it (yet) and fallback to software VLAN. 1457 */ 1458 mv88e6xxx_reg_lock(chip); 1459 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1460 vlan->vid_end); 1461 mv88e6xxx_reg_unlock(chip); 1462 1463 /* We don't need any dynamic resource from the kernel (yet), 1464 * so skip the prepare phase. 1465 */ 1466 return err; 1467 } 1468 1469 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1470 const unsigned char *addr, u16 vid, 1471 u8 state) 1472 { 1473 struct mv88e6xxx_atu_entry entry; 1474 struct mv88e6xxx_vtu_entry vlan; 1475 u16 fid; 1476 int err; 1477 1478 /* Null VLAN ID corresponds to the port private database */ 1479 if (vid == 0) { 1480 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1481 if (err) 1482 return err; 1483 } else { 1484 vlan.vid = vid - 1; 1485 vlan.valid = false; 1486 1487 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1488 if (err) 1489 return err; 1490 1491 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1492 if (vlan.vid != vid || !vlan.valid) 1493 return -EOPNOTSUPP; 1494 1495 fid = vlan.fid; 1496 } 1497 1498 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1499 ether_addr_copy(entry.mac, addr); 1500 eth_addr_dec(entry.mac); 1501 1502 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1503 if (err) 1504 return err; 1505 1506 /* Initialize a fresh ATU entry if it isn't found */ 1507 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1508 !ether_addr_equal(entry.mac, addr)) { 1509 memset(&entry, 0, sizeof(entry)); 1510 ether_addr_copy(entry.mac, addr); 1511 } 1512 1513 /* Purge the ATU entry only if no port is using it anymore */ 1514 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1515 entry.portvec &= ~BIT(port); 1516 if (!entry.portvec) 1517 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1518 } else { 1519 entry.portvec |= BIT(port); 1520 entry.state = state; 1521 } 1522 1523 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1524 } 1525 1526 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1527 u16 vid) 1528 { 1529 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1530 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1531 1532 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1533 } 1534 1535 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1536 { 1537 int port; 1538 int err; 1539 1540 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1541 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1542 if (err) 1543 return err; 1544 } 1545 1546 return 0; 1547 } 1548 1549 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1550 u16 vid, u8 member) 1551 { 1552 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1553 struct mv88e6xxx_vtu_entry vlan; 1554 int i, err; 1555 1556 if (!vid) 1557 return -EOPNOTSUPP; 1558 1559 vlan.vid = vid - 1; 1560 vlan.valid = false; 1561 1562 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1563 if (err) 1564 return err; 1565 1566 if (vlan.vid != vid || !vlan.valid) { 1567 memset(&vlan, 0, sizeof(vlan)); 1568 1569 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1570 if (err) 1571 return err; 1572 1573 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1574 if (i == port) 1575 vlan.member[i] = member; 1576 else 1577 vlan.member[i] = non_member; 1578 1579 vlan.vid = vid; 1580 vlan.valid = true; 1581 1582 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1583 if (err) 1584 return err; 1585 1586 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1587 if (err) 1588 return err; 1589 } else if (vlan.member[port] != member) { 1590 vlan.member[port] = member; 1591 1592 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1593 if (err) 1594 return err; 1595 } else { 1596 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1597 port, vid); 1598 } 1599 1600 return 0; 1601 } 1602 1603 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1604 const struct switchdev_obj_port_vlan *vlan) 1605 { 1606 struct mv88e6xxx_chip *chip = ds->priv; 1607 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1608 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1609 u8 member; 1610 u16 vid; 1611 1612 if (!chip->info->max_vid) 1613 return; 1614 1615 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1616 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1617 else if (untagged) 1618 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1619 else 1620 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1621 1622 mv88e6xxx_reg_lock(chip); 1623 1624 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1625 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1626 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1627 vid, untagged ? 'u' : 't'); 1628 1629 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1630 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1631 vlan->vid_end); 1632 1633 mv88e6xxx_reg_unlock(chip); 1634 } 1635 1636 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1637 int port, u16 vid) 1638 { 1639 struct mv88e6xxx_vtu_entry vlan; 1640 int i, err; 1641 1642 if (!vid) 1643 return -EOPNOTSUPP; 1644 1645 vlan.vid = vid - 1; 1646 vlan.valid = false; 1647 1648 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1649 if (err) 1650 return err; 1651 1652 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1653 * tell switchdev that this VLAN is likely handled in software. 1654 */ 1655 if (vlan.vid != vid || !vlan.valid || 1656 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1657 return -EOPNOTSUPP; 1658 1659 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1660 1661 /* keep the VLAN unless all ports are excluded */ 1662 vlan.valid = false; 1663 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1664 if (vlan.member[i] != 1665 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1666 vlan.valid = true; 1667 break; 1668 } 1669 } 1670 1671 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1672 if (err) 1673 return err; 1674 1675 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1676 } 1677 1678 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1679 const struct switchdev_obj_port_vlan *vlan) 1680 { 1681 struct mv88e6xxx_chip *chip = ds->priv; 1682 u16 pvid, vid; 1683 int err = 0; 1684 1685 if (!chip->info->max_vid) 1686 return -EOPNOTSUPP; 1687 1688 mv88e6xxx_reg_lock(chip); 1689 1690 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1691 if (err) 1692 goto unlock; 1693 1694 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1695 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1696 if (err) 1697 goto unlock; 1698 1699 if (vid == pvid) { 1700 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1701 if (err) 1702 goto unlock; 1703 } 1704 } 1705 1706 unlock: 1707 mv88e6xxx_reg_unlock(chip); 1708 1709 return err; 1710 } 1711 1712 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1713 const unsigned char *addr, u16 vid) 1714 { 1715 struct mv88e6xxx_chip *chip = ds->priv; 1716 int err; 1717 1718 mv88e6xxx_reg_lock(chip); 1719 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1720 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1721 mv88e6xxx_reg_unlock(chip); 1722 1723 return err; 1724 } 1725 1726 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1727 const unsigned char *addr, u16 vid) 1728 { 1729 struct mv88e6xxx_chip *chip = ds->priv; 1730 int err; 1731 1732 mv88e6xxx_reg_lock(chip); 1733 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1734 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1735 mv88e6xxx_reg_unlock(chip); 1736 1737 return err; 1738 } 1739 1740 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1741 u16 fid, u16 vid, int port, 1742 dsa_fdb_dump_cb_t *cb, void *data) 1743 { 1744 struct mv88e6xxx_atu_entry addr; 1745 bool is_static; 1746 int err; 1747 1748 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1749 eth_broadcast_addr(addr.mac); 1750 1751 do { 1752 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1753 if (err) 1754 return err; 1755 1756 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1757 break; 1758 1759 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1760 continue; 1761 1762 if (!is_unicast_ether_addr(addr.mac)) 1763 continue; 1764 1765 is_static = (addr.state == 1766 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1767 err = cb(addr.mac, vid, is_static, data); 1768 if (err) 1769 return err; 1770 } while (!is_broadcast_ether_addr(addr.mac)); 1771 1772 return err; 1773 } 1774 1775 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1776 dsa_fdb_dump_cb_t *cb, void *data) 1777 { 1778 struct mv88e6xxx_vtu_entry vlan; 1779 u16 fid; 1780 int err; 1781 1782 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1783 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1784 if (err) 1785 return err; 1786 1787 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1788 if (err) 1789 return err; 1790 1791 /* Dump VLANs' Filtering Information Databases */ 1792 vlan.vid = chip->info->max_vid; 1793 vlan.valid = false; 1794 1795 do { 1796 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1797 if (err) 1798 return err; 1799 1800 if (!vlan.valid) 1801 break; 1802 1803 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1804 cb, data); 1805 if (err) 1806 return err; 1807 } while (vlan.vid < chip->info->max_vid); 1808 1809 return err; 1810 } 1811 1812 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1813 dsa_fdb_dump_cb_t *cb, void *data) 1814 { 1815 struct mv88e6xxx_chip *chip = ds->priv; 1816 int err; 1817 1818 mv88e6xxx_reg_lock(chip); 1819 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1820 mv88e6xxx_reg_unlock(chip); 1821 1822 return err; 1823 } 1824 1825 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1826 struct net_device *br) 1827 { 1828 struct dsa_switch *ds; 1829 int port; 1830 int dev; 1831 int err; 1832 1833 /* Remap the Port VLAN of each local bridge group member */ 1834 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1835 if (chip->ds->ports[port].bridge_dev == br) { 1836 err = mv88e6xxx_port_vlan_map(chip, port); 1837 if (err) 1838 return err; 1839 } 1840 } 1841 1842 if (!mv88e6xxx_has_pvt(chip)) 1843 return 0; 1844 1845 /* Remap the Port VLAN of each cross-chip bridge group member */ 1846 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1847 ds = chip->ds->dst->ds[dev]; 1848 if (!ds) 1849 break; 1850 1851 for (port = 0; port < ds->num_ports; ++port) { 1852 if (ds->ports[port].bridge_dev == br) { 1853 err = mv88e6xxx_pvt_map(chip, dev, port); 1854 if (err) 1855 return err; 1856 } 1857 } 1858 } 1859 1860 return 0; 1861 } 1862 1863 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1864 struct net_device *br) 1865 { 1866 struct mv88e6xxx_chip *chip = ds->priv; 1867 int err; 1868 1869 mv88e6xxx_reg_lock(chip); 1870 err = mv88e6xxx_bridge_map(chip, br); 1871 mv88e6xxx_reg_unlock(chip); 1872 1873 return err; 1874 } 1875 1876 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1877 struct net_device *br) 1878 { 1879 struct mv88e6xxx_chip *chip = ds->priv; 1880 1881 mv88e6xxx_reg_lock(chip); 1882 if (mv88e6xxx_bridge_map(chip, br) || 1883 mv88e6xxx_port_vlan_map(chip, port)) 1884 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1885 mv88e6xxx_reg_unlock(chip); 1886 } 1887 1888 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1889 int port, struct net_device *br) 1890 { 1891 struct mv88e6xxx_chip *chip = ds->priv; 1892 int err; 1893 1894 if (!mv88e6xxx_has_pvt(chip)) 1895 return 0; 1896 1897 mv88e6xxx_reg_lock(chip); 1898 err = mv88e6xxx_pvt_map(chip, dev, port); 1899 mv88e6xxx_reg_unlock(chip); 1900 1901 return err; 1902 } 1903 1904 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1905 int port, struct net_device *br) 1906 { 1907 struct mv88e6xxx_chip *chip = ds->priv; 1908 1909 if (!mv88e6xxx_has_pvt(chip)) 1910 return; 1911 1912 mv88e6xxx_reg_lock(chip); 1913 if (mv88e6xxx_pvt_map(chip, dev, port)) 1914 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1915 mv88e6xxx_reg_unlock(chip); 1916 } 1917 1918 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1919 { 1920 if (chip->info->ops->reset) 1921 return chip->info->ops->reset(chip); 1922 1923 return 0; 1924 } 1925 1926 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1927 { 1928 struct gpio_desc *gpiod = chip->reset; 1929 1930 /* If there is a GPIO connected to the reset pin, toggle it */ 1931 if (gpiod) { 1932 gpiod_set_value_cansleep(gpiod, 1); 1933 usleep_range(10000, 20000); 1934 gpiod_set_value_cansleep(gpiod, 0); 1935 usleep_range(10000, 20000); 1936 } 1937 } 1938 1939 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1940 { 1941 int i, err; 1942 1943 /* Set all ports to the Disabled state */ 1944 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1945 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1946 if (err) 1947 return err; 1948 } 1949 1950 /* Wait for transmit queues to drain, 1951 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1952 */ 1953 usleep_range(2000, 4000); 1954 1955 return 0; 1956 } 1957 1958 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1959 { 1960 int err; 1961 1962 err = mv88e6xxx_disable_ports(chip); 1963 if (err) 1964 return err; 1965 1966 mv88e6xxx_hardware_reset(chip); 1967 1968 return mv88e6xxx_software_reset(chip); 1969 } 1970 1971 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1972 enum mv88e6xxx_frame_mode frame, 1973 enum mv88e6xxx_egress_mode egress, u16 etype) 1974 { 1975 int err; 1976 1977 if (!chip->info->ops->port_set_frame_mode) 1978 return -EOPNOTSUPP; 1979 1980 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1981 if (err) 1982 return err; 1983 1984 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1985 if (err) 1986 return err; 1987 1988 if (chip->info->ops->port_set_ether_type) 1989 return chip->info->ops->port_set_ether_type(chip, port, etype); 1990 1991 return 0; 1992 } 1993 1994 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1995 { 1996 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1997 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1998 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1999 } 2000 2001 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2002 { 2003 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2004 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2005 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2006 } 2007 2008 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2009 { 2010 return mv88e6xxx_set_port_mode(chip, port, 2011 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2012 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2013 ETH_P_EDSA); 2014 } 2015 2016 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2017 { 2018 if (dsa_is_dsa_port(chip->ds, port)) 2019 return mv88e6xxx_set_port_mode_dsa(chip, port); 2020 2021 if (dsa_is_user_port(chip->ds, port)) 2022 return mv88e6xxx_set_port_mode_normal(chip, port); 2023 2024 /* Setup CPU port mode depending on its supported tag format */ 2025 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2026 return mv88e6xxx_set_port_mode_dsa(chip, port); 2027 2028 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2029 return mv88e6xxx_set_port_mode_edsa(chip, port); 2030 2031 return -EINVAL; 2032 } 2033 2034 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2035 { 2036 bool message = dsa_is_dsa_port(chip->ds, port); 2037 2038 return mv88e6xxx_port_set_message_port(chip, port, message); 2039 } 2040 2041 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2042 { 2043 struct dsa_switch *ds = chip->ds; 2044 bool flood; 2045 2046 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2047 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2048 if (chip->info->ops->port_set_egress_floods) 2049 return chip->info->ops->port_set_egress_floods(chip, port, 2050 flood, flood); 2051 2052 return 0; 2053 } 2054 2055 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2056 bool on) 2057 { 2058 if (chip->info->ops->serdes_power) 2059 return chip->info->ops->serdes_power(chip, port, on); 2060 2061 return 0; 2062 } 2063 2064 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2065 { 2066 struct dsa_switch *ds = chip->ds; 2067 int upstream_port; 2068 int err; 2069 2070 upstream_port = dsa_upstream_port(ds, port); 2071 if (chip->info->ops->port_set_upstream_port) { 2072 err = chip->info->ops->port_set_upstream_port(chip, port, 2073 upstream_port); 2074 if (err) 2075 return err; 2076 } 2077 2078 if (port == upstream_port) { 2079 if (chip->info->ops->set_cpu_port) { 2080 err = chip->info->ops->set_cpu_port(chip, 2081 upstream_port); 2082 if (err) 2083 return err; 2084 } 2085 2086 if (chip->info->ops->set_egress_port) { 2087 err = chip->info->ops->set_egress_port(chip, 2088 upstream_port); 2089 if (err) 2090 return err; 2091 } 2092 } 2093 2094 return 0; 2095 } 2096 2097 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2098 { 2099 struct dsa_switch *ds = chip->ds; 2100 int err; 2101 u16 reg; 2102 2103 chip->ports[port].chip = chip; 2104 chip->ports[port].port = port; 2105 2106 /* MAC Forcing register: don't force link, speed, duplex or flow control 2107 * state to any particular values on physical ports, but force the CPU 2108 * port and all DSA ports to their maximum bandwidth and full duplex. 2109 */ 2110 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2111 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2112 SPEED_MAX, DUPLEX_FULL, 2113 PAUSE_OFF, 2114 PHY_INTERFACE_MODE_NA); 2115 else 2116 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2117 SPEED_UNFORCED, DUPLEX_UNFORCED, 2118 PAUSE_ON, 2119 PHY_INTERFACE_MODE_NA); 2120 if (err) 2121 return err; 2122 2123 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2124 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2125 * tunneling, determine priority by looking at 802.1p and IP 2126 * priority fields (IP prio has precedence), and set STP state 2127 * to Forwarding. 2128 * 2129 * If this is the CPU link, use DSA or EDSA tagging depending 2130 * on which tagging mode was configured. 2131 * 2132 * If this is a link to another switch, use DSA tagging mode. 2133 * 2134 * If this is the upstream port for this switch, enable 2135 * forwarding of unknown unicasts and multicasts. 2136 */ 2137 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2138 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2139 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2140 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2141 if (err) 2142 return err; 2143 2144 err = mv88e6xxx_setup_port_mode(chip, port); 2145 if (err) 2146 return err; 2147 2148 err = mv88e6xxx_setup_egress_floods(chip, port); 2149 if (err) 2150 return err; 2151 2152 /* Enable the SERDES interface for DSA and CPU ports. Normal 2153 * ports SERDES are enabled when the port is enabled, thus 2154 * saving a bit of power. 2155 */ 2156 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2157 err = mv88e6xxx_serdes_power(chip, port, true); 2158 if (err) 2159 return err; 2160 } 2161 2162 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2163 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2164 * untagged frames on this port, do a destination address lookup on all 2165 * received packets as usual, disable ARP mirroring and don't send a 2166 * copy of all transmitted/received frames on this port to the CPU. 2167 */ 2168 err = mv88e6xxx_port_set_map_da(chip, port); 2169 if (err) 2170 return err; 2171 2172 err = mv88e6xxx_setup_upstream_port(chip, port); 2173 if (err) 2174 return err; 2175 2176 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2177 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2178 if (err) 2179 return err; 2180 2181 if (chip->info->ops->port_set_jumbo_size) { 2182 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2183 if (err) 2184 return err; 2185 } 2186 2187 /* Port Association Vector: when learning source addresses 2188 * of packets, add the address to the address database using 2189 * a port bitmap that has only the bit for this port set and 2190 * the other bits clear. 2191 */ 2192 reg = 1 << port; 2193 /* Disable learning for CPU port */ 2194 if (dsa_is_cpu_port(ds, port)) 2195 reg = 0; 2196 2197 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2198 reg); 2199 if (err) 2200 return err; 2201 2202 /* Egress rate control 2: disable egress rate control. */ 2203 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2204 0x0000); 2205 if (err) 2206 return err; 2207 2208 if (chip->info->ops->port_pause_limit) { 2209 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2210 if (err) 2211 return err; 2212 } 2213 2214 if (chip->info->ops->port_disable_learn_limit) { 2215 err = chip->info->ops->port_disable_learn_limit(chip, port); 2216 if (err) 2217 return err; 2218 } 2219 2220 if (chip->info->ops->port_disable_pri_override) { 2221 err = chip->info->ops->port_disable_pri_override(chip, port); 2222 if (err) 2223 return err; 2224 } 2225 2226 if (chip->info->ops->port_tag_remap) { 2227 err = chip->info->ops->port_tag_remap(chip, port); 2228 if (err) 2229 return err; 2230 } 2231 2232 if (chip->info->ops->port_egress_rate_limiting) { 2233 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2234 if (err) 2235 return err; 2236 } 2237 2238 if (chip->info->ops->port_setup_message_port) { 2239 err = chip->info->ops->port_setup_message_port(chip, port); 2240 if (err) 2241 return err; 2242 } 2243 2244 /* Port based VLAN map: give each port the same default address 2245 * database, and allow bidirectional communication between the 2246 * CPU and DSA port(s), and the other ports. 2247 */ 2248 err = mv88e6xxx_port_set_fid(chip, port, 0); 2249 if (err) 2250 return err; 2251 2252 err = mv88e6xxx_port_vlan_map(chip, port); 2253 if (err) 2254 return err; 2255 2256 /* Default VLAN ID and priority: don't set a default VLAN 2257 * ID, and set the default packet priority to zero. 2258 */ 2259 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2260 } 2261 2262 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2263 struct phy_device *phydev) 2264 { 2265 struct mv88e6xxx_chip *chip = ds->priv; 2266 int err; 2267 2268 mv88e6xxx_reg_lock(chip); 2269 2270 err = mv88e6xxx_serdes_power(chip, port, true); 2271 2272 if (!err && chip->info->ops->serdes_irq_setup) 2273 err = chip->info->ops->serdes_irq_setup(chip, port); 2274 2275 mv88e6xxx_reg_unlock(chip); 2276 2277 return err; 2278 } 2279 2280 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2281 { 2282 struct mv88e6xxx_chip *chip = ds->priv; 2283 2284 mv88e6xxx_reg_lock(chip); 2285 2286 if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED)) 2287 dev_err(chip->dev, "failed to disable port\n"); 2288 2289 if (chip->info->ops->serdes_irq_free) 2290 chip->info->ops->serdes_irq_free(chip, port); 2291 2292 if (mv88e6xxx_serdes_power(chip, port, false)) 2293 dev_err(chip->dev, "failed to power off SERDES\n"); 2294 2295 mv88e6xxx_reg_unlock(chip); 2296 } 2297 2298 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2299 unsigned int ageing_time) 2300 { 2301 struct mv88e6xxx_chip *chip = ds->priv; 2302 int err; 2303 2304 mv88e6xxx_reg_lock(chip); 2305 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2306 mv88e6xxx_reg_unlock(chip); 2307 2308 return err; 2309 } 2310 2311 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2312 { 2313 int err; 2314 2315 /* Initialize the statistics unit */ 2316 if (chip->info->ops->stats_set_histogram) { 2317 err = chip->info->ops->stats_set_histogram(chip); 2318 if (err) 2319 return err; 2320 } 2321 2322 return mv88e6xxx_g1_stats_clear(chip); 2323 } 2324 2325 /* The mv88e6390 has some hidden registers used for debug and 2326 * development. The errata also makes use of them. 2327 */ 2328 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2329 int reg, u16 val) 2330 { 2331 u16 ctrl; 2332 int err; 2333 2334 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2335 PORT_RESERVED_1A, val); 2336 if (err) 2337 return err; 2338 2339 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2340 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2341 reg; 2342 2343 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2344 PORT_RESERVED_1A, ctrl); 2345 } 2346 2347 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2348 { 2349 int bit = __bf_shf(PORT_RESERVED_1A_BUSY); 2350 2351 return mv88e6xxx_wait_bit(chip, PORT_RESERVED_1A_CTRL_PORT, 2352 PORT_RESERVED_1A, bit, 0); 2353 } 2354 2355 2356 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2357 int reg, u16 *val) 2358 { 2359 u16 ctrl; 2360 int err; 2361 2362 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2363 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2364 reg; 2365 2366 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2367 PORT_RESERVED_1A, ctrl); 2368 if (err) 2369 return err; 2370 2371 err = mv88e6390_hidden_wait(chip); 2372 if (err) 2373 return err; 2374 2375 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2376 PORT_RESERVED_1A, val); 2377 } 2378 2379 /* Check if the errata has already been applied. */ 2380 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2381 { 2382 int port; 2383 int err; 2384 u16 val; 2385 2386 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2387 err = mv88e6390_hidden_read(chip, port, 0, &val); 2388 if (err) { 2389 dev_err(chip->dev, 2390 "Error reading hidden register: %d\n", err); 2391 return false; 2392 } 2393 if (val != 0x01c0) 2394 return false; 2395 } 2396 2397 return true; 2398 } 2399 2400 /* The 6390 copper ports have an errata which require poking magic 2401 * values into undocumented hidden registers and then performing a 2402 * software reset. 2403 */ 2404 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2405 { 2406 int port; 2407 int err; 2408 2409 if (mv88e6390_setup_errata_applied(chip)) 2410 return 0; 2411 2412 /* Set the ports into blocking mode */ 2413 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2414 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2415 if (err) 2416 return err; 2417 } 2418 2419 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2420 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2421 if (err) 2422 return err; 2423 } 2424 2425 return mv88e6xxx_software_reset(chip); 2426 } 2427 2428 static int mv88e6xxx_setup(struct dsa_switch *ds) 2429 { 2430 struct mv88e6xxx_chip *chip = ds->priv; 2431 u8 cmode; 2432 int err; 2433 int i; 2434 2435 chip->ds = ds; 2436 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2437 2438 mv88e6xxx_reg_lock(chip); 2439 2440 if (chip->info->ops->setup_errata) { 2441 err = chip->info->ops->setup_errata(chip); 2442 if (err) 2443 goto unlock; 2444 } 2445 2446 /* Cache the cmode of each port. */ 2447 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2448 if (chip->info->ops->port_get_cmode) { 2449 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2450 if (err) 2451 goto unlock; 2452 2453 chip->ports[i].cmode = cmode; 2454 } 2455 } 2456 2457 /* Setup Switch Port Registers */ 2458 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2459 /* Prevent the use of an invalid port. */ 2460 if (mv88e6xxx_is_invalid_port(chip, i) && 2461 !dsa_is_unused_port(ds, i)) { 2462 dev_err(chip->dev, "port %d is invalid\n", i); 2463 err = -EINVAL; 2464 goto unlock; 2465 } 2466 2467 if (dsa_is_unused_port(ds, i)) { 2468 err = mv88e6xxx_port_set_state(chip, i, 2469 BR_STATE_DISABLED); 2470 if (err) 2471 goto unlock; 2472 2473 err = mv88e6xxx_serdes_power(chip, i, false); 2474 if (err) 2475 goto unlock; 2476 2477 continue; 2478 } 2479 2480 err = mv88e6xxx_setup_port(chip, i); 2481 if (err) 2482 goto unlock; 2483 } 2484 2485 err = mv88e6xxx_irl_setup(chip); 2486 if (err) 2487 goto unlock; 2488 2489 err = mv88e6xxx_mac_setup(chip); 2490 if (err) 2491 goto unlock; 2492 2493 err = mv88e6xxx_phy_setup(chip); 2494 if (err) 2495 goto unlock; 2496 2497 err = mv88e6xxx_vtu_setup(chip); 2498 if (err) 2499 goto unlock; 2500 2501 err = mv88e6xxx_pvt_setup(chip); 2502 if (err) 2503 goto unlock; 2504 2505 err = mv88e6xxx_atu_setup(chip); 2506 if (err) 2507 goto unlock; 2508 2509 err = mv88e6xxx_broadcast_setup(chip, 0); 2510 if (err) 2511 goto unlock; 2512 2513 err = mv88e6xxx_pot_setup(chip); 2514 if (err) 2515 goto unlock; 2516 2517 err = mv88e6xxx_rmu_setup(chip); 2518 if (err) 2519 goto unlock; 2520 2521 err = mv88e6xxx_rsvd2cpu_setup(chip); 2522 if (err) 2523 goto unlock; 2524 2525 err = mv88e6xxx_trunk_setup(chip); 2526 if (err) 2527 goto unlock; 2528 2529 err = mv88e6xxx_devmap_setup(chip); 2530 if (err) 2531 goto unlock; 2532 2533 err = mv88e6xxx_pri_setup(chip); 2534 if (err) 2535 goto unlock; 2536 2537 /* Setup PTP Hardware Clock and timestamping */ 2538 if (chip->info->ptp_support) { 2539 err = mv88e6xxx_ptp_setup(chip); 2540 if (err) 2541 goto unlock; 2542 2543 err = mv88e6xxx_hwtstamp_setup(chip); 2544 if (err) 2545 goto unlock; 2546 } 2547 2548 err = mv88e6xxx_stats_setup(chip); 2549 if (err) 2550 goto unlock; 2551 2552 unlock: 2553 mv88e6xxx_reg_unlock(chip); 2554 2555 return err; 2556 } 2557 2558 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2559 { 2560 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2561 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2562 u16 val; 2563 int err; 2564 2565 if (!chip->info->ops->phy_read) 2566 return -EOPNOTSUPP; 2567 2568 mv88e6xxx_reg_lock(chip); 2569 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2570 mv88e6xxx_reg_unlock(chip); 2571 2572 if (reg == MII_PHYSID2) { 2573 /* Some internal PHYs don't have a model number. */ 2574 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2575 /* Then there is the 6165 family. It gets is 2576 * PHYs correct. But it can also have two 2577 * SERDES interfaces in the PHY address 2578 * space. And these don't have a model 2579 * number. But they are not PHYs, so we don't 2580 * want to give them something a PHY driver 2581 * will recognise. 2582 * 2583 * Use the mv88e6390 family model number 2584 * instead, for anything which really could be 2585 * a PHY, 2586 */ 2587 if (!(val & 0x3f0)) 2588 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2589 } 2590 2591 return err ? err : val; 2592 } 2593 2594 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2595 { 2596 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2597 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2598 int err; 2599 2600 if (!chip->info->ops->phy_write) 2601 return -EOPNOTSUPP; 2602 2603 mv88e6xxx_reg_lock(chip); 2604 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2605 mv88e6xxx_reg_unlock(chip); 2606 2607 return err; 2608 } 2609 2610 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2611 struct device_node *np, 2612 bool external) 2613 { 2614 static int index; 2615 struct mv88e6xxx_mdio_bus *mdio_bus; 2616 struct mii_bus *bus; 2617 int err; 2618 2619 if (external) { 2620 mv88e6xxx_reg_lock(chip); 2621 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2622 mv88e6xxx_reg_unlock(chip); 2623 2624 if (err) 2625 return err; 2626 } 2627 2628 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2629 if (!bus) 2630 return -ENOMEM; 2631 2632 mdio_bus = bus->priv; 2633 mdio_bus->bus = bus; 2634 mdio_bus->chip = chip; 2635 INIT_LIST_HEAD(&mdio_bus->list); 2636 mdio_bus->external = external; 2637 2638 if (np) { 2639 bus->name = np->full_name; 2640 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2641 } else { 2642 bus->name = "mv88e6xxx SMI"; 2643 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2644 } 2645 2646 bus->read = mv88e6xxx_mdio_read; 2647 bus->write = mv88e6xxx_mdio_write; 2648 bus->parent = chip->dev; 2649 2650 if (!external) { 2651 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2652 if (err) 2653 return err; 2654 } 2655 2656 err = of_mdiobus_register(bus, np); 2657 if (err) { 2658 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2659 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2660 return err; 2661 } 2662 2663 if (external) 2664 list_add_tail(&mdio_bus->list, &chip->mdios); 2665 else 2666 list_add(&mdio_bus->list, &chip->mdios); 2667 2668 return 0; 2669 } 2670 2671 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2672 { .compatible = "marvell,mv88e6xxx-mdio-external", 2673 .data = (void *)true }, 2674 { }, 2675 }; 2676 2677 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2678 2679 { 2680 struct mv88e6xxx_mdio_bus *mdio_bus; 2681 struct mii_bus *bus; 2682 2683 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2684 bus = mdio_bus->bus; 2685 2686 if (!mdio_bus->external) 2687 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2688 2689 mdiobus_unregister(bus); 2690 } 2691 } 2692 2693 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2694 struct device_node *np) 2695 { 2696 const struct of_device_id *match; 2697 struct device_node *child; 2698 int err; 2699 2700 /* Always register one mdio bus for the internal/default mdio 2701 * bus. This maybe represented in the device tree, but is 2702 * optional. 2703 */ 2704 child = of_get_child_by_name(np, "mdio"); 2705 err = mv88e6xxx_mdio_register(chip, child, false); 2706 if (err) 2707 return err; 2708 2709 /* Walk the device tree, and see if there are any other nodes 2710 * which say they are compatible with the external mdio 2711 * bus. 2712 */ 2713 for_each_available_child_of_node(np, child) { 2714 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2715 if (match) { 2716 err = mv88e6xxx_mdio_register(chip, child, true); 2717 if (err) { 2718 mv88e6xxx_mdios_unregister(chip); 2719 of_node_put(child); 2720 return err; 2721 } 2722 } 2723 } 2724 2725 return 0; 2726 } 2727 2728 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2729 { 2730 struct mv88e6xxx_chip *chip = ds->priv; 2731 2732 return chip->eeprom_len; 2733 } 2734 2735 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2736 struct ethtool_eeprom *eeprom, u8 *data) 2737 { 2738 struct mv88e6xxx_chip *chip = ds->priv; 2739 int err; 2740 2741 if (!chip->info->ops->get_eeprom) 2742 return -EOPNOTSUPP; 2743 2744 mv88e6xxx_reg_lock(chip); 2745 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2746 mv88e6xxx_reg_unlock(chip); 2747 2748 if (err) 2749 return err; 2750 2751 eeprom->magic = 0xc3ec4951; 2752 2753 return 0; 2754 } 2755 2756 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2757 struct ethtool_eeprom *eeprom, u8 *data) 2758 { 2759 struct mv88e6xxx_chip *chip = ds->priv; 2760 int err; 2761 2762 if (!chip->info->ops->set_eeprom) 2763 return -EOPNOTSUPP; 2764 2765 if (eeprom->magic != 0xc3ec4951) 2766 return -EINVAL; 2767 2768 mv88e6xxx_reg_lock(chip); 2769 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2770 mv88e6xxx_reg_unlock(chip); 2771 2772 return err; 2773 } 2774 2775 static const struct mv88e6xxx_ops mv88e6085_ops = { 2776 /* MV88E6XXX_FAMILY_6097 */ 2777 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2778 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2779 .irl_init_all = mv88e6352_g2_irl_init_all, 2780 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2781 .phy_read = mv88e6185_phy_ppu_read, 2782 .phy_write = mv88e6185_phy_ppu_write, 2783 .port_set_link = mv88e6xxx_port_set_link, 2784 .port_set_duplex = mv88e6xxx_port_set_duplex, 2785 .port_set_speed = mv88e6185_port_set_speed, 2786 .port_tag_remap = mv88e6095_port_tag_remap, 2787 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2788 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2789 .port_set_ether_type = mv88e6351_port_set_ether_type, 2790 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2791 .port_pause_limit = mv88e6097_port_pause_limit, 2792 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2793 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2794 .port_link_state = mv88e6352_port_link_state, 2795 .port_get_cmode = mv88e6185_port_get_cmode, 2796 .port_setup_message_port = mv88e6xxx_setup_message_port, 2797 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2798 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2799 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2800 .stats_get_strings = mv88e6095_stats_get_strings, 2801 .stats_get_stats = mv88e6095_stats_get_stats, 2802 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2803 .set_egress_port = mv88e6095_g1_set_egress_port, 2804 .watchdog_ops = &mv88e6097_watchdog_ops, 2805 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2806 .pot_clear = mv88e6xxx_g2_pot_clear, 2807 .ppu_enable = mv88e6185_g1_ppu_enable, 2808 .ppu_disable = mv88e6185_g1_ppu_disable, 2809 .reset = mv88e6185_g1_reset, 2810 .rmu_disable = mv88e6085_g1_rmu_disable, 2811 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2812 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2813 .phylink_validate = mv88e6185_phylink_validate, 2814 }; 2815 2816 static const struct mv88e6xxx_ops mv88e6095_ops = { 2817 /* MV88E6XXX_FAMILY_6095 */ 2818 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2819 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2820 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2821 .phy_read = mv88e6185_phy_ppu_read, 2822 .phy_write = mv88e6185_phy_ppu_write, 2823 .port_set_link = mv88e6xxx_port_set_link, 2824 .port_set_duplex = mv88e6xxx_port_set_duplex, 2825 .port_set_speed = mv88e6185_port_set_speed, 2826 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2827 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2828 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2829 .port_link_state = mv88e6185_port_link_state, 2830 .port_get_cmode = mv88e6185_port_get_cmode, 2831 .port_setup_message_port = mv88e6xxx_setup_message_port, 2832 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2833 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2834 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2835 .stats_get_strings = mv88e6095_stats_get_strings, 2836 .stats_get_stats = mv88e6095_stats_get_stats, 2837 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2838 .ppu_enable = mv88e6185_g1_ppu_enable, 2839 .ppu_disable = mv88e6185_g1_ppu_disable, 2840 .reset = mv88e6185_g1_reset, 2841 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2842 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2843 .phylink_validate = mv88e6185_phylink_validate, 2844 }; 2845 2846 static const struct mv88e6xxx_ops mv88e6097_ops = { 2847 /* MV88E6XXX_FAMILY_6097 */ 2848 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2849 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2850 .irl_init_all = mv88e6352_g2_irl_init_all, 2851 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2852 .phy_read = mv88e6xxx_g2_smi_phy_read, 2853 .phy_write = mv88e6xxx_g2_smi_phy_write, 2854 .port_set_link = mv88e6xxx_port_set_link, 2855 .port_set_duplex = mv88e6xxx_port_set_duplex, 2856 .port_set_speed = mv88e6185_port_set_speed, 2857 .port_tag_remap = mv88e6095_port_tag_remap, 2858 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2859 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2860 .port_set_ether_type = mv88e6351_port_set_ether_type, 2861 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2862 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2863 .port_pause_limit = mv88e6097_port_pause_limit, 2864 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2865 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2866 .port_link_state = mv88e6352_port_link_state, 2867 .port_get_cmode = mv88e6185_port_get_cmode, 2868 .port_setup_message_port = mv88e6xxx_setup_message_port, 2869 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2870 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2871 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2872 .stats_get_strings = mv88e6095_stats_get_strings, 2873 .stats_get_stats = mv88e6095_stats_get_stats, 2874 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2875 .set_egress_port = mv88e6095_g1_set_egress_port, 2876 .watchdog_ops = &mv88e6097_watchdog_ops, 2877 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2878 .pot_clear = mv88e6xxx_g2_pot_clear, 2879 .reset = mv88e6352_g1_reset, 2880 .rmu_disable = mv88e6085_g1_rmu_disable, 2881 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2882 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2883 .phylink_validate = mv88e6185_phylink_validate, 2884 }; 2885 2886 static const struct mv88e6xxx_ops mv88e6123_ops = { 2887 /* MV88E6XXX_FAMILY_6165 */ 2888 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2889 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2890 .irl_init_all = mv88e6352_g2_irl_init_all, 2891 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2892 .phy_read = mv88e6xxx_g2_smi_phy_read, 2893 .phy_write = mv88e6xxx_g2_smi_phy_write, 2894 .port_set_link = mv88e6xxx_port_set_link, 2895 .port_set_duplex = mv88e6xxx_port_set_duplex, 2896 .port_set_speed = mv88e6185_port_set_speed, 2897 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2898 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2901 .port_link_state = mv88e6352_port_link_state, 2902 .port_get_cmode = mv88e6185_port_get_cmode, 2903 .port_setup_message_port = mv88e6xxx_setup_message_port, 2904 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2905 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2906 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2907 .stats_get_strings = mv88e6095_stats_get_strings, 2908 .stats_get_stats = mv88e6095_stats_get_stats, 2909 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2910 .set_egress_port = mv88e6095_g1_set_egress_port, 2911 .watchdog_ops = &mv88e6097_watchdog_ops, 2912 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2913 .pot_clear = mv88e6xxx_g2_pot_clear, 2914 .reset = mv88e6352_g1_reset, 2915 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2916 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2917 .phylink_validate = mv88e6185_phylink_validate, 2918 }; 2919 2920 static const struct mv88e6xxx_ops mv88e6131_ops = { 2921 /* MV88E6XXX_FAMILY_6185 */ 2922 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2923 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2924 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2925 .phy_read = mv88e6185_phy_ppu_read, 2926 .phy_write = mv88e6185_phy_ppu_write, 2927 .port_set_link = mv88e6xxx_port_set_link, 2928 .port_set_duplex = mv88e6xxx_port_set_duplex, 2929 .port_set_speed = mv88e6185_port_set_speed, 2930 .port_tag_remap = mv88e6095_port_tag_remap, 2931 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2932 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2933 .port_set_ether_type = mv88e6351_port_set_ether_type, 2934 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2935 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2936 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2937 .port_pause_limit = mv88e6097_port_pause_limit, 2938 .port_set_pause = mv88e6185_port_set_pause, 2939 .port_link_state = mv88e6352_port_link_state, 2940 .port_get_cmode = mv88e6185_port_get_cmode, 2941 .port_setup_message_port = mv88e6xxx_setup_message_port, 2942 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2943 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2944 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2945 .stats_get_strings = mv88e6095_stats_get_strings, 2946 .stats_get_stats = mv88e6095_stats_get_stats, 2947 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2948 .set_egress_port = mv88e6095_g1_set_egress_port, 2949 .watchdog_ops = &mv88e6097_watchdog_ops, 2950 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2951 .ppu_enable = mv88e6185_g1_ppu_enable, 2952 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2953 .ppu_disable = mv88e6185_g1_ppu_disable, 2954 .reset = mv88e6185_g1_reset, 2955 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2956 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2957 .phylink_validate = mv88e6185_phylink_validate, 2958 }; 2959 2960 static const struct mv88e6xxx_ops mv88e6141_ops = { 2961 /* MV88E6XXX_FAMILY_6341 */ 2962 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2963 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2964 .irl_init_all = mv88e6352_g2_irl_init_all, 2965 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2966 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2967 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2968 .phy_read = mv88e6xxx_g2_smi_phy_read, 2969 .phy_write = mv88e6xxx_g2_smi_phy_write, 2970 .port_set_link = mv88e6xxx_port_set_link, 2971 .port_set_duplex = mv88e6xxx_port_set_duplex, 2972 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2973 .port_set_speed = mv88e6341_port_set_speed, 2974 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 2975 .port_tag_remap = mv88e6095_port_tag_remap, 2976 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2977 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2978 .port_set_ether_type = mv88e6351_port_set_ether_type, 2979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2981 .port_pause_limit = mv88e6097_port_pause_limit, 2982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2984 .port_link_state = mv88e6352_port_link_state, 2985 .port_get_cmode = mv88e6352_port_get_cmode, 2986 .port_setup_message_port = mv88e6xxx_setup_message_port, 2987 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2988 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2989 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2990 .stats_get_strings = mv88e6320_stats_get_strings, 2991 .stats_get_stats = mv88e6390_stats_get_stats, 2992 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2993 .set_egress_port = mv88e6390_g1_set_egress_port, 2994 .watchdog_ops = &mv88e6390_watchdog_ops, 2995 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2996 .pot_clear = mv88e6xxx_g2_pot_clear, 2997 .reset = mv88e6352_g1_reset, 2998 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2999 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3000 .serdes_power = mv88e6341_serdes_power, 3001 .gpio_ops = &mv88e6352_gpio_ops, 3002 .phylink_validate = mv88e6341_phylink_validate, 3003 }; 3004 3005 static const struct mv88e6xxx_ops mv88e6161_ops = { 3006 /* MV88E6XXX_FAMILY_6165 */ 3007 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3008 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3009 .irl_init_all = mv88e6352_g2_irl_init_all, 3010 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3011 .phy_read = mv88e6xxx_g2_smi_phy_read, 3012 .phy_write = mv88e6xxx_g2_smi_phy_write, 3013 .port_set_link = mv88e6xxx_port_set_link, 3014 .port_set_duplex = mv88e6xxx_port_set_duplex, 3015 .port_set_speed = mv88e6185_port_set_speed, 3016 .port_tag_remap = mv88e6095_port_tag_remap, 3017 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3018 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3019 .port_set_ether_type = mv88e6351_port_set_ether_type, 3020 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3021 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3022 .port_pause_limit = mv88e6097_port_pause_limit, 3023 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3024 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3025 .port_link_state = mv88e6352_port_link_state, 3026 .port_get_cmode = mv88e6185_port_get_cmode, 3027 .port_setup_message_port = mv88e6xxx_setup_message_port, 3028 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3029 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3030 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3031 .stats_get_strings = mv88e6095_stats_get_strings, 3032 .stats_get_stats = mv88e6095_stats_get_stats, 3033 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3034 .set_egress_port = mv88e6095_g1_set_egress_port, 3035 .watchdog_ops = &mv88e6097_watchdog_ops, 3036 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3037 .pot_clear = mv88e6xxx_g2_pot_clear, 3038 .reset = mv88e6352_g1_reset, 3039 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3040 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3041 .avb_ops = &mv88e6165_avb_ops, 3042 .ptp_ops = &mv88e6165_ptp_ops, 3043 .phylink_validate = mv88e6185_phylink_validate, 3044 }; 3045 3046 static const struct mv88e6xxx_ops mv88e6165_ops = { 3047 /* MV88E6XXX_FAMILY_6165 */ 3048 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3049 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3050 .irl_init_all = mv88e6352_g2_irl_init_all, 3051 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3052 .phy_read = mv88e6165_phy_read, 3053 .phy_write = mv88e6165_phy_write, 3054 .port_set_link = mv88e6xxx_port_set_link, 3055 .port_set_duplex = mv88e6xxx_port_set_duplex, 3056 .port_set_speed = mv88e6185_port_set_speed, 3057 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3058 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3059 .port_link_state = mv88e6352_port_link_state, 3060 .port_get_cmode = mv88e6185_port_get_cmode, 3061 .port_setup_message_port = mv88e6xxx_setup_message_port, 3062 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3063 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3064 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3065 .stats_get_strings = mv88e6095_stats_get_strings, 3066 .stats_get_stats = mv88e6095_stats_get_stats, 3067 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3068 .set_egress_port = mv88e6095_g1_set_egress_port, 3069 .watchdog_ops = &mv88e6097_watchdog_ops, 3070 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3071 .pot_clear = mv88e6xxx_g2_pot_clear, 3072 .reset = mv88e6352_g1_reset, 3073 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3074 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3075 .avb_ops = &mv88e6165_avb_ops, 3076 .ptp_ops = &mv88e6165_ptp_ops, 3077 .phylink_validate = mv88e6185_phylink_validate, 3078 }; 3079 3080 static const struct mv88e6xxx_ops mv88e6171_ops = { 3081 /* MV88E6XXX_FAMILY_6351 */ 3082 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3083 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3084 .irl_init_all = mv88e6352_g2_irl_init_all, 3085 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3086 .phy_read = mv88e6xxx_g2_smi_phy_read, 3087 .phy_write = mv88e6xxx_g2_smi_phy_write, 3088 .port_set_link = mv88e6xxx_port_set_link, 3089 .port_set_duplex = mv88e6xxx_port_set_duplex, 3090 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3091 .port_set_speed = mv88e6185_port_set_speed, 3092 .port_tag_remap = mv88e6095_port_tag_remap, 3093 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3094 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3095 .port_set_ether_type = mv88e6351_port_set_ether_type, 3096 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3097 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3098 .port_pause_limit = mv88e6097_port_pause_limit, 3099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3101 .port_link_state = mv88e6352_port_link_state, 3102 .port_get_cmode = mv88e6352_port_get_cmode, 3103 .port_setup_message_port = mv88e6xxx_setup_message_port, 3104 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3105 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3106 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3107 .stats_get_strings = mv88e6095_stats_get_strings, 3108 .stats_get_stats = mv88e6095_stats_get_stats, 3109 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3110 .set_egress_port = mv88e6095_g1_set_egress_port, 3111 .watchdog_ops = &mv88e6097_watchdog_ops, 3112 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3113 .pot_clear = mv88e6xxx_g2_pot_clear, 3114 .reset = mv88e6352_g1_reset, 3115 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3116 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3117 .phylink_validate = mv88e6185_phylink_validate, 3118 }; 3119 3120 static const struct mv88e6xxx_ops mv88e6172_ops = { 3121 /* MV88E6XXX_FAMILY_6352 */ 3122 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3123 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3124 .irl_init_all = mv88e6352_g2_irl_init_all, 3125 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3126 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3127 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3128 .phy_read = mv88e6xxx_g2_smi_phy_read, 3129 .phy_write = mv88e6xxx_g2_smi_phy_write, 3130 .port_set_link = mv88e6xxx_port_set_link, 3131 .port_set_duplex = mv88e6xxx_port_set_duplex, 3132 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3133 .port_set_speed = mv88e6352_port_set_speed, 3134 .port_tag_remap = mv88e6095_port_tag_remap, 3135 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3136 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3137 .port_set_ether_type = mv88e6351_port_set_ether_type, 3138 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3139 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3140 .port_pause_limit = mv88e6097_port_pause_limit, 3141 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3142 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3143 .port_link_state = mv88e6352_port_link_state, 3144 .port_get_cmode = mv88e6352_port_get_cmode, 3145 .port_setup_message_port = mv88e6xxx_setup_message_port, 3146 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3147 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3148 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3149 .stats_get_strings = mv88e6095_stats_get_strings, 3150 .stats_get_stats = mv88e6095_stats_get_stats, 3151 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3152 .set_egress_port = mv88e6095_g1_set_egress_port, 3153 .watchdog_ops = &mv88e6097_watchdog_ops, 3154 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3155 .pot_clear = mv88e6xxx_g2_pot_clear, 3156 .reset = mv88e6352_g1_reset, 3157 .rmu_disable = mv88e6352_g1_rmu_disable, 3158 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3159 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3160 .serdes_power = mv88e6352_serdes_power, 3161 .gpio_ops = &mv88e6352_gpio_ops, 3162 .phylink_validate = mv88e6352_phylink_validate, 3163 }; 3164 3165 static const struct mv88e6xxx_ops mv88e6175_ops = { 3166 /* MV88E6XXX_FAMILY_6351 */ 3167 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3168 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3169 .irl_init_all = mv88e6352_g2_irl_init_all, 3170 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3171 .phy_read = mv88e6xxx_g2_smi_phy_read, 3172 .phy_write = mv88e6xxx_g2_smi_phy_write, 3173 .port_set_link = mv88e6xxx_port_set_link, 3174 .port_set_duplex = mv88e6xxx_port_set_duplex, 3175 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3176 .port_set_speed = mv88e6185_port_set_speed, 3177 .port_tag_remap = mv88e6095_port_tag_remap, 3178 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3179 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3180 .port_set_ether_type = mv88e6351_port_set_ether_type, 3181 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3182 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3183 .port_pause_limit = mv88e6097_port_pause_limit, 3184 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3185 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3186 .port_link_state = mv88e6352_port_link_state, 3187 .port_get_cmode = mv88e6352_port_get_cmode, 3188 .port_setup_message_port = mv88e6xxx_setup_message_port, 3189 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3190 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3191 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3192 .stats_get_strings = mv88e6095_stats_get_strings, 3193 .stats_get_stats = mv88e6095_stats_get_stats, 3194 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3195 .set_egress_port = mv88e6095_g1_set_egress_port, 3196 .watchdog_ops = &mv88e6097_watchdog_ops, 3197 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3198 .pot_clear = mv88e6xxx_g2_pot_clear, 3199 .reset = mv88e6352_g1_reset, 3200 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3201 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3202 .phylink_validate = mv88e6185_phylink_validate, 3203 }; 3204 3205 static const struct mv88e6xxx_ops mv88e6176_ops = { 3206 /* MV88E6XXX_FAMILY_6352 */ 3207 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3208 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3209 .irl_init_all = mv88e6352_g2_irl_init_all, 3210 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3211 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3212 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3213 .phy_read = mv88e6xxx_g2_smi_phy_read, 3214 .phy_write = mv88e6xxx_g2_smi_phy_write, 3215 .port_set_link = mv88e6xxx_port_set_link, 3216 .port_set_duplex = mv88e6xxx_port_set_duplex, 3217 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3218 .port_set_speed = mv88e6352_port_set_speed, 3219 .port_tag_remap = mv88e6095_port_tag_remap, 3220 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3221 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3222 .port_set_ether_type = mv88e6351_port_set_ether_type, 3223 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3224 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3225 .port_pause_limit = mv88e6097_port_pause_limit, 3226 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3227 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3228 .port_link_state = mv88e6352_port_link_state, 3229 .port_get_cmode = mv88e6352_port_get_cmode, 3230 .port_setup_message_port = mv88e6xxx_setup_message_port, 3231 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3232 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3233 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3234 .stats_get_strings = mv88e6095_stats_get_strings, 3235 .stats_get_stats = mv88e6095_stats_get_stats, 3236 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3237 .set_egress_port = mv88e6095_g1_set_egress_port, 3238 .watchdog_ops = &mv88e6097_watchdog_ops, 3239 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3240 .pot_clear = mv88e6xxx_g2_pot_clear, 3241 .reset = mv88e6352_g1_reset, 3242 .rmu_disable = mv88e6352_g1_rmu_disable, 3243 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3244 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3245 .serdes_power = mv88e6352_serdes_power, 3246 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3247 .serdes_irq_free = mv88e6352_serdes_irq_free, 3248 .gpio_ops = &mv88e6352_gpio_ops, 3249 .phylink_validate = mv88e6352_phylink_validate, 3250 }; 3251 3252 static const struct mv88e6xxx_ops mv88e6185_ops = { 3253 /* MV88E6XXX_FAMILY_6185 */ 3254 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3255 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3256 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3257 .phy_read = mv88e6185_phy_ppu_read, 3258 .phy_write = mv88e6185_phy_ppu_write, 3259 .port_set_link = mv88e6xxx_port_set_link, 3260 .port_set_duplex = mv88e6xxx_port_set_duplex, 3261 .port_set_speed = mv88e6185_port_set_speed, 3262 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3263 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3264 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3265 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3266 .port_set_pause = mv88e6185_port_set_pause, 3267 .port_link_state = mv88e6185_port_link_state, 3268 .port_get_cmode = mv88e6185_port_get_cmode, 3269 .port_setup_message_port = mv88e6xxx_setup_message_port, 3270 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3271 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3272 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3273 .stats_get_strings = mv88e6095_stats_get_strings, 3274 .stats_get_stats = mv88e6095_stats_get_stats, 3275 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3276 .set_egress_port = mv88e6095_g1_set_egress_port, 3277 .watchdog_ops = &mv88e6097_watchdog_ops, 3278 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3279 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3280 .ppu_enable = mv88e6185_g1_ppu_enable, 3281 .ppu_disable = mv88e6185_g1_ppu_disable, 3282 .reset = mv88e6185_g1_reset, 3283 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3284 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3285 .phylink_validate = mv88e6185_phylink_validate, 3286 }; 3287 3288 static const struct mv88e6xxx_ops mv88e6190_ops = { 3289 /* MV88E6XXX_FAMILY_6390 */ 3290 .setup_errata = mv88e6390_setup_errata, 3291 .irl_init_all = mv88e6390_g2_irl_init_all, 3292 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3293 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3295 .phy_read = mv88e6xxx_g2_smi_phy_read, 3296 .phy_write = mv88e6xxx_g2_smi_phy_write, 3297 .port_set_link = mv88e6xxx_port_set_link, 3298 .port_set_duplex = mv88e6xxx_port_set_duplex, 3299 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3300 .port_set_speed = mv88e6390_port_set_speed, 3301 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3302 .port_tag_remap = mv88e6390_port_tag_remap, 3303 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3304 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3305 .port_set_ether_type = mv88e6351_port_set_ether_type, 3306 .port_pause_limit = mv88e6390_port_pause_limit, 3307 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3308 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3309 .port_link_state = mv88e6352_port_link_state, 3310 .port_get_cmode = mv88e6352_port_get_cmode, 3311 .port_set_cmode = mv88e6390_port_set_cmode, 3312 .port_setup_message_port = mv88e6xxx_setup_message_port, 3313 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3314 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3315 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3316 .stats_get_strings = mv88e6320_stats_get_strings, 3317 .stats_get_stats = mv88e6390_stats_get_stats, 3318 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3319 .set_egress_port = mv88e6390_g1_set_egress_port, 3320 .watchdog_ops = &mv88e6390_watchdog_ops, 3321 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3322 .pot_clear = mv88e6xxx_g2_pot_clear, 3323 .reset = mv88e6352_g1_reset, 3324 .rmu_disable = mv88e6390_g1_rmu_disable, 3325 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3326 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3327 .serdes_power = mv88e6390_serdes_power, 3328 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3329 .serdes_irq_free = mv88e6390_serdes_irq_free, 3330 .gpio_ops = &mv88e6352_gpio_ops, 3331 .phylink_validate = mv88e6390_phylink_validate, 3332 }; 3333 3334 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3335 /* MV88E6XXX_FAMILY_6390 */ 3336 .setup_errata = mv88e6390_setup_errata, 3337 .irl_init_all = mv88e6390_g2_irl_init_all, 3338 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3339 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3340 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3341 .phy_read = mv88e6xxx_g2_smi_phy_read, 3342 .phy_write = mv88e6xxx_g2_smi_phy_write, 3343 .port_set_link = mv88e6xxx_port_set_link, 3344 .port_set_duplex = mv88e6xxx_port_set_duplex, 3345 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3346 .port_set_speed = mv88e6390x_port_set_speed, 3347 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3348 .port_tag_remap = mv88e6390_port_tag_remap, 3349 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3350 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3351 .port_set_ether_type = mv88e6351_port_set_ether_type, 3352 .port_pause_limit = mv88e6390_port_pause_limit, 3353 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3354 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3355 .port_link_state = mv88e6352_port_link_state, 3356 .port_get_cmode = mv88e6352_port_get_cmode, 3357 .port_set_cmode = mv88e6390x_port_set_cmode, 3358 .port_setup_message_port = mv88e6xxx_setup_message_port, 3359 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3360 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3361 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3362 .stats_get_strings = mv88e6320_stats_get_strings, 3363 .stats_get_stats = mv88e6390_stats_get_stats, 3364 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3365 .set_egress_port = mv88e6390_g1_set_egress_port, 3366 .watchdog_ops = &mv88e6390_watchdog_ops, 3367 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3368 .pot_clear = mv88e6xxx_g2_pot_clear, 3369 .reset = mv88e6352_g1_reset, 3370 .rmu_disable = mv88e6390_g1_rmu_disable, 3371 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3372 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3373 .serdes_power = mv88e6390x_serdes_power, 3374 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3375 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3376 .gpio_ops = &mv88e6352_gpio_ops, 3377 .phylink_validate = mv88e6390x_phylink_validate, 3378 }; 3379 3380 static const struct mv88e6xxx_ops mv88e6191_ops = { 3381 /* MV88E6XXX_FAMILY_6390 */ 3382 .setup_errata = mv88e6390_setup_errata, 3383 .irl_init_all = mv88e6390_g2_irl_init_all, 3384 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3385 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3386 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3387 .phy_read = mv88e6xxx_g2_smi_phy_read, 3388 .phy_write = mv88e6xxx_g2_smi_phy_write, 3389 .port_set_link = mv88e6xxx_port_set_link, 3390 .port_set_duplex = mv88e6xxx_port_set_duplex, 3391 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3392 .port_set_speed = mv88e6390_port_set_speed, 3393 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3394 .port_tag_remap = mv88e6390_port_tag_remap, 3395 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3396 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3397 .port_set_ether_type = mv88e6351_port_set_ether_type, 3398 .port_pause_limit = mv88e6390_port_pause_limit, 3399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3401 .port_link_state = mv88e6352_port_link_state, 3402 .port_get_cmode = mv88e6352_port_get_cmode, 3403 .port_set_cmode = mv88e6390_port_set_cmode, 3404 .port_setup_message_port = mv88e6xxx_setup_message_port, 3405 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3406 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3407 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3408 .stats_get_strings = mv88e6320_stats_get_strings, 3409 .stats_get_stats = mv88e6390_stats_get_stats, 3410 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3411 .set_egress_port = mv88e6390_g1_set_egress_port, 3412 .watchdog_ops = &mv88e6390_watchdog_ops, 3413 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3414 .pot_clear = mv88e6xxx_g2_pot_clear, 3415 .reset = mv88e6352_g1_reset, 3416 .rmu_disable = mv88e6390_g1_rmu_disable, 3417 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3418 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3419 .serdes_power = mv88e6390_serdes_power, 3420 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3421 .serdes_irq_free = mv88e6390_serdes_irq_free, 3422 .avb_ops = &mv88e6390_avb_ops, 3423 .ptp_ops = &mv88e6352_ptp_ops, 3424 .phylink_validate = mv88e6390_phylink_validate, 3425 }; 3426 3427 static const struct mv88e6xxx_ops mv88e6240_ops = { 3428 /* MV88E6XXX_FAMILY_6352 */ 3429 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3430 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3431 .irl_init_all = mv88e6352_g2_irl_init_all, 3432 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3433 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3434 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3435 .phy_read = mv88e6xxx_g2_smi_phy_read, 3436 .phy_write = mv88e6xxx_g2_smi_phy_write, 3437 .port_set_link = mv88e6xxx_port_set_link, 3438 .port_set_duplex = mv88e6xxx_port_set_duplex, 3439 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3440 .port_set_speed = mv88e6352_port_set_speed, 3441 .port_tag_remap = mv88e6095_port_tag_remap, 3442 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3443 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3444 .port_set_ether_type = mv88e6351_port_set_ether_type, 3445 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3446 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3447 .port_pause_limit = mv88e6097_port_pause_limit, 3448 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3449 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3450 .port_link_state = mv88e6352_port_link_state, 3451 .port_get_cmode = mv88e6352_port_get_cmode, 3452 .port_setup_message_port = mv88e6xxx_setup_message_port, 3453 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3454 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3455 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3456 .stats_get_strings = mv88e6095_stats_get_strings, 3457 .stats_get_stats = mv88e6095_stats_get_stats, 3458 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3459 .set_egress_port = mv88e6095_g1_set_egress_port, 3460 .watchdog_ops = &mv88e6097_watchdog_ops, 3461 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3462 .pot_clear = mv88e6xxx_g2_pot_clear, 3463 .reset = mv88e6352_g1_reset, 3464 .rmu_disable = mv88e6352_g1_rmu_disable, 3465 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3466 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3467 .serdes_power = mv88e6352_serdes_power, 3468 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3469 .serdes_irq_free = mv88e6352_serdes_irq_free, 3470 .gpio_ops = &mv88e6352_gpio_ops, 3471 .avb_ops = &mv88e6352_avb_ops, 3472 .ptp_ops = &mv88e6352_ptp_ops, 3473 .phylink_validate = mv88e6352_phylink_validate, 3474 }; 3475 3476 static const struct mv88e6xxx_ops mv88e6250_ops = { 3477 /* MV88E6XXX_FAMILY_6250 */ 3478 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 3479 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3480 .irl_init_all = mv88e6352_g2_irl_init_all, 3481 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3482 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3483 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3484 .phy_read = mv88e6xxx_g2_smi_phy_read, 3485 .phy_write = mv88e6xxx_g2_smi_phy_write, 3486 .port_set_link = mv88e6xxx_port_set_link, 3487 .port_set_duplex = mv88e6xxx_port_set_duplex, 3488 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3489 .port_set_speed = mv88e6250_port_set_speed, 3490 .port_tag_remap = mv88e6095_port_tag_remap, 3491 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3492 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3493 .port_set_ether_type = mv88e6351_port_set_ether_type, 3494 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3495 .port_pause_limit = mv88e6097_port_pause_limit, 3496 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3497 .port_link_state = mv88e6250_port_link_state, 3498 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3499 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3500 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 3501 .stats_get_strings = mv88e6250_stats_get_strings, 3502 .stats_get_stats = mv88e6250_stats_get_stats, 3503 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3504 .set_egress_port = mv88e6095_g1_set_egress_port, 3505 .watchdog_ops = &mv88e6250_watchdog_ops, 3506 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3507 .pot_clear = mv88e6xxx_g2_pot_clear, 3508 .reset = mv88e6250_g1_reset, 3509 .vtu_getnext = mv88e6250_g1_vtu_getnext, 3510 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 3511 .avb_ops = &mv88e6352_avb_ops, 3512 .ptp_ops = &mv88e6250_ptp_ops, 3513 .phylink_validate = mv88e6065_phylink_validate, 3514 }; 3515 3516 static const struct mv88e6xxx_ops mv88e6290_ops = { 3517 /* MV88E6XXX_FAMILY_6390 */ 3518 .setup_errata = mv88e6390_setup_errata, 3519 .irl_init_all = mv88e6390_g2_irl_init_all, 3520 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3521 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3523 .phy_read = mv88e6xxx_g2_smi_phy_read, 3524 .phy_write = mv88e6xxx_g2_smi_phy_write, 3525 .port_set_link = mv88e6xxx_port_set_link, 3526 .port_set_duplex = mv88e6xxx_port_set_duplex, 3527 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3528 .port_set_speed = mv88e6390_port_set_speed, 3529 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3530 .port_tag_remap = mv88e6390_port_tag_remap, 3531 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3532 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3533 .port_set_ether_type = mv88e6351_port_set_ether_type, 3534 .port_pause_limit = mv88e6390_port_pause_limit, 3535 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3536 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3537 .port_link_state = mv88e6352_port_link_state, 3538 .port_get_cmode = mv88e6352_port_get_cmode, 3539 .port_set_cmode = mv88e6390_port_set_cmode, 3540 .port_setup_message_port = mv88e6xxx_setup_message_port, 3541 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3542 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3543 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3544 .stats_get_strings = mv88e6320_stats_get_strings, 3545 .stats_get_stats = mv88e6390_stats_get_stats, 3546 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3547 .set_egress_port = mv88e6390_g1_set_egress_port, 3548 .watchdog_ops = &mv88e6390_watchdog_ops, 3549 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3550 .pot_clear = mv88e6xxx_g2_pot_clear, 3551 .reset = mv88e6352_g1_reset, 3552 .rmu_disable = mv88e6390_g1_rmu_disable, 3553 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3554 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3555 .serdes_power = mv88e6390_serdes_power, 3556 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3557 .serdes_irq_free = mv88e6390_serdes_irq_free, 3558 .gpio_ops = &mv88e6352_gpio_ops, 3559 .avb_ops = &mv88e6390_avb_ops, 3560 .ptp_ops = &mv88e6352_ptp_ops, 3561 .phylink_validate = mv88e6390_phylink_validate, 3562 }; 3563 3564 static const struct mv88e6xxx_ops mv88e6320_ops = { 3565 /* MV88E6XXX_FAMILY_6320 */ 3566 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3567 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3568 .irl_init_all = mv88e6352_g2_irl_init_all, 3569 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3570 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3571 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3572 .phy_read = mv88e6xxx_g2_smi_phy_read, 3573 .phy_write = mv88e6xxx_g2_smi_phy_write, 3574 .port_set_link = mv88e6xxx_port_set_link, 3575 .port_set_duplex = mv88e6xxx_port_set_duplex, 3576 .port_set_speed = mv88e6185_port_set_speed, 3577 .port_tag_remap = mv88e6095_port_tag_remap, 3578 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3579 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3580 .port_set_ether_type = mv88e6351_port_set_ether_type, 3581 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3582 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3583 .port_pause_limit = mv88e6097_port_pause_limit, 3584 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3585 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3586 .port_link_state = mv88e6352_port_link_state, 3587 .port_get_cmode = mv88e6352_port_get_cmode, 3588 .port_setup_message_port = mv88e6xxx_setup_message_port, 3589 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3590 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3591 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3592 .stats_get_strings = mv88e6320_stats_get_strings, 3593 .stats_get_stats = mv88e6320_stats_get_stats, 3594 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3595 .set_egress_port = mv88e6095_g1_set_egress_port, 3596 .watchdog_ops = &mv88e6390_watchdog_ops, 3597 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3598 .pot_clear = mv88e6xxx_g2_pot_clear, 3599 .reset = mv88e6352_g1_reset, 3600 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3601 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3602 .gpio_ops = &mv88e6352_gpio_ops, 3603 .avb_ops = &mv88e6352_avb_ops, 3604 .ptp_ops = &mv88e6352_ptp_ops, 3605 .phylink_validate = mv88e6185_phylink_validate, 3606 }; 3607 3608 static const struct mv88e6xxx_ops mv88e6321_ops = { 3609 /* MV88E6XXX_FAMILY_6320 */ 3610 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3611 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3612 .irl_init_all = mv88e6352_g2_irl_init_all, 3613 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3614 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3615 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3616 .phy_read = mv88e6xxx_g2_smi_phy_read, 3617 .phy_write = mv88e6xxx_g2_smi_phy_write, 3618 .port_set_link = mv88e6xxx_port_set_link, 3619 .port_set_duplex = mv88e6xxx_port_set_duplex, 3620 .port_set_speed = mv88e6185_port_set_speed, 3621 .port_tag_remap = mv88e6095_port_tag_remap, 3622 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3623 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3624 .port_set_ether_type = mv88e6351_port_set_ether_type, 3625 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3626 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3627 .port_pause_limit = mv88e6097_port_pause_limit, 3628 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3629 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3630 .port_link_state = mv88e6352_port_link_state, 3631 .port_get_cmode = mv88e6352_port_get_cmode, 3632 .port_setup_message_port = mv88e6xxx_setup_message_port, 3633 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3634 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3635 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3636 .stats_get_strings = mv88e6320_stats_get_strings, 3637 .stats_get_stats = mv88e6320_stats_get_stats, 3638 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3639 .set_egress_port = mv88e6095_g1_set_egress_port, 3640 .watchdog_ops = &mv88e6390_watchdog_ops, 3641 .reset = mv88e6352_g1_reset, 3642 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3643 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3644 .gpio_ops = &mv88e6352_gpio_ops, 3645 .avb_ops = &mv88e6352_avb_ops, 3646 .ptp_ops = &mv88e6352_ptp_ops, 3647 .phylink_validate = mv88e6185_phylink_validate, 3648 }; 3649 3650 static const struct mv88e6xxx_ops mv88e6341_ops = { 3651 /* MV88E6XXX_FAMILY_6341 */ 3652 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3653 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3654 .irl_init_all = mv88e6352_g2_irl_init_all, 3655 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3656 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3657 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3658 .phy_read = mv88e6xxx_g2_smi_phy_read, 3659 .phy_write = mv88e6xxx_g2_smi_phy_write, 3660 .port_set_link = mv88e6xxx_port_set_link, 3661 .port_set_duplex = mv88e6xxx_port_set_duplex, 3662 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3663 .port_set_speed = mv88e6341_port_set_speed, 3664 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3665 .port_tag_remap = mv88e6095_port_tag_remap, 3666 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3667 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3668 .port_set_ether_type = mv88e6351_port_set_ether_type, 3669 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3670 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3671 .port_pause_limit = mv88e6097_port_pause_limit, 3672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3674 .port_link_state = mv88e6352_port_link_state, 3675 .port_get_cmode = mv88e6352_port_get_cmode, 3676 .port_setup_message_port = mv88e6xxx_setup_message_port, 3677 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3679 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3680 .stats_get_strings = mv88e6320_stats_get_strings, 3681 .stats_get_stats = mv88e6390_stats_get_stats, 3682 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3683 .set_egress_port = mv88e6390_g1_set_egress_port, 3684 .watchdog_ops = &mv88e6390_watchdog_ops, 3685 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3686 .pot_clear = mv88e6xxx_g2_pot_clear, 3687 .reset = mv88e6352_g1_reset, 3688 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3689 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3690 .serdes_power = mv88e6341_serdes_power, 3691 .gpio_ops = &mv88e6352_gpio_ops, 3692 .avb_ops = &mv88e6390_avb_ops, 3693 .ptp_ops = &mv88e6352_ptp_ops, 3694 .phylink_validate = mv88e6341_phylink_validate, 3695 }; 3696 3697 static const struct mv88e6xxx_ops mv88e6350_ops = { 3698 /* MV88E6XXX_FAMILY_6351 */ 3699 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3700 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3701 .irl_init_all = mv88e6352_g2_irl_init_all, 3702 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3703 .phy_read = mv88e6xxx_g2_smi_phy_read, 3704 .phy_write = mv88e6xxx_g2_smi_phy_write, 3705 .port_set_link = mv88e6xxx_port_set_link, 3706 .port_set_duplex = mv88e6xxx_port_set_duplex, 3707 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3708 .port_set_speed = mv88e6185_port_set_speed, 3709 .port_tag_remap = mv88e6095_port_tag_remap, 3710 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3711 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3712 .port_set_ether_type = mv88e6351_port_set_ether_type, 3713 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3714 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3715 .port_pause_limit = mv88e6097_port_pause_limit, 3716 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3717 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3718 .port_link_state = mv88e6352_port_link_state, 3719 .port_get_cmode = mv88e6352_port_get_cmode, 3720 .port_setup_message_port = mv88e6xxx_setup_message_port, 3721 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3722 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3723 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3724 .stats_get_strings = mv88e6095_stats_get_strings, 3725 .stats_get_stats = mv88e6095_stats_get_stats, 3726 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3727 .set_egress_port = mv88e6095_g1_set_egress_port, 3728 .watchdog_ops = &mv88e6097_watchdog_ops, 3729 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3730 .pot_clear = mv88e6xxx_g2_pot_clear, 3731 .reset = mv88e6352_g1_reset, 3732 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3733 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3734 .phylink_validate = mv88e6185_phylink_validate, 3735 }; 3736 3737 static const struct mv88e6xxx_ops mv88e6351_ops = { 3738 /* MV88E6XXX_FAMILY_6351 */ 3739 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3740 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3741 .irl_init_all = mv88e6352_g2_irl_init_all, 3742 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3743 .phy_read = mv88e6xxx_g2_smi_phy_read, 3744 .phy_write = mv88e6xxx_g2_smi_phy_write, 3745 .port_set_link = mv88e6xxx_port_set_link, 3746 .port_set_duplex = mv88e6xxx_port_set_duplex, 3747 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3748 .port_set_speed = mv88e6185_port_set_speed, 3749 .port_tag_remap = mv88e6095_port_tag_remap, 3750 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3751 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3752 .port_set_ether_type = mv88e6351_port_set_ether_type, 3753 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3754 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3755 .port_pause_limit = mv88e6097_port_pause_limit, 3756 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3757 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3758 .port_link_state = mv88e6352_port_link_state, 3759 .port_get_cmode = mv88e6352_port_get_cmode, 3760 .port_setup_message_port = mv88e6xxx_setup_message_port, 3761 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3762 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3763 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3764 .stats_get_strings = mv88e6095_stats_get_strings, 3765 .stats_get_stats = mv88e6095_stats_get_stats, 3766 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3767 .set_egress_port = mv88e6095_g1_set_egress_port, 3768 .watchdog_ops = &mv88e6097_watchdog_ops, 3769 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3770 .pot_clear = mv88e6xxx_g2_pot_clear, 3771 .reset = mv88e6352_g1_reset, 3772 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3773 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3774 .avb_ops = &mv88e6352_avb_ops, 3775 .ptp_ops = &mv88e6352_ptp_ops, 3776 .phylink_validate = mv88e6185_phylink_validate, 3777 }; 3778 3779 static const struct mv88e6xxx_ops mv88e6352_ops = { 3780 /* MV88E6XXX_FAMILY_6352 */ 3781 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3782 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3783 .irl_init_all = mv88e6352_g2_irl_init_all, 3784 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3785 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3786 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3787 .phy_read = mv88e6xxx_g2_smi_phy_read, 3788 .phy_write = mv88e6xxx_g2_smi_phy_write, 3789 .port_set_link = mv88e6xxx_port_set_link, 3790 .port_set_duplex = mv88e6xxx_port_set_duplex, 3791 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3792 .port_set_speed = mv88e6352_port_set_speed, 3793 .port_tag_remap = mv88e6095_port_tag_remap, 3794 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3795 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3796 .port_set_ether_type = mv88e6351_port_set_ether_type, 3797 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3798 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3799 .port_pause_limit = mv88e6097_port_pause_limit, 3800 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3801 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3802 .port_link_state = mv88e6352_port_link_state, 3803 .port_get_cmode = mv88e6352_port_get_cmode, 3804 .port_setup_message_port = mv88e6xxx_setup_message_port, 3805 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3806 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3807 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3808 .stats_get_strings = mv88e6095_stats_get_strings, 3809 .stats_get_stats = mv88e6095_stats_get_stats, 3810 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3811 .set_egress_port = mv88e6095_g1_set_egress_port, 3812 .watchdog_ops = &mv88e6097_watchdog_ops, 3813 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3814 .pot_clear = mv88e6xxx_g2_pot_clear, 3815 .reset = mv88e6352_g1_reset, 3816 .rmu_disable = mv88e6352_g1_rmu_disable, 3817 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3818 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3819 .serdes_power = mv88e6352_serdes_power, 3820 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3821 .serdes_irq_free = mv88e6352_serdes_irq_free, 3822 .gpio_ops = &mv88e6352_gpio_ops, 3823 .avb_ops = &mv88e6352_avb_ops, 3824 .ptp_ops = &mv88e6352_ptp_ops, 3825 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3826 .serdes_get_strings = mv88e6352_serdes_get_strings, 3827 .serdes_get_stats = mv88e6352_serdes_get_stats, 3828 .phylink_validate = mv88e6352_phylink_validate, 3829 }; 3830 3831 static const struct mv88e6xxx_ops mv88e6390_ops = { 3832 /* MV88E6XXX_FAMILY_6390 */ 3833 .setup_errata = mv88e6390_setup_errata, 3834 .irl_init_all = mv88e6390_g2_irl_init_all, 3835 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3836 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3837 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3838 .phy_read = mv88e6xxx_g2_smi_phy_read, 3839 .phy_write = mv88e6xxx_g2_smi_phy_write, 3840 .port_set_link = mv88e6xxx_port_set_link, 3841 .port_set_duplex = mv88e6xxx_port_set_duplex, 3842 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3843 .port_set_speed = mv88e6390_port_set_speed, 3844 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3845 .port_tag_remap = mv88e6390_port_tag_remap, 3846 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3847 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3848 .port_set_ether_type = mv88e6351_port_set_ether_type, 3849 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3850 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3851 .port_pause_limit = mv88e6390_port_pause_limit, 3852 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3853 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3854 .port_link_state = mv88e6352_port_link_state, 3855 .port_get_cmode = mv88e6352_port_get_cmode, 3856 .port_set_cmode = mv88e6390_port_set_cmode, 3857 .port_setup_message_port = mv88e6xxx_setup_message_port, 3858 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3859 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3860 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3861 .stats_get_strings = mv88e6320_stats_get_strings, 3862 .stats_get_stats = mv88e6390_stats_get_stats, 3863 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3864 .set_egress_port = mv88e6390_g1_set_egress_port, 3865 .watchdog_ops = &mv88e6390_watchdog_ops, 3866 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3867 .pot_clear = mv88e6xxx_g2_pot_clear, 3868 .reset = mv88e6352_g1_reset, 3869 .rmu_disable = mv88e6390_g1_rmu_disable, 3870 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3871 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3872 .serdes_power = mv88e6390_serdes_power, 3873 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3874 .serdes_irq_free = mv88e6390_serdes_irq_free, 3875 .gpio_ops = &mv88e6352_gpio_ops, 3876 .avb_ops = &mv88e6390_avb_ops, 3877 .ptp_ops = &mv88e6352_ptp_ops, 3878 .phylink_validate = mv88e6390_phylink_validate, 3879 }; 3880 3881 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3882 /* MV88E6XXX_FAMILY_6390 */ 3883 .setup_errata = mv88e6390_setup_errata, 3884 .irl_init_all = mv88e6390_g2_irl_init_all, 3885 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3886 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3887 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3888 .phy_read = mv88e6xxx_g2_smi_phy_read, 3889 .phy_write = mv88e6xxx_g2_smi_phy_write, 3890 .port_set_link = mv88e6xxx_port_set_link, 3891 .port_set_duplex = mv88e6xxx_port_set_duplex, 3892 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3893 .port_set_speed = mv88e6390x_port_set_speed, 3894 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3895 .port_tag_remap = mv88e6390_port_tag_remap, 3896 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3897 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3898 .port_set_ether_type = mv88e6351_port_set_ether_type, 3899 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3900 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3901 .port_pause_limit = mv88e6390_port_pause_limit, 3902 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3903 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3904 .port_link_state = mv88e6352_port_link_state, 3905 .port_get_cmode = mv88e6352_port_get_cmode, 3906 .port_set_cmode = mv88e6390x_port_set_cmode, 3907 .port_setup_message_port = mv88e6xxx_setup_message_port, 3908 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3909 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3910 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3911 .stats_get_strings = mv88e6320_stats_get_strings, 3912 .stats_get_stats = mv88e6390_stats_get_stats, 3913 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3914 .set_egress_port = mv88e6390_g1_set_egress_port, 3915 .watchdog_ops = &mv88e6390_watchdog_ops, 3916 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3917 .pot_clear = mv88e6xxx_g2_pot_clear, 3918 .reset = mv88e6352_g1_reset, 3919 .rmu_disable = mv88e6390_g1_rmu_disable, 3920 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3921 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3922 .serdes_power = mv88e6390x_serdes_power, 3923 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3924 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3925 .gpio_ops = &mv88e6352_gpio_ops, 3926 .avb_ops = &mv88e6390_avb_ops, 3927 .ptp_ops = &mv88e6352_ptp_ops, 3928 .phylink_validate = mv88e6390x_phylink_validate, 3929 }; 3930 3931 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3932 [MV88E6085] = { 3933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3934 .family = MV88E6XXX_FAMILY_6097, 3935 .name = "Marvell 88E6085", 3936 .num_databases = 4096, 3937 .num_ports = 10, 3938 .num_internal_phys = 5, 3939 .max_vid = 4095, 3940 .port_base_addr = 0x10, 3941 .phy_base_addr = 0x0, 3942 .global1_addr = 0x1b, 3943 .global2_addr = 0x1c, 3944 .age_time_coeff = 15000, 3945 .g1_irqs = 8, 3946 .g2_irqs = 10, 3947 .atu_move_port_mask = 0xf, 3948 .pvt = true, 3949 .multi_chip = true, 3950 .tag_protocol = DSA_TAG_PROTO_DSA, 3951 .ops = &mv88e6085_ops, 3952 }, 3953 3954 [MV88E6095] = { 3955 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3956 .family = MV88E6XXX_FAMILY_6095, 3957 .name = "Marvell 88E6095/88E6095F", 3958 .num_databases = 256, 3959 .num_ports = 11, 3960 .num_internal_phys = 0, 3961 .max_vid = 4095, 3962 .port_base_addr = 0x10, 3963 .phy_base_addr = 0x0, 3964 .global1_addr = 0x1b, 3965 .global2_addr = 0x1c, 3966 .age_time_coeff = 15000, 3967 .g1_irqs = 8, 3968 .atu_move_port_mask = 0xf, 3969 .multi_chip = true, 3970 .tag_protocol = DSA_TAG_PROTO_DSA, 3971 .ops = &mv88e6095_ops, 3972 }, 3973 3974 [MV88E6097] = { 3975 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3976 .family = MV88E6XXX_FAMILY_6097, 3977 .name = "Marvell 88E6097/88E6097F", 3978 .num_databases = 4096, 3979 .num_ports = 11, 3980 .num_internal_phys = 8, 3981 .max_vid = 4095, 3982 .port_base_addr = 0x10, 3983 .phy_base_addr = 0x0, 3984 .global1_addr = 0x1b, 3985 .global2_addr = 0x1c, 3986 .age_time_coeff = 15000, 3987 .g1_irqs = 8, 3988 .g2_irqs = 10, 3989 .atu_move_port_mask = 0xf, 3990 .pvt = true, 3991 .multi_chip = true, 3992 .tag_protocol = DSA_TAG_PROTO_EDSA, 3993 .ops = &mv88e6097_ops, 3994 }, 3995 3996 [MV88E6123] = { 3997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3998 .family = MV88E6XXX_FAMILY_6165, 3999 .name = "Marvell 88E6123", 4000 .num_databases = 4096, 4001 .num_ports = 3, 4002 .num_internal_phys = 5, 4003 .max_vid = 4095, 4004 .port_base_addr = 0x10, 4005 .phy_base_addr = 0x0, 4006 .global1_addr = 0x1b, 4007 .global2_addr = 0x1c, 4008 .age_time_coeff = 15000, 4009 .g1_irqs = 9, 4010 .g2_irqs = 10, 4011 .atu_move_port_mask = 0xf, 4012 .pvt = true, 4013 .multi_chip = true, 4014 .tag_protocol = DSA_TAG_PROTO_EDSA, 4015 .ops = &mv88e6123_ops, 4016 }, 4017 4018 [MV88E6131] = { 4019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4020 .family = MV88E6XXX_FAMILY_6185, 4021 .name = "Marvell 88E6131", 4022 .num_databases = 256, 4023 .num_ports = 8, 4024 .num_internal_phys = 0, 4025 .max_vid = 4095, 4026 .port_base_addr = 0x10, 4027 .phy_base_addr = 0x0, 4028 .global1_addr = 0x1b, 4029 .global2_addr = 0x1c, 4030 .age_time_coeff = 15000, 4031 .g1_irqs = 9, 4032 .atu_move_port_mask = 0xf, 4033 .multi_chip = true, 4034 .tag_protocol = DSA_TAG_PROTO_DSA, 4035 .ops = &mv88e6131_ops, 4036 }, 4037 4038 [MV88E6141] = { 4039 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4040 .family = MV88E6XXX_FAMILY_6341, 4041 .name = "Marvell 88E6141", 4042 .num_databases = 4096, 4043 .num_ports = 6, 4044 .num_internal_phys = 5, 4045 .num_gpio = 11, 4046 .max_vid = 4095, 4047 .port_base_addr = 0x10, 4048 .phy_base_addr = 0x10, 4049 .global1_addr = 0x1b, 4050 .global2_addr = 0x1c, 4051 .age_time_coeff = 3750, 4052 .atu_move_port_mask = 0x1f, 4053 .g1_irqs = 9, 4054 .g2_irqs = 10, 4055 .pvt = true, 4056 .multi_chip = true, 4057 .tag_protocol = DSA_TAG_PROTO_EDSA, 4058 .ops = &mv88e6141_ops, 4059 }, 4060 4061 [MV88E6161] = { 4062 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4063 .family = MV88E6XXX_FAMILY_6165, 4064 .name = "Marvell 88E6161", 4065 .num_databases = 4096, 4066 .num_ports = 6, 4067 .num_internal_phys = 5, 4068 .max_vid = 4095, 4069 .port_base_addr = 0x10, 4070 .phy_base_addr = 0x0, 4071 .global1_addr = 0x1b, 4072 .global2_addr = 0x1c, 4073 .age_time_coeff = 15000, 4074 .g1_irqs = 9, 4075 .g2_irqs = 10, 4076 .atu_move_port_mask = 0xf, 4077 .pvt = true, 4078 .multi_chip = true, 4079 .tag_protocol = DSA_TAG_PROTO_EDSA, 4080 .ptp_support = true, 4081 .ops = &mv88e6161_ops, 4082 }, 4083 4084 [MV88E6165] = { 4085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4086 .family = MV88E6XXX_FAMILY_6165, 4087 .name = "Marvell 88E6165", 4088 .num_databases = 4096, 4089 .num_ports = 6, 4090 .num_internal_phys = 0, 4091 .max_vid = 4095, 4092 .port_base_addr = 0x10, 4093 .phy_base_addr = 0x0, 4094 .global1_addr = 0x1b, 4095 .global2_addr = 0x1c, 4096 .age_time_coeff = 15000, 4097 .g1_irqs = 9, 4098 .g2_irqs = 10, 4099 .atu_move_port_mask = 0xf, 4100 .pvt = true, 4101 .multi_chip = true, 4102 .tag_protocol = DSA_TAG_PROTO_DSA, 4103 .ptp_support = true, 4104 .ops = &mv88e6165_ops, 4105 }, 4106 4107 [MV88E6171] = { 4108 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4109 .family = MV88E6XXX_FAMILY_6351, 4110 .name = "Marvell 88E6171", 4111 .num_databases = 4096, 4112 .num_ports = 7, 4113 .num_internal_phys = 5, 4114 .max_vid = 4095, 4115 .port_base_addr = 0x10, 4116 .phy_base_addr = 0x0, 4117 .global1_addr = 0x1b, 4118 .global2_addr = 0x1c, 4119 .age_time_coeff = 15000, 4120 .g1_irqs = 9, 4121 .g2_irqs = 10, 4122 .atu_move_port_mask = 0xf, 4123 .pvt = true, 4124 .multi_chip = true, 4125 .tag_protocol = DSA_TAG_PROTO_EDSA, 4126 .ops = &mv88e6171_ops, 4127 }, 4128 4129 [MV88E6172] = { 4130 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4131 .family = MV88E6XXX_FAMILY_6352, 4132 .name = "Marvell 88E6172", 4133 .num_databases = 4096, 4134 .num_ports = 7, 4135 .num_internal_phys = 5, 4136 .num_gpio = 15, 4137 .max_vid = 4095, 4138 .port_base_addr = 0x10, 4139 .phy_base_addr = 0x0, 4140 .global1_addr = 0x1b, 4141 .global2_addr = 0x1c, 4142 .age_time_coeff = 15000, 4143 .g1_irqs = 9, 4144 .g2_irqs = 10, 4145 .atu_move_port_mask = 0xf, 4146 .pvt = true, 4147 .multi_chip = true, 4148 .tag_protocol = DSA_TAG_PROTO_EDSA, 4149 .ops = &mv88e6172_ops, 4150 }, 4151 4152 [MV88E6175] = { 4153 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4154 .family = MV88E6XXX_FAMILY_6351, 4155 .name = "Marvell 88E6175", 4156 .num_databases = 4096, 4157 .num_ports = 7, 4158 .num_internal_phys = 5, 4159 .max_vid = 4095, 4160 .port_base_addr = 0x10, 4161 .phy_base_addr = 0x0, 4162 .global1_addr = 0x1b, 4163 .global2_addr = 0x1c, 4164 .age_time_coeff = 15000, 4165 .g1_irqs = 9, 4166 .g2_irqs = 10, 4167 .atu_move_port_mask = 0xf, 4168 .pvt = true, 4169 .multi_chip = true, 4170 .tag_protocol = DSA_TAG_PROTO_EDSA, 4171 .ops = &mv88e6175_ops, 4172 }, 4173 4174 [MV88E6176] = { 4175 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4176 .family = MV88E6XXX_FAMILY_6352, 4177 .name = "Marvell 88E6176", 4178 .num_databases = 4096, 4179 .num_ports = 7, 4180 .num_internal_phys = 5, 4181 .num_gpio = 15, 4182 .max_vid = 4095, 4183 .port_base_addr = 0x10, 4184 .phy_base_addr = 0x0, 4185 .global1_addr = 0x1b, 4186 .global2_addr = 0x1c, 4187 .age_time_coeff = 15000, 4188 .g1_irqs = 9, 4189 .g2_irqs = 10, 4190 .atu_move_port_mask = 0xf, 4191 .pvt = true, 4192 .multi_chip = true, 4193 .tag_protocol = DSA_TAG_PROTO_EDSA, 4194 .ops = &mv88e6176_ops, 4195 }, 4196 4197 [MV88E6185] = { 4198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4199 .family = MV88E6XXX_FAMILY_6185, 4200 .name = "Marvell 88E6185", 4201 .num_databases = 256, 4202 .num_ports = 10, 4203 .num_internal_phys = 0, 4204 .max_vid = 4095, 4205 .port_base_addr = 0x10, 4206 .phy_base_addr = 0x0, 4207 .global1_addr = 0x1b, 4208 .global2_addr = 0x1c, 4209 .age_time_coeff = 15000, 4210 .g1_irqs = 8, 4211 .atu_move_port_mask = 0xf, 4212 .multi_chip = true, 4213 .tag_protocol = DSA_TAG_PROTO_EDSA, 4214 .ops = &mv88e6185_ops, 4215 }, 4216 4217 [MV88E6190] = { 4218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4219 .family = MV88E6XXX_FAMILY_6390, 4220 .name = "Marvell 88E6190", 4221 .num_databases = 4096, 4222 .num_ports = 11, /* 10 + Z80 */ 4223 .num_internal_phys = 9, 4224 .num_gpio = 16, 4225 .max_vid = 8191, 4226 .port_base_addr = 0x0, 4227 .phy_base_addr = 0x0, 4228 .global1_addr = 0x1b, 4229 .global2_addr = 0x1c, 4230 .tag_protocol = DSA_TAG_PROTO_DSA, 4231 .age_time_coeff = 3750, 4232 .g1_irqs = 9, 4233 .g2_irqs = 14, 4234 .pvt = true, 4235 .multi_chip = true, 4236 .atu_move_port_mask = 0x1f, 4237 .ops = &mv88e6190_ops, 4238 }, 4239 4240 [MV88E6190X] = { 4241 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4242 .family = MV88E6XXX_FAMILY_6390, 4243 .name = "Marvell 88E6190X", 4244 .num_databases = 4096, 4245 .num_ports = 11, /* 10 + Z80 */ 4246 .num_internal_phys = 9, 4247 .num_gpio = 16, 4248 .max_vid = 8191, 4249 .port_base_addr = 0x0, 4250 .phy_base_addr = 0x0, 4251 .global1_addr = 0x1b, 4252 .global2_addr = 0x1c, 4253 .age_time_coeff = 3750, 4254 .g1_irqs = 9, 4255 .g2_irqs = 14, 4256 .atu_move_port_mask = 0x1f, 4257 .pvt = true, 4258 .multi_chip = true, 4259 .tag_protocol = DSA_TAG_PROTO_DSA, 4260 .ops = &mv88e6190x_ops, 4261 }, 4262 4263 [MV88E6191] = { 4264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4265 .family = MV88E6XXX_FAMILY_6390, 4266 .name = "Marvell 88E6191", 4267 .num_databases = 4096, 4268 .num_ports = 11, /* 10 + Z80 */ 4269 .num_internal_phys = 9, 4270 .max_vid = 8191, 4271 .port_base_addr = 0x0, 4272 .phy_base_addr = 0x0, 4273 .global1_addr = 0x1b, 4274 .global2_addr = 0x1c, 4275 .age_time_coeff = 3750, 4276 .g1_irqs = 9, 4277 .g2_irqs = 14, 4278 .atu_move_port_mask = 0x1f, 4279 .pvt = true, 4280 .multi_chip = true, 4281 .tag_protocol = DSA_TAG_PROTO_DSA, 4282 .ptp_support = true, 4283 .ops = &mv88e6191_ops, 4284 }, 4285 4286 [MV88E6220] = { 4287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4288 .family = MV88E6XXX_FAMILY_6250, 4289 .name = "Marvell 88E6220", 4290 .num_databases = 64, 4291 4292 /* Ports 2-4 are not routed to pins 4293 * => usable ports 0, 1, 5, 6 4294 */ 4295 .num_ports = 7, 4296 .num_internal_phys = 2, 4297 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4298 .max_vid = 4095, 4299 .port_base_addr = 0x08, 4300 .phy_base_addr = 0x00, 4301 .global1_addr = 0x0f, 4302 .global2_addr = 0x07, 4303 .age_time_coeff = 15000, 4304 .g1_irqs = 9, 4305 .g2_irqs = 10, 4306 .atu_move_port_mask = 0xf, 4307 .dual_chip = true, 4308 .tag_protocol = DSA_TAG_PROTO_DSA, 4309 .ptp_support = true, 4310 .ops = &mv88e6250_ops, 4311 }, 4312 4313 [MV88E6240] = { 4314 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4315 .family = MV88E6XXX_FAMILY_6352, 4316 .name = "Marvell 88E6240", 4317 .num_databases = 4096, 4318 .num_ports = 7, 4319 .num_internal_phys = 5, 4320 .num_gpio = 15, 4321 .max_vid = 4095, 4322 .port_base_addr = 0x10, 4323 .phy_base_addr = 0x0, 4324 .global1_addr = 0x1b, 4325 .global2_addr = 0x1c, 4326 .age_time_coeff = 15000, 4327 .g1_irqs = 9, 4328 .g2_irqs = 10, 4329 .atu_move_port_mask = 0xf, 4330 .pvt = true, 4331 .multi_chip = true, 4332 .tag_protocol = DSA_TAG_PROTO_EDSA, 4333 .ptp_support = true, 4334 .ops = &mv88e6240_ops, 4335 }, 4336 4337 [MV88E6250] = { 4338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4339 .family = MV88E6XXX_FAMILY_6250, 4340 .name = "Marvell 88E6250", 4341 .num_databases = 64, 4342 .num_ports = 7, 4343 .num_internal_phys = 5, 4344 .max_vid = 4095, 4345 .port_base_addr = 0x08, 4346 .phy_base_addr = 0x00, 4347 .global1_addr = 0x0f, 4348 .global2_addr = 0x07, 4349 .age_time_coeff = 15000, 4350 .g1_irqs = 9, 4351 .g2_irqs = 10, 4352 .atu_move_port_mask = 0xf, 4353 .dual_chip = true, 4354 .tag_protocol = DSA_TAG_PROTO_DSA, 4355 .ptp_support = true, 4356 .ops = &mv88e6250_ops, 4357 }, 4358 4359 [MV88E6290] = { 4360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4361 .family = MV88E6XXX_FAMILY_6390, 4362 .name = "Marvell 88E6290", 4363 .num_databases = 4096, 4364 .num_ports = 11, /* 10 + Z80 */ 4365 .num_internal_phys = 9, 4366 .num_gpio = 16, 4367 .max_vid = 8191, 4368 .port_base_addr = 0x0, 4369 .phy_base_addr = 0x0, 4370 .global1_addr = 0x1b, 4371 .global2_addr = 0x1c, 4372 .age_time_coeff = 3750, 4373 .g1_irqs = 9, 4374 .g2_irqs = 14, 4375 .atu_move_port_mask = 0x1f, 4376 .pvt = true, 4377 .multi_chip = true, 4378 .tag_protocol = DSA_TAG_PROTO_DSA, 4379 .ptp_support = true, 4380 .ops = &mv88e6290_ops, 4381 }, 4382 4383 [MV88E6320] = { 4384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4385 .family = MV88E6XXX_FAMILY_6320, 4386 .name = "Marvell 88E6320", 4387 .num_databases = 4096, 4388 .num_ports = 7, 4389 .num_internal_phys = 5, 4390 .num_gpio = 15, 4391 .max_vid = 4095, 4392 .port_base_addr = 0x10, 4393 .phy_base_addr = 0x0, 4394 .global1_addr = 0x1b, 4395 .global2_addr = 0x1c, 4396 .age_time_coeff = 15000, 4397 .g1_irqs = 8, 4398 .g2_irqs = 10, 4399 .atu_move_port_mask = 0xf, 4400 .pvt = true, 4401 .multi_chip = true, 4402 .tag_protocol = DSA_TAG_PROTO_EDSA, 4403 .ptp_support = true, 4404 .ops = &mv88e6320_ops, 4405 }, 4406 4407 [MV88E6321] = { 4408 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4409 .family = MV88E6XXX_FAMILY_6320, 4410 .name = "Marvell 88E6321", 4411 .num_databases = 4096, 4412 .num_ports = 7, 4413 .num_internal_phys = 5, 4414 .num_gpio = 15, 4415 .max_vid = 4095, 4416 .port_base_addr = 0x10, 4417 .phy_base_addr = 0x0, 4418 .global1_addr = 0x1b, 4419 .global2_addr = 0x1c, 4420 .age_time_coeff = 15000, 4421 .g1_irqs = 8, 4422 .g2_irqs = 10, 4423 .atu_move_port_mask = 0xf, 4424 .multi_chip = true, 4425 .tag_protocol = DSA_TAG_PROTO_EDSA, 4426 .ptp_support = true, 4427 .ops = &mv88e6321_ops, 4428 }, 4429 4430 [MV88E6341] = { 4431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4432 .family = MV88E6XXX_FAMILY_6341, 4433 .name = "Marvell 88E6341", 4434 .num_databases = 4096, 4435 .num_internal_phys = 5, 4436 .num_ports = 6, 4437 .num_gpio = 11, 4438 .max_vid = 4095, 4439 .port_base_addr = 0x10, 4440 .phy_base_addr = 0x10, 4441 .global1_addr = 0x1b, 4442 .global2_addr = 0x1c, 4443 .age_time_coeff = 3750, 4444 .atu_move_port_mask = 0x1f, 4445 .g1_irqs = 9, 4446 .g2_irqs = 10, 4447 .pvt = true, 4448 .multi_chip = true, 4449 .tag_protocol = DSA_TAG_PROTO_EDSA, 4450 .ptp_support = true, 4451 .ops = &mv88e6341_ops, 4452 }, 4453 4454 [MV88E6350] = { 4455 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4456 .family = MV88E6XXX_FAMILY_6351, 4457 .name = "Marvell 88E6350", 4458 .num_databases = 4096, 4459 .num_ports = 7, 4460 .num_internal_phys = 5, 4461 .max_vid = 4095, 4462 .port_base_addr = 0x10, 4463 .phy_base_addr = 0x0, 4464 .global1_addr = 0x1b, 4465 .global2_addr = 0x1c, 4466 .age_time_coeff = 15000, 4467 .g1_irqs = 9, 4468 .g2_irqs = 10, 4469 .atu_move_port_mask = 0xf, 4470 .pvt = true, 4471 .multi_chip = true, 4472 .tag_protocol = DSA_TAG_PROTO_EDSA, 4473 .ops = &mv88e6350_ops, 4474 }, 4475 4476 [MV88E6351] = { 4477 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4478 .family = MV88E6XXX_FAMILY_6351, 4479 .name = "Marvell 88E6351", 4480 .num_databases = 4096, 4481 .num_ports = 7, 4482 .num_internal_phys = 5, 4483 .max_vid = 4095, 4484 .port_base_addr = 0x10, 4485 .phy_base_addr = 0x0, 4486 .global1_addr = 0x1b, 4487 .global2_addr = 0x1c, 4488 .age_time_coeff = 15000, 4489 .g1_irqs = 9, 4490 .g2_irqs = 10, 4491 .atu_move_port_mask = 0xf, 4492 .pvt = true, 4493 .multi_chip = true, 4494 .tag_protocol = DSA_TAG_PROTO_EDSA, 4495 .ops = &mv88e6351_ops, 4496 }, 4497 4498 [MV88E6352] = { 4499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4500 .family = MV88E6XXX_FAMILY_6352, 4501 .name = "Marvell 88E6352", 4502 .num_databases = 4096, 4503 .num_ports = 7, 4504 .num_internal_phys = 5, 4505 .num_gpio = 15, 4506 .max_vid = 4095, 4507 .port_base_addr = 0x10, 4508 .phy_base_addr = 0x0, 4509 .global1_addr = 0x1b, 4510 .global2_addr = 0x1c, 4511 .age_time_coeff = 15000, 4512 .g1_irqs = 9, 4513 .g2_irqs = 10, 4514 .atu_move_port_mask = 0xf, 4515 .pvt = true, 4516 .multi_chip = true, 4517 .tag_protocol = DSA_TAG_PROTO_EDSA, 4518 .ptp_support = true, 4519 .ops = &mv88e6352_ops, 4520 }, 4521 [MV88E6390] = { 4522 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4523 .family = MV88E6XXX_FAMILY_6390, 4524 .name = "Marvell 88E6390", 4525 .num_databases = 4096, 4526 .num_ports = 11, /* 10 + Z80 */ 4527 .num_internal_phys = 9, 4528 .num_gpio = 16, 4529 .max_vid = 8191, 4530 .port_base_addr = 0x0, 4531 .phy_base_addr = 0x0, 4532 .global1_addr = 0x1b, 4533 .global2_addr = 0x1c, 4534 .age_time_coeff = 3750, 4535 .g1_irqs = 9, 4536 .g2_irqs = 14, 4537 .atu_move_port_mask = 0x1f, 4538 .pvt = true, 4539 .multi_chip = true, 4540 .tag_protocol = DSA_TAG_PROTO_DSA, 4541 .ptp_support = true, 4542 .ops = &mv88e6390_ops, 4543 }, 4544 [MV88E6390X] = { 4545 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4546 .family = MV88E6XXX_FAMILY_6390, 4547 .name = "Marvell 88E6390X", 4548 .num_databases = 4096, 4549 .num_ports = 11, /* 10 + Z80 */ 4550 .num_internal_phys = 9, 4551 .num_gpio = 16, 4552 .max_vid = 8191, 4553 .port_base_addr = 0x0, 4554 .phy_base_addr = 0x0, 4555 .global1_addr = 0x1b, 4556 .global2_addr = 0x1c, 4557 .age_time_coeff = 3750, 4558 .g1_irqs = 9, 4559 .g2_irqs = 14, 4560 .atu_move_port_mask = 0x1f, 4561 .pvt = true, 4562 .multi_chip = true, 4563 .tag_protocol = DSA_TAG_PROTO_DSA, 4564 .ptp_support = true, 4565 .ops = &mv88e6390x_ops, 4566 }, 4567 }; 4568 4569 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4570 { 4571 int i; 4572 4573 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4574 if (mv88e6xxx_table[i].prod_num == prod_num) 4575 return &mv88e6xxx_table[i]; 4576 4577 return NULL; 4578 } 4579 4580 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4581 { 4582 const struct mv88e6xxx_info *info; 4583 unsigned int prod_num, rev; 4584 u16 id; 4585 int err; 4586 4587 mv88e6xxx_reg_lock(chip); 4588 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4589 mv88e6xxx_reg_unlock(chip); 4590 if (err) 4591 return err; 4592 4593 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4594 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4595 4596 info = mv88e6xxx_lookup_info(prod_num); 4597 if (!info) 4598 return -ENODEV; 4599 4600 /* Update the compatible info with the probed one */ 4601 chip->info = info; 4602 4603 err = mv88e6xxx_g2_require(chip); 4604 if (err) 4605 return err; 4606 4607 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4608 chip->info->prod_num, chip->info->name, rev); 4609 4610 return 0; 4611 } 4612 4613 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4614 { 4615 struct mv88e6xxx_chip *chip; 4616 4617 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4618 if (!chip) 4619 return NULL; 4620 4621 chip->dev = dev; 4622 4623 mutex_init(&chip->reg_lock); 4624 INIT_LIST_HEAD(&chip->mdios); 4625 4626 return chip; 4627 } 4628 4629 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4630 int port) 4631 { 4632 struct mv88e6xxx_chip *chip = ds->priv; 4633 4634 return chip->info->tag_protocol; 4635 } 4636 4637 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4638 const struct switchdev_obj_port_mdb *mdb) 4639 { 4640 /* We don't need any dynamic resource from the kernel (yet), 4641 * so skip the prepare phase. 4642 */ 4643 4644 return 0; 4645 } 4646 4647 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4648 const struct switchdev_obj_port_mdb *mdb) 4649 { 4650 struct mv88e6xxx_chip *chip = ds->priv; 4651 4652 mv88e6xxx_reg_lock(chip); 4653 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4654 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4655 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4656 port); 4657 mv88e6xxx_reg_unlock(chip); 4658 } 4659 4660 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4661 const struct switchdev_obj_port_mdb *mdb) 4662 { 4663 struct mv88e6xxx_chip *chip = ds->priv; 4664 int err; 4665 4666 mv88e6xxx_reg_lock(chip); 4667 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4668 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4669 mv88e6xxx_reg_unlock(chip); 4670 4671 return err; 4672 } 4673 4674 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4675 bool unicast, bool multicast) 4676 { 4677 struct mv88e6xxx_chip *chip = ds->priv; 4678 int err = -EOPNOTSUPP; 4679 4680 mv88e6xxx_reg_lock(chip); 4681 if (chip->info->ops->port_set_egress_floods) 4682 err = chip->info->ops->port_set_egress_floods(chip, port, 4683 unicast, 4684 multicast); 4685 mv88e6xxx_reg_unlock(chip); 4686 4687 return err; 4688 } 4689 4690 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4691 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4692 .setup = mv88e6xxx_setup, 4693 .phylink_validate = mv88e6xxx_validate, 4694 .phylink_mac_link_state = mv88e6xxx_link_state, 4695 .phylink_mac_config = mv88e6xxx_mac_config, 4696 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4697 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4698 .get_strings = mv88e6xxx_get_strings, 4699 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4700 .get_sset_count = mv88e6xxx_get_sset_count, 4701 .port_enable = mv88e6xxx_port_enable, 4702 .port_disable = mv88e6xxx_port_disable, 4703 .get_mac_eee = mv88e6xxx_get_mac_eee, 4704 .set_mac_eee = mv88e6xxx_set_mac_eee, 4705 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4706 .get_eeprom = mv88e6xxx_get_eeprom, 4707 .set_eeprom = mv88e6xxx_set_eeprom, 4708 .get_regs_len = mv88e6xxx_get_regs_len, 4709 .get_regs = mv88e6xxx_get_regs, 4710 .set_ageing_time = mv88e6xxx_set_ageing_time, 4711 .port_bridge_join = mv88e6xxx_port_bridge_join, 4712 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4713 .port_egress_floods = mv88e6xxx_port_egress_floods, 4714 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4715 .port_fast_age = mv88e6xxx_port_fast_age, 4716 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4717 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4718 .port_vlan_add = mv88e6xxx_port_vlan_add, 4719 .port_vlan_del = mv88e6xxx_port_vlan_del, 4720 .port_fdb_add = mv88e6xxx_port_fdb_add, 4721 .port_fdb_del = mv88e6xxx_port_fdb_del, 4722 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4723 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4724 .port_mdb_add = mv88e6xxx_port_mdb_add, 4725 .port_mdb_del = mv88e6xxx_port_mdb_del, 4726 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4727 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4728 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4729 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4730 .port_txtstamp = mv88e6xxx_port_txtstamp, 4731 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4732 .get_ts_info = mv88e6xxx_get_ts_info, 4733 }; 4734 4735 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4736 { 4737 struct device *dev = chip->dev; 4738 struct dsa_switch *ds; 4739 4740 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4741 if (!ds) 4742 return -ENOMEM; 4743 4744 ds->priv = chip; 4745 ds->dev = dev; 4746 ds->ops = &mv88e6xxx_switch_ops; 4747 ds->ageing_time_min = chip->info->age_time_coeff; 4748 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4749 4750 dev_set_drvdata(dev, ds); 4751 4752 return dsa_register_switch(ds); 4753 } 4754 4755 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4756 { 4757 dsa_unregister_switch(chip->ds); 4758 } 4759 4760 static const void *pdata_device_get_match_data(struct device *dev) 4761 { 4762 const struct of_device_id *matches = dev->driver->of_match_table; 4763 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4764 4765 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4766 matches++) { 4767 if (!strcmp(pdata->compatible, matches->compatible)) 4768 return matches->data; 4769 } 4770 return NULL; 4771 } 4772 4773 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4774 * would be lost after a power cycle so prevent it to be suspended. 4775 */ 4776 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4777 { 4778 return -EOPNOTSUPP; 4779 } 4780 4781 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4782 { 4783 return 0; 4784 } 4785 4786 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4787 4788 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4789 { 4790 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4791 const struct mv88e6xxx_info *compat_info = NULL; 4792 struct device *dev = &mdiodev->dev; 4793 struct device_node *np = dev->of_node; 4794 struct mv88e6xxx_chip *chip; 4795 int port; 4796 int err; 4797 4798 if (!np && !pdata) 4799 return -EINVAL; 4800 4801 if (np) 4802 compat_info = of_device_get_match_data(dev); 4803 4804 if (pdata) { 4805 compat_info = pdata_device_get_match_data(dev); 4806 4807 if (!pdata->netdev) 4808 return -EINVAL; 4809 4810 for (port = 0; port < DSA_MAX_PORTS; port++) { 4811 if (!(pdata->enabled_ports & (1 << port))) 4812 continue; 4813 if (strcmp(pdata->cd.port_names[port], "cpu")) 4814 continue; 4815 pdata->cd.netdev[port] = &pdata->netdev->dev; 4816 break; 4817 } 4818 } 4819 4820 if (!compat_info) 4821 return -EINVAL; 4822 4823 chip = mv88e6xxx_alloc_chip(dev); 4824 if (!chip) { 4825 err = -ENOMEM; 4826 goto out; 4827 } 4828 4829 chip->info = compat_info; 4830 4831 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4832 if (err) 4833 goto out; 4834 4835 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4836 if (IS_ERR(chip->reset)) { 4837 err = PTR_ERR(chip->reset); 4838 goto out; 4839 } 4840 if (chip->reset) 4841 usleep_range(1000, 2000); 4842 4843 err = mv88e6xxx_detect(chip); 4844 if (err) 4845 goto out; 4846 4847 mv88e6xxx_phy_init(chip); 4848 4849 if (chip->info->ops->get_eeprom) { 4850 if (np) 4851 of_property_read_u32(np, "eeprom-length", 4852 &chip->eeprom_len); 4853 else 4854 chip->eeprom_len = pdata->eeprom_len; 4855 } 4856 4857 mv88e6xxx_reg_lock(chip); 4858 err = mv88e6xxx_switch_reset(chip); 4859 mv88e6xxx_reg_unlock(chip); 4860 if (err) 4861 goto out; 4862 4863 if (np) { 4864 chip->irq = of_irq_get(np, 0); 4865 if (chip->irq == -EPROBE_DEFER) { 4866 err = chip->irq; 4867 goto out; 4868 } 4869 } 4870 4871 if (pdata) 4872 chip->irq = pdata->irq; 4873 4874 /* Has to be performed before the MDIO bus is created, because 4875 * the PHYs will link their interrupts to these interrupt 4876 * controllers 4877 */ 4878 mv88e6xxx_reg_lock(chip); 4879 if (chip->irq > 0) 4880 err = mv88e6xxx_g1_irq_setup(chip); 4881 else 4882 err = mv88e6xxx_irq_poll_setup(chip); 4883 mv88e6xxx_reg_unlock(chip); 4884 4885 if (err) 4886 goto out; 4887 4888 if (chip->info->g2_irqs > 0) { 4889 err = mv88e6xxx_g2_irq_setup(chip); 4890 if (err) 4891 goto out_g1_irq; 4892 } 4893 4894 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4895 if (err) 4896 goto out_g2_irq; 4897 4898 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4899 if (err) 4900 goto out_g1_atu_prob_irq; 4901 4902 err = mv88e6xxx_mdios_register(chip, np); 4903 if (err) 4904 goto out_g1_vtu_prob_irq; 4905 4906 err = mv88e6xxx_register_switch(chip); 4907 if (err) 4908 goto out_mdio; 4909 4910 return 0; 4911 4912 out_mdio: 4913 mv88e6xxx_mdios_unregister(chip); 4914 out_g1_vtu_prob_irq: 4915 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4916 out_g1_atu_prob_irq: 4917 mv88e6xxx_g1_atu_prob_irq_free(chip); 4918 out_g2_irq: 4919 if (chip->info->g2_irqs > 0) 4920 mv88e6xxx_g2_irq_free(chip); 4921 out_g1_irq: 4922 if (chip->irq > 0) 4923 mv88e6xxx_g1_irq_free(chip); 4924 else 4925 mv88e6xxx_irq_poll_free(chip); 4926 out: 4927 if (pdata) 4928 dev_put(pdata->netdev); 4929 4930 return err; 4931 } 4932 4933 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4934 { 4935 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4936 struct mv88e6xxx_chip *chip = ds->priv; 4937 4938 if (chip->info->ptp_support) { 4939 mv88e6xxx_hwtstamp_free(chip); 4940 mv88e6xxx_ptp_free(chip); 4941 } 4942 4943 mv88e6xxx_phy_destroy(chip); 4944 mv88e6xxx_unregister_switch(chip); 4945 mv88e6xxx_mdios_unregister(chip); 4946 4947 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4948 mv88e6xxx_g1_atu_prob_irq_free(chip); 4949 4950 if (chip->info->g2_irqs > 0) 4951 mv88e6xxx_g2_irq_free(chip); 4952 4953 if (chip->irq > 0) 4954 mv88e6xxx_g1_irq_free(chip); 4955 else 4956 mv88e6xxx_irq_poll_free(chip); 4957 } 4958 4959 static const struct of_device_id mv88e6xxx_of_match[] = { 4960 { 4961 .compatible = "marvell,mv88e6085", 4962 .data = &mv88e6xxx_table[MV88E6085], 4963 }, 4964 { 4965 .compatible = "marvell,mv88e6190", 4966 .data = &mv88e6xxx_table[MV88E6190], 4967 }, 4968 { 4969 .compatible = "marvell,mv88e6250", 4970 .data = &mv88e6xxx_table[MV88E6250], 4971 }, 4972 { /* sentinel */ }, 4973 }; 4974 4975 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4976 4977 static struct mdio_driver mv88e6xxx_driver = { 4978 .probe = mv88e6xxx_probe, 4979 .remove = mv88e6xxx_remove, 4980 .mdiodrv.driver = { 4981 .name = "mv88e6085", 4982 .of_match_table = mv88e6xxx_of_match, 4983 .pm = &mv88e6xxx_pm_ops, 4984 }, 4985 }; 4986 4987 mdio_module_driver(mv88e6xxx_driver); 4988 4989 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4990 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4991 MODULE_LICENSE("GPL"); 4992