1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/property.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phylink.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "devlink.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "hwtstamp.h" 41 #include "phy.h" 42 #include "port.h" 43 #include "ptp.h" 44 #include "serdes.h" 45 #include "smi.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 56 { 57 int err; 58 59 assert_reg_lock(chip); 60 61 err = mv88e6xxx_smi_read(chip, addr, reg, val); 62 if (err) 63 return err; 64 65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 66 addr, reg, *val); 67 68 return 0; 69 } 70 71 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 72 { 73 int err; 74 75 assert_reg_lock(chip); 76 77 err = mv88e6xxx_smi_write(chip, addr, reg, val); 78 if (err) 79 return err; 80 81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 82 addr, reg, val); 83 84 return 0; 85 } 86 87 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 88 u16 mask, u16 val) 89 { 90 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 91 u16 data; 92 int err; 93 int i; 94 95 /* There's no bus specific operation to wait for a mask. Even 96 * if the initial poll takes longer than 50ms, always do at 97 * least one more attempt. 98 */ 99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 100 err = mv88e6xxx_read(chip, addr, reg, &data); 101 if (err) 102 return err; 103 104 if ((data & mask) == val) 105 return 0; 106 107 if (i < 2) 108 cpu_relax(); 109 else 110 usleep_range(1000, 2000); 111 } 112 113 err = mv88e6xxx_read(chip, addr, reg, &data); 114 if (err) 115 return err; 116 117 if ((data & mask) == val) 118 return 0; 119 120 dev_err(chip->dev, "Timeout while waiting for switch\n"); 121 return -ETIMEDOUT; 122 } 123 124 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 125 int bit, int val) 126 { 127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 128 val ? BIT(bit) : 0x0000); 129 } 130 131 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 132 { 133 struct mv88e6xxx_mdio_bus *mdio_bus; 134 135 mdio_bus = list_first_entry_or_null(&chip->mdios, 136 struct mv88e6xxx_mdio_bus, list); 137 if (!mdio_bus) 138 return NULL; 139 140 return mdio_bus->bus; 141 } 142 143 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked |= (1 << n); 149 } 150 151 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 152 { 153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 154 unsigned int n = d->hwirq; 155 156 chip->g1_irq.masked &= ~(1 << n); 157 } 158 159 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 160 { 161 unsigned int nhandled = 0; 162 unsigned int sub_irq; 163 unsigned int n; 164 u16 reg; 165 u16 ctl1; 166 int err; 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 170 mv88e6xxx_reg_unlock(chip); 171 172 if (err) 173 goto out; 174 175 do { 176 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 177 if (reg & (1 << n)) { 178 sub_irq = irq_find_mapping(chip->g1_irq.domain, 179 n); 180 handle_nested_irq(sub_irq); 181 ++nhandled; 182 } 183 } 184 185 mv88e6xxx_reg_lock(chip); 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 187 if (err) 188 goto unlock; 189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 190 unlock: 191 mv88e6xxx_reg_unlock(chip); 192 if (err) 193 goto out; 194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 195 } while (reg & ctl1); 196 197 out: 198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 199 } 200 201 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 202 { 203 struct mv88e6xxx_chip *chip = dev_id; 204 205 return mv88e6xxx_g1_irq_thread_work(chip); 206 } 207 208 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 209 { 210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 211 212 mv88e6xxx_reg_lock(chip); 213 } 214 215 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 216 { 217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 219 u16 reg; 220 int err; 221 222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 223 if (err) 224 goto out; 225 226 reg &= ~mask; 227 reg |= (~chip->g1_irq.masked & mask); 228 229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 230 if (err) 231 goto out; 232 233 out: 234 mv88e6xxx_reg_unlock(chip); 235 } 236 237 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 238 .name = "mv88e6xxx-g1", 239 .irq_mask = mv88e6xxx_g1_irq_mask, 240 .irq_unmask = mv88e6xxx_g1_irq_unmask, 241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 243 }; 244 245 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 246 unsigned int irq, 247 irq_hw_number_t hwirq) 248 { 249 struct mv88e6xxx_chip *chip = d->host_data; 250 251 irq_set_chip_data(irq, d->host_data); 252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 253 irq_set_noprobe(irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 259 .map = mv88e6xxx_g1_irq_domain_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 /* To be called with reg_lock held */ 264 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 265 { 266 int irq, virq; 267 u16 mask; 268 269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 274 virq = irq_find_mapping(chip->g1_irq.domain, irq); 275 irq_dispose_mapping(virq); 276 } 277 278 irq_domain_remove(chip->g1_irq.domain); 279 } 280 281 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 282 { 283 /* 284 * free_irq must be called without reg_lock taken because the irq 285 * handler takes this lock, too. 286 */ 287 free_irq(chip->irq, chip); 288 289 mv88e6xxx_reg_lock(chip); 290 mv88e6xxx_g1_irq_free_common(chip); 291 mv88e6xxx_reg_unlock(chip); 292 } 293 294 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 295 { 296 int err, irq, virq; 297 u16 reg, mask; 298 299 chip->g1_irq.nirqs = chip->info->g1_irqs; 300 chip->g1_irq.domain = irq_domain_add_simple( 301 NULL, chip->g1_irq.nirqs, 0, 302 &mv88e6xxx_g1_irq_domain_ops, chip); 303 if (!chip->g1_irq.domain) 304 return -ENOMEM; 305 306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 307 irq_create_mapping(chip->g1_irq.domain, irq); 308 309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 310 chip->g1_irq.masked = ~0; 311 312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 313 if (err) 314 goto out_mapping; 315 316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 317 318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 319 if (err) 320 goto out_disable; 321 322 /* Reading the interrupt status clears (most of) them */ 323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 324 if (err) 325 goto out_disable; 326 327 return 0; 328 329 out_disable: 330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 332 333 out_mapping: 334 for (irq = 0; irq < 16; irq++) { 335 virq = irq_find_mapping(chip->g1_irq.domain, irq); 336 irq_dispose_mapping(virq); 337 } 338 339 irq_domain_remove(chip->g1_irq.domain); 340 341 return err; 342 } 343 344 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 345 { 346 static struct lock_class_key lock_key; 347 static struct lock_class_key request_key; 348 int err; 349 350 err = mv88e6xxx_g1_irq_setup_common(chip); 351 if (err) 352 return err; 353 354 /* These lock classes tells lockdep that global 1 irqs are in 355 * a different category than their parent GPIO, so it won't 356 * report false recursion. 357 */ 358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 359 360 snprintf(chip->irq_name, sizeof(chip->irq_name), 361 "mv88e6xxx-%s", dev_name(chip->dev)); 362 363 mv88e6xxx_reg_unlock(chip); 364 err = request_threaded_irq(chip->irq, NULL, 365 mv88e6xxx_g1_irq_thread_fn, 366 IRQF_ONESHOT | IRQF_SHARED, 367 chip->irq_name, chip); 368 mv88e6xxx_reg_lock(chip); 369 if (err) 370 mv88e6xxx_g1_irq_free_common(chip); 371 372 return err; 373 } 374 375 static void mv88e6xxx_irq_poll(struct kthread_work *work) 376 { 377 struct mv88e6xxx_chip *chip = container_of(work, 378 struct mv88e6xxx_chip, 379 irq_poll_work.work); 380 mv88e6xxx_g1_irq_thread_work(chip); 381 382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 383 msecs_to_jiffies(100)); 384 } 385 386 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 387 { 388 int err; 389 390 err = mv88e6xxx_g1_irq_setup_common(chip); 391 if (err) 392 return err; 393 394 kthread_init_delayed_work(&chip->irq_poll_work, 395 mv88e6xxx_irq_poll); 396 397 chip->kworker = kthread_run_worker(0, "%s", dev_name(chip->dev)); 398 if (IS_ERR(chip->kworker)) 399 return PTR_ERR(chip->kworker); 400 401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 402 msecs_to_jiffies(100)); 403 404 return 0; 405 } 406 407 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 408 { 409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 410 kthread_destroy_worker(chip->kworker); 411 412 mv88e6xxx_reg_lock(chip); 413 mv88e6xxx_g1_irq_free_common(chip); 414 mv88e6xxx_reg_unlock(chip); 415 } 416 417 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 418 int port, phy_interface_t interface) 419 { 420 int err; 421 422 if (chip->info->ops->port_set_rgmii_delay) { 423 err = chip->info->ops->port_set_rgmii_delay(chip, port, 424 interface); 425 if (err && err != -EOPNOTSUPP) 426 return err; 427 } 428 429 if (chip->info->ops->port_set_cmode) { 430 err = chip->info->ops->port_set_cmode(chip, port, 431 interface); 432 if (err && err != -EOPNOTSUPP) 433 return err; 434 } 435 436 return 0; 437 } 438 439 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 440 int link, int speed, int duplex, int pause, 441 phy_interface_t mode) 442 { 443 int err; 444 445 if (!chip->info->ops->port_set_link) 446 return 0; 447 448 /* Port's MAC control must not be changed unless the link is down */ 449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 450 if (err) 451 return err; 452 453 if (chip->info->ops->port_set_speed_duplex) { 454 err = chip->info->ops->port_set_speed_duplex(chip, port, 455 speed, duplex); 456 if (err && err != -EOPNOTSUPP) 457 goto restore_link; 458 } 459 460 if (chip->info->ops->port_set_pause) { 461 err = chip->info->ops->port_set_pause(chip, port, pause); 462 if (err) 463 goto restore_link; 464 } 465 466 err = mv88e6xxx_port_config_interface(chip, port, mode); 467 restore_link: 468 if (chip->info->ops->port_set_link(chip, port, link)) 469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 470 471 return err; 472 } 473 474 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 475 { 476 return port >= chip->info->internal_phys_offset && 477 port < chip->info->num_internal_phys + 478 chip->info->internal_phys_offset; 479 } 480 481 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 482 { 483 u16 reg; 484 int err; 485 486 /* The 88e6250 family does not have the PHY detect bit. Instead, 487 * report whether the port is internal. 488 */ 489 if (chip->info->family == MV88E6XXX_FAMILY_6250) 490 return mv88e6xxx_phy_is_internal(chip, port); 491 492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 493 if (err) { 494 dev_err(chip->dev, 495 "p%d: %s: failed to read port status\n", 496 port, __func__); 497 return err; 498 } 499 500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 501 } 502 503 static const u8 mv88e6185_phy_interface_modes[] = { 504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 511 }; 512 513 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 514 struct phylink_config *config) 515 { 516 u8 cmode = chip->ports[port].cmode; 517 518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 519 520 if (mv88e6xxx_phy_is_internal(chip, port)) { 521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 522 } else { 523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 524 mv88e6185_phy_interface_modes[cmode]) 525 __set_bit(mv88e6185_phy_interface_modes[cmode], 526 config->supported_interfaces); 527 528 config->mac_capabilities |= MAC_1000FD; 529 } 530 } 531 532 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 533 struct phylink_config *config) 534 { 535 u8 cmode = chip->ports[port].cmode; 536 537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 538 mv88e6185_phy_interface_modes[cmode]) 539 __set_bit(mv88e6185_phy_interface_modes[cmode], 540 config->supported_interfaces); 541 542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 543 MAC_1000FD; 544 } 545 546 static const u8 mv88e6xxx_phy_interface_modes[] = { 547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 555 /* higher interface modes are not needed here, since ports supporting 556 * them are writable, and so the supported interfaces are filled in the 557 * corresponding .phylink_set_interfaces() implementation below 558 */ 559 }; 560 561 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 562 { 563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 564 mv88e6xxx_phy_interface_modes[cmode]) 565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 567 phy_interface_set_rgmii(supported); 568 } 569 570 static void 571 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 572 struct phylink_config *config) 573 { 574 unsigned long *supported = config->supported_interfaces; 575 int err; 576 u16 reg; 577 578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 579 if (err) { 580 dev_err(chip->dev, "p%d: failed to read port status\n", port); 581 return; 582 } 583 584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 590 break; 591 592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 594 __set_bit(PHY_INTERFACE_MODE_MII, supported); 595 break; 596 597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 602 break; 603 604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 606 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 607 break; 608 609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 611 break; 612 613 default: 614 dev_err(chip->dev, 615 "p%d: invalid port mode in status register: %04x\n", 616 port, reg); 617 } 618 } 619 620 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 621 struct phylink_config *config) 622 { 623 if (!mv88e6xxx_phy_is_internal(chip, port)) 624 mv88e6250_setup_supported_interfaces(chip, port, config); 625 626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 627 } 628 629 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 630 struct phylink_config *config) 631 { 632 unsigned long *supported = config->supported_interfaces; 633 634 /* Translate the default cmode */ 635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 636 637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 638 MAC_1000FD; 639 } 640 641 static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port) 642 { 643 u16 reg, val; 644 int err; 645 646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 647 if (err) 648 return err; 649 650 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 652 return 0xf; 653 654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val); 656 if (err) 657 return err; 658 659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val); 660 if (err) 661 return err; 662 663 /* Restore PHY_DETECT value */ 664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); 665 if (err) 666 return err; 667 668 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 669 } 670 671 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 672 struct phylink_config *config) 673 { 674 unsigned long *supported = config->supported_interfaces; 675 int err, cmode; 676 677 /* Translate the default cmode */ 678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 679 680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 681 MAC_1000FD; 682 683 /* Port 4 supports automedia if the serdes is associated with it. */ 684 if (port == 4) { 685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 686 if (err < 0) 687 dev_err(chip->dev, "p%d: failed to read scratch\n", 688 port); 689 if (err <= 0) 690 return; 691 692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 693 if (cmode < 0) 694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 695 port); 696 else 697 mv88e6xxx_translate_cmode(cmode, supported); 698 } 699 } 700 701 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 702 struct phylink_config *config) 703 { 704 unsigned long *supported = config->supported_interfaces; 705 int cmode; 706 707 /* Translate the default cmode */ 708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 709 710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 711 MAC_1000FD; 712 713 /* Port 0/1 are serdes only ports */ 714 if (port == 0 || port == 1) { 715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port); 716 if (cmode < 0) 717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 718 port); 719 else 720 mv88e6xxx_translate_cmode(cmode, supported); 721 } 722 } 723 724 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 725 struct phylink_config *config) 726 { 727 unsigned long *supported = config->supported_interfaces; 728 729 /* Translate the default cmode */ 730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 731 732 /* No ethtool bits for 200Mbps */ 733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 734 MAC_1000FD; 735 736 /* The C_Mode field is programmable on port 5 */ 737 if (port == 5) { 738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 742 config->mac_capabilities |= MAC_2500FD; 743 } 744 } 745 746 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 747 struct phylink_config *config) 748 { 749 unsigned long *supported = config->supported_interfaces; 750 751 /* Translate the default cmode */ 752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 753 754 /* No ethtool bits for 200Mbps */ 755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 756 MAC_1000FD; 757 758 /* The C_Mode field is programmable on ports 9 and 10 */ 759 if (port == 9 || port == 10) { 760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 763 764 config->mac_capabilities |= MAC_2500FD; 765 } 766 } 767 768 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 769 struct phylink_config *config) 770 { 771 unsigned long *supported = config->supported_interfaces; 772 773 mv88e6390_phylink_get_caps(chip, port, config); 774 775 /* For the 6x90X, ports 2-7 can be in automedia mode. 776 * (Note that 6x90 doesn't support RXAUI nor XAUI). 777 * 778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 779 * configured for 1000BASE-X, SGMII or 2500BASE-X. 780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 782 * 783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 784 * configured for 1000BASE-X, SGMII or 2500BASE-X. 785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 787 * 788 * For now, be permissive (as the old code was) and allow 1000BASE-X 789 * on ports 2..7. 790 */ 791 if (port >= 2 && port <= 7) 792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 793 794 /* The C_Mode field can also be programmed for 10G speeds */ 795 if (port == 9 || port == 10) { 796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 798 799 config->mac_capabilities |= MAC_10000FD; 800 } 801 } 802 803 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 804 struct phylink_config *config) 805 { 806 unsigned long *supported = config->supported_interfaces; 807 bool is_6191x = 808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 809 bool is_6361 = 810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 811 812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 813 814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 815 MAC_1000FD; 816 817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 818 if (port == 0 || port == 9 || port == 10) { 819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 821 822 /* 6191X supports >1G modes only on port 10 */ 823 if (!is_6191x || port == 10) { 824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 825 config->mac_capabilities |= MAC_2500FD; 826 827 /* 6361 only supports up to 2500BaseX */ 828 if (!is_6361) { 829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 832 config->mac_capabilities |= MAC_5000FD | 833 MAC_10000FD; 834 } 835 } 836 } 837 838 if (port == 0) { 839 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 844 } 845 } 846 847 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 848 struct phylink_config *config) 849 { 850 struct mv88e6xxx_chip *chip = ds->priv; 851 852 mv88e6xxx_reg_lock(chip); 853 chip->info->ops->phylink_get_caps(chip, port, config); 854 mv88e6xxx_reg_unlock(chip); 855 856 if (mv88e6xxx_phy_is_internal(chip, port)) { 857 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 858 config->supported_interfaces); 859 /* Internal ports with no phy-mode need GMII for PHYLIB */ 860 __set_bit(PHY_INTERFACE_MODE_GMII, 861 config->supported_interfaces); 862 } 863 } 864 865 static struct phylink_pcs * 866 mv88e6xxx_mac_select_pcs(struct phylink_config *config, 867 phy_interface_t interface) 868 { 869 struct dsa_port *dp = dsa_phylink_to_port(config); 870 struct mv88e6xxx_chip *chip = dp->ds->priv; 871 struct phylink_pcs *pcs = NULL; 872 873 if (chip->info->ops->pcs_ops) 874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index, 875 interface); 876 877 return pcs; 878 } 879 880 static int mv88e6xxx_mac_prepare(struct phylink_config *config, 881 unsigned int mode, phy_interface_t interface) 882 { 883 struct dsa_port *dp = dsa_phylink_to_port(config); 884 struct mv88e6xxx_chip *chip = dp->ds->priv; 885 int port = dp->index; 886 int err = 0; 887 888 /* In inband mode, the link may come up at any time while the link 889 * is not forced down. Force the link down while we reconfigure the 890 * interface mode. 891 */ 892 if (mode == MLO_AN_INBAND && 893 chip->ports[port].interface != interface && 894 chip->info->ops->port_set_link) { 895 mv88e6xxx_reg_lock(chip); 896 err = chip->info->ops->port_set_link(chip, port, 897 LINK_FORCED_DOWN); 898 mv88e6xxx_reg_unlock(chip); 899 } 900 901 return err; 902 } 903 904 static void mv88e6xxx_mac_config(struct phylink_config *config, 905 unsigned int mode, 906 const struct phylink_link_state *state) 907 { 908 struct dsa_port *dp = dsa_phylink_to_port(config); 909 struct mv88e6xxx_chip *chip = dp->ds->priv; 910 int port = dp->index; 911 int err = 0; 912 913 mv88e6xxx_reg_lock(chip); 914 915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 916 err = mv88e6xxx_port_config_interface(chip, port, 917 state->interface); 918 if (err && err != -EOPNOTSUPP) 919 goto err_unlock; 920 } 921 922 err_unlock: 923 mv88e6xxx_reg_unlock(chip); 924 925 if (err && err != -EOPNOTSUPP) 926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port); 927 } 928 929 static int mv88e6xxx_mac_finish(struct phylink_config *config, 930 unsigned int mode, phy_interface_t interface) 931 { 932 struct dsa_port *dp = dsa_phylink_to_port(config); 933 struct mv88e6xxx_chip *chip = dp->ds->priv; 934 int port = dp->index; 935 int err = 0; 936 937 /* Undo the forced down state above after completing configuration 938 * irrespective of its state on entry, which allows the link to come 939 * up in the in-band case where there is no separate SERDES. Also 940 * ensure that the link can come up if the PPU is in use and we are 941 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 942 */ 943 mv88e6xxx_reg_lock(chip); 944 945 if (chip->info->ops->port_set_link && 946 ((mode == MLO_AN_INBAND && 947 chip->ports[port].interface != interface) || 948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 950 951 mv88e6xxx_reg_unlock(chip); 952 953 chip->ports[port].interface = interface; 954 955 return err; 956 } 957 958 static void mv88e6xxx_mac_link_down(struct phylink_config *config, 959 unsigned int mode, 960 phy_interface_t interface) 961 { 962 struct dsa_port *dp = dsa_phylink_to_port(config); 963 struct mv88e6xxx_chip *chip = dp->ds->priv; 964 const struct mv88e6xxx_ops *ops; 965 int port = dp->index; 966 int err = 0; 967 968 ops = chip->info->ops; 969 970 mv88e6xxx_reg_lock(chip); 971 /* Force the link down if we know the port may not be automatically 972 * updated by the switch or if we are using fixed-link mode. 973 */ 974 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 975 mode == MLO_AN_FIXED) && ops->port_sync_link) 976 err = ops->port_sync_link(chip, port, mode, false); 977 978 if (!err && ops->port_set_speed_duplex) 979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 980 DUPLEX_UNFORCED); 981 mv88e6xxx_reg_unlock(chip); 982 983 if (err) 984 dev_err(chip->dev, 985 "p%d: failed to force MAC link down\n", port); 986 } 987 988 static void mv88e6xxx_mac_link_up(struct phylink_config *config, 989 struct phy_device *phydev, 990 unsigned int mode, phy_interface_t interface, 991 int speed, int duplex, 992 bool tx_pause, bool rx_pause) 993 { 994 struct dsa_port *dp = dsa_phylink_to_port(config); 995 struct mv88e6xxx_chip *chip = dp->ds->priv; 996 const struct mv88e6xxx_ops *ops; 997 int port = dp->index; 998 int err = 0; 999 1000 ops = chip->info->ops; 1001 1002 mv88e6xxx_reg_lock(chip); 1003 /* Configure and force the link up if we know that the port may not 1004 * automatically updated by the switch or if we are using fixed-link 1005 * mode. 1006 */ 1007 if (!mv88e6xxx_port_ppu_updates(chip, port) || 1008 mode == MLO_AN_FIXED) { 1009 if (ops->port_set_speed_duplex) { 1010 err = ops->port_set_speed_duplex(chip, port, 1011 speed, duplex); 1012 if (err && err != -EOPNOTSUPP) 1013 goto error; 1014 } 1015 1016 if (ops->port_sync_link) 1017 err = ops->port_sync_link(chip, port, mode, true); 1018 } 1019 error: 1020 mv88e6xxx_reg_unlock(chip); 1021 1022 if (err && err != -EOPNOTSUPP) 1023 dev_err(chip->dev, 1024 "p%d: failed to configure MAC link up\n", port); 1025 } 1026 1027 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1028 { 1029 int err; 1030 1031 if (!chip->info->ops->stats_snapshot) 1032 return -EOPNOTSUPP; 1033 1034 mv88e6xxx_reg_lock(chip); 1035 err = chip->info->ops->stats_snapshot(chip, port); 1036 mv88e6xxx_reg_unlock(chip); 1037 1038 return err; 1039 } 1040 1041 #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ 1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ 1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ 1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ 1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ 1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ 1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ 1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ 1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ 1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ 1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ 1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ 1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ 1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ 1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ 1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ 1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ 1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ 1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ 1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ 1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ 1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ 1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ 1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ 1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ 1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ 1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ 1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ 1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ 1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ 1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ 1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ 1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ 1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ 1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ 1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ 1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ 1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ 1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ 1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ 1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ 1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ 1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ 1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ 1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ 1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ 1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ 1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ 1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ 1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ 1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ 1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ 1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ 1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ 1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ 1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ 1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ 1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ 1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ 1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ 1101 /* */ 1102 1103 #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ 1104 { #_string, _size, _reg, _type } 1105 static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) 1107 }; 1108 1109 #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ 1110 MV88E6XXX_HW_STAT_ID_ ## _string 1111 enum mv88e6xxx_hw_stat_id { 1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) 1113 }; 1114 1115 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1116 const struct mv88e6xxx_hw_stat *s, 1117 int port, u16 bank1_select, 1118 u16 histogram) 1119 { 1120 u32 low; 1121 u32 high = 0; 1122 u16 reg = 0; 1123 int err; 1124 u64 value; 1125 1126 switch (s->type) { 1127 case STATS_TYPE_PORT: 1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1129 if (err) 1130 return U64_MAX; 1131 1132 low = reg; 1133 if (s->size == 4) { 1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1135 if (err) 1136 return U64_MAX; 1137 low |= ((u32)reg) << 16; 1138 } 1139 break; 1140 case STATS_TYPE_BANK1: 1141 reg = bank1_select; 1142 fallthrough; 1143 case STATS_TYPE_BANK0: 1144 reg |= s->reg | histogram; 1145 mv88e6xxx_g1_stats_read(chip, reg, &low); 1146 if (s->size == 8) 1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1148 break; 1149 default: 1150 return U64_MAX; 1151 } 1152 value = (((u64)high) << 32) | low; 1153 return value; 1154 } 1155 1156 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1157 uint8_t **data, int types) 1158 { 1159 const struct mv88e6xxx_hw_stat *stat; 1160 int i; 1161 1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1163 stat = &mv88e6xxx_hw_stats[i]; 1164 if (stat->type & types) 1165 ethtool_puts(data, stat->string); 1166 } 1167 } 1168 1169 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1170 uint8_t **data) 1171 { 1172 mv88e6xxx_stats_get_strings(chip, data, 1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1174 } 1175 1176 static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1177 uint8_t **data) 1178 { 1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1180 } 1181 1182 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1183 uint8_t **data) 1184 { 1185 mv88e6xxx_stats_get_strings(chip, data, 1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1187 } 1188 1189 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1190 "atu_member_violation", 1191 "atu_miss_violation", 1192 "atu_full_violation", 1193 "vtu_member_violation", 1194 "vtu_miss_violation", 1195 }; 1196 1197 static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data) 1198 { 1199 unsigned int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]); 1203 } 1204 1205 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1206 u32 stringset, uint8_t *data) 1207 { 1208 struct mv88e6xxx_chip *chip = ds->priv; 1209 1210 if (stringset != ETH_SS_STATS) 1211 return; 1212 1213 mv88e6xxx_reg_lock(chip); 1214 1215 if (chip->info->ops->stats_get_strings) 1216 chip->info->ops->stats_get_strings(chip, &data); 1217 1218 if (chip->info->ops->serdes_get_strings) 1219 chip->info->ops->serdes_get_strings(chip, port, &data); 1220 1221 mv88e6xxx_atu_vtu_get_strings(&data); 1222 1223 mv88e6xxx_reg_unlock(chip); 1224 } 1225 1226 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1227 int types) 1228 { 1229 const struct mv88e6xxx_hw_stat *stat; 1230 int i, j; 1231 1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1233 stat = &mv88e6xxx_hw_stats[i]; 1234 if (stat->type & types) 1235 j++; 1236 } 1237 return j; 1238 } 1239 1240 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1241 { 1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1243 STATS_TYPE_PORT); 1244 } 1245 1246 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1247 { 1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1249 } 1250 1251 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1252 { 1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1254 STATS_TYPE_BANK1); 1255 } 1256 1257 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1258 { 1259 struct mv88e6xxx_chip *chip = ds->priv; 1260 int serdes_count = 0; 1261 int count = 0; 1262 1263 if (sset != ETH_SS_STATS) 1264 return 0; 1265 1266 mv88e6xxx_reg_lock(chip); 1267 if (chip->info->ops->stats_get_sset_count) 1268 count = chip->info->ops->stats_get_sset_count(chip); 1269 if (count < 0) 1270 goto out; 1271 1272 if (chip->info->ops->serdes_get_sset_count) 1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1274 port); 1275 if (serdes_count < 0) { 1276 count = serdes_count; 1277 goto out; 1278 } 1279 count += serdes_count; 1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1281 1282 out: 1283 mv88e6xxx_reg_unlock(chip); 1284 1285 return count; 1286 } 1287 1288 static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1289 const struct mv88e6xxx_hw_stat *stat, 1290 uint64_t *data) 1291 { 1292 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1293 MV88E6XXX_G1_STATS_OP_HIST_RX); 1294 return 1; 1295 } 1296 1297 static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1298 const struct mv88e6xxx_hw_stat *stat, 1299 uint64_t *data) 1300 { 1301 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0, 1302 MV88E6XXX_G1_STATS_OP_HIST_RX); 1303 return 1; 1304 } 1305 1306 static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1307 const struct mv88e6xxx_hw_stat *stat, 1308 uint64_t *data) 1309 { 1310 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1311 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1312 MV88E6XXX_G1_STATS_OP_HIST_RX); 1313 return 1; 1314 } 1315 1316 static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1317 const struct mv88e6xxx_hw_stat *stat, 1318 uint64_t *data) 1319 { 1320 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1321 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1322 0); 1323 return 1; 1324 } 1325 1326 static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, 1327 const struct mv88e6xxx_hw_stat *stat, 1328 uint64_t *data) 1329 { 1330 int ret = 0; 1331 1332 if (!(stat->type & chip->info->stats_type)) 1333 return 0; 1334 1335 if (chip->info->ops->stats_get_stat) { 1336 mv88e6xxx_reg_lock(chip); 1337 ret = chip->info->ops->stats_get_stat(chip, port, stat, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 return ret; 1342 } 1343 1344 static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1345 uint64_t *data) 1346 { 1347 const struct mv88e6xxx_hw_stat *stat; 1348 size_t i, j; 1349 1350 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1351 stat = &mv88e6xxx_hw_stats[i]; 1352 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]); 1353 } 1354 return j; 1355 } 1356 1357 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1358 uint64_t *data) 1359 { 1360 *data++ = chip->ports[port].atu_member_violation; 1361 *data++ = chip->ports[port].atu_miss_violation; 1362 *data++ = chip->ports[port].atu_full_violation; 1363 *data++ = chip->ports[port].vtu_member_violation; 1364 *data++ = chip->ports[port].vtu_miss_violation; 1365 } 1366 1367 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1368 uint64_t *data) 1369 { 1370 size_t count; 1371 1372 count = mv88e6xxx_stats_get_stats(chip, port, data); 1373 1374 mv88e6xxx_reg_lock(chip); 1375 if (chip->info->ops->serdes_get_stats) { 1376 data += count; 1377 count = chip->info->ops->serdes_get_stats(chip, port, data); 1378 } 1379 data += count; 1380 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1381 mv88e6xxx_reg_unlock(chip); 1382 } 1383 1384 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1385 uint64_t *data) 1386 { 1387 struct mv88e6xxx_chip *chip = ds->priv; 1388 int ret; 1389 1390 ret = mv88e6xxx_stats_snapshot(chip, port); 1391 if (ret < 0) 1392 return; 1393 1394 mv88e6xxx_get_stats(chip, port, data); 1395 } 1396 1397 static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, 1398 struct ethtool_eth_mac_stats *mac_stats) 1399 { 1400 struct mv88e6xxx_chip *chip = ds->priv; 1401 int ret; 1402 1403 ret = mv88e6xxx_stats_snapshot(chip, port); 1404 if (ret < 0) 1405 return; 1406 1407 #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ 1408 mv88e6xxx_stats_get_stat(chip, port, \ 1409 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1410 &mac_stats->stats._member) 1411 1412 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); 1413 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); 1414 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); 1415 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); 1416 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); 1417 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); 1418 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); 1419 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); 1420 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); 1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); 1422 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); 1423 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); 1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); 1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); 1426 1427 #undef MV88E6XXX_ETH_MAC_STAT_MAP 1428 1429 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; 1430 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; 1431 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; 1432 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; 1433 } 1434 1435 static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, 1436 struct ethtool_rmon_stats *rmon_stats, 1437 const struct ethtool_rmon_hist_range **ranges) 1438 { 1439 static const struct ethtool_rmon_hist_range rmon_ranges[] = { 1440 { 64, 64 }, 1441 { 65, 127 }, 1442 { 128, 255 }, 1443 { 256, 511 }, 1444 { 512, 1023 }, 1445 { 1024, 65535 }, 1446 {} 1447 }; 1448 struct mv88e6xxx_chip *chip = ds->priv; 1449 int ret; 1450 1451 ret = mv88e6xxx_stats_snapshot(chip, port); 1452 if (ret < 0) 1453 return; 1454 1455 #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ 1456 mv88e6xxx_stats_get_stat(chip, port, \ 1457 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ 1458 &rmon_stats->stats._member) 1459 1460 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); 1461 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); 1462 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); 1463 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); 1464 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); 1465 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); 1466 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); 1467 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); 1468 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); 1469 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); 1470 1471 #undef MV88E6XXX_RMON_STAT_MAP 1472 1473 *ranges = rmon_ranges; 1474 } 1475 1476 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1477 { 1478 struct mv88e6xxx_chip *chip = ds->priv; 1479 int len; 1480 1481 len = 32 * sizeof(u16); 1482 if (chip->info->ops->serdes_get_regs_len) 1483 len += chip->info->ops->serdes_get_regs_len(chip, port); 1484 1485 return len; 1486 } 1487 1488 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1489 struct ethtool_regs *regs, void *_p) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 int err; 1493 u16 reg; 1494 u16 *p = _p; 1495 int i; 1496 1497 regs->version = chip->info->prod_num; 1498 1499 memset(p, 0xff, 32 * sizeof(u16)); 1500 1501 mv88e6xxx_reg_lock(chip); 1502 1503 for (i = 0; i < 32; i++) { 1504 1505 err = mv88e6xxx_port_read(chip, port, i, ®); 1506 if (!err) 1507 p[i] = reg; 1508 } 1509 1510 if (chip->info->ops->serdes_get_regs) 1511 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1512 1513 mv88e6xxx_reg_unlock(chip); 1514 } 1515 1516 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1517 struct ethtool_keee *e) 1518 { 1519 /* Nothing to do on the port's MAC */ 1520 return 0; 1521 } 1522 1523 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1524 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1525 { 1526 struct dsa_switch *ds = chip->ds; 1527 struct dsa_switch_tree *dst = ds->dst; 1528 struct dsa_port *dp, *other_dp; 1529 bool found = false; 1530 u16 pvlan; 1531 1532 /* dev is a physical switch */ 1533 if (dev <= dst->last_switch) { 1534 list_for_each_entry(dp, &dst->ports, list) { 1535 if (dp->ds->index == dev && dp->index == port) { 1536 /* dp might be a DSA link or a user port, so it 1537 * might or might not have a bridge. 1538 * Use the "found" variable for both cases. 1539 */ 1540 found = true; 1541 break; 1542 } 1543 } 1544 /* dev is a virtual bridge */ 1545 } else { 1546 list_for_each_entry(dp, &dst->ports, list) { 1547 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1548 1549 if (!bridge_num) 1550 continue; 1551 1552 if (bridge_num + dst->last_switch != dev) 1553 continue; 1554 1555 found = true; 1556 break; 1557 } 1558 } 1559 1560 /* Prevent frames from unknown switch or virtual bridge */ 1561 if (!found) 1562 return 0; 1563 1564 /* Frames from DSA links and CPU ports can egress any local port */ 1565 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1566 return mv88e6xxx_port_mask(chip); 1567 1568 pvlan = 0; 1569 1570 /* Frames from standalone user ports can only egress on the 1571 * upstream port. 1572 */ 1573 if (!dsa_port_bridge_dev_get(dp)) 1574 return BIT(dsa_switch_upstream_port(ds)); 1575 1576 /* Frames from bridged user ports can egress any local DSA 1577 * links and CPU ports, as well as any local member of their 1578 * bridge group. 1579 */ 1580 dsa_switch_for_each_port(other_dp, ds) 1581 if (other_dp->type == DSA_PORT_TYPE_CPU || 1582 other_dp->type == DSA_PORT_TYPE_DSA || 1583 dsa_port_bridge_same(dp, other_dp)) 1584 pvlan |= BIT(other_dp->index); 1585 1586 return pvlan; 1587 } 1588 1589 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1590 { 1591 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1592 1593 /* prevent frames from going back out of the port they came in on */ 1594 output_ports &= ~BIT(port); 1595 1596 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1597 } 1598 1599 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1600 u8 state) 1601 { 1602 struct mv88e6xxx_chip *chip = ds->priv; 1603 int err; 1604 1605 mv88e6xxx_reg_lock(chip); 1606 err = mv88e6xxx_port_set_state(chip, port, state); 1607 mv88e6xxx_reg_unlock(chip); 1608 1609 if (err) 1610 dev_err(ds->dev, "p%d: failed to update state\n", port); 1611 } 1612 1613 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1614 { 1615 int err; 1616 1617 if (chip->info->ops->ieee_pri_map) { 1618 err = chip->info->ops->ieee_pri_map(chip); 1619 if (err) 1620 return err; 1621 } 1622 1623 if (chip->info->ops->ip_pri_map) { 1624 err = chip->info->ops->ip_pri_map(chip); 1625 if (err) 1626 return err; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1633 { 1634 struct dsa_switch *ds = chip->ds; 1635 int target, port; 1636 int err; 1637 1638 if (!chip->info->global2_addr) 1639 return 0; 1640 1641 /* Initialize the routing port to the 32 possible target devices */ 1642 for (target = 0; target < 32; target++) { 1643 port = dsa_routing_port(ds, target); 1644 if (port == ds->num_ports) 1645 port = 0x1f; 1646 1647 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1648 if (err) 1649 return err; 1650 } 1651 1652 if (chip->info->ops->set_cascade_port) { 1653 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1654 err = chip->info->ops->set_cascade_port(chip, port); 1655 if (err) 1656 return err; 1657 } 1658 1659 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1660 if (err) 1661 return err; 1662 1663 return 0; 1664 } 1665 1666 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1667 { 1668 /* Clear all trunk masks and mapping */ 1669 if (chip->info->global2_addr) 1670 return mv88e6xxx_g2_trunk_clear(chip); 1671 1672 return 0; 1673 } 1674 1675 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1676 { 1677 if (chip->info->ops->rmu_disable) 1678 return chip->info->ops->rmu_disable(chip); 1679 1680 return 0; 1681 } 1682 1683 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1684 { 1685 if (chip->info->ops->pot_clear) 1686 return chip->info->ops->pot_clear(chip); 1687 1688 return 0; 1689 } 1690 1691 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1692 { 1693 if (chip->info->ops->mgmt_rsvd2cpu) 1694 return chip->info->ops->mgmt_rsvd2cpu(chip); 1695 1696 return 0; 1697 } 1698 1699 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1700 { 1701 int err; 1702 1703 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1704 if (err) 1705 return err; 1706 1707 /* The chips that have a "learn2all" bit in Global1, ATU 1708 * Control are precisely those whose port registers have a 1709 * Message Port bit in Port Control 1 and hence implement 1710 * ->port_setup_message_port. 1711 */ 1712 if (chip->info->ops->port_setup_message_port) { 1713 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1714 if (err) 1715 return err; 1716 } 1717 1718 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1719 } 1720 1721 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1722 { 1723 int port; 1724 int err; 1725 1726 if (!chip->info->ops->irl_init_all) 1727 return 0; 1728 1729 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1730 /* Disable ingress rate limiting by resetting all per port 1731 * ingress rate limit resources to their initial state. 1732 */ 1733 err = chip->info->ops->irl_init_all(chip, port); 1734 if (err) 1735 return err; 1736 } 1737 1738 return 0; 1739 } 1740 1741 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1742 { 1743 if (chip->info->ops->set_switch_mac) { 1744 u8 addr[ETH_ALEN]; 1745 1746 eth_random_addr(addr); 1747 1748 return chip->info->ops->set_switch_mac(chip, addr); 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1755 { 1756 struct dsa_switch_tree *dst = chip->ds->dst; 1757 struct dsa_switch *ds; 1758 struct dsa_port *dp; 1759 u16 pvlan = 0; 1760 1761 if (!mv88e6xxx_has_pvt(chip)) 1762 return 0; 1763 1764 /* Skip the local source device, which uses in-chip port VLAN */ 1765 if (dev != chip->ds->index) { 1766 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1767 1768 ds = dsa_switch_find(dst->index, dev); 1769 dp = ds ? dsa_to_port(ds, port) : NULL; 1770 if (dp && dp->lag) { 1771 /* As the PVT is used to limit flooding of 1772 * FORWARD frames, which use the LAG ID as the 1773 * source port, we must translate dev/port to 1774 * the special "LAG device" in the PVT, using 1775 * the LAG ID (one-based) as the port number 1776 * (zero-based). 1777 */ 1778 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1779 port = dsa_port_lag_id_get(dp) - 1; 1780 } 1781 } 1782 1783 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1784 } 1785 1786 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1787 { 1788 int dev, port; 1789 int err; 1790 1791 if (!mv88e6xxx_has_pvt(chip)) 1792 return 0; 1793 1794 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1795 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1796 */ 1797 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1798 if (err) 1799 return err; 1800 1801 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1802 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1803 err = mv88e6xxx_pvt_map(chip, dev, port); 1804 if (err) 1805 return err; 1806 } 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1813 u16 fid) 1814 { 1815 if (dsa_to_port(chip->ds, port)->lag) 1816 /* Hardware is incapable of fast-aging a LAG through a 1817 * regular ATU move operation. Until we have something 1818 * more fancy in place this is a no-op. 1819 */ 1820 return -EOPNOTSUPP; 1821 1822 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1823 } 1824 1825 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1826 { 1827 struct mv88e6xxx_chip *chip = ds->priv; 1828 int err; 1829 1830 mv88e6xxx_reg_lock(chip); 1831 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1832 mv88e6xxx_reg_unlock(chip); 1833 1834 if (err) 1835 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1836 port, err); 1837 } 1838 1839 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1840 { 1841 if (!mv88e6xxx_max_vid(chip)) 1842 return 0; 1843 1844 return mv88e6xxx_g1_vtu_flush(chip); 1845 } 1846 1847 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1848 struct mv88e6xxx_vtu_entry *entry) 1849 { 1850 int err; 1851 1852 if (!chip->info->ops->vtu_getnext) 1853 return -EOPNOTSUPP; 1854 1855 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1856 entry->valid = false; 1857 1858 err = chip->info->ops->vtu_getnext(chip, entry); 1859 1860 if (entry->vid != vid) 1861 entry->valid = false; 1862 1863 return err; 1864 } 1865 1866 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1867 int (*cb)(struct mv88e6xxx_chip *chip, 1868 const struct mv88e6xxx_vtu_entry *entry, 1869 void *priv), 1870 void *priv) 1871 { 1872 struct mv88e6xxx_vtu_entry entry = { 1873 .vid = mv88e6xxx_max_vid(chip), 1874 .valid = false, 1875 }; 1876 int err; 1877 1878 if (!chip->info->ops->vtu_getnext) 1879 return -EOPNOTSUPP; 1880 1881 do { 1882 err = chip->info->ops->vtu_getnext(chip, &entry); 1883 if (err) 1884 return err; 1885 1886 if (!entry.valid) 1887 break; 1888 1889 err = cb(chip, &entry, priv); 1890 if (err) 1891 return err; 1892 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1893 1894 return 0; 1895 } 1896 1897 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1898 struct mv88e6xxx_vtu_entry *entry) 1899 { 1900 if (!chip->info->ops->vtu_loadpurge) 1901 return -EOPNOTSUPP; 1902 1903 return chip->info->ops->vtu_loadpurge(chip, entry); 1904 } 1905 1906 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1907 { 1908 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID); 1909 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1910 return -ENOSPC; 1911 1912 /* Clear the database */ 1913 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1914 } 1915 1916 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1917 struct mv88e6xxx_stu_entry *entry) 1918 { 1919 if (!chip->info->ops->stu_loadpurge) 1920 return -EOPNOTSUPP; 1921 1922 return chip->info->ops->stu_loadpurge(chip, entry); 1923 } 1924 1925 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1926 { 1927 struct mv88e6xxx_stu_entry stu = { 1928 .valid = true, 1929 .sid = 0 1930 }; 1931 1932 if (!mv88e6xxx_has_stu(chip)) 1933 return 0; 1934 1935 /* Make sure that SID 0 is always valid. This is used by VTU 1936 * entries that do not make use of the STU, e.g. when creating 1937 * a VLAN upper on a port that is also part of a VLAN 1938 * filtering bridge. 1939 */ 1940 return mv88e6xxx_stu_loadpurge(chip, &stu); 1941 } 1942 1943 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1944 { 1945 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1946 struct mv88e6xxx_mst *mst; 1947 1948 __set_bit(0, busy); 1949 1950 list_for_each_entry(mst, &chip->msts, node) 1951 __set_bit(mst->stu.sid, busy); 1952 1953 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1954 1955 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1956 } 1957 1958 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1959 { 1960 struct mv88e6xxx_mst *mst, *tmp; 1961 int err; 1962 1963 if (!sid) 1964 return 0; 1965 1966 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1967 if (mst->stu.sid != sid) 1968 continue; 1969 1970 if (!refcount_dec_and_test(&mst->refcnt)) 1971 return 0; 1972 1973 mst->stu.valid = false; 1974 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1975 if (err) { 1976 refcount_set(&mst->refcnt, 1); 1977 return err; 1978 } 1979 1980 list_del(&mst->node); 1981 kfree(mst); 1982 return 0; 1983 } 1984 1985 return -ENOENT; 1986 } 1987 1988 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1989 u16 msti, u8 *sid) 1990 { 1991 struct mv88e6xxx_mst *mst; 1992 int err, i; 1993 1994 if (!mv88e6xxx_has_stu(chip)) { 1995 err = -EOPNOTSUPP; 1996 goto err; 1997 } 1998 1999 if (!msti) { 2000 *sid = 0; 2001 return 0; 2002 } 2003 2004 list_for_each_entry(mst, &chip->msts, node) { 2005 if (mst->br == br && mst->msti == msti) { 2006 refcount_inc(&mst->refcnt); 2007 *sid = mst->stu.sid; 2008 return 0; 2009 } 2010 } 2011 2012 err = mv88e6xxx_sid_get(chip, sid); 2013 if (err) 2014 goto err; 2015 2016 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 2017 if (!mst) { 2018 err = -ENOMEM; 2019 goto err; 2020 } 2021 2022 INIT_LIST_HEAD(&mst->node); 2023 refcount_set(&mst->refcnt, 1); 2024 mst->br = br; 2025 mst->msti = msti; 2026 mst->stu.valid = true; 2027 mst->stu.sid = *sid; 2028 2029 /* The bridge starts out all ports in the disabled state. But 2030 * a STU state of disabled means to go by the port-global 2031 * state. So we set all user port's initial state to blocking, 2032 * to match the bridge's behavior. 2033 */ 2034 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 2035 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 2036 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 2037 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 2038 2039 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2040 if (err) 2041 goto err_free; 2042 2043 list_add_tail(&mst->node, &chip->msts); 2044 return 0; 2045 2046 err_free: 2047 kfree(mst); 2048 err: 2049 return err; 2050 } 2051 2052 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 2053 const struct switchdev_mst_state *st) 2054 { 2055 struct dsa_port *dp = dsa_to_port(ds, port); 2056 struct mv88e6xxx_chip *chip = ds->priv; 2057 struct mv88e6xxx_mst *mst; 2058 u8 state; 2059 int err; 2060 2061 if (!mv88e6xxx_has_stu(chip)) 2062 return -EOPNOTSUPP; 2063 2064 switch (st->state) { 2065 case BR_STATE_DISABLED: 2066 case BR_STATE_BLOCKING: 2067 case BR_STATE_LISTENING: 2068 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 2069 break; 2070 case BR_STATE_LEARNING: 2071 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 2072 break; 2073 case BR_STATE_FORWARDING: 2074 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2075 break; 2076 default: 2077 return -EINVAL; 2078 } 2079 2080 list_for_each_entry(mst, &chip->msts, node) { 2081 if (mst->br == dsa_port_bridge_dev_get(dp) && 2082 mst->msti == st->msti) { 2083 if (mst->stu.state[port] == state) 2084 return 0; 2085 2086 mst->stu.state[port] = state; 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2089 mv88e6xxx_reg_unlock(chip); 2090 return err; 2091 } 2092 } 2093 2094 return -ENOENT; 2095 } 2096 2097 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2098 u16 vid) 2099 { 2100 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2101 struct mv88e6xxx_chip *chip = ds->priv; 2102 struct mv88e6xxx_vtu_entry vlan; 2103 int err; 2104 2105 /* DSA and CPU ports have to be members of multiple vlans */ 2106 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2107 return 0; 2108 2109 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2110 if (err) 2111 return err; 2112 2113 if (!vlan.valid) 2114 return 0; 2115 2116 dsa_switch_for_each_user_port(other_dp, ds) { 2117 struct net_device *other_br; 2118 2119 if (vlan.member[other_dp->index] == 2120 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2121 continue; 2122 2123 if (dsa_port_bridge_same(dp, other_dp)) 2124 break; /* same bridge, check next VLAN */ 2125 2126 other_br = dsa_port_bridge_dev_get(other_dp); 2127 if (!other_br) 2128 continue; 2129 2130 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2131 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2132 return -EOPNOTSUPP; 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2139 { 2140 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2141 struct net_device *br = dsa_port_bridge_dev_get(dp); 2142 struct mv88e6xxx_port *p = &chip->ports[port]; 2143 u16 pvid = MV88E6XXX_VID_STANDALONE; 2144 bool drop_untagged = false; 2145 int err; 2146 2147 if (br) { 2148 if (br_vlan_enabled(br)) { 2149 pvid = p->bridge_pvid.vid; 2150 drop_untagged = !p->bridge_pvid.valid; 2151 } else { 2152 pvid = MV88E6XXX_VID_BRIDGED; 2153 } 2154 } 2155 2156 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2157 if (err) 2158 return err; 2159 2160 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2161 } 2162 2163 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2164 bool vlan_filtering, 2165 struct netlink_ext_ack *extack) 2166 { 2167 struct mv88e6xxx_chip *chip = ds->priv; 2168 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2169 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2170 int err; 2171 2172 if (!mv88e6xxx_max_vid(chip)) 2173 return -EOPNOTSUPP; 2174 2175 mv88e6xxx_reg_lock(chip); 2176 2177 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2178 if (err) 2179 goto unlock; 2180 2181 err = mv88e6xxx_port_commit_pvid(chip, port); 2182 if (err) 2183 goto unlock; 2184 2185 unlock: 2186 mv88e6xxx_reg_unlock(chip); 2187 2188 return err; 2189 } 2190 2191 static int 2192 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2193 const struct switchdev_obj_port_vlan *vlan) 2194 { 2195 struct mv88e6xxx_chip *chip = ds->priv; 2196 int err; 2197 2198 if (!mv88e6xxx_max_vid(chip)) 2199 return -EOPNOTSUPP; 2200 2201 /* If the requested port doesn't belong to the same bridge as the VLAN 2202 * members, do not support it (yet) and fallback to software VLAN. 2203 */ 2204 mv88e6xxx_reg_lock(chip); 2205 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2206 mv88e6xxx_reg_unlock(chip); 2207 2208 return err; 2209 } 2210 2211 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2212 const unsigned char *addr, u16 vid, 2213 u8 state) 2214 { 2215 struct mv88e6xxx_atu_entry entry; 2216 struct mv88e6xxx_vtu_entry vlan; 2217 u16 fid; 2218 int err; 2219 2220 /* Ports have two private address databases: one for when the port is 2221 * standalone and one for when the port is under a bridge and the 2222 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2223 * address database to remain 100% empty, so we never load an ATU entry 2224 * into a standalone port's database. Therefore, translate the null 2225 * VLAN ID into the port's database used for VLAN-unaware bridging. 2226 */ 2227 if (vid == 0) { 2228 fid = MV88E6XXX_FID_BRIDGED; 2229 } else { 2230 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2231 if (err) 2232 return err; 2233 2234 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2235 if (!vlan.valid) 2236 return -EOPNOTSUPP; 2237 2238 fid = vlan.fid; 2239 } 2240 2241 entry.state = 0; 2242 ether_addr_copy(entry.mac, addr); 2243 eth_addr_dec(entry.mac); 2244 2245 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2246 if (err) 2247 return err; 2248 2249 /* Initialize a fresh ATU entry if it isn't found */ 2250 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2251 memset(&entry, 0, sizeof(entry)); 2252 ether_addr_copy(entry.mac, addr); 2253 } 2254 2255 /* Purge the ATU entry only if no port is using it anymore */ 2256 if (!state) { 2257 entry.portvec &= ~BIT(port); 2258 if (!entry.portvec) 2259 entry.state = 0; 2260 } else { 2261 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2262 entry.portvec = BIT(port); 2263 else 2264 entry.portvec |= BIT(port); 2265 2266 entry.state = state; 2267 } 2268 2269 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2270 } 2271 2272 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2273 const struct mv88e6xxx_policy *policy) 2274 { 2275 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2276 enum mv88e6xxx_policy_action action = policy->action; 2277 const u8 *addr = policy->addr; 2278 u16 vid = policy->vid; 2279 u8 state; 2280 int err; 2281 int id; 2282 2283 if (!chip->info->ops->port_set_policy) 2284 return -EOPNOTSUPP; 2285 2286 switch (mapping) { 2287 case MV88E6XXX_POLICY_MAPPING_DA: 2288 case MV88E6XXX_POLICY_MAPPING_SA: 2289 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2290 state = 0; /* Dissociate the port and address */ 2291 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2292 is_multicast_ether_addr(addr)) 2293 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2294 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2295 is_unicast_ether_addr(addr)) 2296 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2297 else 2298 return -EOPNOTSUPP; 2299 2300 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2301 state); 2302 if (err) 2303 return err; 2304 break; 2305 default: 2306 return -EOPNOTSUPP; 2307 } 2308 2309 /* Skip the port's policy clearing if the mapping is still in use */ 2310 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2311 idr_for_each_entry(&chip->policies, policy, id) 2312 if (policy->port == port && 2313 policy->mapping == mapping && 2314 policy->action != action) 2315 return 0; 2316 2317 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2318 } 2319 2320 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2321 struct ethtool_rx_flow_spec *fs) 2322 { 2323 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2324 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2325 enum mv88e6xxx_policy_mapping mapping; 2326 enum mv88e6xxx_policy_action action; 2327 struct mv88e6xxx_policy *policy; 2328 u16 vid = 0; 2329 u8 *addr; 2330 int err; 2331 int id; 2332 2333 if (fs->location != RX_CLS_LOC_ANY) 2334 return -EINVAL; 2335 2336 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2337 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2338 else 2339 return -EOPNOTSUPP; 2340 2341 switch (fs->flow_type & ~FLOW_EXT) { 2342 case ETHER_FLOW: 2343 if (!is_zero_ether_addr(mac_mask->h_dest) && 2344 is_zero_ether_addr(mac_mask->h_source)) { 2345 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2346 addr = mac_entry->h_dest; 2347 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2348 !is_zero_ether_addr(mac_mask->h_source)) { 2349 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2350 addr = mac_entry->h_source; 2351 } else { 2352 /* Cannot support DA and SA mapping in the same rule */ 2353 return -EOPNOTSUPP; 2354 } 2355 break; 2356 default: 2357 return -EOPNOTSUPP; 2358 } 2359 2360 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2361 if (fs->m_ext.vlan_tci != htons(0xffff)) 2362 return -EOPNOTSUPP; 2363 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2364 } 2365 2366 idr_for_each_entry(&chip->policies, policy, id) { 2367 if (policy->port == port && policy->mapping == mapping && 2368 policy->action == action && policy->vid == vid && 2369 ether_addr_equal(policy->addr, addr)) 2370 return -EEXIST; 2371 } 2372 2373 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2374 if (!policy) 2375 return -ENOMEM; 2376 2377 fs->location = 0; 2378 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2379 GFP_KERNEL); 2380 if (err) { 2381 devm_kfree(chip->dev, policy); 2382 return err; 2383 } 2384 2385 memcpy(&policy->fs, fs, sizeof(*fs)); 2386 ether_addr_copy(policy->addr, addr); 2387 policy->mapping = mapping; 2388 policy->action = action; 2389 policy->port = port; 2390 policy->vid = vid; 2391 2392 err = mv88e6xxx_policy_apply(chip, port, policy); 2393 if (err) { 2394 idr_remove(&chip->policies, fs->location); 2395 devm_kfree(chip->dev, policy); 2396 return err; 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2403 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2404 { 2405 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2406 struct mv88e6xxx_chip *chip = ds->priv; 2407 struct mv88e6xxx_policy *policy; 2408 int err; 2409 int id; 2410 2411 mv88e6xxx_reg_lock(chip); 2412 2413 switch (rxnfc->cmd) { 2414 case ETHTOOL_GRXCLSRLCNT: 2415 rxnfc->data = 0; 2416 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2417 rxnfc->rule_cnt = 0; 2418 idr_for_each_entry(&chip->policies, policy, id) 2419 if (policy->port == port) 2420 rxnfc->rule_cnt++; 2421 err = 0; 2422 break; 2423 case ETHTOOL_GRXCLSRULE: 2424 err = -ENOENT; 2425 policy = idr_find(&chip->policies, fs->location); 2426 if (policy) { 2427 memcpy(fs, &policy->fs, sizeof(*fs)); 2428 err = 0; 2429 } 2430 break; 2431 case ETHTOOL_GRXCLSRLALL: 2432 rxnfc->data = 0; 2433 rxnfc->rule_cnt = 0; 2434 idr_for_each_entry(&chip->policies, policy, id) 2435 if (policy->port == port) 2436 rule_locs[rxnfc->rule_cnt++] = id; 2437 err = 0; 2438 break; 2439 default: 2440 err = -EOPNOTSUPP; 2441 break; 2442 } 2443 2444 mv88e6xxx_reg_unlock(chip); 2445 2446 return err; 2447 } 2448 2449 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2450 struct ethtool_rxnfc *rxnfc) 2451 { 2452 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2453 struct mv88e6xxx_chip *chip = ds->priv; 2454 struct mv88e6xxx_policy *policy; 2455 int err; 2456 2457 mv88e6xxx_reg_lock(chip); 2458 2459 switch (rxnfc->cmd) { 2460 case ETHTOOL_SRXCLSRLINS: 2461 err = mv88e6xxx_policy_insert(chip, port, fs); 2462 break; 2463 case ETHTOOL_SRXCLSRLDEL: 2464 err = -ENOENT; 2465 policy = idr_remove(&chip->policies, fs->location); 2466 if (policy) { 2467 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2468 err = mv88e6xxx_policy_apply(chip, port, policy); 2469 devm_kfree(chip->dev, policy); 2470 } 2471 break; 2472 default: 2473 err = -EOPNOTSUPP; 2474 break; 2475 } 2476 2477 mv88e6xxx_reg_unlock(chip); 2478 2479 return err; 2480 } 2481 2482 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2483 u16 vid) 2484 { 2485 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2486 u8 broadcast[ETH_ALEN]; 2487 2488 eth_broadcast_addr(broadcast); 2489 2490 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2491 } 2492 2493 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2494 { 2495 int port; 2496 int err; 2497 2498 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2499 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2500 struct net_device *brport; 2501 2502 if (dsa_is_unused_port(chip->ds, port)) 2503 continue; 2504 2505 brport = dsa_port_to_bridge_port(dp); 2506 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2507 /* Skip bridged user ports where broadcast 2508 * flooding is disabled. 2509 */ 2510 continue; 2511 2512 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2513 if (err) 2514 return err; 2515 } 2516 2517 return 0; 2518 } 2519 2520 struct mv88e6xxx_port_broadcast_sync_ctx { 2521 int port; 2522 bool flood; 2523 }; 2524 2525 static int 2526 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2527 const struct mv88e6xxx_vtu_entry *vlan, 2528 void *_ctx) 2529 { 2530 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2531 u8 broadcast[ETH_ALEN]; 2532 u8 state; 2533 2534 if (ctx->flood) 2535 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2536 else 2537 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2538 2539 eth_broadcast_addr(broadcast); 2540 2541 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2542 vlan->vid, state); 2543 } 2544 2545 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2546 bool flood) 2547 { 2548 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2549 .port = port, 2550 .flood = flood, 2551 }; 2552 struct mv88e6xxx_vtu_entry vid0 = { 2553 .vid = 0, 2554 }; 2555 int err; 2556 2557 /* Update the port's private database... */ 2558 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2559 if (err) 2560 return err; 2561 2562 /* ...and the database for all VLANs. */ 2563 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2564 &ctx); 2565 } 2566 2567 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2568 u16 vid, u8 member, bool warn) 2569 { 2570 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2571 struct mv88e6xxx_vtu_entry vlan; 2572 int i, err; 2573 2574 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2575 if (err) 2576 return err; 2577 2578 if (!vlan.valid) { 2579 memset(&vlan, 0, sizeof(vlan)); 2580 2581 if (vid == MV88E6XXX_VID_STANDALONE) 2582 vlan.policy = true; 2583 2584 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2585 if (err) 2586 return err; 2587 2588 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2589 if (i == port) 2590 vlan.member[i] = member; 2591 else 2592 vlan.member[i] = non_member; 2593 2594 vlan.vid = vid; 2595 vlan.valid = true; 2596 2597 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2598 if (err) 2599 return err; 2600 2601 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2602 if (err) 2603 return err; 2604 } else if (vlan.member[port] != member) { 2605 vlan.member[port] = member; 2606 2607 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2608 if (err) 2609 return err; 2610 } else if (warn) { 2611 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2612 port, vid); 2613 } 2614 2615 /* Record FID used in SW FID map */ 2616 bitmap_set(chip->fid_bitmap, vlan.fid, 1); 2617 2618 return 0; 2619 } 2620 2621 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2622 const struct switchdev_obj_port_vlan *vlan, 2623 struct netlink_ext_ack *extack) 2624 { 2625 struct mv88e6xxx_chip *chip = ds->priv; 2626 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2627 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2628 struct mv88e6xxx_port *p = &chip->ports[port]; 2629 bool warn; 2630 u8 member; 2631 int err; 2632 2633 if (!vlan->vid) 2634 return 0; 2635 2636 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2637 if (err) 2638 return err; 2639 2640 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2641 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2642 else if (untagged) 2643 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2644 else 2645 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2646 2647 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port 2648 * and then the CPU port. Do not warn for duplicates for the CPU port. 2649 */ 2650 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2651 2652 mv88e6xxx_reg_lock(chip); 2653 2654 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2655 if (err) { 2656 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2657 vlan->vid, untagged ? 'u' : 't'); 2658 goto out; 2659 } 2660 2661 if (pvid) { 2662 p->bridge_pvid.vid = vlan->vid; 2663 p->bridge_pvid.valid = true; 2664 2665 err = mv88e6xxx_port_commit_pvid(chip, port); 2666 if (err) 2667 goto out; 2668 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2669 /* The old pvid was reinstalled as a non-pvid VLAN */ 2670 p->bridge_pvid.valid = false; 2671 2672 err = mv88e6xxx_port_commit_pvid(chip, port); 2673 if (err) 2674 goto out; 2675 } 2676 2677 out: 2678 mv88e6xxx_reg_unlock(chip); 2679 2680 return err; 2681 } 2682 2683 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2684 int port, u16 vid) 2685 { 2686 struct mv88e6xxx_vtu_entry vlan; 2687 int i, err; 2688 2689 if (!vid) 2690 return 0; 2691 2692 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2693 if (err) 2694 return err; 2695 2696 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2697 * tell switchdev that this VLAN is likely handled in software. 2698 */ 2699 if (!vlan.valid || 2700 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2701 return -EOPNOTSUPP; 2702 2703 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2704 2705 /* keep the VLAN unless all ports are excluded */ 2706 vlan.valid = false; 2707 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2708 if (vlan.member[i] != 2709 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2710 vlan.valid = true; 2711 break; 2712 } 2713 } 2714 2715 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2716 if (err) 2717 return err; 2718 2719 if (!vlan.valid) { 2720 err = mv88e6xxx_mst_put(chip, vlan.sid); 2721 if (err) 2722 return err; 2723 2724 /* Record FID freed in SW FID map */ 2725 bitmap_clear(chip->fid_bitmap, vlan.fid, 1); 2726 } 2727 2728 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2729 } 2730 2731 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2732 const struct switchdev_obj_port_vlan *vlan) 2733 { 2734 struct mv88e6xxx_chip *chip = ds->priv; 2735 struct mv88e6xxx_port *p = &chip->ports[port]; 2736 int err = 0; 2737 u16 pvid; 2738 2739 if (!mv88e6xxx_max_vid(chip)) 2740 return -EOPNOTSUPP; 2741 2742 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2743 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2744 * switchdev workqueue to ensure that all FDB entries are deleted 2745 * before we remove the VLAN. 2746 */ 2747 dsa_flush_workqueue(); 2748 2749 mv88e6xxx_reg_lock(chip); 2750 2751 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2752 if (err) 2753 goto unlock; 2754 2755 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2756 if (err) 2757 goto unlock; 2758 2759 if (vlan->vid == pvid) { 2760 p->bridge_pvid.valid = false; 2761 2762 err = mv88e6xxx_port_commit_pvid(chip, port); 2763 if (err) 2764 goto unlock; 2765 } 2766 2767 unlock: 2768 mv88e6xxx_reg_unlock(chip); 2769 2770 return err; 2771 } 2772 2773 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2774 { 2775 struct mv88e6xxx_chip *chip = ds->priv; 2776 struct mv88e6xxx_vtu_entry vlan; 2777 int err; 2778 2779 mv88e6xxx_reg_lock(chip); 2780 2781 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2782 if (err) 2783 goto unlock; 2784 2785 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2786 2787 unlock: 2788 mv88e6xxx_reg_unlock(chip); 2789 2790 return err; 2791 } 2792 2793 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2794 struct dsa_bridge bridge, 2795 const struct switchdev_vlan_msti *msti) 2796 { 2797 struct mv88e6xxx_chip *chip = ds->priv; 2798 struct mv88e6xxx_vtu_entry vlan; 2799 u8 old_sid, new_sid; 2800 int err; 2801 2802 if (!mv88e6xxx_has_stu(chip)) 2803 return -EOPNOTSUPP; 2804 2805 mv88e6xxx_reg_lock(chip); 2806 2807 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2808 if (err) 2809 goto unlock; 2810 2811 if (!vlan.valid) { 2812 err = -EINVAL; 2813 goto unlock; 2814 } 2815 2816 old_sid = vlan.sid; 2817 2818 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2819 if (err) 2820 goto unlock; 2821 2822 if (new_sid != old_sid) { 2823 vlan.sid = new_sid; 2824 2825 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2826 if (err) { 2827 mv88e6xxx_mst_put(chip, new_sid); 2828 goto unlock; 2829 } 2830 } 2831 2832 err = mv88e6xxx_mst_put(chip, old_sid); 2833 2834 unlock: 2835 mv88e6xxx_reg_unlock(chip); 2836 return err; 2837 } 2838 2839 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2840 const unsigned char *addr, u16 vid, 2841 struct dsa_db db) 2842 { 2843 struct mv88e6xxx_chip *chip = ds->priv; 2844 int err; 2845 2846 mv88e6xxx_reg_lock(chip); 2847 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2848 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2849 mv88e6xxx_reg_unlock(chip); 2850 2851 return err; 2852 } 2853 2854 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2855 const unsigned char *addr, u16 vid, 2856 struct dsa_db db) 2857 { 2858 struct mv88e6xxx_chip *chip = ds->priv; 2859 int err; 2860 2861 mv88e6xxx_reg_lock(chip); 2862 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2863 mv88e6xxx_reg_unlock(chip); 2864 2865 return err; 2866 } 2867 2868 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2869 u16 fid, u16 vid, int port, 2870 dsa_fdb_dump_cb_t *cb, void *data) 2871 { 2872 struct mv88e6xxx_atu_entry addr; 2873 bool is_static; 2874 int err; 2875 2876 addr.state = 0; 2877 eth_broadcast_addr(addr.mac); 2878 2879 do { 2880 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2881 if (err) 2882 return err; 2883 2884 if (!addr.state) 2885 break; 2886 2887 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2888 continue; 2889 2890 if (!is_unicast_ether_addr(addr.mac)) 2891 continue; 2892 2893 is_static = (addr.state == 2894 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2895 err = cb(addr.mac, vid, is_static, data); 2896 if (err) 2897 return err; 2898 } while (!is_broadcast_ether_addr(addr.mac)); 2899 2900 return err; 2901 } 2902 2903 struct mv88e6xxx_port_db_dump_vlan_ctx { 2904 int port; 2905 dsa_fdb_dump_cb_t *cb; 2906 void *data; 2907 }; 2908 2909 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2910 const struct mv88e6xxx_vtu_entry *entry, 2911 void *_data) 2912 { 2913 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2914 2915 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2916 ctx->port, ctx->cb, ctx->data); 2917 } 2918 2919 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2920 dsa_fdb_dump_cb_t *cb, void *data) 2921 { 2922 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2923 .port = port, 2924 .cb = cb, 2925 .data = data, 2926 }; 2927 u16 fid; 2928 int err; 2929 2930 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2931 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2932 if (err) 2933 return err; 2934 2935 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2936 if (err) 2937 return err; 2938 2939 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2940 } 2941 2942 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2943 dsa_fdb_dump_cb_t *cb, void *data) 2944 { 2945 struct mv88e6xxx_chip *chip = ds->priv; 2946 int err; 2947 2948 mv88e6xxx_reg_lock(chip); 2949 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2950 mv88e6xxx_reg_unlock(chip); 2951 2952 return err; 2953 } 2954 2955 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2956 struct dsa_bridge bridge) 2957 { 2958 struct dsa_switch *ds = chip->ds; 2959 struct dsa_switch_tree *dst = ds->dst; 2960 struct dsa_port *dp; 2961 int err; 2962 2963 list_for_each_entry(dp, &dst->ports, list) { 2964 if (dsa_port_offloads_bridge(dp, &bridge)) { 2965 if (dp->ds == ds) { 2966 /* This is a local bridge group member, 2967 * remap its Port VLAN Map. 2968 */ 2969 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2970 if (err) 2971 return err; 2972 } else { 2973 /* This is an external bridge group member, 2974 * remap its cross-chip Port VLAN Table entry. 2975 */ 2976 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2977 dp->index); 2978 if (err) 2979 return err; 2980 } 2981 } 2982 } 2983 2984 return 0; 2985 } 2986 2987 /* Treat the software bridge as a virtual single-port switch behind the 2988 * CPU and map in the PVT. First dst->last_switch elements are taken by 2989 * physical switches, so start from beyond that range. 2990 */ 2991 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2992 unsigned int bridge_num) 2993 { 2994 u8 dev = bridge_num + ds->dst->last_switch; 2995 struct mv88e6xxx_chip *chip = ds->priv; 2996 2997 return mv88e6xxx_pvt_map(chip, dev, 0); 2998 } 2999 3000 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 3001 struct dsa_bridge bridge, 3002 bool *tx_fwd_offload, 3003 struct netlink_ext_ack *extack) 3004 { 3005 struct mv88e6xxx_chip *chip = ds->priv; 3006 int err; 3007 3008 mv88e6xxx_reg_lock(chip); 3009 3010 err = mv88e6xxx_bridge_map(chip, bridge); 3011 if (err) 3012 goto unlock; 3013 3014 err = mv88e6xxx_port_set_map_da(chip, port, true); 3015 if (err) 3016 goto unlock; 3017 3018 err = mv88e6xxx_port_commit_pvid(chip, port); 3019 if (err) 3020 goto unlock; 3021 3022 if (mv88e6xxx_has_pvt(chip)) { 3023 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3024 if (err) 3025 goto unlock; 3026 3027 *tx_fwd_offload = true; 3028 } 3029 3030 unlock: 3031 mv88e6xxx_reg_unlock(chip); 3032 3033 return err; 3034 } 3035 3036 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 3037 struct dsa_bridge bridge) 3038 { 3039 struct mv88e6xxx_chip *chip = ds->priv; 3040 int err; 3041 3042 mv88e6xxx_reg_lock(chip); 3043 3044 if (bridge.tx_fwd_offload && 3045 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3046 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3047 3048 if (mv88e6xxx_bridge_map(chip, bridge) || 3049 mv88e6xxx_port_vlan_map(chip, port)) 3050 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 3051 3052 err = mv88e6xxx_port_set_map_da(chip, port, false); 3053 if (err) 3054 dev_err(ds->dev, 3055 "port %d failed to restore map-DA: %pe\n", 3056 port, ERR_PTR(err)); 3057 3058 err = mv88e6xxx_port_commit_pvid(chip, port); 3059 if (err) 3060 dev_err(ds->dev, 3061 "port %d failed to restore standalone pvid: %pe\n", 3062 port, ERR_PTR(err)); 3063 3064 mv88e6xxx_reg_unlock(chip); 3065 } 3066 3067 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 3068 int tree_index, int sw_index, 3069 int port, struct dsa_bridge bridge, 3070 struct netlink_ext_ack *extack) 3071 { 3072 struct mv88e6xxx_chip *chip = ds->priv; 3073 int err; 3074 3075 if (tree_index != ds->dst->index) 3076 return 0; 3077 3078 mv88e6xxx_reg_lock(chip); 3079 err = mv88e6xxx_pvt_map(chip, sw_index, port); 3080 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 3081 mv88e6xxx_reg_unlock(chip); 3082 3083 return err; 3084 } 3085 3086 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3087 int tree_index, int sw_index, 3088 int port, struct dsa_bridge bridge) 3089 { 3090 struct mv88e6xxx_chip *chip = ds->priv; 3091 3092 if (tree_index != ds->dst->index) 3093 return; 3094 3095 mv88e6xxx_reg_lock(chip); 3096 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3097 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3098 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3099 mv88e6xxx_reg_unlock(chip); 3100 } 3101 3102 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3103 { 3104 if (chip->info->ops->reset) 3105 return chip->info->ops->reset(chip); 3106 3107 return 0; 3108 } 3109 3110 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3111 { 3112 struct gpio_desc *gpiod = chip->reset; 3113 int err; 3114 3115 /* If there is a GPIO connected to the reset pin, toggle it */ 3116 if (gpiod) { 3117 /* If the switch has just been reset and not yet completed 3118 * loading EEPROM, the reset may interrupt the I2C transaction 3119 * mid-byte, causing the first EEPROM read after the reset 3120 * from the wrong location resulting in the switch booting 3121 * to wrong mode and inoperable. 3122 * For this reason, switch families with EEPROM support 3123 * generally wait for EEPROM loads to complete as their pre- 3124 * and post-reset handlers. 3125 */ 3126 if (chip->info->ops->hardware_reset_pre) { 3127 err = chip->info->ops->hardware_reset_pre(chip); 3128 if (err) 3129 dev_err(chip->dev, "pre-reset error: %d\n", err); 3130 } 3131 3132 gpiod_set_value_cansleep(gpiod, 1); 3133 usleep_range(10000, 20000); 3134 gpiod_set_value_cansleep(gpiod, 0); 3135 usleep_range(10000, 20000); 3136 3137 if (chip->info->ops->hardware_reset_post) { 3138 err = chip->info->ops->hardware_reset_post(chip); 3139 if (err) 3140 dev_err(chip->dev, "post-reset error: %d\n", err); 3141 } 3142 } 3143 } 3144 3145 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3146 { 3147 int i, err; 3148 3149 /* Set all ports to the Disabled state */ 3150 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3151 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3152 if (err) 3153 return err; 3154 } 3155 3156 /* Wait for transmit queues to drain, 3157 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3158 */ 3159 usleep_range(2000, 4000); 3160 3161 return 0; 3162 } 3163 3164 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3165 { 3166 int err; 3167 3168 err = mv88e6xxx_disable_ports(chip); 3169 if (err) 3170 return err; 3171 3172 mv88e6xxx_hardware_reset(chip); 3173 3174 return mv88e6xxx_software_reset(chip); 3175 } 3176 3177 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3178 enum mv88e6xxx_frame_mode frame, 3179 enum mv88e6xxx_egress_mode egress, u16 etype) 3180 { 3181 int err; 3182 3183 if (!chip->info->ops->port_set_frame_mode) 3184 return -EOPNOTSUPP; 3185 3186 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3187 if (err) 3188 return err; 3189 3190 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3191 if (err) 3192 return err; 3193 3194 if (chip->info->ops->port_set_ether_type) 3195 return chip->info->ops->port_set_ether_type(chip, port, etype); 3196 3197 return 0; 3198 } 3199 3200 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3201 { 3202 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3203 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3204 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3205 } 3206 3207 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3208 { 3209 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3210 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3211 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3212 } 3213 3214 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3215 { 3216 return mv88e6xxx_set_port_mode(chip, port, 3217 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3218 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3219 ETH_P_EDSA); 3220 } 3221 3222 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3223 { 3224 if (dsa_is_dsa_port(chip->ds, port)) 3225 return mv88e6xxx_set_port_mode_dsa(chip, port); 3226 3227 if (dsa_is_user_port(chip->ds, port)) 3228 return mv88e6xxx_set_port_mode_normal(chip, port); 3229 3230 /* Setup CPU port mode depending on its supported tag format */ 3231 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3232 return mv88e6xxx_set_port_mode_dsa(chip, port); 3233 3234 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3235 return mv88e6xxx_set_port_mode_edsa(chip, port); 3236 3237 return -EINVAL; 3238 } 3239 3240 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3241 { 3242 bool message = dsa_is_dsa_port(chip->ds, port); 3243 3244 return mv88e6xxx_port_set_message_port(chip, port, message); 3245 } 3246 3247 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3248 { 3249 int err; 3250 3251 if (chip->info->ops->port_set_ucast_flood) { 3252 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3253 if (err) 3254 return err; 3255 } 3256 if (chip->info->ops->port_set_mcast_flood) { 3257 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3258 if (err) 3259 return err; 3260 } 3261 3262 return 0; 3263 } 3264 3265 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3266 enum mv88e6xxx_egress_direction direction, 3267 int port) 3268 { 3269 int err; 3270 3271 if (!chip->info->ops->set_egress_port) 3272 return -EOPNOTSUPP; 3273 3274 err = chip->info->ops->set_egress_port(chip, direction, port); 3275 if (err) 3276 return err; 3277 3278 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3279 chip->ingress_dest_port = port; 3280 else 3281 chip->egress_dest_port = port; 3282 3283 return 0; 3284 } 3285 3286 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3287 { 3288 struct dsa_switch *ds = chip->ds; 3289 int upstream_port; 3290 int err; 3291 3292 upstream_port = dsa_upstream_port(ds, port); 3293 if (chip->info->ops->port_set_upstream_port) { 3294 err = chip->info->ops->port_set_upstream_port(chip, port, 3295 upstream_port); 3296 if (err) 3297 return err; 3298 } 3299 3300 if (port == upstream_port) { 3301 if (chip->info->ops->set_cpu_port) { 3302 err = chip->info->ops->set_cpu_port(chip, 3303 upstream_port); 3304 if (err) 3305 return err; 3306 } 3307 3308 err = mv88e6xxx_set_egress_port(chip, 3309 MV88E6XXX_EGRESS_DIR_INGRESS, 3310 upstream_port); 3311 if (err && err != -EOPNOTSUPP) 3312 return err; 3313 3314 err = mv88e6xxx_set_egress_port(chip, 3315 MV88E6XXX_EGRESS_DIR_EGRESS, 3316 upstream_port); 3317 if (err && err != -EOPNOTSUPP) 3318 return err; 3319 } 3320 3321 return 0; 3322 } 3323 3324 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3325 { 3326 struct device_node *phy_handle = NULL; 3327 struct fwnode_handle *ports_fwnode; 3328 struct fwnode_handle *port_fwnode; 3329 struct dsa_switch *ds = chip->ds; 3330 struct mv88e6xxx_port *p; 3331 struct dsa_port *dp; 3332 int tx_amp; 3333 int err; 3334 u16 reg; 3335 u32 val; 3336 3337 p = &chip->ports[port]; 3338 p->chip = chip; 3339 p->port = port; 3340 3341 /* Look up corresponding fwnode if any */ 3342 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports"); 3343 if (!ports_fwnode) 3344 ports_fwnode = device_get_named_child_node(chip->dev, "ports"); 3345 if (ports_fwnode) { 3346 fwnode_for_each_child_node(ports_fwnode, port_fwnode) { 3347 if (fwnode_property_read_u32(port_fwnode, "reg", &val)) 3348 continue; 3349 if (val == port) { 3350 p->fwnode = port_fwnode; 3351 p->fiber = fwnode_property_present(port_fwnode, "sfp"); 3352 break; 3353 } 3354 } 3355 fwnode_handle_put(ports_fwnode); 3356 } else { 3357 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n"); 3358 } 3359 3360 if (chip->info->ops->port_setup_leds) { 3361 err = chip->info->ops->port_setup_leds(chip, port); 3362 if (err && err != -EOPNOTSUPP) 3363 return err; 3364 } 3365 3366 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3367 SPEED_UNFORCED, DUPLEX_UNFORCED, 3368 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3369 if (err) 3370 return err; 3371 3372 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3373 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3374 * tunneling, determine priority by looking at 802.1p and IP 3375 * priority fields (IP prio has precedence), and set STP state 3376 * to Forwarding. 3377 * 3378 * If this is the CPU link, use DSA or EDSA tagging depending 3379 * on which tagging mode was configured. 3380 * 3381 * If this is a link to another switch, use DSA tagging mode. 3382 * 3383 * If this is the upstream port for this switch, enable 3384 * forwarding of unknown unicasts and multicasts. 3385 */ 3386 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3387 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3388 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3389 * by a USER port to the CPU port to allow snooping. 3390 */ 3391 if (dsa_is_user_port(ds, port)) 3392 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3393 3394 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3395 if (err) 3396 return err; 3397 3398 err = mv88e6xxx_setup_port_mode(chip, port); 3399 if (err) 3400 return err; 3401 3402 err = mv88e6xxx_setup_egress_floods(chip, port); 3403 if (err) 3404 return err; 3405 3406 /* Port Control 2: don't force a good FCS, set the MTU size to 3407 * 10222 bytes, disable 802.1q tags checking, don't discard 3408 * tagged or untagged frames on this port, skip destination 3409 * address lookup on user ports, disable ARP mirroring and don't 3410 * send a copy of all transmitted/received frames on this port 3411 * to the CPU. 3412 */ 3413 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3414 if (err) 3415 return err; 3416 3417 err = mv88e6xxx_setup_upstream_port(chip, port); 3418 if (err) 3419 return err; 3420 3421 /* On chips that support it, set all downstream DSA ports' 3422 * VLAN policy to TRAP. In combination with loading 3423 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3424 * provides a better isolation barrier between standalone 3425 * ports, as the ATU is bypassed on any intermediate switches 3426 * between the incoming port and the CPU. 3427 */ 3428 if (dsa_is_downstream_port(ds, port) && 3429 chip->info->ops->port_set_policy) { 3430 err = chip->info->ops->port_set_policy(chip, port, 3431 MV88E6XXX_POLICY_MAPPING_VTU, 3432 MV88E6XXX_POLICY_ACTION_TRAP); 3433 if (err) 3434 return err; 3435 } 3436 3437 /* User ports start out in standalone mode and 802.1Q is 3438 * therefore disabled. On DSA ports, all valid VIDs are always 3439 * loaded in the VTU - therefore, enable 802.1Q in order to take 3440 * advantage of VLAN policy on chips that supports it. 3441 */ 3442 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3443 dsa_is_user_port(ds, port) ? 3444 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3445 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3446 if (err) 3447 return err; 3448 3449 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3450 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3451 * the first free FID. This will be used as the private PVID for 3452 * unbridged ports. Shared (DSA and CPU) ports must also be 3453 * members of this VID, in order to trap all frames assigned to 3454 * it to the CPU. 3455 */ 3456 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3457 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3458 false); 3459 if (err) 3460 return err; 3461 3462 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3463 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3464 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3465 * as the private PVID on ports under a VLAN-unaware bridge. 3466 * Shared (DSA and CPU) ports must also be members of it, to translate 3467 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3468 * relying on their port default FID. 3469 */ 3470 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3471 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3472 false); 3473 if (err) 3474 return err; 3475 3476 if (chip->info->ops->port_set_jumbo_size) { 3477 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3478 if (err) 3479 return err; 3480 } 3481 3482 /* Port Association Vector: disable automatic address learning 3483 * on all user ports since they start out in standalone 3484 * mode. When joining a bridge, learning will be configured to 3485 * match the bridge port settings. Enable learning on all 3486 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3487 * learning process. 3488 * 3489 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3490 * and RefreshLocked. I.e. setup standard automatic learning. 3491 */ 3492 if (dsa_is_user_port(ds, port)) 3493 reg = 0; 3494 else 3495 reg = 1 << port; 3496 3497 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3498 reg); 3499 if (err) 3500 return err; 3501 3502 /* Egress rate control 2: disable egress rate control. */ 3503 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3504 0x0000); 3505 if (err) 3506 return err; 3507 3508 if (chip->info->ops->port_pause_limit) { 3509 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3510 if (err) 3511 return err; 3512 } 3513 3514 if (chip->info->ops->port_disable_learn_limit) { 3515 err = chip->info->ops->port_disable_learn_limit(chip, port); 3516 if (err) 3517 return err; 3518 } 3519 3520 if (chip->info->ops->port_disable_pri_override) { 3521 err = chip->info->ops->port_disable_pri_override(chip, port); 3522 if (err) 3523 return err; 3524 } 3525 3526 if (chip->info->ops->port_tag_remap) { 3527 err = chip->info->ops->port_tag_remap(chip, port); 3528 if (err) 3529 return err; 3530 } 3531 3532 if (chip->info->ops->port_egress_rate_limiting) { 3533 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3534 if (err) 3535 return err; 3536 } 3537 3538 if (chip->info->ops->port_setup_message_port) { 3539 err = chip->info->ops->port_setup_message_port(chip, port); 3540 if (err) 3541 return err; 3542 } 3543 3544 if (chip->info->ops->serdes_set_tx_amplitude) { 3545 dp = dsa_to_port(ds, port); 3546 if (dp) 3547 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3548 3549 if (phy_handle && !of_property_read_u32(phy_handle, 3550 "tx-p2p-microvolt", 3551 &tx_amp)) 3552 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3553 port, tx_amp); 3554 if (phy_handle) { 3555 of_node_put(phy_handle); 3556 if (err) 3557 return err; 3558 } 3559 } 3560 3561 /* Port based VLAN map: give each port the same default address 3562 * database, and allow bidirectional communication between the 3563 * CPU and DSA port(s), and the other ports. 3564 */ 3565 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3566 if (err) 3567 return err; 3568 3569 err = mv88e6xxx_port_vlan_map(chip, port); 3570 if (err) 3571 return err; 3572 3573 /* Default VLAN ID and priority: don't set a default VLAN 3574 * ID, and set the default packet priority to zero. 3575 */ 3576 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3577 } 3578 3579 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3580 { 3581 struct mv88e6xxx_chip *chip = ds->priv; 3582 3583 if (chip->info->ops->port_set_jumbo_size) 3584 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3585 else if (chip->info->ops->set_max_frame_size) 3586 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3587 return ETH_DATA_LEN; 3588 } 3589 3590 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3591 { 3592 struct mv88e6xxx_chip *chip = ds->priv; 3593 int ret = 0; 3594 3595 /* For families where we don't know how to alter the MTU, 3596 * just accept any value up to ETH_DATA_LEN 3597 */ 3598 if (!chip->info->ops->port_set_jumbo_size && 3599 !chip->info->ops->set_max_frame_size) { 3600 if (new_mtu > ETH_DATA_LEN) 3601 return -EINVAL; 3602 3603 return 0; 3604 } 3605 3606 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3607 new_mtu += EDSA_HLEN; 3608 3609 mv88e6xxx_reg_lock(chip); 3610 if (chip->info->ops->port_set_jumbo_size) 3611 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3612 else if (chip->info->ops->set_max_frame_size && 3613 dsa_is_cpu_port(ds, port)) 3614 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3615 mv88e6xxx_reg_unlock(chip); 3616 3617 return ret; 3618 } 3619 3620 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3621 unsigned int ageing_time) 3622 { 3623 struct mv88e6xxx_chip *chip = ds->priv; 3624 int err; 3625 3626 mv88e6xxx_reg_lock(chip); 3627 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3628 mv88e6xxx_reg_unlock(chip); 3629 3630 return err; 3631 } 3632 3633 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3634 { 3635 int err; 3636 3637 /* Initialize the statistics unit */ 3638 if (chip->info->ops->stats_set_histogram) { 3639 err = chip->info->ops->stats_set_histogram(chip); 3640 if (err) 3641 return err; 3642 } 3643 3644 return mv88e6xxx_g1_stats_clear(chip); 3645 } 3646 3647 /* Check if the errata has already been applied. */ 3648 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3649 { 3650 int port; 3651 int err; 3652 u16 val; 3653 3654 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3655 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3656 if (err) { 3657 dev_err(chip->dev, 3658 "Error reading hidden register: %d\n", err); 3659 return false; 3660 } 3661 if (val != 0x01c0) 3662 return false; 3663 } 3664 3665 return true; 3666 } 3667 3668 /* The 6390 copper ports have an errata which require poking magic 3669 * values into undocumented hidden registers and then performing a 3670 * software reset. 3671 */ 3672 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3673 { 3674 int port; 3675 int err; 3676 3677 if (mv88e6390_setup_errata_applied(chip)) 3678 return 0; 3679 3680 /* Set the ports into blocking mode */ 3681 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3682 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3683 if (err) 3684 return err; 3685 } 3686 3687 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3688 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3689 if (err) 3690 return err; 3691 } 3692 3693 return mv88e6xxx_software_reset(chip); 3694 } 3695 3696 /* prod_id for switch families which do not have a PHY model number */ 3697 static const u16 family_prod_id_table[] = { 3698 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3699 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3700 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3701 }; 3702 3703 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3704 { 3705 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3706 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3707 u16 prod_id; 3708 u16 val; 3709 int err; 3710 3711 if (!chip->info->ops->phy_read) 3712 return -EOPNOTSUPP; 3713 3714 mv88e6xxx_reg_lock(chip); 3715 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3716 mv88e6xxx_reg_unlock(chip); 3717 3718 /* Some internal PHYs don't have a model number. */ 3719 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3720 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3721 prod_id = family_prod_id_table[chip->info->family]; 3722 if (prod_id) 3723 val |= prod_id >> 4; 3724 } 3725 3726 return err ? err : val; 3727 } 3728 3729 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3730 int reg) 3731 { 3732 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3733 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3734 u16 val; 3735 int err; 3736 3737 if (!chip->info->ops->phy_read_c45) 3738 return -ENODEV; 3739 3740 mv88e6xxx_reg_lock(chip); 3741 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3742 mv88e6xxx_reg_unlock(chip); 3743 3744 return err ? err : val; 3745 } 3746 3747 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3748 { 3749 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3750 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3751 int err; 3752 3753 if (!chip->info->ops->phy_write) 3754 return -EOPNOTSUPP; 3755 3756 mv88e6xxx_reg_lock(chip); 3757 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3758 mv88e6xxx_reg_unlock(chip); 3759 3760 return err; 3761 } 3762 3763 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3764 int reg, u16 val) 3765 { 3766 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3767 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3768 int err; 3769 3770 if (!chip->info->ops->phy_write_c45) 3771 return -EOPNOTSUPP; 3772 3773 mv88e6xxx_reg_lock(chip); 3774 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3775 mv88e6xxx_reg_unlock(chip); 3776 3777 return err; 3778 } 3779 3780 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3781 struct device_node *np, 3782 bool external) 3783 { 3784 static int index; 3785 struct mv88e6xxx_mdio_bus *mdio_bus; 3786 struct mii_bus *bus; 3787 int err; 3788 3789 if (external) { 3790 mv88e6xxx_reg_lock(chip); 3791 if (chip->info->family == MV88E6XXX_FAMILY_6393) 3792 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true); 3793 else 3794 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true); 3795 mv88e6xxx_reg_unlock(chip); 3796 3797 if (err) 3798 return err; 3799 } 3800 3801 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3802 if (!bus) 3803 return -ENOMEM; 3804 3805 mdio_bus = bus->priv; 3806 mdio_bus->bus = bus; 3807 mdio_bus->chip = chip; 3808 INIT_LIST_HEAD(&mdio_bus->list); 3809 mdio_bus->external = external; 3810 3811 if (np) { 3812 bus->name = np->full_name; 3813 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3814 } else { 3815 bus->name = "mv88e6xxx SMI"; 3816 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3817 } 3818 3819 bus->read = mv88e6xxx_mdio_read; 3820 bus->write = mv88e6xxx_mdio_write; 3821 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3822 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3823 bus->parent = chip->dev; 3824 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3825 mv88e6xxx_num_ports(chip) - 1, 3826 chip->info->phy_base_addr); 3827 3828 if (!external) { 3829 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3830 if (err) 3831 goto out; 3832 } 3833 3834 err = of_mdiobus_register(bus, np); 3835 if (err) { 3836 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3837 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3838 goto out; 3839 } 3840 3841 if (external) 3842 list_add_tail(&mdio_bus->list, &chip->mdios); 3843 else 3844 list_add(&mdio_bus->list, &chip->mdios); 3845 3846 return 0; 3847 3848 out: 3849 mdiobus_free(bus); 3850 return err; 3851 } 3852 3853 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3854 3855 { 3856 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3857 struct mii_bus *bus; 3858 3859 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3860 bus = mdio_bus->bus; 3861 3862 if (!mdio_bus->external) 3863 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3864 3865 mdiobus_unregister(bus); 3866 mdiobus_free(bus); 3867 } 3868 } 3869 3870 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3871 { 3872 struct device_node *np = chip->dev->of_node; 3873 struct device_node *child; 3874 int err; 3875 3876 /* Always register one mdio bus for the internal/default mdio 3877 * bus. This maybe represented in the device tree, but is 3878 * optional. 3879 */ 3880 child = of_get_child_by_name(np, "mdio"); 3881 err = mv88e6xxx_mdio_register(chip, child, false); 3882 of_node_put(child); 3883 if (err) 3884 return err; 3885 3886 /* Walk the device tree, and see if there are any other nodes 3887 * which say they are compatible with the external mdio 3888 * bus. 3889 */ 3890 for_each_available_child_of_node(np, child) { 3891 if (of_device_is_compatible( 3892 child, "marvell,mv88e6xxx-mdio-external")) { 3893 err = mv88e6xxx_mdio_register(chip, child, true); 3894 if (err) { 3895 mv88e6xxx_mdios_unregister(chip); 3896 of_node_put(child); 3897 return err; 3898 } 3899 } 3900 } 3901 3902 return 0; 3903 } 3904 3905 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3906 { 3907 struct mv88e6xxx_chip *chip = ds->priv; 3908 3909 mv88e6xxx_teardown_devlink_params(ds); 3910 dsa_devlink_resources_unregister(ds); 3911 mv88e6xxx_teardown_devlink_regions_global(ds); 3912 mv88e6xxx_mdios_unregister(chip); 3913 } 3914 3915 static int mv88e6xxx_setup(struct dsa_switch *ds) 3916 { 3917 struct mv88e6xxx_chip *chip = ds->priv; 3918 u8 cmode; 3919 int err; 3920 int i; 3921 3922 err = mv88e6xxx_mdios_register(chip); 3923 if (err) 3924 return err; 3925 3926 chip->ds = ds; 3927 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3928 3929 /* Since virtual bridges are mapped in the PVT, the number we support 3930 * depends on the physical switch topology. We need to let DSA figure 3931 * that out and therefore we cannot set this at dsa_register_switch() 3932 * time. 3933 */ 3934 if (mv88e6xxx_has_pvt(chip)) 3935 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3936 ds->dst->last_switch - 1; 3937 3938 mv88e6xxx_reg_lock(chip); 3939 3940 if (chip->info->ops->setup_errata) { 3941 err = chip->info->ops->setup_errata(chip); 3942 if (err) 3943 goto unlock; 3944 } 3945 3946 /* Cache the cmode of each port. */ 3947 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3948 if (chip->info->ops->port_get_cmode) { 3949 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3950 if (err) 3951 goto unlock; 3952 3953 chip->ports[i].cmode = cmode; 3954 } 3955 } 3956 3957 err = mv88e6xxx_vtu_setup(chip); 3958 if (err) 3959 goto unlock; 3960 3961 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3962 * VTU, thereby also flushing the STU). 3963 */ 3964 err = mv88e6xxx_stu_setup(chip); 3965 if (err) 3966 goto unlock; 3967 3968 /* Setup Switch Port Registers */ 3969 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3970 if (dsa_is_unused_port(ds, i)) 3971 continue; 3972 3973 /* Prevent the use of an invalid port. */ 3974 if (mv88e6xxx_is_invalid_port(chip, i)) { 3975 dev_err(chip->dev, "port %d is invalid\n", i); 3976 err = -EINVAL; 3977 goto unlock; 3978 } 3979 3980 err = mv88e6xxx_setup_port(chip, i); 3981 if (err) 3982 goto unlock; 3983 } 3984 3985 err = mv88e6xxx_irl_setup(chip); 3986 if (err) 3987 goto unlock; 3988 3989 err = mv88e6xxx_mac_setup(chip); 3990 if (err) 3991 goto unlock; 3992 3993 err = mv88e6xxx_phy_setup(chip); 3994 if (err) 3995 goto unlock; 3996 3997 err = mv88e6xxx_pvt_setup(chip); 3998 if (err) 3999 goto unlock; 4000 4001 err = mv88e6xxx_atu_setup(chip); 4002 if (err) 4003 goto unlock; 4004 4005 err = mv88e6xxx_broadcast_setup(chip, 0); 4006 if (err) 4007 goto unlock; 4008 4009 err = mv88e6xxx_pot_setup(chip); 4010 if (err) 4011 goto unlock; 4012 4013 err = mv88e6xxx_rmu_setup(chip); 4014 if (err) 4015 goto unlock; 4016 4017 err = mv88e6xxx_rsvd2cpu_setup(chip); 4018 if (err) 4019 goto unlock; 4020 4021 err = mv88e6xxx_trunk_setup(chip); 4022 if (err) 4023 goto unlock; 4024 4025 err = mv88e6xxx_devmap_setup(chip); 4026 if (err) 4027 goto unlock; 4028 4029 err = mv88e6xxx_pri_setup(chip); 4030 if (err) 4031 goto unlock; 4032 4033 /* Setup PTP Hardware Clock and timestamping */ 4034 if (chip->info->ptp_support) { 4035 err = mv88e6xxx_ptp_setup(chip); 4036 if (err) 4037 goto unlock; 4038 4039 err = mv88e6xxx_hwtstamp_setup(chip); 4040 if (err) 4041 goto unlock; 4042 } 4043 4044 err = mv88e6xxx_stats_setup(chip); 4045 if (err) 4046 goto unlock; 4047 4048 unlock: 4049 mv88e6xxx_reg_unlock(chip); 4050 4051 if (err) 4052 goto out_mdios; 4053 4054 /* Have to be called without holding the register lock, since 4055 * they take the devlink lock, and we later take the locks in 4056 * the reverse order when getting/setting parameters or 4057 * resource occupancy. 4058 */ 4059 err = mv88e6xxx_setup_devlink_resources(ds); 4060 if (err) 4061 goto out_mdios; 4062 4063 err = mv88e6xxx_setup_devlink_params(ds); 4064 if (err) 4065 goto out_resources; 4066 4067 err = mv88e6xxx_setup_devlink_regions_global(ds); 4068 if (err) 4069 goto out_params; 4070 4071 return 0; 4072 4073 out_params: 4074 mv88e6xxx_teardown_devlink_params(ds); 4075 out_resources: 4076 dsa_devlink_resources_unregister(ds); 4077 out_mdios: 4078 mv88e6xxx_mdios_unregister(chip); 4079 4080 return err; 4081 } 4082 4083 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4084 { 4085 struct mv88e6xxx_chip *chip = ds->priv; 4086 int err; 4087 4088 if (chip->info->ops->pcs_ops && 4089 chip->info->ops->pcs_ops->pcs_init) { 4090 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 4091 if (err) 4092 return err; 4093 } 4094 4095 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4096 } 4097 4098 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4099 { 4100 struct mv88e6xxx_chip *chip = ds->priv; 4101 4102 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4103 4104 if (chip->info->ops->pcs_ops && 4105 chip->info->ops->pcs_ops->pcs_teardown) 4106 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 4107 } 4108 4109 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4110 { 4111 struct mv88e6xxx_chip *chip = ds->priv; 4112 4113 return chip->eeprom_len; 4114 } 4115 4116 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4117 struct ethtool_eeprom *eeprom, u8 *data) 4118 { 4119 struct mv88e6xxx_chip *chip = ds->priv; 4120 int err; 4121 4122 if (!chip->info->ops->get_eeprom) 4123 return -EOPNOTSUPP; 4124 4125 mv88e6xxx_reg_lock(chip); 4126 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4127 mv88e6xxx_reg_unlock(chip); 4128 4129 if (err) 4130 return err; 4131 4132 eeprom->magic = 0xc3ec4951; 4133 4134 return 0; 4135 } 4136 4137 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4138 struct ethtool_eeprom *eeprom, u8 *data) 4139 { 4140 struct mv88e6xxx_chip *chip = ds->priv; 4141 int err; 4142 4143 if (!chip->info->ops->set_eeprom) 4144 return -EOPNOTSUPP; 4145 4146 if (eeprom->magic != 0xc3ec4951) 4147 return -EINVAL; 4148 4149 mv88e6xxx_reg_lock(chip); 4150 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4151 mv88e6xxx_reg_unlock(chip); 4152 4153 return err; 4154 } 4155 4156 static const struct mv88e6xxx_ops mv88e6085_ops = { 4157 /* MV88E6XXX_FAMILY_6097 */ 4158 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4159 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4160 .irl_init_all = mv88e6352_g2_irl_init_all, 4161 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4162 .phy_read = mv88e6185_phy_ppu_read, 4163 .phy_write = mv88e6185_phy_ppu_write, 4164 .port_set_link = mv88e6xxx_port_set_link, 4165 .port_sync_link = mv88e6xxx_port_sync_link, 4166 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4167 .port_tag_remap = mv88e6095_port_tag_remap, 4168 .port_set_policy = mv88e6352_port_set_policy, 4169 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4170 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4171 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4172 .port_set_ether_type = mv88e6351_port_set_ether_type, 4173 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4174 .port_pause_limit = mv88e6097_port_pause_limit, 4175 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4176 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4177 .port_get_cmode = mv88e6185_port_get_cmode, 4178 .port_setup_message_port = mv88e6xxx_setup_message_port, 4179 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4180 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4181 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4182 .stats_get_strings = mv88e6095_stats_get_strings, 4183 .stats_get_stat = mv88e6095_stats_get_stat, 4184 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4185 .set_egress_port = mv88e6095_g1_set_egress_port, 4186 .watchdog_ops = &mv88e6097_watchdog_ops, 4187 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4188 .pot_clear = mv88e6xxx_g2_pot_clear, 4189 .ppu_enable = mv88e6185_g1_ppu_enable, 4190 .ppu_disable = mv88e6185_g1_ppu_disable, 4191 .reset = mv88e6185_g1_reset, 4192 .rmu_disable = mv88e6085_g1_rmu_disable, 4193 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4194 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4195 .stu_getnext = mv88e6352_g1_stu_getnext, 4196 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4197 .phylink_get_caps = mv88e6185_phylink_get_caps, 4198 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4199 }; 4200 4201 static const struct mv88e6xxx_ops mv88e6095_ops = { 4202 /* MV88E6XXX_FAMILY_6095 */ 4203 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4204 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4205 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4206 .phy_read = mv88e6185_phy_ppu_read, 4207 .phy_write = mv88e6185_phy_ppu_write, 4208 .port_set_link = mv88e6xxx_port_set_link, 4209 .port_sync_link = mv88e6185_port_sync_link, 4210 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4211 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4212 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4213 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4214 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4215 .port_get_cmode = mv88e6185_port_get_cmode, 4216 .port_setup_message_port = mv88e6xxx_setup_message_port, 4217 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4218 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4219 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4220 .stats_get_strings = mv88e6095_stats_get_strings, 4221 .stats_get_stat = mv88e6095_stats_get_stat, 4222 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4223 .ppu_enable = mv88e6185_g1_ppu_enable, 4224 .ppu_disable = mv88e6185_g1_ppu_disable, 4225 .reset = mv88e6185_g1_reset, 4226 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4227 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4228 .phylink_get_caps = mv88e6095_phylink_get_caps, 4229 .pcs_ops = &mv88e6185_pcs_ops, 4230 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4231 }; 4232 4233 static const struct mv88e6xxx_ops mv88e6097_ops = { 4234 /* MV88E6XXX_FAMILY_6097 */ 4235 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4236 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4237 .irl_init_all = mv88e6352_g2_irl_init_all, 4238 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4239 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4240 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4241 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4242 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4243 .port_set_link = mv88e6xxx_port_set_link, 4244 .port_sync_link = mv88e6185_port_sync_link, 4245 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4246 .port_tag_remap = mv88e6095_port_tag_remap, 4247 .port_set_policy = mv88e6352_port_set_policy, 4248 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4249 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4250 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4251 .port_set_ether_type = mv88e6351_port_set_ether_type, 4252 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4253 .port_pause_limit = mv88e6097_port_pause_limit, 4254 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4255 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4256 .port_get_cmode = mv88e6185_port_get_cmode, 4257 .port_setup_message_port = mv88e6xxx_setup_message_port, 4258 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4259 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4260 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4261 .stats_get_strings = mv88e6095_stats_get_strings, 4262 .stats_get_stat = mv88e6095_stats_get_stat, 4263 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4264 .set_egress_port = mv88e6095_g1_set_egress_port, 4265 .watchdog_ops = &mv88e6097_watchdog_ops, 4266 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4267 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4268 .pot_clear = mv88e6xxx_g2_pot_clear, 4269 .reset = mv88e6352_g1_reset, 4270 .rmu_disable = mv88e6085_g1_rmu_disable, 4271 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4272 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4273 .phylink_get_caps = mv88e6095_phylink_get_caps, 4274 .pcs_ops = &mv88e6185_pcs_ops, 4275 .stu_getnext = mv88e6352_g1_stu_getnext, 4276 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4277 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4278 }; 4279 4280 static const struct mv88e6xxx_ops mv88e6123_ops = { 4281 /* MV88E6XXX_FAMILY_6165 */ 4282 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4283 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4284 .irl_init_all = mv88e6352_g2_irl_init_all, 4285 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4286 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4287 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4288 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4289 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4290 .port_set_link = mv88e6xxx_port_set_link, 4291 .port_sync_link = mv88e6xxx_port_sync_link, 4292 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4293 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4294 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4295 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4296 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4297 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4298 .port_get_cmode = mv88e6185_port_get_cmode, 4299 .port_setup_message_port = mv88e6xxx_setup_message_port, 4300 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4301 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4302 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4303 .stats_get_strings = mv88e6095_stats_get_strings, 4304 .stats_get_stat = mv88e6095_stats_get_stat, 4305 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4306 .set_egress_port = mv88e6095_g1_set_egress_port, 4307 .watchdog_ops = &mv88e6097_watchdog_ops, 4308 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4309 .pot_clear = mv88e6xxx_g2_pot_clear, 4310 .reset = mv88e6352_g1_reset, 4311 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4312 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4313 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4314 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4315 .stu_getnext = mv88e6352_g1_stu_getnext, 4316 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4317 .phylink_get_caps = mv88e6185_phylink_get_caps, 4318 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4319 }; 4320 4321 static const struct mv88e6xxx_ops mv88e6131_ops = { 4322 /* MV88E6XXX_FAMILY_6185 */ 4323 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4324 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4325 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4326 .phy_read = mv88e6185_phy_ppu_read, 4327 .phy_write = mv88e6185_phy_ppu_write, 4328 .port_set_link = mv88e6xxx_port_set_link, 4329 .port_sync_link = mv88e6xxx_port_sync_link, 4330 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4331 .port_tag_remap = mv88e6095_port_tag_remap, 4332 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4333 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4334 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4335 .port_set_ether_type = mv88e6351_port_set_ether_type, 4336 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4337 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4338 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4339 .port_pause_limit = mv88e6097_port_pause_limit, 4340 .port_set_pause = mv88e6185_port_set_pause, 4341 .port_get_cmode = mv88e6185_port_get_cmode, 4342 .port_setup_message_port = mv88e6xxx_setup_message_port, 4343 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4344 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4345 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4346 .stats_get_strings = mv88e6095_stats_get_strings, 4347 .stats_get_stat = mv88e6095_stats_get_stat, 4348 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4349 .set_egress_port = mv88e6095_g1_set_egress_port, 4350 .watchdog_ops = &mv88e6097_watchdog_ops, 4351 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4352 .ppu_enable = mv88e6185_g1_ppu_enable, 4353 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4354 .ppu_disable = mv88e6185_g1_ppu_disable, 4355 .reset = mv88e6185_g1_reset, 4356 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4357 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4358 .phylink_get_caps = mv88e6185_phylink_get_caps, 4359 }; 4360 4361 static const struct mv88e6xxx_ops mv88e6141_ops = { 4362 /* MV88E6XXX_FAMILY_6341 */ 4363 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4364 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4365 .irl_init_all = mv88e6352_g2_irl_init_all, 4366 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4367 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4368 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4369 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4370 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4371 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4372 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4373 .port_set_link = mv88e6xxx_port_set_link, 4374 .port_sync_link = mv88e6xxx_port_sync_link, 4375 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4376 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4377 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4378 .port_tag_remap = mv88e6095_port_tag_remap, 4379 .port_set_policy = mv88e6352_port_set_policy, 4380 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4381 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4382 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4383 .port_set_ether_type = mv88e6351_port_set_ether_type, 4384 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4385 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4386 .port_pause_limit = mv88e6097_port_pause_limit, 4387 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4388 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4389 .port_get_cmode = mv88e6352_port_get_cmode, 4390 .port_set_cmode = mv88e6341_port_set_cmode, 4391 .port_setup_message_port = mv88e6xxx_setup_message_port, 4392 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4393 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4394 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4395 .stats_get_strings = mv88e6320_stats_get_strings, 4396 .stats_get_stat = mv88e6390_stats_get_stat, 4397 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4398 .set_egress_port = mv88e6390_g1_set_egress_port, 4399 .watchdog_ops = &mv88e6390_watchdog_ops, 4400 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4401 .pot_clear = mv88e6xxx_g2_pot_clear, 4402 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4403 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4404 .reset = mv88e6352_g1_reset, 4405 .rmu_disable = mv88e6390_g1_rmu_disable, 4406 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4407 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4408 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4409 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4410 .stu_getnext = mv88e6352_g1_stu_getnext, 4411 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4412 .serdes_get_lane = mv88e6341_serdes_get_lane, 4413 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4414 .gpio_ops = &mv88e6352_gpio_ops, 4415 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4416 .serdes_get_strings = mv88e6390_serdes_get_strings, 4417 .serdes_get_stats = mv88e6390_serdes_get_stats, 4418 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4419 .serdes_get_regs = mv88e6390_serdes_get_regs, 4420 .phylink_get_caps = mv88e6341_phylink_get_caps, 4421 .pcs_ops = &mv88e6390_pcs_ops, 4422 }; 4423 4424 static const struct mv88e6xxx_ops mv88e6161_ops = { 4425 /* MV88E6XXX_FAMILY_6165 */ 4426 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4427 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4428 .irl_init_all = mv88e6352_g2_irl_init_all, 4429 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4430 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4431 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4432 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4433 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4434 .port_set_link = mv88e6xxx_port_set_link, 4435 .port_sync_link = mv88e6xxx_port_sync_link, 4436 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4437 .port_tag_remap = mv88e6095_port_tag_remap, 4438 .port_set_policy = mv88e6352_port_set_policy, 4439 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4440 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4441 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4442 .port_set_ether_type = mv88e6351_port_set_ether_type, 4443 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4444 .port_pause_limit = mv88e6097_port_pause_limit, 4445 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4446 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4447 .port_get_cmode = mv88e6185_port_get_cmode, 4448 .port_setup_message_port = mv88e6xxx_setup_message_port, 4449 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4450 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4451 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4452 .stats_get_strings = mv88e6095_stats_get_strings, 4453 .stats_get_stat = mv88e6095_stats_get_stat, 4454 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4455 .set_egress_port = mv88e6095_g1_set_egress_port, 4456 .watchdog_ops = &mv88e6097_watchdog_ops, 4457 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4458 .pot_clear = mv88e6xxx_g2_pot_clear, 4459 .reset = mv88e6352_g1_reset, 4460 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4461 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4462 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4463 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4464 .stu_getnext = mv88e6352_g1_stu_getnext, 4465 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4466 .avb_ops = &mv88e6165_avb_ops, 4467 .ptp_ops = &mv88e6165_ptp_ops, 4468 .phylink_get_caps = mv88e6185_phylink_get_caps, 4469 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4470 }; 4471 4472 static const struct mv88e6xxx_ops mv88e6165_ops = { 4473 /* MV88E6XXX_FAMILY_6165 */ 4474 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4475 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4476 .irl_init_all = mv88e6352_g2_irl_init_all, 4477 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4478 .phy_read = mv88e6165_phy_read, 4479 .phy_write = mv88e6165_phy_write, 4480 .port_set_link = mv88e6xxx_port_set_link, 4481 .port_sync_link = mv88e6xxx_port_sync_link, 4482 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4483 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4484 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4485 .port_get_cmode = mv88e6185_port_get_cmode, 4486 .port_setup_message_port = mv88e6xxx_setup_message_port, 4487 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4488 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4489 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4490 .stats_get_strings = mv88e6095_stats_get_strings, 4491 .stats_get_stat = mv88e6095_stats_get_stat, 4492 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4493 .set_egress_port = mv88e6095_g1_set_egress_port, 4494 .watchdog_ops = &mv88e6097_watchdog_ops, 4495 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4496 .pot_clear = mv88e6xxx_g2_pot_clear, 4497 .reset = mv88e6352_g1_reset, 4498 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4499 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4500 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4501 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4502 .stu_getnext = mv88e6352_g1_stu_getnext, 4503 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4504 .avb_ops = &mv88e6165_avb_ops, 4505 .ptp_ops = &mv88e6165_ptp_ops, 4506 .phylink_get_caps = mv88e6185_phylink_get_caps, 4507 }; 4508 4509 static const struct mv88e6xxx_ops mv88e6171_ops = { 4510 /* MV88E6XXX_FAMILY_6351 */ 4511 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4512 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4513 .irl_init_all = mv88e6352_g2_irl_init_all, 4514 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4515 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4516 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4517 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4518 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4519 .port_set_link = mv88e6xxx_port_set_link, 4520 .port_sync_link = mv88e6xxx_port_sync_link, 4521 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4522 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4523 .port_tag_remap = mv88e6095_port_tag_remap, 4524 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4525 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4526 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4527 .port_set_ether_type = mv88e6351_port_set_ether_type, 4528 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4529 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4530 .port_pause_limit = mv88e6097_port_pause_limit, 4531 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4532 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4533 .port_get_cmode = mv88e6352_port_get_cmode, 4534 .port_setup_message_port = mv88e6xxx_setup_message_port, 4535 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4536 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4537 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4538 .stats_get_strings = mv88e6095_stats_get_strings, 4539 .stats_get_stat = mv88e6095_stats_get_stat, 4540 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4541 .set_egress_port = mv88e6095_g1_set_egress_port, 4542 .watchdog_ops = &mv88e6097_watchdog_ops, 4543 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4544 .pot_clear = mv88e6xxx_g2_pot_clear, 4545 .reset = mv88e6352_g1_reset, 4546 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4547 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4548 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4549 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4550 .stu_getnext = mv88e6352_g1_stu_getnext, 4551 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4552 .phylink_get_caps = mv88e6351_phylink_get_caps, 4553 }; 4554 4555 static const struct mv88e6xxx_ops mv88e6172_ops = { 4556 /* MV88E6XXX_FAMILY_6352 */ 4557 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4558 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4559 .irl_init_all = mv88e6352_g2_irl_init_all, 4560 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4561 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4562 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4563 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4564 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4565 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4566 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4567 .port_set_link = mv88e6xxx_port_set_link, 4568 .port_sync_link = mv88e6xxx_port_sync_link, 4569 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4570 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4571 .port_tag_remap = mv88e6095_port_tag_remap, 4572 .port_set_policy = mv88e6352_port_set_policy, 4573 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4574 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4575 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4576 .port_set_ether_type = mv88e6351_port_set_ether_type, 4577 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4578 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4579 .port_pause_limit = mv88e6097_port_pause_limit, 4580 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4581 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4582 .port_get_cmode = mv88e6352_port_get_cmode, 4583 .port_setup_leds = mv88e6xxx_port_setup_leds, 4584 .port_setup_message_port = mv88e6xxx_setup_message_port, 4585 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4586 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4587 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4588 .stats_get_strings = mv88e6095_stats_get_strings, 4589 .stats_get_stat = mv88e6095_stats_get_stat, 4590 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4591 .set_egress_port = mv88e6095_g1_set_egress_port, 4592 .watchdog_ops = &mv88e6097_watchdog_ops, 4593 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4594 .pot_clear = mv88e6xxx_g2_pot_clear, 4595 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4596 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4597 .reset = mv88e6352_g1_reset, 4598 .rmu_disable = mv88e6352_g1_rmu_disable, 4599 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4600 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4601 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4602 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4603 .stu_getnext = mv88e6352_g1_stu_getnext, 4604 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4605 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4606 .serdes_get_regs = mv88e6352_serdes_get_regs, 4607 .gpio_ops = &mv88e6352_gpio_ops, 4608 .phylink_get_caps = mv88e6352_phylink_get_caps, 4609 .pcs_ops = &mv88e6352_pcs_ops, 4610 }; 4611 4612 static const struct mv88e6xxx_ops mv88e6175_ops = { 4613 /* MV88E6XXX_FAMILY_6351 */ 4614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4615 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4616 .irl_init_all = mv88e6352_g2_irl_init_all, 4617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4618 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4619 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4620 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4621 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4622 .port_set_link = mv88e6xxx_port_set_link, 4623 .port_sync_link = mv88e6xxx_port_sync_link, 4624 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4625 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4626 .port_tag_remap = mv88e6095_port_tag_remap, 4627 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4628 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4629 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4630 .port_set_ether_type = mv88e6351_port_set_ether_type, 4631 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4632 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4633 .port_pause_limit = mv88e6097_port_pause_limit, 4634 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4635 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4636 .port_get_cmode = mv88e6352_port_get_cmode, 4637 .port_setup_message_port = mv88e6xxx_setup_message_port, 4638 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4639 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4640 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4641 .stats_get_strings = mv88e6095_stats_get_strings, 4642 .stats_get_stat = mv88e6095_stats_get_stat, 4643 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4644 .set_egress_port = mv88e6095_g1_set_egress_port, 4645 .watchdog_ops = &mv88e6097_watchdog_ops, 4646 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4647 .pot_clear = mv88e6xxx_g2_pot_clear, 4648 .reset = mv88e6352_g1_reset, 4649 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4650 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4651 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4652 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4653 .stu_getnext = mv88e6352_g1_stu_getnext, 4654 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4655 .phylink_get_caps = mv88e6351_phylink_get_caps, 4656 }; 4657 4658 static const struct mv88e6xxx_ops mv88e6176_ops = { 4659 /* MV88E6XXX_FAMILY_6352 */ 4660 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4661 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4662 .irl_init_all = mv88e6352_g2_irl_init_all, 4663 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4664 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4665 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4666 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4667 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4668 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4669 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4670 .port_set_link = mv88e6xxx_port_set_link, 4671 .port_sync_link = mv88e6xxx_port_sync_link, 4672 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4673 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4674 .port_tag_remap = mv88e6095_port_tag_remap, 4675 .port_set_policy = mv88e6352_port_set_policy, 4676 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4677 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4678 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4679 .port_set_ether_type = mv88e6351_port_set_ether_type, 4680 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4681 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4682 .port_pause_limit = mv88e6097_port_pause_limit, 4683 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4684 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4685 .port_get_cmode = mv88e6352_port_get_cmode, 4686 .port_setup_leds = mv88e6xxx_port_setup_leds, 4687 .port_setup_message_port = mv88e6xxx_setup_message_port, 4688 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4689 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4690 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4691 .stats_get_strings = mv88e6095_stats_get_strings, 4692 .stats_get_stat = mv88e6095_stats_get_stat, 4693 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4694 .set_egress_port = mv88e6095_g1_set_egress_port, 4695 .watchdog_ops = &mv88e6097_watchdog_ops, 4696 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4697 .pot_clear = mv88e6xxx_g2_pot_clear, 4698 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4699 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4700 .reset = mv88e6352_g1_reset, 4701 .rmu_disable = mv88e6352_g1_rmu_disable, 4702 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4703 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4704 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4705 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4706 .stu_getnext = mv88e6352_g1_stu_getnext, 4707 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4708 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4709 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4710 .serdes_get_regs = mv88e6352_serdes_get_regs, 4711 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4712 .gpio_ops = &mv88e6352_gpio_ops, 4713 .phylink_get_caps = mv88e6352_phylink_get_caps, 4714 .pcs_ops = &mv88e6352_pcs_ops, 4715 }; 4716 4717 static const struct mv88e6xxx_ops mv88e6185_ops = { 4718 /* MV88E6XXX_FAMILY_6185 */ 4719 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4720 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4721 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4722 .phy_read = mv88e6185_phy_ppu_read, 4723 .phy_write = mv88e6185_phy_ppu_write, 4724 .port_set_link = mv88e6xxx_port_set_link, 4725 .port_sync_link = mv88e6185_port_sync_link, 4726 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4727 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4728 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4729 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4730 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4731 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4732 .port_set_pause = mv88e6185_port_set_pause, 4733 .port_get_cmode = mv88e6185_port_get_cmode, 4734 .port_setup_message_port = mv88e6xxx_setup_message_port, 4735 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4736 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4737 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4738 .stats_get_strings = mv88e6095_stats_get_strings, 4739 .stats_get_stat = mv88e6095_stats_get_stat, 4740 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4741 .set_egress_port = mv88e6095_g1_set_egress_port, 4742 .watchdog_ops = &mv88e6097_watchdog_ops, 4743 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4744 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4745 .ppu_enable = mv88e6185_g1_ppu_enable, 4746 .ppu_disable = mv88e6185_g1_ppu_disable, 4747 .reset = mv88e6185_g1_reset, 4748 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4749 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4750 .phylink_get_caps = mv88e6185_phylink_get_caps, 4751 .pcs_ops = &mv88e6185_pcs_ops, 4752 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4753 }; 4754 4755 static const struct mv88e6xxx_ops mv88e6190_ops = { 4756 /* MV88E6XXX_FAMILY_6390 */ 4757 .setup_errata = mv88e6390_setup_errata, 4758 .irl_init_all = mv88e6390_g2_irl_init_all, 4759 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4760 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4761 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4762 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4763 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4764 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4765 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4766 .port_set_link = mv88e6xxx_port_set_link, 4767 .port_sync_link = mv88e6xxx_port_sync_link, 4768 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4769 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4770 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4771 .port_tag_remap = mv88e6390_port_tag_remap, 4772 .port_set_policy = mv88e6352_port_set_policy, 4773 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4774 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4775 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4776 .port_set_ether_type = mv88e6351_port_set_ether_type, 4777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4778 .port_pause_limit = mv88e6390_port_pause_limit, 4779 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4780 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4781 .port_get_cmode = mv88e6352_port_get_cmode, 4782 .port_set_cmode = mv88e6390_port_set_cmode, 4783 .port_setup_message_port = mv88e6xxx_setup_message_port, 4784 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4785 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4786 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4787 .stats_get_strings = mv88e6320_stats_get_strings, 4788 .stats_get_stat = mv88e6390_stats_get_stat, 4789 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4790 .set_egress_port = mv88e6390_g1_set_egress_port, 4791 .watchdog_ops = &mv88e6390_watchdog_ops, 4792 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4793 .pot_clear = mv88e6xxx_g2_pot_clear, 4794 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4795 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4796 .reset = mv88e6352_g1_reset, 4797 .rmu_disable = mv88e6390_g1_rmu_disable, 4798 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4799 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4800 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4801 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4802 .stu_getnext = mv88e6390_g1_stu_getnext, 4803 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4804 .serdes_get_lane = mv88e6390_serdes_get_lane, 4805 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4806 .serdes_get_strings = mv88e6390_serdes_get_strings, 4807 .serdes_get_stats = mv88e6390_serdes_get_stats, 4808 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4809 .serdes_get_regs = mv88e6390_serdes_get_regs, 4810 .gpio_ops = &mv88e6352_gpio_ops, 4811 .phylink_get_caps = mv88e6390_phylink_get_caps, 4812 .pcs_ops = &mv88e6390_pcs_ops, 4813 }; 4814 4815 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4816 /* MV88E6XXX_FAMILY_6390 */ 4817 .setup_errata = mv88e6390_setup_errata, 4818 .irl_init_all = mv88e6390_g2_irl_init_all, 4819 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4820 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4821 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4822 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4823 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4824 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4825 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4826 .port_set_link = mv88e6xxx_port_set_link, 4827 .port_sync_link = mv88e6xxx_port_sync_link, 4828 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4829 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4830 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4831 .port_tag_remap = mv88e6390_port_tag_remap, 4832 .port_set_policy = mv88e6352_port_set_policy, 4833 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4834 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4835 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4836 .port_set_ether_type = mv88e6351_port_set_ether_type, 4837 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4838 .port_pause_limit = mv88e6390_port_pause_limit, 4839 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4840 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4841 .port_get_cmode = mv88e6352_port_get_cmode, 4842 .port_set_cmode = mv88e6390x_port_set_cmode, 4843 .port_setup_message_port = mv88e6xxx_setup_message_port, 4844 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4845 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4846 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4847 .stats_get_strings = mv88e6320_stats_get_strings, 4848 .stats_get_stat = mv88e6390_stats_get_stat, 4849 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4850 .set_egress_port = mv88e6390_g1_set_egress_port, 4851 .watchdog_ops = &mv88e6390_watchdog_ops, 4852 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4853 .pot_clear = mv88e6xxx_g2_pot_clear, 4854 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4855 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4856 .reset = mv88e6352_g1_reset, 4857 .rmu_disable = mv88e6390_g1_rmu_disable, 4858 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4859 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4860 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4861 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4862 .stu_getnext = mv88e6390_g1_stu_getnext, 4863 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4864 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4865 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4866 .serdes_get_strings = mv88e6390_serdes_get_strings, 4867 .serdes_get_stats = mv88e6390_serdes_get_stats, 4868 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4869 .serdes_get_regs = mv88e6390_serdes_get_regs, 4870 .gpio_ops = &mv88e6352_gpio_ops, 4871 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4872 .pcs_ops = &mv88e6390_pcs_ops, 4873 }; 4874 4875 static const struct mv88e6xxx_ops mv88e6191_ops = { 4876 /* MV88E6XXX_FAMILY_6390 */ 4877 .setup_errata = mv88e6390_setup_errata, 4878 .irl_init_all = mv88e6390_g2_irl_init_all, 4879 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4880 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4881 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4882 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4883 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4884 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4885 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4886 .port_set_link = mv88e6xxx_port_set_link, 4887 .port_sync_link = mv88e6xxx_port_sync_link, 4888 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4889 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4890 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4891 .port_tag_remap = mv88e6390_port_tag_remap, 4892 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4893 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4894 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4895 .port_set_ether_type = mv88e6351_port_set_ether_type, 4896 .port_pause_limit = mv88e6390_port_pause_limit, 4897 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4898 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4899 .port_get_cmode = mv88e6352_port_get_cmode, 4900 .port_set_cmode = mv88e6390_port_set_cmode, 4901 .port_setup_message_port = mv88e6xxx_setup_message_port, 4902 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4903 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4904 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4905 .stats_get_strings = mv88e6320_stats_get_strings, 4906 .stats_get_stat = mv88e6390_stats_get_stat, 4907 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4908 .set_egress_port = mv88e6390_g1_set_egress_port, 4909 .watchdog_ops = &mv88e6390_watchdog_ops, 4910 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4911 .pot_clear = mv88e6xxx_g2_pot_clear, 4912 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4913 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4914 .reset = mv88e6352_g1_reset, 4915 .rmu_disable = mv88e6390_g1_rmu_disable, 4916 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4917 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4918 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4919 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4920 .stu_getnext = mv88e6390_g1_stu_getnext, 4921 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4922 .serdes_get_lane = mv88e6390_serdes_get_lane, 4923 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4924 .serdes_get_strings = mv88e6390_serdes_get_strings, 4925 .serdes_get_stats = mv88e6390_serdes_get_stats, 4926 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4927 .serdes_get_regs = mv88e6390_serdes_get_regs, 4928 .avb_ops = &mv88e6390_avb_ops, 4929 .ptp_ops = &mv88e6352_ptp_ops, 4930 .phylink_get_caps = mv88e6390_phylink_get_caps, 4931 .pcs_ops = &mv88e6390_pcs_ops, 4932 }; 4933 4934 static const struct mv88e6xxx_ops mv88e6240_ops = { 4935 /* MV88E6XXX_FAMILY_6352 */ 4936 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4937 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4938 .irl_init_all = mv88e6352_g2_irl_init_all, 4939 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4940 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4941 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4942 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4943 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4944 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4945 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4946 .port_set_link = mv88e6xxx_port_set_link, 4947 .port_sync_link = mv88e6xxx_port_sync_link, 4948 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4949 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4950 .port_tag_remap = mv88e6095_port_tag_remap, 4951 .port_set_policy = mv88e6352_port_set_policy, 4952 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4953 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4954 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4955 .port_set_ether_type = mv88e6351_port_set_ether_type, 4956 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4957 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4958 .port_pause_limit = mv88e6097_port_pause_limit, 4959 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4960 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4961 .port_get_cmode = mv88e6352_port_get_cmode, 4962 .port_setup_leds = mv88e6xxx_port_setup_leds, 4963 .port_setup_message_port = mv88e6xxx_setup_message_port, 4964 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4965 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4966 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4967 .stats_get_strings = mv88e6095_stats_get_strings, 4968 .stats_get_stat = mv88e6095_stats_get_stat, 4969 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4970 .set_egress_port = mv88e6095_g1_set_egress_port, 4971 .watchdog_ops = &mv88e6097_watchdog_ops, 4972 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4973 .pot_clear = mv88e6xxx_g2_pot_clear, 4974 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 4975 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 4976 .reset = mv88e6352_g1_reset, 4977 .rmu_disable = mv88e6352_g1_rmu_disable, 4978 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4979 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4980 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4981 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4982 .stu_getnext = mv88e6352_g1_stu_getnext, 4983 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4984 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4985 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4986 .serdes_get_regs = mv88e6352_serdes_get_regs, 4987 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4988 .gpio_ops = &mv88e6352_gpio_ops, 4989 .avb_ops = &mv88e6352_avb_ops, 4990 .ptp_ops = &mv88e6352_ptp_ops, 4991 .phylink_get_caps = mv88e6352_phylink_get_caps, 4992 .pcs_ops = &mv88e6352_pcs_ops, 4993 }; 4994 4995 static const struct mv88e6xxx_ops mv88e6250_ops = { 4996 /* MV88E6XXX_FAMILY_6250 */ 4997 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4998 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4999 .irl_init_all = mv88e6352_g2_irl_init_all, 5000 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5001 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5002 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5003 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5004 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5005 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5006 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5007 .port_set_link = mv88e6xxx_port_set_link, 5008 .port_sync_link = mv88e6xxx_port_sync_link, 5009 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5010 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5011 .port_tag_remap = mv88e6095_port_tag_remap, 5012 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5013 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5014 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5015 .port_set_ether_type = mv88e6351_port_set_ether_type, 5016 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5017 .port_pause_limit = mv88e6097_port_pause_limit, 5018 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5019 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5020 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5021 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5022 .stats_get_strings = mv88e6250_stats_get_strings, 5023 .stats_get_stat = mv88e6250_stats_get_stat, 5024 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5025 .set_egress_port = mv88e6095_g1_set_egress_port, 5026 .watchdog_ops = &mv88e6250_watchdog_ops, 5027 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5028 .pot_clear = mv88e6xxx_g2_pot_clear, 5029 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset, 5030 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done, 5031 .reset = mv88e6250_g1_reset, 5032 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5033 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5034 .avb_ops = &mv88e6352_avb_ops, 5035 .ptp_ops = &mv88e6250_ptp_ops, 5036 .phylink_get_caps = mv88e6250_phylink_get_caps, 5037 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5038 }; 5039 5040 static const struct mv88e6xxx_ops mv88e6290_ops = { 5041 /* MV88E6XXX_FAMILY_6390 */ 5042 .setup_errata = mv88e6390_setup_errata, 5043 .irl_init_all = mv88e6390_g2_irl_init_all, 5044 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5045 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5046 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5047 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5048 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5049 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5050 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5051 .port_set_link = mv88e6xxx_port_set_link, 5052 .port_sync_link = mv88e6xxx_port_sync_link, 5053 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5054 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5055 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5056 .port_tag_remap = mv88e6390_port_tag_remap, 5057 .port_set_policy = mv88e6352_port_set_policy, 5058 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5059 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5060 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5061 .port_set_ether_type = mv88e6351_port_set_ether_type, 5062 .port_pause_limit = mv88e6390_port_pause_limit, 5063 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5064 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5065 .port_get_cmode = mv88e6352_port_get_cmode, 5066 .port_set_cmode = mv88e6390_port_set_cmode, 5067 .port_setup_message_port = mv88e6xxx_setup_message_port, 5068 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5069 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5070 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5071 .stats_get_strings = mv88e6320_stats_get_strings, 5072 .stats_get_stat = mv88e6390_stats_get_stat, 5073 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5074 .set_egress_port = mv88e6390_g1_set_egress_port, 5075 .watchdog_ops = &mv88e6390_watchdog_ops, 5076 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5077 .pot_clear = mv88e6xxx_g2_pot_clear, 5078 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5079 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5080 .reset = mv88e6352_g1_reset, 5081 .rmu_disable = mv88e6390_g1_rmu_disable, 5082 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5083 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5084 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5085 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5086 .stu_getnext = mv88e6390_g1_stu_getnext, 5087 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5088 .serdes_get_lane = mv88e6390_serdes_get_lane, 5089 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5090 .serdes_get_strings = mv88e6390_serdes_get_strings, 5091 .serdes_get_stats = mv88e6390_serdes_get_stats, 5092 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5093 .serdes_get_regs = mv88e6390_serdes_get_regs, 5094 .gpio_ops = &mv88e6352_gpio_ops, 5095 .avb_ops = &mv88e6390_avb_ops, 5096 .ptp_ops = &mv88e6390_ptp_ops, 5097 .phylink_get_caps = mv88e6390_phylink_get_caps, 5098 .pcs_ops = &mv88e6390_pcs_ops, 5099 }; 5100 5101 static const struct mv88e6xxx_ops mv88e6320_ops = { 5102 /* MV88E6XXX_FAMILY_6320 */ 5103 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5104 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5105 .irl_init_all = mv88e6352_g2_irl_init_all, 5106 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5107 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5108 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5109 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5110 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5111 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5112 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5113 .port_set_link = mv88e6xxx_port_set_link, 5114 .port_sync_link = mv88e6xxx_port_sync_link, 5115 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5116 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5117 .port_tag_remap = mv88e6095_port_tag_remap, 5118 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5119 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5120 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5121 .port_set_ether_type = mv88e6351_port_set_ether_type, 5122 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5123 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5124 .port_pause_limit = mv88e6097_port_pause_limit, 5125 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5126 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5127 .port_get_cmode = mv88e6352_port_get_cmode, 5128 .port_setup_message_port = mv88e6xxx_setup_message_port, 5129 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5130 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5131 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5132 .stats_get_strings = mv88e6320_stats_get_strings, 5133 .stats_get_stat = mv88e6320_stats_get_stat, 5134 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5135 .set_egress_port = mv88e6095_g1_set_egress_port, 5136 .watchdog_ops = &mv88e6390_watchdog_ops, 5137 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5138 .pot_clear = mv88e6xxx_g2_pot_clear, 5139 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5140 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5141 .reset = mv88e6352_g1_reset, 5142 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5143 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5144 .gpio_ops = &mv88e6352_gpio_ops, 5145 .avb_ops = &mv88e6352_avb_ops, 5146 .ptp_ops = &mv88e6352_ptp_ops, 5147 .phylink_get_caps = mv88e632x_phylink_get_caps, 5148 }; 5149 5150 static const struct mv88e6xxx_ops mv88e6321_ops = { 5151 /* MV88E6XXX_FAMILY_6320 */ 5152 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5153 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5154 .irl_init_all = mv88e6352_g2_irl_init_all, 5155 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5156 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5157 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5158 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5159 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5160 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5161 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5162 .port_set_link = mv88e6xxx_port_set_link, 5163 .port_sync_link = mv88e6xxx_port_sync_link, 5164 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5165 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5166 .port_tag_remap = mv88e6095_port_tag_remap, 5167 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5168 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5169 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5170 .port_set_ether_type = mv88e6351_port_set_ether_type, 5171 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5172 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5173 .port_pause_limit = mv88e6097_port_pause_limit, 5174 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5175 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5176 .port_get_cmode = mv88e6352_port_get_cmode, 5177 .port_setup_message_port = mv88e6xxx_setup_message_port, 5178 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5179 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5180 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5181 .stats_get_strings = mv88e6320_stats_get_strings, 5182 .stats_get_stat = mv88e6320_stats_get_stat, 5183 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5184 .set_egress_port = mv88e6095_g1_set_egress_port, 5185 .watchdog_ops = &mv88e6390_watchdog_ops, 5186 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5187 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5188 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5189 .reset = mv88e6352_g1_reset, 5190 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5191 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5192 .gpio_ops = &mv88e6352_gpio_ops, 5193 .avb_ops = &mv88e6352_avb_ops, 5194 .ptp_ops = &mv88e6352_ptp_ops, 5195 .phylink_get_caps = mv88e632x_phylink_get_caps, 5196 }; 5197 5198 static const struct mv88e6xxx_ops mv88e6341_ops = { 5199 /* MV88E6XXX_FAMILY_6341 */ 5200 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5201 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5202 .irl_init_all = mv88e6352_g2_irl_init_all, 5203 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5204 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5205 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5206 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5207 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5208 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5209 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5210 .port_set_link = mv88e6xxx_port_set_link, 5211 .port_sync_link = mv88e6xxx_port_sync_link, 5212 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5213 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5214 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5215 .port_tag_remap = mv88e6095_port_tag_remap, 5216 .port_set_policy = mv88e6352_port_set_policy, 5217 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5218 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5219 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5220 .port_set_ether_type = mv88e6351_port_set_ether_type, 5221 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5222 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5223 .port_pause_limit = mv88e6097_port_pause_limit, 5224 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5225 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5226 .port_get_cmode = mv88e6352_port_get_cmode, 5227 .port_set_cmode = mv88e6341_port_set_cmode, 5228 .port_setup_message_port = mv88e6xxx_setup_message_port, 5229 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5230 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5231 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5232 .stats_get_strings = mv88e6320_stats_get_strings, 5233 .stats_get_stat = mv88e6390_stats_get_stat, 5234 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5235 .set_egress_port = mv88e6390_g1_set_egress_port, 5236 .watchdog_ops = &mv88e6390_watchdog_ops, 5237 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5238 .pot_clear = mv88e6xxx_g2_pot_clear, 5239 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5240 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5241 .reset = mv88e6352_g1_reset, 5242 .rmu_disable = mv88e6390_g1_rmu_disable, 5243 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5244 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5245 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5246 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5247 .stu_getnext = mv88e6352_g1_stu_getnext, 5248 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5249 .serdes_get_lane = mv88e6341_serdes_get_lane, 5250 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5251 .gpio_ops = &mv88e6352_gpio_ops, 5252 .avb_ops = &mv88e6390_avb_ops, 5253 .ptp_ops = &mv88e6352_ptp_ops, 5254 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5255 .serdes_get_strings = mv88e6390_serdes_get_strings, 5256 .serdes_get_stats = mv88e6390_serdes_get_stats, 5257 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5258 .serdes_get_regs = mv88e6390_serdes_get_regs, 5259 .phylink_get_caps = mv88e6341_phylink_get_caps, 5260 .pcs_ops = &mv88e6390_pcs_ops, 5261 }; 5262 5263 static const struct mv88e6xxx_ops mv88e6350_ops = { 5264 /* MV88E6XXX_FAMILY_6351 */ 5265 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5266 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5267 .irl_init_all = mv88e6352_g2_irl_init_all, 5268 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5269 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5270 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5271 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5272 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5273 .port_set_link = mv88e6xxx_port_set_link, 5274 .port_sync_link = mv88e6xxx_port_sync_link, 5275 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5276 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5277 .port_tag_remap = mv88e6095_port_tag_remap, 5278 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5279 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5280 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5281 .port_set_ether_type = mv88e6351_port_set_ether_type, 5282 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5283 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5284 .port_pause_limit = mv88e6097_port_pause_limit, 5285 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5286 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5287 .port_get_cmode = mv88e6352_port_get_cmode, 5288 .port_setup_message_port = mv88e6xxx_setup_message_port, 5289 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5290 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5291 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5292 .stats_get_strings = mv88e6095_stats_get_strings, 5293 .stats_get_stat = mv88e6095_stats_get_stat, 5294 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5295 .set_egress_port = mv88e6095_g1_set_egress_port, 5296 .watchdog_ops = &mv88e6097_watchdog_ops, 5297 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5298 .pot_clear = mv88e6xxx_g2_pot_clear, 5299 .reset = mv88e6352_g1_reset, 5300 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5301 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5302 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5303 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5304 .stu_getnext = mv88e6352_g1_stu_getnext, 5305 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5306 .phylink_get_caps = mv88e6351_phylink_get_caps, 5307 }; 5308 5309 static const struct mv88e6xxx_ops mv88e6351_ops = { 5310 /* MV88E6XXX_FAMILY_6351 */ 5311 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5312 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5313 .irl_init_all = mv88e6352_g2_irl_init_all, 5314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5315 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5316 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5317 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5318 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5319 .port_set_link = mv88e6xxx_port_set_link, 5320 .port_sync_link = mv88e6xxx_port_sync_link, 5321 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5322 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5323 .port_tag_remap = mv88e6095_port_tag_remap, 5324 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5325 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5326 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5327 .port_set_ether_type = mv88e6351_port_set_ether_type, 5328 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5329 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5330 .port_pause_limit = mv88e6097_port_pause_limit, 5331 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5332 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5333 .port_get_cmode = mv88e6352_port_get_cmode, 5334 .port_setup_message_port = mv88e6xxx_setup_message_port, 5335 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5336 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5337 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5338 .stats_get_strings = mv88e6095_stats_get_strings, 5339 .stats_get_stat = mv88e6095_stats_get_stat, 5340 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5341 .set_egress_port = mv88e6095_g1_set_egress_port, 5342 .watchdog_ops = &mv88e6097_watchdog_ops, 5343 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5344 .pot_clear = mv88e6xxx_g2_pot_clear, 5345 .reset = mv88e6352_g1_reset, 5346 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5347 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5348 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5349 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5350 .stu_getnext = mv88e6352_g1_stu_getnext, 5351 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5352 .avb_ops = &mv88e6352_avb_ops, 5353 .ptp_ops = &mv88e6352_ptp_ops, 5354 .phylink_get_caps = mv88e6351_phylink_get_caps, 5355 }; 5356 5357 static const struct mv88e6xxx_ops mv88e6352_ops = { 5358 /* MV88E6XXX_FAMILY_6352 */ 5359 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5360 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5361 .irl_init_all = mv88e6352_g2_irl_init_all, 5362 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5363 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5364 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5365 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5366 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5367 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5368 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5369 .port_set_link = mv88e6xxx_port_set_link, 5370 .port_sync_link = mv88e6xxx_port_sync_link, 5371 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5372 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5373 .port_tag_remap = mv88e6095_port_tag_remap, 5374 .port_set_policy = mv88e6352_port_set_policy, 5375 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5376 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5377 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5378 .port_set_ether_type = mv88e6351_port_set_ether_type, 5379 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5380 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5381 .port_pause_limit = mv88e6097_port_pause_limit, 5382 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5383 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5384 .port_get_cmode = mv88e6352_port_get_cmode, 5385 .port_setup_leds = mv88e6xxx_port_setup_leds, 5386 .port_setup_message_port = mv88e6xxx_setup_message_port, 5387 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5388 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5389 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5390 .stats_get_strings = mv88e6095_stats_get_strings, 5391 .stats_get_stat = mv88e6095_stats_get_stat, 5392 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5393 .set_egress_port = mv88e6095_g1_set_egress_port, 5394 .watchdog_ops = &mv88e6097_watchdog_ops, 5395 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5396 .pot_clear = mv88e6xxx_g2_pot_clear, 5397 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5398 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5399 .reset = mv88e6352_g1_reset, 5400 .rmu_disable = mv88e6352_g1_rmu_disable, 5401 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5402 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5403 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5404 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5405 .stu_getnext = mv88e6352_g1_stu_getnext, 5406 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5407 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5408 .gpio_ops = &mv88e6352_gpio_ops, 5409 .avb_ops = &mv88e6352_avb_ops, 5410 .ptp_ops = &mv88e6352_ptp_ops, 5411 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5412 .serdes_get_strings = mv88e6352_serdes_get_strings, 5413 .serdes_get_stats = mv88e6352_serdes_get_stats, 5414 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5415 .serdes_get_regs = mv88e6352_serdes_get_regs, 5416 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5417 .phylink_get_caps = mv88e6352_phylink_get_caps, 5418 .pcs_ops = &mv88e6352_pcs_ops, 5419 }; 5420 5421 static const struct mv88e6xxx_ops mv88e6390_ops = { 5422 /* MV88E6XXX_FAMILY_6390 */ 5423 .setup_errata = mv88e6390_setup_errata, 5424 .irl_init_all = mv88e6390_g2_irl_init_all, 5425 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5426 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5427 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5428 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5429 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5430 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5431 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5432 .port_set_link = mv88e6xxx_port_set_link, 5433 .port_sync_link = mv88e6xxx_port_sync_link, 5434 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5435 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5436 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5437 .port_tag_remap = mv88e6390_port_tag_remap, 5438 .port_set_policy = mv88e6352_port_set_policy, 5439 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5440 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5441 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5442 .port_set_ether_type = mv88e6351_port_set_ether_type, 5443 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5444 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5445 .port_pause_limit = mv88e6390_port_pause_limit, 5446 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5447 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5448 .port_get_cmode = mv88e6352_port_get_cmode, 5449 .port_set_cmode = mv88e6390_port_set_cmode, 5450 .port_setup_message_port = mv88e6xxx_setup_message_port, 5451 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5452 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5453 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5454 .stats_get_strings = mv88e6320_stats_get_strings, 5455 .stats_get_stat = mv88e6390_stats_get_stat, 5456 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5457 .set_egress_port = mv88e6390_g1_set_egress_port, 5458 .watchdog_ops = &mv88e6390_watchdog_ops, 5459 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5460 .pot_clear = mv88e6xxx_g2_pot_clear, 5461 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5462 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5463 .reset = mv88e6352_g1_reset, 5464 .rmu_disable = mv88e6390_g1_rmu_disable, 5465 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5466 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5467 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5468 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5469 .stu_getnext = mv88e6390_g1_stu_getnext, 5470 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5471 .serdes_get_lane = mv88e6390_serdes_get_lane, 5472 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5473 .gpio_ops = &mv88e6352_gpio_ops, 5474 .avb_ops = &mv88e6390_avb_ops, 5475 .ptp_ops = &mv88e6390_ptp_ops, 5476 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5477 .serdes_get_strings = mv88e6390_serdes_get_strings, 5478 .serdes_get_stats = mv88e6390_serdes_get_stats, 5479 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5480 .serdes_get_regs = mv88e6390_serdes_get_regs, 5481 .phylink_get_caps = mv88e6390_phylink_get_caps, 5482 .pcs_ops = &mv88e6390_pcs_ops, 5483 }; 5484 5485 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5486 /* MV88E6XXX_FAMILY_6390 */ 5487 .setup_errata = mv88e6390_setup_errata, 5488 .irl_init_all = mv88e6390_g2_irl_init_all, 5489 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5490 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5491 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5492 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5493 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5494 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5495 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5496 .port_set_link = mv88e6xxx_port_set_link, 5497 .port_sync_link = mv88e6xxx_port_sync_link, 5498 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5499 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5500 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5501 .port_tag_remap = mv88e6390_port_tag_remap, 5502 .port_set_policy = mv88e6352_port_set_policy, 5503 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5504 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5505 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5506 .port_set_ether_type = mv88e6351_port_set_ether_type, 5507 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5508 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5509 .port_pause_limit = mv88e6390_port_pause_limit, 5510 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5511 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5512 .port_get_cmode = mv88e6352_port_get_cmode, 5513 .port_set_cmode = mv88e6390x_port_set_cmode, 5514 .port_setup_message_port = mv88e6xxx_setup_message_port, 5515 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5516 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5517 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5518 .stats_get_strings = mv88e6320_stats_get_strings, 5519 .stats_get_stat = mv88e6390_stats_get_stat, 5520 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5521 .set_egress_port = mv88e6390_g1_set_egress_port, 5522 .watchdog_ops = &mv88e6390_watchdog_ops, 5523 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5524 .pot_clear = mv88e6xxx_g2_pot_clear, 5525 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5526 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5527 .reset = mv88e6352_g1_reset, 5528 .rmu_disable = mv88e6390_g1_rmu_disable, 5529 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5530 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5531 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5532 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5533 .stu_getnext = mv88e6390_g1_stu_getnext, 5534 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5535 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5536 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5537 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5538 .serdes_get_strings = mv88e6390_serdes_get_strings, 5539 .serdes_get_stats = mv88e6390_serdes_get_stats, 5540 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5541 .serdes_get_regs = mv88e6390_serdes_get_regs, 5542 .gpio_ops = &mv88e6352_gpio_ops, 5543 .avb_ops = &mv88e6390_avb_ops, 5544 .ptp_ops = &mv88e6390_ptp_ops, 5545 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5546 .pcs_ops = &mv88e6390_pcs_ops, 5547 }; 5548 5549 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5550 /* MV88E6XXX_FAMILY_6393 */ 5551 .irl_init_all = mv88e6390_g2_irl_init_all, 5552 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5553 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5554 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5555 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5556 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5557 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5558 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5559 .port_set_link = mv88e6xxx_port_set_link, 5560 .port_sync_link = mv88e6xxx_port_sync_link, 5561 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5562 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5563 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5564 .port_tag_remap = mv88e6390_port_tag_remap, 5565 .port_set_policy = mv88e6393x_port_set_policy, 5566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5567 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5568 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5569 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5570 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5571 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5572 .port_pause_limit = mv88e6390_port_pause_limit, 5573 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5574 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5575 .port_get_cmode = mv88e6352_port_get_cmode, 5576 .port_set_cmode = mv88e6393x_port_set_cmode, 5577 .port_setup_message_port = mv88e6xxx_setup_message_port, 5578 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5579 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5581 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5582 .stats_get_strings = mv88e6320_stats_get_strings, 5583 .stats_get_stat = mv88e6390_stats_get_stat, 5584 /* .set_cpu_port is missing because this family does not support a global 5585 * CPU port, only per port CPU port which is set via 5586 * .port_set_upstream_port method. 5587 */ 5588 .set_egress_port = mv88e6393x_set_egress_port, 5589 .watchdog_ops = &mv88e6393x_watchdog_ops, 5590 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5591 .pot_clear = mv88e6xxx_g2_pot_clear, 5592 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait, 5593 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait, 5594 .reset = mv88e6352_g1_reset, 5595 .rmu_disable = mv88e6390_g1_rmu_disable, 5596 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5597 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5598 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5599 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5600 .stu_getnext = mv88e6390_g1_stu_getnext, 5601 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5602 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5603 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5604 /* TODO: serdes stats */ 5605 .gpio_ops = &mv88e6352_gpio_ops, 5606 .avb_ops = &mv88e6390_avb_ops, 5607 .ptp_ops = &mv88e6352_ptp_ops, 5608 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5609 .pcs_ops = &mv88e6393x_pcs_ops, 5610 }; 5611 5612 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5613 [MV88E6020] = { 5614 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5615 .family = MV88E6XXX_FAMILY_6250, 5616 .name = "Marvell 88E6020", 5617 .num_databases = 64, 5618 /* Ports 2-4 are not routed to pins 5619 * => usable ports 0, 1, 5, 6 5620 */ 5621 .num_ports = 7, 5622 .num_internal_phys = 2, 5623 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5624 .max_vid = 4095, 5625 .port_base_addr = 0x8, 5626 .phy_base_addr = 0x0, 5627 .global1_addr = 0xf, 5628 .global2_addr = 0x7, 5629 .age_time_coeff = 15000, 5630 .g1_irqs = 9, 5631 .g2_irqs = 5, 5632 .stats_type = STATS_TYPE_BANK0, 5633 .atu_move_port_mask = 0xf, 5634 .dual_chip = true, 5635 .ops = &mv88e6250_ops, 5636 }, 5637 5638 [MV88E6071] = { 5639 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5640 .family = MV88E6XXX_FAMILY_6250, 5641 .name = "Marvell 88E6071", 5642 .num_databases = 64, 5643 .num_ports = 7, 5644 .num_internal_phys = 5, 5645 .max_vid = 4095, 5646 .port_base_addr = 0x08, 5647 .phy_base_addr = 0x00, 5648 .global1_addr = 0x0f, 5649 .global2_addr = 0x07, 5650 .age_time_coeff = 15000, 5651 .g1_irqs = 9, 5652 .g2_irqs = 5, 5653 .stats_type = STATS_TYPE_BANK0, 5654 .atu_move_port_mask = 0xf, 5655 .dual_chip = true, 5656 .ops = &mv88e6250_ops, 5657 }, 5658 5659 [MV88E6085] = { 5660 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5661 .family = MV88E6XXX_FAMILY_6097, 5662 .name = "Marvell 88E6085", 5663 .num_databases = 4096, 5664 .num_macs = 8192, 5665 .num_ports = 10, 5666 .num_internal_phys = 5, 5667 .max_vid = 4095, 5668 .max_sid = 63, 5669 .port_base_addr = 0x10, 5670 .phy_base_addr = 0x0, 5671 .global1_addr = 0x1b, 5672 .global2_addr = 0x1c, 5673 .age_time_coeff = 15000, 5674 .g1_irqs = 8, 5675 .g2_irqs = 10, 5676 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5677 .atu_move_port_mask = 0xf, 5678 .pvt = true, 5679 .multi_chip = true, 5680 .ops = &mv88e6085_ops, 5681 }, 5682 5683 [MV88E6095] = { 5684 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5685 .family = MV88E6XXX_FAMILY_6095, 5686 .name = "Marvell 88E6095/88E6095F", 5687 .num_databases = 256, 5688 .num_macs = 8192, 5689 .num_ports = 11, 5690 .num_internal_phys = 0, 5691 .max_vid = 4095, 5692 .port_base_addr = 0x10, 5693 .phy_base_addr = 0x0, 5694 .global1_addr = 0x1b, 5695 .global2_addr = 0x1c, 5696 .age_time_coeff = 15000, 5697 .g1_irqs = 8, 5698 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5699 .atu_move_port_mask = 0xf, 5700 .multi_chip = true, 5701 .ops = &mv88e6095_ops, 5702 }, 5703 5704 [MV88E6097] = { 5705 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5706 .family = MV88E6XXX_FAMILY_6097, 5707 .name = "Marvell 88E6097/88E6097F", 5708 .num_databases = 4096, 5709 .num_macs = 8192, 5710 .num_ports = 11, 5711 .num_internal_phys = 8, 5712 .max_vid = 4095, 5713 .max_sid = 63, 5714 .port_base_addr = 0x10, 5715 .phy_base_addr = 0x0, 5716 .global1_addr = 0x1b, 5717 .global2_addr = 0x1c, 5718 .age_time_coeff = 15000, 5719 .g1_irqs = 8, 5720 .g2_irqs = 10, 5721 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5722 .atu_move_port_mask = 0xf, 5723 .pvt = true, 5724 .multi_chip = true, 5725 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5726 .ops = &mv88e6097_ops, 5727 }, 5728 5729 [MV88E6123] = { 5730 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5731 .family = MV88E6XXX_FAMILY_6165, 5732 .name = "Marvell 88E6123", 5733 .num_databases = 4096, 5734 .num_macs = 1024, 5735 .num_ports = 3, 5736 .num_internal_phys = 5, 5737 .max_vid = 4095, 5738 .max_sid = 63, 5739 .port_base_addr = 0x10, 5740 .phy_base_addr = 0x0, 5741 .global1_addr = 0x1b, 5742 .global2_addr = 0x1c, 5743 .age_time_coeff = 15000, 5744 .g1_irqs = 9, 5745 .g2_irqs = 10, 5746 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5747 .atu_move_port_mask = 0xf, 5748 .pvt = true, 5749 .multi_chip = true, 5750 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5751 .ops = &mv88e6123_ops, 5752 }, 5753 5754 [MV88E6131] = { 5755 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5756 .family = MV88E6XXX_FAMILY_6185, 5757 .name = "Marvell 88E6131", 5758 .num_databases = 256, 5759 .num_macs = 8192, 5760 .num_ports = 8, 5761 .num_internal_phys = 0, 5762 .max_vid = 4095, 5763 .port_base_addr = 0x10, 5764 .phy_base_addr = 0x0, 5765 .global1_addr = 0x1b, 5766 .global2_addr = 0x1c, 5767 .age_time_coeff = 15000, 5768 .g1_irqs = 9, 5769 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5770 .atu_move_port_mask = 0xf, 5771 .multi_chip = true, 5772 .ops = &mv88e6131_ops, 5773 }, 5774 5775 [MV88E6141] = { 5776 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5777 .family = MV88E6XXX_FAMILY_6341, 5778 .name = "Marvell 88E6141", 5779 .num_databases = 256, 5780 .num_macs = 2048, 5781 .num_ports = 6, 5782 .num_internal_phys = 5, 5783 .num_gpio = 11, 5784 .max_vid = 4095, 5785 .max_sid = 63, 5786 .port_base_addr = 0x10, 5787 .phy_base_addr = 0x10, 5788 .global1_addr = 0x1b, 5789 .global2_addr = 0x1c, 5790 .age_time_coeff = 3750, 5791 .atu_move_port_mask = 0x1f, 5792 .g1_irqs = 9, 5793 .g2_irqs = 10, 5794 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5795 .pvt = true, 5796 .multi_chip = true, 5797 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5798 .ops = &mv88e6141_ops, 5799 }, 5800 5801 [MV88E6161] = { 5802 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5803 .family = MV88E6XXX_FAMILY_6165, 5804 .name = "Marvell 88E6161", 5805 .num_databases = 4096, 5806 .num_macs = 1024, 5807 .num_ports = 6, 5808 .num_internal_phys = 5, 5809 .max_vid = 4095, 5810 .max_sid = 63, 5811 .port_base_addr = 0x10, 5812 .phy_base_addr = 0x0, 5813 .global1_addr = 0x1b, 5814 .global2_addr = 0x1c, 5815 .age_time_coeff = 15000, 5816 .g1_irqs = 9, 5817 .g2_irqs = 10, 5818 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5819 .atu_move_port_mask = 0xf, 5820 .pvt = true, 5821 .multi_chip = true, 5822 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5823 .ptp_support = true, 5824 .ops = &mv88e6161_ops, 5825 }, 5826 5827 [MV88E6165] = { 5828 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5829 .family = MV88E6XXX_FAMILY_6165, 5830 .name = "Marvell 88E6165", 5831 .num_databases = 4096, 5832 .num_macs = 8192, 5833 .num_ports = 6, 5834 .num_internal_phys = 0, 5835 .max_vid = 4095, 5836 .max_sid = 63, 5837 .port_base_addr = 0x10, 5838 .phy_base_addr = 0x0, 5839 .global1_addr = 0x1b, 5840 .global2_addr = 0x1c, 5841 .age_time_coeff = 15000, 5842 .g1_irqs = 9, 5843 .g2_irqs = 10, 5844 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5845 .atu_move_port_mask = 0xf, 5846 .pvt = true, 5847 .multi_chip = true, 5848 .ptp_support = true, 5849 .ops = &mv88e6165_ops, 5850 }, 5851 5852 [MV88E6171] = { 5853 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5854 .family = MV88E6XXX_FAMILY_6351, 5855 .name = "Marvell 88E6171", 5856 .num_databases = 4096, 5857 .num_macs = 8192, 5858 .num_ports = 7, 5859 .num_internal_phys = 5, 5860 .max_vid = 4095, 5861 .max_sid = 63, 5862 .port_base_addr = 0x10, 5863 .phy_base_addr = 0x0, 5864 .global1_addr = 0x1b, 5865 .global2_addr = 0x1c, 5866 .age_time_coeff = 15000, 5867 .g1_irqs = 9, 5868 .g2_irqs = 10, 5869 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5870 .atu_move_port_mask = 0xf, 5871 .pvt = true, 5872 .multi_chip = true, 5873 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5874 .ops = &mv88e6171_ops, 5875 }, 5876 5877 [MV88E6172] = { 5878 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5879 .family = MV88E6XXX_FAMILY_6352, 5880 .name = "Marvell 88E6172", 5881 .num_databases = 4096, 5882 .num_macs = 8192, 5883 .num_ports = 7, 5884 .num_internal_phys = 5, 5885 .num_gpio = 15, 5886 .max_vid = 4095, 5887 .max_sid = 63, 5888 .port_base_addr = 0x10, 5889 .phy_base_addr = 0x0, 5890 .global1_addr = 0x1b, 5891 .global2_addr = 0x1c, 5892 .age_time_coeff = 15000, 5893 .g1_irqs = 9, 5894 .g2_irqs = 10, 5895 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5896 .atu_move_port_mask = 0xf, 5897 .pvt = true, 5898 .multi_chip = true, 5899 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5900 .ops = &mv88e6172_ops, 5901 }, 5902 5903 [MV88E6175] = { 5904 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5905 .family = MV88E6XXX_FAMILY_6351, 5906 .name = "Marvell 88E6175", 5907 .num_databases = 4096, 5908 .num_macs = 8192, 5909 .num_ports = 7, 5910 .num_internal_phys = 5, 5911 .max_vid = 4095, 5912 .max_sid = 63, 5913 .port_base_addr = 0x10, 5914 .phy_base_addr = 0x0, 5915 .global1_addr = 0x1b, 5916 .global2_addr = 0x1c, 5917 .age_time_coeff = 15000, 5918 .g1_irqs = 9, 5919 .g2_irqs = 10, 5920 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5921 .atu_move_port_mask = 0xf, 5922 .pvt = true, 5923 .multi_chip = true, 5924 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5925 .ops = &mv88e6175_ops, 5926 }, 5927 5928 [MV88E6176] = { 5929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5930 .family = MV88E6XXX_FAMILY_6352, 5931 .name = "Marvell 88E6176", 5932 .num_databases = 4096, 5933 .num_macs = 8192, 5934 .num_ports = 7, 5935 .num_internal_phys = 5, 5936 .num_gpio = 15, 5937 .max_vid = 4095, 5938 .max_sid = 63, 5939 .port_base_addr = 0x10, 5940 .phy_base_addr = 0x0, 5941 .global1_addr = 0x1b, 5942 .global2_addr = 0x1c, 5943 .age_time_coeff = 15000, 5944 .g1_irqs = 9, 5945 .g2_irqs = 10, 5946 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5947 .atu_move_port_mask = 0xf, 5948 .pvt = true, 5949 .multi_chip = true, 5950 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5951 .ops = &mv88e6176_ops, 5952 }, 5953 5954 [MV88E6185] = { 5955 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5956 .family = MV88E6XXX_FAMILY_6185, 5957 .name = "Marvell 88E6185", 5958 .num_databases = 256, 5959 .num_macs = 8192, 5960 .num_ports = 10, 5961 .num_internal_phys = 0, 5962 .max_vid = 4095, 5963 .port_base_addr = 0x10, 5964 .phy_base_addr = 0x0, 5965 .global1_addr = 0x1b, 5966 .global2_addr = 0x1c, 5967 .age_time_coeff = 15000, 5968 .g1_irqs = 8, 5969 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 5970 .atu_move_port_mask = 0xf, 5971 .multi_chip = true, 5972 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5973 .ops = &mv88e6185_ops, 5974 }, 5975 5976 [MV88E6190] = { 5977 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5978 .family = MV88E6XXX_FAMILY_6390, 5979 .name = "Marvell 88E6190", 5980 .num_databases = 4096, 5981 .num_macs = 16384, 5982 .num_ports = 11, /* 10 + Z80 */ 5983 .num_internal_phys = 9, 5984 .num_gpio = 16, 5985 .max_vid = 8191, 5986 .max_sid = 63, 5987 .port_base_addr = 0x0, 5988 .phy_base_addr = 0x0, 5989 .global1_addr = 0x1b, 5990 .global2_addr = 0x1c, 5991 .age_time_coeff = 3750, 5992 .g1_irqs = 9, 5993 .g2_irqs = 14, 5994 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 5995 .pvt = true, 5996 .multi_chip = true, 5997 .atu_move_port_mask = 0x1f, 5998 .ops = &mv88e6190_ops, 5999 }, 6000 6001 [MV88E6190X] = { 6002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6003 .family = MV88E6XXX_FAMILY_6390, 6004 .name = "Marvell 88E6190X", 6005 .num_databases = 4096, 6006 .num_macs = 16384, 6007 .num_ports = 11, /* 10 + Z80 */ 6008 .num_internal_phys = 9, 6009 .num_gpio = 16, 6010 .max_vid = 8191, 6011 .max_sid = 63, 6012 .port_base_addr = 0x0, 6013 .phy_base_addr = 0x0, 6014 .global1_addr = 0x1b, 6015 .global2_addr = 0x1c, 6016 .age_time_coeff = 3750, 6017 .g1_irqs = 9, 6018 .g2_irqs = 14, 6019 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6020 .atu_move_port_mask = 0x1f, 6021 .pvt = true, 6022 .multi_chip = true, 6023 .ops = &mv88e6190x_ops, 6024 }, 6025 6026 [MV88E6191] = { 6027 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6028 .family = MV88E6XXX_FAMILY_6390, 6029 .name = "Marvell 88E6191", 6030 .num_databases = 4096, 6031 .num_macs = 16384, 6032 .num_ports = 11, /* 10 + Z80 */ 6033 .num_internal_phys = 9, 6034 .max_vid = 8191, 6035 .max_sid = 63, 6036 .port_base_addr = 0x0, 6037 .phy_base_addr = 0x0, 6038 .global1_addr = 0x1b, 6039 .global2_addr = 0x1c, 6040 .age_time_coeff = 3750, 6041 .g1_irqs = 9, 6042 .g2_irqs = 14, 6043 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6044 .atu_move_port_mask = 0x1f, 6045 .pvt = true, 6046 .multi_chip = true, 6047 .ptp_support = true, 6048 .ops = &mv88e6191_ops, 6049 }, 6050 6051 [MV88E6191X] = { 6052 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6053 .family = MV88E6XXX_FAMILY_6393, 6054 .name = "Marvell 88E6191X", 6055 .num_databases = 4096, 6056 .num_ports = 11, /* 10 + Z80 */ 6057 .num_internal_phys = 8, 6058 .internal_phys_offset = 1, 6059 .max_vid = 8191, 6060 .max_sid = 63, 6061 .port_base_addr = 0x0, 6062 .phy_base_addr = 0x0, 6063 .global1_addr = 0x1b, 6064 .global2_addr = 0x1c, 6065 .age_time_coeff = 3750, 6066 .g1_irqs = 10, 6067 .g2_irqs = 14, 6068 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6069 .atu_move_port_mask = 0x1f, 6070 .pvt = true, 6071 .multi_chip = true, 6072 .ptp_support = true, 6073 .ops = &mv88e6393x_ops, 6074 }, 6075 6076 [MV88E6193X] = { 6077 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6078 .family = MV88E6XXX_FAMILY_6393, 6079 .name = "Marvell 88E6193X", 6080 .num_databases = 4096, 6081 .num_ports = 11, /* 10 + Z80 */ 6082 .num_internal_phys = 8, 6083 .internal_phys_offset = 1, 6084 .max_vid = 8191, 6085 .max_sid = 63, 6086 .port_base_addr = 0x0, 6087 .phy_base_addr = 0x0, 6088 .global1_addr = 0x1b, 6089 .global2_addr = 0x1c, 6090 .age_time_coeff = 3750, 6091 .g1_irqs = 10, 6092 .g2_irqs = 14, 6093 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6094 .atu_move_port_mask = 0x1f, 6095 .pvt = true, 6096 .multi_chip = true, 6097 .ptp_support = true, 6098 .ops = &mv88e6393x_ops, 6099 }, 6100 6101 [MV88E6220] = { 6102 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6103 .family = MV88E6XXX_FAMILY_6250, 6104 .name = "Marvell 88E6220", 6105 .num_databases = 64, 6106 6107 /* Ports 2-4 are not routed to pins 6108 * => usable ports 0, 1, 5, 6 6109 */ 6110 .num_ports = 7, 6111 .num_internal_phys = 2, 6112 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6113 .max_vid = 4095, 6114 .port_base_addr = 0x08, 6115 .phy_base_addr = 0x00, 6116 .global1_addr = 0x0f, 6117 .global2_addr = 0x07, 6118 .age_time_coeff = 15000, 6119 .g1_irqs = 9, 6120 .g2_irqs = 10, 6121 .stats_type = STATS_TYPE_BANK0, 6122 .atu_move_port_mask = 0xf, 6123 .dual_chip = true, 6124 .ptp_support = true, 6125 .ops = &mv88e6250_ops, 6126 }, 6127 6128 [MV88E6240] = { 6129 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6130 .family = MV88E6XXX_FAMILY_6352, 6131 .name = "Marvell 88E6240", 6132 .num_databases = 4096, 6133 .num_macs = 8192, 6134 .num_ports = 7, 6135 .num_internal_phys = 5, 6136 .num_gpio = 15, 6137 .max_vid = 4095, 6138 .max_sid = 63, 6139 .port_base_addr = 0x10, 6140 .phy_base_addr = 0x0, 6141 .global1_addr = 0x1b, 6142 .global2_addr = 0x1c, 6143 .age_time_coeff = 15000, 6144 .g1_irqs = 9, 6145 .g2_irqs = 10, 6146 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6147 .atu_move_port_mask = 0xf, 6148 .pvt = true, 6149 .multi_chip = true, 6150 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6151 .ptp_support = true, 6152 .ops = &mv88e6240_ops, 6153 }, 6154 6155 [MV88E6250] = { 6156 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6157 .family = MV88E6XXX_FAMILY_6250, 6158 .name = "Marvell 88E6250", 6159 .num_databases = 64, 6160 .num_ports = 7, 6161 .num_internal_phys = 5, 6162 .max_vid = 4095, 6163 .port_base_addr = 0x08, 6164 .phy_base_addr = 0x00, 6165 .global1_addr = 0x0f, 6166 .global2_addr = 0x07, 6167 .age_time_coeff = 15000, 6168 .g1_irqs = 9, 6169 .g2_irqs = 10, 6170 .stats_type = STATS_TYPE_BANK0, 6171 .atu_move_port_mask = 0xf, 6172 .dual_chip = true, 6173 .ptp_support = true, 6174 .ops = &mv88e6250_ops, 6175 }, 6176 6177 [MV88E6290] = { 6178 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6179 .family = MV88E6XXX_FAMILY_6390, 6180 .name = "Marvell 88E6290", 6181 .num_databases = 4096, 6182 .num_ports = 11, /* 10 + Z80 */ 6183 .num_internal_phys = 9, 6184 .num_gpio = 16, 6185 .max_vid = 8191, 6186 .max_sid = 63, 6187 .port_base_addr = 0x0, 6188 .phy_base_addr = 0x0, 6189 .global1_addr = 0x1b, 6190 .global2_addr = 0x1c, 6191 .age_time_coeff = 3750, 6192 .g1_irqs = 9, 6193 .g2_irqs = 14, 6194 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6195 .atu_move_port_mask = 0x1f, 6196 .pvt = true, 6197 .multi_chip = true, 6198 .ptp_support = true, 6199 .ops = &mv88e6290_ops, 6200 }, 6201 6202 [MV88E6320] = { 6203 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6204 .family = MV88E6XXX_FAMILY_6320, 6205 .name = "Marvell 88E6320", 6206 .num_databases = 4096, 6207 .num_macs = 8192, 6208 .num_ports = 7, 6209 .num_internal_phys = 5, 6210 .num_gpio = 15, 6211 .max_vid = 4095, 6212 .port_base_addr = 0x10, 6213 .phy_base_addr = 0x0, 6214 .global1_addr = 0x1b, 6215 .global2_addr = 0x1c, 6216 .age_time_coeff = 15000, 6217 .g1_irqs = 8, 6218 .g2_irqs = 10, 6219 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6220 .atu_move_port_mask = 0xf, 6221 .pvt = true, 6222 .multi_chip = true, 6223 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6224 .ptp_support = true, 6225 .ops = &mv88e6320_ops, 6226 }, 6227 6228 [MV88E6321] = { 6229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6230 .family = MV88E6XXX_FAMILY_6320, 6231 .name = "Marvell 88E6321", 6232 .num_databases = 4096, 6233 .num_macs = 8192, 6234 .num_ports = 7, 6235 .num_internal_phys = 5, 6236 .num_gpio = 15, 6237 .max_vid = 4095, 6238 .port_base_addr = 0x10, 6239 .phy_base_addr = 0x0, 6240 .global1_addr = 0x1b, 6241 .global2_addr = 0x1c, 6242 .age_time_coeff = 15000, 6243 .g1_irqs = 8, 6244 .g2_irqs = 10, 6245 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6246 .atu_move_port_mask = 0xf, 6247 .multi_chip = true, 6248 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6249 .ptp_support = true, 6250 .ops = &mv88e6321_ops, 6251 }, 6252 6253 [MV88E6341] = { 6254 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6255 .family = MV88E6XXX_FAMILY_6341, 6256 .name = "Marvell 88E6341", 6257 .num_databases = 256, 6258 .num_macs = 2048, 6259 .num_internal_phys = 5, 6260 .num_ports = 6, 6261 .num_gpio = 11, 6262 .max_vid = 4095, 6263 .max_sid = 63, 6264 .port_base_addr = 0x10, 6265 .phy_base_addr = 0x10, 6266 .global1_addr = 0x1b, 6267 .global2_addr = 0x1c, 6268 .age_time_coeff = 3750, 6269 .atu_move_port_mask = 0x1f, 6270 .g1_irqs = 9, 6271 .g2_irqs = 10, 6272 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6273 .pvt = true, 6274 .multi_chip = true, 6275 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6276 .ptp_support = true, 6277 .ops = &mv88e6341_ops, 6278 }, 6279 6280 [MV88E6350] = { 6281 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6282 .family = MV88E6XXX_FAMILY_6351, 6283 .name = "Marvell 88E6350", 6284 .num_databases = 4096, 6285 .num_macs = 8192, 6286 .num_ports = 7, 6287 .num_internal_phys = 5, 6288 .max_vid = 4095, 6289 .max_sid = 63, 6290 .port_base_addr = 0x10, 6291 .phy_base_addr = 0x0, 6292 .global1_addr = 0x1b, 6293 .global2_addr = 0x1c, 6294 .age_time_coeff = 15000, 6295 .g1_irqs = 9, 6296 .g2_irqs = 10, 6297 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6298 .atu_move_port_mask = 0xf, 6299 .pvt = true, 6300 .multi_chip = true, 6301 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6302 .ops = &mv88e6350_ops, 6303 }, 6304 6305 [MV88E6351] = { 6306 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6307 .family = MV88E6XXX_FAMILY_6351, 6308 .name = "Marvell 88E6351", 6309 .num_databases = 4096, 6310 .num_macs = 8192, 6311 .num_ports = 7, 6312 .num_internal_phys = 5, 6313 .max_vid = 4095, 6314 .max_sid = 63, 6315 .port_base_addr = 0x10, 6316 .phy_base_addr = 0x0, 6317 .global1_addr = 0x1b, 6318 .global2_addr = 0x1c, 6319 .age_time_coeff = 15000, 6320 .g1_irqs = 9, 6321 .g2_irqs = 10, 6322 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6323 .atu_move_port_mask = 0xf, 6324 .pvt = true, 6325 .multi_chip = true, 6326 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6327 .ops = &mv88e6351_ops, 6328 }, 6329 6330 [MV88E6352] = { 6331 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6332 .family = MV88E6XXX_FAMILY_6352, 6333 .name = "Marvell 88E6352", 6334 .num_databases = 4096, 6335 .num_macs = 8192, 6336 .num_ports = 7, 6337 .num_internal_phys = 5, 6338 .num_gpio = 15, 6339 .max_vid = 4095, 6340 .max_sid = 63, 6341 .port_base_addr = 0x10, 6342 .phy_base_addr = 0x0, 6343 .global1_addr = 0x1b, 6344 .global2_addr = 0x1c, 6345 .age_time_coeff = 15000, 6346 .g1_irqs = 9, 6347 .g2_irqs = 10, 6348 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_PORT, 6349 .atu_move_port_mask = 0xf, 6350 .pvt = true, 6351 .multi_chip = true, 6352 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6353 .ptp_support = true, 6354 .ops = &mv88e6352_ops, 6355 }, 6356 [MV88E6361] = { 6357 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6358 .family = MV88E6XXX_FAMILY_6393, 6359 .name = "Marvell 88E6361", 6360 .num_databases = 4096, 6361 .num_macs = 16384, 6362 .num_ports = 11, 6363 /* Ports 1, 2 and 8 are not routed */ 6364 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6365 .num_internal_phys = 5, 6366 .internal_phys_offset = 3, 6367 .max_vid = 8191, 6368 .max_sid = 63, 6369 .port_base_addr = 0x0, 6370 .phy_base_addr = 0x0, 6371 .global1_addr = 0x1b, 6372 .global2_addr = 0x1c, 6373 .age_time_coeff = 3750, 6374 .g1_irqs = 10, 6375 .g2_irqs = 14, 6376 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6377 .atu_move_port_mask = 0x1f, 6378 .pvt = true, 6379 .multi_chip = true, 6380 .ptp_support = true, 6381 .ops = &mv88e6393x_ops, 6382 }, 6383 [MV88E6390] = { 6384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6385 .family = MV88E6XXX_FAMILY_6390, 6386 .name = "Marvell 88E6390", 6387 .num_databases = 4096, 6388 .num_macs = 16384, 6389 .num_ports = 11, /* 10 + Z80 */ 6390 .num_internal_phys = 9, 6391 .num_gpio = 16, 6392 .max_vid = 8191, 6393 .max_sid = 63, 6394 .port_base_addr = 0x0, 6395 .phy_base_addr = 0x0, 6396 .global1_addr = 0x1b, 6397 .global2_addr = 0x1c, 6398 .age_time_coeff = 3750, 6399 .g1_irqs = 9, 6400 .g2_irqs = 14, 6401 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6402 .atu_move_port_mask = 0x1f, 6403 .pvt = true, 6404 .multi_chip = true, 6405 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6406 .ptp_support = true, 6407 .ops = &mv88e6390_ops, 6408 }, 6409 [MV88E6390X] = { 6410 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6411 .family = MV88E6XXX_FAMILY_6390, 6412 .name = "Marvell 88E6390X", 6413 .num_databases = 4096, 6414 .num_macs = 16384, 6415 .num_ports = 11, /* 10 + Z80 */ 6416 .num_internal_phys = 9, 6417 .num_gpio = 16, 6418 .max_vid = 8191, 6419 .max_sid = 63, 6420 .port_base_addr = 0x0, 6421 .phy_base_addr = 0x0, 6422 .global1_addr = 0x1b, 6423 .global2_addr = 0x1c, 6424 .age_time_coeff = 3750, 6425 .g1_irqs = 9, 6426 .g2_irqs = 14, 6427 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6428 .atu_move_port_mask = 0x1f, 6429 .pvt = true, 6430 .multi_chip = true, 6431 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6432 .ptp_support = true, 6433 .ops = &mv88e6390x_ops, 6434 }, 6435 6436 [MV88E6393X] = { 6437 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6438 .family = MV88E6XXX_FAMILY_6393, 6439 .name = "Marvell 88E6393X", 6440 .num_databases = 4096, 6441 .num_ports = 11, /* 10 + Z80 */ 6442 .num_internal_phys = 8, 6443 .internal_phys_offset = 1, 6444 .max_vid = 8191, 6445 .max_sid = 63, 6446 .port_base_addr = 0x0, 6447 .phy_base_addr = 0x0, 6448 .global1_addr = 0x1b, 6449 .global2_addr = 0x1c, 6450 .age_time_coeff = 3750, 6451 .g1_irqs = 10, 6452 .g2_irqs = 14, 6453 .stats_type = STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 6454 .atu_move_port_mask = 0x1f, 6455 .pvt = true, 6456 .multi_chip = true, 6457 .ptp_support = true, 6458 .ops = &mv88e6393x_ops, 6459 }, 6460 }; 6461 6462 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6463 { 6464 int i; 6465 6466 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6467 if (mv88e6xxx_table[i].prod_num == prod_num) 6468 return &mv88e6xxx_table[i]; 6469 6470 return NULL; 6471 } 6472 6473 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6474 { 6475 const struct mv88e6xxx_info *info; 6476 unsigned int prod_num, rev; 6477 u16 id; 6478 int err; 6479 6480 mv88e6xxx_reg_lock(chip); 6481 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6482 mv88e6xxx_reg_unlock(chip); 6483 if (err) 6484 return err; 6485 6486 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6487 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6488 6489 info = mv88e6xxx_lookup_info(prod_num); 6490 if (!info) 6491 return -ENODEV; 6492 6493 /* Update the compatible info with the probed one */ 6494 chip->info = info; 6495 6496 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6497 chip->info->prod_num, chip->info->name, rev); 6498 6499 return 0; 6500 } 6501 6502 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6503 struct mdio_device *mdiodev) 6504 { 6505 int err; 6506 6507 /* dual_chip takes precedence over single/multi-chip modes */ 6508 if (chip->info->dual_chip) 6509 return -EINVAL; 6510 6511 /* If the mdio addr is 16 indicating the first port address of a switch 6512 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6513 * configured in single chip addressing mode. Setup the smi access as 6514 * single chip addressing mode and attempt to detect the model of the 6515 * switch, if this fails the device is not configured in single chip 6516 * addressing mode. 6517 */ 6518 if (mdiodev->addr != 16) 6519 return -EINVAL; 6520 6521 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6522 if (err) 6523 return err; 6524 6525 return mv88e6xxx_detect(chip); 6526 } 6527 6528 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6529 { 6530 struct mv88e6xxx_chip *chip; 6531 6532 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6533 if (!chip) 6534 return NULL; 6535 6536 chip->dev = dev; 6537 6538 mutex_init(&chip->reg_lock); 6539 INIT_LIST_HEAD(&chip->mdios); 6540 idr_init(&chip->policies); 6541 INIT_LIST_HEAD(&chip->msts); 6542 6543 return chip; 6544 } 6545 6546 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6547 int port, 6548 enum dsa_tag_protocol m) 6549 { 6550 struct mv88e6xxx_chip *chip = ds->priv; 6551 6552 return chip->tag_protocol; 6553 } 6554 6555 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6556 enum dsa_tag_protocol proto) 6557 { 6558 struct mv88e6xxx_chip *chip = ds->priv; 6559 enum dsa_tag_protocol old_protocol; 6560 struct dsa_port *cpu_dp; 6561 int err; 6562 6563 switch (proto) { 6564 case DSA_TAG_PROTO_EDSA: 6565 switch (chip->info->edsa_support) { 6566 case MV88E6XXX_EDSA_UNSUPPORTED: 6567 return -EPROTONOSUPPORT; 6568 case MV88E6XXX_EDSA_UNDOCUMENTED: 6569 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6570 fallthrough; 6571 case MV88E6XXX_EDSA_SUPPORTED: 6572 break; 6573 } 6574 break; 6575 case DSA_TAG_PROTO_DSA: 6576 break; 6577 default: 6578 return -EPROTONOSUPPORT; 6579 } 6580 6581 old_protocol = chip->tag_protocol; 6582 chip->tag_protocol = proto; 6583 6584 mv88e6xxx_reg_lock(chip); 6585 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6586 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6587 if (err) { 6588 mv88e6xxx_reg_unlock(chip); 6589 goto unwind; 6590 } 6591 } 6592 mv88e6xxx_reg_unlock(chip); 6593 6594 return 0; 6595 6596 unwind: 6597 chip->tag_protocol = old_protocol; 6598 6599 mv88e6xxx_reg_lock(chip); 6600 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6601 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6602 mv88e6xxx_reg_unlock(chip); 6603 6604 return err; 6605 } 6606 6607 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6608 const struct switchdev_obj_port_mdb *mdb, 6609 struct dsa_db db) 6610 { 6611 struct mv88e6xxx_chip *chip = ds->priv; 6612 int err; 6613 6614 mv88e6xxx_reg_lock(chip); 6615 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6616 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6617 mv88e6xxx_reg_unlock(chip); 6618 6619 return err; 6620 } 6621 6622 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6623 const struct switchdev_obj_port_mdb *mdb, 6624 struct dsa_db db) 6625 { 6626 struct mv88e6xxx_chip *chip = ds->priv; 6627 int err; 6628 6629 mv88e6xxx_reg_lock(chip); 6630 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6631 mv88e6xxx_reg_unlock(chip); 6632 6633 return err; 6634 } 6635 6636 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6637 struct dsa_mall_mirror_tc_entry *mirror, 6638 bool ingress, 6639 struct netlink_ext_ack *extack) 6640 { 6641 enum mv88e6xxx_egress_direction direction = ingress ? 6642 MV88E6XXX_EGRESS_DIR_INGRESS : 6643 MV88E6XXX_EGRESS_DIR_EGRESS; 6644 struct mv88e6xxx_chip *chip = ds->priv; 6645 bool other_mirrors = false; 6646 int i; 6647 int err; 6648 6649 mutex_lock(&chip->reg_lock); 6650 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6651 mirror->to_local_port) { 6652 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6653 other_mirrors |= ingress ? 6654 chip->ports[i].mirror_ingress : 6655 chip->ports[i].mirror_egress; 6656 6657 /* Can't change egress port when other mirror is active */ 6658 if (other_mirrors) { 6659 err = -EBUSY; 6660 goto out; 6661 } 6662 6663 err = mv88e6xxx_set_egress_port(chip, direction, 6664 mirror->to_local_port); 6665 if (err) 6666 goto out; 6667 } 6668 6669 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6670 out: 6671 mutex_unlock(&chip->reg_lock); 6672 6673 return err; 6674 } 6675 6676 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6677 struct dsa_mall_mirror_tc_entry *mirror) 6678 { 6679 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6680 MV88E6XXX_EGRESS_DIR_INGRESS : 6681 MV88E6XXX_EGRESS_DIR_EGRESS; 6682 struct mv88e6xxx_chip *chip = ds->priv; 6683 bool other_mirrors = false; 6684 int i; 6685 6686 mutex_lock(&chip->reg_lock); 6687 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6688 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6689 6690 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6691 other_mirrors |= mirror->ingress ? 6692 chip->ports[i].mirror_ingress : 6693 chip->ports[i].mirror_egress; 6694 6695 /* Reset egress port when no other mirror is active */ 6696 if (!other_mirrors) { 6697 if (mv88e6xxx_set_egress_port(chip, direction, 6698 dsa_upstream_port(ds, port))) 6699 dev_err(ds->dev, "failed to set egress port\n"); 6700 } 6701 6702 mutex_unlock(&chip->reg_lock); 6703 } 6704 6705 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6706 struct switchdev_brport_flags flags, 6707 struct netlink_ext_ack *extack) 6708 { 6709 struct mv88e6xxx_chip *chip = ds->priv; 6710 const struct mv88e6xxx_ops *ops; 6711 6712 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6713 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6714 return -EINVAL; 6715 6716 ops = chip->info->ops; 6717 6718 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6719 return -EINVAL; 6720 6721 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6722 return -EINVAL; 6723 6724 return 0; 6725 } 6726 6727 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6728 struct switchdev_brport_flags flags, 6729 struct netlink_ext_ack *extack) 6730 { 6731 struct mv88e6xxx_chip *chip = ds->priv; 6732 int err = 0; 6733 6734 mv88e6xxx_reg_lock(chip); 6735 6736 if (flags.mask & BR_LEARNING) { 6737 bool learning = !!(flags.val & BR_LEARNING); 6738 u16 pav = learning ? (1 << port) : 0; 6739 6740 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6741 if (err) 6742 goto out; 6743 } 6744 6745 if (flags.mask & BR_FLOOD) { 6746 bool unicast = !!(flags.val & BR_FLOOD); 6747 6748 err = chip->info->ops->port_set_ucast_flood(chip, port, 6749 unicast); 6750 if (err) 6751 goto out; 6752 } 6753 6754 if (flags.mask & BR_MCAST_FLOOD) { 6755 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6756 6757 err = chip->info->ops->port_set_mcast_flood(chip, port, 6758 multicast); 6759 if (err) 6760 goto out; 6761 } 6762 6763 if (flags.mask & BR_BCAST_FLOOD) { 6764 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6765 6766 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6767 if (err) 6768 goto out; 6769 } 6770 6771 if (flags.mask & BR_PORT_MAB) { 6772 bool mab = !!(flags.val & BR_PORT_MAB); 6773 6774 mv88e6xxx_port_set_mab(chip, port, mab); 6775 } 6776 6777 if (flags.mask & BR_PORT_LOCKED) { 6778 bool locked = !!(flags.val & BR_PORT_LOCKED); 6779 6780 err = mv88e6xxx_port_set_lock(chip, port, locked); 6781 if (err) 6782 goto out; 6783 } 6784 out: 6785 mv88e6xxx_reg_unlock(chip); 6786 6787 return err; 6788 } 6789 6790 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6791 struct dsa_lag lag, 6792 struct netdev_lag_upper_info *info, 6793 struct netlink_ext_ack *extack) 6794 { 6795 struct mv88e6xxx_chip *chip = ds->priv; 6796 struct dsa_port *dp; 6797 int members = 0; 6798 6799 if (!mv88e6xxx_has_lag(chip)) { 6800 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6801 return false; 6802 } 6803 6804 if (!lag.id) 6805 return false; 6806 6807 dsa_lag_foreach_port(dp, ds->dst, &lag) 6808 /* Includes the port joining the LAG */ 6809 members++; 6810 6811 if (members > 8) { 6812 NL_SET_ERR_MSG_MOD(extack, 6813 "Cannot offload more than 8 LAG ports"); 6814 return false; 6815 } 6816 6817 /* We could potentially relax this to include active 6818 * backup in the future. 6819 */ 6820 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6821 NL_SET_ERR_MSG_MOD(extack, 6822 "Can only offload LAG using hash TX type"); 6823 return false; 6824 } 6825 6826 /* Ideally we would also validate that the hash type matches 6827 * the hardware. Alas, this is always set to unknown on team 6828 * interfaces. 6829 */ 6830 return true; 6831 } 6832 6833 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6834 { 6835 struct mv88e6xxx_chip *chip = ds->priv; 6836 struct dsa_port *dp; 6837 u16 map = 0; 6838 int id; 6839 6840 /* DSA LAG IDs are one-based, hardware is zero-based */ 6841 id = lag.id - 1; 6842 6843 /* Build the map of all ports to distribute flows destined for 6844 * this LAG. This can be either a local user port, or a DSA 6845 * port if the LAG port is on a remote chip. 6846 */ 6847 dsa_lag_foreach_port(dp, ds->dst, &lag) 6848 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6849 6850 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6851 } 6852 6853 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6854 /* Row number corresponds to the number of active members in a 6855 * LAG. Each column states which of the eight hash buckets are 6856 * mapped to the column:th port in the LAG. 6857 * 6858 * Example: In a LAG with three active ports, the second port 6859 * ([2][1]) would be selected for traffic mapped to buckets 6860 * 3,4,5 (0x38). 6861 */ 6862 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6863 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6864 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6865 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6866 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6867 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6868 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6869 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6870 }; 6871 6872 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6873 int num_tx, int nth) 6874 { 6875 u8 active = 0; 6876 int i; 6877 6878 num_tx = num_tx <= 8 ? num_tx : 8; 6879 if (nth < num_tx) 6880 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6881 6882 for (i = 0; i < 8; i++) { 6883 if (BIT(i) & active) 6884 mask[i] |= BIT(port); 6885 } 6886 } 6887 6888 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6889 { 6890 struct mv88e6xxx_chip *chip = ds->priv; 6891 unsigned int id, num_tx; 6892 struct dsa_port *dp; 6893 struct dsa_lag *lag; 6894 int i, err, nth; 6895 u16 mask[8]; 6896 u16 ivec; 6897 6898 /* Assume no port is a member of any LAG. */ 6899 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6900 6901 /* Disable all masks for ports that _are_ members of a LAG. */ 6902 dsa_switch_for_each_port(dp, ds) { 6903 if (!dp->lag) 6904 continue; 6905 6906 ivec &= ~BIT(dp->index); 6907 } 6908 6909 for (i = 0; i < 8; i++) 6910 mask[i] = ivec; 6911 6912 /* Enable the correct subset of masks for all LAG ports that 6913 * are in the Tx set. 6914 */ 6915 dsa_lags_foreach_id(id, ds->dst) { 6916 lag = dsa_lag_by_id(ds->dst, id); 6917 if (!lag) 6918 continue; 6919 6920 num_tx = 0; 6921 dsa_lag_foreach_port(dp, ds->dst, lag) { 6922 if (dp->lag_tx_enabled) 6923 num_tx++; 6924 } 6925 6926 if (!num_tx) 6927 continue; 6928 6929 nth = 0; 6930 dsa_lag_foreach_port(dp, ds->dst, lag) { 6931 if (!dp->lag_tx_enabled) 6932 continue; 6933 6934 if (dp->ds == ds) 6935 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6936 num_tx, nth); 6937 6938 nth++; 6939 } 6940 } 6941 6942 for (i = 0; i < 8; i++) { 6943 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6944 if (err) 6945 return err; 6946 } 6947 6948 return 0; 6949 } 6950 6951 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6952 struct dsa_lag lag) 6953 { 6954 int err; 6955 6956 err = mv88e6xxx_lag_sync_masks(ds); 6957 6958 if (!err) 6959 err = mv88e6xxx_lag_sync_map(ds, lag); 6960 6961 return err; 6962 } 6963 6964 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6965 { 6966 struct mv88e6xxx_chip *chip = ds->priv; 6967 int err; 6968 6969 mv88e6xxx_reg_lock(chip); 6970 err = mv88e6xxx_lag_sync_masks(ds); 6971 mv88e6xxx_reg_unlock(chip); 6972 return err; 6973 } 6974 6975 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6976 struct dsa_lag lag, 6977 struct netdev_lag_upper_info *info, 6978 struct netlink_ext_ack *extack) 6979 { 6980 struct mv88e6xxx_chip *chip = ds->priv; 6981 int err, id; 6982 6983 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6984 return -EOPNOTSUPP; 6985 6986 /* DSA LAG IDs are one-based */ 6987 id = lag.id - 1; 6988 6989 mv88e6xxx_reg_lock(chip); 6990 6991 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6992 if (err) 6993 goto err_unlock; 6994 6995 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6996 if (err) 6997 goto err_clear_trunk; 6998 6999 mv88e6xxx_reg_unlock(chip); 7000 return 0; 7001 7002 err_clear_trunk: 7003 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7004 err_unlock: 7005 mv88e6xxx_reg_unlock(chip); 7006 return err; 7007 } 7008 7009 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7010 struct dsa_lag lag) 7011 { 7012 struct mv88e6xxx_chip *chip = ds->priv; 7013 int err_sync, err_trunk; 7014 7015 mv88e6xxx_reg_lock(chip); 7016 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7017 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7018 mv88e6xxx_reg_unlock(chip); 7019 return err_sync ? : err_trunk; 7020 } 7021 7022 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7023 int port) 7024 { 7025 struct mv88e6xxx_chip *chip = ds->priv; 7026 int err; 7027 7028 mv88e6xxx_reg_lock(chip); 7029 err = mv88e6xxx_lag_sync_masks(ds); 7030 mv88e6xxx_reg_unlock(chip); 7031 return err; 7032 } 7033 7034 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7035 int port, struct dsa_lag lag, 7036 struct netdev_lag_upper_info *info, 7037 struct netlink_ext_ack *extack) 7038 { 7039 struct mv88e6xxx_chip *chip = ds->priv; 7040 int err; 7041 7042 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7043 return -EOPNOTSUPP; 7044 7045 mv88e6xxx_reg_lock(chip); 7046 7047 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7048 if (err) 7049 goto unlock; 7050 7051 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7052 7053 unlock: 7054 mv88e6xxx_reg_unlock(chip); 7055 return err; 7056 } 7057 7058 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7059 int port, struct dsa_lag lag) 7060 { 7061 struct mv88e6xxx_chip *chip = ds->priv; 7062 int err_sync, err_pvt; 7063 7064 mv88e6xxx_reg_lock(chip); 7065 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7066 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7067 mv88e6xxx_reg_unlock(chip); 7068 return err_sync ? : err_pvt; 7069 } 7070 7071 static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = { 7072 .mac_select_pcs = mv88e6xxx_mac_select_pcs, 7073 .mac_prepare = mv88e6xxx_mac_prepare, 7074 .mac_config = mv88e6xxx_mac_config, 7075 .mac_finish = mv88e6xxx_mac_finish, 7076 .mac_link_down = mv88e6xxx_mac_link_down, 7077 .mac_link_up = mv88e6xxx_mac_link_up, 7078 }; 7079 7080 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7081 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7082 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7083 .setup = mv88e6xxx_setup, 7084 .teardown = mv88e6xxx_teardown, 7085 .port_setup = mv88e6xxx_port_setup, 7086 .port_teardown = mv88e6xxx_port_teardown, 7087 .phylink_get_caps = mv88e6xxx_get_caps, 7088 .get_strings = mv88e6xxx_get_strings, 7089 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7090 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, 7091 .get_rmon_stats = mv88e6xxx_get_rmon_stats, 7092 .get_sset_count = mv88e6xxx_get_sset_count, 7093 .port_max_mtu = mv88e6xxx_get_max_mtu, 7094 .port_change_mtu = mv88e6xxx_change_mtu, 7095 .support_eee = dsa_supports_eee, 7096 .set_mac_eee = mv88e6xxx_set_mac_eee, 7097 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7098 .get_eeprom = mv88e6xxx_get_eeprom, 7099 .set_eeprom = mv88e6xxx_set_eeprom, 7100 .get_regs_len = mv88e6xxx_get_regs_len, 7101 .get_regs = mv88e6xxx_get_regs, 7102 .get_rxnfc = mv88e6xxx_get_rxnfc, 7103 .set_rxnfc = mv88e6xxx_set_rxnfc, 7104 .set_ageing_time = mv88e6xxx_set_ageing_time, 7105 .port_bridge_join = mv88e6xxx_port_bridge_join, 7106 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7107 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7108 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7109 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7110 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7111 .port_fast_age = mv88e6xxx_port_fast_age, 7112 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7113 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7114 .port_vlan_add = mv88e6xxx_port_vlan_add, 7115 .port_vlan_del = mv88e6xxx_port_vlan_del, 7116 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7117 .port_fdb_add = mv88e6xxx_port_fdb_add, 7118 .port_fdb_del = mv88e6xxx_port_fdb_del, 7119 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7120 .port_mdb_add = mv88e6xxx_port_mdb_add, 7121 .port_mdb_del = mv88e6xxx_port_mdb_del, 7122 .port_mirror_add = mv88e6xxx_port_mirror_add, 7123 .port_mirror_del = mv88e6xxx_port_mirror_del, 7124 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7125 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7126 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7127 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7128 .port_txtstamp = mv88e6xxx_port_txtstamp, 7129 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7130 .get_ts_info = mv88e6xxx_get_ts_info, 7131 .devlink_param_get = mv88e6xxx_devlink_param_get, 7132 .devlink_param_set = mv88e6xxx_devlink_param_set, 7133 .devlink_info_get = mv88e6xxx_devlink_info_get, 7134 .port_lag_change = mv88e6xxx_port_lag_change, 7135 .port_lag_join = mv88e6xxx_port_lag_join, 7136 .port_lag_leave = mv88e6xxx_port_lag_leave, 7137 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7138 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7139 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7140 }; 7141 7142 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7143 { 7144 struct device *dev = chip->dev; 7145 struct dsa_switch *ds; 7146 7147 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7148 if (!ds) 7149 return -ENOMEM; 7150 7151 ds->dev = dev; 7152 ds->num_ports = mv88e6xxx_num_ports(chip); 7153 ds->priv = chip; 7154 ds->dev = dev; 7155 ds->ops = &mv88e6xxx_switch_ops; 7156 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops; 7157 ds->ageing_time_min = chip->info->age_time_coeff; 7158 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7159 7160 /* Some chips support up to 32, but that requires enabling the 7161 * 5-bit port mode, which we do not support. 640k^W16 ought to 7162 * be enough for anyone. 7163 */ 7164 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7165 7166 dev_set_drvdata(dev, ds); 7167 7168 return dsa_register_switch(ds); 7169 } 7170 7171 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7172 { 7173 dsa_unregister_switch(chip->ds); 7174 } 7175 7176 static const void *pdata_device_get_match_data(struct device *dev) 7177 { 7178 const struct of_device_id *matches = dev->driver->of_match_table; 7179 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7180 7181 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7182 matches++) { 7183 if (!strcmp(pdata->compatible, matches->compatible)) 7184 return matches->data; 7185 } 7186 return NULL; 7187 } 7188 7189 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7190 * would be lost after a power cycle so prevent it to be suspended. 7191 */ 7192 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7193 { 7194 return -EOPNOTSUPP; 7195 } 7196 7197 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7198 { 7199 return 0; 7200 } 7201 7202 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7203 7204 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7205 { 7206 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7207 const struct mv88e6xxx_info *compat_info = NULL; 7208 struct device *dev = &mdiodev->dev; 7209 struct device_node *np = dev->of_node; 7210 struct mv88e6xxx_chip *chip; 7211 int port; 7212 int err; 7213 7214 if (!np && !pdata) 7215 return -EINVAL; 7216 7217 if (np) 7218 compat_info = of_device_get_match_data(dev); 7219 7220 if (pdata) { 7221 compat_info = pdata_device_get_match_data(dev); 7222 7223 if (!pdata->netdev) 7224 return -EINVAL; 7225 7226 for (port = 0; port < DSA_MAX_PORTS; port++) { 7227 if (!(pdata->enabled_ports & (1 << port))) 7228 continue; 7229 if (strcmp(pdata->cd.port_names[port], "cpu")) 7230 continue; 7231 pdata->cd.netdev[port] = &pdata->netdev->dev; 7232 break; 7233 } 7234 } 7235 7236 if (!compat_info) 7237 return -EINVAL; 7238 7239 chip = mv88e6xxx_alloc_chip(dev); 7240 if (!chip) { 7241 err = -ENOMEM; 7242 goto out; 7243 } 7244 7245 chip->info = compat_info; 7246 7247 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7248 if (IS_ERR(chip->reset)) { 7249 err = PTR_ERR(chip->reset); 7250 goto out; 7251 } 7252 if (chip->reset) 7253 usleep_range(10000, 20000); 7254 7255 /* Detect if the device is configured in single chip addressing mode, 7256 * otherwise continue with address specific smi init/detection. 7257 */ 7258 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7259 if (err) { 7260 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7261 if (err) 7262 goto out; 7263 7264 err = mv88e6xxx_detect(chip); 7265 if (err) 7266 goto out; 7267 } 7268 7269 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7270 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7271 else 7272 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7273 7274 mv88e6xxx_phy_init(chip); 7275 7276 if (chip->info->ops->get_eeprom) { 7277 if (np) 7278 of_property_read_u32(np, "eeprom-length", 7279 &chip->eeprom_len); 7280 else 7281 chip->eeprom_len = pdata->eeprom_len; 7282 } 7283 7284 mv88e6xxx_reg_lock(chip); 7285 err = mv88e6xxx_switch_reset(chip); 7286 mv88e6xxx_reg_unlock(chip); 7287 if (err) 7288 goto out; 7289 7290 if (np) { 7291 chip->irq = of_irq_get(np, 0); 7292 if (chip->irq == -EPROBE_DEFER) { 7293 err = chip->irq; 7294 goto out; 7295 } 7296 } 7297 7298 if (pdata) 7299 chip->irq = pdata->irq; 7300 7301 /* Has to be performed before the MDIO bus is created, because 7302 * the PHYs will link their interrupts to these interrupt 7303 * controllers 7304 */ 7305 mv88e6xxx_reg_lock(chip); 7306 if (chip->irq > 0) 7307 err = mv88e6xxx_g1_irq_setup(chip); 7308 else 7309 err = mv88e6xxx_irq_poll_setup(chip); 7310 mv88e6xxx_reg_unlock(chip); 7311 7312 if (err) 7313 goto out; 7314 7315 if (chip->info->g2_irqs > 0) { 7316 err = mv88e6xxx_g2_irq_setup(chip); 7317 if (err) 7318 goto out_g1_irq; 7319 } 7320 7321 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7322 if (err) 7323 goto out_g2_irq; 7324 7325 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7326 if (err) 7327 goto out_g1_atu_prob_irq; 7328 7329 err = mv88e6xxx_register_switch(chip); 7330 if (err) 7331 goto out_g1_vtu_prob_irq; 7332 7333 return 0; 7334 7335 out_g1_vtu_prob_irq: 7336 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7337 out_g1_atu_prob_irq: 7338 mv88e6xxx_g1_atu_prob_irq_free(chip); 7339 out_g2_irq: 7340 if (chip->info->g2_irqs > 0) 7341 mv88e6xxx_g2_irq_free(chip); 7342 out_g1_irq: 7343 if (chip->irq > 0) 7344 mv88e6xxx_g1_irq_free(chip); 7345 else 7346 mv88e6xxx_irq_poll_free(chip); 7347 out: 7348 if (pdata) 7349 dev_put(pdata->netdev); 7350 7351 return err; 7352 } 7353 7354 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7355 { 7356 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7357 struct mv88e6xxx_chip *chip; 7358 7359 if (!ds) 7360 return; 7361 7362 chip = ds->priv; 7363 7364 if (chip->info->ptp_support) { 7365 mv88e6xxx_hwtstamp_free(chip); 7366 mv88e6xxx_ptp_free(chip); 7367 } 7368 7369 mv88e6xxx_phy_destroy(chip); 7370 mv88e6xxx_unregister_switch(chip); 7371 7372 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7373 mv88e6xxx_g1_atu_prob_irq_free(chip); 7374 7375 if (chip->info->g2_irqs > 0) 7376 mv88e6xxx_g2_irq_free(chip); 7377 7378 if (chip->irq > 0) 7379 mv88e6xxx_g1_irq_free(chip); 7380 else 7381 mv88e6xxx_irq_poll_free(chip); 7382 } 7383 7384 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7385 { 7386 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7387 7388 if (!ds) 7389 return; 7390 7391 dsa_switch_shutdown(ds); 7392 7393 dev_set_drvdata(&mdiodev->dev, NULL); 7394 } 7395 7396 static const struct of_device_id mv88e6xxx_of_match[] = { 7397 { 7398 .compatible = "marvell,mv88e6085", 7399 .data = &mv88e6xxx_table[MV88E6085], 7400 }, 7401 { 7402 .compatible = "marvell,mv88e6190", 7403 .data = &mv88e6xxx_table[MV88E6190], 7404 }, 7405 { 7406 .compatible = "marvell,mv88e6250", 7407 .data = &mv88e6xxx_table[MV88E6250], 7408 }, 7409 { /* sentinel */ }, 7410 }; 7411 7412 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7413 7414 static struct mdio_driver mv88e6xxx_driver = { 7415 .probe = mv88e6xxx_probe, 7416 .remove = mv88e6xxx_remove, 7417 .shutdown = mv88e6xxx_shutdown, 7418 .mdiodrv.driver = { 7419 .name = "mv88e6085", 7420 .of_match_table = mv88e6xxx_of_match, 7421 .pm = &mv88e6xxx_pm_ops, 7422 }, 7423 }; 7424 7425 mdio_module_driver(mv88e6xxx_driver); 7426 7427 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7428 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7429 MODULE_LICENSE("GPL"); 7430