1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 453 mode = chip->info->ops->port_max_speed_mode(port); 454 455 if (chip->info->ops->port_set_pause) { 456 err = chip->info->ops->port_set_pause(chip, port, pause); 457 if (err) 458 goto restore_link; 459 } 460 461 err = mv88e6xxx_port_config_interface(chip, port, mode); 462 restore_link: 463 if (chip->info->ops->port_set_link(chip, port, link)) 464 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 465 466 return err; 467 } 468 469 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 470 { 471 struct mv88e6xxx_chip *chip = ds->priv; 472 473 return port < chip->info->num_internal_phys; 474 } 475 476 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 477 { 478 u16 reg; 479 int err; 480 481 /* The 88e6250 family does not have the PHY detect bit. Instead, 482 * report whether the port is internal. 483 */ 484 if (chip->info->family == MV88E6XXX_FAMILY_6250) 485 return port < chip->info->num_internal_phys; 486 487 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 488 if (err) { 489 dev_err(chip->dev, 490 "p%d: %s: failed to read port status\n", 491 port, __func__); 492 return err; 493 } 494 495 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 496 } 497 498 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 499 struct phylink_link_state *state) 500 { 501 struct mv88e6xxx_chip *chip = ds->priv; 502 int lane; 503 int err; 504 505 mv88e6xxx_reg_lock(chip); 506 lane = mv88e6xxx_serdes_get_lane(chip, port); 507 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 508 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 509 state); 510 else 511 err = -EOPNOTSUPP; 512 mv88e6xxx_reg_unlock(chip); 513 514 return err; 515 } 516 517 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 518 unsigned int mode, 519 phy_interface_t interface, 520 const unsigned long *advertise) 521 { 522 const struct mv88e6xxx_ops *ops = chip->info->ops; 523 int lane; 524 525 if (ops->serdes_pcs_config) { 526 lane = mv88e6xxx_serdes_get_lane(chip, port); 527 if (lane >= 0) 528 return ops->serdes_pcs_config(chip, port, lane, mode, 529 interface, advertise); 530 } 531 532 return 0; 533 } 534 535 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 536 { 537 struct mv88e6xxx_chip *chip = ds->priv; 538 const struct mv88e6xxx_ops *ops; 539 int err = 0; 540 int lane; 541 542 ops = chip->info->ops; 543 544 if (ops->serdes_pcs_an_restart) { 545 mv88e6xxx_reg_lock(chip); 546 lane = mv88e6xxx_serdes_get_lane(chip, port); 547 if (lane >= 0) 548 err = ops->serdes_pcs_an_restart(chip, port, lane); 549 mv88e6xxx_reg_unlock(chip); 550 551 if (err) 552 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 553 } 554 } 555 556 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 557 unsigned int mode, 558 int speed, int duplex) 559 { 560 const struct mv88e6xxx_ops *ops = chip->info->ops; 561 int lane; 562 563 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 564 lane = mv88e6xxx_serdes_get_lane(chip, port); 565 if (lane >= 0) 566 return ops->serdes_pcs_link_up(chip, port, lane, 567 speed, duplex); 568 } 569 570 return 0; 571 } 572 573 static const u8 mv88e6185_phy_interface_modes[] = { 574 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 575 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 576 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 577 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 578 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 579 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 580 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 581 }; 582 583 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 584 struct phylink_config *config) 585 { 586 u8 cmode = chip->ports[port].cmode; 587 588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 589 590 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 591 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 592 } else { 593 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 594 mv88e6185_phy_interface_modes[cmode]) 595 __set_bit(mv88e6185_phy_interface_modes[cmode], 596 config->supported_interfaces); 597 598 config->mac_capabilities |= MAC_1000FD; 599 } 600 } 601 602 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 603 struct phylink_config *config) 604 { 605 u8 cmode = chip->ports[port].cmode; 606 607 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 608 mv88e6185_phy_interface_modes[cmode]) 609 __set_bit(mv88e6185_phy_interface_modes[cmode], 610 config->supported_interfaces); 611 612 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 613 MAC_1000FD; 614 } 615 616 static const u8 mv88e6xxx_phy_interface_modes[] = { 617 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII, 618 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 619 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 620 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII, 621 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 622 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 623 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 624 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 625 /* higher interface modes are not needed here, since ports supporting 626 * them are writable, and so the supported interfaces are filled in the 627 * corresponding .phylink_set_interfaces() implementation below 628 */ 629 }; 630 631 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 632 { 633 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 634 mv88e6xxx_phy_interface_modes[cmode]) 635 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 636 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 637 phy_interface_set_rgmii(supported); 638 } 639 640 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 641 struct phylink_config *config) 642 { 643 unsigned long *supported = config->supported_interfaces; 644 645 /* Translate the default cmode */ 646 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 647 648 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 649 } 650 651 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 652 { 653 u16 reg, val; 654 int err; 655 656 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 657 if (err) 658 return err; 659 660 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 661 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 662 return 0xf; 663 664 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 665 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 666 if (err) 667 return err; 668 669 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 670 if (err) 671 return err; 672 673 /* Restore PHY_DETECT value */ 674 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 675 if (err) 676 return err; 677 678 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 679 } 680 681 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 682 struct phylink_config *config) 683 { 684 unsigned long *supported = config->supported_interfaces; 685 int err, cmode; 686 687 /* Translate the default cmode */ 688 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 689 690 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 691 MAC_1000FD; 692 693 /* Port 4 supports automedia if the serdes is associated with it. */ 694 if (port == 4) { 695 mv88e6xxx_reg_lock(chip); 696 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 697 if (err < 0) 698 dev_err(chip->dev, "p%d: failed to read scratch\n", 699 port); 700 if (err <= 0) 701 goto unlock; 702 703 cmode = mv88e6352_get_port4_serdes_cmode(chip); 704 if (cmode < 0) 705 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 706 port); 707 else 708 mv88e6xxx_translate_cmode(cmode, supported); 709 unlock: 710 mv88e6xxx_reg_unlock(chip); 711 } 712 } 713 714 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 715 struct phylink_config *config) 716 { 717 unsigned long *supported = config->supported_interfaces; 718 719 /* Translate the default cmode */ 720 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 721 722 /* No ethtool bits for 200Mbps */ 723 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 724 MAC_1000FD; 725 726 /* The C_Mode field is programmable on port 5 */ 727 if (port == 5) { 728 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 729 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 730 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 731 732 config->mac_capabilities |= MAC_2500FD; 733 } 734 } 735 736 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 737 struct phylink_config *config) 738 { 739 unsigned long *supported = config->supported_interfaces; 740 741 /* Translate the default cmode */ 742 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 743 744 /* No ethtool bits for 200Mbps */ 745 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 746 MAC_1000FD; 747 748 /* The C_Mode field is programmable on ports 9 and 10 */ 749 if (port == 9 || port == 10) { 750 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 751 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 753 754 config->mac_capabilities |= MAC_2500FD; 755 } 756 } 757 758 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 759 struct phylink_config *config) 760 { 761 unsigned long *supported = config->supported_interfaces; 762 763 mv88e6390_phylink_get_caps(chip, port, config); 764 765 /* For the 6x90X, ports 2-7 can be in automedia mode. 766 * (Note that 6x90 doesn't support RXAUI nor XAUI). 767 * 768 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 769 * configured for 1000BASE-X, SGMII or 2500BASE-X. 770 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 771 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 772 * 773 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 774 * configured for 1000BASE-X, SGMII or 2500BASE-X. 775 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 776 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 777 * 778 * For now, be permissive (as the old code was) and allow 1000BASE-X 779 * on ports 2..7. 780 */ 781 if (port >= 2 && port <= 7) 782 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 783 784 /* The C_Mode field can also be programmed for 10G speeds */ 785 if (port == 9 || port == 10) { 786 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 787 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 788 789 config->mac_capabilities |= MAC_10000FD; 790 } 791 } 792 793 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 794 struct phylink_config *config) 795 { 796 unsigned long *supported = config->supported_interfaces; 797 bool is_6191x = 798 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 799 800 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 801 802 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 803 MAC_1000FD; 804 805 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 806 if (port == 0 || port == 9 || port == 10) { 807 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 808 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 809 810 /* 6191X supports >1G modes only on port 10 */ 811 if (!is_6191x || port == 10) { 812 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 813 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 814 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 815 /* FIXME: USXGMII is not supported yet */ 816 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 817 818 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 819 MAC_10000FD; 820 } 821 } 822 } 823 824 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 825 struct phylink_config *config) 826 { 827 struct mv88e6xxx_chip *chip = ds->priv; 828 829 chip->info->ops->phylink_get_caps(chip, port, config); 830 831 /* Internal ports need GMII for PHYLIB */ 832 if (mv88e6xxx_phy_is_internal(ds, port)) 833 __set_bit(PHY_INTERFACE_MODE_GMII, 834 config->supported_interfaces); 835 } 836 837 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 838 unsigned int mode, 839 const struct phylink_link_state *state) 840 { 841 struct mv88e6xxx_chip *chip = ds->priv; 842 struct mv88e6xxx_port *p; 843 int err = 0; 844 845 p = &chip->ports[port]; 846 847 mv88e6xxx_reg_lock(chip); 848 849 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 850 /* In inband mode, the link may come up at any time while the 851 * link is not forced down. Force the link down while we 852 * reconfigure the interface mode. 853 */ 854 if (mode == MLO_AN_INBAND && 855 p->interface != state->interface && 856 chip->info->ops->port_set_link) 857 chip->info->ops->port_set_link(chip, port, 858 LINK_FORCED_DOWN); 859 860 err = mv88e6xxx_port_config_interface(chip, port, 861 state->interface); 862 if (err && err != -EOPNOTSUPP) 863 goto err_unlock; 864 865 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 866 state->interface, 867 state->advertising); 868 /* FIXME: we should restart negotiation if something changed - 869 * which is something we get if we convert to using phylinks 870 * PCS operations. 871 */ 872 if (err > 0) 873 err = 0; 874 } 875 876 /* Undo the forced down state above after completing configuration 877 * irrespective of its state on entry, which allows the link to come 878 * up in the in-band case where there is no separate SERDES. Also 879 * ensure that the link can come up if the PPU is in use and we are 880 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 881 */ 882 if (chip->info->ops->port_set_link && 883 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 884 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 885 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 886 887 p->interface = state->interface; 888 889 err_unlock: 890 mv88e6xxx_reg_unlock(chip); 891 892 if (err && err != -EOPNOTSUPP) 893 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 894 } 895 896 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 897 unsigned int mode, 898 phy_interface_t interface) 899 { 900 struct mv88e6xxx_chip *chip = ds->priv; 901 const struct mv88e6xxx_ops *ops; 902 int err = 0; 903 904 ops = chip->info->ops; 905 906 mv88e6xxx_reg_lock(chip); 907 /* Force the link down if we know the port may not be automatically 908 * updated by the switch or if we are using fixed-link mode. 909 */ 910 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 911 mode == MLO_AN_FIXED) && ops->port_sync_link) 912 err = ops->port_sync_link(chip, port, mode, false); 913 914 if (!err && ops->port_set_speed_duplex) 915 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 916 DUPLEX_UNFORCED); 917 mv88e6xxx_reg_unlock(chip); 918 919 if (err) 920 dev_err(chip->dev, 921 "p%d: failed to force MAC link down\n", port); 922 } 923 924 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 925 unsigned int mode, phy_interface_t interface, 926 struct phy_device *phydev, 927 int speed, int duplex, 928 bool tx_pause, bool rx_pause) 929 { 930 struct mv88e6xxx_chip *chip = ds->priv; 931 const struct mv88e6xxx_ops *ops; 932 int err = 0; 933 934 ops = chip->info->ops; 935 936 mv88e6xxx_reg_lock(chip); 937 /* Configure and force the link up if we know that the port may not 938 * automatically updated by the switch or if we are using fixed-link 939 * mode. 940 */ 941 if (!mv88e6xxx_port_ppu_updates(chip, port) || 942 mode == MLO_AN_FIXED) { 943 /* FIXME: for an automedia port, should we force the link 944 * down here - what if the link comes up due to "other" media 945 * while we're bringing the port up, how is the exclusivity 946 * handled in the Marvell hardware? E.g. port 2 on 88E6390 947 * shared between internal PHY and Serdes. 948 */ 949 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 950 duplex); 951 if (err) 952 goto error; 953 954 if (ops->port_set_speed_duplex) { 955 err = ops->port_set_speed_duplex(chip, port, 956 speed, duplex); 957 if (err && err != -EOPNOTSUPP) 958 goto error; 959 } 960 961 if (ops->port_sync_link) 962 err = ops->port_sync_link(chip, port, mode, true); 963 } 964 error: 965 mv88e6xxx_reg_unlock(chip); 966 967 if (err && err != -EOPNOTSUPP) 968 dev_err(ds->dev, 969 "p%d: failed to configure MAC link up\n", port); 970 } 971 972 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 973 { 974 if (!chip->info->ops->stats_snapshot) 975 return -EOPNOTSUPP; 976 977 return chip->info->ops->stats_snapshot(chip, port); 978 } 979 980 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 981 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 982 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 983 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 984 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 985 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 986 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 987 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 988 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 989 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 990 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 991 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 992 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 993 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 994 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 995 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 996 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 997 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 998 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 999 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1000 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1001 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1002 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1003 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1004 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1005 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1006 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1007 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1008 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1009 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1010 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1011 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1012 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1013 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1014 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1015 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1016 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1017 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1018 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1019 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1020 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1021 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1022 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1023 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1024 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1025 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1026 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1027 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1028 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1029 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1030 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1031 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1032 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1033 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1034 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1035 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1036 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1037 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1038 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1039 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1040 }; 1041 1042 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1043 struct mv88e6xxx_hw_stat *s, 1044 int port, u16 bank1_select, 1045 u16 histogram) 1046 { 1047 u32 low; 1048 u32 high = 0; 1049 u16 reg = 0; 1050 int err; 1051 u64 value; 1052 1053 switch (s->type) { 1054 case STATS_TYPE_PORT: 1055 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1056 if (err) 1057 return U64_MAX; 1058 1059 low = reg; 1060 if (s->size == 4) { 1061 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1062 if (err) 1063 return U64_MAX; 1064 low |= ((u32)reg) << 16; 1065 } 1066 break; 1067 case STATS_TYPE_BANK1: 1068 reg = bank1_select; 1069 fallthrough; 1070 case STATS_TYPE_BANK0: 1071 reg |= s->reg | histogram; 1072 mv88e6xxx_g1_stats_read(chip, reg, &low); 1073 if (s->size == 8) 1074 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1075 break; 1076 default: 1077 return U64_MAX; 1078 } 1079 value = (((u64)high) << 32) | low; 1080 return value; 1081 } 1082 1083 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1084 uint8_t *data, int types) 1085 { 1086 struct mv88e6xxx_hw_stat *stat; 1087 int i, j; 1088 1089 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1090 stat = &mv88e6xxx_hw_stats[i]; 1091 if (stat->type & types) { 1092 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1093 ETH_GSTRING_LEN); 1094 j++; 1095 } 1096 } 1097 1098 return j; 1099 } 1100 1101 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1102 uint8_t *data) 1103 { 1104 return mv88e6xxx_stats_get_strings(chip, data, 1105 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1106 } 1107 1108 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1109 uint8_t *data) 1110 { 1111 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1112 } 1113 1114 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1115 uint8_t *data) 1116 { 1117 return mv88e6xxx_stats_get_strings(chip, data, 1118 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1119 } 1120 1121 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1122 "atu_member_violation", 1123 "atu_miss_violation", 1124 "atu_full_violation", 1125 "vtu_member_violation", 1126 "vtu_miss_violation", 1127 }; 1128 1129 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1130 { 1131 unsigned int i; 1132 1133 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1134 strlcpy(data + i * ETH_GSTRING_LEN, 1135 mv88e6xxx_atu_vtu_stats_strings[i], 1136 ETH_GSTRING_LEN); 1137 } 1138 1139 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1140 u32 stringset, uint8_t *data) 1141 { 1142 struct mv88e6xxx_chip *chip = ds->priv; 1143 int count = 0; 1144 1145 if (stringset != ETH_SS_STATS) 1146 return; 1147 1148 mv88e6xxx_reg_lock(chip); 1149 1150 if (chip->info->ops->stats_get_strings) 1151 count = chip->info->ops->stats_get_strings(chip, data); 1152 1153 if (chip->info->ops->serdes_get_strings) { 1154 data += count * ETH_GSTRING_LEN; 1155 count = chip->info->ops->serdes_get_strings(chip, port, data); 1156 } 1157 1158 data += count * ETH_GSTRING_LEN; 1159 mv88e6xxx_atu_vtu_get_strings(data); 1160 1161 mv88e6xxx_reg_unlock(chip); 1162 } 1163 1164 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1165 int types) 1166 { 1167 struct mv88e6xxx_hw_stat *stat; 1168 int i, j; 1169 1170 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1171 stat = &mv88e6xxx_hw_stats[i]; 1172 if (stat->type & types) 1173 j++; 1174 } 1175 return j; 1176 } 1177 1178 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1179 { 1180 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1181 STATS_TYPE_PORT); 1182 } 1183 1184 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1185 { 1186 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1187 } 1188 1189 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1190 { 1191 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1192 STATS_TYPE_BANK1); 1193 } 1194 1195 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1196 { 1197 struct mv88e6xxx_chip *chip = ds->priv; 1198 int serdes_count = 0; 1199 int count = 0; 1200 1201 if (sset != ETH_SS_STATS) 1202 return 0; 1203 1204 mv88e6xxx_reg_lock(chip); 1205 if (chip->info->ops->stats_get_sset_count) 1206 count = chip->info->ops->stats_get_sset_count(chip); 1207 if (count < 0) 1208 goto out; 1209 1210 if (chip->info->ops->serdes_get_sset_count) 1211 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1212 port); 1213 if (serdes_count < 0) { 1214 count = serdes_count; 1215 goto out; 1216 } 1217 count += serdes_count; 1218 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1219 1220 out: 1221 mv88e6xxx_reg_unlock(chip); 1222 1223 return count; 1224 } 1225 1226 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1227 uint64_t *data, int types, 1228 u16 bank1_select, u16 histogram) 1229 { 1230 struct mv88e6xxx_hw_stat *stat; 1231 int i, j; 1232 1233 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1234 stat = &mv88e6xxx_hw_stats[i]; 1235 if (stat->type & types) { 1236 mv88e6xxx_reg_lock(chip); 1237 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1238 bank1_select, 1239 histogram); 1240 mv88e6xxx_reg_unlock(chip); 1241 1242 j++; 1243 } 1244 } 1245 return j; 1246 } 1247 1248 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1249 uint64_t *data) 1250 { 1251 return mv88e6xxx_stats_get_stats(chip, port, data, 1252 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1253 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1254 } 1255 1256 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1257 uint64_t *data) 1258 { 1259 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1261 } 1262 1263 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1264 uint64_t *data) 1265 { 1266 return mv88e6xxx_stats_get_stats(chip, port, data, 1267 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1268 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1269 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1270 } 1271 1272 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1273 uint64_t *data) 1274 { 1275 return mv88e6xxx_stats_get_stats(chip, port, data, 1276 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1277 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1278 0); 1279 } 1280 1281 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1282 uint64_t *data) 1283 { 1284 *data++ = chip->ports[port].atu_member_violation; 1285 *data++ = chip->ports[port].atu_miss_violation; 1286 *data++ = chip->ports[port].atu_full_violation; 1287 *data++ = chip->ports[port].vtu_member_violation; 1288 *data++ = chip->ports[port].vtu_miss_violation; 1289 } 1290 1291 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1292 uint64_t *data) 1293 { 1294 int count = 0; 1295 1296 if (chip->info->ops->stats_get_stats) 1297 count = chip->info->ops->stats_get_stats(chip, port, data); 1298 1299 mv88e6xxx_reg_lock(chip); 1300 if (chip->info->ops->serdes_get_stats) { 1301 data += count; 1302 count = chip->info->ops->serdes_get_stats(chip, port, data); 1303 } 1304 data += count; 1305 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1306 mv88e6xxx_reg_unlock(chip); 1307 } 1308 1309 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1310 uint64_t *data) 1311 { 1312 struct mv88e6xxx_chip *chip = ds->priv; 1313 int ret; 1314 1315 mv88e6xxx_reg_lock(chip); 1316 1317 ret = mv88e6xxx_stats_snapshot(chip, port); 1318 mv88e6xxx_reg_unlock(chip); 1319 1320 if (ret < 0) 1321 return; 1322 1323 mv88e6xxx_get_stats(chip, port, data); 1324 1325 } 1326 1327 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1328 { 1329 struct mv88e6xxx_chip *chip = ds->priv; 1330 int len; 1331 1332 len = 32 * sizeof(u16); 1333 if (chip->info->ops->serdes_get_regs_len) 1334 len += chip->info->ops->serdes_get_regs_len(chip, port); 1335 1336 return len; 1337 } 1338 1339 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1340 struct ethtool_regs *regs, void *_p) 1341 { 1342 struct mv88e6xxx_chip *chip = ds->priv; 1343 int err; 1344 u16 reg; 1345 u16 *p = _p; 1346 int i; 1347 1348 regs->version = chip->info->prod_num; 1349 1350 memset(p, 0xff, 32 * sizeof(u16)); 1351 1352 mv88e6xxx_reg_lock(chip); 1353 1354 for (i = 0; i < 32; i++) { 1355 1356 err = mv88e6xxx_port_read(chip, port, i, ®); 1357 if (!err) 1358 p[i] = reg; 1359 } 1360 1361 if (chip->info->ops->serdes_get_regs) 1362 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1363 1364 mv88e6xxx_reg_unlock(chip); 1365 } 1366 1367 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1368 struct ethtool_eee *e) 1369 { 1370 /* Nothing to do on the port's MAC */ 1371 return 0; 1372 } 1373 1374 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1375 struct ethtool_eee *e) 1376 { 1377 /* Nothing to do on the port's MAC */ 1378 return 0; 1379 } 1380 1381 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1382 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1383 { 1384 struct dsa_switch *ds = chip->ds; 1385 struct dsa_switch_tree *dst = ds->dst; 1386 struct dsa_port *dp, *other_dp; 1387 bool found = false; 1388 u16 pvlan; 1389 1390 /* dev is a physical switch */ 1391 if (dev <= dst->last_switch) { 1392 list_for_each_entry(dp, &dst->ports, list) { 1393 if (dp->ds->index == dev && dp->index == port) { 1394 /* dp might be a DSA link or a user port, so it 1395 * might or might not have a bridge. 1396 * Use the "found" variable for both cases. 1397 */ 1398 found = true; 1399 break; 1400 } 1401 } 1402 /* dev is a virtual bridge */ 1403 } else { 1404 list_for_each_entry(dp, &dst->ports, list) { 1405 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1406 1407 if (!bridge_num) 1408 continue; 1409 1410 if (bridge_num + dst->last_switch != dev) 1411 continue; 1412 1413 found = true; 1414 break; 1415 } 1416 } 1417 1418 /* Prevent frames from unknown switch or virtual bridge */ 1419 if (!found) 1420 return 0; 1421 1422 /* Frames from DSA links and CPU ports can egress any local port */ 1423 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1424 return mv88e6xxx_port_mask(chip); 1425 1426 pvlan = 0; 1427 1428 /* Frames from standalone user ports can only egress on the 1429 * upstream port. 1430 */ 1431 if (!dsa_port_bridge_dev_get(dp)) 1432 return BIT(dsa_switch_upstream_port(ds)); 1433 1434 /* Frames from bridged user ports can egress any local DSA 1435 * links and CPU ports, as well as any local member of their 1436 * bridge group. 1437 */ 1438 dsa_switch_for_each_port(other_dp, ds) 1439 if (other_dp->type == DSA_PORT_TYPE_CPU || 1440 other_dp->type == DSA_PORT_TYPE_DSA || 1441 dsa_port_bridge_same(dp, other_dp)) 1442 pvlan |= BIT(other_dp->index); 1443 1444 return pvlan; 1445 } 1446 1447 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1448 { 1449 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1450 1451 /* prevent frames from going back out of the port they came in on */ 1452 output_ports &= ~BIT(port); 1453 1454 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1455 } 1456 1457 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1458 u8 state) 1459 { 1460 struct mv88e6xxx_chip *chip = ds->priv; 1461 int err; 1462 1463 mv88e6xxx_reg_lock(chip); 1464 err = mv88e6xxx_port_set_state(chip, port, state); 1465 mv88e6xxx_reg_unlock(chip); 1466 1467 if (err) 1468 dev_err(ds->dev, "p%d: failed to update state\n", port); 1469 } 1470 1471 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1472 { 1473 int err; 1474 1475 if (chip->info->ops->ieee_pri_map) { 1476 err = chip->info->ops->ieee_pri_map(chip); 1477 if (err) 1478 return err; 1479 } 1480 1481 if (chip->info->ops->ip_pri_map) { 1482 err = chip->info->ops->ip_pri_map(chip); 1483 if (err) 1484 return err; 1485 } 1486 1487 return 0; 1488 } 1489 1490 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1491 { 1492 struct dsa_switch *ds = chip->ds; 1493 int target, port; 1494 int err; 1495 1496 if (!chip->info->global2_addr) 1497 return 0; 1498 1499 /* Initialize the routing port to the 32 possible target devices */ 1500 for (target = 0; target < 32; target++) { 1501 port = dsa_routing_port(ds, target); 1502 if (port == ds->num_ports) 1503 port = 0x1f; 1504 1505 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1506 if (err) 1507 return err; 1508 } 1509 1510 if (chip->info->ops->set_cascade_port) { 1511 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1512 err = chip->info->ops->set_cascade_port(chip, port); 1513 if (err) 1514 return err; 1515 } 1516 1517 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1518 if (err) 1519 return err; 1520 1521 return 0; 1522 } 1523 1524 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1525 { 1526 /* Clear all trunk masks and mapping */ 1527 if (chip->info->global2_addr) 1528 return mv88e6xxx_g2_trunk_clear(chip); 1529 1530 return 0; 1531 } 1532 1533 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1534 { 1535 if (chip->info->ops->rmu_disable) 1536 return chip->info->ops->rmu_disable(chip); 1537 1538 return 0; 1539 } 1540 1541 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1542 { 1543 if (chip->info->ops->pot_clear) 1544 return chip->info->ops->pot_clear(chip); 1545 1546 return 0; 1547 } 1548 1549 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1550 { 1551 if (chip->info->ops->mgmt_rsvd2cpu) 1552 return chip->info->ops->mgmt_rsvd2cpu(chip); 1553 1554 return 0; 1555 } 1556 1557 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1558 { 1559 int err; 1560 1561 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1562 if (err) 1563 return err; 1564 1565 /* The chips that have a "learn2all" bit in Global1, ATU 1566 * Control are precisely those whose port registers have a 1567 * Message Port bit in Port Control 1 and hence implement 1568 * ->port_setup_message_port. 1569 */ 1570 if (chip->info->ops->port_setup_message_port) { 1571 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1572 if (err) 1573 return err; 1574 } 1575 1576 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1577 } 1578 1579 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1580 { 1581 int port; 1582 int err; 1583 1584 if (!chip->info->ops->irl_init_all) 1585 return 0; 1586 1587 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1588 /* Disable ingress rate limiting by resetting all per port 1589 * ingress rate limit resources to their initial state. 1590 */ 1591 err = chip->info->ops->irl_init_all(chip, port); 1592 if (err) 1593 return err; 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1600 { 1601 if (chip->info->ops->set_switch_mac) { 1602 u8 addr[ETH_ALEN]; 1603 1604 eth_random_addr(addr); 1605 1606 return chip->info->ops->set_switch_mac(chip, addr); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1613 { 1614 struct dsa_switch_tree *dst = chip->ds->dst; 1615 struct dsa_switch *ds; 1616 struct dsa_port *dp; 1617 u16 pvlan = 0; 1618 1619 if (!mv88e6xxx_has_pvt(chip)) 1620 return 0; 1621 1622 /* Skip the local source device, which uses in-chip port VLAN */ 1623 if (dev != chip->ds->index) { 1624 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1625 1626 ds = dsa_switch_find(dst->index, dev); 1627 dp = ds ? dsa_to_port(ds, port) : NULL; 1628 if (dp && dp->lag) { 1629 /* As the PVT is used to limit flooding of 1630 * FORWARD frames, which use the LAG ID as the 1631 * source port, we must translate dev/port to 1632 * the special "LAG device" in the PVT, using 1633 * the LAG ID (one-based) as the port number 1634 * (zero-based). 1635 */ 1636 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1637 port = dsa_port_lag_id_get(dp) - 1; 1638 } 1639 } 1640 1641 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1642 } 1643 1644 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1645 { 1646 int dev, port; 1647 int err; 1648 1649 if (!mv88e6xxx_has_pvt(chip)) 1650 return 0; 1651 1652 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1653 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1654 */ 1655 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1656 if (err) 1657 return err; 1658 1659 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1660 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1661 err = mv88e6xxx_pvt_map(chip, dev, port); 1662 if (err) 1663 return err; 1664 } 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1671 { 1672 struct mv88e6xxx_chip *chip = ds->priv; 1673 int err; 1674 1675 if (dsa_to_port(ds, port)->lag) 1676 /* Hardware is incapable of fast-aging a LAG through a 1677 * regular ATU move operation. Until we have something 1678 * more fancy in place this is a no-op. 1679 */ 1680 return; 1681 1682 mv88e6xxx_reg_lock(chip); 1683 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1684 mv88e6xxx_reg_unlock(chip); 1685 1686 if (err) 1687 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1688 } 1689 1690 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1691 { 1692 if (!mv88e6xxx_max_vid(chip)) 1693 return 0; 1694 1695 return mv88e6xxx_g1_vtu_flush(chip); 1696 } 1697 1698 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1699 struct mv88e6xxx_vtu_entry *entry) 1700 { 1701 int err; 1702 1703 if (!chip->info->ops->vtu_getnext) 1704 return -EOPNOTSUPP; 1705 1706 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1707 entry->valid = false; 1708 1709 err = chip->info->ops->vtu_getnext(chip, entry); 1710 1711 if (entry->vid != vid) 1712 entry->valid = false; 1713 1714 return err; 1715 } 1716 1717 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1718 int (*cb)(struct mv88e6xxx_chip *chip, 1719 const struct mv88e6xxx_vtu_entry *entry, 1720 void *priv), 1721 void *priv) 1722 { 1723 struct mv88e6xxx_vtu_entry entry = { 1724 .vid = mv88e6xxx_max_vid(chip), 1725 .valid = false, 1726 }; 1727 int err; 1728 1729 if (!chip->info->ops->vtu_getnext) 1730 return -EOPNOTSUPP; 1731 1732 do { 1733 err = chip->info->ops->vtu_getnext(chip, &entry); 1734 if (err) 1735 return err; 1736 1737 if (!entry.valid) 1738 break; 1739 1740 err = cb(chip, &entry, priv); 1741 if (err) 1742 return err; 1743 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1744 1745 return 0; 1746 } 1747 1748 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1749 struct mv88e6xxx_vtu_entry *entry) 1750 { 1751 if (!chip->info->ops->vtu_loadpurge) 1752 return -EOPNOTSUPP; 1753 1754 return chip->info->ops->vtu_loadpurge(chip, entry); 1755 } 1756 1757 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1758 const struct mv88e6xxx_vtu_entry *entry, 1759 void *_fid_bitmap) 1760 { 1761 unsigned long *fid_bitmap = _fid_bitmap; 1762 1763 set_bit(entry->fid, fid_bitmap); 1764 return 0; 1765 } 1766 1767 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1768 { 1769 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1770 1771 /* Every FID has an associated VID, so walking the VTU 1772 * will discover the full set of FIDs in use. 1773 */ 1774 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1775 } 1776 1777 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1778 { 1779 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1780 int err; 1781 1782 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1783 if (err) 1784 return err; 1785 1786 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1787 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1788 return -ENOSPC; 1789 1790 /* Clear the database */ 1791 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1792 } 1793 1794 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1795 u16 vid) 1796 { 1797 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1798 struct mv88e6xxx_chip *chip = ds->priv; 1799 struct mv88e6xxx_vtu_entry vlan; 1800 int err; 1801 1802 /* DSA and CPU ports have to be members of multiple vlans */ 1803 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1804 return 0; 1805 1806 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1807 if (err) 1808 return err; 1809 1810 if (!vlan.valid) 1811 return 0; 1812 1813 dsa_switch_for_each_user_port(other_dp, ds) { 1814 struct net_device *other_br; 1815 1816 if (vlan.member[other_dp->index] == 1817 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1818 continue; 1819 1820 if (dsa_port_bridge_same(dp, other_dp)) 1821 break; /* same bridge, check next VLAN */ 1822 1823 other_br = dsa_port_bridge_dev_get(other_dp); 1824 if (!other_br) 1825 continue; 1826 1827 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1828 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1829 return -EOPNOTSUPP; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1836 { 1837 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1838 struct net_device *br = dsa_port_bridge_dev_get(dp); 1839 struct mv88e6xxx_port *p = &chip->ports[port]; 1840 u16 pvid = MV88E6XXX_VID_STANDALONE; 1841 bool drop_untagged = false; 1842 int err; 1843 1844 if (br) { 1845 if (br_vlan_enabled(br)) { 1846 pvid = p->bridge_pvid.vid; 1847 drop_untagged = !p->bridge_pvid.valid; 1848 } else { 1849 pvid = MV88E6XXX_VID_BRIDGED; 1850 } 1851 } 1852 1853 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1854 if (err) 1855 return err; 1856 1857 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1858 } 1859 1860 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1861 bool vlan_filtering, 1862 struct netlink_ext_ack *extack) 1863 { 1864 struct mv88e6xxx_chip *chip = ds->priv; 1865 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1866 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1867 int err; 1868 1869 if (!mv88e6xxx_max_vid(chip)) 1870 return -EOPNOTSUPP; 1871 1872 mv88e6xxx_reg_lock(chip); 1873 1874 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1875 if (err) 1876 goto unlock; 1877 1878 err = mv88e6xxx_port_commit_pvid(chip, port); 1879 if (err) 1880 goto unlock; 1881 1882 unlock: 1883 mv88e6xxx_reg_unlock(chip); 1884 1885 return err; 1886 } 1887 1888 static int 1889 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1890 const struct switchdev_obj_port_vlan *vlan) 1891 { 1892 struct mv88e6xxx_chip *chip = ds->priv; 1893 int err; 1894 1895 if (!mv88e6xxx_max_vid(chip)) 1896 return -EOPNOTSUPP; 1897 1898 /* If the requested port doesn't belong to the same bridge as the VLAN 1899 * members, do not support it (yet) and fallback to software VLAN. 1900 */ 1901 mv88e6xxx_reg_lock(chip); 1902 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1903 mv88e6xxx_reg_unlock(chip); 1904 1905 return err; 1906 } 1907 1908 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1909 const unsigned char *addr, u16 vid, 1910 u8 state) 1911 { 1912 struct mv88e6xxx_atu_entry entry; 1913 struct mv88e6xxx_vtu_entry vlan; 1914 u16 fid; 1915 int err; 1916 1917 /* Ports have two private address databases: one for when the port is 1918 * standalone and one for when the port is under a bridge and the 1919 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1920 * address database to remain 100% empty, so we never load an ATU entry 1921 * into a standalone port's database. Therefore, translate the null 1922 * VLAN ID into the port's database used for VLAN-unaware bridging. 1923 */ 1924 if (vid == 0) { 1925 fid = MV88E6XXX_FID_BRIDGED; 1926 } else { 1927 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1928 if (err) 1929 return err; 1930 1931 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1932 if (!vlan.valid) 1933 return -EOPNOTSUPP; 1934 1935 fid = vlan.fid; 1936 } 1937 1938 entry.state = 0; 1939 ether_addr_copy(entry.mac, addr); 1940 eth_addr_dec(entry.mac); 1941 1942 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1943 if (err) 1944 return err; 1945 1946 /* Initialize a fresh ATU entry if it isn't found */ 1947 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1948 memset(&entry, 0, sizeof(entry)); 1949 ether_addr_copy(entry.mac, addr); 1950 } 1951 1952 /* Purge the ATU entry only if no port is using it anymore */ 1953 if (!state) { 1954 entry.portvec &= ~BIT(port); 1955 if (!entry.portvec) 1956 entry.state = 0; 1957 } else { 1958 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1959 entry.portvec = BIT(port); 1960 else 1961 entry.portvec |= BIT(port); 1962 1963 entry.state = state; 1964 } 1965 1966 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1967 } 1968 1969 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1970 const struct mv88e6xxx_policy *policy) 1971 { 1972 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1973 enum mv88e6xxx_policy_action action = policy->action; 1974 const u8 *addr = policy->addr; 1975 u16 vid = policy->vid; 1976 u8 state; 1977 int err; 1978 int id; 1979 1980 if (!chip->info->ops->port_set_policy) 1981 return -EOPNOTSUPP; 1982 1983 switch (mapping) { 1984 case MV88E6XXX_POLICY_MAPPING_DA: 1985 case MV88E6XXX_POLICY_MAPPING_SA: 1986 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1987 state = 0; /* Dissociate the port and address */ 1988 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1989 is_multicast_ether_addr(addr)) 1990 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1991 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1992 is_unicast_ether_addr(addr)) 1993 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1994 else 1995 return -EOPNOTSUPP; 1996 1997 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1998 state); 1999 if (err) 2000 return err; 2001 break; 2002 default: 2003 return -EOPNOTSUPP; 2004 } 2005 2006 /* Skip the port's policy clearing if the mapping is still in use */ 2007 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2008 idr_for_each_entry(&chip->policies, policy, id) 2009 if (policy->port == port && 2010 policy->mapping == mapping && 2011 policy->action != action) 2012 return 0; 2013 2014 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2015 } 2016 2017 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2018 struct ethtool_rx_flow_spec *fs) 2019 { 2020 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2021 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2022 enum mv88e6xxx_policy_mapping mapping; 2023 enum mv88e6xxx_policy_action action; 2024 struct mv88e6xxx_policy *policy; 2025 u16 vid = 0; 2026 u8 *addr; 2027 int err; 2028 int id; 2029 2030 if (fs->location != RX_CLS_LOC_ANY) 2031 return -EINVAL; 2032 2033 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2034 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2035 else 2036 return -EOPNOTSUPP; 2037 2038 switch (fs->flow_type & ~FLOW_EXT) { 2039 case ETHER_FLOW: 2040 if (!is_zero_ether_addr(mac_mask->h_dest) && 2041 is_zero_ether_addr(mac_mask->h_source)) { 2042 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2043 addr = mac_entry->h_dest; 2044 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2045 !is_zero_ether_addr(mac_mask->h_source)) { 2046 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2047 addr = mac_entry->h_source; 2048 } else { 2049 /* Cannot support DA and SA mapping in the same rule */ 2050 return -EOPNOTSUPP; 2051 } 2052 break; 2053 default: 2054 return -EOPNOTSUPP; 2055 } 2056 2057 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2058 if (fs->m_ext.vlan_tci != htons(0xffff)) 2059 return -EOPNOTSUPP; 2060 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2061 } 2062 2063 idr_for_each_entry(&chip->policies, policy, id) { 2064 if (policy->port == port && policy->mapping == mapping && 2065 policy->action == action && policy->vid == vid && 2066 ether_addr_equal(policy->addr, addr)) 2067 return -EEXIST; 2068 } 2069 2070 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2071 if (!policy) 2072 return -ENOMEM; 2073 2074 fs->location = 0; 2075 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2076 GFP_KERNEL); 2077 if (err) { 2078 devm_kfree(chip->dev, policy); 2079 return err; 2080 } 2081 2082 memcpy(&policy->fs, fs, sizeof(*fs)); 2083 ether_addr_copy(policy->addr, addr); 2084 policy->mapping = mapping; 2085 policy->action = action; 2086 policy->port = port; 2087 policy->vid = vid; 2088 2089 err = mv88e6xxx_policy_apply(chip, port, policy); 2090 if (err) { 2091 idr_remove(&chip->policies, fs->location); 2092 devm_kfree(chip->dev, policy); 2093 return err; 2094 } 2095 2096 return 0; 2097 } 2098 2099 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2100 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2101 { 2102 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2103 struct mv88e6xxx_chip *chip = ds->priv; 2104 struct mv88e6xxx_policy *policy; 2105 int err; 2106 int id; 2107 2108 mv88e6xxx_reg_lock(chip); 2109 2110 switch (rxnfc->cmd) { 2111 case ETHTOOL_GRXCLSRLCNT: 2112 rxnfc->data = 0; 2113 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2114 rxnfc->rule_cnt = 0; 2115 idr_for_each_entry(&chip->policies, policy, id) 2116 if (policy->port == port) 2117 rxnfc->rule_cnt++; 2118 err = 0; 2119 break; 2120 case ETHTOOL_GRXCLSRULE: 2121 err = -ENOENT; 2122 policy = idr_find(&chip->policies, fs->location); 2123 if (policy) { 2124 memcpy(fs, &policy->fs, sizeof(*fs)); 2125 err = 0; 2126 } 2127 break; 2128 case ETHTOOL_GRXCLSRLALL: 2129 rxnfc->data = 0; 2130 rxnfc->rule_cnt = 0; 2131 idr_for_each_entry(&chip->policies, policy, id) 2132 if (policy->port == port) 2133 rule_locs[rxnfc->rule_cnt++] = id; 2134 err = 0; 2135 break; 2136 default: 2137 err = -EOPNOTSUPP; 2138 break; 2139 } 2140 2141 mv88e6xxx_reg_unlock(chip); 2142 2143 return err; 2144 } 2145 2146 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2147 struct ethtool_rxnfc *rxnfc) 2148 { 2149 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2150 struct mv88e6xxx_chip *chip = ds->priv; 2151 struct mv88e6xxx_policy *policy; 2152 int err; 2153 2154 mv88e6xxx_reg_lock(chip); 2155 2156 switch (rxnfc->cmd) { 2157 case ETHTOOL_SRXCLSRLINS: 2158 err = mv88e6xxx_policy_insert(chip, port, fs); 2159 break; 2160 case ETHTOOL_SRXCLSRLDEL: 2161 err = -ENOENT; 2162 policy = idr_remove(&chip->policies, fs->location); 2163 if (policy) { 2164 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2165 err = mv88e6xxx_policy_apply(chip, port, policy); 2166 devm_kfree(chip->dev, policy); 2167 } 2168 break; 2169 default: 2170 err = -EOPNOTSUPP; 2171 break; 2172 } 2173 2174 mv88e6xxx_reg_unlock(chip); 2175 2176 return err; 2177 } 2178 2179 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2180 u16 vid) 2181 { 2182 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2183 u8 broadcast[ETH_ALEN]; 2184 2185 eth_broadcast_addr(broadcast); 2186 2187 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2188 } 2189 2190 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2191 { 2192 int port; 2193 int err; 2194 2195 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2196 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2197 struct net_device *brport; 2198 2199 if (dsa_is_unused_port(chip->ds, port)) 2200 continue; 2201 2202 brport = dsa_port_to_bridge_port(dp); 2203 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2204 /* Skip bridged user ports where broadcast 2205 * flooding is disabled. 2206 */ 2207 continue; 2208 2209 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2210 if (err) 2211 return err; 2212 } 2213 2214 return 0; 2215 } 2216 2217 struct mv88e6xxx_port_broadcast_sync_ctx { 2218 int port; 2219 bool flood; 2220 }; 2221 2222 static int 2223 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2224 const struct mv88e6xxx_vtu_entry *vlan, 2225 void *_ctx) 2226 { 2227 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2228 u8 broadcast[ETH_ALEN]; 2229 u8 state; 2230 2231 if (ctx->flood) 2232 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2233 else 2234 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2235 2236 eth_broadcast_addr(broadcast); 2237 2238 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2239 vlan->vid, state); 2240 } 2241 2242 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2243 bool flood) 2244 { 2245 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2246 .port = port, 2247 .flood = flood, 2248 }; 2249 struct mv88e6xxx_vtu_entry vid0 = { 2250 .vid = 0, 2251 }; 2252 int err; 2253 2254 /* Update the port's private database... */ 2255 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2256 if (err) 2257 return err; 2258 2259 /* ...and the database for all VLANs. */ 2260 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2261 &ctx); 2262 } 2263 2264 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2265 u16 vid, u8 member, bool warn) 2266 { 2267 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2268 struct mv88e6xxx_vtu_entry vlan; 2269 int i, err; 2270 2271 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2272 if (err) 2273 return err; 2274 2275 if (!vlan.valid) { 2276 memset(&vlan, 0, sizeof(vlan)); 2277 2278 if (vid == MV88E6XXX_VID_STANDALONE) 2279 vlan.policy = true; 2280 2281 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2282 if (err) 2283 return err; 2284 2285 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2286 if (i == port) 2287 vlan.member[i] = member; 2288 else 2289 vlan.member[i] = non_member; 2290 2291 vlan.vid = vid; 2292 vlan.valid = true; 2293 2294 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2295 if (err) 2296 return err; 2297 2298 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2299 if (err) 2300 return err; 2301 } else if (vlan.member[port] != member) { 2302 vlan.member[port] = member; 2303 2304 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2305 if (err) 2306 return err; 2307 } else if (warn) { 2308 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2309 port, vid); 2310 } 2311 2312 return 0; 2313 } 2314 2315 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2316 const struct switchdev_obj_port_vlan *vlan, 2317 struct netlink_ext_ack *extack) 2318 { 2319 struct mv88e6xxx_chip *chip = ds->priv; 2320 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2321 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2322 struct mv88e6xxx_port *p = &chip->ports[port]; 2323 bool warn; 2324 u8 member; 2325 int err; 2326 2327 if (!vlan->vid) 2328 return 0; 2329 2330 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2331 if (err) 2332 return err; 2333 2334 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2335 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2336 else if (untagged) 2337 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2338 else 2339 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2340 2341 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2342 * and then the CPU port. Do not warn for duplicates for the CPU port. 2343 */ 2344 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2345 2346 mv88e6xxx_reg_lock(chip); 2347 2348 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2349 if (err) { 2350 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2351 vlan->vid, untagged ? 'u' : 't'); 2352 goto out; 2353 } 2354 2355 if (pvid) { 2356 p->bridge_pvid.vid = vlan->vid; 2357 p->bridge_pvid.valid = true; 2358 2359 err = mv88e6xxx_port_commit_pvid(chip, port); 2360 if (err) 2361 goto out; 2362 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2363 /* The old pvid was reinstalled as a non-pvid VLAN */ 2364 p->bridge_pvid.valid = false; 2365 2366 err = mv88e6xxx_port_commit_pvid(chip, port); 2367 if (err) 2368 goto out; 2369 } 2370 2371 out: 2372 mv88e6xxx_reg_unlock(chip); 2373 2374 return err; 2375 } 2376 2377 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2378 int port, u16 vid) 2379 { 2380 struct mv88e6xxx_vtu_entry vlan; 2381 int i, err; 2382 2383 if (!vid) 2384 return 0; 2385 2386 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2387 if (err) 2388 return err; 2389 2390 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2391 * tell switchdev that this VLAN is likely handled in software. 2392 */ 2393 if (!vlan.valid || 2394 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2395 return -EOPNOTSUPP; 2396 2397 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2398 2399 /* keep the VLAN unless all ports are excluded */ 2400 vlan.valid = false; 2401 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2402 if (vlan.member[i] != 2403 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2404 vlan.valid = true; 2405 break; 2406 } 2407 } 2408 2409 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2410 if (err) 2411 return err; 2412 2413 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2414 } 2415 2416 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2417 const struct switchdev_obj_port_vlan *vlan) 2418 { 2419 struct mv88e6xxx_chip *chip = ds->priv; 2420 struct mv88e6xxx_port *p = &chip->ports[port]; 2421 int err = 0; 2422 u16 pvid; 2423 2424 if (!mv88e6xxx_max_vid(chip)) 2425 return -EOPNOTSUPP; 2426 2427 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2428 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2429 * switchdev workqueue to ensure that all FDB entries are deleted 2430 * before we remove the VLAN. 2431 */ 2432 dsa_flush_workqueue(); 2433 2434 mv88e6xxx_reg_lock(chip); 2435 2436 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2437 if (err) 2438 goto unlock; 2439 2440 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2441 if (err) 2442 goto unlock; 2443 2444 if (vlan->vid == pvid) { 2445 p->bridge_pvid.valid = false; 2446 2447 err = mv88e6xxx_port_commit_pvid(chip, port); 2448 if (err) 2449 goto unlock; 2450 } 2451 2452 unlock: 2453 mv88e6xxx_reg_unlock(chip); 2454 2455 return err; 2456 } 2457 2458 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2459 const unsigned char *addr, u16 vid, 2460 struct dsa_db db) 2461 { 2462 struct mv88e6xxx_chip *chip = ds->priv; 2463 int err; 2464 2465 mv88e6xxx_reg_lock(chip); 2466 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2467 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2468 mv88e6xxx_reg_unlock(chip); 2469 2470 return err; 2471 } 2472 2473 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2474 const unsigned char *addr, u16 vid, 2475 struct dsa_db db) 2476 { 2477 struct mv88e6xxx_chip *chip = ds->priv; 2478 int err; 2479 2480 mv88e6xxx_reg_lock(chip); 2481 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2482 mv88e6xxx_reg_unlock(chip); 2483 2484 return err; 2485 } 2486 2487 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2488 u16 fid, u16 vid, int port, 2489 dsa_fdb_dump_cb_t *cb, void *data) 2490 { 2491 struct mv88e6xxx_atu_entry addr; 2492 bool is_static; 2493 int err; 2494 2495 addr.state = 0; 2496 eth_broadcast_addr(addr.mac); 2497 2498 do { 2499 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2500 if (err) 2501 return err; 2502 2503 if (!addr.state) 2504 break; 2505 2506 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2507 continue; 2508 2509 if (!is_unicast_ether_addr(addr.mac)) 2510 continue; 2511 2512 is_static = (addr.state == 2513 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2514 err = cb(addr.mac, vid, is_static, data); 2515 if (err) 2516 return err; 2517 } while (!is_broadcast_ether_addr(addr.mac)); 2518 2519 return err; 2520 } 2521 2522 struct mv88e6xxx_port_db_dump_vlan_ctx { 2523 int port; 2524 dsa_fdb_dump_cb_t *cb; 2525 void *data; 2526 }; 2527 2528 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2529 const struct mv88e6xxx_vtu_entry *entry, 2530 void *_data) 2531 { 2532 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2533 2534 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2535 ctx->port, ctx->cb, ctx->data); 2536 } 2537 2538 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2539 dsa_fdb_dump_cb_t *cb, void *data) 2540 { 2541 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2542 .port = port, 2543 .cb = cb, 2544 .data = data, 2545 }; 2546 u16 fid; 2547 int err; 2548 2549 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2550 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2551 if (err) 2552 return err; 2553 2554 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2555 if (err) 2556 return err; 2557 2558 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2559 } 2560 2561 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2562 dsa_fdb_dump_cb_t *cb, void *data) 2563 { 2564 struct mv88e6xxx_chip *chip = ds->priv; 2565 int err; 2566 2567 mv88e6xxx_reg_lock(chip); 2568 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2569 mv88e6xxx_reg_unlock(chip); 2570 2571 return err; 2572 } 2573 2574 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2575 struct dsa_bridge bridge) 2576 { 2577 struct dsa_switch *ds = chip->ds; 2578 struct dsa_switch_tree *dst = ds->dst; 2579 struct dsa_port *dp; 2580 int err; 2581 2582 list_for_each_entry(dp, &dst->ports, list) { 2583 if (dsa_port_offloads_bridge(dp, &bridge)) { 2584 if (dp->ds == ds) { 2585 /* This is a local bridge group member, 2586 * remap its Port VLAN Map. 2587 */ 2588 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2589 if (err) 2590 return err; 2591 } else { 2592 /* This is an external bridge group member, 2593 * remap its cross-chip Port VLAN Table entry. 2594 */ 2595 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2596 dp->index); 2597 if (err) 2598 return err; 2599 } 2600 } 2601 } 2602 2603 return 0; 2604 } 2605 2606 /* Treat the software bridge as a virtual single-port switch behind the 2607 * CPU and map in the PVT. First dst->last_switch elements are taken by 2608 * physical switches, so start from beyond that range. 2609 */ 2610 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2611 unsigned int bridge_num) 2612 { 2613 u8 dev = bridge_num + ds->dst->last_switch; 2614 struct mv88e6xxx_chip *chip = ds->priv; 2615 2616 return mv88e6xxx_pvt_map(chip, dev, 0); 2617 } 2618 2619 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2620 struct dsa_bridge bridge, 2621 bool *tx_fwd_offload, 2622 struct netlink_ext_ack *extack) 2623 { 2624 struct mv88e6xxx_chip *chip = ds->priv; 2625 int err; 2626 2627 mv88e6xxx_reg_lock(chip); 2628 2629 err = mv88e6xxx_bridge_map(chip, bridge); 2630 if (err) 2631 goto unlock; 2632 2633 err = mv88e6xxx_port_set_map_da(chip, port, true); 2634 if (err) 2635 goto unlock; 2636 2637 err = mv88e6xxx_port_commit_pvid(chip, port); 2638 if (err) 2639 goto unlock; 2640 2641 if (mv88e6xxx_has_pvt(chip)) { 2642 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2643 if (err) 2644 goto unlock; 2645 2646 *tx_fwd_offload = true; 2647 } 2648 2649 unlock: 2650 mv88e6xxx_reg_unlock(chip); 2651 2652 return err; 2653 } 2654 2655 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2656 struct dsa_bridge bridge) 2657 { 2658 struct mv88e6xxx_chip *chip = ds->priv; 2659 int err; 2660 2661 mv88e6xxx_reg_lock(chip); 2662 2663 if (bridge.tx_fwd_offload && 2664 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2665 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2666 2667 if (mv88e6xxx_bridge_map(chip, bridge) || 2668 mv88e6xxx_port_vlan_map(chip, port)) 2669 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2670 2671 err = mv88e6xxx_port_set_map_da(chip, port, false); 2672 if (err) 2673 dev_err(ds->dev, 2674 "port %d failed to restore map-DA: %pe\n", 2675 port, ERR_PTR(err)); 2676 2677 err = mv88e6xxx_port_commit_pvid(chip, port); 2678 if (err) 2679 dev_err(ds->dev, 2680 "port %d failed to restore standalone pvid: %pe\n", 2681 port, ERR_PTR(err)); 2682 2683 mv88e6xxx_reg_unlock(chip); 2684 } 2685 2686 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2687 int tree_index, int sw_index, 2688 int port, struct dsa_bridge bridge, 2689 struct netlink_ext_ack *extack) 2690 { 2691 struct mv88e6xxx_chip *chip = ds->priv; 2692 int err; 2693 2694 if (tree_index != ds->dst->index) 2695 return 0; 2696 2697 mv88e6xxx_reg_lock(chip); 2698 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2699 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2700 mv88e6xxx_reg_unlock(chip); 2701 2702 return err; 2703 } 2704 2705 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2706 int tree_index, int sw_index, 2707 int port, struct dsa_bridge bridge) 2708 { 2709 struct mv88e6xxx_chip *chip = ds->priv; 2710 2711 if (tree_index != ds->dst->index) 2712 return; 2713 2714 mv88e6xxx_reg_lock(chip); 2715 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2716 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2717 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2718 mv88e6xxx_reg_unlock(chip); 2719 } 2720 2721 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2722 { 2723 if (chip->info->ops->reset) 2724 return chip->info->ops->reset(chip); 2725 2726 return 0; 2727 } 2728 2729 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2730 { 2731 struct gpio_desc *gpiod = chip->reset; 2732 2733 /* If there is a GPIO connected to the reset pin, toggle it */ 2734 if (gpiod) { 2735 gpiod_set_value_cansleep(gpiod, 1); 2736 usleep_range(10000, 20000); 2737 gpiod_set_value_cansleep(gpiod, 0); 2738 usleep_range(10000, 20000); 2739 2740 mv88e6xxx_g1_wait_eeprom_done(chip); 2741 } 2742 } 2743 2744 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2745 { 2746 int i, err; 2747 2748 /* Set all ports to the Disabled state */ 2749 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2750 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2751 if (err) 2752 return err; 2753 } 2754 2755 /* Wait for transmit queues to drain, 2756 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2757 */ 2758 usleep_range(2000, 4000); 2759 2760 return 0; 2761 } 2762 2763 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2764 { 2765 int err; 2766 2767 err = mv88e6xxx_disable_ports(chip); 2768 if (err) 2769 return err; 2770 2771 mv88e6xxx_hardware_reset(chip); 2772 2773 return mv88e6xxx_software_reset(chip); 2774 } 2775 2776 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2777 enum mv88e6xxx_frame_mode frame, 2778 enum mv88e6xxx_egress_mode egress, u16 etype) 2779 { 2780 int err; 2781 2782 if (!chip->info->ops->port_set_frame_mode) 2783 return -EOPNOTSUPP; 2784 2785 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2786 if (err) 2787 return err; 2788 2789 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2790 if (err) 2791 return err; 2792 2793 if (chip->info->ops->port_set_ether_type) 2794 return chip->info->ops->port_set_ether_type(chip, port, etype); 2795 2796 return 0; 2797 } 2798 2799 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2800 { 2801 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2802 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2803 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2804 } 2805 2806 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2807 { 2808 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2809 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2810 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2811 } 2812 2813 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2814 { 2815 return mv88e6xxx_set_port_mode(chip, port, 2816 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2817 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2818 ETH_P_EDSA); 2819 } 2820 2821 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2822 { 2823 if (dsa_is_dsa_port(chip->ds, port)) 2824 return mv88e6xxx_set_port_mode_dsa(chip, port); 2825 2826 if (dsa_is_user_port(chip->ds, port)) 2827 return mv88e6xxx_set_port_mode_normal(chip, port); 2828 2829 /* Setup CPU port mode depending on its supported tag format */ 2830 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2831 return mv88e6xxx_set_port_mode_dsa(chip, port); 2832 2833 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2834 return mv88e6xxx_set_port_mode_edsa(chip, port); 2835 2836 return -EINVAL; 2837 } 2838 2839 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2840 { 2841 bool message = dsa_is_dsa_port(chip->ds, port); 2842 2843 return mv88e6xxx_port_set_message_port(chip, port, message); 2844 } 2845 2846 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2847 { 2848 int err; 2849 2850 if (chip->info->ops->port_set_ucast_flood) { 2851 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2852 if (err) 2853 return err; 2854 } 2855 if (chip->info->ops->port_set_mcast_flood) { 2856 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2857 if (err) 2858 return err; 2859 } 2860 2861 return 0; 2862 } 2863 2864 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2865 { 2866 struct mv88e6xxx_port *mvp = dev_id; 2867 struct mv88e6xxx_chip *chip = mvp->chip; 2868 irqreturn_t ret = IRQ_NONE; 2869 int port = mvp->port; 2870 int lane; 2871 2872 mv88e6xxx_reg_lock(chip); 2873 lane = mv88e6xxx_serdes_get_lane(chip, port); 2874 if (lane >= 0) 2875 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2876 mv88e6xxx_reg_unlock(chip); 2877 2878 return ret; 2879 } 2880 2881 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2882 int lane) 2883 { 2884 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2885 unsigned int irq; 2886 int err; 2887 2888 /* Nothing to request if this SERDES port has no IRQ */ 2889 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2890 if (!irq) 2891 return 0; 2892 2893 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2894 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2895 2896 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2897 mv88e6xxx_reg_unlock(chip); 2898 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2899 IRQF_ONESHOT, dev_id->serdes_irq_name, 2900 dev_id); 2901 mv88e6xxx_reg_lock(chip); 2902 if (err) 2903 return err; 2904 2905 dev_id->serdes_irq = irq; 2906 2907 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2908 } 2909 2910 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2911 int lane) 2912 { 2913 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2914 unsigned int irq = dev_id->serdes_irq; 2915 int err; 2916 2917 /* Nothing to free if no IRQ has been requested */ 2918 if (!irq) 2919 return 0; 2920 2921 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2922 2923 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2924 mv88e6xxx_reg_unlock(chip); 2925 free_irq(irq, dev_id); 2926 mv88e6xxx_reg_lock(chip); 2927 2928 dev_id->serdes_irq = 0; 2929 2930 return err; 2931 } 2932 2933 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2934 bool on) 2935 { 2936 int lane; 2937 int err; 2938 2939 lane = mv88e6xxx_serdes_get_lane(chip, port); 2940 if (lane < 0) 2941 return 0; 2942 2943 if (on) { 2944 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2945 if (err) 2946 return err; 2947 2948 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2949 } else { 2950 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2951 if (err) 2952 return err; 2953 2954 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2955 } 2956 2957 return err; 2958 } 2959 2960 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2961 enum mv88e6xxx_egress_direction direction, 2962 int port) 2963 { 2964 int err; 2965 2966 if (!chip->info->ops->set_egress_port) 2967 return -EOPNOTSUPP; 2968 2969 err = chip->info->ops->set_egress_port(chip, direction, port); 2970 if (err) 2971 return err; 2972 2973 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2974 chip->ingress_dest_port = port; 2975 else 2976 chip->egress_dest_port = port; 2977 2978 return 0; 2979 } 2980 2981 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2982 { 2983 struct dsa_switch *ds = chip->ds; 2984 int upstream_port; 2985 int err; 2986 2987 upstream_port = dsa_upstream_port(ds, port); 2988 if (chip->info->ops->port_set_upstream_port) { 2989 err = chip->info->ops->port_set_upstream_port(chip, port, 2990 upstream_port); 2991 if (err) 2992 return err; 2993 } 2994 2995 if (port == upstream_port) { 2996 if (chip->info->ops->set_cpu_port) { 2997 err = chip->info->ops->set_cpu_port(chip, 2998 upstream_port); 2999 if (err) 3000 return err; 3001 } 3002 3003 err = mv88e6xxx_set_egress_port(chip, 3004 MV88E6XXX_EGRESS_DIR_INGRESS, 3005 upstream_port); 3006 if (err && err != -EOPNOTSUPP) 3007 return err; 3008 3009 err = mv88e6xxx_set_egress_port(chip, 3010 MV88E6XXX_EGRESS_DIR_EGRESS, 3011 upstream_port); 3012 if (err && err != -EOPNOTSUPP) 3013 return err; 3014 } 3015 3016 return 0; 3017 } 3018 3019 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3020 { 3021 struct device_node *phy_handle = NULL; 3022 struct dsa_switch *ds = chip->ds; 3023 struct dsa_port *dp; 3024 int tx_amp; 3025 int err; 3026 u16 reg; 3027 3028 chip->ports[port].chip = chip; 3029 chip->ports[port].port = port; 3030 3031 /* MAC Forcing register: don't force link, speed, duplex or flow control 3032 * state to any particular values on physical ports, but force the CPU 3033 * port and all DSA ports to their maximum bandwidth and full duplex. 3034 */ 3035 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 3036 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3037 SPEED_MAX, DUPLEX_FULL, 3038 PAUSE_OFF, 3039 PHY_INTERFACE_MODE_NA); 3040 else 3041 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3042 SPEED_UNFORCED, DUPLEX_UNFORCED, 3043 PAUSE_ON, 3044 PHY_INTERFACE_MODE_NA); 3045 if (err) 3046 return err; 3047 3048 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3049 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3050 * tunneling, determine priority by looking at 802.1p and IP 3051 * priority fields (IP prio has precedence), and set STP state 3052 * to Forwarding. 3053 * 3054 * If this is the CPU link, use DSA or EDSA tagging depending 3055 * on which tagging mode was configured. 3056 * 3057 * If this is a link to another switch, use DSA tagging mode. 3058 * 3059 * If this is the upstream port for this switch, enable 3060 * forwarding of unknown unicasts and multicasts. 3061 */ 3062 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 3063 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3064 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3065 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3066 if (err) 3067 return err; 3068 3069 err = mv88e6xxx_setup_port_mode(chip, port); 3070 if (err) 3071 return err; 3072 3073 err = mv88e6xxx_setup_egress_floods(chip, port); 3074 if (err) 3075 return err; 3076 3077 /* Port Control 2: don't force a good FCS, set the MTU size to 3078 * 10222 bytes, disable 802.1q tags checking, don't discard 3079 * tagged or untagged frames on this port, skip destination 3080 * address lookup on user ports, disable ARP mirroring and don't 3081 * send a copy of all transmitted/received frames on this port 3082 * to the CPU. 3083 */ 3084 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3085 if (err) 3086 return err; 3087 3088 err = mv88e6xxx_setup_upstream_port(chip, port); 3089 if (err) 3090 return err; 3091 3092 /* On chips that support it, set all downstream DSA ports' 3093 * VLAN policy to TRAP. In combination with loading 3094 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3095 * provides a better isolation barrier between standalone 3096 * ports, as the ATU is bypassed on any intermediate switches 3097 * between the incoming port and the CPU. 3098 */ 3099 if (dsa_is_downstream_port(ds, port) && 3100 chip->info->ops->port_set_policy) { 3101 err = chip->info->ops->port_set_policy(chip, port, 3102 MV88E6XXX_POLICY_MAPPING_VTU, 3103 MV88E6XXX_POLICY_ACTION_TRAP); 3104 if (err) 3105 return err; 3106 } 3107 3108 /* User ports start out in standalone mode and 802.1Q is 3109 * therefore disabled. On DSA ports, all valid VIDs are always 3110 * loaded in the VTU - therefore, enable 802.1Q in order to take 3111 * advantage of VLAN policy on chips that supports it. 3112 */ 3113 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3114 dsa_is_user_port(ds, port) ? 3115 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3116 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3117 if (err) 3118 return err; 3119 3120 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3121 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3122 * the first free FID. This will be used as the private PVID for 3123 * unbridged ports. Shared (DSA and CPU) ports must also be 3124 * members of this VID, in order to trap all frames assigned to 3125 * it to the CPU. 3126 */ 3127 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3128 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3129 false); 3130 if (err) 3131 return err; 3132 3133 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3134 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3135 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3136 * as the private PVID on ports under a VLAN-unaware bridge. 3137 * Shared (DSA and CPU) ports must also be members of it, to translate 3138 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3139 * relying on their port default FID. 3140 */ 3141 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3142 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3143 false); 3144 if (err) 3145 return err; 3146 3147 if (chip->info->ops->port_set_jumbo_size) { 3148 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3149 if (err) 3150 return err; 3151 } 3152 3153 /* Port Association Vector: disable automatic address learning 3154 * on all user ports since they start out in standalone 3155 * mode. When joining a bridge, learning will be configured to 3156 * match the bridge port settings. Enable learning on all 3157 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3158 * learning process. 3159 * 3160 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3161 * and RefreshLocked. I.e. setup standard automatic learning. 3162 */ 3163 if (dsa_is_user_port(ds, port)) 3164 reg = 0; 3165 else 3166 reg = 1 << port; 3167 3168 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3169 reg); 3170 if (err) 3171 return err; 3172 3173 /* Egress rate control 2: disable egress rate control. */ 3174 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3175 0x0000); 3176 if (err) 3177 return err; 3178 3179 if (chip->info->ops->port_pause_limit) { 3180 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3181 if (err) 3182 return err; 3183 } 3184 3185 if (chip->info->ops->port_disable_learn_limit) { 3186 err = chip->info->ops->port_disable_learn_limit(chip, port); 3187 if (err) 3188 return err; 3189 } 3190 3191 if (chip->info->ops->port_disable_pri_override) { 3192 err = chip->info->ops->port_disable_pri_override(chip, port); 3193 if (err) 3194 return err; 3195 } 3196 3197 if (chip->info->ops->port_tag_remap) { 3198 err = chip->info->ops->port_tag_remap(chip, port); 3199 if (err) 3200 return err; 3201 } 3202 3203 if (chip->info->ops->port_egress_rate_limiting) { 3204 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3205 if (err) 3206 return err; 3207 } 3208 3209 if (chip->info->ops->port_setup_message_port) { 3210 err = chip->info->ops->port_setup_message_port(chip, port); 3211 if (err) 3212 return err; 3213 } 3214 3215 if (chip->info->ops->serdes_set_tx_amplitude) { 3216 dp = dsa_to_port(ds, port); 3217 if (dp) 3218 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3219 3220 if (phy_handle && !of_property_read_u32(phy_handle, 3221 "tx-p2p-microvolt", 3222 &tx_amp)) 3223 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3224 port, tx_amp); 3225 if (phy_handle) { 3226 of_node_put(phy_handle); 3227 if (err) 3228 return err; 3229 } 3230 } 3231 3232 /* Port based VLAN map: give each port the same default address 3233 * database, and allow bidirectional communication between the 3234 * CPU and DSA port(s), and the other ports. 3235 */ 3236 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3237 if (err) 3238 return err; 3239 3240 err = mv88e6xxx_port_vlan_map(chip, port); 3241 if (err) 3242 return err; 3243 3244 /* Default VLAN ID and priority: don't set a default VLAN 3245 * ID, and set the default packet priority to zero. 3246 */ 3247 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3248 } 3249 3250 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3251 { 3252 struct mv88e6xxx_chip *chip = ds->priv; 3253 3254 if (chip->info->ops->port_set_jumbo_size) 3255 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3256 else if (chip->info->ops->set_max_frame_size) 3257 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3258 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3259 } 3260 3261 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3262 { 3263 struct mv88e6xxx_chip *chip = ds->priv; 3264 int ret = 0; 3265 3266 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3267 new_mtu += EDSA_HLEN; 3268 3269 mv88e6xxx_reg_lock(chip); 3270 if (chip->info->ops->port_set_jumbo_size) 3271 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3272 else if (chip->info->ops->set_max_frame_size) 3273 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3274 else 3275 if (new_mtu > 1522) 3276 ret = -EINVAL; 3277 mv88e6xxx_reg_unlock(chip); 3278 3279 return ret; 3280 } 3281 3282 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3283 struct phy_device *phydev) 3284 { 3285 struct mv88e6xxx_chip *chip = ds->priv; 3286 int err; 3287 3288 mv88e6xxx_reg_lock(chip); 3289 err = mv88e6xxx_serdes_power(chip, port, true); 3290 mv88e6xxx_reg_unlock(chip); 3291 3292 return err; 3293 } 3294 3295 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3296 { 3297 struct mv88e6xxx_chip *chip = ds->priv; 3298 3299 mv88e6xxx_reg_lock(chip); 3300 if (mv88e6xxx_serdes_power(chip, port, false)) 3301 dev_err(chip->dev, "failed to power off SERDES\n"); 3302 mv88e6xxx_reg_unlock(chip); 3303 } 3304 3305 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3306 unsigned int ageing_time) 3307 { 3308 struct mv88e6xxx_chip *chip = ds->priv; 3309 int err; 3310 3311 mv88e6xxx_reg_lock(chip); 3312 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3313 mv88e6xxx_reg_unlock(chip); 3314 3315 return err; 3316 } 3317 3318 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3319 { 3320 int err; 3321 3322 /* Initialize the statistics unit */ 3323 if (chip->info->ops->stats_set_histogram) { 3324 err = chip->info->ops->stats_set_histogram(chip); 3325 if (err) 3326 return err; 3327 } 3328 3329 return mv88e6xxx_g1_stats_clear(chip); 3330 } 3331 3332 /* Check if the errata has already been applied. */ 3333 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3334 { 3335 int port; 3336 int err; 3337 u16 val; 3338 3339 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3340 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3341 if (err) { 3342 dev_err(chip->dev, 3343 "Error reading hidden register: %d\n", err); 3344 return false; 3345 } 3346 if (val != 0x01c0) 3347 return false; 3348 } 3349 3350 return true; 3351 } 3352 3353 /* The 6390 copper ports have an errata which require poking magic 3354 * values into undocumented hidden registers and then performing a 3355 * software reset. 3356 */ 3357 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3358 { 3359 int port; 3360 int err; 3361 3362 if (mv88e6390_setup_errata_applied(chip)) 3363 return 0; 3364 3365 /* Set the ports into blocking mode */ 3366 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3367 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3368 if (err) 3369 return err; 3370 } 3371 3372 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3373 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3374 if (err) 3375 return err; 3376 } 3377 3378 return mv88e6xxx_software_reset(chip); 3379 } 3380 3381 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3382 { 3383 mv88e6xxx_teardown_devlink_params(ds); 3384 dsa_devlink_resources_unregister(ds); 3385 mv88e6xxx_teardown_devlink_regions_global(ds); 3386 } 3387 3388 static int mv88e6xxx_setup(struct dsa_switch *ds) 3389 { 3390 struct mv88e6xxx_chip *chip = ds->priv; 3391 u8 cmode; 3392 int err; 3393 int i; 3394 3395 chip->ds = ds; 3396 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3397 3398 /* Since virtual bridges are mapped in the PVT, the number we support 3399 * depends on the physical switch topology. We need to let DSA figure 3400 * that out and therefore we cannot set this at dsa_register_switch() 3401 * time. 3402 */ 3403 if (mv88e6xxx_has_pvt(chip)) 3404 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3405 ds->dst->last_switch - 1; 3406 3407 mv88e6xxx_reg_lock(chip); 3408 3409 if (chip->info->ops->setup_errata) { 3410 err = chip->info->ops->setup_errata(chip); 3411 if (err) 3412 goto unlock; 3413 } 3414 3415 /* Cache the cmode of each port. */ 3416 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3417 if (chip->info->ops->port_get_cmode) { 3418 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3419 if (err) 3420 goto unlock; 3421 3422 chip->ports[i].cmode = cmode; 3423 } 3424 } 3425 3426 err = mv88e6xxx_vtu_setup(chip); 3427 if (err) 3428 goto unlock; 3429 3430 /* Setup Switch Port Registers */ 3431 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3432 if (dsa_is_unused_port(ds, i)) 3433 continue; 3434 3435 /* Prevent the use of an invalid port. */ 3436 if (mv88e6xxx_is_invalid_port(chip, i)) { 3437 dev_err(chip->dev, "port %d is invalid\n", i); 3438 err = -EINVAL; 3439 goto unlock; 3440 } 3441 3442 err = mv88e6xxx_setup_port(chip, i); 3443 if (err) 3444 goto unlock; 3445 } 3446 3447 err = mv88e6xxx_irl_setup(chip); 3448 if (err) 3449 goto unlock; 3450 3451 err = mv88e6xxx_mac_setup(chip); 3452 if (err) 3453 goto unlock; 3454 3455 err = mv88e6xxx_phy_setup(chip); 3456 if (err) 3457 goto unlock; 3458 3459 err = mv88e6xxx_pvt_setup(chip); 3460 if (err) 3461 goto unlock; 3462 3463 err = mv88e6xxx_atu_setup(chip); 3464 if (err) 3465 goto unlock; 3466 3467 err = mv88e6xxx_broadcast_setup(chip, 0); 3468 if (err) 3469 goto unlock; 3470 3471 err = mv88e6xxx_pot_setup(chip); 3472 if (err) 3473 goto unlock; 3474 3475 err = mv88e6xxx_rmu_setup(chip); 3476 if (err) 3477 goto unlock; 3478 3479 err = mv88e6xxx_rsvd2cpu_setup(chip); 3480 if (err) 3481 goto unlock; 3482 3483 err = mv88e6xxx_trunk_setup(chip); 3484 if (err) 3485 goto unlock; 3486 3487 err = mv88e6xxx_devmap_setup(chip); 3488 if (err) 3489 goto unlock; 3490 3491 err = mv88e6xxx_pri_setup(chip); 3492 if (err) 3493 goto unlock; 3494 3495 /* Setup PTP Hardware Clock and timestamping */ 3496 if (chip->info->ptp_support) { 3497 err = mv88e6xxx_ptp_setup(chip); 3498 if (err) 3499 goto unlock; 3500 3501 err = mv88e6xxx_hwtstamp_setup(chip); 3502 if (err) 3503 goto unlock; 3504 } 3505 3506 err = mv88e6xxx_stats_setup(chip); 3507 if (err) 3508 goto unlock; 3509 3510 unlock: 3511 mv88e6xxx_reg_unlock(chip); 3512 3513 if (err) 3514 return err; 3515 3516 /* Have to be called without holding the register lock, since 3517 * they take the devlink lock, and we later take the locks in 3518 * the reverse order when getting/setting parameters or 3519 * resource occupancy. 3520 */ 3521 err = mv88e6xxx_setup_devlink_resources(ds); 3522 if (err) 3523 return err; 3524 3525 err = mv88e6xxx_setup_devlink_params(ds); 3526 if (err) 3527 goto out_resources; 3528 3529 err = mv88e6xxx_setup_devlink_regions_global(ds); 3530 if (err) 3531 goto out_params; 3532 3533 return 0; 3534 3535 out_params: 3536 mv88e6xxx_teardown_devlink_params(ds); 3537 out_resources: 3538 dsa_devlink_resources_unregister(ds); 3539 3540 return err; 3541 } 3542 3543 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3544 { 3545 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3546 } 3547 3548 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3549 { 3550 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3551 } 3552 3553 /* prod_id for switch families which do not have a PHY model number */ 3554 static const u16 family_prod_id_table[] = { 3555 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3556 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3557 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3558 }; 3559 3560 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3561 { 3562 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3563 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3564 u16 prod_id; 3565 u16 val; 3566 int err; 3567 3568 if (!chip->info->ops->phy_read) 3569 return -EOPNOTSUPP; 3570 3571 mv88e6xxx_reg_lock(chip); 3572 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3573 mv88e6xxx_reg_unlock(chip); 3574 3575 /* Some internal PHYs don't have a model number. */ 3576 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3577 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3578 prod_id = family_prod_id_table[chip->info->family]; 3579 if (prod_id) 3580 val |= prod_id >> 4; 3581 } 3582 3583 return err ? err : val; 3584 } 3585 3586 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3587 { 3588 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3589 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3590 int err; 3591 3592 if (!chip->info->ops->phy_write) 3593 return -EOPNOTSUPP; 3594 3595 mv88e6xxx_reg_lock(chip); 3596 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3597 mv88e6xxx_reg_unlock(chip); 3598 3599 return err; 3600 } 3601 3602 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3603 struct device_node *np, 3604 bool external) 3605 { 3606 static int index; 3607 struct mv88e6xxx_mdio_bus *mdio_bus; 3608 struct mii_bus *bus; 3609 int err; 3610 3611 if (external) { 3612 mv88e6xxx_reg_lock(chip); 3613 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3614 mv88e6xxx_reg_unlock(chip); 3615 3616 if (err) 3617 return err; 3618 } 3619 3620 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3621 if (!bus) 3622 return -ENOMEM; 3623 3624 mdio_bus = bus->priv; 3625 mdio_bus->bus = bus; 3626 mdio_bus->chip = chip; 3627 INIT_LIST_HEAD(&mdio_bus->list); 3628 mdio_bus->external = external; 3629 3630 if (np) { 3631 bus->name = np->full_name; 3632 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3633 } else { 3634 bus->name = "mv88e6xxx SMI"; 3635 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3636 } 3637 3638 bus->read = mv88e6xxx_mdio_read; 3639 bus->write = mv88e6xxx_mdio_write; 3640 bus->parent = chip->dev; 3641 3642 if (!external) { 3643 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3644 if (err) 3645 goto out; 3646 } 3647 3648 err = of_mdiobus_register(bus, np); 3649 if (err) { 3650 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3651 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3652 goto out; 3653 } 3654 3655 if (external) 3656 list_add_tail(&mdio_bus->list, &chip->mdios); 3657 else 3658 list_add(&mdio_bus->list, &chip->mdios); 3659 3660 return 0; 3661 3662 out: 3663 mdiobus_free(bus); 3664 return err; 3665 } 3666 3667 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3668 3669 { 3670 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3671 struct mii_bus *bus; 3672 3673 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3674 bus = mdio_bus->bus; 3675 3676 if (!mdio_bus->external) 3677 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3678 3679 mdiobus_unregister(bus); 3680 mdiobus_free(bus); 3681 } 3682 } 3683 3684 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3685 struct device_node *np) 3686 { 3687 struct device_node *child; 3688 int err; 3689 3690 /* Always register one mdio bus for the internal/default mdio 3691 * bus. This maybe represented in the device tree, but is 3692 * optional. 3693 */ 3694 child = of_get_child_by_name(np, "mdio"); 3695 err = mv88e6xxx_mdio_register(chip, child, false); 3696 if (err) 3697 return err; 3698 3699 /* Walk the device tree, and see if there are any other nodes 3700 * which say they are compatible with the external mdio 3701 * bus. 3702 */ 3703 for_each_available_child_of_node(np, child) { 3704 if (of_device_is_compatible( 3705 child, "marvell,mv88e6xxx-mdio-external")) { 3706 err = mv88e6xxx_mdio_register(chip, child, true); 3707 if (err) { 3708 mv88e6xxx_mdios_unregister(chip); 3709 of_node_put(child); 3710 return err; 3711 } 3712 } 3713 } 3714 3715 return 0; 3716 } 3717 3718 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3719 { 3720 struct mv88e6xxx_chip *chip = ds->priv; 3721 3722 return chip->eeprom_len; 3723 } 3724 3725 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3726 struct ethtool_eeprom *eeprom, u8 *data) 3727 { 3728 struct mv88e6xxx_chip *chip = ds->priv; 3729 int err; 3730 3731 if (!chip->info->ops->get_eeprom) 3732 return -EOPNOTSUPP; 3733 3734 mv88e6xxx_reg_lock(chip); 3735 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3736 mv88e6xxx_reg_unlock(chip); 3737 3738 if (err) 3739 return err; 3740 3741 eeprom->magic = 0xc3ec4951; 3742 3743 return 0; 3744 } 3745 3746 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3747 struct ethtool_eeprom *eeprom, u8 *data) 3748 { 3749 struct mv88e6xxx_chip *chip = ds->priv; 3750 int err; 3751 3752 if (!chip->info->ops->set_eeprom) 3753 return -EOPNOTSUPP; 3754 3755 if (eeprom->magic != 0xc3ec4951) 3756 return -EINVAL; 3757 3758 mv88e6xxx_reg_lock(chip); 3759 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3760 mv88e6xxx_reg_unlock(chip); 3761 3762 return err; 3763 } 3764 3765 static const struct mv88e6xxx_ops mv88e6085_ops = { 3766 /* MV88E6XXX_FAMILY_6097 */ 3767 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3768 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3769 .irl_init_all = mv88e6352_g2_irl_init_all, 3770 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3771 .phy_read = mv88e6185_phy_ppu_read, 3772 .phy_write = mv88e6185_phy_ppu_write, 3773 .port_set_link = mv88e6xxx_port_set_link, 3774 .port_sync_link = mv88e6xxx_port_sync_link, 3775 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3776 .port_tag_remap = mv88e6095_port_tag_remap, 3777 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3778 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3779 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3780 .port_set_ether_type = mv88e6351_port_set_ether_type, 3781 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3782 .port_pause_limit = mv88e6097_port_pause_limit, 3783 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3784 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3785 .port_get_cmode = mv88e6185_port_get_cmode, 3786 .port_setup_message_port = mv88e6xxx_setup_message_port, 3787 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3788 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3789 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3790 .stats_get_strings = mv88e6095_stats_get_strings, 3791 .stats_get_stats = mv88e6095_stats_get_stats, 3792 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3793 .set_egress_port = mv88e6095_g1_set_egress_port, 3794 .watchdog_ops = &mv88e6097_watchdog_ops, 3795 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3796 .pot_clear = mv88e6xxx_g2_pot_clear, 3797 .ppu_enable = mv88e6185_g1_ppu_enable, 3798 .ppu_disable = mv88e6185_g1_ppu_disable, 3799 .reset = mv88e6185_g1_reset, 3800 .rmu_disable = mv88e6085_g1_rmu_disable, 3801 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3802 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3803 .phylink_get_caps = mv88e6185_phylink_get_caps, 3804 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3805 }; 3806 3807 static const struct mv88e6xxx_ops mv88e6095_ops = { 3808 /* MV88E6XXX_FAMILY_6095 */ 3809 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3810 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3811 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3812 .phy_read = mv88e6185_phy_ppu_read, 3813 .phy_write = mv88e6185_phy_ppu_write, 3814 .port_set_link = mv88e6xxx_port_set_link, 3815 .port_sync_link = mv88e6185_port_sync_link, 3816 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3817 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3818 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3819 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3820 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3821 .port_get_cmode = mv88e6185_port_get_cmode, 3822 .port_setup_message_port = mv88e6xxx_setup_message_port, 3823 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3824 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3825 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3826 .stats_get_strings = mv88e6095_stats_get_strings, 3827 .stats_get_stats = mv88e6095_stats_get_stats, 3828 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3829 .serdes_power = mv88e6185_serdes_power, 3830 .serdes_get_lane = mv88e6185_serdes_get_lane, 3831 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3832 .ppu_enable = mv88e6185_g1_ppu_enable, 3833 .ppu_disable = mv88e6185_g1_ppu_disable, 3834 .reset = mv88e6185_g1_reset, 3835 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3836 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3837 .phylink_get_caps = mv88e6095_phylink_get_caps, 3838 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3839 }; 3840 3841 static const struct mv88e6xxx_ops mv88e6097_ops = { 3842 /* MV88E6XXX_FAMILY_6097 */ 3843 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3844 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3845 .irl_init_all = mv88e6352_g2_irl_init_all, 3846 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3847 .phy_read = mv88e6xxx_g2_smi_phy_read, 3848 .phy_write = mv88e6xxx_g2_smi_phy_write, 3849 .port_set_link = mv88e6xxx_port_set_link, 3850 .port_sync_link = mv88e6185_port_sync_link, 3851 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3852 .port_tag_remap = mv88e6095_port_tag_remap, 3853 .port_set_policy = mv88e6352_port_set_policy, 3854 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3855 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3856 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3857 .port_set_ether_type = mv88e6351_port_set_ether_type, 3858 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3859 .port_pause_limit = mv88e6097_port_pause_limit, 3860 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3861 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3862 .port_get_cmode = mv88e6185_port_get_cmode, 3863 .port_setup_message_port = mv88e6xxx_setup_message_port, 3864 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3865 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3866 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3867 .stats_get_strings = mv88e6095_stats_get_strings, 3868 .stats_get_stats = mv88e6095_stats_get_stats, 3869 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3870 .set_egress_port = mv88e6095_g1_set_egress_port, 3871 .watchdog_ops = &mv88e6097_watchdog_ops, 3872 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3873 .serdes_power = mv88e6185_serdes_power, 3874 .serdes_get_lane = mv88e6185_serdes_get_lane, 3875 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3876 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3877 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3878 .serdes_irq_status = mv88e6097_serdes_irq_status, 3879 .pot_clear = mv88e6xxx_g2_pot_clear, 3880 .reset = mv88e6352_g1_reset, 3881 .rmu_disable = mv88e6085_g1_rmu_disable, 3882 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3883 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3884 .phylink_get_caps = mv88e6095_phylink_get_caps, 3885 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3886 }; 3887 3888 static const struct mv88e6xxx_ops mv88e6123_ops = { 3889 /* MV88E6XXX_FAMILY_6165 */ 3890 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3891 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3892 .irl_init_all = mv88e6352_g2_irl_init_all, 3893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3894 .phy_read = mv88e6xxx_g2_smi_phy_read, 3895 .phy_write = mv88e6xxx_g2_smi_phy_write, 3896 .port_set_link = mv88e6xxx_port_set_link, 3897 .port_sync_link = mv88e6xxx_port_sync_link, 3898 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3899 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3900 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3901 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3902 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3903 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3904 .port_get_cmode = mv88e6185_port_get_cmode, 3905 .port_setup_message_port = mv88e6xxx_setup_message_port, 3906 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3907 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3908 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3909 .stats_get_strings = mv88e6095_stats_get_strings, 3910 .stats_get_stats = mv88e6095_stats_get_stats, 3911 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3912 .set_egress_port = mv88e6095_g1_set_egress_port, 3913 .watchdog_ops = &mv88e6097_watchdog_ops, 3914 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3915 .pot_clear = mv88e6xxx_g2_pot_clear, 3916 .reset = mv88e6352_g1_reset, 3917 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3918 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3919 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3920 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3921 .phylink_get_caps = mv88e6185_phylink_get_caps, 3922 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3923 }; 3924 3925 static const struct mv88e6xxx_ops mv88e6131_ops = { 3926 /* MV88E6XXX_FAMILY_6185 */ 3927 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3928 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3929 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3930 .phy_read = mv88e6185_phy_ppu_read, 3931 .phy_write = mv88e6185_phy_ppu_write, 3932 .port_set_link = mv88e6xxx_port_set_link, 3933 .port_sync_link = mv88e6xxx_port_sync_link, 3934 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3935 .port_tag_remap = mv88e6095_port_tag_remap, 3936 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3937 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3938 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3939 .port_set_ether_type = mv88e6351_port_set_ether_type, 3940 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3941 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3942 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3943 .port_pause_limit = mv88e6097_port_pause_limit, 3944 .port_set_pause = mv88e6185_port_set_pause, 3945 .port_get_cmode = mv88e6185_port_get_cmode, 3946 .port_setup_message_port = mv88e6xxx_setup_message_port, 3947 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3948 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3949 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3950 .stats_get_strings = mv88e6095_stats_get_strings, 3951 .stats_get_stats = mv88e6095_stats_get_stats, 3952 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3953 .set_egress_port = mv88e6095_g1_set_egress_port, 3954 .watchdog_ops = &mv88e6097_watchdog_ops, 3955 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3956 .ppu_enable = mv88e6185_g1_ppu_enable, 3957 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3958 .ppu_disable = mv88e6185_g1_ppu_disable, 3959 .reset = mv88e6185_g1_reset, 3960 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3961 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3962 .phylink_get_caps = mv88e6185_phylink_get_caps, 3963 }; 3964 3965 static const struct mv88e6xxx_ops mv88e6141_ops = { 3966 /* MV88E6XXX_FAMILY_6341 */ 3967 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3968 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3969 .irl_init_all = mv88e6352_g2_irl_init_all, 3970 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3971 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3972 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3973 .phy_read = mv88e6xxx_g2_smi_phy_read, 3974 .phy_write = mv88e6xxx_g2_smi_phy_write, 3975 .port_set_link = mv88e6xxx_port_set_link, 3976 .port_sync_link = mv88e6xxx_port_sync_link, 3977 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3978 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3979 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3980 .port_tag_remap = mv88e6095_port_tag_remap, 3981 .port_set_policy = mv88e6352_port_set_policy, 3982 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3983 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3984 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3985 .port_set_ether_type = mv88e6351_port_set_ether_type, 3986 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3987 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3988 .port_pause_limit = mv88e6097_port_pause_limit, 3989 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3990 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3991 .port_get_cmode = mv88e6352_port_get_cmode, 3992 .port_set_cmode = mv88e6341_port_set_cmode, 3993 .port_setup_message_port = mv88e6xxx_setup_message_port, 3994 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3995 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3996 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3997 .stats_get_strings = mv88e6320_stats_get_strings, 3998 .stats_get_stats = mv88e6390_stats_get_stats, 3999 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4000 .set_egress_port = mv88e6390_g1_set_egress_port, 4001 .watchdog_ops = &mv88e6390_watchdog_ops, 4002 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4003 .pot_clear = mv88e6xxx_g2_pot_clear, 4004 .reset = mv88e6352_g1_reset, 4005 .rmu_disable = mv88e6390_g1_rmu_disable, 4006 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4007 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4008 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4009 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4010 .serdes_power = mv88e6390_serdes_power, 4011 .serdes_get_lane = mv88e6341_serdes_get_lane, 4012 /* Check status register pause & lpa register */ 4013 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4014 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4015 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4016 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4017 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4018 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4019 .serdes_irq_status = mv88e6390_serdes_irq_status, 4020 .gpio_ops = &mv88e6352_gpio_ops, 4021 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4022 .serdes_get_strings = mv88e6390_serdes_get_strings, 4023 .serdes_get_stats = mv88e6390_serdes_get_stats, 4024 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4025 .serdes_get_regs = mv88e6390_serdes_get_regs, 4026 .phylink_get_caps = mv88e6341_phylink_get_caps, 4027 }; 4028 4029 static const struct mv88e6xxx_ops mv88e6161_ops = { 4030 /* MV88E6XXX_FAMILY_6165 */ 4031 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4032 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4033 .irl_init_all = mv88e6352_g2_irl_init_all, 4034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4035 .phy_read = mv88e6xxx_g2_smi_phy_read, 4036 .phy_write = mv88e6xxx_g2_smi_phy_write, 4037 .port_set_link = mv88e6xxx_port_set_link, 4038 .port_sync_link = mv88e6xxx_port_sync_link, 4039 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4040 .port_tag_remap = mv88e6095_port_tag_remap, 4041 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4042 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4043 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4044 .port_set_ether_type = mv88e6351_port_set_ether_type, 4045 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4046 .port_pause_limit = mv88e6097_port_pause_limit, 4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4049 .port_get_cmode = mv88e6185_port_get_cmode, 4050 .port_setup_message_port = mv88e6xxx_setup_message_port, 4051 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4052 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4053 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4054 .stats_get_strings = mv88e6095_stats_get_strings, 4055 .stats_get_stats = mv88e6095_stats_get_stats, 4056 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4057 .set_egress_port = mv88e6095_g1_set_egress_port, 4058 .watchdog_ops = &mv88e6097_watchdog_ops, 4059 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4060 .pot_clear = mv88e6xxx_g2_pot_clear, 4061 .reset = mv88e6352_g1_reset, 4062 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4063 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4064 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4065 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4066 .avb_ops = &mv88e6165_avb_ops, 4067 .ptp_ops = &mv88e6165_ptp_ops, 4068 .phylink_get_caps = mv88e6185_phylink_get_caps, 4069 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4070 }; 4071 4072 static const struct mv88e6xxx_ops mv88e6165_ops = { 4073 /* MV88E6XXX_FAMILY_6165 */ 4074 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4075 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4076 .irl_init_all = mv88e6352_g2_irl_init_all, 4077 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4078 .phy_read = mv88e6165_phy_read, 4079 .phy_write = mv88e6165_phy_write, 4080 .port_set_link = mv88e6xxx_port_set_link, 4081 .port_sync_link = mv88e6xxx_port_sync_link, 4082 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4085 .port_get_cmode = mv88e6185_port_get_cmode, 4086 .port_setup_message_port = mv88e6xxx_setup_message_port, 4087 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4088 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4089 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4090 .stats_get_strings = mv88e6095_stats_get_strings, 4091 .stats_get_stats = mv88e6095_stats_get_stats, 4092 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4093 .set_egress_port = mv88e6095_g1_set_egress_port, 4094 .watchdog_ops = &mv88e6097_watchdog_ops, 4095 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4096 .pot_clear = mv88e6xxx_g2_pot_clear, 4097 .reset = mv88e6352_g1_reset, 4098 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4099 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4100 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4101 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4102 .avb_ops = &mv88e6165_avb_ops, 4103 .ptp_ops = &mv88e6165_ptp_ops, 4104 .phylink_get_caps = mv88e6185_phylink_get_caps, 4105 }; 4106 4107 static const struct mv88e6xxx_ops mv88e6171_ops = { 4108 /* MV88E6XXX_FAMILY_6351 */ 4109 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4110 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4111 .irl_init_all = mv88e6352_g2_irl_init_all, 4112 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4113 .phy_read = mv88e6xxx_g2_smi_phy_read, 4114 .phy_write = mv88e6xxx_g2_smi_phy_write, 4115 .port_set_link = mv88e6xxx_port_set_link, 4116 .port_sync_link = mv88e6xxx_port_sync_link, 4117 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4118 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4119 .port_tag_remap = mv88e6095_port_tag_remap, 4120 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4121 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4122 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4123 .port_set_ether_type = mv88e6351_port_set_ether_type, 4124 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4125 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4126 .port_pause_limit = mv88e6097_port_pause_limit, 4127 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4128 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4129 .port_get_cmode = mv88e6352_port_get_cmode, 4130 .port_setup_message_port = mv88e6xxx_setup_message_port, 4131 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4132 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4133 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4134 .stats_get_strings = mv88e6095_stats_get_strings, 4135 .stats_get_stats = mv88e6095_stats_get_stats, 4136 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4137 .set_egress_port = mv88e6095_g1_set_egress_port, 4138 .watchdog_ops = &mv88e6097_watchdog_ops, 4139 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4140 .pot_clear = mv88e6xxx_g2_pot_clear, 4141 .reset = mv88e6352_g1_reset, 4142 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4143 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4144 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4145 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4146 .phylink_get_caps = mv88e6185_phylink_get_caps, 4147 }; 4148 4149 static const struct mv88e6xxx_ops mv88e6172_ops = { 4150 /* MV88E6XXX_FAMILY_6352 */ 4151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4153 .irl_init_all = mv88e6352_g2_irl_init_all, 4154 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4155 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4156 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4157 .phy_read = mv88e6xxx_g2_smi_phy_read, 4158 .phy_write = mv88e6xxx_g2_smi_phy_write, 4159 .port_set_link = mv88e6xxx_port_set_link, 4160 .port_sync_link = mv88e6xxx_port_sync_link, 4161 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4162 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4163 .port_tag_remap = mv88e6095_port_tag_remap, 4164 .port_set_policy = mv88e6352_port_set_policy, 4165 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4166 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4167 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4168 .port_set_ether_type = mv88e6351_port_set_ether_type, 4169 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4170 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4171 .port_pause_limit = mv88e6097_port_pause_limit, 4172 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4173 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4174 .port_get_cmode = mv88e6352_port_get_cmode, 4175 .port_setup_message_port = mv88e6xxx_setup_message_port, 4176 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4177 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4178 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4179 .stats_get_strings = mv88e6095_stats_get_strings, 4180 .stats_get_stats = mv88e6095_stats_get_stats, 4181 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4182 .set_egress_port = mv88e6095_g1_set_egress_port, 4183 .watchdog_ops = &mv88e6097_watchdog_ops, 4184 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4185 .pot_clear = mv88e6xxx_g2_pot_clear, 4186 .reset = mv88e6352_g1_reset, 4187 .rmu_disable = mv88e6352_g1_rmu_disable, 4188 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4189 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4190 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4191 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4192 .serdes_get_lane = mv88e6352_serdes_get_lane, 4193 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4194 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4195 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4196 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4197 .serdes_power = mv88e6352_serdes_power, 4198 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4199 .serdes_get_regs = mv88e6352_serdes_get_regs, 4200 .gpio_ops = &mv88e6352_gpio_ops, 4201 .phylink_get_caps = mv88e6352_phylink_get_caps, 4202 }; 4203 4204 static const struct mv88e6xxx_ops mv88e6175_ops = { 4205 /* MV88E6XXX_FAMILY_6351 */ 4206 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4207 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4208 .irl_init_all = mv88e6352_g2_irl_init_all, 4209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4210 .phy_read = mv88e6xxx_g2_smi_phy_read, 4211 .phy_write = mv88e6xxx_g2_smi_phy_write, 4212 .port_set_link = mv88e6xxx_port_set_link, 4213 .port_sync_link = mv88e6xxx_port_sync_link, 4214 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4215 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4216 .port_tag_remap = mv88e6095_port_tag_remap, 4217 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4218 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4219 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4220 .port_set_ether_type = mv88e6351_port_set_ether_type, 4221 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4222 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4223 .port_pause_limit = mv88e6097_port_pause_limit, 4224 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4225 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4226 .port_get_cmode = mv88e6352_port_get_cmode, 4227 .port_setup_message_port = mv88e6xxx_setup_message_port, 4228 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4229 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4230 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4231 .stats_get_strings = mv88e6095_stats_get_strings, 4232 .stats_get_stats = mv88e6095_stats_get_stats, 4233 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4234 .set_egress_port = mv88e6095_g1_set_egress_port, 4235 .watchdog_ops = &mv88e6097_watchdog_ops, 4236 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4237 .pot_clear = mv88e6xxx_g2_pot_clear, 4238 .reset = mv88e6352_g1_reset, 4239 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4240 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4241 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4242 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4243 .phylink_get_caps = mv88e6185_phylink_get_caps, 4244 }; 4245 4246 static const struct mv88e6xxx_ops mv88e6176_ops = { 4247 /* MV88E6XXX_FAMILY_6352 */ 4248 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4249 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4250 .irl_init_all = mv88e6352_g2_irl_init_all, 4251 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4252 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4253 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4254 .phy_read = mv88e6xxx_g2_smi_phy_read, 4255 .phy_write = mv88e6xxx_g2_smi_phy_write, 4256 .port_set_link = mv88e6xxx_port_set_link, 4257 .port_sync_link = mv88e6xxx_port_sync_link, 4258 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4259 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4260 .port_tag_remap = mv88e6095_port_tag_remap, 4261 .port_set_policy = mv88e6352_port_set_policy, 4262 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4263 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4264 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4265 .port_set_ether_type = mv88e6351_port_set_ether_type, 4266 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4267 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4268 .port_pause_limit = mv88e6097_port_pause_limit, 4269 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4270 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4271 .port_get_cmode = mv88e6352_port_get_cmode, 4272 .port_setup_message_port = mv88e6xxx_setup_message_port, 4273 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4274 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4275 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4276 .stats_get_strings = mv88e6095_stats_get_strings, 4277 .stats_get_stats = mv88e6095_stats_get_stats, 4278 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4279 .set_egress_port = mv88e6095_g1_set_egress_port, 4280 .watchdog_ops = &mv88e6097_watchdog_ops, 4281 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4282 .pot_clear = mv88e6xxx_g2_pot_clear, 4283 .reset = mv88e6352_g1_reset, 4284 .rmu_disable = mv88e6352_g1_rmu_disable, 4285 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4286 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4287 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4288 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4289 .serdes_get_lane = mv88e6352_serdes_get_lane, 4290 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4291 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4292 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4293 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4294 .serdes_power = mv88e6352_serdes_power, 4295 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4296 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4297 .serdes_irq_status = mv88e6352_serdes_irq_status, 4298 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4299 .serdes_get_regs = mv88e6352_serdes_get_regs, 4300 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4301 .gpio_ops = &mv88e6352_gpio_ops, 4302 .phylink_get_caps = mv88e6352_phylink_get_caps, 4303 }; 4304 4305 static const struct mv88e6xxx_ops mv88e6185_ops = { 4306 /* MV88E6XXX_FAMILY_6185 */ 4307 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4308 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4309 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4310 .phy_read = mv88e6185_phy_ppu_read, 4311 .phy_write = mv88e6185_phy_ppu_write, 4312 .port_set_link = mv88e6xxx_port_set_link, 4313 .port_sync_link = mv88e6185_port_sync_link, 4314 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4315 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4316 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4317 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4318 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4319 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4320 .port_set_pause = mv88e6185_port_set_pause, 4321 .port_get_cmode = mv88e6185_port_get_cmode, 4322 .port_setup_message_port = mv88e6xxx_setup_message_port, 4323 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4324 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4325 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4326 .stats_get_strings = mv88e6095_stats_get_strings, 4327 .stats_get_stats = mv88e6095_stats_get_stats, 4328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4329 .set_egress_port = mv88e6095_g1_set_egress_port, 4330 .watchdog_ops = &mv88e6097_watchdog_ops, 4331 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4332 .serdes_power = mv88e6185_serdes_power, 4333 .serdes_get_lane = mv88e6185_serdes_get_lane, 4334 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4335 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4336 .ppu_enable = mv88e6185_g1_ppu_enable, 4337 .ppu_disable = mv88e6185_g1_ppu_disable, 4338 .reset = mv88e6185_g1_reset, 4339 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4340 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4341 .phylink_get_caps = mv88e6185_phylink_get_caps, 4342 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4343 }; 4344 4345 static const struct mv88e6xxx_ops mv88e6190_ops = { 4346 /* MV88E6XXX_FAMILY_6390 */ 4347 .setup_errata = mv88e6390_setup_errata, 4348 .irl_init_all = mv88e6390_g2_irl_init_all, 4349 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4350 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4352 .phy_read = mv88e6xxx_g2_smi_phy_read, 4353 .phy_write = mv88e6xxx_g2_smi_phy_write, 4354 .port_set_link = mv88e6xxx_port_set_link, 4355 .port_sync_link = mv88e6xxx_port_sync_link, 4356 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4357 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4358 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4359 .port_tag_remap = mv88e6390_port_tag_remap, 4360 .port_set_policy = mv88e6352_port_set_policy, 4361 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4362 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4363 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4364 .port_set_ether_type = mv88e6351_port_set_ether_type, 4365 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4366 .port_pause_limit = mv88e6390_port_pause_limit, 4367 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4368 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4369 .port_get_cmode = mv88e6352_port_get_cmode, 4370 .port_set_cmode = mv88e6390_port_set_cmode, 4371 .port_setup_message_port = mv88e6xxx_setup_message_port, 4372 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4373 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4374 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4375 .stats_get_strings = mv88e6320_stats_get_strings, 4376 .stats_get_stats = mv88e6390_stats_get_stats, 4377 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4378 .set_egress_port = mv88e6390_g1_set_egress_port, 4379 .watchdog_ops = &mv88e6390_watchdog_ops, 4380 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4381 .pot_clear = mv88e6xxx_g2_pot_clear, 4382 .reset = mv88e6352_g1_reset, 4383 .rmu_disable = mv88e6390_g1_rmu_disable, 4384 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4385 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4386 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4387 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4388 .serdes_power = mv88e6390_serdes_power, 4389 .serdes_get_lane = mv88e6390_serdes_get_lane, 4390 /* Check status register pause & lpa register */ 4391 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4392 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4393 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4394 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4395 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4396 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4397 .serdes_irq_status = mv88e6390_serdes_irq_status, 4398 .serdes_get_strings = mv88e6390_serdes_get_strings, 4399 .serdes_get_stats = mv88e6390_serdes_get_stats, 4400 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4401 .serdes_get_regs = mv88e6390_serdes_get_regs, 4402 .gpio_ops = &mv88e6352_gpio_ops, 4403 .phylink_get_caps = mv88e6390_phylink_get_caps, 4404 }; 4405 4406 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4407 /* MV88E6XXX_FAMILY_6390 */ 4408 .setup_errata = mv88e6390_setup_errata, 4409 .irl_init_all = mv88e6390_g2_irl_init_all, 4410 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4411 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4412 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4413 .phy_read = mv88e6xxx_g2_smi_phy_read, 4414 .phy_write = mv88e6xxx_g2_smi_phy_write, 4415 .port_set_link = mv88e6xxx_port_set_link, 4416 .port_sync_link = mv88e6xxx_port_sync_link, 4417 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4418 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4419 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4420 .port_tag_remap = mv88e6390_port_tag_remap, 4421 .port_set_policy = mv88e6352_port_set_policy, 4422 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4423 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4424 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4425 .port_set_ether_type = mv88e6351_port_set_ether_type, 4426 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4427 .port_pause_limit = mv88e6390_port_pause_limit, 4428 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4429 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4430 .port_get_cmode = mv88e6352_port_get_cmode, 4431 .port_set_cmode = mv88e6390x_port_set_cmode, 4432 .port_setup_message_port = mv88e6xxx_setup_message_port, 4433 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4434 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4435 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4436 .stats_get_strings = mv88e6320_stats_get_strings, 4437 .stats_get_stats = mv88e6390_stats_get_stats, 4438 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4439 .set_egress_port = mv88e6390_g1_set_egress_port, 4440 .watchdog_ops = &mv88e6390_watchdog_ops, 4441 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4442 .pot_clear = mv88e6xxx_g2_pot_clear, 4443 .reset = mv88e6352_g1_reset, 4444 .rmu_disable = mv88e6390_g1_rmu_disable, 4445 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4446 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4447 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4448 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4449 .serdes_power = mv88e6390_serdes_power, 4450 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4451 /* Check status register pause & lpa register */ 4452 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4453 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4454 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4455 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4456 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4457 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4458 .serdes_irq_status = mv88e6390_serdes_irq_status, 4459 .serdes_get_strings = mv88e6390_serdes_get_strings, 4460 .serdes_get_stats = mv88e6390_serdes_get_stats, 4461 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4462 .serdes_get_regs = mv88e6390_serdes_get_regs, 4463 .gpio_ops = &mv88e6352_gpio_ops, 4464 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4465 }; 4466 4467 static const struct mv88e6xxx_ops mv88e6191_ops = { 4468 /* MV88E6XXX_FAMILY_6390 */ 4469 .setup_errata = mv88e6390_setup_errata, 4470 .irl_init_all = mv88e6390_g2_irl_init_all, 4471 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4472 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4473 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4474 .phy_read = mv88e6xxx_g2_smi_phy_read, 4475 .phy_write = mv88e6xxx_g2_smi_phy_write, 4476 .port_set_link = mv88e6xxx_port_set_link, 4477 .port_sync_link = mv88e6xxx_port_sync_link, 4478 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4479 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4480 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4481 .port_tag_remap = mv88e6390_port_tag_remap, 4482 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4483 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4484 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4485 .port_set_ether_type = mv88e6351_port_set_ether_type, 4486 .port_pause_limit = mv88e6390_port_pause_limit, 4487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4489 .port_get_cmode = mv88e6352_port_get_cmode, 4490 .port_set_cmode = mv88e6390_port_set_cmode, 4491 .port_setup_message_port = mv88e6xxx_setup_message_port, 4492 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4493 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4494 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4495 .stats_get_strings = mv88e6320_stats_get_strings, 4496 .stats_get_stats = mv88e6390_stats_get_stats, 4497 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4498 .set_egress_port = mv88e6390_g1_set_egress_port, 4499 .watchdog_ops = &mv88e6390_watchdog_ops, 4500 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4501 .pot_clear = mv88e6xxx_g2_pot_clear, 4502 .reset = mv88e6352_g1_reset, 4503 .rmu_disable = mv88e6390_g1_rmu_disable, 4504 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4505 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4506 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4507 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4508 .serdes_power = mv88e6390_serdes_power, 4509 .serdes_get_lane = mv88e6390_serdes_get_lane, 4510 /* Check status register pause & lpa register */ 4511 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4512 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4513 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4514 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4515 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4516 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4517 .serdes_irq_status = mv88e6390_serdes_irq_status, 4518 .serdes_get_strings = mv88e6390_serdes_get_strings, 4519 .serdes_get_stats = mv88e6390_serdes_get_stats, 4520 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4521 .serdes_get_regs = mv88e6390_serdes_get_regs, 4522 .avb_ops = &mv88e6390_avb_ops, 4523 .ptp_ops = &mv88e6352_ptp_ops, 4524 .phylink_get_caps = mv88e6390_phylink_get_caps, 4525 }; 4526 4527 static const struct mv88e6xxx_ops mv88e6240_ops = { 4528 /* MV88E6XXX_FAMILY_6352 */ 4529 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4530 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4531 .irl_init_all = mv88e6352_g2_irl_init_all, 4532 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4533 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4534 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4535 .phy_read = mv88e6xxx_g2_smi_phy_read, 4536 .phy_write = mv88e6xxx_g2_smi_phy_write, 4537 .port_set_link = mv88e6xxx_port_set_link, 4538 .port_sync_link = mv88e6xxx_port_sync_link, 4539 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4540 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4541 .port_tag_remap = mv88e6095_port_tag_remap, 4542 .port_set_policy = mv88e6352_port_set_policy, 4543 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4544 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4545 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4546 .port_set_ether_type = mv88e6351_port_set_ether_type, 4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4549 .port_pause_limit = mv88e6097_port_pause_limit, 4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4552 .port_get_cmode = mv88e6352_port_get_cmode, 4553 .port_setup_message_port = mv88e6xxx_setup_message_port, 4554 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4555 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4556 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4557 .stats_get_strings = mv88e6095_stats_get_strings, 4558 .stats_get_stats = mv88e6095_stats_get_stats, 4559 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4560 .set_egress_port = mv88e6095_g1_set_egress_port, 4561 .watchdog_ops = &mv88e6097_watchdog_ops, 4562 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4563 .pot_clear = mv88e6xxx_g2_pot_clear, 4564 .reset = mv88e6352_g1_reset, 4565 .rmu_disable = mv88e6352_g1_rmu_disable, 4566 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4567 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4568 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4569 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4570 .serdes_get_lane = mv88e6352_serdes_get_lane, 4571 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4572 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4573 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4574 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4575 .serdes_power = mv88e6352_serdes_power, 4576 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4577 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4578 .serdes_irq_status = mv88e6352_serdes_irq_status, 4579 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4580 .serdes_get_regs = mv88e6352_serdes_get_regs, 4581 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4582 .gpio_ops = &mv88e6352_gpio_ops, 4583 .avb_ops = &mv88e6352_avb_ops, 4584 .ptp_ops = &mv88e6352_ptp_ops, 4585 .phylink_get_caps = mv88e6352_phylink_get_caps, 4586 }; 4587 4588 static const struct mv88e6xxx_ops mv88e6250_ops = { 4589 /* MV88E6XXX_FAMILY_6250 */ 4590 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4591 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4592 .irl_init_all = mv88e6352_g2_irl_init_all, 4593 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4594 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4595 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4596 .phy_read = mv88e6xxx_g2_smi_phy_read, 4597 .phy_write = mv88e6xxx_g2_smi_phy_write, 4598 .port_set_link = mv88e6xxx_port_set_link, 4599 .port_sync_link = mv88e6xxx_port_sync_link, 4600 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4601 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4602 .port_tag_remap = mv88e6095_port_tag_remap, 4603 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4604 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4605 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4606 .port_set_ether_type = mv88e6351_port_set_ether_type, 4607 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4608 .port_pause_limit = mv88e6097_port_pause_limit, 4609 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4610 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4611 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4612 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4613 .stats_get_strings = mv88e6250_stats_get_strings, 4614 .stats_get_stats = mv88e6250_stats_get_stats, 4615 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4616 .set_egress_port = mv88e6095_g1_set_egress_port, 4617 .watchdog_ops = &mv88e6250_watchdog_ops, 4618 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4619 .pot_clear = mv88e6xxx_g2_pot_clear, 4620 .reset = mv88e6250_g1_reset, 4621 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4622 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4623 .avb_ops = &mv88e6352_avb_ops, 4624 .ptp_ops = &mv88e6250_ptp_ops, 4625 .phylink_get_caps = mv88e6250_phylink_get_caps, 4626 }; 4627 4628 static const struct mv88e6xxx_ops mv88e6290_ops = { 4629 /* MV88E6XXX_FAMILY_6390 */ 4630 .setup_errata = mv88e6390_setup_errata, 4631 .irl_init_all = mv88e6390_g2_irl_init_all, 4632 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4633 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4634 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4635 .phy_read = mv88e6xxx_g2_smi_phy_read, 4636 .phy_write = mv88e6xxx_g2_smi_phy_write, 4637 .port_set_link = mv88e6xxx_port_set_link, 4638 .port_sync_link = mv88e6xxx_port_sync_link, 4639 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4640 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4641 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4642 .port_tag_remap = mv88e6390_port_tag_remap, 4643 .port_set_policy = mv88e6352_port_set_policy, 4644 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4645 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4646 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4647 .port_set_ether_type = mv88e6351_port_set_ether_type, 4648 .port_pause_limit = mv88e6390_port_pause_limit, 4649 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4650 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4651 .port_get_cmode = mv88e6352_port_get_cmode, 4652 .port_set_cmode = mv88e6390_port_set_cmode, 4653 .port_setup_message_port = mv88e6xxx_setup_message_port, 4654 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4655 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4656 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4657 .stats_get_strings = mv88e6320_stats_get_strings, 4658 .stats_get_stats = mv88e6390_stats_get_stats, 4659 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4660 .set_egress_port = mv88e6390_g1_set_egress_port, 4661 .watchdog_ops = &mv88e6390_watchdog_ops, 4662 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4663 .pot_clear = mv88e6xxx_g2_pot_clear, 4664 .reset = mv88e6352_g1_reset, 4665 .rmu_disable = mv88e6390_g1_rmu_disable, 4666 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4667 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4668 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4669 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4670 .serdes_power = mv88e6390_serdes_power, 4671 .serdes_get_lane = mv88e6390_serdes_get_lane, 4672 /* Check status register pause & lpa register */ 4673 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4674 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4675 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4676 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4677 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4678 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4679 .serdes_irq_status = mv88e6390_serdes_irq_status, 4680 .serdes_get_strings = mv88e6390_serdes_get_strings, 4681 .serdes_get_stats = mv88e6390_serdes_get_stats, 4682 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4683 .serdes_get_regs = mv88e6390_serdes_get_regs, 4684 .gpio_ops = &mv88e6352_gpio_ops, 4685 .avb_ops = &mv88e6390_avb_ops, 4686 .ptp_ops = &mv88e6352_ptp_ops, 4687 .phylink_get_caps = mv88e6390_phylink_get_caps, 4688 }; 4689 4690 static const struct mv88e6xxx_ops mv88e6320_ops = { 4691 /* MV88E6XXX_FAMILY_6320 */ 4692 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4693 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4694 .irl_init_all = mv88e6352_g2_irl_init_all, 4695 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4696 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4697 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4698 .phy_read = mv88e6xxx_g2_smi_phy_read, 4699 .phy_write = mv88e6xxx_g2_smi_phy_write, 4700 .port_set_link = mv88e6xxx_port_set_link, 4701 .port_sync_link = mv88e6xxx_port_sync_link, 4702 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4703 .port_tag_remap = mv88e6095_port_tag_remap, 4704 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4705 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4706 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4707 .port_set_ether_type = mv88e6351_port_set_ether_type, 4708 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4709 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4710 .port_pause_limit = mv88e6097_port_pause_limit, 4711 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4712 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4713 .port_get_cmode = mv88e6352_port_get_cmode, 4714 .port_setup_message_port = mv88e6xxx_setup_message_port, 4715 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4716 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4717 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4718 .stats_get_strings = mv88e6320_stats_get_strings, 4719 .stats_get_stats = mv88e6320_stats_get_stats, 4720 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4721 .set_egress_port = mv88e6095_g1_set_egress_port, 4722 .watchdog_ops = &mv88e6390_watchdog_ops, 4723 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4724 .pot_clear = mv88e6xxx_g2_pot_clear, 4725 .reset = mv88e6352_g1_reset, 4726 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4727 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4728 .gpio_ops = &mv88e6352_gpio_ops, 4729 .avb_ops = &mv88e6352_avb_ops, 4730 .ptp_ops = &mv88e6352_ptp_ops, 4731 .phylink_get_caps = mv88e6185_phylink_get_caps, 4732 }; 4733 4734 static const struct mv88e6xxx_ops mv88e6321_ops = { 4735 /* MV88E6XXX_FAMILY_6320 */ 4736 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4737 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4738 .irl_init_all = mv88e6352_g2_irl_init_all, 4739 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4740 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4741 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4742 .phy_read = mv88e6xxx_g2_smi_phy_read, 4743 .phy_write = mv88e6xxx_g2_smi_phy_write, 4744 .port_set_link = mv88e6xxx_port_set_link, 4745 .port_sync_link = mv88e6xxx_port_sync_link, 4746 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4747 .port_tag_remap = mv88e6095_port_tag_remap, 4748 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4749 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4750 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4751 .port_set_ether_type = mv88e6351_port_set_ether_type, 4752 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4753 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4754 .port_pause_limit = mv88e6097_port_pause_limit, 4755 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4756 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4757 .port_get_cmode = mv88e6352_port_get_cmode, 4758 .port_setup_message_port = mv88e6xxx_setup_message_port, 4759 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4760 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4761 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4762 .stats_get_strings = mv88e6320_stats_get_strings, 4763 .stats_get_stats = mv88e6320_stats_get_stats, 4764 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4765 .set_egress_port = mv88e6095_g1_set_egress_port, 4766 .watchdog_ops = &mv88e6390_watchdog_ops, 4767 .reset = mv88e6352_g1_reset, 4768 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4769 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4770 .gpio_ops = &mv88e6352_gpio_ops, 4771 .avb_ops = &mv88e6352_avb_ops, 4772 .ptp_ops = &mv88e6352_ptp_ops, 4773 .phylink_get_caps = mv88e6185_phylink_get_caps, 4774 }; 4775 4776 static const struct mv88e6xxx_ops mv88e6341_ops = { 4777 /* MV88E6XXX_FAMILY_6341 */ 4778 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4779 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4780 .irl_init_all = mv88e6352_g2_irl_init_all, 4781 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4782 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4784 .phy_read = mv88e6xxx_g2_smi_phy_read, 4785 .phy_write = mv88e6xxx_g2_smi_phy_write, 4786 .port_set_link = mv88e6xxx_port_set_link, 4787 .port_sync_link = mv88e6xxx_port_sync_link, 4788 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4789 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4790 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4791 .port_tag_remap = mv88e6095_port_tag_remap, 4792 .port_set_policy = mv88e6352_port_set_policy, 4793 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4794 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4795 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4796 .port_set_ether_type = mv88e6351_port_set_ether_type, 4797 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4798 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4799 .port_pause_limit = mv88e6097_port_pause_limit, 4800 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4801 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4802 .port_get_cmode = mv88e6352_port_get_cmode, 4803 .port_set_cmode = mv88e6341_port_set_cmode, 4804 .port_setup_message_port = mv88e6xxx_setup_message_port, 4805 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4806 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4807 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4808 .stats_get_strings = mv88e6320_stats_get_strings, 4809 .stats_get_stats = mv88e6390_stats_get_stats, 4810 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4811 .set_egress_port = mv88e6390_g1_set_egress_port, 4812 .watchdog_ops = &mv88e6390_watchdog_ops, 4813 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4814 .pot_clear = mv88e6xxx_g2_pot_clear, 4815 .reset = mv88e6352_g1_reset, 4816 .rmu_disable = mv88e6390_g1_rmu_disable, 4817 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4818 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4819 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4820 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4821 .serdes_power = mv88e6390_serdes_power, 4822 .serdes_get_lane = mv88e6341_serdes_get_lane, 4823 /* Check status register pause & lpa register */ 4824 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4825 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4826 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4827 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4828 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4829 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4830 .serdes_irq_status = mv88e6390_serdes_irq_status, 4831 .gpio_ops = &mv88e6352_gpio_ops, 4832 .avb_ops = &mv88e6390_avb_ops, 4833 .ptp_ops = &mv88e6352_ptp_ops, 4834 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4835 .serdes_get_strings = mv88e6390_serdes_get_strings, 4836 .serdes_get_stats = mv88e6390_serdes_get_stats, 4837 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4838 .serdes_get_regs = mv88e6390_serdes_get_regs, 4839 .phylink_get_caps = mv88e6341_phylink_get_caps, 4840 }; 4841 4842 static const struct mv88e6xxx_ops mv88e6350_ops = { 4843 /* MV88E6XXX_FAMILY_6351 */ 4844 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4845 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4846 .irl_init_all = mv88e6352_g2_irl_init_all, 4847 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4848 .phy_read = mv88e6xxx_g2_smi_phy_read, 4849 .phy_write = mv88e6xxx_g2_smi_phy_write, 4850 .port_set_link = mv88e6xxx_port_set_link, 4851 .port_sync_link = mv88e6xxx_port_sync_link, 4852 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4853 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4854 .port_tag_remap = mv88e6095_port_tag_remap, 4855 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4856 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4857 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4858 .port_set_ether_type = mv88e6351_port_set_ether_type, 4859 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4860 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4861 .port_pause_limit = mv88e6097_port_pause_limit, 4862 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4863 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4864 .port_get_cmode = mv88e6352_port_get_cmode, 4865 .port_setup_message_port = mv88e6xxx_setup_message_port, 4866 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4867 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4868 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4869 .stats_get_strings = mv88e6095_stats_get_strings, 4870 .stats_get_stats = mv88e6095_stats_get_stats, 4871 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4872 .set_egress_port = mv88e6095_g1_set_egress_port, 4873 .watchdog_ops = &mv88e6097_watchdog_ops, 4874 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4875 .pot_clear = mv88e6xxx_g2_pot_clear, 4876 .reset = mv88e6352_g1_reset, 4877 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4878 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4879 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4880 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4881 .phylink_get_caps = mv88e6185_phylink_get_caps, 4882 }; 4883 4884 static const struct mv88e6xxx_ops mv88e6351_ops = { 4885 /* MV88E6XXX_FAMILY_6351 */ 4886 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4887 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4888 .irl_init_all = mv88e6352_g2_irl_init_all, 4889 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4890 .phy_read = mv88e6xxx_g2_smi_phy_read, 4891 .phy_write = mv88e6xxx_g2_smi_phy_write, 4892 .port_set_link = mv88e6xxx_port_set_link, 4893 .port_sync_link = mv88e6xxx_port_sync_link, 4894 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4895 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4896 .port_tag_remap = mv88e6095_port_tag_remap, 4897 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4898 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4899 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4900 .port_set_ether_type = mv88e6351_port_set_ether_type, 4901 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4902 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4903 .port_pause_limit = mv88e6097_port_pause_limit, 4904 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4905 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4906 .port_get_cmode = mv88e6352_port_get_cmode, 4907 .port_setup_message_port = mv88e6xxx_setup_message_port, 4908 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4909 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4910 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4911 .stats_get_strings = mv88e6095_stats_get_strings, 4912 .stats_get_stats = mv88e6095_stats_get_stats, 4913 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4914 .set_egress_port = mv88e6095_g1_set_egress_port, 4915 .watchdog_ops = &mv88e6097_watchdog_ops, 4916 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4917 .pot_clear = mv88e6xxx_g2_pot_clear, 4918 .reset = mv88e6352_g1_reset, 4919 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4920 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4921 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4922 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4923 .avb_ops = &mv88e6352_avb_ops, 4924 .ptp_ops = &mv88e6352_ptp_ops, 4925 .phylink_get_caps = mv88e6185_phylink_get_caps, 4926 }; 4927 4928 static const struct mv88e6xxx_ops mv88e6352_ops = { 4929 /* MV88E6XXX_FAMILY_6352 */ 4930 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4931 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4932 .irl_init_all = mv88e6352_g2_irl_init_all, 4933 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4934 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4935 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4936 .phy_read = mv88e6xxx_g2_smi_phy_read, 4937 .phy_write = mv88e6xxx_g2_smi_phy_write, 4938 .port_set_link = mv88e6xxx_port_set_link, 4939 .port_sync_link = mv88e6xxx_port_sync_link, 4940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4941 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4942 .port_tag_remap = mv88e6095_port_tag_remap, 4943 .port_set_policy = mv88e6352_port_set_policy, 4944 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4945 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4946 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4947 .port_set_ether_type = mv88e6351_port_set_ether_type, 4948 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4949 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4950 .port_pause_limit = mv88e6097_port_pause_limit, 4951 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4952 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4953 .port_get_cmode = mv88e6352_port_get_cmode, 4954 .port_setup_message_port = mv88e6xxx_setup_message_port, 4955 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4956 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4957 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4958 .stats_get_strings = mv88e6095_stats_get_strings, 4959 .stats_get_stats = mv88e6095_stats_get_stats, 4960 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4961 .set_egress_port = mv88e6095_g1_set_egress_port, 4962 .watchdog_ops = &mv88e6097_watchdog_ops, 4963 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4964 .pot_clear = mv88e6xxx_g2_pot_clear, 4965 .reset = mv88e6352_g1_reset, 4966 .rmu_disable = mv88e6352_g1_rmu_disable, 4967 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4968 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4969 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4970 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4971 .serdes_get_lane = mv88e6352_serdes_get_lane, 4972 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4973 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4974 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4975 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4976 .serdes_power = mv88e6352_serdes_power, 4977 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4978 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4979 .serdes_irq_status = mv88e6352_serdes_irq_status, 4980 .gpio_ops = &mv88e6352_gpio_ops, 4981 .avb_ops = &mv88e6352_avb_ops, 4982 .ptp_ops = &mv88e6352_ptp_ops, 4983 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4984 .serdes_get_strings = mv88e6352_serdes_get_strings, 4985 .serdes_get_stats = mv88e6352_serdes_get_stats, 4986 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4987 .serdes_get_regs = mv88e6352_serdes_get_regs, 4988 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4989 .phylink_get_caps = mv88e6352_phylink_get_caps, 4990 }; 4991 4992 static const struct mv88e6xxx_ops mv88e6390_ops = { 4993 /* MV88E6XXX_FAMILY_6390 */ 4994 .setup_errata = mv88e6390_setup_errata, 4995 .irl_init_all = mv88e6390_g2_irl_init_all, 4996 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4997 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4998 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4999 .phy_read = mv88e6xxx_g2_smi_phy_read, 5000 .phy_write = mv88e6xxx_g2_smi_phy_write, 5001 .port_set_link = mv88e6xxx_port_set_link, 5002 .port_sync_link = mv88e6xxx_port_sync_link, 5003 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5004 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5005 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5006 .port_tag_remap = mv88e6390_port_tag_remap, 5007 .port_set_policy = mv88e6352_port_set_policy, 5008 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5009 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5010 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5011 .port_set_ether_type = mv88e6351_port_set_ether_type, 5012 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5013 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5014 .port_pause_limit = mv88e6390_port_pause_limit, 5015 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5016 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5017 .port_get_cmode = mv88e6352_port_get_cmode, 5018 .port_set_cmode = mv88e6390_port_set_cmode, 5019 .port_setup_message_port = mv88e6xxx_setup_message_port, 5020 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5021 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5022 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5023 .stats_get_strings = mv88e6320_stats_get_strings, 5024 .stats_get_stats = mv88e6390_stats_get_stats, 5025 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5026 .set_egress_port = mv88e6390_g1_set_egress_port, 5027 .watchdog_ops = &mv88e6390_watchdog_ops, 5028 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5029 .pot_clear = mv88e6xxx_g2_pot_clear, 5030 .reset = mv88e6352_g1_reset, 5031 .rmu_disable = mv88e6390_g1_rmu_disable, 5032 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5033 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5034 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5035 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5036 .serdes_power = mv88e6390_serdes_power, 5037 .serdes_get_lane = mv88e6390_serdes_get_lane, 5038 /* Check status register pause & lpa register */ 5039 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5040 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5041 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5042 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5043 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5044 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5045 .serdes_irq_status = mv88e6390_serdes_irq_status, 5046 .gpio_ops = &mv88e6352_gpio_ops, 5047 .avb_ops = &mv88e6390_avb_ops, 5048 .ptp_ops = &mv88e6352_ptp_ops, 5049 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5050 .serdes_get_strings = mv88e6390_serdes_get_strings, 5051 .serdes_get_stats = mv88e6390_serdes_get_stats, 5052 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5053 .serdes_get_regs = mv88e6390_serdes_get_regs, 5054 .phylink_get_caps = mv88e6390_phylink_get_caps, 5055 }; 5056 5057 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5058 /* MV88E6XXX_FAMILY_6390 */ 5059 .setup_errata = mv88e6390_setup_errata, 5060 .irl_init_all = mv88e6390_g2_irl_init_all, 5061 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5062 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5063 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5064 .phy_read = mv88e6xxx_g2_smi_phy_read, 5065 .phy_write = mv88e6xxx_g2_smi_phy_write, 5066 .port_set_link = mv88e6xxx_port_set_link, 5067 .port_sync_link = mv88e6xxx_port_sync_link, 5068 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5069 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5070 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5071 .port_tag_remap = mv88e6390_port_tag_remap, 5072 .port_set_policy = mv88e6352_port_set_policy, 5073 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5074 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5075 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5076 .port_set_ether_type = mv88e6351_port_set_ether_type, 5077 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5078 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5079 .port_pause_limit = mv88e6390_port_pause_limit, 5080 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5081 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5082 .port_get_cmode = mv88e6352_port_get_cmode, 5083 .port_set_cmode = mv88e6390x_port_set_cmode, 5084 .port_setup_message_port = mv88e6xxx_setup_message_port, 5085 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5086 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5087 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5088 .stats_get_strings = mv88e6320_stats_get_strings, 5089 .stats_get_stats = mv88e6390_stats_get_stats, 5090 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5091 .set_egress_port = mv88e6390_g1_set_egress_port, 5092 .watchdog_ops = &mv88e6390_watchdog_ops, 5093 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5094 .pot_clear = mv88e6xxx_g2_pot_clear, 5095 .reset = mv88e6352_g1_reset, 5096 .rmu_disable = mv88e6390_g1_rmu_disable, 5097 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5098 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5099 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5100 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5101 .serdes_power = mv88e6390_serdes_power, 5102 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5103 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5104 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5105 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5106 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5107 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5108 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5109 .serdes_irq_status = mv88e6390_serdes_irq_status, 5110 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5111 .serdes_get_strings = mv88e6390_serdes_get_strings, 5112 .serdes_get_stats = mv88e6390_serdes_get_stats, 5113 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5114 .serdes_get_regs = mv88e6390_serdes_get_regs, 5115 .gpio_ops = &mv88e6352_gpio_ops, 5116 .avb_ops = &mv88e6390_avb_ops, 5117 .ptp_ops = &mv88e6352_ptp_ops, 5118 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5119 }; 5120 5121 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5122 /* MV88E6XXX_FAMILY_6393 */ 5123 .setup_errata = mv88e6393x_serdes_setup_errata, 5124 .irl_init_all = mv88e6390_g2_irl_init_all, 5125 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5126 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5127 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5128 .phy_read = mv88e6xxx_g2_smi_phy_read, 5129 .phy_write = mv88e6xxx_g2_smi_phy_write, 5130 .port_set_link = mv88e6xxx_port_set_link, 5131 .port_sync_link = mv88e6xxx_port_sync_link, 5132 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5133 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5134 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5135 .port_tag_remap = mv88e6390_port_tag_remap, 5136 .port_set_policy = mv88e6393x_port_set_policy, 5137 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5138 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5139 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5140 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5142 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5143 .port_pause_limit = mv88e6390_port_pause_limit, 5144 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5145 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5146 .port_get_cmode = mv88e6352_port_get_cmode, 5147 .port_set_cmode = mv88e6393x_port_set_cmode, 5148 .port_setup_message_port = mv88e6xxx_setup_message_port, 5149 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5150 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5151 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5152 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5153 .stats_get_strings = mv88e6320_stats_get_strings, 5154 .stats_get_stats = mv88e6390_stats_get_stats, 5155 /* .set_cpu_port is missing because this family does not support a global 5156 * CPU port, only per port CPU port which is set via 5157 * .port_set_upstream_port method. 5158 */ 5159 .set_egress_port = mv88e6393x_set_egress_port, 5160 .watchdog_ops = &mv88e6390_watchdog_ops, 5161 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5162 .pot_clear = mv88e6xxx_g2_pot_clear, 5163 .reset = mv88e6352_g1_reset, 5164 .rmu_disable = mv88e6390_g1_rmu_disable, 5165 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5166 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5167 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5168 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5169 .serdes_power = mv88e6393x_serdes_power, 5170 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5171 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5172 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5173 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5174 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5175 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5176 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5177 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5178 /* TODO: serdes stats */ 5179 .gpio_ops = &mv88e6352_gpio_ops, 5180 .avb_ops = &mv88e6390_avb_ops, 5181 .ptp_ops = &mv88e6352_ptp_ops, 5182 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5183 }; 5184 5185 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5186 [MV88E6085] = { 5187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5188 .family = MV88E6XXX_FAMILY_6097, 5189 .name = "Marvell 88E6085", 5190 .num_databases = 4096, 5191 .num_macs = 8192, 5192 .num_ports = 10, 5193 .num_internal_phys = 5, 5194 .max_vid = 4095, 5195 .port_base_addr = 0x10, 5196 .phy_base_addr = 0x0, 5197 .global1_addr = 0x1b, 5198 .global2_addr = 0x1c, 5199 .age_time_coeff = 15000, 5200 .g1_irqs = 8, 5201 .g2_irqs = 10, 5202 .atu_move_port_mask = 0xf, 5203 .pvt = true, 5204 .multi_chip = true, 5205 .ops = &mv88e6085_ops, 5206 }, 5207 5208 [MV88E6095] = { 5209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5210 .family = MV88E6XXX_FAMILY_6095, 5211 .name = "Marvell 88E6095/88E6095F", 5212 .num_databases = 256, 5213 .num_macs = 8192, 5214 .num_ports = 11, 5215 .num_internal_phys = 0, 5216 .max_vid = 4095, 5217 .port_base_addr = 0x10, 5218 .phy_base_addr = 0x0, 5219 .global1_addr = 0x1b, 5220 .global2_addr = 0x1c, 5221 .age_time_coeff = 15000, 5222 .g1_irqs = 8, 5223 .atu_move_port_mask = 0xf, 5224 .multi_chip = true, 5225 .ops = &mv88e6095_ops, 5226 }, 5227 5228 [MV88E6097] = { 5229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5230 .family = MV88E6XXX_FAMILY_6097, 5231 .name = "Marvell 88E6097/88E6097F", 5232 .num_databases = 4096, 5233 .num_macs = 8192, 5234 .num_ports = 11, 5235 .num_internal_phys = 8, 5236 .max_vid = 4095, 5237 .port_base_addr = 0x10, 5238 .phy_base_addr = 0x0, 5239 .global1_addr = 0x1b, 5240 .global2_addr = 0x1c, 5241 .age_time_coeff = 15000, 5242 .g1_irqs = 8, 5243 .g2_irqs = 10, 5244 .atu_move_port_mask = 0xf, 5245 .pvt = true, 5246 .multi_chip = true, 5247 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5248 .ops = &mv88e6097_ops, 5249 }, 5250 5251 [MV88E6123] = { 5252 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5253 .family = MV88E6XXX_FAMILY_6165, 5254 .name = "Marvell 88E6123", 5255 .num_databases = 4096, 5256 .num_macs = 1024, 5257 .num_ports = 3, 5258 .num_internal_phys = 5, 5259 .max_vid = 4095, 5260 .port_base_addr = 0x10, 5261 .phy_base_addr = 0x0, 5262 .global1_addr = 0x1b, 5263 .global2_addr = 0x1c, 5264 .age_time_coeff = 15000, 5265 .g1_irqs = 9, 5266 .g2_irqs = 10, 5267 .atu_move_port_mask = 0xf, 5268 .pvt = true, 5269 .multi_chip = true, 5270 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5271 .ops = &mv88e6123_ops, 5272 }, 5273 5274 [MV88E6131] = { 5275 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5276 .family = MV88E6XXX_FAMILY_6185, 5277 .name = "Marvell 88E6131", 5278 .num_databases = 256, 5279 .num_macs = 8192, 5280 .num_ports = 8, 5281 .num_internal_phys = 0, 5282 .max_vid = 4095, 5283 .port_base_addr = 0x10, 5284 .phy_base_addr = 0x0, 5285 .global1_addr = 0x1b, 5286 .global2_addr = 0x1c, 5287 .age_time_coeff = 15000, 5288 .g1_irqs = 9, 5289 .atu_move_port_mask = 0xf, 5290 .multi_chip = true, 5291 .ops = &mv88e6131_ops, 5292 }, 5293 5294 [MV88E6141] = { 5295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5296 .family = MV88E6XXX_FAMILY_6341, 5297 .name = "Marvell 88E6141", 5298 .num_databases = 4096, 5299 .num_macs = 2048, 5300 .num_ports = 6, 5301 .num_internal_phys = 5, 5302 .num_gpio = 11, 5303 .max_vid = 4095, 5304 .port_base_addr = 0x10, 5305 .phy_base_addr = 0x10, 5306 .global1_addr = 0x1b, 5307 .global2_addr = 0x1c, 5308 .age_time_coeff = 3750, 5309 .atu_move_port_mask = 0x1f, 5310 .g1_irqs = 9, 5311 .g2_irqs = 10, 5312 .pvt = true, 5313 .multi_chip = true, 5314 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5315 .ops = &mv88e6141_ops, 5316 }, 5317 5318 [MV88E6161] = { 5319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5320 .family = MV88E6XXX_FAMILY_6165, 5321 .name = "Marvell 88E6161", 5322 .num_databases = 4096, 5323 .num_macs = 1024, 5324 .num_ports = 6, 5325 .num_internal_phys = 5, 5326 .max_vid = 4095, 5327 .port_base_addr = 0x10, 5328 .phy_base_addr = 0x0, 5329 .global1_addr = 0x1b, 5330 .global2_addr = 0x1c, 5331 .age_time_coeff = 15000, 5332 .g1_irqs = 9, 5333 .g2_irqs = 10, 5334 .atu_move_port_mask = 0xf, 5335 .pvt = true, 5336 .multi_chip = true, 5337 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5338 .ptp_support = true, 5339 .ops = &mv88e6161_ops, 5340 }, 5341 5342 [MV88E6165] = { 5343 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5344 .family = MV88E6XXX_FAMILY_6165, 5345 .name = "Marvell 88E6165", 5346 .num_databases = 4096, 5347 .num_macs = 8192, 5348 .num_ports = 6, 5349 .num_internal_phys = 0, 5350 .max_vid = 4095, 5351 .port_base_addr = 0x10, 5352 .phy_base_addr = 0x0, 5353 .global1_addr = 0x1b, 5354 .global2_addr = 0x1c, 5355 .age_time_coeff = 15000, 5356 .g1_irqs = 9, 5357 .g2_irqs = 10, 5358 .atu_move_port_mask = 0xf, 5359 .pvt = true, 5360 .multi_chip = true, 5361 .ptp_support = true, 5362 .ops = &mv88e6165_ops, 5363 }, 5364 5365 [MV88E6171] = { 5366 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5367 .family = MV88E6XXX_FAMILY_6351, 5368 .name = "Marvell 88E6171", 5369 .num_databases = 4096, 5370 .num_macs = 8192, 5371 .num_ports = 7, 5372 .num_internal_phys = 5, 5373 .max_vid = 4095, 5374 .port_base_addr = 0x10, 5375 .phy_base_addr = 0x0, 5376 .global1_addr = 0x1b, 5377 .global2_addr = 0x1c, 5378 .age_time_coeff = 15000, 5379 .g1_irqs = 9, 5380 .g2_irqs = 10, 5381 .atu_move_port_mask = 0xf, 5382 .pvt = true, 5383 .multi_chip = true, 5384 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5385 .ops = &mv88e6171_ops, 5386 }, 5387 5388 [MV88E6172] = { 5389 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5390 .family = MV88E6XXX_FAMILY_6352, 5391 .name = "Marvell 88E6172", 5392 .num_databases = 4096, 5393 .num_macs = 8192, 5394 .num_ports = 7, 5395 .num_internal_phys = 5, 5396 .num_gpio = 15, 5397 .max_vid = 4095, 5398 .port_base_addr = 0x10, 5399 .phy_base_addr = 0x0, 5400 .global1_addr = 0x1b, 5401 .global2_addr = 0x1c, 5402 .age_time_coeff = 15000, 5403 .g1_irqs = 9, 5404 .g2_irqs = 10, 5405 .atu_move_port_mask = 0xf, 5406 .pvt = true, 5407 .multi_chip = true, 5408 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5409 .ops = &mv88e6172_ops, 5410 }, 5411 5412 [MV88E6175] = { 5413 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5414 .family = MV88E6XXX_FAMILY_6351, 5415 .name = "Marvell 88E6175", 5416 .num_databases = 4096, 5417 .num_macs = 8192, 5418 .num_ports = 7, 5419 .num_internal_phys = 5, 5420 .max_vid = 4095, 5421 .port_base_addr = 0x10, 5422 .phy_base_addr = 0x0, 5423 .global1_addr = 0x1b, 5424 .global2_addr = 0x1c, 5425 .age_time_coeff = 15000, 5426 .g1_irqs = 9, 5427 .g2_irqs = 10, 5428 .atu_move_port_mask = 0xf, 5429 .pvt = true, 5430 .multi_chip = true, 5431 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5432 .ops = &mv88e6175_ops, 5433 }, 5434 5435 [MV88E6176] = { 5436 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5437 .family = MV88E6XXX_FAMILY_6352, 5438 .name = "Marvell 88E6176", 5439 .num_databases = 4096, 5440 .num_macs = 8192, 5441 .num_ports = 7, 5442 .num_internal_phys = 5, 5443 .num_gpio = 15, 5444 .max_vid = 4095, 5445 .port_base_addr = 0x10, 5446 .phy_base_addr = 0x0, 5447 .global1_addr = 0x1b, 5448 .global2_addr = 0x1c, 5449 .age_time_coeff = 15000, 5450 .g1_irqs = 9, 5451 .g2_irqs = 10, 5452 .atu_move_port_mask = 0xf, 5453 .pvt = true, 5454 .multi_chip = true, 5455 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5456 .ops = &mv88e6176_ops, 5457 }, 5458 5459 [MV88E6185] = { 5460 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5461 .family = MV88E6XXX_FAMILY_6185, 5462 .name = "Marvell 88E6185", 5463 .num_databases = 256, 5464 .num_macs = 8192, 5465 .num_ports = 10, 5466 .num_internal_phys = 0, 5467 .max_vid = 4095, 5468 .port_base_addr = 0x10, 5469 .phy_base_addr = 0x0, 5470 .global1_addr = 0x1b, 5471 .global2_addr = 0x1c, 5472 .age_time_coeff = 15000, 5473 .g1_irqs = 8, 5474 .atu_move_port_mask = 0xf, 5475 .multi_chip = true, 5476 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5477 .ops = &mv88e6185_ops, 5478 }, 5479 5480 [MV88E6190] = { 5481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5482 .family = MV88E6XXX_FAMILY_6390, 5483 .name = "Marvell 88E6190", 5484 .num_databases = 4096, 5485 .num_macs = 16384, 5486 .num_ports = 11, /* 10 + Z80 */ 5487 .num_internal_phys = 9, 5488 .num_gpio = 16, 5489 .max_vid = 8191, 5490 .port_base_addr = 0x0, 5491 .phy_base_addr = 0x0, 5492 .global1_addr = 0x1b, 5493 .global2_addr = 0x1c, 5494 .age_time_coeff = 3750, 5495 .g1_irqs = 9, 5496 .g2_irqs = 14, 5497 .pvt = true, 5498 .multi_chip = true, 5499 .atu_move_port_mask = 0x1f, 5500 .ops = &mv88e6190_ops, 5501 }, 5502 5503 [MV88E6190X] = { 5504 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5505 .family = MV88E6XXX_FAMILY_6390, 5506 .name = "Marvell 88E6190X", 5507 .num_databases = 4096, 5508 .num_macs = 16384, 5509 .num_ports = 11, /* 10 + Z80 */ 5510 .num_internal_phys = 9, 5511 .num_gpio = 16, 5512 .max_vid = 8191, 5513 .port_base_addr = 0x0, 5514 .phy_base_addr = 0x0, 5515 .global1_addr = 0x1b, 5516 .global2_addr = 0x1c, 5517 .age_time_coeff = 3750, 5518 .g1_irqs = 9, 5519 .g2_irqs = 14, 5520 .atu_move_port_mask = 0x1f, 5521 .pvt = true, 5522 .multi_chip = true, 5523 .ops = &mv88e6190x_ops, 5524 }, 5525 5526 [MV88E6191] = { 5527 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5528 .family = MV88E6XXX_FAMILY_6390, 5529 .name = "Marvell 88E6191", 5530 .num_databases = 4096, 5531 .num_macs = 16384, 5532 .num_ports = 11, /* 10 + Z80 */ 5533 .num_internal_phys = 9, 5534 .max_vid = 8191, 5535 .port_base_addr = 0x0, 5536 .phy_base_addr = 0x0, 5537 .global1_addr = 0x1b, 5538 .global2_addr = 0x1c, 5539 .age_time_coeff = 3750, 5540 .g1_irqs = 9, 5541 .g2_irqs = 14, 5542 .atu_move_port_mask = 0x1f, 5543 .pvt = true, 5544 .multi_chip = true, 5545 .ptp_support = true, 5546 .ops = &mv88e6191_ops, 5547 }, 5548 5549 [MV88E6191X] = { 5550 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5551 .family = MV88E6XXX_FAMILY_6393, 5552 .name = "Marvell 88E6191X", 5553 .num_databases = 4096, 5554 .num_ports = 11, /* 10 + Z80 */ 5555 .num_internal_phys = 9, 5556 .max_vid = 8191, 5557 .port_base_addr = 0x0, 5558 .phy_base_addr = 0x0, 5559 .global1_addr = 0x1b, 5560 .global2_addr = 0x1c, 5561 .age_time_coeff = 3750, 5562 .g1_irqs = 10, 5563 .g2_irqs = 14, 5564 .atu_move_port_mask = 0x1f, 5565 .pvt = true, 5566 .multi_chip = true, 5567 .ptp_support = true, 5568 .ops = &mv88e6393x_ops, 5569 }, 5570 5571 [MV88E6193X] = { 5572 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5573 .family = MV88E6XXX_FAMILY_6393, 5574 .name = "Marvell 88E6193X", 5575 .num_databases = 4096, 5576 .num_ports = 11, /* 10 + Z80 */ 5577 .num_internal_phys = 9, 5578 .max_vid = 8191, 5579 .port_base_addr = 0x0, 5580 .phy_base_addr = 0x0, 5581 .global1_addr = 0x1b, 5582 .global2_addr = 0x1c, 5583 .age_time_coeff = 3750, 5584 .g1_irqs = 10, 5585 .g2_irqs = 14, 5586 .atu_move_port_mask = 0x1f, 5587 .pvt = true, 5588 .multi_chip = true, 5589 .ptp_support = true, 5590 .ops = &mv88e6393x_ops, 5591 }, 5592 5593 [MV88E6220] = { 5594 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5595 .family = MV88E6XXX_FAMILY_6250, 5596 .name = "Marvell 88E6220", 5597 .num_databases = 64, 5598 5599 /* Ports 2-4 are not routed to pins 5600 * => usable ports 0, 1, 5, 6 5601 */ 5602 .num_ports = 7, 5603 .num_internal_phys = 2, 5604 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5605 .max_vid = 4095, 5606 .port_base_addr = 0x08, 5607 .phy_base_addr = 0x00, 5608 .global1_addr = 0x0f, 5609 .global2_addr = 0x07, 5610 .age_time_coeff = 15000, 5611 .g1_irqs = 9, 5612 .g2_irqs = 10, 5613 .atu_move_port_mask = 0xf, 5614 .dual_chip = true, 5615 .ptp_support = true, 5616 .ops = &mv88e6250_ops, 5617 }, 5618 5619 [MV88E6240] = { 5620 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5621 .family = MV88E6XXX_FAMILY_6352, 5622 .name = "Marvell 88E6240", 5623 .num_databases = 4096, 5624 .num_macs = 8192, 5625 .num_ports = 7, 5626 .num_internal_phys = 5, 5627 .num_gpio = 15, 5628 .max_vid = 4095, 5629 .port_base_addr = 0x10, 5630 .phy_base_addr = 0x0, 5631 .global1_addr = 0x1b, 5632 .global2_addr = 0x1c, 5633 .age_time_coeff = 15000, 5634 .g1_irqs = 9, 5635 .g2_irqs = 10, 5636 .atu_move_port_mask = 0xf, 5637 .pvt = true, 5638 .multi_chip = true, 5639 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5640 .ptp_support = true, 5641 .ops = &mv88e6240_ops, 5642 }, 5643 5644 [MV88E6250] = { 5645 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5646 .family = MV88E6XXX_FAMILY_6250, 5647 .name = "Marvell 88E6250", 5648 .num_databases = 64, 5649 .num_ports = 7, 5650 .num_internal_phys = 5, 5651 .max_vid = 4095, 5652 .port_base_addr = 0x08, 5653 .phy_base_addr = 0x00, 5654 .global1_addr = 0x0f, 5655 .global2_addr = 0x07, 5656 .age_time_coeff = 15000, 5657 .g1_irqs = 9, 5658 .g2_irqs = 10, 5659 .atu_move_port_mask = 0xf, 5660 .dual_chip = true, 5661 .ptp_support = true, 5662 .ops = &mv88e6250_ops, 5663 }, 5664 5665 [MV88E6290] = { 5666 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5667 .family = MV88E6XXX_FAMILY_6390, 5668 .name = "Marvell 88E6290", 5669 .num_databases = 4096, 5670 .num_ports = 11, /* 10 + Z80 */ 5671 .num_internal_phys = 9, 5672 .num_gpio = 16, 5673 .max_vid = 8191, 5674 .port_base_addr = 0x0, 5675 .phy_base_addr = 0x0, 5676 .global1_addr = 0x1b, 5677 .global2_addr = 0x1c, 5678 .age_time_coeff = 3750, 5679 .g1_irqs = 9, 5680 .g2_irqs = 14, 5681 .atu_move_port_mask = 0x1f, 5682 .pvt = true, 5683 .multi_chip = true, 5684 .ptp_support = true, 5685 .ops = &mv88e6290_ops, 5686 }, 5687 5688 [MV88E6320] = { 5689 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5690 .family = MV88E6XXX_FAMILY_6320, 5691 .name = "Marvell 88E6320", 5692 .num_databases = 4096, 5693 .num_macs = 8192, 5694 .num_ports = 7, 5695 .num_internal_phys = 5, 5696 .num_gpio = 15, 5697 .max_vid = 4095, 5698 .port_base_addr = 0x10, 5699 .phy_base_addr = 0x0, 5700 .global1_addr = 0x1b, 5701 .global2_addr = 0x1c, 5702 .age_time_coeff = 15000, 5703 .g1_irqs = 8, 5704 .g2_irqs = 10, 5705 .atu_move_port_mask = 0xf, 5706 .pvt = true, 5707 .multi_chip = true, 5708 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5709 .ptp_support = true, 5710 .ops = &mv88e6320_ops, 5711 }, 5712 5713 [MV88E6321] = { 5714 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5715 .family = MV88E6XXX_FAMILY_6320, 5716 .name = "Marvell 88E6321", 5717 .num_databases = 4096, 5718 .num_macs = 8192, 5719 .num_ports = 7, 5720 .num_internal_phys = 5, 5721 .num_gpio = 15, 5722 .max_vid = 4095, 5723 .port_base_addr = 0x10, 5724 .phy_base_addr = 0x0, 5725 .global1_addr = 0x1b, 5726 .global2_addr = 0x1c, 5727 .age_time_coeff = 15000, 5728 .g1_irqs = 8, 5729 .g2_irqs = 10, 5730 .atu_move_port_mask = 0xf, 5731 .multi_chip = true, 5732 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5733 .ptp_support = true, 5734 .ops = &mv88e6321_ops, 5735 }, 5736 5737 [MV88E6341] = { 5738 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5739 .family = MV88E6XXX_FAMILY_6341, 5740 .name = "Marvell 88E6341", 5741 .num_databases = 4096, 5742 .num_macs = 2048, 5743 .num_internal_phys = 5, 5744 .num_ports = 6, 5745 .num_gpio = 11, 5746 .max_vid = 4095, 5747 .port_base_addr = 0x10, 5748 .phy_base_addr = 0x10, 5749 .global1_addr = 0x1b, 5750 .global2_addr = 0x1c, 5751 .age_time_coeff = 3750, 5752 .atu_move_port_mask = 0x1f, 5753 .g1_irqs = 9, 5754 .g2_irqs = 10, 5755 .pvt = true, 5756 .multi_chip = true, 5757 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5758 .ptp_support = true, 5759 .ops = &mv88e6341_ops, 5760 }, 5761 5762 [MV88E6350] = { 5763 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5764 .family = MV88E6XXX_FAMILY_6351, 5765 .name = "Marvell 88E6350", 5766 .num_databases = 4096, 5767 .num_macs = 8192, 5768 .num_ports = 7, 5769 .num_internal_phys = 5, 5770 .max_vid = 4095, 5771 .port_base_addr = 0x10, 5772 .phy_base_addr = 0x0, 5773 .global1_addr = 0x1b, 5774 .global2_addr = 0x1c, 5775 .age_time_coeff = 15000, 5776 .g1_irqs = 9, 5777 .g2_irqs = 10, 5778 .atu_move_port_mask = 0xf, 5779 .pvt = true, 5780 .multi_chip = true, 5781 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5782 .ops = &mv88e6350_ops, 5783 }, 5784 5785 [MV88E6351] = { 5786 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5787 .family = MV88E6XXX_FAMILY_6351, 5788 .name = "Marvell 88E6351", 5789 .num_databases = 4096, 5790 .num_macs = 8192, 5791 .num_ports = 7, 5792 .num_internal_phys = 5, 5793 .max_vid = 4095, 5794 .port_base_addr = 0x10, 5795 .phy_base_addr = 0x0, 5796 .global1_addr = 0x1b, 5797 .global2_addr = 0x1c, 5798 .age_time_coeff = 15000, 5799 .g1_irqs = 9, 5800 .g2_irqs = 10, 5801 .atu_move_port_mask = 0xf, 5802 .pvt = true, 5803 .multi_chip = true, 5804 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5805 .ops = &mv88e6351_ops, 5806 }, 5807 5808 [MV88E6352] = { 5809 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5810 .family = MV88E6XXX_FAMILY_6352, 5811 .name = "Marvell 88E6352", 5812 .num_databases = 4096, 5813 .num_macs = 8192, 5814 .num_ports = 7, 5815 .num_internal_phys = 5, 5816 .num_gpio = 15, 5817 .max_vid = 4095, 5818 .port_base_addr = 0x10, 5819 .phy_base_addr = 0x0, 5820 .global1_addr = 0x1b, 5821 .global2_addr = 0x1c, 5822 .age_time_coeff = 15000, 5823 .g1_irqs = 9, 5824 .g2_irqs = 10, 5825 .atu_move_port_mask = 0xf, 5826 .pvt = true, 5827 .multi_chip = true, 5828 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5829 .ptp_support = true, 5830 .ops = &mv88e6352_ops, 5831 }, 5832 [MV88E6390] = { 5833 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5834 .family = MV88E6XXX_FAMILY_6390, 5835 .name = "Marvell 88E6390", 5836 .num_databases = 4096, 5837 .num_macs = 16384, 5838 .num_ports = 11, /* 10 + Z80 */ 5839 .num_internal_phys = 9, 5840 .num_gpio = 16, 5841 .max_vid = 8191, 5842 .port_base_addr = 0x0, 5843 .phy_base_addr = 0x0, 5844 .global1_addr = 0x1b, 5845 .global2_addr = 0x1c, 5846 .age_time_coeff = 3750, 5847 .g1_irqs = 9, 5848 .g2_irqs = 14, 5849 .atu_move_port_mask = 0x1f, 5850 .pvt = true, 5851 .multi_chip = true, 5852 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5853 .ptp_support = true, 5854 .ops = &mv88e6390_ops, 5855 }, 5856 [MV88E6390X] = { 5857 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5858 .family = MV88E6XXX_FAMILY_6390, 5859 .name = "Marvell 88E6390X", 5860 .num_databases = 4096, 5861 .num_macs = 16384, 5862 .num_ports = 11, /* 10 + Z80 */ 5863 .num_internal_phys = 9, 5864 .num_gpio = 16, 5865 .max_vid = 8191, 5866 .port_base_addr = 0x0, 5867 .phy_base_addr = 0x0, 5868 .global1_addr = 0x1b, 5869 .global2_addr = 0x1c, 5870 .age_time_coeff = 3750, 5871 .g1_irqs = 9, 5872 .g2_irqs = 14, 5873 .atu_move_port_mask = 0x1f, 5874 .pvt = true, 5875 .multi_chip = true, 5876 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5877 .ptp_support = true, 5878 .ops = &mv88e6390x_ops, 5879 }, 5880 5881 [MV88E6393X] = { 5882 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5883 .family = MV88E6XXX_FAMILY_6393, 5884 .name = "Marvell 88E6393X", 5885 .num_databases = 4096, 5886 .num_ports = 11, /* 10 + Z80 */ 5887 .num_internal_phys = 9, 5888 .max_vid = 8191, 5889 .port_base_addr = 0x0, 5890 .phy_base_addr = 0x0, 5891 .global1_addr = 0x1b, 5892 .global2_addr = 0x1c, 5893 .age_time_coeff = 3750, 5894 .g1_irqs = 10, 5895 .g2_irqs = 14, 5896 .atu_move_port_mask = 0x1f, 5897 .pvt = true, 5898 .multi_chip = true, 5899 .ptp_support = true, 5900 .ops = &mv88e6393x_ops, 5901 }, 5902 }; 5903 5904 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5905 { 5906 int i; 5907 5908 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5909 if (mv88e6xxx_table[i].prod_num == prod_num) 5910 return &mv88e6xxx_table[i]; 5911 5912 return NULL; 5913 } 5914 5915 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5916 { 5917 const struct mv88e6xxx_info *info; 5918 unsigned int prod_num, rev; 5919 u16 id; 5920 int err; 5921 5922 mv88e6xxx_reg_lock(chip); 5923 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5924 mv88e6xxx_reg_unlock(chip); 5925 if (err) 5926 return err; 5927 5928 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5929 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5930 5931 info = mv88e6xxx_lookup_info(prod_num); 5932 if (!info) 5933 return -ENODEV; 5934 5935 /* Update the compatible info with the probed one */ 5936 chip->info = info; 5937 5938 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5939 chip->info->prod_num, chip->info->name, rev); 5940 5941 return 0; 5942 } 5943 5944 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5945 { 5946 struct mv88e6xxx_chip *chip; 5947 5948 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5949 if (!chip) 5950 return NULL; 5951 5952 chip->dev = dev; 5953 5954 mutex_init(&chip->reg_lock); 5955 INIT_LIST_HEAD(&chip->mdios); 5956 idr_init(&chip->policies); 5957 5958 return chip; 5959 } 5960 5961 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5962 int port, 5963 enum dsa_tag_protocol m) 5964 { 5965 struct mv88e6xxx_chip *chip = ds->priv; 5966 5967 return chip->tag_protocol; 5968 } 5969 5970 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5971 enum dsa_tag_protocol proto) 5972 { 5973 struct mv88e6xxx_chip *chip = ds->priv; 5974 enum dsa_tag_protocol old_protocol; 5975 int err; 5976 5977 switch (proto) { 5978 case DSA_TAG_PROTO_EDSA: 5979 switch (chip->info->edsa_support) { 5980 case MV88E6XXX_EDSA_UNSUPPORTED: 5981 return -EPROTONOSUPPORT; 5982 case MV88E6XXX_EDSA_UNDOCUMENTED: 5983 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5984 fallthrough; 5985 case MV88E6XXX_EDSA_SUPPORTED: 5986 break; 5987 } 5988 break; 5989 case DSA_TAG_PROTO_DSA: 5990 break; 5991 default: 5992 return -EPROTONOSUPPORT; 5993 } 5994 5995 old_protocol = chip->tag_protocol; 5996 chip->tag_protocol = proto; 5997 5998 mv88e6xxx_reg_lock(chip); 5999 err = mv88e6xxx_setup_port_mode(chip, port); 6000 mv88e6xxx_reg_unlock(chip); 6001 6002 if (err) 6003 chip->tag_protocol = old_protocol; 6004 6005 return err; 6006 } 6007 6008 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6009 const struct switchdev_obj_port_mdb *mdb, 6010 struct dsa_db db) 6011 { 6012 struct mv88e6xxx_chip *chip = ds->priv; 6013 int err; 6014 6015 mv88e6xxx_reg_lock(chip); 6016 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6017 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6018 mv88e6xxx_reg_unlock(chip); 6019 6020 return err; 6021 } 6022 6023 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6024 const struct switchdev_obj_port_mdb *mdb, 6025 struct dsa_db db) 6026 { 6027 struct mv88e6xxx_chip *chip = ds->priv; 6028 int err; 6029 6030 mv88e6xxx_reg_lock(chip); 6031 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6032 mv88e6xxx_reg_unlock(chip); 6033 6034 return err; 6035 } 6036 6037 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6038 struct dsa_mall_mirror_tc_entry *mirror, 6039 bool ingress) 6040 { 6041 enum mv88e6xxx_egress_direction direction = ingress ? 6042 MV88E6XXX_EGRESS_DIR_INGRESS : 6043 MV88E6XXX_EGRESS_DIR_EGRESS; 6044 struct mv88e6xxx_chip *chip = ds->priv; 6045 bool other_mirrors = false; 6046 int i; 6047 int err; 6048 6049 mutex_lock(&chip->reg_lock); 6050 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6051 mirror->to_local_port) { 6052 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6053 other_mirrors |= ingress ? 6054 chip->ports[i].mirror_ingress : 6055 chip->ports[i].mirror_egress; 6056 6057 /* Can't change egress port when other mirror is active */ 6058 if (other_mirrors) { 6059 err = -EBUSY; 6060 goto out; 6061 } 6062 6063 err = mv88e6xxx_set_egress_port(chip, direction, 6064 mirror->to_local_port); 6065 if (err) 6066 goto out; 6067 } 6068 6069 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6070 out: 6071 mutex_unlock(&chip->reg_lock); 6072 6073 return err; 6074 } 6075 6076 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6077 struct dsa_mall_mirror_tc_entry *mirror) 6078 { 6079 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6080 MV88E6XXX_EGRESS_DIR_INGRESS : 6081 MV88E6XXX_EGRESS_DIR_EGRESS; 6082 struct mv88e6xxx_chip *chip = ds->priv; 6083 bool other_mirrors = false; 6084 int i; 6085 6086 mutex_lock(&chip->reg_lock); 6087 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6088 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6089 6090 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6091 other_mirrors |= mirror->ingress ? 6092 chip->ports[i].mirror_ingress : 6093 chip->ports[i].mirror_egress; 6094 6095 /* Reset egress port when no other mirror is active */ 6096 if (!other_mirrors) { 6097 if (mv88e6xxx_set_egress_port(chip, direction, 6098 dsa_upstream_port(ds, port))) 6099 dev_err(ds->dev, "failed to set egress port\n"); 6100 } 6101 6102 mutex_unlock(&chip->reg_lock); 6103 } 6104 6105 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6106 struct switchdev_brport_flags flags, 6107 struct netlink_ext_ack *extack) 6108 { 6109 struct mv88e6xxx_chip *chip = ds->priv; 6110 const struct mv88e6xxx_ops *ops; 6111 6112 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6113 BR_BCAST_FLOOD | BR_PORT_LOCKED)) 6114 return -EINVAL; 6115 6116 ops = chip->info->ops; 6117 6118 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6119 return -EINVAL; 6120 6121 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6122 return -EINVAL; 6123 6124 return 0; 6125 } 6126 6127 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6128 struct switchdev_brport_flags flags, 6129 struct netlink_ext_ack *extack) 6130 { 6131 struct mv88e6xxx_chip *chip = ds->priv; 6132 int err = -EOPNOTSUPP; 6133 6134 mv88e6xxx_reg_lock(chip); 6135 6136 if (flags.mask & BR_LEARNING) { 6137 bool learning = !!(flags.val & BR_LEARNING); 6138 u16 pav = learning ? (1 << port) : 0; 6139 6140 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6141 if (err) 6142 goto out; 6143 } 6144 6145 if (flags.mask & BR_FLOOD) { 6146 bool unicast = !!(flags.val & BR_FLOOD); 6147 6148 err = chip->info->ops->port_set_ucast_flood(chip, port, 6149 unicast); 6150 if (err) 6151 goto out; 6152 } 6153 6154 if (flags.mask & BR_MCAST_FLOOD) { 6155 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6156 6157 err = chip->info->ops->port_set_mcast_flood(chip, port, 6158 multicast); 6159 if (err) 6160 goto out; 6161 } 6162 6163 if (flags.mask & BR_BCAST_FLOOD) { 6164 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6165 6166 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6167 if (err) 6168 goto out; 6169 } 6170 6171 if (flags.mask & BR_PORT_LOCKED) { 6172 bool locked = !!(flags.val & BR_PORT_LOCKED); 6173 6174 err = mv88e6xxx_port_set_lock(chip, port, locked); 6175 if (err) 6176 goto out; 6177 } 6178 out: 6179 mv88e6xxx_reg_unlock(chip); 6180 6181 return err; 6182 } 6183 6184 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6185 struct dsa_lag lag, 6186 struct netdev_lag_upper_info *info) 6187 { 6188 struct mv88e6xxx_chip *chip = ds->priv; 6189 struct dsa_port *dp; 6190 int members = 0; 6191 6192 if (!mv88e6xxx_has_lag(chip)) 6193 return false; 6194 6195 if (!lag.id) 6196 return false; 6197 6198 dsa_lag_foreach_port(dp, ds->dst, &lag) 6199 /* Includes the port joining the LAG */ 6200 members++; 6201 6202 if (members > 8) 6203 return false; 6204 6205 /* We could potentially relax this to include active 6206 * backup in the future. 6207 */ 6208 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 6209 return false; 6210 6211 /* Ideally we would also validate that the hash type matches 6212 * the hardware. Alas, this is always set to unknown on team 6213 * interfaces. 6214 */ 6215 return true; 6216 } 6217 6218 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6219 { 6220 struct mv88e6xxx_chip *chip = ds->priv; 6221 struct dsa_port *dp; 6222 u16 map = 0; 6223 int id; 6224 6225 /* DSA LAG IDs are one-based, hardware is zero-based */ 6226 id = lag.id - 1; 6227 6228 /* Build the map of all ports to distribute flows destined for 6229 * this LAG. This can be either a local user port, or a DSA 6230 * port if the LAG port is on a remote chip. 6231 */ 6232 dsa_lag_foreach_port(dp, ds->dst, &lag) 6233 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6234 6235 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6236 } 6237 6238 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6239 /* Row number corresponds to the number of active members in a 6240 * LAG. Each column states which of the eight hash buckets are 6241 * mapped to the column:th port in the LAG. 6242 * 6243 * Example: In a LAG with three active ports, the second port 6244 * ([2][1]) would be selected for traffic mapped to buckets 6245 * 3,4,5 (0x38). 6246 */ 6247 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6248 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6249 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6250 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6251 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6252 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6253 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6254 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6255 }; 6256 6257 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6258 int num_tx, int nth) 6259 { 6260 u8 active = 0; 6261 int i; 6262 6263 num_tx = num_tx <= 8 ? num_tx : 8; 6264 if (nth < num_tx) 6265 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6266 6267 for (i = 0; i < 8; i++) { 6268 if (BIT(i) & active) 6269 mask[i] |= BIT(port); 6270 } 6271 } 6272 6273 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6274 { 6275 struct mv88e6xxx_chip *chip = ds->priv; 6276 unsigned int id, num_tx; 6277 struct dsa_port *dp; 6278 struct dsa_lag *lag; 6279 int i, err, nth; 6280 u16 mask[8]; 6281 u16 ivec; 6282 6283 /* Assume no port is a member of any LAG. */ 6284 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6285 6286 /* Disable all masks for ports that _are_ members of a LAG. */ 6287 dsa_switch_for_each_port(dp, ds) { 6288 if (!dp->lag) 6289 continue; 6290 6291 ivec &= ~BIT(dp->index); 6292 } 6293 6294 for (i = 0; i < 8; i++) 6295 mask[i] = ivec; 6296 6297 /* Enable the correct subset of masks for all LAG ports that 6298 * are in the Tx set. 6299 */ 6300 dsa_lags_foreach_id(id, ds->dst) { 6301 lag = dsa_lag_by_id(ds->dst, id); 6302 if (!lag) 6303 continue; 6304 6305 num_tx = 0; 6306 dsa_lag_foreach_port(dp, ds->dst, lag) { 6307 if (dp->lag_tx_enabled) 6308 num_tx++; 6309 } 6310 6311 if (!num_tx) 6312 continue; 6313 6314 nth = 0; 6315 dsa_lag_foreach_port(dp, ds->dst, lag) { 6316 if (!dp->lag_tx_enabled) 6317 continue; 6318 6319 if (dp->ds == ds) 6320 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6321 num_tx, nth); 6322 6323 nth++; 6324 } 6325 } 6326 6327 for (i = 0; i < 8; i++) { 6328 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6329 if (err) 6330 return err; 6331 } 6332 6333 return 0; 6334 } 6335 6336 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6337 struct dsa_lag lag) 6338 { 6339 int err; 6340 6341 err = mv88e6xxx_lag_sync_masks(ds); 6342 6343 if (!err) 6344 err = mv88e6xxx_lag_sync_map(ds, lag); 6345 6346 return err; 6347 } 6348 6349 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6350 { 6351 struct mv88e6xxx_chip *chip = ds->priv; 6352 int err; 6353 6354 mv88e6xxx_reg_lock(chip); 6355 err = mv88e6xxx_lag_sync_masks(ds); 6356 mv88e6xxx_reg_unlock(chip); 6357 return err; 6358 } 6359 6360 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6361 struct dsa_lag lag, 6362 struct netdev_lag_upper_info *info) 6363 { 6364 struct mv88e6xxx_chip *chip = ds->priv; 6365 int err, id; 6366 6367 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6368 return -EOPNOTSUPP; 6369 6370 /* DSA LAG IDs are one-based */ 6371 id = lag.id - 1; 6372 6373 mv88e6xxx_reg_lock(chip); 6374 6375 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6376 if (err) 6377 goto err_unlock; 6378 6379 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6380 if (err) 6381 goto err_clear_trunk; 6382 6383 mv88e6xxx_reg_unlock(chip); 6384 return 0; 6385 6386 err_clear_trunk: 6387 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6388 err_unlock: 6389 mv88e6xxx_reg_unlock(chip); 6390 return err; 6391 } 6392 6393 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6394 struct dsa_lag lag) 6395 { 6396 struct mv88e6xxx_chip *chip = ds->priv; 6397 int err_sync, err_trunk; 6398 6399 mv88e6xxx_reg_lock(chip); 6400 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6401 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6402 mv88e6xxx_reg_unlock(chip); 6403 return err_sync ? : err_trunk; 6404 } 6405 6406 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6407 int port) 6408 { 6409 struct mv88e6xxx_chip *chip = ds->priv; 6410 int err; 6411 6412 mv88e6xxx_reg_lock(chip); 6413 err = mv88e6xxx_lag_sync_masks(ds); 6414 mv88e6xxx_reg_unlock(chip); 6415 return err; 6416 } 6417 6418 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6419 int port, struct dsa_lag lag, 6420 struct netdev_lag_upper_info *info) 6421 { 6422 struct mv88e6xxx_chip *chip = ds->priv; 6423 int err; 6424 6425 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6426 return -EOPNOTSUPP; 6427 6428 mv88e6xxx_reg_lock(chip); 6429 6430 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6431 if (err) 6432 goto unlock; 6433 6434 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6435 6436 unlock: 6437 mv88e6xxx_reg_unlock(chip); 6438 return err; 6439 } 6440 6441 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6442 int port, struct dsa_lag lag) 6443 { 6444 struct mv88e6xxx_chip *chip = ds->priv; 6445 int err_sync, err_pvt; 6446 6447 mv88e6xxx_reg_lock(chip); 6448 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6449 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6450 mv88e6xxx_reg_unlock(chip); 6451 return err_sync ? : err_pvt; 6452 } 6453 6454 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6455 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6456 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6457 .setup = mv88e6xxx_setup, 6458 .teardown = mv88e6xxx_teardown, 6459 .port_setup = mv88e6xxx_port_setup, 6460 .port_teardown = mv88e6xxx_port_teardown, 6461 .phylink_get_caps = mv88e6xxx_get_caps, 6462 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6463 .phylink_mac_config = mv88e6xxx_mac_config, 6464 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6465 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6466 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6467 .get_strings = mv88e6xxx_get_strings, 6468 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6469 .get_sset_count = mv88e6xxx_get_sset_count, 6470 .port_enable = mv88e6xxx_port_enable, 6471 .port_disable = mv88e6xxx_port_disable, 6472 .port_max_mtu = mv88e6xxx_get_max_mtu, 6473 .port_change_mtu = mv88e6xxx_change_mtu, 6474 .get_mac_eee = mv88e6xxx_get_mac_eee, 6475 .set_mac_eee = mv88e6xxx_set_mac_eee, 6476 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6477 .get_eeprom = mv88e6xxx_get_eeprom, 6478 .set_eeprom = mv88e6xxx_set_eeprom, 6479 .get_regs_len = mv88e6xxx_get_regs_len, 6480 .get_regs = mv88e6xxx_get_regs, 6481 .get_rxnfc = mv88e6xxx_get_rxnfc, 6482 .set_rxnfc = mv88e6xxx_set_rxnfc, 6483 .set_ageing_time = mv88e6xxx_set_ageing_time, 6484 .port_bridge_join = mv88e6xxx_port_bridge_join, 6485 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6486 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6487 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6488 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6489 .port_fast_age = mv88e6xxx_port_fast_age, 6490 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6491 .port_vlan_add = mv88e6xxx_port_vlan_add, 6492 .port_vlan_del = mv88e6xxx_port_vlan_del, 6493 .port_fdb_add = mv88e6xxx_port_fdb_add, 6494 .port_fdb_del = mv88e6xxx_port_fdb_del, 6495 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6496 .port_mdb_add = mv88e6xxx_port_mdb_add, 6497 .port_mdb_del = mv88e6xxx_port_mdb_del, 6498 .port_mirror_add = mv88e6xxx_port_mirror_add, 6499 .port_mirror_del = mv88e6xxx_port_mirror_del, 6500 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6501 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6502 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6503 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6504 .port_txtstamp = mv88e6xxx_port_txtstamp, 6505 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6506 .get_ts_info = mv88e6xxx_get_ts_info, 6507 .devlink_param_get = mv88e6xxx_devlink_param_get, 6508 .devlink_param_set = mv88e6xxx_devlink_param_set, 6509 .devlink_info_get = mv88e6xxx_devlink_info_get, 6510 .port_lag_change = mv88e6xxx_port_lag_change, 6511 .port_lag_join = mv88e6xxx_port_lag_join, 6512 .port_lag_leave = mv88e6xxx_port_lag_leave, 6513 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6514 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6515 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6516 }; 6517 6518 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6519 { 6520 struct device *dev = chip->dev; 6521 struct dsa_switch *ds; 6522 6523 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6524 if (!ds) 6525 return -ENOMEM; 6526 6527 ds->dev = dev; 6528 ds->num_ports = mv88e6xxx_num_ports(chip); 6529 ds->priv = chip; 6530 ds->dev = dev; 6531 ds->ops = &mv88e6xxx_switch_ops; 6532 ds->ageing_time_min = chip->info->age_time_coeff; 6533 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6534 6535 /* Some chips support up to 32, but that requires enabling the 6536 * 5-bit port mode, which we do not support. 640k^W16 ought to 6537 * be enough for anyone. 6538 */ 6539 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6540 6541 dev_set_drvdata(dev, ds); 6542 6543 return dsa_register_switch(ds); 6544 } 6545 6546 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6547 { 6548 dsa_unregister_switch(chip->ds); 6549 } 6550 6551 static const void *pdata_device_get_match_data(struct device *dev) 6552 { 6553 const struct of_device_id *matches = dev->driver->of_match_table; 6554 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6555 6556 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6557 matches++) { 6558 if (!strcmp(pdata->compatible, matches->compatible)) 6559 return matches->data; 6560 } 6561 return NULL; 6562 } 6563 6564 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6565 * would be lost after a power cycle so prevent it to be suspended. 6566 */ 6567 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6568 { 6569 return -EOPNOTSUPP; 6570 } 6571 6572 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6573 { 6574 return 0; 6575 } 6576 6577 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6578 6579 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6580 { 6581 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6582 const struct mv88e6xxx_info *compat_info = NULL; 6583 struct device *dev = &mdiodev->dev; 6584 struct device_node *np = dev->of_node; 6585 struct mv88e6xxx_chip *chip; 6586 int port; 6587 int err; 6588 6589 if (!np && !pdata) 6590 return -EINVAL; 6591 6592 if (np) 6593 compat_info = of_device_get_match_data(dev); 6594 6595 if (pdata) { 6596 compat_info = pdata_device_get_match_data(dev); 6597 6598 if (!pdata->netdev) 6599 return -EINVAL; 6600 6601 for (port = 0; port < DSA_MAX_PORTS; port++) { 6602 if (!(pdata->enabled_ports & (1 << port))) 6603 continue; 6604 if (strcmp(pdata->cd.port_names[port], "cpu")) 6605 continue; 6606 pdata->cd.netdev[port] = &pdata->netdev->dev; 6607 break; 6608 } 6609 } 6610 6611 if (!compat_info) 6612 return -EINVAL; 6613 6614 chip = mv88e6xxx_alloc_chip(dev); 6615 if (!chip) { 6616 err = -ENOMEM; 6617 goto out; 6618 } 6619 6620 chip->info = compat_info; 6621 6622 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6623 if (err) 6624 goto out; 6625 6626 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6627 if (IS_ERR(chip->reset)) { 6628 err = PTR_ERR(chip->reset); 6629 goto out; 6630 } 6631 if (chip->reset) 6632 usleep_range(1000, 2000); 6633 6634 err = mv88e6xxx_detect(chip); 6635 if (err) 6636 goto out; 6637 6638 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6639 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6640 else 6641 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6642 6643 mv88e6xxx_phy_init(chip); 6644 6645 if (chip->info->ops->get_eeprom) { 6646 if (np) 6647 of_property_read_u32(np, "eeprom-length", 6648 &chip->eeprom_len); 6649 else 6650 chip->eeprom_len = pdata->eeprom_len; 6651 } 6652 6653 mv88e6xxx_reg_lock(chip); 6654 err = mv88e6xxx_switch_reset(chip); 6655 mv88e6xxx_reg_unlock(chip); 6656 if (err) 6657 goto out; 6658 6659 if (np) { 6660 chip->irq = of_irq_get(np, 0); 6661 if (chip->irq == -EPROBE_DEFER) { 6662 err = chip->irq; 6663 goto out; 6664 } 6665 } 6666 6667 if (pdata) 6668 chip->irq = pdata->irq; 6669 6670 /* Has to be performed before the MDIO bus is created, because 6671 * the PHYs will link their interrupts to these interrupt 6672 * controllers 6673 */ 6674 mv88e6xxx_reg_lock(chip); 6675 if (chip->irq > 0) 6676 err = mv88e6xxx_g1_irq_setup(chip); 6677 else 6678 err = mv88e6xxx_irq_poll_setup(chip); 6679 mv88e6xxx_reg_unlock(chip); 6680 6681 if (err) 6682 goto out; 6683 6684 if (chip->info->g2_irqs > 0) { 6685 err = mv88e6xxx_g2_irq_setup(chip); 6686 if (err) 6687 goto out_g1_irq; 6688 } 6689 6690 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6691 if (err) 6692 goto out_g2_irq; 6693 6694 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6695 if (err) 6696 goto out_g1_atu_prob_irq; 6697 6698 err = mv88e6xxx_mdios_register(chip, np); 6699 if (err) 6700 goto out_g1_vtu_prob_irq; 6701 6702 err = mv88e6xxx_register_switch(chip); 6703 if (err) 6704 goto out_mdio; 6705 6706 return 0; 6707 6708 out_mdio: 6709 mv88e6xxx_mdios_unregister(chip); 6710 out_g1_vtu_prob_irq: 6711 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6712 out_g1_atu_prob_irq: 6713 mv88e6xxx_g1_atu_prob_irq_free(chip); 6714 out_g2_irq: 6715 if (chip->info->g2_irqs > 0) 6716 mv88e6xxx_g2_irq_free(chip); 6717 out_g1_irq: 6718 if (chip->irq > 0) 6719 mv88e6xxx_g1_irq_free(chip); 6720 else 6721 mv88e6xxx_irq_poll_free(chip); 6722 out: 6723 if (pdata) 6724 dev_put(pdata->netdev); 6725 6726 return err; 6727 } 6728 6729 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6730 { 6731 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6732 struct mv88e6xxx_chip *chip; 6733 6734 if (!ds) 6735 return; 6736 6737 chip = ds->priv; 6738 6739 if (chip->info->ptp_support) { 6740 mv88e6xxx_hwtstamp_free(chip); 6741 mv88e6xxx_ptp_free(chip); 6742 } 6743 6744 mv88e6xxx_phy_destroy(chip); 6745 mv88e6xxx_unregister_switch(chip); 6746 mv88e6xxx_mdios_unregister(chip); 6747 6748 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6749 mv88e6xxx_g1_atu_prob_irq_free(chip); 6750 6751 if (chip->info->g2_irqs > 0) 6752 mv88e6xxx_g2_irq_free(chip); 6753 6754 if (chip->irq > 0) 6755 mv88e6xxx_g1_irq_free(chip); 6756 else 6757 mv88e6xxx_irq_poll_free(chip); 6758 6759 dev_set_drvdata(&mdiodev->dev, NULL); 6760 } 6761 6762 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6763 { 6764 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6765 6766 if (!ds) 6767 return; 6768 6769 dsa_switch_shutdown(ds); 6770 6771 dev_set_drvdata(&mdiodev->dev, NULL); 6772 } 6773 6774 static const struct of_device_id mv88e6xxx_of_match[] = { 6775 { 6776 .compatible = "marvell,mv88e6085", 6777 .data = &mv88e6xxx_table[MV88E6085], 6778 }, 6779 { 6780 .compatible = "marvell,mv88e6190", 6781 .data = &mv88e6xxx_table[MV88E6190], 6782 }, 6783 { 6784 .compatible = "marvell,mv88e6250", 6785 .data = &mv88e6xxx_table[MV88E6250], 6786 }, 6787 { /* sentinel */ }, 6788 }; 6789 6790 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6791 6792 static struct mdio_driver mv88e6xxx_driver = { 6793 .probe = mv88e6xxx_probe, 6794 .remove = mv88e6xxx_remove, 6795 .shutdown = mv88e6xxx_shutdown, 6796 .mdiodrv.driver = { 6797 .name = "mv88e6085", 6798 .of_match_table = mv88e6xxx_of_match, 6799 .pm = &mv88e6xxx_pm_ops, 6800 }, 6801 }; 6802 6803 mdio_module_driver(mv88e6xxx_driver); 6804 6805 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6806 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6807 MODULE_LICENSE("GPL"); 6808