1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 }; 23 24 #define NUM_TRGMII_CTRL 5 25 26 #define TRGMII_BASE(x) (0x10000 + (x)) 27 28 /* Registers to ethsys access */ 29 #define ETHSYS_CLKCFG0 0x2c 30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 31 32 #define SYSC_REG_RSTCTRL 0x34 33 #define RESET_MCM BIT(2) 34 35 /* Registers to mac forward control for unknown frames */ 36 #define MT7530_MFC 0x10 37 #define BC_FFP(x) (((x) & 0xff) << 24) 38 #define BC_FFP_MASK BC_FFP(~0) 39 #define UNM_FFP(x) (((x) & 0xff) << 16) 40 #define UNM_FFP_MASK UNM_FFP(~0) 41 #define UNU_FFP(x) (((x) & 0xff) << 8) 42 #define UNU_FFP_MASK UNU_FFP(~0) 43 #define CPU_EN BIT(7) 44 #define CPU_PORT(x) ((x) << 4) 45 #define CPU_MASK (0xf << 4) 46 #define MIRROR_EN BIT(3) 47 #define MIRROR_PORT(x) ((x) & 0x7) 48 #define MIRROR_MASK 0x7 49 50 /* Registers for CPU forward control */ 51 #define MT7531_CFC 0x4 52 #define MT7531_MIRROR_EN BIT(19) 53 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 54 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 55 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 57 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 58 59 #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 60 MT7531_CFC : MT7530_MFC) 61 #define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 62 MT7531_MIRROR_EN : MIRROR_EN) 63 #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 64 MT7531_MIRROR_MASK : MIRROR_MASK) 65 66 /* Registers for BPDU and PAE frame control*/ 67 #define MT753X_BPC 0x24 68 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 69 70 /* Register for :03 and :0E MAC DA frame control */ 71 #define MT753X_RGAC2 0x2c 72 #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) 73 #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) 74 75 enum mt753x_bpdu_port_fw { 76 MT753X_BPDU_FOLLOW_MFC, 77 MT753X_BPDU_CPU_EXCLUDE = 4, 78 MT753X_BPDU_CPU_INCLUDE = 5, 79 MT753X_BPDU_CPU_ONLY = 6, 80 MT753X_BPDU_DROP = 7, 81 }; 82 83 /* Registers for address table access */ 84 #define MT7530_ATA1 0x74 85 #define STATIC_EMP 0 86 #define STATIC_ENT 3 87 #define MT7530_ATA2 0x78 88 #define ATA2_IVL BIT(15) 89 #define ATA2_FID(x) (((x) & 0x7) << 12) 90 91 /* Register for address table write data */ 92 #define MT7530_ATWD 0x7c 93 94 /* Register for address table control */ 95 #define MT7530_ATC 0x80 96 #define ATC_HASH (((x) & 0xfff) << 16) 97 #define ATC_BUSY BIT(15) 98 #define ATC_SRCH_END BIT(14) 99 #define ATC_SRCH_HIT BIT(13) 100 #define ATC_INVALID BIT(12) 101 #define ATC_MAT(x) (((x) & 0xf) << 8) 102 #define ATC_MAT_MACTAB ATC_MAT(0) 103 104 enum mt7530_fdb_cmd { 105 MT7530_FDB_READ = 0, 106 MT7530_FDB_WRITE = 1, 107 MT7530_FDB_FLUSH = 2, 108 MT7530_FDB_START = 4, 109 MT7530_FDB_NEXT = 5, 110 }; 111 112 /* Registers for table search read address */ 113 #define MT7530_TSRA1 0x84 114 #define MAC_BYTE_0 24 115 #define MAC_BYTE_1 16 116 #define MAC_BYTE_2 8 117 #define MAC_BYTE_3 0 118 #define MAC_BYTE_MASK 0xff 119 120 #define MT7530_TSRA2 0x88 121 #define MAC_BYTE_4 24 122 #define MAC_BYTE_5 16 123 #define CVID 0 124 #define CVID_MASK 0xfff 125 126 #define MT7530_ATRD 0x8C 127 #define AGE_TIMER 24 128 #define AGE_TIMER_MASK 0xff 129 #define PORT_MAP 4 130 #define PORT_MAP_MASK 0xff 131 #define ENT_STATUS 2 132 #define ENT_STATUS_MASK 0x3 133 134 /* Register for vlan table control */ 135 #define MT7530_VTCR 0x90 136 #define VTCR_BUSY BIT(31) 137 #define VTCR_INVALID BIT(16) 138 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 139 #define VTCR_VID ((x) & 0xfff) 140 141 enum mt7530_vlan_cmd { 142 /* Read/Write the specified VID entry from VAWD register based 143 * on VID. 144 */ 145 MT7530_VTCR_RD_VID = 0, 146 MT7530_VTCR_WR_VID = 1, 147 }; 148 149 /* Register for setup vlan and acl write data */ 150 #define MT7530_VAWD1 0x94 151 #define PORT_STAG BIT(31) 152 /* Independent VLAN Learning */ 153 #define IVL_MAC BIT(30) 154 /* Egress Tag Consistent */ 155 #define EG_CON BIT(29) 156 /* Per VLAN Egress Tag Control */ 157 #define VTAG_EN BIT(28) 158 /* VLAN Member Control */ 159 #define PORT_MEM(x) (((x) & 0xff) << 16) 160 /* Filter ID */ 161 #define FID(x) (((x) & 0x7) << 1) 162 /* VLAN Entry Valid */ 163 #define VLAN_VALID BIT(0) 164 #define PORT_MEM_SHFT 16 165 #define PORT_MEM_MASK 0xff 166 167 enum mt7530_fid { 168 FID_STANDALONE = 0, 169 FID_BRIDGED = 1, 170 }; 171 172 #define MT7530_VAWD2 0x98 173 /* Egress Tag Control */ 174 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 175 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 176 177 enum mt7530_vlan_egress_attr { 178 MT7530_VLAN_EGRESS_UNTAG = 0, 179 MT7530_VLAN_EGRESS_TAG = 2, 180 MT7530_VLAN_EGRESS_STACK = 3, 181 }; 182 183 /* Register for address age control */ 184 #define MT7530_AAC 0xa0 185 /* Disable ageing */ 186 #define AGE_DIS BIT(20) 187 /* Age count */ 188 #define AGE_CNT_MASK GENMASK(19, 12) 189 #define AGE_CNT_MAX 0xff 190 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 191 /* Age unit */ 192 #define AGE_UNIT_MASK GENMASK(11, 0) 193 #define AGE_UNIT_MAX 0xfff 194 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 195 196 /* Register for port STP state control */ 197 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 198 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 199 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 200 201 enum mt7530_stp_state { 202 MT7530_STP_DISABLED = 0, 203 MT7530_STP_BLOCKING = 1, 204 MT7530_STP_LISTENING = 1, 205 MT7530_STP_LEARNING = 2, 206 MT7530_STP_FORWARDING = 3 207 }; 208 209 /* Register for port control */ 210 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 211 #define PORT_TX_MIR BIT(9) 212 #define PORT_RX_MIR BIT(8) 213 #define PORT_VLAN(x) ((x) & 0x3) 214 215 enum mt7530_port_mode { 216 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 217 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 218 219 /* Fallback Mode: Forward received frames with ingress ports that do 220 * not belong to the VLAN member. Frames whose VID is not listed on 221 * the VLAN table are forwarded by the PCR_MATRIX members. 222 */ 223 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 224 225 /* Security Mode: Discard any frame due to ingress membership 226 * violation or VID missed on the VLAN table. 227 */ 228 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 229 }; 230 231 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 232 #define PORT_PRI(x) (((x) & 0x7) << 24) 233 #define EG_TAG(x) (((x) & 0x3) << 28) 234 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 235 #define PCR_MATRIX_CLR PCR_MATRIX(0) 236 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 237 238 /* Register for port security control */ 239 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 240 #define SA_DIS BIT(4) 241 242 /* Register for port vlan control */ 243 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 244 #define PORT_SPEC_TAG BIT(5) 245 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 246 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 247 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 248 #define VLAN_ATTR_MASK VLAN_ATTR(3) 249 #define ACC_FRM_MASK GENMASK(1, 0) 250 251 enum mt7530_vlan_port_eg_tag { 252 MT7530_VLAN_EG_DISABLED = 0, 253 MT7530_VLAN_EG_CONSISTENT = 1, 254 }; 255 256 enum mt7530_vlan_port_attr { 257 MT7530_VLAN_USER = 0, 258 MT7530_VLAN_TRANSPARENT = 3, 259 }; 260 261 enum mt7530_vlan_port_acc_frm { 262 MT7530_VLAN_ACC_ALL = 0, 263 MT7530_VLAN_ACC_TAGGED = 1, 264 MT7530_VLAN_ACC_UNTAGGED = 2, 265 }; 266 267 #define STAG_VPID (((x) & 0xffff) << 16) 268 269 /* Register for port port-and-protocol based vlan 1 control */ 270 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 271 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 272 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 273 #define G0_PORT_VID_DEF G0_PORT_VID(0) 274 275 /* Register for port MAC control register */ 276 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 277 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 278 #define PMCR_EXT_PHY BIT(17) 279 #define PMCR_MAC_MODE BIT(16) 280 #define PMCR_FORCE_MODE BIT(15) 281 #define PMCR_TX_EN BIT(14) 282 #define PMCR_RX_EN BIT(13) 283 #define PMCR_BACKOFF_EN BIT(9) 284 #define PMCR_BACKPR_EN BIT(8) 285 #define PMCR_FORCE_EEE1G BIT(7) 286 #define PMCR_FORCE_EEE100 BIT(6) 287 #define PMCR_TX_FC_EN BIT(5) 288 #define PMCR_RX_FC_EN BIT(4) 289 #define PMCR_FORCE_SPEED_1000 BIT(3) 290 #define PMCR_FORCE_SPEED_100 BIT(2) 291 #define PMCR_FORCE_FDX BIT(1) 292 #define PMCR_FORCE_LNK BIT(0) 293 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 294 PMCR_FORCE_SPEED_1000) 295 #define MT7531_FORCE_LNK BIT(31) 296 #define MT7531_FORCE_SPD BIT(30) 297 #define MT7531_FORCE_DPX BIT(29) 298 #define MT7531_FORCE_RX_FC BIT(28) 299 #define MT7531_FORCE_TX_FC BIT(27) 300 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 301 MT7531_FORCE_SPD | \ 302 MT7531_FORCE_DPX | \ 303 MT7531_FORCE_RX_FC | \ 304 MT7531_FORCE_TX_FC) 305 #define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ 306 MT7531_FORCE_MODE : PMCR_FORCE_MODE) 307 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 308 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 309 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 310 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ 311 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) 312 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ 313 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 314 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 315 PMCR_TX_EN | PMCR_RX_EN | \ 316 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 317 PMCR_FORCE_SPEED_1000 | \ 318 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 319 320 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) 321 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) 322 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) 323 #define LPI_THRESH_MASK GENMASK(15, 4) 324 #define LPI_THRESH_SHT 4 325 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) 326 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) 327 #define LPI_MODE_EN BIT(0) 328 329 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 330 #define PMSR_EEE1G BIT(7) 331 #define PMSR_EEE100M BIT(6) 332 #define PMSR_RX_FC BIT(5) 333 #define PMSR_TX_FC BIT(4) 334 #define PMSR_SPEED_1000 BIT(3) 335 #define PMSR_SPEED_100 BIT(2) 336 #define PMSR_SPEED_10 0x00 337 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 338 #define PMSR_DPX BIT(1) 339 #define PMSR_LINK BIT(0) 340 341 /* Register for port debug count */ 342 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 343 #define MT7531_DIS_CLR BIT(31) 344 345 #define MT7530_GMACCR 0x30e0 346 #define MAX_RX_JUMBO(x) ((x) << 2) 347 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 348 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 349 #define MAX_RX_PKT_LEN_1522 0x0 350 #define MAX_RX_PKT_LEN_1536 0x1 351 #define MAX_RX_PKT_LEN_1552 0x2 352 #define MAX_RX_PKT_LEN_JUMBO 0x3 353 354 /* Register for MIB */ 355 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 356 #define MT7530_MIB_CCR 0x4fe0 357 #define CCR_MIB_ENABLE BIT(31) 358 #define CCR_RX_OCT_CNT_GOOD BIT(7) 359 #define CCR_RX_OCT_CNT_BAD BIT(6) 360 #define CCR_TX_OCT_CNT_GOOD BIT(5) 361 #define CCR_TX_OCT_CNT_BAD BIT(4) 362 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 363 CCR_RX_OCT_CNT_BAD | \ 364 CCR_TX_OCT_CNT_GOOD | \ 365 CCR_TX_OCT_CNT_BAD) 366 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 367 CCR_RX_OCT_CNT_GOOD | \ 368 CCR_RX_OCT_CNT_BAD | \ 369 CCR_TX_OCT_CNT_GOOD | \ 370 CCR_TX_OCT_CNT_BAD) 371 372 /* MT7531 SGMII register group */ 373 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 374 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 375 376 /* Register for system reset */ 377 #define MT7530_SYS_CTRL 0x7000 378 #define SYS_CTRL_PHY_RST BIT(2) 379 #define SYS_CTRL_SW_RST BIT(1) 380 #define SYS_CTRL_REG_RST BIT(0) 381 382 /* Register for system interrupt */ 383 #define MT7530_SYS_INT_EN 0x7008 384 385 /* Register for system interrupt status */ 386 #define MT7530_SYS_INT_STS 0x700c 387 388 /* Register for PHY Indirect Access Control */ 389 #define MT7531_PHY_IAC 0x701C 390 #define MT7531_PHY_ACS_ST BIT(31) 391 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 392 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 393 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 394 #define MT7531_MDIO_ST_MASK (0x3 << 16) 395 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 396 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 397 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 398 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 399 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 400 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 401 402 enum mt7531_phy_iac_cmd { 403 MT7531_MDIO_ADDR = 0, 404 MT7531_MDIO_WRITE = 1, 405 MT7531_MDIO_READ = 2, 406 MT7531_MDIO_READ_CL45 = 3, 407 }; 408 409 /* MDIO_ST: MDIO start field */ 410 enum mt7531_mdio_st { 411 MT7531_MDIO_ST_CL45 = 0, 412 MT7531_MDIO_ST_CL22 = 1, 413 }; 414 415 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 416 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 417 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 418 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 419 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 420 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 421 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 422 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 423 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 424 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 425 426 /* Register for RGMII clock phase */ 427 #define MT7531_CLKGEN_CTRL 0x7500 428 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 429 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 430 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 431 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 432 #define RXCLK_NO_DELAY BIT(5) 433 #define TXCLK_NO_REVERSE BIT(4) 434 #define GP_MODE(x) (((x) & 0x3) << 1) 435 #define GP_MODE_MASK GENMASK(2, 1) 436 #define GP_CLK_EN BIT(0) 437 438 enum mt7531_gp_mode { 439 MT7531_GP_MODE_RGMII = 0, 440 MT7531_GP_MODE_MII = 1, 441 MT7531_GP_MODE_REV_MII = 2 442 }; 443 444 enum mt7531_clk_skew { 445 MT7531_CLK_SKEW_NO_CHG = 0, 446 MT7531_CLK_SKEW_DLY_100PPS = 1, 447 MT7531_CLK_SKEW_DLY_200PPS = 2, 448 MT7531_CLK_SKEW_REVERSE = 3, 449 }; 450 451 /* Register for hw trap status */ 452 #define MT7530_HWTRAP 0x7800 453 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 454 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 455 #define HWTRAP_XTAL_40MHZ (BIT(10)) 456 #define HWTRAP_XTAL_20MHZ (BIT(9)) 457 458 #define MT7531_HWTRAP 0x7800 459 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 460 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 461 #define HWTRAP_XTAL_FSEL_40MHZ 0 462 /* Unique fields of (M)HWSTRAP for MT7531 */ 463 #define XTAL_FSEL_S 7 464 #define XTAL_FSEL_M BIT(7) 465 #define PHY_EN BIT(6) 466 #define CHG_STRAP BIT(8) 467 468 /* Register for hw trap modification */ 469 #define MT7530_MHWTRAP 0x7804 470 #define MHWTRAP_PHY0_SEL BIT(20) 471 #define MHWTRAP_MANUAL BIT(16) 472 #define MHWTRAP_P5_MAC_SEL BIT(13) 473 #define MHWTRAP_P6_DIS BIT(8) 474 #define MHWTRAP_P5_RGMII_MODE BIT(7) 475 #define MHWTRAP_P5_DIS BIT(6) 476 #define MHWTRAP_PHY_ACCESS BIT(5) 477 478 /* Register for TOP signal control */ 479 #define MT7530_TOP_SIG_CTRL 0x7808 480 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 481 482 #define MT7531_TOP_SIG_SR 0x780c 483 #define PAD_DUAL_SGMII_EN BIT(1) 484 #define PAD_MCM_SMI_EN BIT(0) 485 486 #define MT7530_IO_DRV_CR 0x7810 487 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 488 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 489 490 #define MT7531_CHIP_REV 0x781C 491 492 #define MT7531_PLLGP_EN 0x7820 493 #define EN_COREPLL BIT(2) 494 #define SW_CLKSW BIT(1) 495 #define SW_PLLGP BIT(0) 496 497 #define MT7530_P6ECR 0x7830 498 #define P6_INTF_MODE_MASK 0x3 499 #define P6_INTF_MODE(x) ((x) & 0x3) 500 501 #define MT7531_PLLGP_CR0 0x78a8 502 #define RG_COREPLL_EN BIT(22) 503 #define RG_COREPLL_POSDIV_S 23 504 #define RG_COREPLL_POSDIV_M 0x3800000 505 #define RG_COREPLL_SDM_PCW_S 1 506 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 507 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 508 509 /* Registers for RGMII and SGMII PLL clock */ 510 #define MT7531_ANA_PLLGP_CR2 0x78b0 511 #define MT7531_ANA_PLLGP_CR5 0x78bc 512 513 /* Registers for TRGMII on the both side */ 514 #define MT7530_TRGMII_RCK_CTRL 0x7a00 515 #define RX_RST BIT(31) 516 #define RXC_DQSISEL BIT(30) 517 #define DQSI1_TAP_MASK (0x7f << 8) 518 #define DQSI0_TAP_MASK 0x7f 519 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 520 #define DQSI0_TAP(x) ((x) & 0x7f) 521 522 #define MT7530_TRGMII_RCK_RTT 0x7a04 523 #define DQS1_GATE BIT(31) 524 #define DQS0_GATE BIT(30) 525 526 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 527 #define BSLIP_EN BIT(31) 528 #define EDGE_CHK BIT(30) 529 #define RD_TAP_MASK 0x7f 530 #define RD_TAP(x) ((x) & 0x7f) 531 532 #define MT7530_TRGMII_TXCTRL 0x7a40 533 #define TRAIN_TXEN BIT(31) 534 #define TXC_INV BIT(30) 535 #define TX_RST BIT(28) 536 537 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 538 #define TD_DM_DRVP(x) ((x) & 0xf) 539 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 540 541 #define MT7530_TRGMII_TCK_CTRL 0x7a78 542 #define TCK_TAP(x) (((x) & 0xf) << 8) 543 544 #define MT7530_P5RGMIIRXCR 0x7b00 545 #define CSR_RGMII_EDGE_ALIGN BIT(8) 546 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 547 548 #define MT7530_P5RGMIITXCR 0x7b04 549 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 550 551 /* Registers for GPIO mode */ 552 #define MT7531_GPIO_MODE0 0x7c0c 553 #define MT7531_GPIO0_MASK GENMASK(3, 0) 554 #define MT7531_GPIO0_INTERRUPT 1 555 556 #define MT7531_GPIO_MODE1 0x7c10 557 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 558 #define MT7531_EXT_P_MDC_11 (2 << 12) 559 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 560 #define MT7531_EXT_P_MDIO_12 (2 << 16) 561 562 /* Registers for LED GPIO control (MT7530 only) 563 * All registers follow this pattern: 564 * [ 2: 0] port 0 565 * [ 6: 4] port 1 566 * [10: 8] port 2 567 * [14:12] port 3 568 * [18:16] port 4 569 */ 570 571 /* LED enable, 0: Disable, 1: Enable (Default) */ 572 #define MT7530_LED_EN 0x7d00 573 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 574 #define MT7530_LED_IO_MODE 0x7d04 575 /* GPIO direction, 0: Input, 1: Output */ 576 #define MT7530_LED_GPIO_DIR 0x7d10 577 /* GPIO output enable, 0: Disable, 1: Enable */ 578 #define MT7530_LED_GPIO_OE 0x7d14 579 /* GPIO value, 0: Low, 1: High */ 580 #define MT7530_LED_GPIO_DATA 0x7d18 581 582 #define MT7530_CREV 0x7ffc 583 #define CHIP_NAME_SHIFT 16 584 #define MT7530_ID 0x7530 585 586 #define MT7531_CREV 0x781C 587 #define CHIP_REV_M 0x0f 588 #define MT7531_ID 0x7531 589 590 /* Registers for core PLL access through mmd indirect */ 591 #define CORE_PLL_GROUP2 0x401 592 #define RG_SYSPLL_EN_NORMAL BIT(15) 593 #define RG_SYSPLL_VODEN BIT(14) 594 #define RG_SYSPLL_LF BIT(13) 595 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 596 #define RG_SYSPLL_LVROD_EN BIT(10) 597 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 598 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 599 #define RG_SYSPLL_FBKSEL BIT(4) 600 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 601 602 #define CORE_PLL_GROUP4 0x403 603 #define RG_SYSPLL_DDSFBK_EN BIT(12) 604 #define RG_SYSPLL_BIAS_EN BIT(11) 605 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 606 #define MT7531_PHY_PLL_OFF BIT(5) 607 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 608 609 #define MT753X_CTRL_PHY_ADDR 0 610 611 #define CORE_PLL_GROUP5 0x404 612 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 613 614 #define CORE_PLL_GROUP6 0x405 615 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 616 617 #define CORE_PLL_GROUP7 0x406 618 #define RG_LCDDS_PWDB BIT(15) 619 #define RG_LCDDS_ISO_EN BIT(13) 620 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 621 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 622 623 #define CORE_PLL_GROUP10 0x409 624 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 625 626 #define CORE_PLL_GROUP11 0x40a 627 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 628 629 #define CORE_GSWPLL_GRP1 0x40d 630 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 631 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 632 #define RG_GSWPLL_EN_PRE BIT(11) 633 #define RG_GSWPLL_FBKSEL BIT(10) 634 #define RG_GSWPLL_BP BIT(9) 635 #define RG_GSWPLL_BR BIT(8) 636 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 637 638 #define CORE_GSWPLL_GRP2 0x40e 639 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 640 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 641 642 #define CORE_TRGMII_GSW_CLK_CG 0x410 643 #define REG_GSWCK_EN BIT(0) 644 #define REG_TRGMIICK_EN BIT(1) 645 646 #define MIB_DESC(_s, _o, _n) \ 647 { \ 648 .size = (_s), \ 649 .offset = (_o), \ 650 .name = (_n), \ 651 } 652 653 struct mt7530_mib_desc { 654 unsigned int size; 655 unsigned int offset; 656 const char *name; 657 }; 658 659 struct mt7530_fdb { 660 u16 vid; 661 u8 port_mask; 662 u8 aging; 663 u8 mac[6]; 664 bool noarp; 665 }; 666 667 /* struct mt7530_port - This is the main data structure for holding the state 668 * of the port. 669 * @enable: The status used for show port is enabled or not. 670 * @pm: The matrix used to show all connections with the port. 671 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 672 * untagged frames will be assigned to the related VLAN. 673 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 674 */ 675 struct mt7530_port { 676 bool enable; 677 u32 pm; 678 u16 pvid; 679 struct phylink_pcs *sgmii_pcs; 680 }; 681 682 /* Port 5 interface select definitions */ 683 enum p5_interface_select { 684 P5_DISABLED = 0, 685 P5_INTF_SEL_PHY_P0, 686 P5_INTF_SEL_PHY_P4, 687 P5_INTF_SEL_GMAC5, 688 P5_INTF_SEL_GMAC5_SGMII, 689 }; 690 691 struct mt7530_priv; 692 693 struct mt753x_pcs { 694 struct phylink_pcs pcs; 695 struct mt7530_priv *priv; 696 int port; 697 }; 698 699 /* struct mt753x_info - This is the main data structure for holding the specific 700 * part for each supported device 701 * @sw_setup: Holding the handler to a device initialization 702 * @phy_read_c22: Holding the way reading PHY port using C22 703 * @phy_write_c22: Holding the way writing PHY port using C22 704 * @phy_read_c45: Holding the way reading PHY port using C45 705 * @phy_write_c45: Holding the way writing PHY port using C45 706 * @pad_setup: Holding the way setting up the bus pad for a certain 707 * MAC port 708 * @phy_mode_supported: Check if the PHY type is being supported on a certain 709 * port 710 * @mac_port_validate: Holding the way to set addition validate type for a 711 * certan MAC port 712 * @mac_port_config: Holding the way setting up the PHY attribute to a 713 * certain MAC port 714 */ 715 struct mt753x_info { 716 enum mt753x_id id; 717 718 const struct phylink_pcs_ops *pcs_ops; 719 720 int (*sw_setup)(struct dsa_switch *ds); 721 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 722 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 723 u16 val); 724 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 725 int regnum); 726 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 727 int regnum, u16 val); 728 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); 729 int (*cpu_port_config)(struct dsa_switch *ds, int port); 730 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 731 struct phylink_config *config); 732 void (*mac_port_validate)(struct dsa_switch *ds, int port, 733 phy_interface_t interface, 734 unsigned long *supported); 735 int (*mac_port_config)(struct dsa_switch *ds, int port, 736 unsigned int mode, 737 phy_interface_t interface); 738 }; 739 740 /* struct mt7530_priv - This is the main data structure for holding the state 741 * of the driver 742 * @dev: The device pointer 743 * @ds: The pointer to the dsa core structure 744 * @bus: The bus used for the device and built-in PHY 745 * @regmap: The regmap instance representing all switch registers 746 * @rstc: The pointer to reset control used by MCM 747 * @core_pwr: The power supplied into the core 748 * @io_pwr: The power supplied into the I/O 749 * @reset: The descriptor for GPIO line tied to its reset pin 750 * @mcm: Flag for distinguishing if standalone IC or module 751 * coupling 752 * @ports: Holding the state among ports 753 * @reg_mutex: The lock for protecting among process accessing 754 * registers 755 * @p6_interface Holding the current port 6 interface 756 * @p5_intf_sel: Holding the current port 5 interface select 757 * @irq: IRQ number of the switch 758 * @irq_domain: IRQ domain of the switch irq_chip 759 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN 760 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 761 */ 762 struct mt7530_priv { 763 struct device *dev; 764 struct dsa_switch *ds; 765 struct mii_bus *bus; 766 struct regmap *regmap; 767 struct reset_control *rstc; 768 struct regulator *core_pwr; 769 struct regulator *io_pwr; 770 struct gpio_desc *reset; 771 const struct mt753x_info *info; 772 unsigned int id; 773 bool mcm; 774 phy_interface_t p6_interface; 775 phy_interface_t p5_interface; 776 unsigned int p5_intf_sel; 777 u8 mirror_rx; 778 u8 mirror_tx; 779 struct mt7530_port ports[MT7530_NUM_PORTS]; 780 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 781 /* protect among processes for registers access*/ 782 struct mutex reg_mutex; 783 int irq; 784 struct irq_domain *irq_domain; 785 u32 irq_enable; 786 int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); 787 }; 788 789 struct mt7530_hw_vlan_entry { 790 int port; 791 u8 old_members; 792 bool untagged; 793 }; 794 795 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 796 int port, bool untagged) 797 { 798 e->port = port; 799 e->untagged = untagged; 800 } 801 802 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 803 struct mt7530_hw_vlan_entry *); 804 805 struct mt7530_hw_stats { 806 const char *string; 807 u16 reg; 808 u8 sizeof_stat; 809 }; 810 811 struct mt7530_dummy_poll { 812 struct mt7530_priv *priv; 813 u32 reg; 814 }; 815 816 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 817 struct mt7530_priv *priv, u32 reg) 818 { 819 p->priv = priv; 820 p->reg = reg; 821 } 822 823 int mt7530_probe_common(struct mt7530_priv *priv); 824 void mt7530_remove_common(struct mt7530_priv *priv); 825 826 extern const struct dsa_switch_ops mt7530_switch_ops; 827 extern const struct mt753x_info mt753x_table[]; 828 829 #endif /* __MT7530_H */ 830