1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_CPU_PORT 6 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 }; 22 23 #define NUM_TRGMII_CTRL 5 24 25 #define TRGMII_BASE(x) (0x10000 + (x)) 26 27 /* Registers to ethsys access */ 28 #define ETHSYS_CLKCFG0 0x2c 29 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 30 31 #define SYSC_REG_RSTCTRL 0x34 32 #define RESET_MCM BIT(2) 33 34 /* Registers to mac forward control for unknown frames */ 35 #define MT7530_MFC 0x10 36 #define BC_FFP(x) (((x) & 0xff) << 24) 37 #define BC_FFP_MASK BC_FFP(~0) 38 #define UNM_FFP(x) (((x) & 0xff) << 16) 39 #define UNM_FFP_MASK UNM_FFP(~0) 40 #define UNU_FFP(x) (((x) & 0xff) << 8) 41 #define UNU_FFP_MASK UNU_FFP(~0) 42 #define CPU_EN BIT(7) 43 #define CPU_PORT(x) ((x) << 4) 44 #define CPU_MASK (0xf << 4) 45 #define MIRROR_EN BIT(3) 46 #define MIRROR_PORT(x) ((x) & 0x7) 47 #define MIRROR_MASK 0x7 48 49 /* Registers for CPU forward control */ 50 #define MT7531_CFC 0x4 51 #define MT7531_MIRROR_EN BIT(19) 52 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 53 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 54 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 55 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 56 57 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ 58 MT7531_CFC : MT7530_MFC) 59 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \ 60 MT7531_MIRROR_EN : MIRROR_EN) 61 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \ 62 MT7531_MIRROR_MASK : MIRROR_MASK) 63 64 /* Registers for BPDU and PAE frame control*/ 65 #define MT753X_BPC 0x24 66 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 67 68 enum mt753x_bpdu_port_fw { 69 MT753X_BPDU_FOLLOW_MFC, 70 MT753X_BPDU_CPU_EXCLUDE = 4, 71 MT753X_BPDU_CPU_INCLUDE = 5, 72 MT753X_BPDU_CPU_ONLY = 6, 73 MT753X_BPDU_DROP = 7, 74 }; 75 76 /* Registers for address table access */ 77 #define MT7530_ATA1 0x74 78 #define STATIC_EMP 0 79 #define STATIC_ENT 3 80 #define MT7530_ATA2 0x78 81 82 /* Register for address table write data */ 83 #define MT7530_ATWD 0x7c 84 85 /* Register for address table control */ 86 #define MT7530_ATC 0x80 87 #define ATC_HASH (((x) & 0xfff) << 16) 88 #define ATC_BUSY BIT(15) 89 #define ATC_SRCH_END BIT(14) 90 #define ATC_SRCH_HIT BIT(13) 91 #define ATC_INVALID BIT(12) 92 #define ATC_MAT(x) (((x) & 0xf) << 8) 93 #define ATC_MAT_MACTAB ATC_MAT(0) 94 95 enum mt7530_fdb_cmd { 96 MT7530_FDB_READ = 0, 97 MT7530_FDB_WRITE = 1, 98 MT7530_FDB_FLUSH = 2, 99 MT7530_FDB_START = 4, 100 MT7530_FDB_NEXT = 5, 101 }; 102 103 /* Registers for table search read address */ 104 #define MT7530_TSRA1 0x84 105 #define MAC_BYTE_0 24 106 #define MAC_BYTE_1 16 107 #define MAC_BYTE_2 8 108 #define MAC_BYTE_3 0 109 #define MAC_BYTE_MASK 0xff 110 111 #define MT7530_TSRA2 0x88 112 #define MAC_BYTE_4 24 113 #define MAC_BYTE_5 16 114 #define CVID 0 115 #define CVID_MASK 0xfff 116 117 #define MT7530_ATRD 0x8C 118 #define AGE_TIMER 24 119 #define AGE_TIMER_MASK 0xff 120 #define PORT_MAP 4 121 #define PORT_MAP_MASK 0xff 122 #define ENT_STATUS 2 123 #define ENT_STATUS_MASK 0x3 124 125 /* Register for vlan table control */ 126 #define MT7530_VTCR 0x90 127 #define VTCR_BUSY BIT(31) 128 #define VTCR_INVALID BIT(16) 129 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 130 #define VTCR_VID ((x) & 0xfff) 131 132 enum mt7530_vlan_cmd { 133 /* Read/Write the specified VID entry from VAWD register based 134 * on VID. 135 */ 136 MT7530_VTCR_RD_VID = 0, 137 MT7530_VTCR_WR_VID = 1, 138 }; 139 140 /* Register for setup vlan and acl write data */ 141 #define MT7530_VAWD1 0x94 142 #define PORT_STAG BIT(31) 143 /* Independent VLAN Learning */ 144 #define IVL_MAC BIT(30) 145 /* Per VLAN Egress Tag Control */ 146 #define VTAG_EN BIT(28) 147 /* VLAN Member Control */ 148 #define PORT_MEM(x) (((x) & 0xff) << 16) 149 /* VLAN Entry Valid */ 150 #define VLAN_VALID BIT(0) 151 #define PORT_MEM_SHFT 16 152 #define PORT_MEM_MASK 0xff 153 154 #define MT7530_VAWD2 0x98 155 /* Egress Tag Control */ 156 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 157 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 158 159 enum mt7530_vlan_egress_attr { 160 MT7530_VLAN_EGRESS_UNTAG = 0, 161 MT7530_VLAN_EGRESS_TAG = 2, 162 MT7530_VLAN_EGRESS_STACK = 3, 163 }; 164 165 /* Register for address age control */ 166 #define MT7530_AAC 0xa0 167 /* Disable ageing */ 168 #define AGE_DIS BIT(20) 169 /* Age count */ 170 #define AGE_CNT_MASK GENMASK(19, 12) 171 #define AGE_CNT_MAX 0xff 172 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 173 /* Age unit */ 174 #define AGE_UNIT_MASK GENMASK(11, 0) 175 #define AGE_UNIT_MAX 0xfff 176 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 177 178 /* Register for port STP state control */ 179 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 180 #define FID_PST(x) ((x) & 0x3) 181 #define FID_PST_MASK FID_PST(0x3) 182 183 enum mt7530_stp_state { 184 MT7530_STP_DISABLED = 0, 185 MT7530_STP_BLOCKING = 1, 186 MT7530_STP_LISTENING = 1, 187 MT7530_STP_LEARNING = 2, 188 MT7530_STP_FORWARDING = 3 189 }; 190 191 /* Register for port control */ 192 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 193 #define PORT_TX_MIR BIT(9) 194 #define PORT_RX_MIR BIT(8) 195 #define PORT_VLAN(x) ((x) & 0x3) 196 197 enum mt7530_port_mode { 198 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 199 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 200 201 /* Fallback Mode: Forward received frames with ingress ports that do 202 * not belong to the VLAN member. Frames whose VID is not listed on 203 * the VLAN table are forwarded by the PCR_MATRIX members. 204 */ 205 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 206 207 /* Security Mode: Discard any frame due to ingress membership 208 * violation or VID missed on the VLAN table. 209 */ 210 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 211 }; 212 213 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 214 #define PORT_PRI(x) (((x) & 0x7) << 24) 215 #define EG_TAG(x) (((x) & 0x3) << 28) 216 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 217 #define PCR_MATRIX_CLR PCR_MATRIX(0) 218 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 219 220 /* Register for port security control */ 221 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 222 #define SA_DIS BIT(4) 223 224 /* Register for port vlan control */ 225 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 226 #define PORT_SPEC_TAG BIT(5) 227 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 228 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 229 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 230 #define VLAN_ATTR_MASK VLAN_ATTR(3) 231 232 enum mt7530_vlan_port_eg_tag { 233 MT7530_VLAN_EG_DISABLED = 0, 234 MT7530_VLAN_EG_CONSISTENT = 1, 235 }; 236 237 enum mt7530_vlan_port_attr { 238 MT7530_VLAN_USER = 0, 239 MT7530_VLAN_TRANSPARENT = 3, 240 }; 241 242 #define STAG_VPID (((x) & 0xffff) << 16) 243 244 /* Register for port port-and-protocol based vlan 1 control */ 245 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 246 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 247 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 248 #define G0_PORT_VID_DEF G0_PORT_VID(1) 249 250 /* Register for port MAC control register */ 251 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 252 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 253 #define PMCR_EXT_PHY BIT(17) 254 #define PMCR_MAC_MODE BIT(16) 255 #define PMCR_FORCE_MODE BIT(15) 256 #define PMCR_TX_EN BIT(14) 257 #define PMCR_RX_EN BIT(13) 258 #define PMCR_BACKOFF_EN BIT(9) 259 #define PMCR_BACKPR_EN BIT(8) 260 #define PMCR_TX_FC_EN BIT(5) 261 #define PMCR_RX_FC_EN BIT(4) 262 #define PMCR_FORCE_SPEED_1000 BIT(3) 263 #define PMCR_FORCE_SPEED_100 BIT(2) 264 #define PMCR_FORCE_FDX BIT(1) 265 #define PMCR_FORCE_LNK BIT(0) 266 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 267 PMCR_FORCE_SPEED_1000) 268 #define MT7531_FORCE_LNK BIT(31) 269 #define MT7531_FORCE_SPD BIT(30) 270 #define MT7531_FORCE_DPX BIT(29) 271 #define MT7531_FORCE_RX_FC BIT(28) 272 #define MT7531_FORCE_TX_FC BIT(27) 273 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 274 MT7531_FORCE_SPD | \ 275 MT7531_FORCE_DPX | \ 276 MT7531_FORCE_RX_FC | \ 277 MT7531_FORCE_TX_FC) 278 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \ 279 MT7531_FORCE_MODE : \ 280 PMCR_FORCE_MODE) 281 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 282 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 283 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 284 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 285 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ 286 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 287 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 288 PMCR_TX_EN | PMCR_RX_EN | \ 289 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 290 PMCR_FORCE_SPEED_1000 | \ 291 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 292 293 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 294 #define PMSR_EEE1G BIT(7) 295 #define PMSR_EEE100M BIT(6) 296 #define PMSR_RX_FC BIT(5) 297 #define PMSR_TX_FC BIT(4) 298 #define PMSR_SPEED_1000 BIT(3) 299 #define PMSR_SPEED_100 BIT(2) 300 #define PMSR_SPEED_10 0x00 301 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 302 #define PMSR_DPX BIT(1) 303 #define PMSR_LINK BIT(0) 304 305 /* Register for port debug count */ 306 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 307 #define MT7531_DIS_CLR BIT(31) 308 309 #define MT7530_GMACCR 0x30e0 310 #define MAX_RX_JUMBO(x) ((x) << 2) 311 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 312 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 313 #define MAX_RX_PKT_LEN_1522 0x0 314 #define MAX_RX_PKT_LEN_1536 0x1 315 #define MAX_RX_PKT_LEN_1552 0x2 316 #define MAX_RX_PKT_LEN_JUMBO 0x3 317 318 /* Register for MIB */ 319 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 320 #define MT7530_MIB_CCR 0x4fe0 321 #define CCR_MIB_ENABLE BIT(31) 322 #define CCR_RX_OCT_CNT_GOOD BIT(7) 323 #define CCR_RX_OCT_CNT_BAD BIT(6) 324 #define CCR_TX_OCT_CNT_GOOD BIT(5) 325 #define CCR_TX_OCT_CNT_BAD BIT(4) 326 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 327 CCR_RX_OCT_CNT_BAD | \ 328 CCR_TX_OCT_CNT_GOOD | \ 329 CCR_TX_OCT_CNT_BAD) 330 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 331 CCR_RX_OCT_CNT_GOOD | \ 332 CCR_RX_OCT_CNT_BAD | \ 333 CCR_TX_OCT_CNT_GOOD | \ 334 CCR_TX_OCT_CNT_BAD) 335 336 /* MT7531 SGMII register group */ 337 #define MT7531_SGMII_REG_BASE 0x5000 338 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ 339 ((p) - 5) * 0x1000 + (r)) 340 341 /* Register forSGMII PCS_CONTROL_1 */ 342 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00) 343 #define MT7531_SGMII_LINK_STATUS BIT(18) 344 #define MT7531_SGMII_AN_ENABLE BIT(12) 345 #define MT7531_SGMII_AN_RESTART BIT(9) 346 347 /* Register for SGMII PCS_SPPED_ABILITY */ 348 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) 349 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0) 350 #define MT7531_SGMII_TX_CONFIG BIT(0) 351 352 /* Register for SGMII_MODE */ 353 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20) 354 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8) 355 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1) 356 #define MT7531_SGMII_FORCE_DUPLEX BIT(4) 357 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2) 358 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3) 359 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2) 360 #define MT7531_SGMII_FORCE_SPEED_10 0 361 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1) 362 363 enum mt7531_sgmii_force_duplex { 364 MT7531_SGMII_FORCE_FULL_DUPLEX = 0, 365 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10, 366 }; 367 368 /* Fields of QPHY_PWR_STATE_CTRL */ 369 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8) 370 #define MT7531_SGMII_PHYA_PWD BIT(4) 371 372 /* Values of SGMII SPEED */ 373 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128) 374 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3)) 375 #define MT7531_RG_TPHY_SPEED_1_25G 0x0 376 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2) 377 378 /* Register for system reset */ 379 #define MT7530_SYS_CTRL 0x7000 380 #define SYS_CTRL_PHY_RST BIT(2) 381 #define SYS_CTRL_SW_RST BIT(1) 382 #define SYS_CTRL_REG_RST BIT(0) 383 384 /* Register for PHY Indirect Access Control */ 385 #define MT7531_PHY_IAC 0x701C 386 #define MT7531_PHY_ACS_ST BIT(31) 387 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 388 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 389 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 390 #define MT7531_MDIO_ST_MASK (0x3 << 16) 391 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 392 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 393 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 394 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 395 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 396 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 397 398 enum mt7531_phy_iac_cmd { 399 MT7531_MDIO_ADDR = 0, 400 MT7531_MDIO_WRITE = 1, 401 MT7531_MDIO_READ = 2, 402 MT7531_MDIO_READ_CL45 = 3, 403 }; 404 405 /* MDIO_ST: MDIO start field */ 406 enum mt7531_mdio_st { 407 MT7531_MDIO_ST_CL45 = 0, 408 MT7531_MDIO_ST_CL22 = 1, 409 }; 410 411 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 412 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 413 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 414 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 415 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 416 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 417 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 418 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 419 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 420 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 421 422 /* Register for RGMII clock phase */ 423 #define MT7531_CLKGEN_CTRL 0x7500 424 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 425 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 426 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 427 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 428 #define RXCLK_NO_DELAY BIT(5) 429 #define TXCLK_NO_REVERSE BIT(4) 430 #define GP_MODE(x) (((x) & 0x3) << 1) 431 #define GP_MODE_MASK GENMASK(2, 1) 432 #define GP_CLK_EN BIT(0) 433 434 enum mt7531_gp_mode { 435 MT7531_GP_MODE_RGMII = 0, 436 MT7531_GP_MODE_MII = 1, 437 MT7531_GP_MODE_REV_MII = 2 438 }; 439 440 enum mt7531_clk_skew { 441 MT7531_CLK_SKEW_NO_CHG = 0, 442 MT7531_CLK_SKEW_DLY_100PPS = 1, 443 MT7531_CLK_SKEW_DLY_200PPS = 2, 444 MT7531_CLK_SKEW_REVERSE = 3, 445 }; 446 447 /* Register for hw trap status */ 448 #define MT7530_HWTRAP 0x7800 449 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 450 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 451 #define HWTRAP_XTAL_40MHZ (BIT(10)) 452 #define HWTRAP_XTAL_20MHZ (BIT(9)) 453 454 #define MT7531_HWTRAP 0x7800 455 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 456 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 457 #define HWTRAP_XTAL_FSEL_40MHZ 0 458 /* Unique fields of (M)HWSTRAP for MT7531 */ 459 #define XTAL_FSEL_S 7 460 #define XTAL_FSEL_M BIT(7) 461 #define PHY_EN BIT(6) 462 #define CHG_STRAP BIT(8) 463 464 /* Register for hw trap modification */ 465 #define MT7530_MHWTRAP 0x7804 466 #define MHWTRAP_PHY0_SEL BIT(20) 467 #define MHWTRAP_MANUAL BIT(16) 468 #define MHWTRAP_P5_MAC_SEL BIT(13) 469 #define MHWTRAP_P6_DIS BIT(8) 470 #define MHWTRAP_P5_RGMII_MODE BIT(7) 471 #define MHWTRAP_P5_DIS BIT(6) 472 #define MHWTRAP_PHY_ACCESS BIT(5) 473 474 /* Register for TOP signal control */ 475 #define MT7530_TOP_SIG_CTRL 0x7808 476 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 477 478 #define MT7531_TOP_SIG_SR 0x780c 479 #define PAD_DUAL_SGMII_EN BIT(1) 480 #define PAD_MCM_SMI_EN BIT(0) 481 482 #define MT7530_IO_DRV_CR 0x7810 483 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 484 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 485 486 #define MT7531_CHIP_REV 0x781C 487 488 #define MT7531_PLLGP_EN 0x7820 489 #define EN_COREPLL BIT(2) 490 #define SW_CLKSW BIT(1) 491 #define SW_PLLGP BIT(0) 492 493 #define MT7530_P6ECR 0x7830 494 #define P6_INTF_MODE_MASK 0x3 495 #define P6_INTF_MODE(x) ((x) & 0x3) 496 497 #define MT7531_PLLGP_CR0 0x78a8 498 #define RG_COREPLL_EN BIT(22) 499 #define RG_COREPLL_POSDIV_S 23 500 #define RG_COREPLL_POSDIV_M 0x3800000 501 #define RG_COREPLL_SDM_PCW_S 1 502 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 503 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 504 505 /* Registers for RGMII and SGMII PLL clock */ 506 #define MT7531_ANA_PLLGP_CR2 0x78b0 507 #define MT7531_ANA_PLLGP_CR5 0x78bc 508 509 /* Registers for TRGMII on the both side */ 510 #define MT7530_TRGMII_RCK_CTRL 0x7a00 511 #define RX_RST BIT(31) 512 #define RXC_DQSISEL BIT(30) 513 #define DQSI1_TAP_MASK (0x7f << 8) 514 #define DQSI0_TAP_MASK 0x7f 515 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 516 #define DQSI0_TAP(x) ((x) & 0x7f) 517 518 #define MT7530_TRGMII_RCK_RTT 0x7a04 519 #define DQS1_GATE BIT(31) 520 #define DQS0_GATE BIT(30) 521 522 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 523 #define BSLIP_EN BIT(31) 524 #define EDGE_CHK BIT(30) 525 #define RD_TAP_MASK 0x7f 526 #define RD_TAP(x) ((x) & 0x7f) 527 528 #define MT7530_TRGMII_TXCTRL 0x7a40 529 #define TRAIN_TXEN BIT(31) 530 #define TXC_INV BIT(30) 531 #define TX_RST BIT(28) 532 533 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 534 #define TD_DM_DRVP(x) ((x) & 0xf) 535 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 536 537 #define MT7530_TRGMII_TCK_CTRL 0x7a78 538 #define TCK_TAP(x) (((x) & 0xf) << 8) 539 540 #define MT7530_P5RGMIIRXCR 0x7b00 541 #define CSR_RGMII_EDGE_ALIGN BIT(8) 542 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 543 544 #define MT7530_P5RGMIITXCR 0x7b04 545 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 546 547 /* Registers for GPIO mode */ 548 #define MT7531_GPIO_MODE0 0x7c0c 549 #define MT7531_GPIO0_MASK GENMASK(3, 0) 550 #define MT7531_GPIO0_INTERRUPT 1 551 552 #define MT7531_GPIO_MODE1 0x7c10 553 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 554 #define MT7531_EXT_P_MDC_11 (2 << 12) 555 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 556 #define MT7531_EXT_P_MDIO_12 (2 << 16) 557 558 /* Registers for LED GPIO control (MT7530 only) 559 * All registers follow this pattern: 560 * [ 2: 0] port 0 561 * [ 6: 4] port 1 562 * [10: 8] port 2 563 * [14:12] port 3 564 * [18:16] port 4 565 */ 566 567 /* LED enable, 0: Disable, 1: Enable (Default) */ 568 #define MT7530_LED_EN 0x7d00 569 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 570 #define MT7530_LED_IO_MODE 0x7d04 571 /* GPIO direction, 0: Input, 1: Output */ 572 #define MT7530_LED_GPIO_DIR 0x7d10 573 /* GPIO output enable, 0: Disable, 1: Enable */ 574 #define MT7530_LED_GPIO_OE 0x7d14 575 /* GPIO value, 0: Low, 1: High */ 576 #define MT7530_LED_GPIO_DATA 0x7d18 577 578 #define MT7530_CREV 0x7ffc 579 #define CHIP_NAME_SHIFT 16 580 #define MT7530_ID 0x7530 581 582 #define MT7531_CREV 0x781C 583 #define CHIP_REV_M 0x0f 584 #define MT7531_ID 0x7531 585 586 /* Registers for core PLL access through mmd indirect */ 587 #define CORE_PLL_GROUP2 0x401 588 #define RG_SYSPLL_EN_NORMAL BIT(15) 589 #define RG_SYSPLL_VODEN BIT(14) 590 #define RG_SYSPLL_LF BIT(13) 591 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 592 #define RG_SYSPLL_LVROD_EN BIT(10) 593 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 594 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 595 #define RG_SYSPLL_FBKSEL BIT(4) 596 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 597 598 #define CORE_PLL_GROUP4 0x403 599 #define RG_SYSPLL_DDSFBK_EN BIT(12) 600 #define RG_SYSPLL_BIAS_EN BIT(11) 601 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 602 #define MT7531_PHY_PLL_OFF BIT(5) 603 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 604 605 #define MT753X_CTRL_PHY_ADDR 0 606 607 #define CORE_PLL_GROUP5 0x404 608 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 609 610 #define CORE_PLL_GROUP6 0x405 611 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 612 613 #define CORE_PLL_GROUP7 0x406 614 #define RG_LCDDS_PWDB BIT(15) 615 #define RG_LCDDS_ISO_EN BIT(13) 616 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 617 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 618 619 #define CORE_PLL_GROUP10 0x409 620 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 621 622 #define CORE_PLL_GROUP11 0x40a 623 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 624 625 #define CORE_GSWPLL_GRP1 0x40d 626 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 627 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 628 #define RG_GSWPLL_EN_PRE BIT(11) 629 #define RG_GSWPLL_FBKSEL BIT(10) 630 #define RG_GSWPLL_BP BIT(9) 631 #define RG_GSWPLL_BR BIT(8) 632 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 633 634 #define CORE_GSWPLL_GRP2 0x40e 635 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 636 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 637 638 #define CORE_TRGMII_GSW_CLK_CG 0x410 639 #define REG_GSWCK_EN BIT(0) 640 #define REG_TRGMIICK_EN BIT(1) 641 642 #define MIB_DESC(_s, _o, _n) \ 643 { \ 644 .size = (_s), \ 645 .offset = (_o), \ 646 .name = (_n), \ 647 } 648 649 struct mt7530_mib_desc { 650 unsigned int size; 651 unsigned int offset; 652 const char *name; 653 }; 654 655 struct mt7530_fdb { 656 u16 vid; 657 u8 port_mask; 658 u8 aging; 659 u8 mac[6]; 660 bool noarp; 661 }; 662 663 /* struct mt7530_port - This is the main data structure for holding the state 664 * of the port. 665 * @enable: The status used for show port is enabled or not. 666 * @pm: The matrix used to show all connections with the port. 667 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 668 * untagged frames will be assigned to the related VLAN. 669 * @vlan_filtering: The flags indicating whether the port that can recognize 670 * VLAN-tagged frames. 671 */ 672 struct mt7530_port { 673 bool enable; 674 u32 pm; 675 u16 pvid; 676 }; 677 678 /* Port 5 interface select definitions */ 679 enum p5_interface_select { 680 P5_DISABLED = 0, 681 P5_INTF_SEL_PHY_P0, 682 P5_INTF_SEL_PHY_P4, 683 P5_INTF_SEL_GMAC5, 684 P5_INTF_SEL_GMAC5_SGMII, 685 }; 686 687 static const char *p5_intf_modes(unsigned int p5_interface) 688 { 689 switch (p5_interface) { 690 case P5_DISABLED: 691 return "DISABLED"; 692 case P5_INTF_SEL_PHY_P0: 693 return "PHY P0"; 694 case P5_INTF_SEL_PHY_P4: 695 return "PHY P4"; 696 case P5_INTF_SEL_GMAC5: 697 return "GMAC5"; 698 case P5_INTF_SEL_GMAC5_SGMII: 699 return "GMAC5_SGMII"; 700 default: 701 return "unknown"; 702 } 703 } 704 705 /* struct mt753x_info - This is the main data structure for holding the specific 706 * part for each supported device 707 * @sw_setup: Holding the handler to a device initialization 708 * @phy_read: Holding the way reading PHY port 709 * @phy_write: Holding the way writing PHY port 710 * @pad_setup: Holding the way setting up the bus pad for a certain 711 * MAC port 712 * @phy_mode_supported: Check if the PHY type is being supported on a certain 713 * port 714 * @mac_port_validate: Holding the way to set addition validate type for a 715 * certan MAC port 716 * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain 717 * MAC port 718 * @mac_port_config: Holding the way setting up the PHY attribute to a 719 * certain MAC port 720 * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a 721 * certain MAC port 722 * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs 723 * of the certain MAC port 724 */ 725 struct mt753x_info { 726 enum mt753x_id id; 727 728 int (*sw_setup)(struct dsa_switch *ds); 729 int (*phy_read)(struct dsa_switch *ds, int port, int regnum); 730 int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val); 731 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); 732 int (*cpu_port_config)(struct dsa_switch *ds, int port); 733 bool (*phy_mode_supported)(struct dsa_switch *ds, int port, 734 const struct phylink_link_state *state); 735 void (*mac_port_validate)(struct dsa_switch *ds, int port, 736 unsigned long *supported); 737 int (*mac_port_get_state)(struct dsa_switch *ds, int port, 738 struct phylink_link_state *state); 739 int (*mac_port_config)(struct dsa_switch *ds, int port, 740 unsigned int mode, 741 phy_interface_t interface); 742 void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port); 743 void (*mac_pcs_link_up)(struct dsa_switch *ds, int port, 744 unsigned int mode, phy_interface_t interface, 745 int speed, int duplex); 746 }; 747 748 /* struct mt7530_priv - This is the main data structure for holding the state 749 * of the driver 750 * @dev: The device pointer 751 * @ds: The pointer to the dsa core structure 752 * @bus: The bus used for the device and built-in PHY 753 * @rstc: The pointer to reset control used by MCM 754 * @core_pwr: The power supplied into the core 755 * @io_pwr: The power supplied into the I/O 756 * @reset: The descriptor for GPIO line tied to its reset pin 757 * @mcm: Flag for distinguishing if standalone IC or module 758 * coupling 759 * @ports: Holding the state among ports 760 * @reg_mutex: The lock for protecting among process accessing 761 * registers 762 * @p6_interface Holding the current port 6 interface 763 * @p5_intf_sel: Holding the current port 5 interface select 764 */ 765 struct mt7530_priv { 766 struct device *dev; 767 struct dsa_switch *ds; 768 struct mii_bus *bus; 769 struct reset_control *rstc; 770 struct regulator *core_pwr; 771 struct regulator *io_pwr; 772 struct gpio_desc *reset; 773 const struct mt753x_info *info; 774 unsigned int id; 775 bool mcm; 776 phy_interface_t p6_interface; 777 phy_interface_t p5_interface; 778 unsigned int p5_intf_sel; 779 u8 mirror_rx; 780 u8 mirror_tx; 781 782 struct mt7530_port ports[MT7530_NUM_PORTS]; 783 /* protect among processes for registers access*/ 784 struct mutex reg_mutex; 785 }; 786 787 struct mt7530_hw_vlan_entry { 788 int port; 789 u8 old_members; 790 bool untagged; 791 }; 792 793 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 794 int port, bool untagged) 795 { 796 e->port = port; 797 e->untagged = untagged; 798 } 799 800 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 801 struct mt7530_hw_vlan_entry *); 802 803 struct mt7530_hw_stats { 804 const char *string; 805 u16 reg; 806 u8 sizeof_stat; 807 }; 808 809 struct mt7530_dummy_poll { 810 struct mt7530_priv *priv; 811 u32 reg; 812 }; 813 814 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 815 struct mt7530_priv *priv, u32 reg) 816 { 817 p->priv = priv; 818 p->reg = reg; 819 } 820 821 #endif /* __MT7530_H */ 822