1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_CPU_PORT 6 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 enum { 15 ID_MT7530 = 0, 16 ID_MT7621 = 1, 17 }; 18 19 #define NUM_TRGMII_CTRL 5 20 21 #define TRGMII_BASE(x) (0x10000 + (x)) 22 23 /* Registers to ethsys access */ 24 #define ETHSYS_CLKCFG0 0x2c 25 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 26 27 #define SYSC_REG_RSTCTRL 0x34 28 #define RESET_MCM BIT(2) 29 30 /* Registers to mac forward control for unknown frames */ 31 #define MT7530_MFC 0x10 32 #define BC_FFP(x) (((x) & 0xff) << 24) 33 #define UNM_FFP(x) (((x) & 0xff) << 16) 34 #define UNU_FFP(x) (((x) & 0xff) << 8) 35 #define UNU_FFP_MASK UNU_FFP(~0) 36 #define CPU_EN BIT(7) 37 #define CPU_PORT(x) ((x) << 4) 38 #define CPU_MASK (0xf << 4) 39 #define MIRROR_EN BIT(3) 40 #define MIRROR_PORT(x) ((x) & 0x7) 41 #define MIRROR_MASK 0x7 42 43 /* Registers for address table access */ 44 #define MT7530_ATA1 0x74 45 #define STATIC_EMP 0 46 #define STATIC_ENT 3 47 #define MT7530_ATA2 0x78 48 49 /* Register for address table write data */ 50 #define MT7530_ATWD 0x7c 51 52 /* Register for address table control */ 53 #define MT7530_ATC 0x80 54 #define ATC_HASH (((x) & 0xfff) << 16) 55 #define ATC_BUSY BIT(15) 56 #define ATC_SRCH_END BIT(14) 57 #define ATC_SRCH_HIT BIT(13) 58 #define ATC_INVALID BIT(12) 59 #define ATC_MAT(x) (((x) & 0xf) << 8) 60 #define ATC_MAT_MACTAB ATC_MAT(0) 61 62 enum mt7530_fdb_cmd { 63 MT7530_FDB_READ = 0, 64 MT7530_FDB_WRITE = 1, 65 MT7530_FDB_FLUSH = 2, 66 MT7530_FDB_START = 4, 67 MT7530_FDB_NEXT = 5, 68 }; 69 70 /* Registers for table search read address */ 71 #define MT7530_TSRA1 0x84 72 #define MAC_BYTE_0 24 73 #define MAC_BYTE_1 16 74 #define MAC_BYTE_2 8 75 #define MAC_BYTE_3 0 76 #define MAC_BYTE_MASK 0xff 77 78 #define MT7530_TSRA2 0x88 79 #define MAC_BYTE_4 24 80 #define MAC_BYTE_5 16 81 #define CVID 0 82 #define CVID_MASK 0xfff 83 84 #define MT7530_ATRD 0x8C 85 #define AGE_TIMER 24 86 #define AGE_TIMER_MASK 0xff 87 #define PORT_MAP 4 88 #define PORT_MAP_MASK 0xff 89 #define ENT_STATUS 2 90 #define ENT_STATUS_MASK 0x3 91 92 /* Register for vlan table control */ 93 #define MT7530_VTCR 0x90 94 #define VTCR_BUSY BIT(31) 95 #define VTCR_INVALID BIT(16) 96 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 97 #define VTCR_VID ((x) & 0xfff) 98 99 enum mt7530_vlan_cmd { 100 /* Read/Write the specified VID entry from VAWD register based 101 * on VID. 102 */ 103 MT7530_VTCR_RD_VID = 0, 104 MT7530_VTCR_WR_VID = 1, 105 }; 106 107 /* Register for setup vlan and acl write data */ 108 #define MT7530_VAWD1 0x94 109 #define PORT_STAG BIT(31) 110 /* Independent VLAN Learning */ 111 #define IVL_MAC BIT(30) 112 /* Per VLAN Egress Tag Control */ 113 #define VTAG_EN BIT(28) 114 /* VLAN Member Control */ 115 #define PORT_MEM(x) (((x) & 0xff) << 16) 116 /* VLAN Entry Valid */ 117 #define VLAN_VALID BIT(0) 118 #define PORT_MEM_SHFT 16 119 #define PORT_MEM_MASK 0xff 120 121 #define MT7530_VAWD2 0x98 122 /* Egress Tag Control */ 123 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 124 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 125 126 enum mt7530_vlan_egress_attr { 127 MT7530_VLAN_EGRESS_UNTAG = 0, 128 MT7530_VLAN_EGRESS_TAG = 2, 129 MT7530_VLAN_EGRESS_STACK = 3, 130 }; 131 132 /* Register for port STP state control */ 133 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 134 #define FID_PST(x) ((x) & 0x3) 135 #define FID_PST_MASK FID_PST(0x3) 136 137 enum mt7530_stp_state { 138 MT7530_STP_DISABLED = 0, 139 MT7530_STP_BLOCKING = 1, 140 MT7530_STP_LISTENING = 1, 141 MT7530_STP_LEARNING = 2, 142 MT7530_STP_FORWARDING = 3 143 }; 144 145 /* Register for port control */ 146 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 147 #define PORT_TX_MIR BIT(9) 148 #define PORT_RX_MIR BIT(8) 149 #define PORT_VLAN(x) ((x) & 0x3) 150 151 enum mt7530_port_mode { 152 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 153 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 154 155 /* Security Mode: Discard any frame due to ingress membership 156 * violation or VID missed on the VLAN table. 157 */ 158 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 159 }; 160 161 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 162 #define PORT_PRI(x) (((x) & 0x7) << 24) 163 #define EG_TAG(x) (((x) & 0x3) << 28) 164 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 165 #define PCR_MATRIX_CLR PCR_MATRIX(0) 166 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 167 168 /* Register for port security control */ 169 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 170 #define SA_DIS BIT(4) 171 172 /* Register for port vlan control */ 173 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 174 #define PORT_SPEC_TAG BIT(5) 175 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 176 #define VLAN_ATTR_MASK VLAN_ATTR(3) 177 178 enum mt7530_vlan_port_attr { 179 MT7530_VLAN_USER = 0, 180 MT7530_VLAN_TRANSPARENT = 3, 181 }; 182 183 #define STAG_VPID (((x) & 0xffff) << 16) 184 185 /* Register for port port-and-protocol based vlan 1 control */ 186 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 187 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 188 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 189 #define G0_PORT_VID_DEF G0_PORT_VID(1) 190 191 /* Register for port MAC control register */ 192 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 193 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 194 #define PMCR_EXT_PHY BIT(17) 195 #define PMCR_MAC_MODE BIT(16) 196 #define PMCR_FORCE_MODE BIT(15) 197 #define PMCR_TX_EN BIT(14) 198 #define PMCR_RX_EN BIT(13) 199 #define PMCR_BACKOFF_EN BIT(9) 200 #define PMCR_BACKPR_EN BIT(8) 201 #define PMCR_TX_FC_EN BIT(5) 202 #define PMCR_RX_FC_EN BIT(4) 203 #define PMCR_FORCE_SPEED_1000 BIT(3) 204 #define PMCR_FORCE_SPEED_100 BIT(2) 205 #define PMCR_FORCE_FDX BIT(1) 206 #define PMCR_FORCE_LNK BIT(0) 207 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 208 PMCR_FORCE_SPEED_1000) 209 210 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 211 #define PMSR_EEE1G BIT(7) 212 #define PMSR_EEE100M BIT(6) 213 #define PMSR_RX_FC BIT(5) 214 #define PMSR_TX_FC BIT(4) 215 #define PMSR_SPEED_1000 BIT(3) 216 #define PMSR_SPEED_100 BIT(2) 217 #define PMSR_SPEED_10 0x00 218 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 219 #define PMSR_DPX BIT(1) 220 #define PMSR_LINK BIT(0) 221 222 /* Register for MIB */ 223 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 224 #define MT7530_MIB_CCR 0x4fe0 225 #define CCR_MIB_ENABLE BIT(31) 226 #define CCR_RX_OCT_CNT_GOOD BIT(7) 227 #define CCR_RX_OCT_CNT_BAD BIT(6) 228 #define CCR_TX_OCT_CNT_GOOD BIT(5) 229 #define CCR_TX_OCT_CNT_BAD BIT(4) 230 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 231 CCR_RX_OCT_CNT_BAD | \ 232 CCR_TX_OCT_CNT_GOOD | \ 233 CCR_TX_OCT_CNT_BAD) 234 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 235 CCR_RX_OCT_CNT_GOOD | \ 236 CCR_RX_OCT_CNT_BAD | \ 237 CCR_TX_OCT_CNT_GOOD | \ 238 CCR_TX_OCT_CNT_BAD) 239 /* Register for system reset */ 240 #define MT7530_SYS_CTRL 0x7000 241 #define SYS_CTRL_PHY_RST BIT(2) 242 #define SYS_CTRL_SW_RST BIT(1) 243 #define SYS_CTRL_REG_RST BIT(0) 244 245 /* Register for hw trap status */ 246 #define MT7530_HWTRAP 0x7800 247 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 248 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 249 #define HWTRAP_XTAL_40MHZ (BIT(10)) 250 #define HWTRAP_XTAL_20MHZ (BIT(9)) 251 252 /* Register for hw trap modification */ 253 #define MT7530_MHWTRAP 0x7804 254 #define MHWTRAP_PHY0_SEL BIT(20) 255 #define MHWTRAP_MANUAL BIT(16) 256 #define MHWTRAP_P5_MAC_SEL BIT(13) 257 #define MHWTRAP_P6_DIS BIT(8) 258 #define MHWTRAP_P5_RGMII_MODE BIT(7) 259 #define MHWTRAP_P5_DIS BIT(6) 260 #define MHWTRAP_PHY_ACCESS BIT(5) 261 262 /* Register for TOP signal control */ 263 #define MT7530_TOP_SIG_CTRL 0x7808 264 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 265 266 #define MT7530_IO_DRV_CR 0x7810 267 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 268 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 269 270 #define MT7530_P6ECR 0x7830 271 #define P6_INTF_MODE_MASK 0x3 272 #define P6_INTF_MODE(x) ((x) & 0x3) 273 274 /* Registers for TRGMII on the both side */ 275 #define MT7530_TRGMII_RCK_CTRL 0x7a00 276 #define GSW_TRGMII_RCK_CTRL 0x300 277 #define RX_RST BIT(31) 278 #define RXC_DQSISEL BIT(30) 279 #define DQSI1_TAP_MASK (0x7f << 8) 280 #define DQSI0_TAP_MASK 0x7f 281 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 282 #define DQSI0_TAP(x) ((x) & 0x7f) 283 284 #define MT7530_TRGMII_RCK_RTT 0x7a04 285 #define GSW_TRGMII_RCK_RTT 0x304 286 #define DQS1_GATE BIT(31) 287 #define DQS0_GATE BIT(30) 288 289 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 290 #define GSW_TRGMII_RD(x) (0x310 + (x) * 8) 291 #define BSLIP_EN BIT(31) 292 #define EDGE_CHK BIT(30) 293 #define RD_TAP_MASK 0x7f 294 #define RD_TAP(x) ((x) & 0x7f) 295 296 #define GSW_TRGMII_TXCTRL 0x340 297 #define MT7530_TRGMII_TXCTRL 0x7a40 298 #define TRAIN_TXEN BIT(31) 299 #define TXC_INV BIT(30) 300 #define TX_RST BIT(28) 301 302 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 303 #define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i)) 304 #define TD_DM_DRVP(x) ((x) & 0xf) 305 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 306 307 #define GSW_INTF_MODE 0x390 308 #define INTF_MODE_TRGMII BIT(1) 309 310 #define MT7530_TRGMII_TCK_CTRL 0x7a78 311 #define TCK_TAP(x) (((x) & 0xf) << 8) 312 313 #define MT7530_P5RGMIIRXCR 0x7b00 314 #define CSR_RGMII_EDGE_ALIGN BIT(8) 315 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 316 317 #define MT7530_P5RGMIITXCR 0x7b04 318 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 319 320 #define MT7530_CREV 0x7ffc 321 #define CHIP_NAME_SHIFT 16 322 #define MT7530_ID 0x7530 323 324 /* Registers for core PLL access through mmd indirect */ 325 #define CORE_PLL_GROUP2 0x401 326 #define RG_SYSPLL_EN_NORMAL BIT(15) 327 #define RG_SYSPLL_VODEN BIT(14) 328 #define RG_SYSPLL_LF BIT(13) 329 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 330 #define RG_SYSPLL_LVROD_EN BIT(10) 331 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 332 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 333 #define RG_SYSPLL_FBKSEL BIT(4) 334 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 335 336 #define CORE_PLL_GROUP4 0x403 337 #define RG_SYSPLL_DDSFBK_EN BIT(12) 338 #define RG_SYSPLL_BIAS_EN BIT(11) 339 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 340 341 #define CORE_PLL_GROUP5 0x404 342 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 343 344 #define CORE_PLL_GROUP6 0x405 345 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 346 347 #define CORE_PLL_GROUP7 0x406 348 #define RG_LCDDS_PWDB BIT(15) 349 #define RG_LCDDS_ISO_EN BIT(13) 350 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 351 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 352 353 #define CORE_PLL_GROUP10 0x409 354 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 355 356 #define CORE_PLL_GROUP11 0x40a 357 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 358 359 #define CORE_GSWPLL_GRP1 0x40d 360 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 361 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 362 #define RG_GSWPLL_EN_PRE BIT(11) 363 #define RG_GSWPLL_FBKSEL BIT(10) 364 #define RG_GSWPLL_BP BIT(9) 365 #define RG_GSWPLL_BR BIT(8) 366 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 367 368 #define CORE_GSWPLL_GRP2 0x40e 369 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 370 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 371 372 #define CORE_TRGMII_GSW_CLK_CG 0x410 373 #define REG_GSWCK_EN BIT(0) 374 #define REG_TRGMIICK_EN BIT(1) 375 376 #define MIB_DESC(_s, _o, _n) \ 377 { \ 378 .size = (_s), \ 379 .offset = (_o), \ 380 .name = (_n), \ 381 } 382 383 struct mt7530_mib_desc { 384 unsigned int size; 385 unsigned int offset; 386 const char *name; 387 }; 388 389 struct mt7530_fdb { 390 u16 vid; 391 u8 port_mask; 392 u8 aging; 393 u8 mac[6]; 394 bool noarp; 395 }; 396 397 /* struct mt7530_port - This is the main data structure for holding the state 398 * of the port. 399 * @enable: The status used for show port is enabled or not. 400 * @pm: The matrix used to show all connections with the port. 401 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 402 * untagged frames will be assigned to the related VLAN. 403 * @vlan_filtering: The flags indicating whether the port that can recognize 404 * VLAN-tagged frames. 405 */ 406 struct mt7530_port { 407 bool enable; 408 u32 pm; 409 u16 pvid; 410 }; 411 412 /* Port 5 interface select definitions */ 413 enum p5_interface_select { 414 P5_DISABLED = 0, 415 P5_INTF_SEL_PHY_P0, 416 P5_INTF_SEL_PHY_P4, 417 P5_INTF_SEL_GMAC5, 418 }; 419 420 static const char *p5_intf_modes(unsigned int p5_interface) 421 { 422 switch (p5_interface) { 423 case P5_DISABLED: 424 return "DISABLED"; 425 case P5_INTF_SEL_PHY_P0: 426 return "PHY P0"; 427 case P5_INTF_SEL_PHY_P4: 428 return "PHY P4"; 429 case P5_INTF_SEL_GMAC5: 430 return "GMAC5"; 431 default: 432 return "unknown"; 433 } 434 } 435 436 /* struct mt7530_priv - This is the main data structure for holding the state 437 * of the driver 438 * @dev: The device pointer 439 * @ds: The pointer to the dsa core structure 440 * @bus: The bus used for the device and built-in PHY 441 * @rstc: The pointer to reset control used by MCM 442 * @ethernet: The regmap used for access TRGMII-based registers 443 * @core_pwr: The power supplied into the core 444 * @io_pwr: The power supplied into the I/O 445 * @reset: The descriptor for GPIO line tied to its reset pin 446 * @mcm: Flag for distinguishing if standalone IC or module 447 * coupling 448 * @ports: Holding the state among ports 449 * @reg_mutex: The lock for protecting among process accessing 450 * registers 451 * @p6_interface Holding the current port 6 interface 452 * @p5_intf_sel: Holding the current port 5 interface select 453 */ 454 struct mt7530_priv { 455 struct device *dev; 456 struct dsa_switch *ds; 457 struct mii_bus *bus; 458 struct reset_control *rstc; 459 struct regmap *ethernet; 460 struct regulator *core_pwr; 461 struct regulator *io_pwr; 462 struct gpio_desc *reset; 463 unsigned int id; 464 bool mcm; 465 phy_interface_t p6_interface; 466 phy_interface_t p5_interface; 467 unsigned int p5_intf_sel; 468 u8 mirror_rx; 469 u8 mirror_tx; 470 471 struct mt7530_port ports[MT7530_NUM_PORTS]; 472 /* protect among processes for registers access*/ 473 struct mutex reg_mutex; 474 }; 475 476 struct mt7530_hw_vlan_entry { 477 int port; 478 u8 old_members; 479 bool untagged; 480 }; 481 482 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 483 int port, bool untagged) 484 { 485 e->port = port; 486 e->untagged = untagged; 487 } 488 489 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 490 struct mt7530_hw_vlan_entry *); 491 492 struct mt7530_hw_stats { 493 const char *string; 494 u16 reg; 495 u8 sizeof_stat; 496 }; 497 498 struct mt7530_dummy_poll { 499 struct mt7530_priv *priv; 500 u32 reg; 501 }; 502 503 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 504 struct mt7530_priv *priv, u32 reg) 505 { 506 p->priv = priv; 507 p->reg = reg; 508 } 509 510 #endif /* __MT7530_H */ 511