1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 ID_EN7581 = 4, 23 ID_AN7583 = 5, 24 ID_EN7528 = 6, 25 }; 26 27 #define NUM_TRGMII_CTRL 5 28 29 #define TRGMII_BASE(x) (0x10000 + (x)) 30 31 /* Registers to ethsys access */ 32 #define ETHSYS_CLKCFG0 0x2c 33 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 34 35 #define SYSC_REG_RSTCTRL 0x34 36 #define RESET_MCM BIT(2) 37 38 /* Register for ARL global control */ 39 #define MT753X_AGC 0xc 40 #define LOCAL_EN BIT(7) 41 42 /* Register for MAC forward control */ 43 #define MT753X_MFC 0x10 44 #define BC_FFP_MASK GENMASK(31, 24) 45 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) 46 #define UNM_FFP_MASK GENMASK(23, 16) 47 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) 48 #define UNU_FFP_MASK GENMASK(15, 8) 49 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) 50 #define MT7530_CPU_EN BIT(7) 51 #define MT7530_CPU_PORT_MASK GENMASK(6, 4) 52 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) 53 #define MT7530_MIRROR_EN BIT(3) 54 #define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) 55 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) 56 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) 57 #define MT7531_QRY_FFP_MASK GENMASK(7, 0) 58 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) 59 60 /* Register for CPU forward control */ 61 #define MT7531_CFC 0x4 62 #define MT7531_MIRROR_EN BIT(19) 63 #define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) 64 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) 65 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) 66 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 67 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 68 69 #define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ 70 id == ID_MT7988 || \ 71 id == ID_EN7581 || \ 72 id == ID_AN7583) ? \ 73 MT7531_CFC : MT753X_MFC) 74 75 #define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ 76 id == ID_MT7988 || \ 77 id == ID_EN7581) ? \ 78 MT7531_MIRROR_EN : MT7530_MIRROR_EN) 79 80 #define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ 81 id == ID_MT7988 || \ 82 id == ID_EN7581 || \ 83 id == ID_AN7583) ? \ 84 MT7531_MIRROR_PORT_MASK : \ 85 MT7530_MIRROR_PORT_MASK) 86 87 #define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ 88 id == ID_MT7988 || \ 89 id == ID_EN7581 || \ 90 id == ID_AN7583) ? \ 91 MT7531_MIRROR_PORT_GET(val) : \ 92 MT7530_MIRROR_PORT_GET(val)) 93 94 #define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ 95 id == ID_MT7988 || \ 96 id == ID_EN7581 || \ 97 id == ID_AN7583) ? \ 98 MT7531_MIRROR_PORT_SET(val) : \ 99 MT7530_MIRROR_PORT_SET(val)) 100 101 /* Register for BPDU and PAE frame control */ 102 #define MT753X_BPC 0x24 103 #define PAE_BPDU_FR BIT(25) 104 #define PAE_EG_TAG_MASK GENMASK(24, 22) 105 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) 106 #define PAE_PORT_FW_MASK GENMASK(18, 16) 107 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) 108 #define BPDU_EG_TAG_MASK GENMASK(8, 6) 109 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) 110 #define BPDU_PORT_FW_MASK GENMASK(2, 0) 111 112 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ 113 #define MT753X_RGAC1 0x28 114 #define R02_BPDU_FR BIT(25) 115 #define R02_EG_TAG_MASK GENMASK(24, 22) 116 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) 117 #define R02_PORT_FW_MASK GENMASK(18, 16) 118 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) 119 #define R01_BPDU_FR BIT(9) 120 #define R01_EG_TAG_MASK GENMASK(8, 6) 121 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) 122 #define R01_PORT_FW_MASK GENMASK(2, 0) 123 124 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ 125 #define MT753X_RGAC2 0x2c 126 #define R0E_BPDU_FR BIT(25) 127 #define R0E_EG_TAG_MASK GENMASK(24, 22) 128 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) 129 #define R0E_PORT_FW_MASK GENMASK(18, 16) 130 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) 131 #define R03_BPDU_FR BIT(9) 132 #define R03_EG_TAG_MASK GENMASK(8, 6) 133 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) 134 #define R03_PORT_FW_MASK GENMASK(2, 0) 135 136 enum mt753x_to_cpu_fw { 137 TO_CPU_FW_SYSTEM_DEFAULT, 138 TO_CPU_FW_CPU_EXCLUDE = 4, 139 TO_CPU_FW_CPU_INCLUDE = 5, 140 TO_CPU_FW_CPU_ONLY = 6, 141 TO_CPU_FW_DROP = 7, 142 }; 143 144 /* Registers for address table access */ 145 #define MT7530_ATA1 0x74 146 #define STATIC_EMP 0 147 #define STATIC_ENT 3 148 #define MT7530_ATA2 0x78 149 #define ATA2_IVL BIT(15) 150 #define ATA2_FID(x) (((x) & 0x7) << 12) 151 152 /* Register for address table write data */ 153 #define MT7530_ATWD 0x7c 154 155 /* Register for address table control */ 156 #define MT7530_ATC 0x80 157 #define ATC_HASH (((x) & 0xfff) << 16) 158 #define ATC_BUSY BIT(15) 159 #define ATC_SRCH_END BIT(14) 160 #define ATC_SRCH_HIT BIT(13) 161 #define ATC_INVALID BIT(12) 162 #define ATC_MAT(x) (((x) & 0xf) << 8) 163 #define ATC_MAT_MACTAB ATC_MAT(0) 164 165 enum mt7530_fdb_cmd { 166 MT7530_FDB_READ = 0, 167 MT7530_FDB_WRITE = 1, 168 MT7530_FDB_FLUSH = 2, 169 MT7530_FDB_START = 4, 170 MT7530_FDB_NEXT = 5, 171 }; 172 173 /* Registers for table search read address */ 174 #define MT7530_TSRA1 0x84 175 #define MAC_BYTE_0 24 176 #define MAC_BYTE_1 16 177 #define MAC_BYTE_2 8 178 #define MAC_BYTE_3 0 179 #define MAC_BYTE_MASK 0xff 180 181 #define MT7530_TSRA2 0x88 182 #define MAC_BYTE_4 24 183 #define MAC_BYTE_5 16 184 #define CVID 0 185 #define CVID_MASK 0xfff 186 187 #define MT7530_ATRD 0x8C 188 #define AGE_TIMER 24 189 #define AGE_TIMER_MASK 0xff 190 #define PORT_MAP 4 191 #define PORT_MAP_MASK 0xff 192 #define ENT_STATUS 2 193 #define ENT_STATUS_MASK 0x3 194 195 /* Register for vlan table control */ 196 #define MT7530_VTCR 0x90 197 #define VTCR_BUSY BIT(31) 198 #define VTCR_INVALID BIT(16) 199 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 200 #define VTCR_VID ((x) & 0xfff) 201 202 enum mt7530_vlan_cmd { 203 /* Read/Write the specified VID entry from VAWD register based 204 * on VID. 205 */ 206 MT7530_VTCR_RD_VID = 0, 207 MT7530_VTCR_WR_VID = 1, 208 }; 209 210 /* Register for setup vlan and acl write data */ 211 #define MT7530_VAWD1 0x94 212 #define PORT_STAG BIT(31) 213 /* Independent VLAN Learning */ 214 #define IVL_MAC BIT(30) 215 /* Egress Tag Consistent */ 216 #define EG_CON BIT(29) 217 /* Per VLAN Egress Tag Control */ 218 #define VTAG_EN BIT(28) 219 /* VLAN Member Control */ 220 #define PORT_MEM(x) (((x) & 0xff) << 16) 221 /* Filter ID */ 222 #define FID(x) (((x) & 0x7) << 1) 223 /* VLAN Entry Valid */ 224 #define VLAN_VALID BIT(0) 225 #define PORT_MEM_SHFT 16 226 #define PORT_MEM_MASK 0xff 227 228 enum mt7530_fid { 229 FID_STANDALONE = 0, 230 FID_BRIDGED = 1, 231 }; 232 233 #define MT7530_VAWD2 0x98 234 /* Egress Tag Control */ 235 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 236 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 237 238 enum mt7530_vlan_egress_attr { 239 MT7530_VLAN_EGRESS_UNTAG = 0, 240 MT7530_VLAN_EGRESS_TAG = 2, 241 MT7530_VLAN_EGRESS_STACK = 3, 242 }; 243 244 /* Register for address age control */ 245 #define MT7530_AAC 0xa0 246 /* Disable ageing */ 247 #define AGE_DIS BIT(20) 248 /* Age count */ 249 #define AGE_CNT_MASK GENMASK(19, 12) 250 #define AGE_CNT_MAX 0xff 251 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 252 /* Age unit */ 253 #define AGE_UNIT_MASK GENMASK(11, 0) 254 #define AGE_UNIT_MAX 0xfff 255 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 256 257 #define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100)) 258 #define ERLCR_CIR_MASK GENMASK(31, 16) 259 #define ERLCR_EN_MASK BIT(15) 260 #define ERLCR_EXP_MASK GENMASK(11, 8) 261 #define ERLCR_TBF_MODE_MASK BIT(7) 262 #define ERLCR_MANT_MASK GENMASK(6, 0) 263 264 #define MT753X_GERLCR 0x10e0 265 #define EGR_BC_MASK GENMASK(7, 0) 266 #define EGR_BC_CRC 0x4 /* crc */ 267 #define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */ 268 269 /* Register for port STP state control */ 270 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 271 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 272 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 273 274 enum mt7530_stp_state { 275 MT7530_STP_DISABLED = 0, 276 MT7530_STP_BLOCKING = 1, 277 MT7530_STP_LISTENING = 1, 278 MT7530_STP_LEARNING = 2, 279 MT7530_STP_FORWARDING = 3 280 }; 281 282 /* Register for port control */ 283 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 284 #define PORT_TX_MIR BIT(9) 285 #define PORT_RX_MIR BIT(8) 286 #define PORT_VLAN(x) ((x) & 0x3) 287 288 enum mt7530_port_mode { 289 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 290 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 291 292 /* Fallback Mode: Forward received frames with ingress ports that do 293 * not belong to the VLAN member. Frames whose VID is not listed on 294 * the VLAN table are forwarded by the PCR_MATRIX members. 295 */ 296 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 297 298 /* Security Mode: Discard any frame due to ingress membership 299 * violation or VID missed on the VLAN table. 300 */ 301 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 302 }; 303 304 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 305 #define PORT_PRI(x) (((x) & 0x7) << 24) 306 #define EG_TAG(x) (((x) & 0x3) << 28) 307 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 308 #define PCR_MATRIX_CLR PCR_MATRIX(0) 309 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 310 311 /* Register for port security control */ 312 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 313 #define SA_DIS BIT(4) 314 315 /* Register for port vlan control */ 316 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 317 #define PORT_SPEC_TAG BIT(5) 318 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 319 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 320 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 321 #define VLAN_ATTR_MASK VLAN_ATTR(3) 322 #define ACC_FRM_MASK GENMASK(1, 0) 323 324 enum mt7530_vlan_port_eg_tag { 325 MT7530_VLAN_EG_DISABLED = 0, 326 MT7530_VLAN_EG_CONSISTENT = 1, 327 MT7530_VLAN_EG_UNTAGGED = 4, 328 }; 329 330 enum mt7530_vlan_port_attr { 331 MT7530_VLAN_USER = 0, 332 MT7530_VLAN_TRANSPARENT = 3, 333 }; 334 335 enum mt7530_vlan_port_acc_frm { 336 MT7530_VLAN_ACC_ALL = 0, 337 MT7530_VLAN_ACC_TAGGED = 1, 338 MT7530_VLAN_ACC_UNTAGGED = 2, 339 }; 340 341 #define STAG_VPID (((x) & 0xffff) << 16) 342 343 /* Register for port port-and-protocol based vlan 1 control */ 344 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 345 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 346 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 347 #define G0_PORT_VID_DEF G0_PORT_VID(0) 348 349 /* Register for port MAC control register */ 350 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) 351 #define PMCR_IFG_XMIT_MASK GENMASK(19, 18) 352 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) 353 #define PMCR_EXT_PHY BIT(17) 354 #define PMCR_MAC_MODE BIT(16) 355 #define MT7530_FORCE_MODE BIT(15) 356 #define PMCR_MAC_TX_EN BIT(14) 357 #define PMCR_MAC_RX_EN BIT(13) 358 #define PMCR_BACKOFF_EN BIT(9) 359 #define PMCR_BACKPR_EN BIT(8) 360 #define PMCR_FORCE_EEE1G BIT(7) 361 #define PMCR_FORCE_EEE100 BIT(6) 362 #define PMCR_FORCE_RX_FC_EN BIT(5) 363 #define PMCR_FORCE_TX_FC_EN BIT(4) 364 #define PMCR_FORCE_SPEED_1000 BIT(3) 365 #define PMCR_FORCE_SPEED_100 BIT(2) 366 #define PMCR_FORCE_FDX BIT(1) 367 #define PMCR_FORCE_LNK BIT(0) 368 #define MT7531_FORCE_MODE_LNK BIT(31) 369 #define MT7531_FORCE_MODE_SPD BIT(30) 370 #define MT7531_FORCE_MODE_DPX BIT(29) 371 #define MT7531_FORCE_MODE_RX_FC BIT(28) 372 #define MT7531_FORCE_MODE_TX_FC BIT(27) 373 #define MT7531_FORCE_MODE_EEE100 BIT(26) 374 #define MT7531_FORCE_MODE_EEE1G BIT(25) 375 #define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ 376 MT7531_FORCE_MODE_SPD | \ 377 MT7531_FORCE_MODE_DPX | \ 378 MT7531_FORCE_MODE_RX_FC | \ 379 MT7531_FORCE_MODE_TX_FC | \ 380 MT7531_FORCE_MODE_EEE100 | \ 381 MT7531_FORCE_MODE_EEE1G) 382 #define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \ 383 id == ID_MT7988) ? \ 384 MT7531_FORCE_MODE_MASK : \ 385 MT7530_FORCE_MODE) 386 #define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ 387 PMCR_FORCE_EEE1G | \ 388 PMCR_FORCE_EEE100 | \ 389 PMCR_FORCE_RX_FC_EN | \ 390 PMCR_FORCE_TX_FC_EN | \ 391 PMCR_FORCE_SPEED_1000 | \ 392 PMCR_FORCE_SPEED_100 | \ 393 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 394 395 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) 396 #define WAKEUP_TIME_1000_MASK GENMASK(31, 24) 397 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) 398 #define WAKEUP_TIME_100_MASK GENMASK(23, 16) 399 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) 400 #define LPI_THRESH_MASK GENMASK(15, 4) 401 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) 402 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) 403 #define LPI_MODE_EN BIT(0) 404 405 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 406 #define PMSR_EEE1G BIT(7) 407 #define PMSR_EEE100M BIT(6) 408 #define PMSR_RX_FC BIT(5) 409 #define PMSR_TX_FC BIT(4) 410 #define PMSR_SPEED_1000 BIT(3) 411 #define PMSR_SPEED_100 BIT(2) 412 #define PMSR_SPEED_10 0x00 413 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 414 #define PMSR_DPX BIT(1) 415 #define PMSR_LINK BIT(0) 416 417 /* Register for port debug count */ 418 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 419 #define MT7531_DIS_CLR BIT(31) 420 421 #define MT7530_GMACCR 0x30e0 422 #define MAX_RX_JUMBO(x) ((x) << 2) 423 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 424 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 425 #define MAX_RX_PKT_LEN_1522 0x0 426 #define MAX_RX_PKT_LEN_1536 0x1 427 #define MAX_RX_PKT_LEN_1552 0x2 428 #define MAX_RX_PKT_LEN_JUMBO 0x3 429 430 /* Register for MIB */ 431 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 432 /* Each define is an offset of MT7530_PORT_MIB_COUNTER */ 433 #define MT7530_PORT_MIB_TX_DROP 0x00 434 #define MT7530_PORT_MIB_TX_CRC_ERR 0x04 435 #define MT7530_PORT_MIB_TX_UNICAST 0x08 436 #define MT7530_PORT_MIB_TX_MULTICAST 0x0c 437 #define MT7530_PORT_MIB_TX_BROADCAST 0x10 438 #define MT7530_PORT_MIB_TX_COLLISION 0x14 439 #define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18 440 #define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c 441 #define MT7530_PORT_MIB_TX_DEFERRED 0x20 442 #define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24 443 #define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 444 #define MT7530_PORT_MIB_TX_PAUSE 0x2c 445 #define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30 446 #define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 447 #define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 448 #define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c 449 #define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 450 #define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44 451 #define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */ 452 #define MT7530_PORT_MIB_RX_DROP 0x60 453 #define MT7530_PORT_MIB_RX_FILTERING 0x64 454 #define MT7530_PORT_MIB_RX_UNICAST 0x68 455 #define MT7530_PORT_MIB_RX_MULTICAST 0x6c 456 #define MT7530_PORT_MIB_RX_BROADCAST 0x70 457 #define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74 458 #define MT7530_PORT_MIB_RX_CRC_ERR 0x78 459 #define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c 460 #define MT7530_PORT_MIB_RX_FRAG_ERR 0x80 461 #define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84 462 #define MT7530_PORT_MIB_RX_JABBER_ERR 0x88 463 #define MT7530_PORT_MIB_RX_PAUSE 0x8c 464 #define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90 465 #define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94 466 #define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98 467 #define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c 468 #define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0 469 #define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4 470 #define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */ 471 #define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0 472 #define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4 473 #define MT7530_PORT_MIB_RX_ARL_DROP 0xb8 474 #define MT7530_MIB_CCR 0x4fe0 475 #define CCR_MIB_ENABLE BIT(31) 476 #define CCR_RX_OCT_CNT_GOOD BIT(7) 477 #define CCR_RX_OCT_CNT_BAD BIT(6) 478 #define CCR_TX_OCT_CNT_GOOD BIT(5) 479 #define CCR_TX_OCT_CNT_BAD BIT(4) 480 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 481 CCR_RX_OCT_CNT_BAD | \ 482 CCR_TX_OCT_CNT_GOOD | \ 483 CCR_TX_OCT_CNT_BAD) 484 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 485 CCR_RX_OCT_CNT_GOOD | \ 486 CCR_RX_OCT_CNT_BAD | \ 487 CCR_TX_OCT_CNT_GOOD | \ 488 CCR_TX_OCT_CNT_BAD) 489 490 /* MT7531 SGMII register group */ 491 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 492 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 493 494 /* Register for system reset */ 495 #define MT7530_SYS_CTRL 0x7000 496 #define SYS_CTRL_PHY_RST BIT(2) 497 #define SYS_CTRL_SW_RST BIT(1) 498 #define SYS_CTRL_REG_RST BIT(0) 499 500 /* Register for system interrupt */ 501 #define MT7530_SYS_INT_EN 0x7008 502 503 /* Register for system interrupt status */ 504 #define MT7530_SYS_INT_STS 0x700c 505 506 /* Register for PHY Indirect Access Control */ 507 #define MT7531_PHY_IAC 0x701C 508 #define MT7531_PHY_ACS_ST BIT(31) 509 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 510 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 511 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 512 #define MT7531_MDIO_ST_MASK (0x3 << 16) 513 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 514 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 515 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 516 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 517 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 518 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 519 520 enum mt7531_phy_iac_cmd { 521 MT7531_MDIO_ADDR = 0, 522 MT7531_MDIO_WRITE = 1, 523 MT7531_MDIO_READ = 2, 524 MT7531_MDIO_READ_CL45 = 3, 525 }; 526 527 /* MDIO_ST: MDIO start field */ 528 enum mt7531_mdio_st { 529 MT7531_MDIO_ST_CL45 = 0, 530 MT7531_MDIO_ST_CL22 = 1, 531 }; 532 533 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 534 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 535 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 536 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 537 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 538 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 539 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 540 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 541 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 542 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 543 544 /* Register for RGMII clock phase */ 545 #define MT7531_CLKGEN_CTRL 0x7500 546 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 547 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 548 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 549 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 550 #define RXCLK_NO_DELAY BIT(5) 551 #define TXCLK_NO_REVERSE BIT(4) 552 #define GP_MODE(x) (((x) & 0x3) << 1) 553 #define GP_MODE_MASK GENMASK(2, 1) 554 #define GP_CLK_EN BIT(0) 555 556 enum mt7531_gp_mode { 557 MT7531_GP_MODE_RGMII = 0, 558 MT7531_GP_MODE_MII = 1, 559 MT7531_GP_MODE_REV_MII = 2 560 }; 561 562 enum mt7531_clk_skew { 563 MT7531_CLK_SKEW_NO_CHG = 0, 564 MT7531_CLK_SKEW_DLY_100PPS = 1, 565 MT7531_CLK_SKEW_DLY_200PPS = 2, 566 MT7531_CLK_SKEW_REVERSE = 3, 567 }; 568 569 /* Register for trap status */ 570 #define MT753X_TRAP 0x7800 571 #define MT7530_XTAL_MASK (BIT(10) | BIT(9)) 572 #define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) 573 #define MT7530_XTAL_40MHZ BIT(10) 574 #define MT7530_XTAL_20MHZ BIT(9) 575 #define MT7531_XTAL25 BIT(7) 576 577 /* Register for trap modification */ 578 #define MT753X_MTRAP 0x7804 579 #define MT7530_P5_PHY0_SEL BIT(20) 580 #define MT7530_CHG_TRAP BIT(16) 581 #define MT7530_P5_MAC_SEL BIT(13) 582 #define MT7530_P6_DIS BIT(8) 583 #define MT7530_P5_RGMII_MODE BIT(7) 584 #define MT7530_P5_DIS BIT(6) 585 #define MT7530_PHY_INDIRECT_ACCESS BIT(5) 586 #define MT7531_CHG_STRAP BIT(8) 587 #define MT7531_PHY_EN BIT(6) 588 589 enum mt7531_xtal_fsel { 590 MT7531_XTAL_FSEL_25MHZ, 591 MT7531_XTAL_FSEL_40MHZ, 592 }; 593 594 /* Register for TOP signal control */ 595 #define MT7530_TOP_SIG_CTRL 0x7808 596 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 597 598 #define MT7531_TOP_SIG_SR 0x780c 599 #define PAD_DUAL_SGMII_EN BIT(1) 600 #define PAD_MCM_SMI_EN BIT(0) 601 602 #define MT7530_IO_DRV_CR 0x7810 603 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 604 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 605 606 #define MT7531_CHIP_REV 0x781C 607 608 #define MT7531_PLLGP_EN 0x7820 609 #define EN_COREPLL BIT(2) 610 #define SW_CLKSW BIT(1) 611 #define SW_PLLGP BIT(0) 612 613 #define MT7530_P6ECR 0x7830 614 #define P6_INTF_MODE_MASK 0x3 615 #define P6_INTF_MODE(x) ((x) & 0x3) 616 617 #define MT7531_PLLGP_CR0 0x78a8 618 #define RG_COREPLL_EN BIT(22) 619 #define RG_COREPLL_POSDIV_S 23 620 #define RG_COREPLL_POSDIV_M 0x3800000 621 #define RG_COREPLL_SDM_PCW_S 1 622 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 623 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 624 625 /* Registers for RGMII and SGMII PLL clock */ 626 #define MT7531_ANA_PLLGP_CR2 0x78b0 627 #define MT7531_ANA_PLLGP_CR5 0x78bc 628 629 /* Registers for TRGMII on the both side */ 630 #define MT7530_TRGMII_RCK_CTRL 0x7a00 631 #define RX_RST BIT(31) 632 #define RXC_DQSISEL BIT(30) 633 #define DQSI1_TAP_MASK (0x7f << 8) 634 #define DQSI0_TAP_MASK 0x7f 635 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 636 #define DQSI0_TAP(x) ((x) & 0x7f) 637 638 #define MT7530_TRGMII_RCK_RTT 0x7a04 639 #define DQS1_GATE BIT(31) 640 #define DQS0_GATE BIT(30) 641 642 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 643 #define BSLIP_EN BIT(31) 644 #define EDGE_CHK BIT(30) 645 #define RD_TAP_MASK 0x7f 646 #define RD_TAP(x) ((x) & 0x7f) 647 648 #define MT7530_TRGMII_TXCTRL 0x7a40 649 #define TRAIN_TXEN BIT(31) 650 #define TXC_INV BIT(30) 651 #define TX_RST BIT(28) 652 653 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 654 #define TD_DM_DRVP(x) ((x) & 0xf) 655 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 656 657 #define MT7530_TRGMII_TCK_CTRL 0x7a78 658 #define TCK_TAP(x) (((x) & 0xf) << 8) 659 660 #define MT7530_P5RGMIIRXCR 0x7b00 661 #define CSR_RGMII_EDGE_ALIGN BIT(8) 662 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 663 664 #define MT7530_P5RGMIITXCR 0x7b04 665 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 666 667 /* Registers for GPIO mode */ 668 #define MT7531_GPIO_MODE0 0x7c0c 669 #define MT7531_GPIO0_MASK GENMASK(3, 0) 670 #define MT7531_GPIO0_INTERRUPT 1 671 672 #define MT7531_GPIO_MODE1 0x7c10 673 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 674 #define MT7531_EXT_P_MDC_11 (2 << 12) 675 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 676 #define MT7531_EXT_P_MDIO_12 (2 << 16) 677 678 #define MT753X_CPORT_SPTAG_CFG 0x7c10 679 #define CPORT_SW2FE_STAG_EN BIT(1) 680 #define CPORT_FE2SW_STAG_EN BIT(0) 681 682 #define AN7583_GEPHY_CONN_CFG 0x7c14 683 #define AN7583_CSR_DPHY_CKIN_SEL BIT(31) 684 #define AN7583_CSR_PHY_CORE_REG_CLK_SEL BIT(30) 685 #define AN7583_CSR_ETHER_AFE_PWD GENMASK(28, 24) 686 687 /* Registers for LED GPIO control (MT7530 only) 688 * All registers follow this pattern: 689 * [ 2: 0] port 0 690 * [ 6: 4] port 1 691 * [10: 8] port 2 692 * [14:12] port 3 693 * [18:16] port 4 694 */ 695 696 /* LED enable, 0: Disable, 1: Enable (Default) */ 697 #define MT7530_LED_EN 0x7d00 698 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 699 #define MT7530_LED_IO_MODE 0x7d04 700 /* GPIO direction, 0: Input, 1: Output */ 701 #define MT7530_LED_GPIO_DIR 0x7d10 702 /* GPIO output enable, 0: Disable, 1: Enable */ 703 #define MT7530_LED_GPIO_OE 0x7d14 704 /* GPIO value, 0: Low, 1: High */ 705 #define MT7530_LED_GPIO_DATA 0x7d18 706 707 #define MT7530_CREV 0x7ffc 708 #define CHIP_NAME_SHIFT 16 709 #define MT7530_ID 0x7530 710 711 #define MT7531_CREV 0x781C 712 #define CHIP_REV_M 0x0f 713 #define MT7531_ID 0x7531 714 715 /* Registers for core PLL access through mmd indirect */ 716 #define CORE_PLL_GROUP2 0x401 717 #define RG_SYSPLL_EN_NORMAL BIT(15) 718 #define RG_SYSPLL_VODEN BIT(14) 719 #define RG_SYSPLL_LF BIT(13) 720 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 721 #define RG_SYSPLL_LVROD_EN BIT(10) 722 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 723 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 724 #define RG_SYSPLL_FBKSEL BIT(4) 725 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 726 727 #define CORE_PLL_GROUP4 0x403 728 #define RG_SYSPLL_DDSFBK_EN BIT(12) 729 #define RG_SYSPLL_BIAS_EN BIT(11) 730 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 731 #define MT7531_RG_SYSPLL_DMY2 BIT(6) 732 #define MT7531_PHY_PLL_OFF BIT(5) 733 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 734 735 #define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f) 736 737 #define CORE_PLL_GROUP5 0x404 738 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 739 740 #define CORE_PLL_GROUP6 0x405 741 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 742 743 #define CORE_PLL_GROUP7 0x406 744 #define RG_LCDDS_PWDB BIT(15) 745 #define RG_LCDDS_ISO_EN BIT(13) 746 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 747 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 748 749 #define CORE_PLL_GROUP10 0x409 750 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 751 752 #define CORE_PLL_GROUP11 0x40a 753 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 754 755 #define CORE_GSWPLL_GRP1 0x40d 756 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 757 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 758 #define RG_GSWPLL_EN_PRE BIT(11) 759 #define RG_GSWPLL_FBKSEL BIT(10) 760 #define RG_GSWPLL_BP BIT(9) 761 #define RG_GSWPLL_BR BIT(8) 762 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 763 764 #define CORE_GSWPLL_GRP2 0x40e 765 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 766 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 767 768 #define CORE_TRGMII_GSW_CLK_CG 0x410 769 #define REG_GSWCK_EN BIT(0) 770 #define REG_TRGMIICK_EN BIT(1) 771 772 #define MIB_DESC(_s, _o, _n) \ 773 { \ 774 .size = (_s), \ 775 .offset = (_o), \ 776 .name = (_n), \ 777 } 778 779 struct mt7530_mib_desc { 780 unsigned int size; 781 unsigned int offset; 782 const char *name; 783 }; 784 785 struct mt7530_fdb { 786 u16 vid; 787 u8 port_mask; 788 u8 aging; 789 u8 mac[6]; 790 bool noarp; 791 }; 792 793 /* struct mt7530_port - This is the main data structure for holding the state 794 * of the port. 795 * @enable: The status used for show port is enabled or not. 796 * @pm: The matrix used to show all connections with the port. 797 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 798 * untagged frames will be assigned to the related VLAN. 799 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 800 * @stats: Cached port statistics for MDIO-connected switches 801 */ 802 struct mt7530_port { 803 bool enable; 804 bool isolated; 805 u32 pm; 806 u16 pvid; 807 struct phylink_pcs *sgmii_pcs; 808 struct rtnl_link_stats64 stats; 809 }; 810 811 /* Port 5 mode definitions of the MT7530 switch */ 812 enum mt7530_p5_mode { 813 GMAC5, 814 MUX_PHY_P0, 815 MUX_PHY_P4, 816 }; 817 818 struct mt7530_priv; 819 820 struct mt753x_pcs { 821 struct phylink_pcs pcs; 822 struct mt7530_priv *priv; 823 int port; 824 }; 825 826 /* struct mt753x_info - This is the main data structure for holding the specific 827 * part for each supported device 828 * @id: Holding the identifier to a switch model 829 * @pcs_ops: Holding the pointer to the MAC PCS operations structure 830 * @sw_setup: Holding the handler to a device initialization 831 * @phy_read_c22: Holding the way reading PHY port using C22 832 * @phy_write_c22: Holding the way writing PHY port using C22 833 * @phy_read_c45: Holding the way reading PHY port using C45 834 * @phy_write_c45: Holding the way writing PHY port using C45 835 * @mac_port_get_caps: Holding the handler that provides MAC capabilities 836 * @mac_port_config: Holding the way setting up the PHY attribute to a 837 * certain MAC port 838 */ 839 struct mt753x_info { 840 enum mt753x_id id; 841 842 const struct phylink_pcs_ops *pcs_ops; 843 844 int (*sw_setup)(struct dsa_switch *ds); 845 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 846 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 847 u16 val); 848 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 849 int regnum); 850 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 851 int regnum, u16 val); 852 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 853 struct phylink_config *config); 854 void (*mac_port_config)(struct dsa_switch *ds, int port, 855 unsigned int mode, 856 phy_interface_t interface); 857 }; 858 859 /* struct mt7530_priv - This is the main data structure for holding the state 860 * of the driver 861 * @dev: The device pointer 862 * @ds: The pointer to the dsa core structure 863 * @bus: The bus used for the device and built-in PHY 864 * @regmap: The regmap instance representing all switch registers 865 * @rstc: The pointer to reset control used by MCM 866 * @core_pwr: The power supplied into the core 867 * @io_pwr: The power supplied into the I/O 868 * @reset: The descriptor for GPIO line tied to its reset pin 869 * @mcm: Flag for distinguishing if standalone IC or module 870 * coupling 871 * @ports: Holding the state among ports 872 * @reg_mutex: The lock for protecting among process accessing 873 * registers 874 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch 875 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch 876 * has got SGMII 877 * @irq_domain: IRQ domain of the switch irq_chip 878 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 879 * @active_cpu_ports: Holding the active CPU ports 880 * @mdiodev: The pointer to the MDIO device structure 881 * @stats_lock: Protects cached per-port stats from concurrent access 882 * @stats_work: Delayed work for polling MIB counters on MDIO switches 883 * @stats_last: Jiffies timestamp of last MIB counter poll 884 */ 885 struct mt7530_priv { 886 struct device *dev; 887 struct dsa_switch *ds; 888 struct mii_bus *bus; 889 struct regmap *regmap; 890 struct reset_control *rstc; 891 struct regulator *core_pwr; 892 struct regulator *io_pwr; 893 struct gpio_desc *reset; 894 const struct mt753x_info *info; 895 unsigned int id; 896 bool mcm; 897 enum mt7530_p5_mode p5_mode; 898 bool p5_sgmii; 899 u8 mirror_rx; 900 u8 mirror_tx; 901 struct mt7530_port ports[MT7530_NUM_PORTS]; 902 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 903 /* protect among processes for registers access*/ 904 struct mutex reg_mutex; 905 struct irq_domain *irq_domain; 906 int (*create_sgmii)(struct mt7530_priv *priv); 907 u8 active_cpu_ports; 908 struct mdio_device *mdiodev; 909 spinlock_t stats_lock; /* protects cached stats counters */ 910 struct delayed_work stats_work; 911 unsigned long stats_last; 912 }; 913 914 struct mt7530_hw_vlan_entry { 915 int port; 916 u8 old_members; 917 bool untagged; 918 }; 919 920 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 921 int port, bool untagged) 922 { 923 e->port = port; 924 e->untagged = untagged; 925 } 926 927 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 928 struct mt7530_hw_vlan_entry *); 929 930 struct mt7530_hw_stats { 931 const char *string; 932 u16 reg; 933 u8 sizeof_stat; 934 }; 935 936 struct mt7530_dummy_poll { 937 struct mt7530_priv *priv; 938 u32 reg; 939 }; 940 941 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 942 struct mt7530_priv *priv, u32 reg) 943 { 944 p->priv = priv; 945 p->reg = reg; 946 } 947 948 int mt7530_probe_common(struct mt7530_priv *priv); 949 void mt7530_remove_common(struct mt7530_priv *priv); 950 951 extern const struct mt753x_info mt753x_table[]; 952 953 #endif /* __MT7530_H */ 954