1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 ID_MT7988 = 3, 22 }; 23 24 #define NUM_TRGMII_CTRL 5 25 26 #define TRGMII_BASE(x) (0x10000 + (x)) 27 28 /* Registers to ethsys access */ 29 #define ETHSYS_CLKCFG0 0x2c 30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 31 32 #define SYSC_REG_RSTCTRL 0x34 33 #define RESET_MCM BIT(2) 34 35 /* Register for ARL global control */ 36 #define MT753X_AGC 0xc 37 #define LOCAL_EN BIT(7) 38 39 /* Register for MAC forward control */ 40 #define MT753X_MFC 0x10 41 #define BC_FFP_MASK GENMASK(31, 24) 42 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) 43 #define UNM_FFP_MASK GENMASK(23, 16) 44 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) 45 #define UNU_FFP_MASK GENMASK(15, 8) 46 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) 47 #define MT7530_CPU_EN BIT(7) 48 #define MT7530_CPU_PORT_MASK GENMASK(6, 4) 49 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) 50 #define MT7530_MIRROR_EN BIT(3) 51 #define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) 52 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) 53 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) 54 #define MT7531_QRY_FFP_MASK GENMASK(7, 0) 55 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) 56 57 /* Register for CPU forward control */ 58 #define MT7531_CFC 0x4 59 #define MT7531_MIRROR_EN BIT(19) 60 #define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) 61 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) 62 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) 63 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 64 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 65 66 #define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ 67 id == ID_MT7988) ? \ 68 MT7531_CFC : MT753X_MFC) 69 70 #define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ 71 id == ID_MT7988) ? \ 72 MT7531_MIRROR_EN : MT7530_MIRROR_EN) 73 74 #define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ 75 id == ID_MT7988) ? \ 76 MT7531_MIRROR_PORT_MASK : \ 77 MT7530_MIRROR_PORT_MASK) 78 79 #define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ 80 id == ID_MT7988) ? \ 81 MT7531_MIRROR_PORT_GET(val) : \ 82 MT7530_MIRROR_PORT_GET(val)) 83 84 #define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ 85 id == ID_MT7988) ? \ 86 MT7531_MIRROR_PORT_SET(val) : \ 87 MT7530_MIRROR_PORT_SET(val)) 88 89 /* Register for BPDU and PAE frame control */ 90 #define MT753X_BPC 0x24 91 #define PAE_BPDU_FR BIT(25) 92 #define PAE_EG_TAG_MASK GENMASK(24, 22) 93 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) 94 #define PAE_PORT_FW_MASK GENMASK(18, 16) 95 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) 96 #define BPDU_EG_TAG_MASK GENMASK(8, 6) 97 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) 98 #define BPDU_PORT_FW_MASK GENMASK(2, 0) 99 100 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ 101 #define MT753X_RGAC1 0x28 102 #define R02_BPDU_FR BIT(25) 103 #define R02_EG_TAG_MASK GENMASK(24, 22) 104 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) 105 #define R02_PORT_FW_MASK GENMASK(18, 16) 106 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) 107 #define R01_BPDU_FR BIT(9) 108 #define R01_EG_TAG_MASK GENMASK(8, 6) 109 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) 110 #define R01_PORT_FW_MASK GENMASK(2, 0) 111 112 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ 113 #define MT753X_RGAC2 0x2c 114 #define R0E_BPDU_FR BIT(25) 115 #define R0E_EG_TAG_MASK GENMASK(24, 22) 116 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) 117 #define R0E_PORT_FW_MASK GENMASK(18, 16) 118 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) 119 #define R03_BPDU_FR BIT(9) 120 #define R03_EG_TAG_MASK GENMASK(8, 6) 121 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) 122 #define R03_PORT_FW_MASK GENMASK(2, 0) 123 124 enum mt753x_to_cpu_fw { 125 TO_CPU_FW_SYSTEM_DEFAULT, 126 TO_CPU_FW_CPU_EXCLUDE = 4, 127 TO_CPU_FW_CPU_INCLUDE = 5, 128 TO_CPU_FW_CPU_ONLY = 6, 129 TO_CPU_FW_DROP = 7, 130 }; 131 132 /* Registers for address table access */ 133 #define MT7530_ATA1 0x74 134 #define STATIC_EMP 0 135 #define STATIC_ENT 3 136 #define MT7530_ATA2 0x78 137 #define ATA2_IVL BIT(15) 138 #define ATA2_FID(x) (((x) & 0x7) << 12) 139 140 /* Register for address table write data */ 141 #define MT7530_ATWD 0x7c 142 143 /* Register for address table control */ 144 #define MT7530_ATC 0x80 145 #define ATC_HASH (((x) & 0xfff) << 16) 146 #define ATC_BUSY BIT(15) 147 #define ATC_SRCH_END BIT(14) 148 #define ATC_SRCH_HIT BIT(13) 149 #define ATC_INVALID BIT(12) 150 #define ATC_MAT(x) (((x) & 0xf) << 8) 151 #define ATC_MAT_MACTAB ATC_MAT(0) 152 153 enum mt7530_fdb_cmd { 154 MT7530_FDB_READ = 0, 155 MT7530_FDB_WRITE = 1, 156 MT7530_FDB_FLUSH = 2, 157 MT7530_FDB_START = 4, 158 MT7530_FDB_NEXT = 5, 159 }; 160 161 /* Registers for table search read address */ 162 #define MT7530_TSRA1 0x84 163 #define MAC_BYTE_0 24 164 #define MAC_BYTE_1 16 165 #define MAC_BYTE_2 8 166 #define MAC_BYTE_3 0 167 #define MAC_BYTE_MASK 0xff 168 169 #define MT7530_TSRA2 0x88 170 #define MAC_BYTE_4 24 171 #define MAC_BYTE_5 16 172 #define CVID 0 173 #define CVID_MASK 0xfff 174 175 #define MT7530_ATRD 0x8C 176 #define AGE_TIMER 24 177 #define AGE_TIMER_MASK 0xff 178 #define PORT_MAP 4 179 #define PORT_MAP_MASK 0xff 180 #define ENT_STATUS 2 181 #define ENT_STATUS_MASK 0x3 182 183 /* Register for vlan table control */ 184 #define MT7530_VTCR 0x90 185 #define VTCR_BUSY BIT(31) 186 #define VTCR_INVALID BIT(16) 187 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 188 #define VTCR_VID ((x) & 0xfff) 189 190 enum mt7530_vlan_cmd { 191 /* Read/Write the specified VID entry from VAWD register based 192 * on VID. 193 */ 194 MT7530_VTCR_RD_VID = 0, 195 MT7530_VTCR_WR_VID = 1, 196 }; 197 198 /* Register for setup vlan and acl write data */ 199 #define MT7530_VAWD1 0x94 200 #define PORT_STAG BIT(31) 201 /* Independent VLAN Learning */ 202 #define IVL_MAC BIT(30) 203 /* Egress Tag Consistent */ 204 #define EG_CON BIT(29) 205 /* Per VLAN Egress Tag Control */ 206 #define VTAG_EN BIT(28) 207 /* VLAN Member Control */ 208 #define PORT_MEM(x) (((x) & 0xff) << 16) 209 /* Filter ID */ 210 #define FID(x) (((x) & 0x7) << 1) 211 /* VLAN Entry Valid */ 212 #define VLAN_VALID BIT(0) 213 #define PORT_MEM_SHFT 16 214 #define PORT_MEM_MASK 0xff 215 216 enum mt7530_fid { 217 FID_STANDALONE = 0, 218 FID_BRIDGED = 1, 219 }; 220 221 #define MT7530_VAWD2 0x98 222 /* Egress Tag Control */ 223 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 224 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 225 226 enum mt7530_vlan_egress_attr { 227 MT7530_VLAN_EGRESS_UNTAG = 0, 228 MT7530_VLAN_EGRESS_TAG = 2, 229 MT7530_VLAN_EGRESS_STACK = 3, 230 }; 231 232 /* Register for address age control */ 233 #define MT7530_AAC 0xa0 234 /* Disable ageing */ 235 #define AGE_DIS BIT(20) 236 /* Age count */ 237 #define AGE_CNT_MASK GENMASK(19, 12) 238 #define AGE_CNT_MAX 0xff 239 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 240 /* Age unit */ 241 #define AGE_UNIT_MASK GENMASK(11, 0) 242 #define AGE_UNIT_MAX 0xfff 243 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 244 245 /* Register for port STP state control */ 246 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 247 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 248 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 249 250 enum mt7530_stp_state { 251 MT7530_STP_DISABLED = 0, 252 MT7530_STP_BLOCKING = 1, 253 MT7530_STP_LISTENING = 1, 254 MT7530_STP_LEARNING = 2, 255 MT7530_STP_FORWARDING = 3 256 }; 257 258 /* Register for port control */ 259 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 260 #define PORT_TX_MIR BIT(9) 261 #define PORT_RX_MIR BIT(8) 262 #define PORT_VLAN(x) ((x) & 0x3) 263 264 enum mt7530_port_mode { 265 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 266 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 267 268 /* Fallback Mode: Forward received frames with ingress ports that do 269 * not belong to the VLAN member. Frames whose VID is not listed on 270 * the VLAN table are forwarded by the PCR_MATRIX members. 271 */ 272 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 273 274 /* Security Mode: Discard any frame due to ingress membership 275 * violation or VID missed on the VLAN table. 276 */ 277 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 278 }; 279 280 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 281 #define PORT_PRI(x) (((x) & 0x7) << 24) 282 #define EG_TAG(x) (((x) & 0x3) << 28) 283 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 284 #define PCR_MATRIX_CLR PCR_MATRIX(0) 285 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 286 287 /* Register for port security control */ 288 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 289 #define SA_DIS BIT(4) 290 291 /* Register for port vlan control */ 292 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 293 #define PORT_SPEC_TAG BIT(5) 294 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 295 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 296 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 297 #define VLAN_ATTR_MASK VLAN_ATTR(3) 298 #define ACC_FRM_MASK GENMASK(1, 0) 299 300 enum mt7530_vlan_port_eg_tag { 301 MT7530_VLAN_EG_DISABLED = 0, 302 MT7530_VLAN_EG_CONSISTENT = 1, 303 MT7530_VLAN_EG_UNTAGGED = 4, 304 }; 305 306 enum mt7530_vlan_port_attr { 307 MT7530_VLAN_USER = 0, 308 MT7530_VLAN_TRANSPARENT = 3, 309 }; 310 311 enum mt7530_vlan_port_acc_frm { 312 MT7530_VLAN_ACC_ALL = 0, 313 MT7530_VLAN_ACC_TAGGED = 1, 314 MT7530_VLAN_ACC_UNTAGGED = 2, 315 }; 316 317 #define STAG_VPID (((x) & 0xffff) << 16) 318 319 /* Register for port port-and-protocol based vlan 1 control */ 320 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 321 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 322 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 323 #define G0_PORT_VID_DEF G0_PORT_VID(0) 324 325 /* Register for port MAC control register */ 326 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) 327 #define PMCR_IFG_XMIT_MASK GENMASK(19, 18) 328 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) 329 #define PMCR_EXT_PHY BIT(17) 330 #define PMCR_MAC_MODE BIT(16) 331 #define MT7530_FORCE_MODE BIT(15) 332 #define PMCR_MAC_TX_EN BIT(14) 333 #define PMCR_MAC_RX_EN BIT(13) 334 #define PMCR_BACKOFF_EN BIT(9) 335 #define PMCR_BACKPR_EN BIT(8) 336 #define PMCR_FORCE_EEE1G BIT(7) 337 #define PMCR_FORCE_EEE100 BIT(6) 338 #define PMCR_FORCE_RX_FC_EN BIT(5) 339 #define PMCR_FORCE_TX_FC_EN BIT(4) 340 #define PMCR_FORCE_SPEED_1000 BIT(3) 341 #define PMCR_FORCE_SPEED_100 BIT(2) 342 #define PMCR_FORCE_FDX BIT(1) 343 #define PMCR_FORCE_LNK BIT(0) 344 #define MT7531_FORCE_MODE_LNK BIT(31) 345 #define MT7531_FORCE_MODE_SPD BIT(30) 346 #define MT7531_FORCE_MODE_DPX BIT(29) 347 #define MT7531_FORCE_MODE_RX_FC BIT(28) 348 #define MT7531_FORCE_MODE_TX_FC BIT(27) 349 #define MT7531_FORCE_MODE_EEE100 BIT(26) 350 #define MT7531_FORCE_MODE_EEE1G BIT(25) 351 #define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ 352 MT7531_FORCE_MODE_SPD | \ 353 MT7531_FORCE_MODE_DPX | \ 354 MT7531_FORCE_MODE_RX_FC | \ 355 MT7531_FORCE_MODE_TX_FC | \ 356 MT7531_FORCE_MODE_EEE100 | \ 357 MT7531_FORCE_MODE_EEE1G) 358 #define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ 359 PMCR_FORCE_EEE1G | \ 360 PMCR_FORCE_EEE100 | \ 361 PMCR_FORCE_RX_FC_EN | \ 362 PMCR_FORCE_TX_FC_EN | \ 363 PMCR_FORCE_SPEED_1000 | \ 364 PMCR_FORCE_SPEED_100 | \ 365 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 366 367 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) 368 #define WAKEUP_TIME_1000_MASK GENMASK(31, 24) 369 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) 370 #define WAKEUP_TIME_100_MASK GENMASK(23, 16) 371 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) 372 #define LPI_THRESH_MASK GENMASK(15, 4) 373 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) 374 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) 375 #define LPI_MODE_EN BIT(0) 376 377 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 378 #define PMSR_EEE1G BIT(7) 379 #define PMSR_EEE100M BIT(6) 380 #define PMSR_RX_FC BIT(5) 381 #define PMSR_TX_FC BIT(4) 382 #define PMSR_SPEED_1000 BIT(3) 383 #define PMSR_SPEED_100 BIT(2) 384 #define PMSR_SPEED_10 0x00 385 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 386 #define PMSR_DPX BIT(1) 387 #define PMSR_LINK BIT(0) 388 389 /* Register for port debug count */ 390 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 391 #define MT7531_DIS_CLR BIT(31) 392 393 #define MT7530_GMACCR 0x30e0 394 #define MAX_RX_JUMBO(x) ((x) << 2) 395 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 396 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 397 #define MAX_RX_PKT_LEN_1522 0x0 398 #define MAX_RX_PKT_LEN_1536 0x1 399 #define MAX_RX_PKT_LEN_1552 0x2 400 #define MAX_RX_PKT_LEN_JUMBO 0x3 401 402 /* Register for MIB */ 403 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 404 #define MT7530_MIB_CCR 0x4fe0 405 #define CCR_MIB_ENABLE BIT(31) 406 #define CCR_RX_OCT_CNT_GOOD BIT(7) 407 #define CCR_RX_OCT_CNT_BAD BIT(6) 408 #define CCR_TX_OCT_CNT_GOOD BIT(5) 409 #define CCR_TX_OCT_CNT_BAD BIT(4) 410 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 411 CCR_RX_OCT_CNT_BAD | \ 412 CCR_TX_OCT_CNT_GOOD | \ 413 CCR_TX_OCT_CNT_BAD) 414 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 415 CCR_RX_OCT_CNT_GOOD | \ 416 CCR_RX_OCT_CNT_BAD | \ 417 CCR_TX_OCT_CNT_GOOD | \ 418 CCR_TX_OCT_CNT_BAD) 419 420 /* MT7531 SGMII register group */ 421 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 422 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 423 424 /* Register for system reset */ 425 #define MT7530_SYS_CTRL 0x7000 426 #define SYS_CTRL_PHY_RST BIT(2) 427 #define SYS_CTRL_SW_RST BIT(1) 428 #define SYS_CTRL_REG_RST BIT(0) 429 430 /* Register for system interrupt */ 431 #define MT7530_SYS_INT_EN 0x7008 432 433 /* Register for system interrupt status */ 434 #define MT7530_SYS_INT_STS 0x700c 435 436 /* Register for PHY Indirect Access Control */ 437 #define MT7531_PHY_IAC 0x701C 438 #define MT7531_PHY_ACS_ST BIT(31) 439 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 440 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 441 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 442 #define MT7531_MDIO_ST_MASK (0x3 << 16) 443 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 444 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 445 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 446 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 447 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 448 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 449 450 enum mt7531_phy_iac_cmd { 451 MT7531_MDIO_ADDR = 0, 452 MT7531_MDIO_WRITE = 1, 453 MT7531_MDIO_READ = 2, 454 MT7531_MDIO_READ_CL45 = 3, 455 }; 456 457 /* MDIO_ST: MDIO start field */ 458 enum mt7531_mdio_st { 459 MT7531_MDIO_ST_CL45 = 0, 460 MT7531_MDIO_ST_CL22 = 1, 461 }; 462 463 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 464 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 465 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 466 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 467 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 468 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 469 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 470 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 471 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 472 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 473 474 /* Register for RGMII clock phase */ 475 #define MT7531_CLKGEN_CTRL 0x7500 476 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 477 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 478 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 479 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 480 #define RXCLK_NO_DELAY BIT(5) 481 #define TXCLK_NO_REVERSE BIT(4) 482 #define GP_MODE(x) (((x) & 0x3) << 1) 483 #define GP_MODE_MASK GENMASK(2, 1) 484 #define GP_CLK_EN BIT(0) 485 486 enum mt7531_gp_mode { 487 MT7531_GP_MODE_RGMII = 0, 488 MT7531_GP_MODE_MII = 1, 489 MT7531_GP_MODE_REV_MII = 2 490 }; 491 492 enum mt7531_clk_skew { 493 MT7531_CLK_SKEW_NO_CHG = 0, 494 MT7531_CLK_SKEW_DLY_100PPS = 1, 495 MT7531_CLK_SKEW_DLY_200PPS = 2, 496 MT7531_CLK_SKEW_REVERSE = 3, 497 }; 498 499 /* Register for trap status */ 500 #define MT753X_TRAP 0x7800 501 #define MT7530_XTAL_MASK (BIT(10) | BIT(9)) 502 #define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) 503 #define MT7530_XTAL_40MHZ BIT(10) 504 #define MT7530_XTAL_20MHZ BIT(9) 505 #define MT7531_XTAL25 BIT(7) 506 507 /* Register for trap modification */ 508 #define MT753X_MTRAP 0x7804 509 #define MT7530_P5_PHY0_SEL BIT(20) 510 #define MT7530_CHG_TRAP BIT(16) 511 #define MT7530_P5_MAC_SEL BIT(13) 512 #define MT7530_P6_DIS BIT(8) 513 #define MT7530_P5_RGMII_MODE BIT(7) 514 #define MT7530_P5_DIS BIT(6) 515 #define MT7530_PHY_INDIRECT_ACCESS BIT(5) 516 #define MT7531_CHG_STRAP BIT(8) 517 #define MT7531_PHY_EN BIT(6) 518 519 enum mt7531_xtal_fsel { 520 MT7531_XTAL_FSEL_25MHZ, 521 MT7531_XTAL_FSEL_40MHZ, 522 }; 523 524 /* Register for TOP signal control */ 525 #define MT7530_TOP_SIG_CTRL 0x7808 526 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 527 528 #define MT7531_TOP_SIG_SR 0x780c 529 #define PAD_DUAL_SGMII_EN BIT(1) 530 #define PAD_MCM_SMI_EN BIT(0) 531 532 #define MT7530_IO_DRV_CR 0x7810 533 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 534 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 535 536 #define MT7531_CHIP_REV 0x781C 537 538 #define MT7531_PLLGP_EN 0x7820 539 #define EN_COREPLL BIT(2) 540 #define SW_CLKSW BIT(1) 541 #define SW_PLLGP BIT(0) 542 543 #define MT7530_P6ECR 0x7830 544 #define P6_INTF_MODE_MASK 0x3 545 #define P6_INTF_MODE(x) ((x) & 0x3) 546 547 #define MT7531_PLLGP_CR0 0x78a8 548 #define RG_COREPLL_EN BIT(22) 549 #define RG_COREPLL_POSDIV_S 23 550 #define RG_COREPLL_POSDIV_M 0x3800000 551 #define RG_COREPLL_SDM_PCW_S 1 552 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 553 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 554 555 /* Registers for RGMII and SGMII PLL clock */ 556 #define MT7531_ANA_PLLGP_CR2 0x78b0 557 #define MT7531_ANA_PLLGP_CR5 0x78bc 558 559 /* Registers for TRGMII on the both side */ 560 #define MT7530_TRGMII_RCK_CTRL 0x7a00 561 #define RX_RST BIT(31) 562 #define RXC_DQSISEL BIT(30) 563 #define DQSI1_TAP_MASK (0x7f << 8) 564 #define DQSI0_TAP_MASK 0x7f 565 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 566 #define DQSI0_TAP(x) ((x) & 0x7f) 567 568 #define MT7530_TRGMII_RCK_RTT 0x7a04 569 #define DQS1_GATE BIT(31) 570 #define DQS0_GATE BIT(30) 571 572 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 573 #define BSLIP_EN BIT(31) 574 #define EDGE_CHK BIT(30) 575 #define RD_TAP_MASK 0x7f 576 #define RD_TAP(x) ((x) & 0x7f) 577 578 #define MT7530_TRGMII_TXCTRL 0x7a40 579 #define TRAIN_TXEN BIT(31) 580 #define TXC_INV BIT(30) 581 #define TX_RST BIT(28) 582 583 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 584 #define TD_DM_DRVP(x) ((x) & 0xf) 585 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 586 587 #define MT7530_TRGMII_TCK_CTRL 0x7a78 588 #define TCK_TAP(x) (((x) & 0xf) << 8) 589 590 #define MT7530_P5RGMIIRXCR 0x7b00 591 #define CSR_RGMII_EDGE_ALIGN BIT(8) 592 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 593 594 #define MT7530_P5RGMIITXCR 0x7b04 595 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 596 597 /* Registers for GPIO mode */ 598 #define MT7531_GPIO_MODE0 0x7c0c 599 #define MT7531_GPIO0_MASK GENMASK(3, 0) 600 #define MT7531_GPIO0_INTERRUPT 1 601 602 #define MT7531_GPIO_MODE1 0x7c10 603 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 604 #define MT7531_EXT_P_MDC_11 (2 << 12) 605 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 606 #define MT7531_EXT_P_MDIO_12 (2 << 16) 607 608 /* Registers for LED GPIO control (MT7530 only) 609 * All registers follow this pattern: 610 * [ 2: 0] port 0 611 * [ 6: 4] port 1 612 * [10: 8] port 2 613 * [14:12] port 3 614 * [18:16] port 4 615 */ 616 617 /* LED enable, 0: Disable, 1: Enable (Default) */ 618 #define MT7530_LED_EN 0x7d00 619 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 620 #define MT7530_LED_IO_MODE 0x7d04 621 /* GPIO direction, 0: Input, 1: Output */ 622 #define MT7530_LED_GPIO_DIR 0x7d10 623 /* GPIO output enable, 0: Disable, 1: Enable */ 624 #define MT7530_LED_GPIO_OE 0x7d14 625 /* GPIO value, 0: Low, 1: High */ 626 #define MT7530_LED_GPIO_DATA 0x7d18 627 628 #define MT7530_CREV 0x7ffc 629 #define CHIP_NAME_SHIFT 16 630 #define MT7530_ID 0x7530 631 632 #define MT7531_CREV 0x781C 633 #define CHIP_REV_M 0x0f 634 #define MT7531_ID 0x7531 635 636 /* Registers for core PLL access through mmd indirect */ 637 #define CORE_PLL_GROUP2 0x401 638 #define RG_SYSPLL_EN_NORMAL BIT(15) 639 #define RG_SYSPLL_VODEN BIT(14) 640 #define RG_SYSPLL_LF BIT(13) 641 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 642 #define RG_SYSPLL_LVROD_EN BIT(10) 643 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 644 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 645 #define RG_SYSPLL_FBKSEL BIT(4) 646 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 647 648 #define CORE_PLL_GROUP4 0x403 649 #define RG_SYSPLL_DDSFBK_EN BIT(12) 650 #define RG_SYSPLL_BIAS_EN BIT(11) 651 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 652 #define MT7531_RG_SYSPLL_DMY2 BIT(6) 653 #define MT7531_PHY_PLL_OFF BIT(5) 654 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 655 656 #define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f) 657 658 #define CORE_PLL_GROUP5 0x404 659 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 660 661 #define CORE_PLL_GROUP6 0x405 662 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 663 664 #define CORE_PLL_GROUP7 0x406 665 #define RG_LCDDS_PWDB BIT(15) 666 #define RG_LCDDS_ISO_EN BIT(13) 667 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 668 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 669 670 #define CORE_PLL_GROUP10 0x409 671 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 672 673 #define CORE_PLL_GROUP11 0x40a 674 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 675 676 #define CORE_GSWPLL_GRP1 0x40d 677 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 678 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 679 #define RG_GSWPLL_EN_PRE BIT(11) 680 #define RG_GSWPLL_FBKSEL BIT(10) 681 #define RG_GSWPLL_BP BIT(9) 682 #define RG_GSWPLL_BR BIT(8) 683 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 684 685 #define CORE_GSWPLL_GRP2 0x40e 686 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 687 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 688 689 #define CORE_TRGMII_GSW_CLK_CG 0x410 690 #define REG_GSWCK_EN BIT(0) 691 #define REG_TRGMIICK_EN BIT(1) 692 693 #define MIB_DESC(_s, _o, _n) \ 694 { \ 695 .size = (_s), \ 696 .offset = (_o), \ 697 .name = (_n), \ 698 } 699 700 struct mt7530_mib_desc { 701 unsigned int size; 702 unsigned int offset; 703 const char *name; 704 }; 705 706 struct mt7530_fdb { 707 u16 vid; 708 u8 port_mask; 709 u8 aging; 710 u8 mac[6]; 711 bool noarp; 712 }; 713 714 /* struct mt7530_port - This is the main data structure for holding the state 715 * of the port. 716 * @enable: The status used for show port is enabled or not. 717 * @pm: The matrix used to show all connections with the port. 718 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 719 * untagged frames will be assigned to the related VLAN. 720 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 721 */ 722 struct mt7530_port { 723 bool enable; 724 u32 pm; 725 u16 pvid; 726 struct phylink_pcs *sgmii_pcs; 727 }; 728 729 /* Port 5 mode definitions of the MT7530 switch */ 730 enum mt7530_p5_mode { 731 GMAC5, 732 MUX_PHY_P0, 733 MUX_PHY_P4, 734 }; 735 736 struct mt7530_priv; 737 738 struct mt753x_pcs { 739 struct phylink_pcs pcs; 740 struct mt7530_priv *priv; 741 int port; 742 }; 743 744 /* struct mt753x_info - This is the main data structure for holding the specific 745 * part for each supported device 746 * @id: Holding the identifier to a switch model 747 * @pcs_ops: Holding the pointer to the MAC PCS operations structure 748 * @sw_setup: Holding the handler to a device initialization 749 * @phy_read_c22: Holding the way reading PHY port using C22 750 * @phy_write_c22: Holding the way writing PHY port using C22 751 * @phy_read_c45: Holding the way reading PHY port using C45 752 * @phy_write_c45: Holding the way writing PHY port using C45 753 * @mac_port_get_caps: Holding the handler that provides MAC capabilities 754 * @mac_port_config: Holding the way setting up the PHY attribute to a 755 * certain MAC port 756 */ 757 struct mt753x_info { 758 enum mt753x_id id; 759 760 const struct phylink_pcs_ops *pcs_ops; 761 762 int (*sw_setup)(struct dsa_switch *ds); 763 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 764 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 765 u16 val); 766 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 767 int regnum); 768 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 769 int regnum, u16 val); 770 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 771 struct phylink_config *config); 772 void (*mac_port_config)(struct dsa_switch *ds, int port, 773 unsigned int mode, 774 phy_interface_t interface); 775 }; 776 777 /* struct mt7530_priv - This is the main data structure for holding the state 778 * of the driver 779 * @dev: The device pointer 780 * @ds: The pointer to the dsa core structure 781 * @bus: The bus used for the device and built-in PHY 782 * @regmap: The regmap instance representing all switch registers 783 * @rstc: The pointer to reset control used by MCM 784 * @core_pwr: The power supplied into the core 785 * @io_pwr: The power supplied into the I/O 786 * @reset: The descriptor for GPIO line tied to its reset pin 787 * @mcm: Flag for distinguishing if standalone IC or module 788 * coupling 789 * @ports: Holding the state among ports 790 * @reg_mutex: The lock for protecting among process accessing 791 * registers 792 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch 793 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch 794 * has got SGMII 795 * @irq: IRQ number of the switch 796 * @irq_domain: IRQ domain of the switch irq_chip 797 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN 798 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 799 * @active_cpu_ports: Holding the active CPU ports 800 * @mdiodev: The pointer to the MDIO device structure 801 */ 802 struct mt7530_priv { 803 struct device *dev; 804 struct dsa_switch *ds; 805 struct mii_bus *bus; 806 struct regmap *regmap; 807 struct reset_control *rstc; 808 struct regulator *core_pwr; 809 struct regulator *io_pwr; 810 struct gpio_desc *reset; 811 const struct mt753x_info *info; 812 unsigned int id; 813 bool mcm; 814 enum mt7530_p5_mode p5_mode; 815 bool p5_sgmii; 816 u8 mirror_rx; 817 u8 mirror_tx; 818 struct mt7530_port ports[MT7530_NUM_PORTS]; 819 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 820 /* protect among processes for registers access*/ 821 struct mutex reg_mutex; 822 int irq; 823 struct irq_domain *irq_domain; 824 u32 irq_enable; 825 int (*create_sgmii)(struct mt7530_priv *priv); 826 u8 active_cpu_ports; 827 struct mdio_device *mdiodev; 828 }; 829 830 struct mt7530_hw_vlan_entry { 831 int port; 832 u8 old_members; 833 bool untagged; 834 }; 835 836 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 837 int port, bool untagged) 838 { 839 e->port = port; 840 e->untagged = untagged; 841 } 842 843 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 844 struct mt7530_hw_vlan_entry *); 845 846 struct mt7530_hw_stats { 847 const char *string; 848 u16 reg; 849 u8 sizeof_stat; 850 }; 851 852 struct mt7530_dummy_poll { 853 struct mt7530_priv *priv; 854 u32 reg; 855 }; 856 857 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 858 struct mt7530_priv *priv, u32 reg) 859 { 860 p->priv = priv; 861 p->reg = reg; 862 } 863 864 int mt7530_probe_common(struct mt7530_priv *priv); 865 void mt7530_remove_common(struct mt7530_priv *priv); 866 867 extern const struct dsa_switch_ops mt7530_switch_ops; 868 extern const struct mt753x_info mt753x_table[]; 869 870 #endif /* __MT7530_H */ 871