1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_CPU_PORT 6 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 enum { 15 ID_MT7530 = 0, 16 ID_MT7621 = 1, 17 }; 18 19 #define NUM_TRGMII_CTRL 5 20 21 #define TRGMII_BASE(x) (0x10000 + (x)) 22 23 /* Registers to ethsys access */ 24 #define ETHSYS_CLKCFG0 0x2c 25 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 26 27 #define SYSC_REG_RSTCTRL 0x34 28 #define RESET_MCM BIT(2) 29 30 /* Registers to mac forward control for unknown frames */ 31 #define MT7530_MFC 0x10 32 #define BC_FFP(x) (((x) & 0xff) << 24) 33 #define UNM_FFP(x) (((x) & 0xff) << 16) 34 #define UNU_FFP(x) (((x) & 0xff) << 8) 35 #define UNU_FFP_MASK UNU_FFP(~0) 36 #define CPU_EN BIT(7) 37 #define CPU_PORT(x) ((x) << 4) 38 #define CPU_MASK (0xf << 4) 39 #define MIRROR_EN BIT(3) 40 #define MIRROR_PORT(x) ((x) & 0x7) 41 #define MIRROR_MASK 0x7 42 43 /* Registers for address table access */ 44 #define MT7530_ATA1 0x74 45 #define STATIC_EMP 0 46 #define STATIC_ENT 3 47 #define MT7530_ATA2 0x78 48 49 /* Register for address table write data */ 50 #define MT7530_ATWD 0x7c 51 52 /* Register for address table control */ 53 #define MT7530_ATC 0x80 54 #define ATC_HASH (((x) & 0xfff) << 16) 55 #define ATC_BUSY BIT(15) 56 #define ATC_SRCH_END BIT(14) 57 #define ATC_SRCH_HIT BIT(13) 58 #define ATC_INVALID BIT(12) 59 #define ATC_MAT(x) (((x) & 0xf) << 8) 60 #define ATC_MAT_MACTAB ATC_MAT(0) 61 62 enum mt7530_fdb_cmd { 63 MT7530_FDB_READ = 0, 64 MT7530_FDB_WRITE = 1, 65 MT7530_FDB_FLUSH = 2, 66 MT7530_FDB_START = 4, 67 MT7530_FDB_NEXT = 5, 68 }; 69 70 /* Registers for table search read address */ 71 #define MT7530_TSRA1 0x84 72 #define MAC_BYTE_0 24 73 #define MAC_BYTE_1 16 74 #define MAC_BYTE_2 8 75 #define MAC_BYTE_3 0 76 #define MAC_BYTE_MASK 0xff 77 78 #define MT7530_TSRA2 0x88 79 #define MAC_BYTE_4 24 80 #define MAC_BYTE_5 16 81 #define CVID 0 82 #define CVID_MASK 0xfff 83 84 #define MT7530_ATRD 0x8C 85 #define AGE_TIMER 24 86 #define AGE_TIMER_MASK 0xff 87 #define PORT_MAP 4 88 #define PORT_MAP_MASK 0xff 89 #define ENT_STATUS 2 90 #define ENT_STATUS_MASK 0x3 91 92 /* Register for vlan table control */ 93 #define MT7530_VTCR 0x90 94 #define VTCR_BUSY BIT(31) 95 #define VTCR_INVALID BIT(16) 96 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 97 #define VTCR_VID ((x) & 0xfff) 98 99 enum mt7530_vlan_cmd { 100 /* Read/Write the specified VID entry from VAWD register based 101 * on VID. 102 */ 103 MT7530_VTCR_RD_VID = 0, 104 MT7530_VTCR_WR_VID = 1, 105 }; 106 107 /* Register for setup vlan and acl write data */ 108 #define MT7530_VAWD1 0x94 109 #define PORT_STAG BIT(31) 110 /* Independent VLAN Learning */ 111 #define IVL_MAC BIT(30) 112 /* Per VLAN Egress Tag Control */ 113 #define VTAG_EN BIT(28) 114 /* VLAN Member Control */ 115 #define PORT_MEM(x) (((x) & 0xff) << 16) 116 /* VLAN Entry Valid */ 117 #define VLAN_VALID BIT(0) 118 #define PORT_MEM_SHFT 16 119 #define PORT_MEM_MASK 0xff 120 121 #define MT7530_VAWD2 0x98 122 /* Egress Tag Control */ 123 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 124 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 125 126 enum mt7530_vlan_egress_attr { 127 MT7530_VLAN_EGRESS_UNTAG = 0, 128 MT7530_VLAN_EGRESS_TAG = 2, 129 MT7530_VLAN_EGRESS_STACK = 3, 130 }; 131 132 /* Register for port STP state control */ 133 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 134 #define FID_PST(x) ((x) & 0x3) 135 #define FID_PST_MASK FID_PST(0x3) 136 137 enum mt7530_stp_state { 138 MT7530_STP_DISABLED = 0, 139 MT7530_STP_BLOCKING = 1, 140 MT7530_STP_LISTENING = 1, 141 MT7530_STP_LEARNING = 2, 142 MT7530_STP_FORWARDING = 3 143 }; 144 145 /* Register for port control */ 146 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 147 #define PORT_TX_MIR BIT(9) 148 #define PORT_RX_MIR BIT(8) 149 #define PORT_VLAN(x) ((x) & 0x3) 150 151 enum mt7530_port_mode { 152 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 153 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 154 155 /* Fallback Mode: Forward received frames with ingress ports that do 156 * not belong to the VLAN member. Frames whose VID is not listed on 157 * the VLAN table are forwarded by the PCR_MATRIX members. 158 */ 159 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 160 161 /* Security Mode: Discard any frame due to ingress membership 162 * violation or VID missed on the VLAN table. 163 */ 164 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 165 }; 166 167 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 168 #define PORT_PRI(x) (((x) & 0x7) << 24) 169 #define EG_TAG(x) (((x) & 0x3) << 28) 170 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 171 #define PCR_MATRIX_CLR PCR_MATRIX(0) 172 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 173 174 /* Register for port security control */ 175 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 176 #define SA_DIS BIT(4) 177 178 /* Register for port vlan control */ 179 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 180 #define PORT_SPEC_TAG BIT(5) 181 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 182 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 183 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 184 #define VLAN_ATTR_MASK VLAN_ATTR(3) 185 186 enum mt7530_vlan_port_eg_tag { 187 MT7530_VLAN_EG_DISABLED = 0, 188 MT7530_VLAN_EG_CONSISTENT = 1, 189 }; 190 191 enum mt7530_vlan_port_attr { 192 MT7530_VLAN_USER = 0, 193 MT7530_VLAN_TRANSPARENT = 3, 194 }; 195 196 #define STAG_VPID (((x) & 0xffff) << 16) 197 198 /* Register for port port-and-protocol based vlan 1 control */ 199 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 200 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 201 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 202 #define G0_PORT_VID_DEF G0_PORT_VID(1) 203 204 /* Register for port MAC control register */ 205 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 206 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 207 #define PMCR_EXT_PHY BIT(17) 208 #define PMCR_MAC_MODE BIT(16) 209 #define PMCR_FORCE_MODE BIT(15) 210 #define PMCR_TX_EN BIT(14) 211 #define PMCR_RX_EN BIT(13) 212 #define PMCR_BACKOFF_EN BIT(9) 213 #define PMCR_BACKPR_EN BIT(8) 214 #define PMCR_TX_FC_EN BIT(5) 215 #define PMCR_RX_FC_EN BIT(4) 216 #define PMCR_FORCE_SPEED_1000 BIT(3) 217 #define PMCR_FORCE_SPEED_100 BIT(2) 218 #define PMCR_FORCE_FDX BIT(1) 219 #define PMCR_FORCE_LNK BIT(0) 220 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 221 PMCR_FORCE_SPEED_1000) 222 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 223 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 224 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 225 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 226 227 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 228 #define PMSR_EEE1G BIT(7) 229 #define PMSR_EEE100M BIT(6) 230 #define PMSR_RX_FC BIT(5) 231 #define PMSR_TX_FC BIT(4) 232 #define PMSR_SPEED_1000 BIT(3) 233 #define PMSR_SPEED_100 BIT(2) 234 #define PMSR_SPEED_10 0x00 235 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 236 #define PMSR_DPX BIT(1) 237 #define PMSR_LINK BIT(0) 238 239 /* Register for MIB */ 240 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 241 #define MT7530_MIB_CCR 0x4fe0 242 #define CCR_MIB_ENABLE BIT(31) 243 #define CCR_RX_OCT_CNT_GOOD BIT(7) 244 #define CCR_RX_OCT_CNT_BAD BIT(6) 245 #define CCR_TX_OCT_CNT_GOOD BIT(5) 246 #define CCR_TX_OCT_CNT_BAD BIT(4) 247 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 248 CCR_RX_OCT_CNT_BAD | \ 249 CCR_TX_OCT_CNT_GOOD | \ 250 CCR_TX_OCT_CNT_BAD) 251 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 252 CCR_RX_OCT_CNT_GOOD | \ 253 CCR_RX_OCT_CNT_BAD | \ 254 CCR_TX_OCT_CNT_GOOD | \ 255 CCR_TX_OCT_CNT_BAD) 256 /* Register for system reset */ 257 #define MT7530_SYS_CTRL 0x7000 258 #define SYS_CTRL_PHY_RST BIT(2) 259 #define SYS_CTRL_SW_RST BIT(1) 260 #define SYS_CTRL_REG_RST BIT(0) 261 262 /* Register for hw trap status */ 263 #define MT7530_HWTRAP 0x7800 264 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 265 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 266 #define HWTRAP_XTAL_40MHZ (BIT(10)) 267 #define HWTRAP_XTAL_20MHZ (BIT(9)) 268 269 /* Register for hw trap modification */ 270 #define MT7530_MHWTRAP 0x7804 271 #define MHWTRAP_PHY0_SEL BIT(20) 272 #define MHWTRAP_MANUAL BIT(16) 273 #define MHWTRAP_P5_MAC_SEL BIT(13) 274 #define MHWTRAP_P6_DIS BIT(8) 275 #define MHWTRAP_P5_RGMII_MODE BIT(7) 276 #define MHWTRAP_P5_DIS BIT(6) 277 #define MHWTRAP_PHY_ACCESS BIT(5) 278 279 /* Register for TOP signal control */ 280 #define MT7530_TOP_SIG_CTRL 0x7808 281 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 282 283 #define MT7530_IO_DRV_CR 0x7810 284 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 285 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 286 287 #define MT7530_P6ECR 0x7830 288 #define P6_INTF_MODE_MASK 0x3 289 #define P6_INTF_MODE(x) ((x) & 0x3) 290 291 /* Registers for TRGMII on the both side */ 292 #define MT7530_TRGMII_RCK_CTRL 0x7a00 293 #define RX_RST BIT(31) 294 #define RXC_DQSISEL BIT(30) 295 #define DQSI1_TAP_MASK (0x7f << 8) 296 #define DQSI0_TAP_MASK 0x7f 297 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 298 #define DQSI0_TAP(x) ((x) & 0x7f) 299 300 #define MT7530_TRGMII_RCK_RTT 0x7a04 301 #define DQS1_GATE BIT(31) 302 #define DQS0_GATE BIT(30) 303 304 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 305 #define BSLIP_EN BIT(31) 306 #define EDGE_CHK BIT(30) 307 #define RD_TAP_MASK 0x7f 308 #define RD_TAP(x) ((x) & 0x7f) 309 310 #define MT7530_TRGMII_TXCTRL 0x7a40 311 #define TRAIN_TXEN BIT(31) 312 #define TXC_INV BIT(30) 313 #define TX_RST BIT(28) 314 315 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 316 #define TD_DM_DRVP(x) ((x) & 0xf) 317 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 318 319 #define MT7530_TRGMII_TCK_CTRL 0x7a78 320 #define TCK_TAP(x) (((x) & 0xf) << 8) 321 322 #define MT7530_P5RGMIIRXCR 0x7b00 323 #define CSR_RGMII_EDGE_ALIGN BIT(8) 324 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 325 326 #define MT7530_P5RGMIITXCR 0x7b04 327 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 328 329 #define MT7530_CREV 0x7ffc 330 #define CHIP_NAME_SHIFT 16 331 #define MT7530_ID 0x7530 332 333 /* Registers for core PLL access through mmd indirect */ 334 #define CORE_PLL_GROUP2 0x401 335 #define RG_SYSPLL_EN_NORMAL BIT(15) 336 #define RG_SYSPLL_VODEN BIT(14) 337 #define RG_SYSPLL_LF BIT(13) 338 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 339 #define RG_SYSPLL_LVROD_EN BIT(10) 340 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 341 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 342 #define RG_SYSPLL_FBKSEL BIT(4) 343 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 344 345 #define CORE_PLL_GROUP4 0x403 346 #define RG_SYSPLL_DDSFBK_EN BIT(12) 347 #define RG_SYSPLL_BIAS_EN BIT(11) 348 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 349 350 #define CORE_PLL_GROUP5 0x404 351 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 352 353 #define CORE_PLL_GROUP6 0x405 354 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 355 356 #define CORE_PLL_GROUP7 0x406 357 #define RG_LCDDS_PWDB BIT(15) 358 #define RG_LCDDS_ISO_EN BIT(13) 359 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 360 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 361 362 #define CORE_PLL_GROUP10 0x409 363 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 364 365 #define CORE_PLL_GROUP11 0x40a 366 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 367 368 #define CORE_GSWPLL_GRP1 0x40d 369 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 370 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 371 #define RG_GSWPLL_EN_PRE BIT(11) 372 #define RG_GSWPLL_FBKSEL BIT(10) 373 #define RG_GSWPLL_BP BIT(9) 374 #define RG_GSWPLL_BR BIT(8) 375 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 376 377 #define CORE_GSWPLL_GRP2 0x40e 378 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 379 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 380 381 #define CORE_TRGMII_GSW_CLK_CG 0x410 382 #define REG_GSWCK_EN BIT(0) 383 #define REG_TRGMIICK_EN BIT(1) 384 385 #define MIB_DESC(_s, _o, _n) \ 386 { \ 387 .size = (_s), \ 388 .offset = (_o), \ 389 .name = (_n), \ 390 } 391 392 struct mt7530_mib_desc { 393 unsigned int size; 394 unsigned int offset; 395 const char *name; 396 }; 397 398 struct mt7530_fdb { 399 u16 vid; 400 u8 port_mask; 401 u8 aging; 402 u8 mac[6]; 403 bool noarp; 404 }; 405 406 /* struct mt7530_port - This is the main data structure for holding the state 407 * of the port. 408 * @enable: The status used for show port is enabled or not. 409 * @pm: The matrix used to show all connections with the port. 410 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 411 * untagged frames will be assigned to the related VLAN. 412 * @vlan_filtering: The flags indicating whether the port that can recognize 413 * VLAN-tagged frames. 414 */ 415 struct mt7530_port { 416 bool enable; 417 u32 pm; 418 u16 pvid; 419 }; 420 421 /* Port 5 interface select definitions */ 422 enum p5_interface_select { 423 P5_DISABLED = 0, 424 P5_INTF_SEL_PHY_P0, 425 P5_INTF_SEL_PHY_P4, 426 P5_INTF_SEL_GMAC5, 427 }; 428 429 static const char *p5_intf_modes(unsigned int p5_interface) 430 { 431 switch (p5_interface) { 432 case P5_DISABLED: 433 return "DISABLED"; 434 case P5_INTF_SEL_PHY_P0: 435 return "PHY P0"; 436 case P5_INTF_SEL_PHY_P4: 437 return "PHY P4"; 438 case P5_INTF_SEL_GMAC5: 439 return "GMAC5"; 440 default: 441 return "unknown"; 442 } 443 } 444 445 /* struct mt7530_priv - This is the main data structure for holding the state 446 * of the driver 447 * @dev: The device pointer 448 * @ds: The pointer to the dsa core structure 449 * @bus: The bus used for the device and built-in PHY 450 * @rstc: The pointer to reset control used by MCM 451 * @core_pwr: The power supplied into the core 452 * @io_pwr: The power supplied into the I/O 453 * @reset: The descriptor for GPIO line tied to its reset pin 454 * @mcm: Flag for distinguishing if standalone IC or module 455 * coupling 456 * @ports: Holding the state among ports 457 * @reg_mutex: The lock for protecting among process accessing 458 * registers 459 * @p6_interface Holding the current port 6 interface 460 * @p5_intf_sel: Holding the current port 5 interface select 461 */ 462 struct mt7530_priv { 463 struct device *dev; 464 struct dsa_switch *ds; 465 struct mii_bus *bus; 466 struct reset_control *rstc; 467 struct regulator *core_pwr; 468 struct regulator *io_pwr; 469 struct gpio_desc *reset; 470 unsigned int id; 471 bool mcm; 472 phy_interface_t p6_interface; 473 phy_interface_t p5_interface; 474 unsigned int p5_intf_sel; 475 u8 mirror_rx; 476 u8 mirror_tx; 477 478 struct mt7530_port ports[MT7530_NUM_PORTS]; 479 /* protect among processes for registers access*/ 480 struct mutex reg_mutex; 481 }; 482 483 struct mt7530_hw_vlan_entry { 484 int port; 485 u8 old_members; 486 bool untagged; 487 }; 488 489 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 490 int port, bool untagged) 491 { 492 e->port = port; 493 e->untagged = untagged; 494 } 495 496 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 497 struct mt7530_hw_vlan_entry *); 498 499 struct mt7530_hw_stats { 500 const char *string; 501 u16 reg; 502 u8 sizeof_stat; 503 }; 504 505 struct mt7530_dummy_poll { 506 struct mt7530_priv *priv; 507 u32 reg; 508 }; 509 510 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 511 struct mt7530_priv *priv, u32 reg) 512 { 513 p->priv = priv; 514 p->reg = reg; 515 } 516 517 #endif /* __MT7530_H */ 518