1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6 #ifndef __MT7530_H
7 #define __MT7530_H
8
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_NUM_PHYS 5
11 #define MT7530_NUM_FDB_RECORDS 2048
12 #define MT7530_ALL_MEMBERS 0xff
13
14 #define MTK_HDR_LEN 4
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16
17 enum mt753x_id {
18 ID_MT7530 = 0,
19 ID_MT7621 = 1,
20 ID_MT7531 = 2,
21 ID_MT7988 = 3,
22 ID_EN7581 = 4,
23 };
24
25 #define NUM_TRGMII_CTRL 5
26
27 #define TRGMII_BASE(x) (0x10000 + (x))
28
29 /* Registers to ethsys access */
30 #define ETHSYS_CLKCFG0 0x2c
31 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
32
33 #define SYSC_REG_RSTCTRL 0x34
34 #define RESET_MCM BIT(2)
35
36 /* Register for ARL global control */
37 #define MT753X_AGC 0xc
38 #define LOCAL_EN BIT(7)
39
40 /* Register for MAC forward control */
41 #define MT753X_MFC 0x10
42 #define BC_FFP_MASK GENMASK(31, 24)
43 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
44 #define UNM_FFP_MASK GENMASK(23, 16)
45 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
46 #define UNU_FFP_MASK GENMASK(15, 8)
47 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
48 #define MT7530_CPU_EN BIT(7)
49 #define MT7530_CPU_PORT_MASK GENMASK(6, 4)
50 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
51 #define MT7530_MIRROR_EN BIT(3)
52 #define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
53 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
54 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
55 #define MT7531_QRY_FFP_MASK GENMASK(7, 0)
56 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
57
58 /* Register for CPU forward control */
59 #define MT7531_CFC 0x4
60 #define MT7531_MIRROR_EN BIT(19)
61 #define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
62 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
63 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
64 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
65 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
66
67 #define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
68 id == ID_MT7988 || \
69 id == ID_EN7581) ? \
70 MT7531_CFC : MT753X_MFC)
71
72 #define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
73 id == ID_MT7988 || \
74 id == ID_EN7581) ? \
75 MT7531_MIRROR_EN : MT7530_MIRROR_EN)
76
77 #define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
78 id == ID_MT7988 || \
79 id == ID_EN7581) ? \
80 MT7531_MIRROR_PORT_MASK : \
81 MT7530_MIRROR_PORT_MASK)
82
83 #define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
84 id == ID_MT7988 || \
85 id == ID_EN7581) ? \
86 MT7531_MIRROR_PORT_GET(val) : \
87 MT7530_MIRROR_PORT_GET(val))
88
89 #define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
90 id == ID_MT7988 || \
91 id == ID_EN7581) ? \
92 MT7531_MIRROR_PORT_SET(val) : \
93 MT7530_MIRROR_PORT_SET(val))
94
95 /* Register for BPDU and PAE frame control */
96 #define MT753X_BPC 0x24
97 #define PAE_BPDU_FR BIT(25)
98 #define PAE_EG_TAG_MASK GENMASK(24, 22)
99 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
100 #define PAE_PORT_FW_MASK GENMASK(18, 16)
101 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
102 #define BPDU_EG_TAG_MASK GENMASK(8, 6)
103 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
104 #define BPDU_PORT_FW_MASK GENMASK(2, 0)
105
106 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
107 #define MT753X_RGAC1 0x28
108 #define R02_BPDU_FR BIT(25)
109 #define R02_EG_TAG_MASK GENMASK(24, 22)
110 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
111 #define R02_PORT_FW_MASK GENMASK(18, 16)
112 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
113 #define R01_BPDU_FR BIT(9)
114 #define R01_EG_TAG_MASK GENMASK(8, 6)
115 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
116 #define R01_PORT_FW_MASK GENMASK(2, 0)
117
118 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
119 #define MT753X_RGAC2 0x2c
120 #define R0E_BPDU_FR BIT(25)
121 #define R0E_EG_TAG_MASK GENMASK(24, 22)
122 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
123 #define R0E_PORT_FW_MASK GENMASK(18, 16)
124 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
125 #define R03_BPDU_FR BIT(9)
126 #define R03_EG_TAG_MASK GENMASK(8, 6)
127 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
128 #define R03_PORT_FW_MASK GENMASK(2, 0)
129
130 enum mt753x_to_cpu_fw {
131 TO_CPU_FW_SYSTEM_DEFAULT,
132 TO_CPU_FW_CPU_EXCLUDE = 4,
133 TO_CPU_FW_CPU_INCLUDE = 5,
134 TO_CPU_FW_CPU_ONLY = 6,
135 TO_CPU_FW_DROP = 7,
136 };
137
138 /* Registers for address table access */
139 #define MT7530_ATA1 0x74
140 #define STATIC_EMP 0
141 #define STATIC_ENT 3
142 #define MT7530_ATA2 0x78
143 #define ATA2_IVL BIT(15)
144 #define ATA2_FID(x) (((x) & 0x7) << 12)
145
146 /* Register for address table write data */
147 #define MT7530_ATWD 0x7c
148
149 /* Register for address table control */
150 #define MT7530_ATC 0x80
151 #define ATC_HASH (((x) & 0xfff) << 16)
152 #define ATC_BUSY BIT(15)
153 #define ATC_SRCH_END BIT(14)
154 #define ATC_SRCH_HIT BIT(13)
155 #define ATC_INVALID BIT(12)
156 #define ATC_MAT(x) (((x) & 0xf) << 8)
157 #define ATC_MAT_MACTAB ATC_MAT(0)
158
159 enum mt7530_fdb_cmd {
160 MT7530_FDB_READ = 0,
161 MT7530_FDB_WRITE = 1,
162 MT7530_FDB_FLUSH = 2,
163 MT7530_FDB_START = 4,
164 MT7530_FDB_NEXT = 5,
165 };
166
167 /* Registers for table search read address */
168 #define MT7530_TSRA1 0x84
169 #define MAC_BYTE_0 24
170 #define MAC_BYTE_1 16
171 #define MAC_BYTE_2 8
172 #define MAC_BYTE_3 0
173 #define MAC_BYTE_MASK 0xff
174
175 #define MT7530_TSRA2 0x88
176 #define MAC_BYTE_4 24
177 #define MAC_BYTE_5 16
178 #define CVID 0
179 #define CVID_MASK 0xfff
180
181 #define MT7530_ATRD 0x8C
182 #define AGE_TIMER 24
183 #define AGE_TIMER_MASK 0xff
184 #define PORT_MAP 4
185 #define PORT_MAP_MASK 0xff
186 #define ENT_STATUS 2
187 #define ENT_STATUS_MASK 0x3
188
189 /* Register for vlan table control */
190 #define MT7530_VTCR 0x90
191 #define VTCR_BUSY BIT(31)
192 #define VTCR_INVALID BIT(16)
193 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
194 #define VTCR_VID ((x) & 0xfff)
195
196 enum mt7530_vlan_cmd {
197 /* Read/Write the specified VID entry from VAWD register based
198 * on VID.
199 */
200 MT7530_VTCR_RD_VID = 0,
201 MT7530_VTCR_WR_VID = 1,
202 };
203
204 /* Register for setup vlan and acl write data */
205 #define MT7530_VAWD1 0x94
206 #define PORT_STAG BIT(31)
207 /* Independent VLAN Learning */
208 #define IVL_MAC BIT(30)
209 /* Egress Tag Consistent */
210 #define EG_CON BIT(29)
211 /* Per VLAN Egress Tag Control */
212 #define VTAG_EN BIT(28)
213 /* VLAN Member Control */
214 #define PORT_MEM(x) (((x) & 0xff) << 16)
215 /* Filter ID */
216 #define FID(x) (((x) & 0x7) << 1)
217 /* VLAN Entry Valid */
218 #define VLAN_VALID BIT(0)
219 #define PORT_MEM_SHFT 16
220 #define PORT_MEM_MASK 0xff
221
222 enum mt7530_fid {
223 FID_STANDALONE = 0,
224 FID_BRIDGED = 1,
225 };
226
227 #define MT7530_VAWD2 0x98
228 /* Egress Tag Control */
229 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
230 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
231
232 enum mt7530_vlan_egress_attr {
233 MT7530_VLAN_EGRESS_UNTAG = 0,
234 MT7530_VLAN_EGRESS_TAG = 2,
235 MT7530_VLAN_EGRESS_STACK = 3,
236 };
237
238 /* Register for address age control */
239 #define MT7530_AAC 0xa0
240 /* Disable ageing */
241 #define AGE_DIS BIT(20)
242 /* Age count */
243 #define AGE_CNT_MASK GENMASK(19, 12)
244 #define AGE_CNT_MAX 0xff
245 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
246 /* Age unit */
247 #define AGE_UNIT_MASK GENMASK(11, 0)
248 #define AGE_UNIT_MAX 0xfff
249 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
250
251 /* Register for port STP state control */
252 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
253 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
254 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
255
256 enum mt7530_stp_state {
257 MT7530_STP_DISABLED = 0,
258 MT7530_STP_BLOCKING = 1,
259 MT7530_STP_LISTENING = 1,
260 MT7530_STP_LEARNING = 2,
261 MT7530_STP_FORWARDING = 3
262 };
263
264 /* Register for port control */
265 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
266 #define PORT_TX_MIR BIT(9)
267 #define PORT_RX_MIR BIT(8)
268 #define PORT_VLAN(x) ((x) & 0x3)
269
270 enum mt7530_port_mode {
271 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
272 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
273
274 /* Fallback Mode: Forward received frames with ingress ports that do
275 * not belong to the VLAN member. Frames whose VID is not listed on
276 * the VLAN table are forwarded by the PCR_MATRIX members.
277 */
278 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
279
280 /* Security Mode: Discard any frame due to ingress membership
281 * violation or VID missed on the VLAN table.
282 */
283 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
284 };
285
286 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
287 #define PORT_PRI(x) (((x) & 0x7) << 24)
288 #define EG_TAG(x) (((x) & 0x3) << 28)
289 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
290 #define PCR_MATRIX_CLR PCR_MATRIX(0)
291 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
292
293 /* Register for port security control */
294 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
295 #define SA_DIS BIT(4)
296
297 /* Register for port vlan control */
298 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
299 #define PORT_SPEC_TAG BIT(5)
300 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
301 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
302 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
303 #define VLAN_ATTR_MASK VLAN_ATTR(3)
304 #define ACC_FRM_MASK GENMASK(1, 0)
305
306 enum mt7530_vlan_port_eg_tag {
307 MT7530_VLAN_EG_DISABLED = 0,
308 MT7530_VLAN_EG_CONSISTENT = 1,
309 MT7530_VLAN_EG_UNTAGGED = 4,
310 };
311
312 enum mt7530_vlan_port_attr {
313 MT7530_VLAN_USER = 0,
314 MT7530_VLAN_TRANSPARENT = 3,
315 };
316
317 enum mt7530_vlan_port_acc_frm {
318 MT7530_VLAN_ACC_ALL = 0,
319 MT7530_VLAN_ACC_TAGGED = 1,
320 MT7530_VLAN_ACC_UNTAGGED = 2,
321 };
322
323 #define STAG_VPID (((x) & 0xffff) << 16)
324
325 /* Register for port port-and-protocol based vlan 1 control */
326 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
327 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
328 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
329 #define G0_PORT_VID_DEF G0_PORT_VID(0)
330
331 /* Register for port MAC control register */
332 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
333 #define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
334 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
335 #define PMCR_EXT_PHY BIT(17)
336 #define PMCR_MAC_MODE BIT(16)
337 #define MT7530_FORCE_MODE BIT(15)
338 #define PMCR_MAC_TX_EN BIT(14)
339 #define PMCR_MAC_RX_EN BIT(13)
340 #define PMCR_BACKOFF_EN BIT(9)
341 #define PMCR_BACKPR_EN BIT(8)
342 #define PMCR_FORCE_EEE1G BIT(7)
343 #define PMCR_FORCE_EEE100 BIT(6)
344 #define PMCR_FORCE_RX_FC_EN BIT(5)
345 #define PMCR_FORCE_TX_FC_EN BIT(4)
346 #define PMCR_FORCE_SPEED_1000 BIT(3)
347 #define PMCR_FORCE_SPEED_100 BIT(2)
348 #define PMCR_FORCE_FDX BIT(1)
349 #define PMCR_FORCE_LNK BIT(0)
350 #define MT7531_FORCE_MODE_LNK BIT(31)
351 #define MT7531_FORCE_MODE_SPD BIT(30)
352 #define MT7531_FORCE_MODE_DPX BIT(29)
353 #define MT7531_FORCE_MODE_RX_FC BIT(28)
354 #define MT7531_FORCE_MODE_TX_FC BIT(27)
355 #define MT7531_FORCE_MODE_EEE100 BIT(26)
356 #define MT7531_FORCE_MODE_EEE1G BIT(25)
357 #define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
358 MT7531_FORCE_MODE_SPD | \
359 MT7531_FORCE_MODE_DPX | \
360 MT7531_FORCE_MODE_RX_FC | \
361 MT7531_FORCE_MODE_TX_FC | \
362 MT7531_FORCE_MODE_EEE100 | \
363 MT7531_FORCE_MODE_EEE1G)
364 #define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \
365 id == ID_MT7988) ? \
366 MT7531_FORCE_MODE_MASK : \
367 MT7530_FORCE_MODE)
368 #define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
369 PMCR_FORCE_EEE1G | \
370 PMCR_FORCE_EEE100 | \
371 PMCR_FORCE_RX_FC_EN | \
372 PMCR_FORCE_TX_FC_EN | \
373 PMCR_FORCE_SPEED_1000 | \
374 PMCR_FORCE_SPEED_100 | \
375 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
376
377 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
378 #define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
379 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
380 #define WAKEUP_TIME_100_MASK GENMASK(23, 16)
381 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
382 #define LPI_THRESH_MASK GENMASK(15, 4)
383 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
384 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
385 #define LPI_MODE_EN BIT(0)
386
387 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
388 #define PMSR_EEE1G BIT(7)
389 #define PMSR_EEE100M BIT(6)
390 #define PMSR_RX_FC BIT(5)
391 #define PMSR_TX_FC BIT(4)
392 #define PMSR_SPEED_1000 BIT(3)
393 #define PMSR_SPEED_100 BIT(2)
394 #define PMSR_SPEED_10 0x00
395 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
396 #define PMSR_DPX BIT(1)
397 #define PMSR_LINK BIT(0)
398
399 /* Register for port debug count */
400 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
401 #define MT7531_DIS_CLR BIT(31)
402
403 #define MT7530_GMACCR 0x30e0
404 #define MAX_RX_JUMBO(x) ((x) << 2)
405 #define MAX_RX_JUMBO_MASK GENMASK(5, 2)
406 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
407 #define MAX_RX_PKT_LEN_1522 0x0
408 #define MAX_RX_PKT_LEN_1536 0x1
409 #define MAX_RX_PKT_LEN_1552 0x2
410 #define MAX_RX_PKT_LEN_JUMBO 0x3
411
412 /* Register for MIB */
413 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
414 #define MT7530_MIB_CCR 0x4fe0
415 #define CCR_MIB_ENABLE BIT(31)
416 #define CCR_RX_OCT_CNT_GOOD BIT(7)
417 #define CCR_RX_OCT_CNT_BAD BIT(6)
418 #define CCR_TX_OCT_CNT_GOOD BIT(5)
419 #define CCR_TX_OCT_CNT_BAD BIT(4)
420 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
421 CCR_RX_OCT_CNT_BAD | \
422 CCR_TX_OCT_CNT_GOOD | \
423 CCR_TX_OCT_CNT_BAD)
424 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
425 CCR_RX_OCT_CNT_GOOD | \
426 CCR_RX_OCT_CNT_BAD | \
427 CCR_TX_OCT_CNT_GOOD | \
428 CCR_TX_OCT_CNT_BAD)
429
430 /* MT7531 SGMII register group */
431 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
432 #define MT7531_PHYA_CTRL_SIGNAL3 0x128
433
434 /* Register for system reset */
435 #define MT7530_SYS_CTRL 0x7000
436 #define SYS_CTRL_PHY_RST BIT(2)
437 #define SYS_CTRL_SW_RST BIT(1)
438 #define SYS_CTRL_REG_RST BIT(0)
439
440 /* Register for system interrupt */
441 #define MT7530_SYS_INT_EN 0x7008
442
443 /* Register for system interrupt status */
444 #define MT7530_SYS_INT_STS 0x700c
445
446 /* Register for PHY Indirect Access Control */
447 #define MT7531_PHY_IAC 0x701C
448 #define MT7531_PHY_ACS_ST BIT(31)
449 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
450 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
451 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
452 #define MT7531_MDIO_ST_MASK (0x3 << 16)
453 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
454 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
455 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
456 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
457 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
458 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
459
460 enum mt7531_phy_iac_cmd {
461 MT7531_MDIO_ADDR = 0,
462 MT7531_MDIO_WRITE = 1,
463 MT7531_MDIO_READ = 2,
464 MT7531_MDIO_READ_CL45 = 3,
465 };
466
467 /* MDIO_ST: MDIO start field */
468 enum mt7531_mdio_st {
469 MT7531_MDIO_ST_CL45 = 0,
470 MT7531_MDIO_ST_CL22 = 1,
471 };
472
473 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
474 MT7531_MDIO_CMD(MT7531_MDIO_READ))
475 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
476 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
477 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
478 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
479 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
480 MT7531_MDIO_CMD(MT7531_MDIO_READ))
481 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
482 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
483
484 /* Register for RGMII clock phase */
485 #define MT7531_CLKGEN_CTRL 0x7500
486 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
487 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
488 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
489 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
490 #define RXCLK_NO_DELAY BIT(5)
491 #define TXCLK_NO_REVERSE BIT(4)
492 #define GP_MODE(x) (((x) & 0x3) << 1)
493 #define GP_MODE_MASK GENMASK(2, 1)
494 #define GP_CLK_EN BIT(0)
495
496 enum mt7531_gp_mode {
497 MT7531_GP_MODE_RGMII = 0,
498 MT7531_GP_MODE_MII = 1,
499 MT7531_GP_MODE_REV_MII = 2
500 };
501
502 enum mt7531_clk_skew {
503 MT7531_CLK_SKEW_NO_CHG = 0,
504 MT7531_CLK_SKEW_DLY_100PPS = 1,
505 MT7531_CLK_SKEW_DLY_200PPS = 2,
506 MT7531_CLK_SKEW_REVERSE = 3,
507 };
508
509 /* Register for trap status */
510 #define MT753X_TRAP 0x7800
511 #define MT7530_XTAL_MASK (BIT(10) | BIT(9))
512 #define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
513 #define MT7530_XTAL_40MHZ BIT(10)
514 #define MT7530_XTAL_20MHZ BIT(9)
515 #define MT7531_XTAL25 BIT(7)
516
517 /* Register for trap modification */
518 #define MT753X_MTRAP 0x7804
519 #define MT7530_P5_PHY0_SEL BIT(20)
520 #define MT7530_CHG_TRAP BIT(16)
521 #define MT7530_P5_MAC_SEL BIT(13)
522 #define MT7530_P6_DIS BIT(8)
523 #define MT7530_P5_RGMII_MODE BIT(7)
524 #define MT7530_P5_DIS BIT(6)
525 #define MT7530_PHY_INDIRECT_ACCESS BIT(5)
526 #define MT7531_CHG_STRAP BIT(8)
527 #define MT7531_PHY_EN BIT(6)
528
529 enum mt7531_xtal_fsel {
530 MT7531_XTAL_FSEL_25MHZ,
531 MT7531_XTAL_FSEL_40MHZ,
532 };
533
534 /* Register for TOP signal control */
535 #define MT7530_TOP_SIG_CTRL 0x7808
536 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
537
538 #define MT7531_TOP_SIG_SR 0x780c
539 #define PAD_DUAL_SGMII_EN BIT(1)
540 #define PAD_MCM_SMI_EN BIT(0)
541
542 #define MT7530_IO_DRV_CR 0x7810
543 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
544 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
545
546 #define MT7531_CHIP_REV 0x781C
547
548 #define MT7531_PLLGP_EN 0x7820
549 #define EN_COREPLL BIT(2)
550 #define SW_CLKSW BIT(1)
551 #define SW_PLLGP BIT(0)
552
553 #define MT7530_P6ECR 0x7830
554 #define P6_INTF_MODE_MASK 0x3
555 #define P6_INTF_MODE(x) ((x) & 0x3)
556
557 #define MT7531_PLLGP_CR0 0x78a8
558 #define RG_COREPLL_EN BIT(22)
559 #define RG_COREPLL_POSDIV_S 23
560 #define RG_COREPLL_POSDIV_M 0x3800000
561 #define RG_COREPLL_SDM_PCW_S 1
562 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
563 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
564
565 /* Registers for RGMII and SGMII PLL clock */
566 #define MT7531_ANA_PLLGP_CR2 0x78b0
567 #define MT7531_ANA_PLLGP_CR5 0x78bc
568
569 /* Registers for TRGMII on the both side */
570 #define MT7530_TRGMII_RCK_CTRL 0x7a00
571 #define RX_RST BIT(31)
572 #define RXC_DQSISEL BIT(30)
573 #define DQSI1_TAP_MASK (0x7f << 8)
574 #define DQSI0_TAP_MASK 0x7f
575 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
576 #define DQSI0_TAP(x) ((x) & 0x7f)
577
578 #define MT7530_TRGMII_RCK_RTT 0x7a04
579 #define DQS1_GATE BIT(31)
580 #define DQS0_GATE BIT(30)
581
582 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
583 #define BSLIP_EN BIT(31)
584 #define EDGE_CHK BIT(30)
585 #define RD_TAP_MASK 0x7f
586 #define RD_TAP(x) ((x) & 0x7f)
587
588 #define MT7530_TRGMII_TXCTRL 0x7a40
589 #define TRAIN_TXEN BIT(31)
590 #define TXC_INV BIT(30)
591 #define TX_RST BIT(28)
592
593 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
594 #define TD_DM_DRVP(x) ((x) & 0xf)
595 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
596
597 #define MT7530_TRGMII_TCK_CTRL 0x7a78
598 #define TCK_TAP(x) (((x) & 0xf) << 8)
599
600 #define MT7530_P5RGMIIRXCR 0x7b00
601 #define CSR_RGMII_EDGE_ALIGN BIT(8)
602 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
603
604 #define MT7530_P5RGMIITXCR 0x7b04
605 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
606
607 /* Registers for GPIO mode */
608 #define MT7531_GPIO_MODE0 0x7c0c
609 #define MT7531_GPIO0_MASK GENMASK(3, 0)
610 #define MT7531_GPIO0_INTERRUPT 1
611
612 #define MT7531_GPIO_MODE1 0x7c10
613 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
614 #define MT7531_EXT_P_MDC_11 (2 << 12)
615 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
616 #define MT7531_EXT_P_MDIO_12 (2 << 16)
617
618 /* Registers for LED GPIO control (MT7530 only)
619 * All registers follow this pattern:
620 * [ 2: 0] port 0
621 * [ 6: 4] port 1
622 * [10: 8] port 2
623 * [14:12] port 3
624 * [18:16] port 4
625 */
626
627 /* LED enable, 0: Disable, 1: Enable (Default) */
628 #define MT7530_LED_EN 0x7d00
629 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
630 #define MT7530_LED_IO_MODE 0x7d04
631 /* GPIO direction, 0: Input, 1: Output */
632 #define MT7530_LED_GPIO_DIR 0x7d10
633 /* GPIO output enable, 0: Disable, 1: Enable */
634 #define MT7530_LED_GPIO_OE 0x7d14
635 /* GPIO value, 0: Low, 1: High */
636 #define MT7530_LED_GPIO_DATA 0x7d18
637
638 #define MT7530_CREV 0x7ffc
639 #define CHIP_NAME_SHIFT 16
640 #define MT7530_ID 0x7530
641
642 #define MT7531_CREV 0x781C
643 #define CHIP_REV_M 0x0f
644 #define MT7531_ID 0x7531
645
646 /* Registers for core PLL access through mmd indirect */
647 #define CORE_PLL_GROUP2 0x401
648 #define RG_SYSPLL_EN_NORMAL BIT(15)
649 #define RG_SYSPLL_VODEN BIT(14)
650 #define RG_SYSPLL_LF BIT(13)
651 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
652 #define RG_SYSPLL_LVROD_EN BIT(10)
653 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
654 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
655 #define RG_SYSPLL_FBKSEL BIT(4)
656 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
657
658 #define CORE_PLL_GROUP4 0x403
659 #define RG_SYSPLL_DDSFBK_EN BIT(12)
660 #define RG_SYSPLL_BIAS_EN BIT(11)
661 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
662 #define MT7531_RG_SYSPLL_DMY2 BIT(6)
663 #define MT7531_PHY_PLL_OFF BIT(5)
664 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
665
666 #define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
667
668 #define CORE_PLL_GROUP5 0x404
669 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
670
671 #define CORE_PLL_GROUP6 0x405
672 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
673
674 #define CORE_PLL_GROUP7 0x406
675 #define RG_LCDDS_PWDB BIT(15)
676 #define RG_LCDDS_ISO_EN BIT(13)
677 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
678 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
679
680 #define CORE_PLL_GROUP10 0x409
681 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
682
683 #define CORE_PLL_GROUP11 0x40a
684 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
685
686 #define CORE_GSWPLL_GRP1 0x40d
687 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
688 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
689 #define RG_GSWPLL_EN_PRE BIT(11)
690 #define RG_GSWPLL_FBKSEL BIT(10)
691 #define RG_GSWPLL_BP BIT(9)
692 #define RG_GSWPLL_BR BIT(8)
693 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
694
695 #define CORE_GSWPLL_GRP2 0x40e
696 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
697 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
698
699 #define CORE_TRGMII_GSW_CLK_CG 0x410
700 #define REG_GSWCK_EN BIT(0)
701 #define REG_TRGMIICK_EN BIT(1)
702
703 #define MIB_DESC(_s, _o, _n) \
704 { \
705 .size = (_s), \
706 .offset = (_o), \
707 .name = (_n), \
708 }
709
710 struct mt7530_mib_desc {
711 unsigned int size;
712 unsigned int offset;
713 const char *name;
714 };
715
716 struct mt7530_fdb {
717 u16 vid;
718 u8 port_mask;
719 u8 aging;
720 u8 mac[6];
721 bool noarp;
722 };
723
724 /* struct mt7530_port - This is the main data structure for holding the state
725 * of the port.
726 * @enable: The status used for show port is enabled or not.
727 * @pm: The matrix used to show all connections with the port.
728 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
729 * untagged frames will be assigned to the related VLAN.
730 * @sgmii_pcs: Pointer to PCS instance for SerDes ports
731 */
732 struct mt7530_port {
733 bool enable;
734 bool isolated;
735 u32 pm;
736 u16 pvid;
737 struct phylink_pcs *sgmii_pcs;
738 };
739
740 /* Port 5 mode definitions of the MT7530 switch */
741 enum mt7530_p5_mode {
742 GMAC5,
743 MUX_PHY_P0,
744 MUX_PHY_P4,
745 };
746
747 struct mt7530_priv;
748
749 struct mt753x_pcs {
750 struct phylink_pcs pcs;
751 struct mt7530_priv *priv;
752 int port;
753 };
754
755 /* struct mt753x_info - This is the main data structure for holding the specific
756 * part for each supported device
757 * @id: Holding the identifier to a switch model
758 * @pcs_ops: Holding the pointer to the MAC PCS operations structure
759 * @sw_setup: Holding the handler to a device initialization
760 * @phy_read_c22: Holding the way reading PHY port using C22
761 * @phy_write_c22: Holding the way writing PHY port using C22
762 * @phy_read_c45: Holding the way reading PHY port using C45
763 * @phy_write_c45: Holding the way writing PHY port using C45
764 * @mac_port_get_caps: Holding the handler that provides MAC capabilities
765 * @mac_port_config: Holding the way setting up the PHY attribute to a
766 * certain MAC port
767 */
768 struct mt753x_info {
769 enum mt753x_id id;
770
771 const struct phylink_pcs_ops *pcs_ops;
772
773 int (*sw_setup)(struct dsa_switch *ds);
774 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
775 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
776 u16 val);
777 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
778 int regnum);
779 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
780 int regnum, u16 val);
781 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
782 struct phylink_config *config);
783 void (*mac_port_config)(struct dsa_switch *ds, int port,
784 unsigned int mode,
785 phy_interface_t interface);
786 };
787
788 /* struct mt7530_priv - This is the main data structure for holding the state
789 * of the driver
790 * @dev: The device pointer
791 * @ds: The pointer to the dsa core structure
792 * @bus: The bus used for the device and built-in PHY
793 * @regmap: The regmap instance representing all switch registers
794 * @rstc: The pointer to reset control used by MCM
795 * @core_pwr: The power supplied into the core
796 * @io_pwr: The power supplied into the I/O
797 * @reset: The descriptor for GPIO line tied to its reset pin
798 * @mcm: Flag for distinguishing if standalone IC or module
799 * coupling
800 * @ports: Holding the state among ports
801 * @reg_mutex: The lock for protecting among process accessing
802 * registers
803 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
804 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
805 * has got SGMII
806 * @irq: IRQ number of the switch
807 * @irq_domain: IRQ domain of the switch irq_chip
808 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
809 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
810 * @active_cpu_ports: Holding the active CPU ports
811 * @mdiodev: The pointer to the MDIO device structure
812 */
813 struct mt7530_priv {
814 struct device *dev;
815 struct dsa_switch *ds;
816 struct mii_bus *bus;
817 struct regmap *regmap;
818 struct reset_control *rstc;
819 struct regulator *core_pwr;
820 struct regulator *io_pwr;
821 struct gpio_desc *reset;
822 const struct mt753x_info *info;
823 unsigned int id;
824 bool mcm;
825 enum mt7530_p5_mode p5_mode;
826 bool p5_sgmii;
827 u8 mirror_rx;
828 u8 mirror_tx;
829 struct mt7530_port ports[MT7530_NUM_PORTS];
830 struct mt753x_pcs pcs[MT7530_NUM_PORTS];
831 /* protect among processes for registers access*/
832 struct mutex reg_mutex;
833 int irq;
834 struct irq_domain *irq_domain;
835 u32 irq_enable;
836 int (*create_sgmii)(struct mt7530_priv *priv);
837 u8 active_cpu_ports;
838 struct mdio_device *mdiodev;
839 };
840
841 struct mt7530_hw_vlan_entry {
842 int port;
843 u8 old_members;
844 bool untagged;
845 };
846
mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry * e,int port,bool untagged)847 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
848 int port, bool untagged)
849 {
850 e->port = port;
851 e->untagged = untagged;
852 }
853
854 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
855 struct mt7530_hw_vlan_entry *);
856
857 struct mt7530_hw_stats {
858 const char *string;
859 u16 reg;
860 u8 sizeof_stat;
861 };
862
863 struct mt7530_dummy_poll {
864 struct mt7530_priv *priv;
865 u32 reg;
866 };
867
INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll * p,struct mt7530_priv * priv,u32 reg)868 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
869 struct mt7530_priv *priv, u32 reg)
870 {
871 p->priv = priv;
872 p->reg = reg;
873 }
874
875 int mt7530_probe_common(struct mt7530_priv *priv);
876 void mt7530_remove_common(struct mt7530_priv *priv);
877
878 extern const struct dsa_switch_ops mt7530_switch_ops;
879 extern const struct mt753x_info mt753x_table[];
880
881 #endif /* __MT7530_H */
882