1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6 #ifndef __MT7530_H
7 #define __MT7530_H
8
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_NUM_PHYS 5
11 #define MT7530_NUM_FDB_RECORDS 2048
12 #define MT7530_ALL_MEMBERS 0xff
13
14 #define MTK_HDR_LEN 4
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16
17 enum mt753x_id {
18 ID_MT7530 = 0,
19 ID_MT7621 = 1,
20 ID_MT7531 = 2,
21 ID_MT7988 = 3,
22 ID_EN7581 = 4,
23 };
24
25 #define NUM_TRGMII_CTRL 5
26
27 #define TRGMII_BASE(x) (0x10000 + (x))
28
29 /* Registers to ethsys access */
30 #define ETHSYS_CLKCFG0 0x2c
31 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
32
33 #define SYSC_REG_RSTCTRL 0x34
34 #define RESET_MCM BIT(2)
35
36 /* Register for ARL global control */
37 #define MT753X_AGC 0xc
38 #define LOCAL_EN BIT(7)
39
40 /* Register for MAC forward control */
41 #define MT753X_MFC 0x10
42 #define BC_FFP_MASK GENMASK(31, 24)
43 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
44 #define UNM_FFP_MASK GENMASK(23, 16)
45 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
46 #define UNU_FFP_MASK GENMASK(15, 8)
47 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
48 #define MT7530_CPU_EN BIT(7)
49 #define MT7530_CPU_PORT_MASK GENMASK(6, 4)
50 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
51 #define MT7530_MIRROR_EN BIT(3)
52 #define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
53 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
54 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
55 #define MT7531_QRY_FFP_MASK GENMASK(7, 0)
56 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
57
58 /* Register for CPU forward control */
59 #define MT7531_CFC 0x4
60 #define MT7531_MIRROR_EN BIT(19)
61 #define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
62 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
63 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
64 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
65 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
66
67 #define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
68 id == ID_MT7988 || \
69 id == ID_EN7581) ? \
70 MT7531_CFC : MT753X_MFC)
71
72 #define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
73 id == ID_MT7988 || \
74 id == ID_EN7581) ? \
75 MT7531_MIRROR_EN : MT7530_MIRROR_EN)
76
77 #define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
78 id == ID_MT7988 || \
79 id == ID_EN7581) ? \
80 MT7531_MIRROR_PORT_MASK : \
81 MT7530_MIRROR_PORT_MASK)
82
83 #define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
84 id == ID_MT7988 || \
85 id == ID_EN7581) ? \
86 MT7531_MIRROR_PORT_GET(val) : \
87 MT7530_MIRROR_PORT_GET(val))
88
89 #define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
90 id == ID_MT7988 || \
91 id == ID_EN7581) ? \
92 MT7531_MIRROR_PORT_SET(val) : \
93 MT7530_MIRROR_PORT_SET(val))
94
95 /* Register for BPDU and PAE frame control */
96 #define MT753X_BPC 0x24
97 #define PAE_BPDU_FR BIT(25)
98 #define PAE_EG_TAG_MASK GENMASK(24, 22)
99 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
100 #define PAE_PORT_FW_MASK GENMASK(18, 16)
101 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
102 #define BPDU_EG_TAG_MASK GENMASK(8, 6)
103 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
104 #define BPDU_PORT_FW_MASK GENMASK(2, 0)
105
106 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
107 #define MT753X_RGAC1 0x28
108 #define R02_BPDU_FR BIT(25)
109 #define R02_EG_TAG_MASK GENMASK(24, 22)
110 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
111 #define R02_PORT_FW_MASK GENMASK(18, 16)
112 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
113 #define R01_BPDU_FR BIT(9)
114 #define R01_EG_TAG_MASK GENMASK(8, 6)
115 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
116 #define R01_PORT_FW_MASK GENMASK(2, 0)
117
118 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
119 #define MT753X_RGAC2 0x2c
120 #define R0E_BPDU_FR BIT(25)
121 #define R0E_EG_TAG_MASK GENMASK(24, 22)
122 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
123 #define R0E_PORT_FW_MASK GENMASK(18, 16)
124 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
125 #define R03_BPDU_FR BIT(9)
126 #define R03_EG_TAG_MASK GENMASK(8, 6)
127 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
128 #define R03_PORT_FW_MASK GENMASK(2, 0)
129
130 enum mt753x_to_cpu_fw {
131 TO_CPU_FW_SYSTEM_DEFAULT,
132 TO_CPU_FW_CPU_EXCLUDE = 4,
133 TO_CPU_FW_CPU_INCLUDE = 5,
134 TO_CPU_FW_CPU_ONLY = 6,
135 TO_CPU_FW_DROP = 7,
136 };
137
138 /* Registers for address table access */
139 #define MT7530_ATA1 0x74
140 #define STATIC_EMP 0
141 #define STATIC_ENT 3
142 #define MT7530_ATA2 0x78
143 #define ATA2_IVL BIT(15)
144 #define ATA2_FID(x) (((x) & 0x7) << 12)
145
146 /* Register for address table write data */
147 #define MT7530_ATWD 0x7c
148
149 /* Register for address table control */
150 #define MT7530_ATC 0x80
151 #define ATC_HASH (((x) & 0xfff) << 16)
152 #define ATC_BUSY BIT(15)
153 #define ATC_SRCH_END BIT(14)
154 #define ATC_SRCH_HIT BIT(13)
155 #define ATC_INVALID BIT(12)
156 #define ATC_MAT(x) (((x) & 0xf) << 8)
157 #define ATC_MAT_MACTAB ATC_MAT(0)
158
159 enum mt7530_fdb_cmd {
160 MT7530_FDB_READ = 0,
161 MT7530_FDB_WRITE = 1,
162 MT7530_FDB_FLUSH = 2,
163 MT7530_FDB_START = 4,
164 MT7530_FDB_NEXT = 5,
165 };
166
167 /* Registers for table search read address */
168 #define MT7530_TSRA1 0x84
169 #define MAC_BYTE_0 24
170 #define MAC_BYTE_1 16
171 #define MAC_BYTE_2 8
172 #define MAC_BYTE_3 0
173 #define MAC_BYTE_MASK 0xff
174
175 #define MT7530_TSRA2 0x88
176 #define MAC_BYTE_4 24
177 #define MAC_BYTE_5 16
178 #define CVID 0
179 #define CVID_MASK 0xfff
180
181 #define MT7530_ATRD 0x8C
182 #define AGE_TIMER 24
183 #define AGE_TIMER_MASK 0xff
184 #define PORT_MAP 4
185 #define PORT_MAP_MASK 0xff
186 #define ENT_STATUS 2
187 #define ENT_STATUS_MASK 0x3
188
189 /* Register for vlan table control */
190 #define MT7530_VTCR 0x90
191 #define VTCR_BUSY BIT(31)
192 #define VTCR_INVALID BIT(16)
193 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
194 #define VTCR_VID ((x) & 0xfff)
195
196 enum mt7530_vlan_cmd {
197 /* Read/Write the specified VID entry from VAWD register based
198 * on VID.
199 */
200 MT7530_VTCR_RD_VID = 0,
201 MT7530_VTCR_WR_VID = 1,
202 };
203
204 /* Register for setup vlan and acl write data */
205 #define MT7530_VAWD1 0x94
206 #define PORT_STAG BIT(31)
207 /* Independent VLAN Learning */
208 #define IVL_MAC BIT(30)
209 /* Egress Tag Consistent */
210 #define EG_CON BIT(29)
211 /* Per VLAN Egress Tag Control */
212 #define VTAG_EN BIT(28)
213 /* VLAN Member Control */
214 #define PORT_MEM(x) (((x) & 0xff) << 16)
215 /* Filter ID */
216 #define FID(x) (((x) & 0x7) << 1)
217 /* VLAN Entry Valid */
218 #define VLAN_VALID BIT(0)
219 #define PORT_MEM_SHFT 16
220 #define PORT_MEM_MASK 0xff
221
222 enum mt7530_fid {
223 FID_STANDALONE = 0,
224 FID_BRIDGED = 1,
225 };
226
227 #define MT7530_VAWD2 0x98
228 /* Egress Tag Control */
229 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
230 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
231
232 enum mt7530_vlan_egress_attr {
233 MT7530_VLAN_EGRESS_UNTAG = 0,
234 MT7530_VLAN_EGRESS_TAG = 2,
235 MT7530_VLAN_EGRESS_STACK = 3,
236 };
237
238 /* Register for address age control */
239 #define MT7530_AAC 0xa0
240 /* Disable ageing */
241 #define AGE_DIS BIT(20)
242 /* Age count */
243 #define AGE_CNT_MASK GENMASK(19, 12)
244 #define AGE_CNT_MAX 0xff
245 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
246 /* Age unit */
247 #define AGE_UNIT_MASK GENMASK(11, 0)
248 #define AGE_UNIT_MAX 0xfff
249 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
250
251 #define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100))
252 #define ERLCR_CIR_MASK GENMASK(31, 16)
253 #define ERLCR_EN_MASK BIT(15)
254 #define ERLCR_EXP_MASK GENMASK(11, 8)
255 #define ERLCR_TBF_MODE_MASK BIT(7)
256 #define ERLCR_MANT_MASK GENMASK(6, 0)
257
258 #define MT753X_GERLCR 0x10e0
259 #define EGR_BC_MASK GENMASK(7, 0)
260 #define EGR_BC_CRC 0x4 /* crc */
261 #define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */
262
263 /* Register for port STP state control */
264 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
265 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
266 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
267
268 enum mt7530_stp_state {
269 MT7530_STP_DISABLED = 0,
270 MT7530_STP_BLOCKING = 1,
271 MT7530_STP_LISTENING = 1,
272 MT7530_STP_LEARNING = 2,
273 MT7530_STP_FORWARDING = 3
274 };
275
276 /* Register for port control */
277 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
278 #define PORT_TX_MIR BIT(9)
279 #define PORT_RX_MIR BIT(8)
280 #define PORT_VLAN(x) ((x) & 0x3)
281
282 enum mt7530_port_mode {
283 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
284 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
285
286 /* Fallback Mode: Forward received frames with ingress ports that do
287 * not belong to the VLAN member. Frames whose VID is not listed on
288 * the VLAN table are forwarded by the PCR_MATRIX members.
289 */
290 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
291
292 /* Security Mode: Discard any frame due to ingress membership
293 * violation or VID missed on the VLAN table.
294 */
295 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
296 };
297
298 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
299 #define PORT_PRI(x) (((x) & 0x7) << 24)
300 #define EG_TAG(x) (((x) & 0x3) << 28)
301 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
302 #define PCR_MATRIX_CLR PCR_MATRIX(0)
303 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
304
305 /* Register for port security control */
306 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
307 #define SA_DIS BIT(4)
308
309 /* Register for port vlan control */
310 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
311 #define PORT_SPEC_TAG BIT(5)
312 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
313 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
314 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
315 #define VLAN_ATTR_MASK VLAN_ATTR(3)
316 #define ACC_FRM_MASK GENMASK(1, 0)
317
318 enum mt7530_vlan_port_eg_tag {
319 MT7530_VLAN_EG_DISABLED = 0,
320 MT7530_VLAN_EG_CONSISTENT = 1,
321 MT7530_VLAN_EG_UNTAGGED = 4,
322 };
323
324 enum mt7530_vlan_port_attr {
325 MT7530_VLAN_USER = 0,
326 MT7530_VLAN_TRANSPARENT = 3,
327 };
328
329 enum mt7530_vlan_port_acc_frm {
330 MT7530_VLAN_ACC_ALL = 0,
331 MT7530_VLAN_ACC_TAGGED = 1,
332 MT7530_VLAN_ACC_UNTAGGED = 2,
333 };
334
335 #define STAG_VPID (((x) & 0xffff) << 16)
336
337 /* Register for port port-and-protocol based vlan 1 control */
338 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
339 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
340 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
341 #define G0_PORT_VID_DEF G0_PORT_VID(0)
342
343 /* Register for port MAC control register */
344 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
345 #define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
346 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
347 #define PMCR_EXT_PHY BIT(17)
348 #define PMCR_MAC_MODE BIT(16)
349 #define MT7530_FORCE_MODE BIT(15)
350 #define PMCR_MAC_TX_EN BIT(14)
351 #define PMCR_MAC_RX_EN BIT(13)
352 #define PMCR_BACKOFF_EN BIT(9)
353 #define PMCR_BACKPR_EN BIT(8)
354 #define PMCR_FORCE_EEE1G BIT(7)
355 #define PMCR_FORCE_EEE100 BIT(6)
356 #define PMCR_FORCE_RX_FC_EN BIT(5)
357 #define PMCR_FORCE_TX_FC_EN BIT(4)
358 #define PMCR_FORCE_SPEED_1000 BIT(3)
359 #define PMCR_FORCE_SPEED_100 BIT(2)
360 #define PMCR_FORCE_FDX BIT(1)
361 #define PMCR_FORCE_LNK BIT(0)
362 #define MT7531_FORCE_MODE_LNK BIT(31)
363 #define MT7531_FORCE_MODE_SPD BIT(30)
364 #define MT7531_FORCE_MODE_DPX BIT(29)
365 #define MT7531_FORCE_MODE_RX_FC BIT(28)
366 #define MT7531_FORCE_MODE_TX_FC BIT(27)
367 #define MT7531_FORCE_MODE_EEE100 BIT(26)
368 #define MT7531_FORCE_MODE_EEE1G BIT(25)
369 #define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
370 MT7531_FORCE_MODE_SPD | \
371 MT7531_FORCE_MODE_DPX | \
372 MT7531_FORCE_MODE_RX_FC | \
373 MT7531_FORCE_MODE_TX_FC | \
374 MT7531_FORCE_MODE_EEE100 | \
375 MT7531_FORCE_MODE_EEE1G)
376 #define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \
377 id == ID_MT7988) ? \
378 MT7531_FORCE_MODE_MASK : \
379 MT7530_FORCE_MODE)
380 #define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
381 PMCR_FORCE_EEE1G | \
382 PMCR_FORCE_EEE100 | \
383 PMCR_FORCE_RX_FC_EN | \
384 PMCR_FORCE_TX_FC_EN | \
385 PMCR_FORCE_SPEED_1000 | \
386 PMCR_FORCE_SPEED_100 | \
387 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
388
389 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
390 #define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
391 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
392 #define WAKEUP_TIME_100_MASK GENMASK(23, 16)
393 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
394 #define LPI_THRESH_MASK GENMASK(15, 4)
395 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
396 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
397 #define LPI_MODE_EN BIT(0)
398
399 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
400 #define PMSR_EEE1G BIT(7)
401 #define PMSR_EEE100M BIT(6)
402 #define PMSR_RX_FC BIT(5)
403 #define PMSR_TX_FC BIT(4)
404 #define PMSR_SPEED_1000 BIT(3)
405 #define PMSR_SPEED_100 BIT(2)
406 #define PMSR_SPEED_10 0x00
407 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
408 #define PMSR_DPX BIT(1)
409 #define PMSR_LINK BIT(0)
410
411 /* Register for port debug count */
412 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
413 #define MT7531_DIS_CLR BIT(31)
414
415 #define MT7530_GMACCR 0x30e0
416 #define MAX_RX_JUMBO(x) ((x) << 2)
417 #define MAX_RX_JUMBO_MASK GENMASK(5, 2)
418 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
419 #define MAX_RX_PKT_LEN_1522 0x0
420 #define MAX_RX_PKT_LEN_1536 0x1
421 #define MAX_RX_PKT_LEN_1552 0x2
422 #define MAX_RX_PKT_LEN_JUMBO 0x3
423
424 /* Register for MIB */
425 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
426 #define MT7530_MIB_CCR 0x4fe0
427 #define CCR_MIB_ENABLE BIT(31)
428 #define CCR_RX_OCT_CNT_GOOD BIT(7)
429 #define CCR_RX_OCT_CNT_BAD BIT(6)
430 #define CCR_TX_OCT_CNT_GOOD BIT(5)
431 #define CCR_TX_OCT_CNT_BAD BIT(4)
432 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
433 CCR_RX_OCT_CNT_BAD | \
434 CCR_TX_OCT_CNT_GOOD | \
435 CCR_TX_OCT_CNT_BAD)
436 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
437 CCR_RX_OCT_CNT_GOOD | \
438 CCR_RX_OCT_CNT_BAD | \
439 CCR_TX_OCT_CNT_GOOD | \
440 CCR_TX_OCT_CNT_BAD)
441
442 /* MT7531 SGMII register group */
443 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
444 #define MT7531_PHYA_CTRL_SIGNAL3 0x128
445
446 /* Register for system reset */
447 #define MT7530_SYS_CTRL 0x7000
448 #define SYS_CTRL_PHY_RST BIT(2)
449 #define SYS_CTRL_SW_RST BIT(1)
450 #define SYS_CTRL_REG_RST BIT(0)
451
452 /* Register for system interrupt */
453 #define MT7530_SYS_INT_EN 0x7008
454
455 /* Register for system interrupt status */
456 #define MT7530_SYS_INT_STS 0x700c
457
458 /* Register for PHY Indirect Access Control */
459 #define MT7531_PHY_IAC 0x701C
460 #define MT7531_PHY_ACS_ST BIT(31)
461 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
462 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
463 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
464 #define MT7531_MDIO_ST_MASK (0x3 << 16)
465 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
466 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
467 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
468 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
469 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
470 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
471
472 enum mt7531_phy_iac_cmd {
473 MT7531_MDIO_ADDR = 0,
474 MT7531_MDIO_WRITE = 1,
475 MT7531_MDIO_READ = 2,
476 MT7531_MDIO_READ_CL45 = 3,
477 };
478
479 /* MDIO_ST: MDIO start field */
480 enum mt7531_mdio_st {
481 MT7531_MDIO_ST_CL45 = 0,
482 MT7531_MDIO_ST_CL22 = 1,
483 };
484
485 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
486 MT7531_MDIO_CMD(MT7531_MDIO_READ))
487 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
488 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
489 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
490 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
491 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
492 MT7531_MDIO_CMD(MT7531_MDIO_READ))
493 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
494 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
495
496 /* Register for RGMII clock phase */
497 #define MT7531_CLKGEN_CTRL 0x7500
498 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
499 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
500 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
501 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
502 #define RXCLK_NO_DELAY BIT(5)
503 #define TXCLK_NO_REVERSE BIT(4)
504 #define GP_MODE(x) (((x) & 0x3) << 1)
505 #define GP_MODE_MASK GENMASK(2, 1)
506 #define GP_CLK_EN BIT(0)
507
508 enum mt7531_gp_mode {
509 MT7531_GP_MODE_RGMII = 0,
510 MT7531_GP_MODE_MII = 1,
511 MT7531_GP_MODE_REV_MII = 2
512 };
513
514 enum mt7531_clk_skew {
515 MT7531_CLK_SKEW_NO_CHG = 0,
516 MT7531_CLK_SKEW_DLY_100PPS = 1,
517 MT7531_CLK_SKEW_DLY_200PPS = 2,
518 MT7531_CLK_SKEW_REVERSE = 3,
519 };
520
521 /* Register for trap status */
522 #define MT753X_TRAP 0x7800
523 #define MT7530_XTAL_MASK (BIT(10) | BIT(9))
524 #define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
525 #define MT7530_XTAL_40MHZ BIT(10)
526 #define MT7530_XTAL_20MHZ BIT(9)
527 #define MT7531_XTAL25 BIT(7)
528
529 /* Register for trap modification */
530 #define MT753X_MTRAP 0x7804
531 #define MT7530_P5_PHY0_SEL BIT(20)
532 #define MT7530_CHG_TRAP BIT(16)
533 #define MT7530_P5_MAC_SEL BIT(13)
534 #define MT7530_P6_DIS BIT(8)
535 #define MT7530_P5_RGMII_MODE BIT(7)
536 #define MT7530_P5_DIS BIT(6)
537 #define MT7530_PHY_INDIRECT_ACCESS BIT(5)
538 #define MT7531_CHG_STRAP BIT(8)
539 #define MT7531_PHY_EN BIT(6)
540
541 enum mt7531_xtal_fsel {
542 MT7531_XTAL_FSEL_25MHZ,
543 MT7531_XTAL_FSEL_40MHZ,
544 };
545
546 /* Register for TOP signal control */
547 #define MT7530_TOP_SIG_CTRL 0x7808
548 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
549
550 #define MT7531_TOP_SIG_SR 0x780c
551 #define PAD_DUAL_SGMII_EN BIT(1)
552 #define PAD_MCM_SMI_EN BIT(0)
553
554 #define MT7530_IO_DRV_CR 0x7810
555 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
556 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
557
558 #define MT7531_CHIP_REV 0x781C
559
560 #define MT7531_PLLGP_EN 0x7820
561 #define EN_COREPLL BIT(2)
562 #define SW_CLKSW BIT(1)
563 #define SW_PLLGP BIT(0)
564
565 #define MT7530_P6ECR 0x7830
566 #define P6_INTF_MODE_MASK 0x3
567 #define P6_INTF_MODE(x) ((x) & 0x3)
568
569 #define MT7531_PLLGP_CR0 0x78a8
570 #define RG_COREPLL_EN BIT(22)
571 #define RG_COREPLL_POSDIV_S 23
572 #define RG_COREPLL_POSDIV_M 0x3800000
573 #define RG_COREPLL_SDM_PCW_S 1
574 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
575 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
576
577 /* Registers for RGMII and SGMII PLL clock */
578 #define MT7531_ANA_PLLGP_CR2 0x78b0
579 #define MT7531_ANA_PLLGP_CR5 0x78bc
580
581 /* Registers for TRGMII on the both side */
582 #define MT7530_TRGMII_RCK_CTRL 0x7a00
583 #define RX_RST BIT(31)
584 #define RXC_DQSISEL BIT(30)
585 #define DQSI1_TAP_MASK (0x7f << 8)
586 #define DQSI0_TAP_MASK 0x7f
587 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
588 #define DQSI0_TAP(x) ((x) & 0x7f)
589
590 #define MT7530_TRGMII_RCK_RTT 0x7a04
591 #define DQS1_GATE BIT(31)
592 #define DQS0_GATE BIT(30)
593
594 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
595 #define BSLIP_EN BIT(31)
596 #define EDGE_CHK BIT(30)
597 #define RD_TAP_MASK 0x7f
598 #define RD_TAP(x) ((x) & 0x7f)
599
600 #define MT7530_TRGMII_TXCTRL 0x7a40
601 #define TRAIN_TXEN BIT(31)
602 #define TXC_INV BIT(30)
603 #define TX_RST BIT(28)
604
605 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
606 #define TD_DM_DRVP(x) ((x) & 0xf)
607 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
608
609 #define MT7530_TRGMII_TCK_CTRL 0x7a78
610 #define TCK_TAP(x) (((x) & 0xf) << 8)
611
612 #define MT7530_P5RGMIIRXCR 0x7b00
613 #define CSR_RGMII_EDGE_ALIGN BIT(8)
614 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
615
616 #define MT7530_P5RGMIITXCR 0x7b04
617 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
618
619 /* Registers for GPIO mode */
620 #define MT7531_GPIO_MODE0 0x7c0c
621 #define MT7531_GPIO0_MASK GENMASK(3, 0)
622 #define MT7531_GPIO0_INTERRUPT 1
623
624 #define MT7531_GPIO_MODE1 0x7c10
625 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
626 #define MT7531_EXT_P_MDC_11 (2 << 12)
627 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
628 #define MT7531_EXT_P_MDIO_12 (2 << 16)
629
630 /* Registers for LED GPIO control (MT7530 only)
631 * All registers follow this pattern:
632 * [ 2: 0] port 0
633 * [ 6: 4] port 1
634 * [10: 8] port 2
635 * [14:12] port 3
636 * [18:16] port 4
637 */
638
639 /* LED enable, 0: Disable, 1: Enable (Default) */
640 #define MT7530_LED_EN 0x7d00
641 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
642 #define MT7530_LED_IO_MODE 0x7d04
643 /* GPIO direction, 0: Input, 1: Output */
644 #define MT7530_LED_GPIO_DIR 0x7d10
645 /* GPIO output enable, 0: Disable, 1: Enable */
646 #define MT7530_LED_GPIO_OE 0x7d14
647 /* GPIO value, 0: Low, 1: High */
648 #define MT7530_LED_GPIO_DATA 0x7d18
649
650 #define MT7530_CREV 0x7ffc
651 #define CHIP_NAME_SHIFT 16
652 #define MT7530_ID 0x7530
653
654 #define MT7531_CREV 0x781C
655 #define CHIP_REV_M 0x0f
656 #define MT7531_ID 0x7531
657
658 /* Registers for core PLL access through mmd indirect */
659 #define CORE_PLL_GROUP2 0x401
660 #define RG_SYSPLL_EN_NORMAL BIT(15)
661 #define RG_SYSPLL_VODEN BIT(14)
662 #define RG_SYSPLL_LF BIT(13)
663 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
664 #define RG_SYSPLL_LVROD_EN BIT(10)
665 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
666 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
667 #define RG_SYSPLL_FBKSEL BIT(4)
668 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
669
670 #define CORE_PLL_GROUP4 0x403
671 #define RG_SYSPLL_DDSFBK_EN BIT(12)
672 #define RG_SYSPLL_BIAS_EN BIT(11)
673 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
674 #define MT7531_RG_SYSPLL_DMY2 BIT(6)
675 #define MT7531_PHY_PLL_OFF BIT(5)
676 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
677
678 #define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
679
680 #define CORE_PLL_GROUP5 0x404
681 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
682
683 #define CORE_PLL_GROUP6 0x405
684 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
685
686 #define CORE_PLL_GROUP7 0x406
687 #define RG_LCDDS_PWDB BIT(15)
688 #define RG_LCDDS_ISO_EN BIT(13)
689 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
690 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
691
692 #define CORE_PLL_GROUP10 0x409
693 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
694
695 #define CORE_PLL_GROUP11 0x40a
696 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
697
698 #define CORE_GSWPLL_GRP1 0x40d
699 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
700 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
701 #define RG_GSWPLL_EN_PRE BIT(11)
702 #define RG_GSWPLL_FBKSEL BIT(10)
703 #define RG_GSWPLL_BP BIT(9)
704 #define RG_GSWPLL_BR BIT(8)
705 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
706
707 #define CORE_GSWPLL_GRP2 0x40e
708 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
709 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
710
711 #define CORE_TRGMII_GSW_CLK_CG 0x410
712 #define REG_GSWCK_EN BIT(0)
713 #define REG_TRGMIICK_EN BIT(1)
714
715 #define MIB_DESC(_s, _o, _n) \
716 { \
717 .size = (_s), \
718 .offset = (_o), \
719 .name = (_n), \
720 }
721
722 struct mt7530_mib_desc {
723 unsigned int size;
724 unsigned int offset;
725 const char *name;
726 };
727
728 struct mt7530_fdb {
729 u16 vid;
730 u8 port_mask;
731 u8 aging;
732 u8 mac[6];
733 bool noarp;
734 };
735
736 /* struct mt7530_port - This is the main data structure for holding the state
737 * of the port.
738 * @enable: The status used for show port is enabled or not.
739 * @pm: The matrix used to show all connections with the port.
740 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
741 * untagged frames will be assigned to the related VLAN.
742 * @sgmii_pcs: Pointer to PCS instance for SerDes ports
743 */
744 struct mt7530_port {
745 bool enable;
746 bool isolated;
747 u32 pm;
748 u16 pvid;
749 struct phylink_pcs *sgmii_pcs;
750 };
751
752 /* Port 5 mode definitions of the MT7530 switch */
753 enum mt7530_p5_mode {
754 GMAC5,
755 MUX_PHY_P0,
756 MUX_PHY_P4,
757 };
758
759 struct mt7530_priv;
760
761 struct mt753x_pcs {
762 struct phylink_pcs pcs;
763 struct mt7530_priv *priv;
764 int port;
765 };
766
767 /* struct mt753x_info - This is the main data structure for holding the specific
768 * part for each supported device
769 * @id: Holding the identifier to a switch model
770 * @pcs_ops: Holding the pointer to the MAC PCS operations structure
771 * @sw_setup: Holding the handler to a device initialization
772 * @phy_read_c22: Holding the way reading PHY port using C22
773 * @phy_write_c22: Holding the way writing PHY port using C22
774 * @phy_read_c45: Holding the way reading PHY port using C45
775 * @phy_write_c45: Holding the way writing PHY port using C45
776 * @mac_port_get_caps: Holding the handler that provides MAC capabilities
777 * @mac_port_config: Holding the way setting up the PHY attribute to a
778 * certain MAC port
779 */
780 struct mt753x_info {
781 enum mt753x_id id;
782
783 const struct phylink_pcs_ops *pcs_ops;
784
785 int (*sw_setup)(struct dsa_switch *ds);
786 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
787 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
788 u16 val);
789 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
790 int regnum);
791 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
792 int regnum, u16 val);
793 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
794 struct phylink_config *config);
795 void (*mac_port_config)(struct dsa_switch *ds, int port,
796 unsigned int mode,
797 phy_interface_t interface);
798 };
799
800 /* struct mt7530_priv - This is the main data structure for holding the state
801 * of the driver
802 * @dev: The device pointer
803 * @ds: The pointer to the dsa core structure
804 * @bus: The bus used for the device and built-in PHY
805 * @regmap: The regmap instance representing all switch registers
806 * @rstc: The pointer to reset control used by MCM
807 * @core_pwr: The power supplied into the core
808 * @io_pwr: The power supplied into the I/O
809 * @reset: The descriptor for GPIO line tied to its reset pin
810 * @mcm: Flag for distinguishing if standalone IC or module
811 * coupling
812 * @ports: Holding the state among ports
813 * @reg_mutex: The lock for protecting among process accessing
814 * registers
815 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
816 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
817 * has got SGMII
818 * @irq: IRQ number of the switch
819 * @irq_domain: IRQ domain of the switch irq_chip
820 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
821 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
822 * @active_cpu_ports: Holding the active CPU ports
823 * @mdiodev: The pointer to the MDIO device structure
824 */
825 struct mt7530_priv {
826 struct device *dev;
827 struct dsa_switch *ds;
828 struct mii_bus *bus;
829 struct regmap *regmap;
830 struct reset_control *rstc;
831 struct regulator *core_pwr;
832 struct regulator *io_pwr;
833 struct gpio_desc *reset;
834 const struct mt753x_info *info;
835 unsigned int id;
836 bool mcm;
837 enum mt7530_p5_mode p5_mode;
838 bool p5_sgmii;
839 u8 mirror_rx;
840 u8 mirror_tx;
841 struct mt7530_port ports[MT7530_NUM_PORTS];
842 struct mt753x_pcs pcs[MT7530_NUM_PORTS];
843 /* protect among processes for registers access*/
844 struct mutex reg_mutex;
845 int irq;
846 struct irq_domain *irq_domain;
847 u32 irq_enable;
848 int (*create_sgmii)(struct mt7530_priv *priv);
849 u8 active_cpu_ports;
850 struct mdio_device *mdiodev;
851 };
852
853 struct mt7530_hw_vlan_entry {
854 int port;
855 u8 old_members;
856 bool untagged;
857 };
858
mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry * e,int port,bool untagged)859 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
860 int port, bool untagged)
861 {
862 e->port = port;
863 e->untagged = untagged;
864 }
865
866 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
867 struct mt7530_hw_vlan_entry *);
868
869 struct mt7530_hw_stats {
870 const char *string;
871 u16 reg;
872 u8 sizeof_stat;
873 };
874
875 struct mt7530_dummy_poll {
876 struct mt7530_priv *priv;
877 u32 reg;
878 };
879
INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll * p,struct mt7530_priv * priv,u32 reg)880 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
881 struct mt7530_priv *priv, u32 reg)
882 {
883 p->priv = priv;
884 p->reg = reg;
885 }
886
887 int mt7530_probe_common(struct mt7530_priv *priv);
888 void mt7530_remove_common(struct mt7530_priv *priv);
889
890 extern const struct dsa_switch_ops mt7530_switch_ops;
891 extern const struct mt753x_info mt753x_table[];
892
893 #endif /* __MT7530_H */
894