1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 #define MT7530_STATS_POLL_INTERVAL (1 * HZ) 29 #define MT7530_STATS_RATE_LIMIT (HZ / 10) 30 31 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 32 { 33 return container_of(pcs, struct mt753x_pcs, pcs); 34 } 35 36 /* String, offset, and register size in bytes if different from 4 bytes */ 37 static const struct mt7530_mib_desc mt7530_mib[] = { 38 MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"), 39 MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"), 40 MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"), 41 MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"), 42 MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"), 43 MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"), 44 MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"), 45 MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"), 46 MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"), 47 }; 48 49 static void 50 mt7530_mutex_lock(struct mt7530_priv *priv) 51 { 52 if (priv->bus) 53 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 54 } 55 56 static void 57 mt7530_mutex_unlock(struct mt7530_priv *priv) 58 { 59 if (priv->bus) 60 mutex_unlock(&priv->bus->mdio_lock); 61 } 62 63 static void 64 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 65 { 66 struct mii_bus *bus = priv->bus; 67 int ret; 68 69 mt7530_mutex_lock(priv); 70 71 /* Write the desired MMD Devad */ 72 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 73 MII_MMD_CTRL, MDIO_MMD_VEND2); 74 if (ret < 0) 75 goto err; 76 77 /* Write the desired MMD register address */ 78 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 79 MII_MMD_DATA, reg); 80 if (ret < 0) 81 goto err; 82 83 /* Select the Function : DATA with no post increment */ 84 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 85 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 86 if (ret < 0) 87 goto err; 88 89 /* Write the data into MMD's selected register */ 90 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 91 MII_MMD_DATA, val); 92 err: 93 if (ret < 0) 94 dev_err(&bus->dev, "failed to write mmd register\n"); 95 96 mt7530_mutex_unlock(priv); 97 } 98 99 static void 100 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 101 { 102 struct mii_bus *bus = priv->bus; 103 u32 val; 104 int ret; 105 106 mt7530_mutex_lock(priv); 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 110 MII_MMD_CTRL, MDIO_MMD_VEND2); 111 if (ret < 0) 112 goto err; 113 114 /* Write the desired MMD register address */ 115 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 116 MII_MMD_DATA, reg); 117 if (ret < 0) 118 goto err; 119 120 /* Select the Function : DATA with no post increment */ 121 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 122 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 123 if (ret < 0) 124 goto err; 125 126 /* Read the content of the MMD's selected register */ 127 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 128 MII_MMD_DATA); 129 val &= ~mask; 130 val |= set; 131 /* Write the data into MMD's selected register */ 132 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 133 MII_MMD_DATA, val); 134 err: 135 if (ret < 0) 136 dev_err(&bus->dev, "failed to write mmd register\n"); 137 138 mt7530_mutex_unlock(priv); 139 } 140 141 static void 142 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 143 { 144 core_rmw(priv, reg, 0, val); 145 } 146 147 static void 148 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 149 { 150 core_rmw(priv, reg, val, 0); 151 } 152 153 static int 154 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 155 { 156 int ret; 157 158 ret = regmap_write(priv->regmap, reg, val); 159 160 if (ret < 0) 161 dev_err(priv->dev, 162 "failed to write mt7530 register\n"); 163 164 return ret; 165 } 166 167 static u32 168 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 169 { 170 int ret; 171 u32 val; 172 173 ret = regmap_read(priv->regmap, reg, &val); 174 if (ret) { 175 WARN_ON_ONCE(1); 176 dev_err(priv->dev, 177 "failed to read mt7530 register\n"); 178 return 0; 179 } 180 181 return val; 182 } 183 184 static void 185 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 mt7530_mutex_lock(priv); 188 189 mt7530_mii_write(priv, reg, val); 190 191 mt7530_mutex_unlock(priv); 192 } 193 194 static u32 195 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 196 { 197 return mt7530_mii_read(p->priv, p->reg); 198 } 199 200 static u32 201 _mt7530_read(struct mt7530_dummy_poll *p) 202 { 203 u32 val; 204 205 mt7530_mutex_lock(p->priv); 206 207 val = mt7530_mii_read(p->priv, p->reg); 208 209 mt7530_mutex_unlock(p->priv); 210 211 return val; 212 } 213 214 static u32 215 mt7530_read(struct mt7530_priv *priv, u32 reg) 216 { 217 struct mt7530_dummy_poll p; 218 219 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 220 return _mt7530_read(&p); 221 } 222 223 static void 224 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 225 u32 mask, u32 set) 226 { 227 mt7530_mutex_lock(priv); 228 229 regmap_update_bits(priv->regmap, reg, mask, set); 230 231 mt7530_mutex_unlock(priv); 232 } 233 234 static void 235 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 236 { 237 mt7530_rmw(priv, reg, val, val); 238 } 239 240 static void 241 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 242 { 243 mt7530_rmw(priv, reg, val, 0); 244 } 245 246 static int 247 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 248 { 249 u32 val; 250 int ret; 251 struct mt7530_dummy_poll p; 252 253 /* Set the command operating upon the MAC address entries */ 254 val = ATC_BUSY | ATC_MAT(0) | cmd; 255 mt7530_write(priv, MT7530_ATC, val); 256 257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 258 ret = readx_poll_timeout(_mt7530_read, &p, val, 259 !(val & ATC_BUSY), 20, 20000); 260 if (ret < 0) { 261 dev_err(priv->dev, "reset timeout\n"); 262 return ret; 263 } 264 265 /* Additional sanity for read command if the specified 266 * entry is invalid 267 */ 268 val = mt7530_read(priv, MT7530_ATC); 269 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 270 return -EINVAL; 271 272 if (rsp) 273 *rsp = val; 274 275 return 0; 276 } 277 278 static void 279 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 280 { 281 u32 reg[3]; 282 int i; 283 284 /* Read from ARL table into an array */ 285 for (i = 0; i < 3; i++) { 286 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 287 288 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 289 __func__, __LINE__, i, reg[i]); 290 } 291 292 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 293 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 294 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 295 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 296 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 297 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 298 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 299 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 300 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 301 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 302 } 303 304 static void 305 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 306 u8 port_mask, const u8 *mac, 307 u8 aging, u8 type) 308 { 309 u32 reg[3] = { 0 }; 310 int i; 311 312 reg[1] |= vid & CVID_MASK; 313 reg[1] |= ATA2_IVL; 314 reg[1] |= ATA2_FID(FID_BRIDGED); 315 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 316 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 317 /* STATIC_ENT indicate that entry is static wouldn't 318 * be aged out and STATIC_EMP specified as erasing an 319 * entry 320 */ 321 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 322 reg[1] |= mac[5] << MAC_BYTE_5; 323 reg[1] |= mac[4] << MAC_BYTE_4; 324 reg[0] |= mac[3] << MAC_BYTE_3; 325 reg[0] |= mac[2] << MAC_BYTE_2; 326 reg[0] |= mac[1] << MAC_BYTE_1; 327 reg[0] |= mac[0] << MAC_BYTE_0; 328 329 /* Write array into the ARL table */ 330 for (i = 0; i < 3; i++) 331 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 332 } 333 334 /* Set up switch core clock for MT7530 */ 335 static void mt7530_pll_setup(struct mt7530_priv *priv) 336 { 337 /* Disable core clock */ 338 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 339 340 /* Disable PLL */ 341 core_write(priv, CORE_GSWPLL_GRP1, 0); 342 343 /* Set core clock into 500Mhz */ 344 core_write(priv, CORE_GSWPLL_GRP2, 345 RG_GSWPLL_POSDIV_500M(1) | 346 RG_GSWPLL_FBKDIV_500M(25)); 347 348 /* Enable PLL */ 349 core_write(priv, CORE_GSWPLL_GRP1, 350 RG_GSWPLL_EN_PRE | 351 RG_GSWPLL_POSDIV_200M(2) | 352 RG_GSWPLL_FBKDIV_200M(32)); 353 354 udelay(20); 355 356 /* Enable core clock */ 357 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 358 } 359 360 /* If port 6 is available as a CPU port, always prefer that as the default, 361 * otherwise don't care. 362 */ 363 static struct dsa_port * 364 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 365 { 366 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 367 368 if (dsa_port_is_cpu(cpu_dp)) 369 return cpu_dp; 370 371 return NULL; 372 } 373 374 /* Setup port 6 interface mode and TRGMII TX circuit */ 375 static void 376 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 377 { 378 struct mt7530_priv *priv = ds->priv; 379 u32 ncpo1, ssc_delta, xtal; 380 381 /* Disable the MT7530 TRGMII clocks */ 382 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 383 384 if (interface == PHY_INTERFACE_MODE_RGMII) { 385 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 386 P6_INTF_MODE(0)); 387 return; 388 } 389 390 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 391 392 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 393 394 if (xtal == MT7530_XTAL_25MHZ) 395 ssc_delta = 0x57; 396 else 397 ssc_delta = 0x87; 398 399 if (priv->id == ID_MT7621) { 400 /* PLL frequency: 125MHz: 1.0GBit */ 401 if (xtal == MT7530_XTAL_40MHZ) 402 ncpo1 = 0x0640; 403 if (xtal == MT7530_XTAL_25MHZ) 404 ncpo1 = 0x0a00; 405 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 406 if (xtal == MT7530_XTAL_40MHZ) 407 ncpo1 = 0x0c80; 408 if (xtal == MT7530_XTAL_25MHZ) 409 ncpo1 = 0x1400; 410 } 411 412 /* Setup the MT7530 TRGMII Tx Clock */ 413 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 414 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 415 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 416 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 417 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 418 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 419 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 420 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 421 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 422 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 423 424 /* Enable the MT7530 TRGMII clocks */ 425 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 426 } 427 428 static void 429 mt7531_pll_setup(struct mt7530_priv *priv) 430 { 431 enum mt7531_xtal_fsel xtal; 432 u32 top_sig; 433 u32 hwstrap; 434 u32 val; 435 436 val = mt7530_read(priv, MT7531_CREV); 437 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 438 hwstrap = mt7530_read(priv, MT753X_TRAP); 439 if ((val & CHIP_REV_M) > 0) 440 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 441 MT7531_XTAL_FSEL_25MHZ; 442 else 443 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 444 MT7531_XTAL_FSEL_40MHZ; 445 446 /* Step 1 : Disable MT7531 COREPLL */ 447 val = mt7530_read(priv, MT7531_PLLGP_EN); 448 val &= ~EN_COREPLL; 449 mt7530_write(priv, MT7531_PLLGP_EN, val); 450 451 /* Step 2: switch to XTAL output */ 452 val = mt7530_read(priv, MT7531_PLLGP_EN); 453 val |= SW_CLKSW; 454 mt7530_write(priv, MT7531_PLLGP_EN, val); 455 456 val = mt7530_read(priv, MT7531_PLLGP_CR0); 457 val &= ~RG_COREPLL_EN; 458 mt7530_write(priv, MT7531_PLLGP_CR0, val); 459 460 /* Step 3: disable PLLGP and enable program PLLGP */ 461 val = mt7530_read(priv, MT7531_PLLGP_EN); 462 val |= SW_PLLGP; 463 mt7530_write(priv, MT7531_PLLGP_EN, val); 464 465 /* Step 4: program COREPLL output frequency to 500MHz */ 466 val = mt7530_read(priv, MT7531_PLLGP_CR0); 467 val &= ~RG_COREPLL_POSDIV_M; 468 val |= 2 << RG_COREPLL_POSDIV_S; 469 mt7530_write(priv, MT7531_PLLGP_CR0, val); 470 usleep_range(25, 35); 471 472 switch (xtal) { 473 case MT7531_XTAL_FSEL_25MHZ: 474 val = mt7530_read(priv, MT7531_PLLGP_CR0); 475 val &= ~RG_COREPLL_SDM_PCW_M; 476 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 477 mt7530_write(priv, MT7531_PLLGP_CR0, val); 478 break; 479 case MT7531_XTAL_FSEL_40MHZ: 480 val = mt7530_read(priv, MT7531_PLLGP_CR0); 481 val &= ~RG_COREPLL_SDM_PCW_M; 482 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 483 mt7530_write(priv, MT7531_PLLGP_CR0, val); 484 break; 485 } 486 487 /* Set feedback divide ratio update signal to high */ 488 val = mt7530_read(priv, MT7531_PLLGP_CR0); 489 val |= RG_COREPLL_SDM_PCW_CHG; 490 mt7530_write(priv, MT7531_PLLGP_CR0, val); 491 /* Wait for at least 16 XTAL clocks */ 492 usleep_range(10, 20); 493 494 /* Step 5: set feedback divide ratio update signal to low */ 495 val = mt7530_read(priv, MT7531_PLLGP_CR0); 496 val &= ~RG_COREPLL_SDM_PCW_CHG; 497 mt7530_write(priv, MT7531_PLLGP_CR0, val); 498 499 /* Enable 325M clock for SGMII */ 500 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 501 502 /* Enable 250SSC clock for RGMII */ 503 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 504 505 /* Step 6: Enable MT7531 PLL */ 506 val = mt7530_read(priv, MT7531_PLLGP_CR0); 507 val |= RG_COREPLL_EN; 508 mt7530_write(priv, MT7531_PLLGP_CR0, val); 509 510 val = mt7530_read(priv, MT7531_PLLGP_EN); 511 val |= EN_COREPLL; 512 mt7530_write(priv, MT7531_PLLGP_EN, val); 513 usleep_range(25, 35); 514 } 515 516 static void 517 mt7530_mib_reset(struct dsa_switch *ds) 518 { 519 struct mt7530_priv *priv = ds->priv; 520 521 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 522 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 523 } 524 525 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 526 { 527 return mdiobus_read_nested(priv->bus, port, regnum); 528 } 529 530 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 531 u16 val) 532 { 533 return mdiobus_write_nested(priv->bus, port, regnum, val); 534 } 535 536 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 537 int devad, int regnum) 538 { 539 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 540 } 541 542 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 543 int regnum, u16 val) 544 { 545 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 546 } 547 548 static int 549 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 550 int regnum) 551 { 552 struct mt7530_dummy_poll p; 553 u32 reg, val; 554 int ret; 555 556 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 557 558 mt7530_mutex_lock(priv); 559 560 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 561 !(val & MT7531_PHY_ACS_ST), 20, 100000); 562 if (ret < 0) { 563 dev_err(priv->dev, "poll timeout\n"); 564 goto out; 565 } 566 567 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 568 MT7531_MDIO_DEV_ADDR(devad) | regnum; 569 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 570 571 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 572 !(val & MT7531_PHY_ACS_ST), 20, 100000); 573 if (ret < 0) { 574 dev_err(priv->dev, "poll timeout\n"); 575 goto out; 576 } 577 578 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 579 MT7531_MDIO_DEV_ADDR(devad); 580 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 581 582 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 583 !(val & MT7531_PHY_ACS_ST), 20, 100000); 584 if (ret < 0) { 585 dev_err(priv->dev, "poll timeout\n"); 586 goto out; 587 } 588 589 ret = val & MT7531_MDIO_RW_DATA_MASK; 590 out: 591 mt7530_mutex_unlock(priv); 592 593 return ret; 594 } 595 596 static int 597 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 598 int regnum, u16 data) 599 { 600 struct mt7530_dummy_poll p; 601 u32 val, reg; 602 int ret; 603 604 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 605 606 mt7530_mutex_lock(priv); 607 608 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 609 !(val & MT7531_PHY_ACS_ST), 20, 100000); 610 if (ret < 0) { 611 dev_err(priv->dev, "poll timeout\n"); 612 goto out; 613 } 614 615 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 616 MT7531_MDIO_DEV_ADDR(devad) | regnum; 617 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 618 619 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 620 !(val & MT7531_PHY_ACS_ST), 20, 100000); 621 if (ret < 0) { 622 dev_err(priv->dev, "poll timeout\n"); 623 goto out; 624 } 625 626 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 627 MT7531_MDIO_DEV_ADDR(devad) | data; 628 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 629 630 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 631 !(val & MT7531_PHY_ACS_ST), 20, 100000); 632 if (ret < 0) { 633 dev_err(priv->dev, "poll timeout\n"); 634 goto out; 635 } 636 637 out: 638 mt7530_mutex_unlock(priv); 639 640 return ret; 641 } 642 643 static int 644 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 645 { 646 struct mt7530_dummy_poll p; 647 int ret; 648 u32 val; 649 650 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 651 652 mt7530_mutex_lock(priv); 653 654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 655 !(val & MT7531_PHY_ACS_ST), 20, 100000); 656 if (ret < 0) { 657 dev_err(priv->dev, "poll timeout\n"); 658 goto out; 659 } 660 661 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 662 MT7531_MDIO_REG_ADDR(regnum); 663 664 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 665 666 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 667 !(val & MT7531_PHY_ACS_ST), 20, 100000); 668 if (ret < 0) { 669 dev_err(priv->dev, "poll timeout\n"); 670 goto out; 671 } 672 673 ret = val & MT7531_MDIO_RW_DATA_MASK; 674 out: 675 mt7530_mutex_unlock(priv); 676 677 return ret; 678 } 679 680 static int 681 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 682 u16 data) 683 { 684 struct mt7530_dummy_poll p; 685 int ret; 686 u32 reg; 687 688 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 689 690 mt7530_mutex_lock(priv); 691 692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 693 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 694 if (ret < 0) { 695 dev_err(priv->dev, "poll timeout\n"); 696 goto out; 697 } 698 699 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 700 MT7531_MDIO_REG_ADDR(regnum) | data; 701 702 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 703 704 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 705 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 706 if (ret < 0) { 707 dev_err(priv->dev, "poll timeout\n"); 708 goto out; 709 } 710 711 out: 712 mt7530_mutex_unlock(priv); 713 714 return ret; 715 } 716 717 static int 718 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 719 { 720 struct mt7530_priv *priv = bus->priv; 721 722 return priv->info->phy_read_c22(priv, port, regnum); 723 } 724 725 static int 726 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 727 { 728 struct mt7530_priv *priv = bus->priv; 729 730 return priv->info->phy_read_c45(priv, port, devad, regnum); 731 } 732 733 static int 734 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 735 { 736 struct mt7530_priv *priv = bus->priv; 737 738 return priv->info->phy_write_c22(priv, port, regnum, val); 739 } 740 741 static int 742 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 743 u16 val) 744 { 745 struct mt7530_priv *priv = bus->priv; 746 747 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 748 } 749 750 static void 751 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 752 uint8_t *data) 753 { 754 int i; 755 756 if (stringset != ETH_SS_STATS) 757 return; 758 759 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 760 ethtool_puts(&data, mt7530_mib[i].name); 761 } 762 763 static void 764 mt7530_read_port_stats(struct mt7530_priv *priv, int port, 765 u32 offset, u8 size, uint64_t *data) 766 { 767 u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset; 768 769 val = mt7530_read(priv, reg); 770 *data = val; 771 772 if (size == 2) { 773 val = mt7530_read(priv, reg + 4); 774 *data |= (u64)val << 32; 775 } 776 } 777 778 static void 779 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 780 uint64_t *data) 781 { 782 struct mt7530_priv *priv = ds->priv; 783 const struct mt7530_mib_desc *mib; 784 int i; 785 786 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 787 mib = &mt7530_mib[i]; 788 789 mt7530_read_port_stats(priv, port, mib->offset, mib->size, 790 data + i); 791 } 792 } 793 794 static int 795 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 796 { 797 if (sset != ETH_SS_STATS) 798 return 0; 799 800 return ARRAY_SIZE(mt7530_mib); 801 } 802 803 static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port, 804 struct ethtool_eth_mac_stats *mac_stats) 805 { 806 struct mt7530_priv *priv = ds->priv; 807 808 /* MIB counter doesn't provide a FramesTransmittedOK but instead 809 * provide stats for Unicast, Broadcast and Multicast frames separately. 810 * To simulate a global frame counter, read Unicast and addition Multicast 811 * and Broadcast later 812 */ 813 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 814 &mac_stats->FramesTransmittedOK); 815 816 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1, 817 &mac_stats->SingleCollisionFrames); 818 819 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1, 820 &mac_stats->MultipleCollisionFrames); 821 822 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 823 &mac_stats->FramesReceivedOK); 824 825 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 826 &mac_stats->OctetsTransmittedOK); 827 828 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1, 829 &mac_stats->AlignmentErrors); 830 831 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1, 832 &mac_stats->FramesWithDeferredXmissions); 833 834 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1, 835 &mac_stats->LateCollisions); 836 837 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1, 838 &mac_stats->FramesAbortedDueToXSColls); 839 840 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 841 &mac_stats->OctetsReceivedOK); 842 843 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 844 &mac_stats->MulticastFramesXmittedOK); 845 mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK; 846 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 847 &mac_stats->BroadcastFramesXmittedOK); 848 mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK; 849 850 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 851 &mac_stats->MulticastFramesReceivedOK); 852 mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK; 853 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 854 &mac_stats->BroadcastFramesReceivedOK); 855 mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK; 856 } 857 858 static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = { 859 { 0, 64 }, 860 { 65, 127 }, 861 { 128, 255 }, 862 { 256, 511 }, 863 { 512, 1023 }, 864 { 1024, MT7530_MAX_MTU }, 865 {} 866 }; 867 868 static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port, 869 struct ethtool_rmon_stats *rmon_stats, 870 const struct ethtool_rmon_hist_range **ranges) 871 { 872 struct mt7530_priv *priv = ds->priv; 873 874 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1, 875 &rmon_stats->undersize_pkts); 876 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1, 877 &rmon_stats->oversize_pkts); 878 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1, 879 &rmon_stats->fragments); 880 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1, 881 &rmon_stats->jabbers); 882 883 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1, 884 &rmon_stats->hist[0]); 885 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1, 886 &rmon_stats->hist[1]); 887 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1, 888 &rmon_stats->hist[2]); 889 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1, 890 &rmon_stats->hist[3]); 891 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1, 892 &rmon_stats->hist[4]); 893 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1, 894 &rmon_stats->hist[5]); 895 896 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1, 897 &rmon_stats->hist_tx[0]); 898 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1, 899 &rmon_stats->hist_tx[1]); 900 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1, 901 &rmon_stats->hist_tx[2]); 902 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1, 903 &rmon_stats->hist_tx[3]); 904 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1, 905 &rmon_stats->hist_tx[4]); 906 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1, 907 &rmon_stats->hist_tx[5]); 908 909 *ranges = mt7530_rmon_ranges; 910 } 911 912 static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port, 913 struct rtnl_link_stats64 *storage) 914 { 915 uint64_t data; 916 917 /* MIB counter doesn't provide a FramesTransmittedOK but instead 918 * provide stats for Unicast, Broadcast and Multicast frames separately. 919 * To simulate a global frame counter, read Unicast and addition Multicast 920 * and Broadcast later 921 */ 922 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1, 923 &storage->rx_packets); 924 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1, 925 &storage->multicast); 926 storage->rx_packets += storage->multicast; 927 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1, 928 &data); 929 storage->rx_packets += data; 930 931 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1, 932 &storage->tx_packets); 933 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1, 934 &data); 935 storage->tx_packets += data; 936 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1, 937 &data); 938 storage->tx_packets += data; 939 940 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2, 941 &storage->rx_bytes); 942 943 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2, 944 &storage->tx_bytes); 945 946 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1, 947 &storage->rx_dropped); 948 949 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1, 950 &storage->tx_dropped); 951 952 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1, 953 &storage->rx_crc_errors); 954 } 955 956 static void mt7530_stats_refresh(struct mt7530_priv *priv) 957 { 958 struct rtnl_link_stats64 stats = {}; 959 struct dsa_port *dp; 960 int port; 961 962 dsa_switch_for_each_user_port(dp, priv->ds) { 963 port = dp->index; 964 965 mt7530_read_port_stats64(priv, port, &stats); 966 967 spin_lock_bh(&priv->stats_lock); 968 priv->ports[port].stats = stats; 969 priv->stats_last = jiffies; 970 spin_unlock_bh(&priv->stats_lock); 971 } 972 } 973 974 static void mt7530_stats_poll(struct work_struct *work) 975 { 976 struct mt7530_priv *priv = container_of(work, struct mt7530_priv, 977 stats_work.work); 978 979 mt7530_stats_refresh(priv); 980 schedule_delayed_work(&priv->stats_work, 981 MT7530_STATS_POLL_INTERVAL); 982 } 983 984 static void mt7530_get_stats64(struct dsa_switch *ds, int port, 985 struct rtnl_link_stats64 *storage) 986 { 987 struct mt7530_priv *priv = ds->priv; 988 bool refresh; 989 990 if (priv->bus) { 991 spin_lock_bh(&priv->stats_lock); 992 *storage = priv->ports[port].stats; 993 refresh = time_after(jiffies, priv->stats_last + 994 MT7530_STATS_RATE_LIMIT); 995 spin_unlock_bh(&priv->stats_lock); 996 if (refresh) 997 mod_delayed_work(system_percpu_wq, 998 &priv->stats_work, 0); 999 } else { 1000 mt7530_read_port_stats64(priv, port, storage); 1001 } 1002 } 1003 1004 static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 1005 struct ethtool_eth_ctrl_stats *ctrl_stats) 1006 { 1007 struct mt7530_priv *priv = ds->priv; 1008 1009 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1, 1010 &ctrl_stats->MACControlFramesTransmitted); 1011 1012 mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1, 1013 &ctrl_stats->MACControlFramesReceived); 1014 } 1015 1016 static int 1017 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1018 { 1019 struct mt7530_priv *priv = ds->priv; 1020 unsigned int secs = msecs / 1000; 1021 unsigned int tmp_age_count; 1022 unsigned int error = -1; 1023 unsigned int age_count; 1024 unsigned int age_unit; 1025 1026 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 1027 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 1028 return -ERANGE; 1029 1030 /* iterate through all possible age_count to find the closest pair */ 1031 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 1032 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 1033 1034 if (tmp_age_unit <= AGE_UNIT_MAX) { 1035 unsigned int tmp_error = secs - 1036 (tmp_age_count + 1) * (tmp_age_unit + 1); 1037 1038 /* found a closer pair */ 1039 if (error > tmp_error) { 1040 error = tmp_error; 1041 age_count = tmp_age_count; 1042 age_unit = tmp_age_unit; 1043 } 1044 1045 /* found the exact match, so break the loop */ 1046 if (!error) 1047 break; 1048 } 1049 } 1050 1051 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 1052 1053 return 0; 1054 } 1055 1056 static const char *mt7530_p5_mode_str(unsigned int mode) 1057 { 1058 switch (mode) { 1059 case MUX_PHY_P0: 1060 return "MUX PHY P0"; 1061 case MUX_PHY_P4: 1062 return "MUX PHY P4"; 1063 default: 1064 return "GMAC5"; 1065 } 1066 } 1067 1068 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 1069 { 1070 struct mt7530_priv *priv = ds->priv; 1071 u8 tx_delay = 0; 1072 int val; 1073 1074 mutex_lock(&priv->reg_mutex); 1075 1076 val = mt7530_read(priv, MT753X_MTRAP); 1077 1078 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 1079 1080 switch (priv->p5_mode) { 1081 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 1082 case MUX_PHY_P0: 1083 val |= MT7530_P5_PHY0_SEL; 1084 fallthrough; 1085 1086 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 1087 case MUX_PHY_P4: 1088 /* Setup the MAC by default for the cpu port */ 1089 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 1090 break; 1091 1092 /* GMAC5: P5 -> SoC MAC or external PHY */ 1093 default: 1094 val |= MT7530_P5_MAC_SEL; 1095 break; 1096 } 1097 1098 /* Setup RGMII settings */ 1099 if (phy_interface_mode_is_rgmii(interface)) { 1100 val |= MT7530_P5_RGMII_MODE; 1101 1102 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 1103 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 1104 1105 /* Don't set delay in DSA mode */ 1106 if (!dsa_is_dsa_port(priv->ds, 5) && 1107 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 1108 interface == PHY_INTERFACE_MODE_RGMII_ID)) 1109 tx_delay = 4; /* n * 0.5 ns */ 1110 1111 /* P5 RGMII TX Clock Control: delay x */ 1112 mt7530_write(priv, MT7530_P5RGMIITXCR, 1113 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 1114 1115 /* reduce P5 RGMII Tx driving, 8mA */ 1116 mt7530_write(priv, MT7530_IO_DRV_CR, 1117 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 1118 } 1119 1120 mt7530_write(priv, MT753X_MTRAP, val); 1121 1122 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 1123 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 1124 1125 mutex_unlock(&priv->reg_mutex); 1126 } 1127 1128 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 1129 * of the Open Systems Interconnection basic reference model (OSI/RM) are 1130 * described; the medium access control (MAC) and logical link control (LLC) 1131 * sublayers. The MAC sublayer is the one facing the physical layer. 1132 * 1133 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 1134 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 1135 * of the Bridge, at least two Ports, and higher layer entities with at least a 1136 * Spanning Tree Protocol Entity included. 1137 * 1138 * Each Bridge Port also functions as an end station and shall provide the MAC 1139 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 1140 * distinct LLC Entity that supports protocol identification, multiplexing, and 1141 * demultiplexing, for protocol data unit (PDU) transmission and reception by 1142 * one or more higher layer entities. 1143 * 1144 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 1145 * Entity associated with each Bridge Port is modeled as being directly 1146 * connected to the attached Local Area Network (LAN). 1147 * 1148 * On the switch with CPU port architecture, CPU port functions as Management 1149 * Port, and the Management Port functionality is provided by software which 1150 * functions as an end station. Software is connected to an IEEE 802 LAN that is 1151 * wholly contained within the system that incorporates the Bridge. Software 1152 * provides access to the LLC Entity associated with each Bridge Port by the 1153 * value of the source port field on the special tag on the frame received by 1154 * software. 1155 * 1156 * We call frames that carry control information to determine the active 1157 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 1158 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 1159 * Protocol Data Units (MVRPDUs), and frames from other link constrained 1160 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 1161 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 1162 * forwarded by a Bridge. Permanently configured entries in the filtering 1163 * database (FDB) ensure that such frames are discarded by the Forwarding 1164 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 1165 * 1166 * Each of the reserved MAC addresses specified in Table 8-1 1167 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 1168 * permanently configured in the FDB in C-VLAN components and ERs. 1169 * 1170 * Each of the reserved MAC addresses specified in Table 8-2 1171 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 1172 * configured in the FDB in S-VLAN components. 1173 * 1174 * Each of the reserved MAC addresses specified in Table 8-3 1175 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 1176 * TPMR components. 1177 * 1178 * The FDB entries for reserved MAC addresses shall specify filtering for all 1179 * Bridge Ports and all VIDs. Management shall not provide the capability to 1180 * modify or remove entries for reserved MAC addresses. 1181 * 1182 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 1183 * propagation of PDUs within a Bridged Network, as follows: 1184 * 1185 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 1186 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 1187 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 1188 * PDUs transmitted using this destination address, or any other addresses 1189 * that appear in Table 8-1, Table 8-2, and Table 8-3 1190 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 1191 * therefore travel no further than those stations that can be reached via a 1192 * single individual LAN from the originating station. 1193 * 1194 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1195 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1196 * Bridge can forward; however, this address is relayed by a TPMR component. 1197 * PDUs using this destination address, or any of the other addresses that 1198 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1199 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1200 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1201 * C-VLAN component, or MAC Bridge. 1202 * 1203 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1204 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1205 * relayed by TPMR components and S-VLAN components. PDUs using this 1206 * destination address, or any of the other addresses that appear in Table 8-1 1207 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1208 * will be relayed by TPMR components and S-VLAN components but will propagate 1209 * no further than the nearest C-VLAN component or MAC Bridge. 1210 * 1211 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1212 * port, we must not filter these frames but forward them to CPU port. 1213 * 1214 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1215 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1216 * For link-local frames, only CPU port should be designated as destination port 1217 * in the FDB, and the other functions of the Forwarding Process must not 1218 * interfere with the decision of the transmission Port. We call this process 1219 * trapping frames to CPU port. 1220 * 1221 * Therefore, on the switch with CPU port architecture, link-local frames must 1222 * be trapped to CPU port, and certain link-local frames received by a Port of a 1223 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1224 * from it. 1225 * 1226 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1227 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1228 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1229 * doesn't count) of this architecture will either function as a standard MAC 1230 * Bridge or a standard VLAN Bridge. 1231 * 1232 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1233 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1234 * we don't need to relay PDUs using the destination addresses specified on the 1235 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1236 * section where they must be relayed by TPMR components. 1237 * 1238 * One option to trap link-local frames to CPU port is to add static FDB entries 1239 * with CPU port designated as destination port. However, because that 1240 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1241 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1242 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1243 * entries. This switch intellectual property can only hold a maximum of 2048 1244 * entries. Using this option, there also isn't a mechanism to prevent 1245 * link-local frames from being discarded when the spanning tree Port State of 1246 * the reception Port is discarding. 1247 * 1248 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1249 * registers. Whilst this applies to every VID, it doesn't contain all of the 1250 * reserved MAC addresses without affecting the remaining Standard Group MAC 1251 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1252 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1253 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1254 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1255 * The latter option provides better but not complete conformance. 1256 * 1257 * This switch intellectual property also does not provide a mechanism to trap 1258 * link-local frames with specific destination addresses to CPU port by Bridge, 1259 * to conform to the filtering rules for the distinct Bridge components. 1260 * 1261 * Therefore, regardless of the type of the Bridge component, link-local frames 1262 * with these destination addresses will be trapped to CPU port: 1263 * 1264 * 01-80-C2-00-00-[00,01,02,03,0E] 1265 * 1266 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1267 * 1268 * Link-local frames with these destination addresses won't be trapped to CPU 1269 * port which won't conform to IEEE Std 802.1Q-2022: 1270 * 1271 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1272 * 1273 * In a Bridge comprising an S-VLAN component: 1274 * 1275 * Link-local frames with these destination addresses will be trapped to CPU 1276 * port which won't conform to IEEE Std 802.1Q-2022: 1277 * 1278 * 01-80-C2-00-00-00 1279 * 1280 * Link-local frames with these destination addresses won't be trapped to CPU 1281 * port which won't conform to IEEE Std 802.1Q-2022: 1282 * 1283 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1284 * 1285 * To trap link-local frames to CPU port as conformant as this switch 1286 * intellectual property can allow, link-local frames are made to be regarded as 1287 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1288 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1289 * State function of the Forwarding Process. 1290 * 1291 * The only remaining interference is the ingress rules. When the reception Port 1292 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1293 * There doesn't seem to be a mechanism on the switch intellectual property to 1294 * have link-local frames bypass this function of the Forwarding Process. 1295 */ 1296 static void 1297 mt753x_trap_frames(struct mt7530_priv *priv) 1298 { 1299 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1300 * VLAN-untagged. 1301 */ 1302 mt7530_rmw(priv, MT753X_BPC, 1303 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1304 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1305 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1306 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1307 BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1308 TO_CPU_FW_CPU_ONLY); 1309 1310 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1311 * them VLAN-untagged. 1312 */ 1313 mt7530_rmw(priv, MT753X_RGAC1, 1314 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1315 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1316 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1317 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1318 R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1319 TO_CPU_FW_CPU_ONLY); 1320 1321 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1322 * them VLAN-untagged. 1323 */ 1324 mt7530_rmw(priv, MT753X_RGAC2, 1325 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1326 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1327 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1328 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1329 R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1330 TO_CPU_FW_CPU_ONLY); 1331 } 1332 1333 static void 1334 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1335 { 1336 struct mt7530_priv *priv = ds->priv; 1337 1338 /* Enable Mediatek header mode on the cpu port */ 1339 mt7530_write(priv, MT7530_PVC_P(port), 1340 PORT_SPEC_TAG); 1341 1342 /* Enable flooding on the CPU port */ 1343 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1344 UNU_FFP(BIT(port))); 1345 1346 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1347 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1348 * is affine to the inbound user port. 1349 */ 1350 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1351 priv->id == ID_EN7581 || priv->id == ID_AN7583) 1352 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1353 1354 /* CPU port gets connected to all user ports of 1355 * the switch. 1356 */ 1357 mt7530_write(priv, MT7530_PCR_P(port), 1358 PCR_MATRIX(dsa_user_ports(priv->ds))); 1359 1360 /* Set to fallback mode for independent VLAN learning */ 1361 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1362 MT7530_PORT_FALLBACK_MODE); 1363 } 1364 1365 static int 1366 mt7530_port_enable(struct dsa_switch *ds, int port, 1367 struct phy_device *phy) 1368 { 1369 struct dsa_port *dp = dsa_to_port(ds, port); 1370 struct mt7530_priv *priv = ds->priv; 1371 1372 mutex_lock(&priv->reg_mutex); 1373 1374 /* Allow the user port gets connected to the cpu port and also 1375 * restore the port matrix if the port is the member of a certain 1376 * bridge. 1377 */ 1378 if (dsa_port_is_user(dp)) { 1379 struct dsa_port *cpu_dp = dp->cpu_dp; 1380 1381 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1382 } 1383 priv->ports[port].enable = true; 1384 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1385 priv->ports[port].pm); 1386 1387 mutex_unlock(&priv->reg_mutex); 1388 1389 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1390 return 0; 1391 1392 if (port == 5) 1393 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1394 else if (port == 6) 1395 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1396 1397 return 0; 1398 } 1399 1400 static void 1401 mt7530_port_disable(struct dsa_switch *ds, int port) 1402 { 1403 struct mt7530_priv *priv = ds->priv; 1404 1405 mutex_lock(&priv->reg_mutex); 1406 1407 /* Clear up all port matrix which could be restored in the next 1408 * enablement for the port. 1409 */ 1410 priv->ports[port].enable = false; 1411 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1412 PCR_MATRIX_CLR); 1413 1414 mutex_unlock(&priv->reg_mutex); 1415 1416 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1417 return; 1418 1419 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1420 if (port == 5 && priv->p5_mode == GMAC5) 1421 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1422 else if (port == 6) 1423 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1424 } 1425 1426 static int 1427 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1428 { 1429 struct mt7530_priv *priv = ds->priv; 1430 int length; 1431 u32 val; 1432 1433 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1434 * largest MTU of the user ports. Because the switch only has a global 1435 * RX length register, only allowing CPU port here is enough. 1436 */ 1437 if (!dsa_is_cpu_port(ds, port)) 1438 return 0; 1439 1440 mt7530_mutex_lock(priv); 1441 1442 val = mt7530_mii_read(priv, MT7530_GMACCR); 1443 val &= ~MAX_RX_PKT_LEN_MASK; 1444 1445 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1446 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1447 if (length <= 1522) { 1448 val |= MAX_RX_PKT_LEN_1522; 1449 } else if (length <= 1536) { 1450 val |= MAX_RX_PKT_LEN_1536; 1451 } else if (length <= 1552) { 1452 val |= MAX_RX_PKT_LEN_1552; 1453 } else { 1454 val &= ~MAX_RX_JUMBO_MASK; 1455 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1456 val |= MAX_RX_PKT_LEN_JUMBO; 1457 } 1458 1459 mt7530_mii_write(priv, MT7530_GMACCR, val); 1460 1461 mt7530_mutex_unlock(priv); 1462 1463 return 0; 1464 } 1465 1466 static int 1467 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1468 { 1469 return MT7530_MAX_MTU; 1470 } 1471 1472 static void 1473 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1474 { 1475 struct mt7530_priv *priv = ds->priv; 1476 u32 stp_state; 1477 1478 switch (state) { 1479 case BR_STATE_DISABLED: 1480 stp_state = MT7530_STP_DISABLED; 1481 break; 1482 case BR_STATE_BLOCKING: 1483 stp_state = MT7530_STP_BLOCKING; 1484 break; 1485 case BR_STATE_LISTENING: 1486 stp_state = MT7530_STP_LISTENING; 1487 break; 1488 case BR_STATE_LEARNING: 1489 stp_state = MT7530_STP_LEARNING; 1490 break; 1491 case BR_STATE_FORWARDING: 1492 default: 1493 stp_state = MT7530_STP_FORWARDING; 1494 break; 1495 } 1496 1497 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1498 FID_PST(FID_BRIDGED, stp_state)); 1499 } 1500 1501 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1502 const struct net_device *bridge_dev, 1503 bool join) __must_hold(&priv->reg_mutex) 1504 { 1505 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1506 struct mt7530_port *p = &priv->ports[port], *other_p; 1507 struct dsa_port *cpu_dp = dp->cpu_dp; 1508 u32 port_bitmap = BIT(cpu_dp->index); 1509 int other_port; 1510 bool isolated; 1511 1512 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1513 other_port = other_dp->index; 1514 other_p = &priv->ports[other_port]; 1515 1516 if (dp == other_dp) 1517 continue; 1518 1519 /* Add/remove this port to/from the port matrix of the other 1520 * ports in the same bridge. If the port is disabled, port 1521 * matrix is kept and not being setup until the port becomes 1522 * enabled. 1523 */ 1524 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1525 continue; 1526 1527 isolated = p->isolated && other_p->isolated; 1528 1529 if (join && !isolated) { 1530 other_p->pm |= PCR_MATRIX(BIT(port)); 1531 port_bitmap |= BIT(other_port); 1532 } else { 1533 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1534 } 1535 1536 if (other_p->enable) 1537 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1538 PCR_MATRIX_MASK, other_p->pm); 1539 } 1540 1541 /* Add/remove the all other ports to this port matrix. For !join 1542 * (leaving the bridge), only the CPU port will remain in the port matrix 1543 * of this port. 1544 */ 1545 p->pm = PCR_MATRIX(port_bitmap); 1546 if (priv->ports[port].enable) 1547 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1548 } 1549 1550 static int 1551 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1552 struct switchdev_brport_flags flags, 1553 struct netlink_ext_ack *extack) 1554 { 1555 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1556 BR_BCAST_FLOOD | BR_ISOLATED)) 1557 return -EINVAL; 1558 1559 return 0; 1560 } 1561 1562 static int 1563 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1564 struct switchdev_brport_flags flags, 1565 struct netlink_ext_ack *extack) 1566 { 1567 struct mt7530_priv *priv = ds->priv; 1568 1569 if (flags.mask & BR_LEARNING) 1570 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1571 flags.val & BR_LEARNING ? 0 : SA_DIS); 1572 1573 if (flags.mask & BR_FLOOD) 1574 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1575 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1576 1577 if (flags.mask & BR_MCAST_FLOOD) 1578 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1579 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1580 1581 if (flags.mask & BR_BCAST_FLOOD) 1582 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1583 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1584 1585 if (flags.mask & BR_ISOLATED) { 1586 struct dsa_port *dp = dsa_to_port(ds, port); 1587 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1588 1589 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1590 1591 mutex_lock(&priv->reg_mutex); 1592 mt7530_update_port_member(priv, port, bridge_dev, true); 1593 mutex_unlock(&priv->reg_mutex); 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int 1600 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1601 struct dsa_bridge bridge, bool *tx_fwd_offload, 1602 struct netlink_ext_ack *extack) 1603 { 1604 struct mt7530_priv *priv = ds->priv; 1605 1606 mutex_lock(&priv->reg_mutex); 1607 1608 mt7530_update_port_member(priv, port, bridge.dev, true); 1609 1610 /* Set to fallback mode for independent VLAN learning */ 1611 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1612 MT7530_PORT_FALLBACK_MODE); 1613 1614 mutex_unlock(&priv->reg_mutex); 1615 1616 return 0; 1617 } 1618 1619 static void 1620 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1621 { 1622 struct mt7530_priv *priv = ds->priv; 1623 bool all_user_ports_removed = true; 1624 int i; 1625 1626 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1627 * bridge. Don't set standalone ports to fallback mode. 1628 */ 1629 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1630 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1631 MT7530_PORT_FALLBACK_MODE); 1632 1633 mt7530_rmw(priv, MT7530_PVC_P(port), 1634 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1635 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1636 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1637 MT7530_VLAN_ACC_ALL); 1638 1639 /* Set PVID to 0 */ 1640 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1641 G0_PORT_VID_DEF); 1642 1643 for (i = 0; i < priv->ds->num_ports; i++) { 1644 if (dsa_is_user_port(ds, i) && 1645 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1646 all_user_ports_removed = false; 1647 break; 1648 } 1649 } 1650 1651 /* CPU port also does the same thing until all user ports belonging to 1652 * the CPU port get out of VLAN filtering mode. 1653 */ 1654 if (all_user_ports_removed) { 1655 struct dsa_port *dp = dsa_to_port(ds, port); 1656 struct dsa_port *cpu_dp = dp->cpu_dp; 1657 1658 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1659 PCR_MATRIX(dsa_user_ports(priv->ds))); 1660 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1661 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1662 } 1663 } 1664 1665 static void 1666 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1667 { 1668 struct mt7530_priv *priv = ds->priv; 1669 1670 /* Trapped into security mode allows packet forwarding through VLAN 1671 * table lookup. 1672 */ 1673 if (dsa_is_user_port(ds, port)) { 1674 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1675 MT7530_PORT_SECURITY_MODE); 1676 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1677 G0_PORT_VID(priv->ports[port].pvid)); 1678 1679 /* Only accept tagged frames if PVID is not set */ 1680 if (!priv->ports[port].pvid) 1681 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1682 MT7530_VLAN_ACC_TAGGED); 1683 1684 /* Set the port as a user port which is to be able to recognize 1685 * VID from incoming packets before fetching entry within the 1686 * VLAN table. 1687 */ 1688 mt7530_rmw(priv, MT7530_PVC_P(port), 1689 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1690 VLAN_ATTR(MT7530_VLAN_USER) | 1691 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1692 } else { 1693 /* Also set CPU ports to the "user" VLAN port attribute, to 1694 * allow VLAN classification, but keep the EG_TAG attribute as 1695 * "consistent" (i.o.w. don't change its value) for packets 1696 * received by the switch from the CPU, so that tagged packets 1697 * are forwarded to user ports as tagged, and untagged as 1698 * untagged. 1699 */ 1700 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1701 VLAN_ATTR(MT7530_VLAN_USER)); 1702 } 1703 } 1704 1705 static void 1706 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1707 struct dsa_bridge bridge) 1708 { 1709 struct mt7530_priv *priv = ds->priv; 1710 1711 mutex_lock(&priv->reg_mutex); 1712 1713 mt7530_update_port_member(priv, port, bridge.dev, false); 1714 1715 /* When a port is removed from the bridge, the port would be set up 1716 * back to the default as is at initial boot which is a VLAN-unaware 1717 * port. 1718 */ 1719 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1720 MT7530_PORT_MATRIX_MODE); 1721 1722 mutex_unlock(&priv->reg_mutex); 1723 } 1724 1725 static int 1726 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1727 const unsigned char *addr, u16 vid, 1728 struct dsa_db db) 1729 { 1730 struct mt7530_priv *priv = ds->priv; 1731 int ret; 1732 u8 port_mask = BIT(port); 1733 1734 mutex_lock(&priv->reg_mutex); 1735 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1736 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1737 mutex_unlock(&priv->reg_mutex); 1738 1739 return ret; 1740 } 1741 1742 static int 1743 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1744 const unsigned char *addr, u16 vid, 1745 struct dsa_db db) 1746 { 1747 struct mt7530_priv *priv = ds->priv; 1748 int ret; 1749 u8 port_mask = BIT(port); 1750 1751 mutex_lock(&priv->reg_mutex); 1752 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1753 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1754 mutex_unlock(&priv->reg_mutex); 1755 1756 return ret; 1757 } 1758 1759 static int 1760 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1761 dsa_fdb_dump_cb_t *cb, void *data) 1762 { 1763 struct mt7530_priv *priv = ds->priv; 1764 struct mt7530_fdb _fdb = { 0 }; 1765 int cnt = MT7530_NUM_FDB_RECORDS; 1766 int ret = 0; 1767 u32 rsp = 0; 1768 1769 mutex_lock(&priv->reg_mutex); 1770 1771 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1772 if (ret < 0) 1773 goto err; 1774 1775 do { 1776 if (rsp & ATC_SRCH_HIT) { 1777 mt7530_fdb_read(priv, &_fdb); 1778 if (_fdb.port_mask & BIT(port)) { 1779 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1780 data); 1781 if (ret < 0) 1782 break; 1783 } 1784 } 1785 } while (--cnt && 1786 !(rsp & ATC_SRCH_END) && 1787 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1788 err: 1789 mutex_unlock(&priv->reg_mutex); 1790 1791 return 0; 1792 } 1793 1794 static int 1795 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1796 const struct switchdev_obj_port_mdb *mdb, 1797 struct dsa_db db) 1798 { 1799 struct mt7530_priv *priv = ds->priv; 1800 const u8 *addr = mdb->addr; 1801 u16 vid = mdb->vid; 1802 u8 port_mask = 0; 1803 int ret; 1804 1805 mutex_lock(&priv->reg_mutex); 1806 1807 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1808 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1809 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1810 & PORT_MAP_MASK; 1811 1812 port_mask |= BIT(port); 1813 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1814 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1815 1816 mutex_unlock(&priv->reg_mutex); 1817 1818 return ret; 1819 } 1820 1821 static int 1822 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1823 const struct switchdev_obj_port_mdb *mdb, 1824 struct dsa_db db) 1825 { 1826 struct mt7530_priv *priv = ds->priv; 1827 const u8 *addr = mdb->addr; 1828 u16 vid = mdb->vid; 1829 u8 port_mask = 0; 1830 int ret; 1831 1832 mutex_lock(&priv->reg_mutex); 1833 1834 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1835 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1836 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1837 & PORT_MAP_MASK; 1838 1839 port_mask &= ~BIT(port); 1840 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1841 port_mask ? STATIC_ENT : STATIC_EMP); 1842 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1843 1844 mutex_unlock(&priv->reg_mutex); 1845 1846 return ret; 1847 } 1848 1849 static int 1850 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1851 { 1852 struct mt7530_dummy_poll p; 1853 u32 val; 1854 int ret; 1855 1856 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1857 mt7530_write(priv, MT7530_VTCR, val); 1858 1859 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1860 ret = readx_poll_timeout(_mt7530_read, &p, val, 1861 !(val & VTCR_BUSY), 20, 20000); 1862 if (ret < 0) { 1863 dev_err(priv->dev, "poll timeout\n"); 1864 return ret; 1865 } 1866 1867 val = mt7530_read(priv, MT7530_VTCR); 1868 if (val & VTCR_INVALID) { 1869 dev_err(priv->dev, "read VTCR invalid\n"); 1870 return -EINVAL; 1871 } 1872 1873 return 0; 1874 } 1875 1876 static int 1877 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1878 struct netlink_ext_ack *extack) 1879 { 1880 struct dsa_port *dp = dsa_to_port(ds, port); 1881 struct dsa_port *cpu_dp = dp->cpu_dp; 1882 1883 if (vlan_filtering) { 1884 /* The port is being kept as VLAN-unaware port when bridge is 1885 * set up with vlan_filtering not being set, Otherwise, the 1886 * port and the corresponding CPU port is required the setup 1887 * for becoming a VLAN-aware port. 1888 */ 1889 mt7530_port_set_vlan_aware(ds, port); 1890 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1891 } else { 1892 mt7530_port_set_vlan_unaware(ds, port); 1893 } 1894 1895 return 0; 1896 } 1897 1898 static void 1899 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1900 struct mt7530_hw_vlan_entry *entry) 1901 { 1902 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1903 u8 new_members; 1904 u32 val; 1905 1906 new_members = entry->old_members | BIT(entry->port); 1907 1908 /* Validate the entry with independent learning, create egress tag per 1909 * VLAN and joining the port as one of the port members. 1910 */ 1911 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1912 VLAN_VALID; 1913 mt7530_write(priv, MT7530_VAWD1, val); 1914 1915 /* Decide whether adding tag or not for those outgoing packets from the 1916 * port inside the VLAN. 1917 * CPU port is always taken as a tagged port for serving more than one 1918 * VLANs across and also being applied with egress type stack mode for 1919 * that VLAN tags would be appended after hardware special tag used as 1920 * DSA tag. 1921 */ 1922 if (dsa_port_is_cpu(dp)) 1923 val = MT7530_VLAN_EGRESS_STACK; 1924 else if (entry->untagged) 1925 val = MT7530_VLAN_EGRESS_UNTAG; 1926 else 1927 val = MT7530_VLAN_EGRESS_TAG; 1928 mt7530_rmw(priv, MT7530_VAWD2, 1929 ETAG_CTRL_P_MASK(entry->port), 1930 ETAG_CTRL_P(entry->port, val)); 1931 } 1932 1933 static void 1934 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1935 struct mt7530_hw_vlan_entry *entry) 1936 { 1937 u8 new_members; 1938 u32 val; 1939 1940 new_members = entry->old_members & ~BIT(entry->port); 1941 1942 val = mt7530_read(priv, MT7530_VAWD1); 1943 if (!(val & VLAN_VALID)) { 1944 dev_err(priv->dev, 1945 "Cannot be deleted due to invalid entry\n"); 1946 return; 1947 } 1948 1949 if (new_members) { 1950 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1951 VLAN_VALID; 1952 mt7530_write(priv, MT7530_VAWD1, val); 1953 } else { 1954 mt7530_write(priv, MT7530_VAWD1, 0); 1955 mt7530_write(priv, MT7530_VAWD2, 0); 1956 } 1957 } 1958 1959 static void 1960 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1961 struct mt7530_hw_vlan_entry *entry, 1962 mt7530_vlan_op vlan_op) 1963 { 1964 u32 val; 1965 1966 /* Fetch entry */ 1967 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1968 1969 val = mt7530_read(priv, MT7530_VAWD1); 1970 1971 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1972 1973 /* Manipulate entry */ 1974 vlan_op(priv, entry); 1975 1976 /* Flush result to hardware */ 1977 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1978 } 1979 1980 static int 1981 mt7530_setup_vlan0(struct mt7530_priv *priv) 1982 { 1983 u32 val; 1984 1985 /* Validate the entry with independent learning, keep the original 1986 * ingress tag attribute. 1987 */ 1988 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1989 VLAN_VALID; 1990 mt7530_write(priv, MT7530_VAWD1, val); 1991 1992 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1993 } 1994 1995 static int 1996 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1997 const struct switchdev_obj_port_vlan *vlan, 1998 struct netlink_ext_ack *extack) 1999 { 2000 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2001 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2002 struct mt7530_hw_vlan_entry new_entry; 2003 struct mt7530_priv *priv = ds->priv; 2004 2005 mutex_lock(&priv->reg_mutex); 2006 2007 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 2008 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 2009 2010 if (pvid) { 2011 priv->ports[port].pvid = vlan->vid; 2012 2013 /* Accept all frames if PVID is set */ 2014 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2015 MT7530_VLAN_ACC_ALL); 2016 2017 /* Only configure PVID if VLAN filtering is enabled */ 2018 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2019 mt7530_rmw(priv, MT7530_PPBV1_P(port), 2020 G0_PORT_VID_MASK, 2021 G0_PORT_VID(vlan->vid)); 2022 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 2023 /* This VLAN is overwritten without PVID, so unset it */ 2024 priv->ports[port].pvid = G0_PORT_VID_DEF; 2025 2026 /* Only accept tagged frames if the port is VLAN-aware */ 2027 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2028 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2029 MT7530_VLAN_ACC_TAGGED); 2030 2031 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2032 G0_PORT_VID_DEF); 2033 } 2034 2035 mutex_unlock(&priv->reg_mutex); 2036 2037 return 0; 2038 } 2039 2040 static int 2041 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 2042 const struct switchdev_obj_port_vlan *vlan) 2043 { 2044 struct mt7530_hw_vlan_entry target_entry; 2045 struct mt7530_priv *priv = ds->priv; 2046 2047 mutex_lock(&priv->reg_mutex); 2048 2049 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 2050 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 2051 mt7530_hw_vlan_del); 2052 2053 /* PVID is being restored to the default whenever the PVID port 2054 * is being removed from the VLAN. 2055 */ 2056 if (priv->ports[port].pvid == vlan->vid) { 2057 priv->ports[port].pvid = G0_PORT_VID_DEF; 2058 2059 /* Only accept tagged frames if the port is VLAN-aware */ 2060 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 2061 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 2062 MT7530_VLAN_ACC_TAGGED); 2063 2064 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 2065 G0_PORT_VID_DEF); 2066 } 2067 2068 2069 mutex_unlock(&priv->reg_mutex); 2070 2071 return 0; 2072 } 2073 2074 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 2075 struct dsa_mall_mirror_tc_entry *mirror, 2076 bool ingress, struct netlink_ext_ack *extack) 2077 { 2078 struct mt7530_priv *priv = ds->priv; 2079 int monitor_port; 2080 u32 val; 2081 2082 /* Check for existent entry */ 2083 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 2084 return -EEXIST; 2085 2086 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2087 2088 /* MT7530 only supports one monitor port */ 2089 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 2090 if (val & MT753X_MIRROR_EN(priv->id) && 2091 monitor_port != mirror->to_local_port) 2092 return -EEXIST; 2093 2094 val |= MT753X_MIRROR_EN(priv->id); 2095 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 2096 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 2097 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2098 2099 val = mt7530_read(priv, MT7530_PCR_P(port)); 2100 if (ingress) { 2101 val |= PORT_RX_MIR; 2102 priv->mirror_rx |= BIT(port); 2103 } else { 2104 val |= PORT_TX_MIR; 2105 priv->mirror_tx |= BIT(port); 2106 } 2107 mt7530_write(priv, MT7530_PCR_P(port), val); 2108 2109 return 0; 2110 } 2111 2112 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 2113 struct dsa_mall_mirror_tc_entry *mirror) 2114 { 2115 struct mt7530_priv *priv = ds->priv; 2116 u32 val; 2117 2118 val = mt7530_read(priv, MT7530_PCR_P(port)); 2119 if (mirror->ingress) { 2120 val &= ~PORT_RX_MIR; 2121 priv->mirror_rx &= ~BIT(port); 2122 } else { 2123 val &= ~PORT_TX_MIR; 2124 priv->mirror_tx &= ~BIT(port); 2125 } 2126 mt7530_write(priv, MT7530_PCR_P(port), val); 2127 2128 if (!priv->mirror_rx && !priv->mirror_tx) { 2129 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 2130 val &= ~MT753X_MIRROR_EN(priv->id); 2131 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 2132 } 2133 } 2134 2135 static enum dsa_tag_protocol 2136 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 2137 enum dsa_tag_protocol mp) 2138 { 2139 return DSA_TAG_PROTO_MTK; 2140 } 2141 2142 #ifdef CONFIG_GPIOLIB 2143 static inline u32 2144 mt7530_gpio_to_bit(unsigned int offset) 2145 { 2146 /* Map GPIO offset to register bit 2147 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 2148 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 2149 * [10: 8] port 2 LED 0..2 as GPIO 6..8 2150 * [14:12] port 3 LED 0..2 as GPIO 9..11 2151 * [18:16] port 4 LED 0..2 as GPIO 12..14 2152 */ 2153 return BIT(offset + offset / 3); 2154 } 2155 2156 static int 2157 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 2158 { 2159 struct mt7530_priv *priv = gpiochip_get_data(gc); 2160 u32 bit = mt7530_gpio_to_bit(offset); 2161 2162 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 2163 } 2164 2165 static int 2166 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 2167 { 2168 struct mt7530_priv *priv = gpiochip_get_data(gc); 2169 u32 bit = mt7530_gpio_to_bit(offset); 2170 2171 if (value) 2172 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2173 else 2174 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2175 2176 return 0; 2177 } 2178 2179 static int 2180 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 2181 { 2182 struct mt7530_priv *priv = gpiochip_get_data(gc); 2183 u32 bit = mt7530_gpio_to_bit(offset); 2184 2185 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 2186 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 2187 } 2188 2189 static int 2190 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 2191 { 2192 struct mt7530_priv *priv = gpiochip_get_data(gc); 2193 u32 bit = mt7530_gpio_to_bit(offset); 2194 2195 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2196 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2197 2198 return 0; 2199 } 2200 2201 static int 2202 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2203 { 2204 struct mt7530_priv *priv = gpiochip_get_data(gc); 2205 u32 bit = mt7530_gpio_to_bit(offset); 2206 2207 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2208 2209 if (value) 2210 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2211 else 2212 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2213 2214 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2215 2216 return 0; 2217 } 2218 2219 static int 2220 mt7530_setup_gpio(struct mt7530_priv *priv) 2221 { 2222 struct device *dev = priv->dev; 2223 struct gpio_chip *gc; 2224 2225 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2226 if (!gc) 2227 return -ENOMEM; 2228 2229 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2230 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2231 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2232 2233 gc->label = "mt7530"; 2234 gc->parent = dev; 2235 gc->owner = THIS_MODULE; 2236 gc->get_direction = mt7530_gpio_get_direction; 2237 gc->direction_input = mt7530_gpio_direction_input; 2238 gc->direction_output = mt7530_gpio_direction_output; 2239 gc->get = mt7530_gpio_get; 2240 gc->set = mt7530_gpio_set; 2241 gc->base = -1; 2242 gc->ngpio = 15; 2243 gc->can_sleep = true; 2244 2245 return devm_gpiochip_add_data(dev, gc, priv); 2246 } 2247 #endif /* CONFIG_GPIOLIB */ 2248 2249 static void 2250 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2251 { 2252 struct dsa_switch *ds = priv->ds; 2253 int p; 2254 2255 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2256 if (BIT(p) & ds->phys_mii_mask) { 2257 unsigned int irq; 2258 2259 irq = irq_create_mapping(priv->irq_domain, p); 2260 ds->user_mii_bus->irq[p] = irq; 2261 } 2262 } 2263 } 2264 2265 static const struct regmap_irq mt7530_irqs[] = { 2266 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2267 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2268 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2269 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2270 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2271 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2272 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2273 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2274 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2275 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2276 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2277 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2278 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2279 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2280 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2281 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2282 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2283 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2284 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2285 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2286 }; 2287 2288 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2289 .name = KBUILD_MODNAME, 2290 .status_base = MT7530_SYS_INT_STS, 2291 .unmask_base = MT7530_SYS_INT_EN, 2292 .ack_base = MT7530_SYS_INT_STS, 2293 .init_ack_masked = true, 2294 .irqs = mt7530_irqs, 2295 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2296 .num_regs = 1, 2297 }; 2298 2299 static int 2300 mt7530_setup_irq(struct mt7530_priv *priv) 2301 { 2302 struct regmap_irq_chip_data *irq_data; 2303 struct device *dev = priv->dev; 2304 struct device_node *np = dev->of_node; 2305 int irq, ret; 2306 2307 if (!of_property_read_bool(np, "interrupt-controller")) { 2308 dev_info(dev, "no interrupt support\n"); 2309 return 0; 2310 } 2311 2312 irq = of_irq_get(np, 0); 2313 if (irq <= 0) { 2314 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2315 return irq ? : -EINVAL; 2316 } 2317 2318 /* This register must be set for MT7530 to properly fire interrupts */ 2319 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2320 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2321 2322 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2323 priv->regmap, irq, 2324 IRQF_ONESHOT, 2325 0, &mt7530_regmap_irq_chip, 2326 &irq_data); 2327 if (ret) 2328 return ret; 2329 2330 priv->irq_domain = regmap_irq_get_domain(irq_data); 2331 2332 return 0; 2333 } 2334 2335 static void 2336 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2337 { 2338 int p; 2339 2340 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2341 if (BIT(p) & priv->ds->phys_mii_mask) { 2342 unsigned int irq; 2343 2344 irq = irq_find_mapping(priv->irq_domain, p); 2345 irq_dispose_mapping(irq); 2346 } 2347 } 2348 } 2349 2350 static int 2351 mt7530_setup_mdio(struct mt7530_priv *priv) 2352 { 2353 struct device_node *mnp, *np = priv->dev->of_node; 2354 struct dsa_switch *ds = priv->ds; 2355 struct device *dev = priv->dev; 2356 struct mii_bus *bus; 2357 static int idx; 2358 int ret = 0; 2359 2360 mnp = of_get_child_by_name(np, "mdio"); 2361 2362 if (mnp && !of_device_is_available(mnp)) 2363 goto out; 2364 2365 bus = devm_mdiobus_alloc(dev); 2366 if (!bus) { 2367 ret = -ENOMEM; 2368 goto out; 2369 } 2370 2371 if (!mnp) 2372 ds->user_mii_bus = bus; 2373 2374 bus->priv = priv; 2375 bus->name = KBUILD_MODNAME "-mii"; 2376 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2377 bus->read = mt753x_phy_read_c22; 2378 bus->write = mt753x_phy_write_c22; 2379 bus->read_c45 = mt753x_phy_read_c45; 2380 bus->write_c45 = mt753x_phy_write_c45; 2381 bus->parent = dev; 2382 bus->phy_mask = ~ds->phys_mii_mask; 2383 2384 if (priv->irq_domain && !mnp) 2385 mt7530_setup_mdio_irq(priv); 2386 2387 ret = devm_of_mdiobus_register(dev, bus, mnp); 2388 if (ret) { 2389 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2390 if (priv->irq_domain && !mnp) 2391 mt7530_free_mdio_irq(priv); 2392 } 2393 2394 out: 2395 of_node_put(mnp); 2396 return ret; 2397 } 2398 2399 static int 2400 mt7530_setup(struct dsa_switch *ds) 2401 { 2402 struct mt7530_priv *priv = ds->priv; 2403 struct device_node *dn = NULL; 2404 struct device_node *phy_node; 2405 struct device_node *mac_np; 2406 struct mt7530_dummy_poll p; 2407 phy_interface_t interface; 2408 struct dsa_port *cpu_dp; 2409 u32 id, val; 2410 int ret, i; 2411 2412 /* The parent node of conduit netdev which holds the common system 2413 * controller also is the container for two GMACs nodes representing 2414 * as two netdev instances. 2415 */ 2416 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2417 dn = cpu_dp->conduit->dev.of_node->parent; 2418 /* It doesn't matter which CPU port is found first, 2419 * their conduits should share the same parent OF node 2420 */ 2421 break; 2422 } 2423 2424 if (!dn) { 2425 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2426 return -EINVAL; 2427 } 2428 2429 ds->assisted_learning_on_cpu_port = true; 2430 ds->mtu_enforcement_ingress = true; 2431 2432 if (priv->id == ID_MT7530) { 2433 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2434 ret = regulator_enable(priv->core_pwr); 2435 if (ret < 0) { 2436 dev_err(priv->dev, 2437 "Failed to enable core power: %d\n", ret); 2438 return ret; 2439 } 2440 2441 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2442 ret = regulator_enable(priv->io_pwr); 2443 if (ret < 0) { 2444 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2445 ret); 2446 return ret; 2447 } 2448 } 2449 2450 /* Reset whole chip through gpio pin or memory-mapped registers for 2451 * different type of hardware 2452 */ 2453 if (priv->mcm) { 2454 reset_control_assert(priv->rstc); 2455 usleep_range(5000, 5100); 2456 reset_control_deassert(priv->rstc); 2457 } else { 2458 gpiod_set_value_cansleep(priv->reset, 0); 2459 usleep_range(5000, 5100); 2460 gpiod_set_value_cansleep(priv->reset, 1); 2461 } 2462 2463 /* Waiting for MT7530 got to stable */ 2464 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2465 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2466 20, 1000000); 2467 if (ret < 0) { 2468 dev_err(priv->dev, "reset timeout\n"); 2469 return ret; 2470 } 2471 2472 id = mt7530_read(priv, MT7530_CREV); 2473 id >>= CHIP_NAME_SHIFT; 2474 if (id != MT7530_ID) { 2475 dev_err(priv->dev, "chip %x can't be supported\n", id); 2476 return -ENODEV; 2477 } 2478 2479 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2480 dev_err(priv->dev, 2481 "MT7530 with a 20MHz XTAL is not supported!\n"); 2482 return -EINVAL; 2483 } 2484 2485 /* Reset the switch through internal reset */ 2486 mt7530_write(priv, MT7530_SYS_CTRL, 2487 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2488 SYS_CTRL_REG_RST); 2489 2490 /* Lower Tx driving for TRGMII path */ 2491 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2492 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2493 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2494 2495 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2496 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2497 RD_TAP_MASK, RD_TAP(16)); 2498 2499 /* Allow modifying the trap and directly access PHY registers via the 2500 * MDIO bus the switch is on. 2501 */ 2502 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2503 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2504 2505 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2506 mt7530_pll_setup(priv); 2507 2508 mt753x_trap_frames(priv); 2509 2510 /* Enable and reset MIB counters */ 2511 mt7530_mib_reset(ds); 2512 2513 for (i = 0; i < priv->ds->num_ports; i++) { 2514 /* Clear link settings and enable force mode to force link down 2515 * on all ports until they're enabled later. 2516 */ 2517 mt7530_rmw(priv, MT753X_PMCR_P(i), 2518 PMCR_LINK_SETTINGS_MASK | 2519 MT753X_FORCE_MODE(priv->id), 2520 MT753X_FORCE_MODE(priv->id)); 2521 2522 /* Disable forwarding by default on all ports */ 2523 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2524 PCR_MATRIX_CLR); 2525 2526 /* Disable learning by default on all ports */ 2527 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2528 2529 if (dsa_is_cpu_port(ds, i)) { 2530 mt753x_cpu_port_enable(ds, i); 2531 } else { 2532 mt7530_port_disable(ds, i); 2533 2534 /* Set default PVID to 0 on all user ports */ 2535 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2536 G0_PORT_VID_DEF); 2537 } 2538 /* Enable consistent egress tag */ 2539 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2540 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2541 } 2542 2543 /* Allow mirroring frames received on the local port (monitor port). */ 2544 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2545 2546 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2547 ret = mt7530_setup_vlan0(priv); 2548 if (ret) 2549 return ret; 2550 2551 /* Check for PHY muxing on port 5 */ 2552 if (dsa_is_unused_port(ds, 5)) { 2553 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2554 * Set priv->p5_mode to the appropriate value if PHY muxing is 2555 * detected. 2556 */ 2557 for_each_child_of_node(dn, mac_np) { 2558 if (!of_device_is_compatible(mac_np, 2559 "mediatek,eth-mac")) 2560 continue; 2561 2562 ret = of_property_read_u32(mac_np, "reg", &id); 2563 if (ret < 0 || id != 1) 2564 continue; 2565 2566 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2567 if (!phy_node) 2568 continue; 2569 2570 if (phy_node->parent == priv->dev->of_node->parent || 2571 phy_node->parent->parent == priv->dev->of_node) { 2572 ret = of_get_phy_mode(mac_np, &interface); 2573 if (ret && ret != -ENODEV) { 2574 of_node_put(mac_np); 2575 of_node_put(phy_node); 2576 return ret; 2577 } 2578 id = of_mdio_parse_addr(ds->dev, phy_node); 2579 if (id == 0) 2580 priv->p5_mode = MUX_PHY_P0; 2581 if (id == 4) 2582 priv->p5_mode = MUX_PHY_P4; 2583 } 2584 of_node_put(mac_np); 2585 of_node_put(phy_node); 2586 break; 2587 } 2588 2589 if (priv->p5_mode == MUX_PHY_P0 || 2590 priv->p5_mode == MUX_PHY_P4) { 2591 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2592 mt7530_setup_port5(ds, interface); 2593 } 2594 } 2595 2596 #ifdef CONFIG_GPIOLIB 2597 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2598 ret = mt7530_setup_gpio(priv); 2599 if (ret) 2600 return ret; 2601 } 2602 #endif /* CONFIG_GPIOLIB */ 2603 2604 /* Flush the FDB table */ 2605 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2606 if (ret < 0) 2607 return ret; 2608 2609 return 0; 2610 } 2611 2612 static int 2613 mt7531_setup_common(struct dsa_switch *ds) 2614 { 2615 struct mt7530_priv *priv = ds->priv; 2616 int ret, i; 2617 2618 ds->assisted_learning_on_cpu_port = true; 2619 ds->mtu_enforcement_ingress = true; 2620 2621 mt753x_trap_frames(priv); 2622 2623 /* Enable and reset MIB counters */ 2624 mt7530_mib_reset(ds); 2625 2626 /* Disable flooding on all ports */ 2627 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2628 UNU_FFP_MASK); 2629 2630 for (i = 0; i < priv->ds->num_ports; i++) { 2631 /* Clear link settings and enable force mode to force link down 2632 * on all ports until they're enabled later. 2633 */ 2634 mt7530_rmw(priv, MT753X_PMCR_P(i), 2635 PMCR_LINK_SETTINGS_MASK | 2636 MT753X_FORCE_MODE(priv->id), 2637 MT753X_FORCE_MODE(priv->id)); 2638 2639 /* Disable forwarding by default on all ports */ 2640 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2641 PCR_MATRIX_CLR); 2642 2643 /* Disable learning by default on all ports */ 2644 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2645 2646 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2647 2648 if (dsa_is_cpu_port(ds, i)) { 2649 mt753x_cpu_port_enable(ds, i); 2650 } else { 2651 mt7530_port_disable(ds, i); 2652 2653 /* Set default PVID to 0 on all user ports */ 2654 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2655 G0_PORT_VID_DEF); 2656 } 2657 2658 /* Enable consistent egress tag */ 2659 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2660 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2661 } 2662 2663 /* Allow mirroring frames received on the local port (monitor port). */ 2664 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2665 2666 /* Enable Special Tag for rx frames */ 2667 if (priv->id == ID_EN7581 || priv->id == ID_AN7583) 2668 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2669 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2670 2671 /* Flush the FDB table */ 2672 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2673 if (ret < 0) 2674 return ret; 2675 2676 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2677 return mt7530_setup_vlan0(priv); 2678 } 2679 2680 static int 2681 mt7531_setup(struct dsa_switch *ds) 2682 { 2683 struct mt7530_priv *priv = ds->priv; 2684 struct mt7530_dummy_poll p; 2685 u32 val, id; 2686 int ret, i; 2687 2688 /* Reset whole chip through gpio pin or memory-mapped registers for 2689 * different type of hardware 2690 */ 2691 if (priv->mcm) { 2692 reset_control_assert(priv->rstc); 2693 usleep_range(5000, 5100); 2694 reset_control_deassert(priv->rstc); 2695 } else { 2696 gpiod_set_value_cansleep(priv->reset, 0); 2697 usleep_range(5000, 5100); 2698 gpiod_set_value_cansleep(priv->reset, 1); 2699 } 2700 2701 /* Waiting for MT7530 got to stable */ 2702 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2703 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2704 20, 1000000); 2705 if (ret < 0) { 2706 dev_err(priv->dev, "reset timeout\n"); 2707 return ret; 2708 } 2709 2710 id = mt7530_read(priv, MT7531_CREV); 2711 id >>= CHIP_NAME_SHIFT; 2712 2713 if (id != MT7531_ID) { 2714 dev_err(priv->dev, "chip %x can't be supported\n", id); 2715 return -ENODEV; 2716 } 2717 2718 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2719 * MT7531BE has got only one SGMII unit which is for port 6. 2720 */ 2721 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2722 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2723 2724 /* Force link down on all ports before internal reset */ 2725 for (i = 0; i < priv->ds->num_ports; i++) 2726 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2727 2728 /* Reset the switch through internal reset */ 2729 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2730 2731 if (!priv->p5_sgmii) { 2732 mt7531_pll_setup(priv); 2733 } else { 2734 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2735 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2736 * to expose the MDIO bus of the switch. 2737 */ 2738 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2739 MT7531_EXT_P_MDC_11); 2740 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2741 MT7531_EXT_P_MDIO_12); 2742 } 2743 2744 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2745 MT7531_GPIO0_INTERRUPT); 2746 2747 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2748 * phy_device has not yet been created provided for 2749 * phy_[read,write]_mmd_indirect is called, we provide our own 2750 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2751 */ 2752 val = mt7531_ind_c45_phy_read(priv, 2753 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2754 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2755 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2756 val &= ~MT7531_PHY_PLL_OFF; 2757 mt7531_ind_c45_phy_write(priv, 2758 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2759 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2760 2761 /* Disable EEE advertisement on the switch PHYs. */ 2762 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2763 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2764 i++) { 2765 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2766 0); 2767 } 2768 2769 ret = mt7531_setup_common(ds); 2770 if (ret) 2771 return ret; 2772 2773 return 0; 2774 } 2775 2776 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2777 struct phylink_config *config) 2778 { 2779 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2780 2781 switch (port) { 2782 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2783 case 0 ... 4: 2784 __set_bit(PHY_INTERFACE_MODE_GMII, 2785 config->supported_interfaces); 2786 break; 2787 2788 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2789 case 5: 2790 phy_interface_set_rgmii(config->supported_interfaces); 2791 __set_bit(PHY_INTERFACE_MODE_MII, 2792 config->supported_interfaces); 2793 __set_bit(PHY_INTERFACE_MODE_GMII, 2794 config->supported_interfaces); 2795 break; 2796 2797 /* Port 6 supports rgmii and trgmii. */ 2798 case 6: 2799 __set_bit(PHY_INTERFACE_MODE_RGMII, 2800 config->supported_interfaces); 2801 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2802 config->supported_interfaces); 2803 break; 2804 } 2805 } 2806 2807 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2808 struct phylink_config *config) 2809 { 2810 struct mt7530_priv *priv = ds->priv; 2811 2812 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2813 2814 switch (port) { 2815 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2816 case 0 ... 4: 2817 __set_bit(PHY_INTERFACE_MODE_GMII, 2818 config->supported_interfaces); 2819 break; 2820 2821 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2822 * MT7531AE. 2823 */ 2824 case 5: 2825 if (!priv->p5_sgmii) { 2826 phy_interface_set_rgmii(config->supported_interfaces); 2827 break; 2828 } 2829 fallthrough; 2830 2831 /* Port 6 supports sgmii/802.3z. */ 2832 case 6: 2833 __set_bit(PHY_INTERFACE_MODE_SGMII, 2834 config->supported_interfaces); 2835 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2836 config->supported_interfaces); 2837 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2838 config->supported_interfaces); 2839 2840 config->mac_capabilities |= MAC_2500FD; 2841 break; 2842 } 2843 } 2844 2845 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2846 struct phylink_config *config) 2847 { 2848 switch (port) { 2849 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2850 case 0 ... 3: 2851 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2852 config->supported_interfaces); 2853 2854 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2855 break; 2856 2857 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2858 case 6: 2859 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2860 config->supported_interfaces); 2861 2862 config->mac_capabilities |= MAC_10000FD; 2863 break; 2864 } 2865 } 2866 2867 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2868 struct phylink_config *config) 2869 { 2870 switch (port) { 2871 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2872 case 0 ... 4: 2873 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2874 config->supported_interfaces); 2875 2876 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2877 break; 2878 2879 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2880 case 6: 2881 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2882 config->supported_interfaces); 2883 2884 config->mac_capabilities |= MAC_10000FD; 2885 break; 2886 } 2887 } 2888 2889 static void 2890 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2891 phy_interface_t interface) 2892 { 2893 struct mt7530_priv *priv = ds->priv; 2894 2895 if (port == 5) 2896 mt7530_setup_port5(priv->ds, interface); 2897 else if (port == 6) 2898 mt7530_setup_port6(priv->ds, interface); 2899 } 2900 2901 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2902 phy_interface_t interface, 2903 struct phy_device *phydev) 2904 { 2905 u32 val; 2906 2907 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2908 val |= GP_CLK_EN; 2909 val &= ~GP_MODE_MASK; 2910 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2911 val &= ~CLK_SKEW_IN_MASK; 2912 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2913 val &= ~CLK_SKEW_OUT_MASK; 2914 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2915 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2916 2917 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2918 if (!phydev || phy_driver_is_genphy(phydev)) { 2919 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2920 switch (interface) { 2921 case PHY_INTERFACE_MODE_RGMII: 2922 val |= TXCLK_NO_REVERSE; 2923 val |= RXCLK_NO_DELAY; 2924 break; 2925 case PHY_INTERFACE_MODE_RGMII_RXID: 2926 val |= TXCLK_NO_REVERSE; 2927 break; 2928 case PHY_INTERFACE_MODE_RGMII_TXID: 2929 val |= RXCLK_NO_DELAY; 2930 break; 2931 case PHY_INTERFACE_MODE_RGMII_ID: 2932 break; 2933 default: 2934 break; 2935 } 2936 } 2937 2938 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2939 } 2940 2941 static void 2942 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2943 phy_interface_t interface) 2944 { 2945 struct mt7530_priv *priv = ds->priv; 2946 struct phy_device *phydev; 2947 struct dsa_port *dp; 2948 2949 if (phy_interface_mode_is_rgmii(interface)) { 2950 dp = dsa_to_port(ds, port); 2951 phydev = dp->user->phydev; 2952 mt7531_rgmii_setup(priv, interface, phydev); 2953 } 2954 } 2955 2956 static struct phylink_pcs * 2957 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2958 phy_interface_t interface) 2959 { 2960 struct dsa_port *dp = dsa_phylink_to_port(config); 2961 struct mt7530_priv *priv = dp->ds->priv; 2962 2963 switch (interface) { 2964 case PHY_INTERFACE_MODE_TRGMII: 2965 return &priv->pcs[dp->index].pcs; 2966 case PHY_INTERFACE_MODE_SGMII: 2967 case PHY_INTERFACE_MODE_1000BASEX: 2968 case PHY_INTERFACE_MODE_2500BASEX: 2969 return priv->ports[dp->index].sgmii_pcs; 2970 default: 2971 return NULL; 2972 } 2973 } 2974 2975 static void 2976 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2977 const struct phylink_link_state *state) 2978 { 2979 struct dsa_port *dp = dsa_phylink_to_port(config); 2980 struct dsa_switch *ds = dp->ds; 2981 struct mt7530_priv *priv; 2982 int port = dp->index; 2983 2984 priv = ds->priv; 2985 2986 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2987 priv->info->mac_port_config(ds, port, mode, state->interface); 2988 2989 /* Are we connected to external phy */ 2990 if (port == 5 && dsa_is_user_port(ds, 5)) 2991 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 2992 } 2993 2994 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 2995 unsigned int mode, 2996 phy_interface_t interface) 2997 { 2998 struct dsa_port *dp = dsa_phylink_to_port(config); 2999 struct mt7530_priv *priv = dp->ds->priv; 3000 3001 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 3002 } 3003 3004 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 3005 struct phy_device *phydev, 3006 unsigned int mode, 3007 phy_interface_t interface, 3008 int speed, int duplex, 3009 bool tx_pause, bool rx_pause) 3010 { 3011 struct dsa_port *dp = dsa_phylink_to_port(config); 3012 struct mt7530_priv *priv = dp->ds->priv; 3013 u32 mcr; 3014 3015 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 3016 3017 switch (speed) { 3018 case SPEED_1000: 3019 case SPEED_2500: 3020 case SPEED_10000: 3021 mcr |= PMCR_FORCE_SPEED_1000; 3022 break; 3023 case SPEED_100: 3024 mcr |= PMCR_FORCE_SPEED_100; 3025 break; 3026 } 3027 if (duplex == DUPLEX_FULL) { 3028 mcr |= PMCR_FORCE_FDX; 3029 if (tx_pause) 3030 mcr |= PMCR_FORCE_TX_FC_EN; 3031 if (rx_pause) 3032 mcr |= PMCR_FORCE_RX_FC_EN; 3033 } 3034 3035 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 3036 } 3037 3038 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 3039 { 3040 struct dsa_port *dp = dsa_phylink_to_port(config); 3041 struct mt7530_priv *priv = dp->ds->priv; 3042 3043 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 3044 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3045 } 3046 3047 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 3048 u32 timer, bool tx_clock_stop) 3049 { 3050 struct dsa_port *dp = dsa_phylink_to_port(config); 3051 struct mt7530_priv *priv = dp->ds->priv; 3052 u32 val; 3053 3054 /* If the timer is zero, then set LPI_MODE_EN, which allows the 3055 * system to enter LPI mode immediately rather than waiting for 3056 * the LPI threshold. 3057 */ 3058 if (!timer) 3059 val = LPI_MODE_EN; 3060 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 3061 val = FIELD_PREP(LPI_THRESH_MASK, timer); 3062 else 3063 val = LPI_THRESH_MASK; 3064 3065 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 3066 LPI_THRESH_MASK | LPI_MODE_EN, val); 3067 3068 mt7530_set(priv, MT753X_PMCR_P(dp->index), 3069 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 3070 3071 return 0; 3072 } 3073 3074 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 3075 struct phylink_config *config) 3076 { 3077 struct mt7530_priv *priv = ds->priv; 3078 u32 eeecr; 3079 3080 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 3081 3082 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 3083 3084 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 3085 /* tx_lpi_timer should be in microseconds. The time units for 3086 * LPI threshold are unspecified. 3087 */ 3088 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 3089 3090 priv->info->mac_port_get_caps(ds, port, config); 3091 } 3092 3093 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 3094 unsigned long *supported, 3095 const struct phylink_link_state *state) 3096 { 3097 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 3098 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 3099 phy_interface_mode_is_8023z(state->interface)) 3100 phylink_clear(supported, Autoneg); 3101 3102 return 0; 3103 } 3104 3105 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 3106 struct phylink_link_state *state) 3107 { 3108 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3109 int port = pcs_to_mt753x_pcs(pcs)->port; 3110 u32 pmsr; 3111 3112 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 3113 3114 state->link = (pmsr & PMSR_LINK); 3115 state->an_complete = state->link; 3116 state->duplex = !!(pmsr & PMSR_DPX); 3117 3118 switch (pmsr & PMSR_SPEED_MASK) { 3119 case PMSR_SPEED_10: 3120 state->speed = SPEED_10; 3121 break; 3122 case PMSR_SPEED_100: 3123 state->speed = SPEED_100; 3124 break; 3125 case PMSR_SPEED_1000: 3126 state->speed = SPEED_1000; 3127 break; 3128 default: 3129 state->speed = SPEED_UNKNOWN; 3130 break; 3131 } 3132 3133 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3134 if (pmsr & PMSR_RX_FC) 3135 state->pause |= MLO_PAUSE_RX; 3136 if (pmsr & PMSR_TX_FC) 3137 state->pause |= MLO_PAUSE_TX; 3138 } 3139 3140 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 3141 phy_interface_t interface, 3142 const unsigned long *advertising, 3143 bool permit_pause_to_mac) 3144 { 3145 return 0; 3146 } 3147 3148 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3149 { 3150 } 3151 3152 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3153 .pcs_validate = mt753x_pcs_validate, 3154 .pcs_get_state = mt7530_pcs_get_state, 3155 .pcs_config = mt753x_pcs_config, 3156 .pcs_an_restart = mt7530_pcs_an_restart, 3157 }; 3158 3159 static int 3160 mt753x_setup(struct dsa_switch *ds) 3161 { 3162 struct mt7530_priv *priv = ds->priv; 3163 int ret = priv->info->sw_setup(ds); 3164 int i; 3165 3166 if (ret) 3167 return ret; 3168 3169 ret = mt7530_setup_irq(priv); 3170 if (ret) 3171 return ret; 3172 3173 ret = mt7530_setup_mdio(priv); 3174 if (ret) 3175 return ret; 3176 3177 /* Initialise the PCS devices */ 3178 for (i = 0; i < priv->ds->num_ports; i++) { 3179 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3180 priv->pcs[i].priv = priv; 3181 priv->pcs[i].port = i; 3182 } 3183 3184 if (priv->create_sgmii) 3185 ret = priv->create_sgmii(priv); 3186 3187 if (ret && priv->irq_domain) 3188 mt7530_free_mdio_irq(priv); 3189 3190 if (!ret && priv->bus) { 3191 mt7530_stats_refresh(priv); 3192 schedule_delayed_work(&priv->stats_work, 3193 MT7530_STATS_POLL_INTERVAL); 3194 } 3195 3196 return ret; 3197 } 3198 3199 static void 3200 mt753x_teardown(struct dsa_switch *ds) 3201 { 3202 struct mt7530_priv *priv = ds->priv; 3203 3204 if (priv->bus) 3205 cancel_delayed_work_sync(&priv->stats_work); 3206 } 3207 3208 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3209 struct ethtool_keee *e) 3210 { 3211 if (e->tx_lpi_timer > 0xFFF) 3212 return -EINVAL; 3213 3214 return 0; 3215 } 3216 3217 static void 3218 mt753x_conduit_state_change(struct dsa_switch *ds, 3219 const struct net_device *conduit, 3220 bool operational) 3221 { 3222 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3223 struct mt7530_priv *priv = ds->priv; 3224 int val = 0; 3225 u8 mask; 3226 3227 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3228 * forwarded to the numerically smallest CPU port whose conduit 3229 * interface is up. 3230 */ 3231 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3232 return; 3233 3234 mask = BIT(cpu_dp->index); 3235 3236 if (operational) 3237 priv->active_cpu_ports |= mask; 3238 else 3239 priv->active_cpu_ports &= ~mask; 3240 3241 if (priv->active_cpu_ports) { 3242 val = MT7530_CPU_EN | 3243 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3244 } 3245 3246 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3247 } 3248 3249 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3250 struct tc_tbf_qopt_offload *qopt) 3251 { 3252 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3253 struct mt7530_priv *priv = ds->priv; 3254 u32 rate = 0; 3255 3256 switch (qopt->command) { 3257 case TC_TBF_REPLACE: 3258 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3259 fallthrough; 3260 case TC_TBF_DESTROY: { 3261 u32 val, tick; 3262 3263 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3264 EGR_BC_CRC_IPG_PREAMBLE); 3265 3266 /* if rate is greater than 10Mbps tick is 1/32 ms, 3267 * 1ms otherwise 3268 */ 3269 tick = rate > 10000 ? 2 : 7; 3270 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3271 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3272 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3273 ERLCR_TBF_MODE_MASK | 3274 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3275 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3276 break; 3277 } 3278 default: 3279 return -EOPNOTSUPP; 3280 } 3281 3282 return 0; 3283 } 3284 3285 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3286 enum tc_setup_type type, void *type_data) 3287 { 3288 switch (type) { 3289 case TC_SETUP_QDISC_TBF: 3290 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3291 default: 3292 return -EOPNOTSUPP; 3293 } 3294 } 3295 3296 static int mt7988_setup(struct dsa_switch *ds) 3297 { 3298 struct mt7530_priv *priv = ds->priv; 3299 3300 /* Reset the switch */ 3301 reset_control_assert(priv->rstc); 3302 usleep_range(20, 50); 3303 reset_control_deassert(priv->rstc); 3304 usleep_range(20, 50); 3305 3306 /* AN7583 require additional tweak to CONN_CFG */ 3307 if (priv->id == ID_AN7583) 3308 mt7530_rmw(priv, AN7583_GEPHY_CONN_CFG, 3309 AN7583_CSR_DPHY_CKIN_SEL | 3310 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3311 AN7583_CSR_ETHER_AFE_PWD, 3312 AN7583_CSR_DPHY_CKIN_SEL | 3313 AN7583_CSR_PHY_CORE_REG_CLK_SEL | 3314 FIELD_PREP(AN7583_CSR_ETHER_AFE_PWD, 0)); 3315 3316 /* Reset the switch PHYs */ 3317 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3318 3319 return mt7531_setup_common(ds); 3320 } 3321 3322 static const struct dsa_switch_ops mt7530_switch_ops = { 3323 .get_tag_protocol = mtk_get_tag_protocol, 3324 .setup = mt753x_setup, 3325 .teardown = mt753x_teardown, 3326 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3327 .get_strings = mt7530_get_strings, 3328 .get_ethtool_stats = mt7530_get_ethtool_stats, 3329 .get_sset_count = mt7530_get_sset_count, 3330 .get_eth_mac_stats = mt7530_get_eth_mac_stats, 3331 .get_rmon_stats = mt7530_get_rmon_stats, 3332 .get_eth_ctrl_stats = mt7530_get_eth_ctrl_stats, 3333 .get_stats64 = mt7530_get_stats64, 3334 .set_ageing_time = mt7530_set_ageing_time, 3335 .port_enable = mt7530_port_enable, 3336 .port_disable = mt7530_port_disable, 3337 .port_change_mtu = mt7530_port_change_mtu, 3338 .port_max_mtu = mt7530_port_max_mtu, 3339 .port_stp_state_set = mt7530_stp_state_set, 3340 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3341 .port_bridge_flags = mt7530_port_bridge_flags, 3342 .port_bridge_join = mt7530_port_bridge_join, 3343 .port_bridge_leave = mt7530_port_bridge_leave, 3344 .port_fdb_add = mt7530_port_fdb_add, 3345 .port_fdb_del = mt7530_port_fdb_del, 3346 .port_fdb_dump = mt7530_port_fdb_dump, 3347 .port_mdb_add = mt7530_port_mdb_add, 3348 .port_mdb_del = mt7530_port_mdb_del, 3349 .port_vlan_filtering = mt7530_port_vlan_filtering, 3350 .port_vlan_add = mt7530_port_vlan_add, 3351 .port_vlan_del = mt7530_port_vlan_del, 3352 .port_mirror_add = mt753x_port_mirror_add, 3353 .port_mirror_del = mt753x_port_mirror_del, 3354 .phylink_get_caps = mt753x_phylink_get_caps, 3355 .support_eee = dsa_supports_eee, 3356 .set_mac_eee = mt753x_set_mac_eee, 3357 .conduit_state_change = mt753x_conduit_state_change, 3358 .port_setup_tc = mt753x_setup_tc, 3359 .port_hsr_join = dsa_port_simple_hsr_join, 3360 .port_hsr_leave = dsa_port_simple_hsr_leave, 3361 }; 3362 3363 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3364 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3365 .mac_config = mt753x_phylink_mac_config, 3366 .mac_link_down = mt753x_phylink_mac_link_down, 3367 .mac_link_up = mt753x_phylink_mac_link_up, 3368 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3369 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3370 }; 3371 3372 const struct mt753x_info mt753x_table[] = { 3373 [ID_MT7621] = { 3374 .id = ID_MT7621, 3375 .pcs_ops = &mt7530_pcs_ops, 3376 .sw_setup = mt7530_setup, 3377 .phy_read_c22 = mt7530_phy_read_c22, 3378 .phy_write_c22 = mt7530_phy_write_c22, 3379 .phy_read_c45 = mt7530_phy_read_c45, 3380 .phy_write_c45 = mt7530_phy_write_c45, 3381 .mac_port_get_caps = mt7530_mac_port_get_caps, 3382 .mac_port_config = mt7530_mac_config, 3383 }, 3384 [ID_MT7530] = { 3385 .id = ID_MT7530, 3386 .pcs_ops = &mt7530_pcs_ops, 3387 .sw_setup = mt7530_setup, 3388 .phy_read_c22 = mt7530_phy_read_c22, 3389 .phy_write_c22 = mt7530_phy_write_c22, 3390 .phy_read_c45 = mt7530_phy_read_c45, 3391 .phy_write_c45 = mt7530_phy_write_c45, 3392 .mac_port_get_caps = mt7530_mac_port_get_caps, 3393 .mac_port_config = mt7530_mac_config, 3394 }, 3395 [ID_MT7531] = { 3396 .id = ID_MT7531, 3397 .pcs_ops = &mt7530_pcs_ops, 3398 .sw_setup = mt7531_setup, 3399 .phy_read_c22 = mt7531_ind_c22_phy_read, 3400 .phy_write_c22 = mt7531_ind_c22_phy_write, 3401 .phy_read_c45 = mt7531_ind_c45_phy_read, 3402 .phy_write_c45 = mt7531_ind_c45_phy_write, 3403 .mac_port_get_caps = mt7531_mac_port_get_caps, 3404 .mac_port_config = mt7531_mac_config, 3405 }, 3406 [ID_MT7988] = { 3407 .id = ID_MT7988, 3408 .pcs_ops = &mt7530_pcs_ops, 3409 .sw_setup = mt7988_setup, 3410 .phy_read_c22 = mt7531_ind_c22_phy_read, 3411 .phy_write_c22 = mt7531_ind_c22_phy_write, 3412 .phy_read_c45 = mt7531_ind_c45_phy_read, 3413 .phy_write_c45 = mt7531_ind_c45_phy_write, 3414 .mac_port_get_caps = mt7988_mac_port_get_caps, 3415 }, 3416 [ID_EN7581] = { 3417 .id = ID_EN7581, 3418 .pcs_ops = &mt7530_pcs_ops, 3419 .sw_setup = mt7988_setup, 3420 .phy_read_c22 = mt7531_ind_c22_phy_read, 3421 .phy_write_c22 = mt7531_ind_c22_phy_write, 3422 .phy_read_c45 = mt7531_ind_c45_phy_read, 3423 .phy_write_c45 = mt7531_ind_c45_phy_write, 3424 .mac_port_get_caps = en7581_mac_port_get_caps, 3425 }, 3426 [ID_AN7583] = { 3427 .id = ID_AN7583, 3428 .pcs_ops = &mt7530_pcs_ops, 3429 .sw_setup = mt7988_setup, 3430 .phy_read_c22 = mt7531_ind_c22_phy_read, 3431 .phy_write_c22 = mt7531_ind_c22_phy_write, 3432 .phy_read_c45 = mt7531_ind_c45_phy_read, 3433 .phy_write_c45 = mt7531_ind_c45_phy_write, 3434 .mac_port_get_caps = en7581_mac_port_get_caps, 3435 }, 3436 }; 3437 EXPORT_SYMBOL_GPL(mt753x_table); 3438 3439 int 3440 mt7530_probe_common(struct mt7530_priv *priv) 3441 { 3442 struct device *dev = priv->dev; 3443 3444 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3445 if (!priv->ds) 3446 return -ENOMEM; 3447 3448 priv->ds->dev = dev; 3449 priv->ds->num_ports = MT7530_NUM_PORTS; 3450 3451 /* Get the hardware identifier from the devicetree node. 3452 * We will need it for some of the clock and regulator setup. 3453 */ 3454 priv->info = of_device_get_match_data(dev); 3455 if (!priv->info) 3456 return -EINVAL; 3457 3458 priv->id = priv->info->id; 3459 priv->dev = dev; 3460 priv->ds->priv = priv; 3461 priv->ds->ops = &mt7530_switch_ops; 3462 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3463 mutex_init(&priv->reg_mutex); 3464 spin_lock_init(&priv->stats_lock); 3465 INIT_DELAYED_WORK(&priv->stats_work, mt7530_stats_poll); 3466 3467 dev_set_drvdata(dev, priv); 3468 3469 return 0; 3470 } 3471 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3472 3473 void 3474 mt7530_remove_common(struct mt7530_priv *priv) 3475 { 3476 if (priv->irq_domain) 3477 mt7530_free_mdio_irq(priv); 3478 3479 dsa_unregister_switch(priv->ds); 3480 3481 mutex_destroy(&priv->reg_mutex); 3482 } 3483 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3484 3485 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3486 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3487 MODULE_LICENSE("GPL"); 3488