1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 struct mii_bus *bus = priv->bus; 148 149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 150 151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 152 153 mutex_unlock(&bus->mdio_lock); 154 } 155 156 static void 157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 158 { 159 struct mii_bus *bus = priv->bus; 160 u32 val; 161 162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 163 164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 165 val &= ~mask; 166 val |= set; 167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 168 169 mutex_unlock(&bus->mdio_lock); 170 } 171 172 static void 173 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, 0, val); 176 } 177 178 static void 179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 core_rmw(priv, reg, val, 0); 182 } 183 184 static int 185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 struct mii_bus *bus = priv->bus; 188 u16 page, r, lo, hi; 189 int ret; 190 191 page = (reg >> 6) & 0x3ff; 192 r = (reg >> 2) & 0xf; 193 lo = val & 0xffff; 194 hi = val >> 16; 195 196 /* MT7530 uses 31 as the pseudo port */ 197 ret = bus->write(bus, 0x1f, 0x1f, page); 198 if (ret < 0) 199 goto err; 200 201 ret = bus->write(bus, 0x1f, r, lo); 202 if (ret < 0) 203 goto err; 204 205 ret = bus->write(bus, 0x1f, 0x10, hi); 206 err: 207 if (ret < 0) 208 dev_err(&bus->dev, 209 "failed to write mt7530 register\n"); 210 return ret; 211 } 212 213 static u32 214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 215 { 216 struct mii_bus *bus = priv->bus; 217 u16 page, r, lo, hi; 218 int ret; 219 220 page = (reg >> 6) & 0x3ff; 221 r = (reg >> 2) & 0xf; 222 223 /* MT7530 uses 31 as the pseudo port */ 224 ret = bus->write(bus, 0x1f, 0x1f, page); 225 if (ret < 0) { 226 dev_err(&bus->dev, 227 "failed to read mt7530 register\n"); 228 return ret; 229 } 230 231 lo = bus->read(bus, 0x1f, r); 232 hi = bus->read(bus, 0x1f, 0x10); 233 234 return (hi << 16) | (lo & 0xffff); 235 } 236 237 static void 238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 struct mii_bus *bus = priv->bus; 241 242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 243 244 mt7530_mii_write(priv, reg, val); 245 246 mutex_unlock(&bus->mdio_lock); 247 } 248 249 static u32 250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 251 { 252 return mt7530_mii_read(p->priv, p->reg); 253 } 254 255 static u32 256 _mt7530_read(struct mt7530_dummy_poll *p) 257 { 258 struct mii_bus *bus = p->priv->bus; 259 u32 val; 260 261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 262 263 val = mt7530_mii_read(p->priv, p->reg); 264 265 mutex_unlock(&bus->mdio_lock); 266 267 return val; 268 } 269 270 static u32 271 mt7530_read(struct mt7530_priv *priv, u32 reg) 272 { 273 struct mt7530_dummy_poll p; 274 275 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 276 return _mt7530_read(&p); 277 } 278 279 static void 280 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 281 u32 mask, u32 set) 282 { 283 struct mii_bus *bus = priv->bus; 284 u32 val; 285 286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 287 288 val = mt7530_mii_read(priv, reg); 289 val &= ~mask; 290 val |= set; 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static void 297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, 0, val); 300 } 301 302 static void 303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 304 { 305 mt7530_rmw(priv, reg, val, 0); 306 } 307 308 static int 309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 310 { 311 u32 val; 312 int ret; 313 struct mt7530_dummy_poll p; 314 315 /* Set the command operating upon the MAC address entries */ 316 val = ATC_BUSY | ATC_MAT(0) | cmd; 317 mt7530_write(priv, MT7530_ATC, val); 318 319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 320 ret = readx_poll_timeout(_mt7530_read, &p, val, 321 !(val & ATC_BUSY), 20, 20000); 322 if (ret < 0) { 323 dev_err(priv->dev, "reset timeout\n"); 324 return ret; 325 } 326 327 /* Additional sanity for read command if the specified 328 * entry is invalid 329 */ 330 val = mt7530_read(priv, MT7530_ATC); 331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 332 return -EINVAL; 333 334 if (rsp) 335 *rsp = val; 336 337 return 0; 338 } 339 340 static void 341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 342 { 343 u32 reg[3]; 344 int i; 345 346 /* Read from ARL table into an array */ 347 for (i = 0; i < 3; i++) { 348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 349 350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 351 __func__, __LINE__, i, reg[i]); 352 } 353 354 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 364 } 365 366 static void 367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 368 u8 port_mask, const u8 *mac, 369 u8 aging, u8 type) 370 { 371 u32 reg[3] = { 0 }; 372 int i; 373 374 reg[1] |= vid & CVID_MASK; 375 reg[1] |= ATA2_IVL; 376 reg[1] |= ATA2_FID(FID_BRIDGED); 377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 379 /* STATIC_ENT indicate that entry is static wouldn't 380 * be aged out and STATIC_EMP specified as erasing an 381 * entry 382 */ 383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 384 reg[1] |= mac[5] << MAC_BYTE_5; 385 reg[1] |= mac[4] << MAC_BYTE_4; 386 reg[0] |= mac[3] << MAC_BYTE_3; 387 reg[0] |= mac[2] << MAC_BYTE_2; 388 reg[0] |= mac[1] << MAC_BYTE_1; 389 reg[0] |= mac[0] << MAC_BYTE_0; 390 391 /* Write array into the ARL table */ 392 for (i = 0; i < 3; i++) 393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 394 } 395 396 /* Setup TX circuit including relevant PAD and driving */ 397 static int 398 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 399 { 400 struct mt7530_priv *priv = ds->priv; 401 u32 ncpo1, ssc_delta, trgint, i, xtal; 402 403 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 404 405 if (xtal == HWTRAP_XTAL_20MHZ) { 406 dev_err(priv->dev, 407 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 408 __func__); 409 return -EINVAL; 410 } 411 412 switch (interface) { 413 case PHY_INTERFACE_MODE_RGMII: 414 trgint = 0; 415 /* PLL frequency: 125MHz */ 416 ncpo1 = 0x0c80; 417 break; 418 case PHY_INTERFACE_MODE_TRGMII: 419 trgint = 1; 420 if (priv->id == ID_MT7621) { 421 /* PLL frequency: 150MHz: 1.2GBit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0780; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x0a00; 426 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 427 if (xtal == HWTRAP_XTAL_40MHZ) 428 ncpo1 = 0x0c80; 429 if (xtal == HWTRAP_XTAL_25MHZ) 430 ncpo1 = 0x1400; 431 } 432 break; 433 default: 434 dev_err(priv->dev, "xMII interface %d not supported\n", 435 interface); 436 return -EINVAL; 437 } 438 439 if (xtal == HWTRAP_XTAL_25MHZ) 440 ssc_delta = 0x57; 441 else 442 ssc_delta = 0x87; 443 444 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 445 P6_INTF_MODE(trgint)); 446 447 /* Lower Tx Driving for TRGMII path */ 448 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 449 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 450 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 451 452 /* Disable MT7530 core and TRGMII Tx clocks */ 453 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 454 REG_GSWCK_EN | REG_TRGMIICK_EN); 455 456 /* Setup core clock for MT7530 */ 457 /* Disable PLL */ 458 core_write(priv, CORE_GSWPLL_GRP1, 0); 459 460 /* Set core clock into 500Mhz */ 461 core_write(priv, CORE_GSWPLL_GRP2, 462 RG_GSWPLL_POSDIV_500M(1) | 463 RG_GSWPLL_FBKDIV_500M(25)); 464 465 /* Enable PLL */ 466 core_write(priv, CORE_GSWPLL_GRP1, 467 RG_GSWPLL_EN_PRE | 468 RG_GSWPLL_POSDIV_200M(2) | 469 RG_GSWPLL_FBKDIV_200M(32)); 470 471 /* Setup the MT7530 TRGMII Tx Clock */ 472 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 473 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 474 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 475 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 476 core_write(priv, CORE_PLL_GROUP4, 477 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 478 RG_SYSPLL_BIAS_LPF_EN); 479 core_write(priv, CORE_PLL_GROUP2, 480 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 481 RG_SYSPLL_POSDIV(1)); 482 core_write(priv, CORE_PLL_GROUP7, 483 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 484 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 485 486 /* Enable MT7530 core and TRGMII Tx clocks */ 487 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 488 REG_GSWCK_EN | REG_TRGMIICK_EN); 489 490 if (!trgint) 491 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 492 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 493 RD_TAP_MASK, RD_TAP(16)); 494 return 0; 495 } 496 497 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 498 { 499 u32 val; 500 501 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 502 503 return (val & PAD_DUAL_SGMII_EN) != 0; 504 } 505 506 static int 507 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 508 { 509 struct mt7530_priv *priv = ds->priv; 510 u32 top_sig; 511 u32 hwstrap; 512 u32 xtal; 513 u32 val; 514 515 if (mt7531_dual_sgmii_supported(priv)) 516 return 0; 517 518 val = mt7530_read(priv, MT7531_CREV); 519 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 520 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 521 if ((val & CHIP_REV_M) > 0) 522 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 523 HWTRAP_XTAL_FSEL_25MHZ; 524 else 525 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 526 527 /* Step 1 : Disable MT7531 COREPLL */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val &= ~EN_COREPLL; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 /* Step 2: switch to XTAL output */ 533 val = mt7530_read(priv, MT7531_PLLGP_EN); 534 val |= SW_CLKSW; 535 mt7530_write(priv, MT7531_PLLGP_EN, val); 536 537 val = mt7530_read(priv, MT7531_PLLGP_CR0); 538 val &= ~RG_COREPLL_EN; 539 mt7530_write(priv, MT7531_PLLGP_CR0, val); 540 541 /* Step 3: disable PLLGP and enable program PLLGP */ 542 val = mt7530_read(priv, MT7531_PLLGP_EN); 543 val |= SW_PLLGP; 544 mt7530_write(priv, MT7531_PLLGP_EN, val); 545 546 /* Step 4: program COREPLL output frequency to 500MHz */ 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val &= ~RG_COREPLL_POSDIV_M; 549 val |= 2 << RG_COREPLL_POSDIV_S; 550 mt7530_write(priv, MT7531_PLLGP_CR0, val); 551 usleep_range(25, 35); 552 553 switch (xtal) { 554 case HWTRAP_XTAL_FSEL_25MHZ: 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_SDM_PCW_M; 557 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 break; 560 case HWTRAP_XTAL_FSEL_40MHZ: 561 val = mt7530_read(priv, MT7531_PLLGP_CR0); 562 val &= ~RG_COREPLL_SDM_PCW_M; 563 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 564 mt7530_write(priv, MT7531_PLLGP_CR0, val); 565 break; 566 } 567 568 /* Set feedback divide ratio update signal to high */ 569 val = mt7530_read(priv, MT7531_PLLGP_CR0); 570 val |= RG_COREPLL_SDM_PCW_CHG; 571 mt7530_write(priv, MT7531_PLLGP_CR0, val); 572 /* Wait for at least 16 XTAL clocks */ 573 usleep_range(10, 20); 574 575 /* Step 5: set feedback divide ratio update signal to low */ 576 val = mt7530_read(priv, MT7531_PLLGP_CR0); 577 val &= ~RG_COREPLL_SDM_PCW_CHG; 578 mt7530_write(priv, MT7531_PLLGP_CR0, val); 579 580 /* Enable 325M clock for SGMII */ 581 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 582 583 /* Enable 250SSC clock for RGMII */ 584 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 585 586 /* Step 6: Enable MT7531 PLL */ 587 val = mt7530_read(priv, MT7531_PLLGP_CR0); 588 val |= RG_COREPLL_EN; 589 mt7530_write(priv, MT7531_PLLGP_CR0, val); 590 591 val = mt7530_read(priv, MT7531_PLLGP_EN); 592 val |= EN_COREPLL; 593 mt7530_write(priv, MT7531_PLLGP_EN, val); 594 usleep_range(25, 35); 595 596 return 0; 597 } 598 599 static void 600 mt7530_mib_reset(struct dsa_switch *ds) 601 { 602 struct mt7530_priv *priv = ds->priv; 603 604 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 605 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 606 } 607 608 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 609 { 610 return mdiobus_read_nested(priv->bus, port, regnum); 611 } 612 613 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 614 u16 val) 615 { 616 return mdiobus_write_nested(priv->bus, port, regnum, val); 617 } 618 619 static int 620 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 621 int regnum) 622 { 623 struct mii_bus *bus = priv->bus; 624 struct mt7530_dummy_poll p; 625 u32 reg, val; 626 int ret; 627 628 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 629 630 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 631 632 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 633 !(val & MT7531_PHY_ACS_ST), 20, 100000); 634 if (ret < 0) { 635 dev_err(priv->dev, "poll timeout\n"); 636 goto out; 637 } 638 639 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 640 MT7531_MDIO_DEV_ADDR(devad) | regnum; 641 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 642 643 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 644 !(val & MT7531_PHY_ACS_ST), 20, 100000); 645 if (ret < 0) { 646 dev_err(priv->dev, "poll timeout\n"); 647 goto out; 648 } 649 650 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 651 MT7531_MDIO_DEV_ADDR(devad); 652 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 653 654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 655 !(val & MT7531_PHY_ACS_ST), 20, 100000); 656 if (ret < 0) { 657 dev_err(priv->dev, "poll timeout\n"); 658 goto out; 659 } 660 661 ret = val & MT7531_MDIO_RW_DATA_MASK; 662 out: 663 mutex_unlock(&bus->mdio_lock); 664 665 return ret; 666 } 667 668 static int 669 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 670 int regnum, u32 data) 671 { 672 struct mii_bus *bus = priv->bus; 673 struct mt7530_dummy_poll p; 674 u32 val, reg; 675 int ret; 676 677 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 678 679 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 680 681 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 682 !(val & MT7531_PHY_ACS_ST), 20, 100000); 683 if (ret < 0) { 684 dev_err(priv->dev, "poll timeout\n"); 685 goto out; 686 } 687 688 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 689 MT7531_MDIO_DEV_ADDR(devad) | regnum; 690 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 691 692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 693 !(val & MT7531_PHY_ACS_ST), 20, 100000); 694 if (ret < 0) { 695 dev_err(priv->dev, "poll timeout\n"); 696 goto out; 697 } 698 699 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 700 MT7531_MDIO_DEV_ADDR(devad) | data; 701 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 702 703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 704 !(val & MT7531_PHY_ACS_ST), 20, 100000); 705 if (ret < 0) { 706 dev_err(priv->dev, "poll timeout\n"); 707 goto out; 708 } 709 710 out: 711 mutex_unlock(&bus->mdio_lock); 712 713 return ret; 714 } 715 716 static int 717 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 718 { 719 struct mii_bus *bus = priv->bus; 720 struct mt7530_dummy_poll p; 721 int ret; 722 u32 val; 723 724 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 725 726 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 727 728 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 729 !(val & MT7531_PHY_ACS_ST), 20, 100000); 730 if (ret < 0) { 731 dev_err(priv->dev, "poll timeout\n"); 732 goto out; 733 } 734 735 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 736 MT7531_MDIO_REG_ADDR(regnum); 737 738 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 739 740 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 741 !(val & MT7531_PHY_ACS_ST), 20, 100000); 742 if (ret < 0) { 743 dev_err(priv->dev, "poll timeout\n"); 744 goto out; 745 } 746 747 ret = val & MT7531_MDIO_RW_DATA_MASK; 748 out: 749 mutex_unlock(&bus->mdio_lock); 750 751 return ret; 752 } 753 754 static int 755 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 756 u16 data) 757 { 758 struct mii_bus *bus = priv->bus; 759 struct mt7530_dummy_poll p; 760 int ret; 761 u32 reg; 762 763 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 764 765 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 766 767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 768 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 769 if (ret < 0) { 770 dev_err(priv->dev, "poll timeout\n"); 771 goto out; 772 } 773 774 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 775 MT7531_MDIO_REG_ADDR(regnum) | data; 776 777 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 778 779 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 780 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 781 if (ret < 0) { 782 dev_err(priv->dev, "poll timeout\n"); 783 goto out; 784 } 785 786 out: 787 mutex_unlock(&bus->mdio_lock); 788 789 return ret; 790 } 791 792 static int 793 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 794 { 795 int devad; 796 int ret; 797 798 if (regnum & MII_ADDR_C45) { 799 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 800 ret = mt7531_ind_c45_phy_read(priv, port, devad, 801 regnum & MII_REGADDR_C45_MASK); 802 } else { 803 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 804 } 805 806 return ret; 807 } 808 809 static int 810 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 811 u16 data) 812 { 813 int devad; 814 int ret; 815 816 if (regnum & MII_ADDR_C45) { 817 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 818 ret = mt7531_ind_c45_phy_write(priv, port, devad, 819 regnum & MII_REGADDR_C45_MASK, 820 data); 821 } else { 822 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 823 } 824 825 return ret; 826 } 827 828 static int 829 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 830 { 831 struct mt7530_priv *priv = bus->priv; 832 833 return priv->info->phy_read(priv, port, regnum); 834 } 835 836 static int 837 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 838 { 839 struct mt7530_priv *priv = bus->priv; 840 841 return priv->info->phy_write(priv, port, regnum, val); 842 } 843 844 static void 845 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 846 uint8_t *data) 847 { 848 int i; 849 850 if (stringset != ETH_SS_STATS) 851 return; 852 853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 854 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 855 ETH_GSTRING_LEN); 856 } 857 858 static void 859 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 860 uint64_t *data) 861 { 862 struct mt7530_priv *priv = ds->priv; 863 const struct mt7530_mib_desc *mib; 864 u32 reg, i; 865 u64 hi; 866 867 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 868 mib = &mt7530_mib[i]; 869 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 870 871 data[i] = mt7530_read(priv, reg); 872 if (mib->size == 2) { 873 hi = mt7530_read(priv, reg + 4); 874 data[i] |= hi << 32; 875 } 876 } 877 } 878 879 static int 880 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 881 { 882 if (sset != ETH_SS_STATS) 883 return 0; 884 885 return ARRAY_SIZE(mt7530_mib); 886 } 887 888 static int 889 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 890 { 891 struct mt7530_priv *priv = ds->priv; 892 unsigned int secs = msecs / 1000; 893 unsigned int tmp_age_count; 894 unsigned int error = -1; 895 unsigned int age_count; 896 unsigned int age_unit; 897 898 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 899 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 900 return -ERANGE; 901 902 /* iterate through all possible age_count to find the closest pair */ 903 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 904 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 905 906 if (tmp_age_unit <= AGE_UNIT_MAX) { 907 unsigned int tmp_error = secs - 908 (tmp_age_count + 1) * (tmp_age_unit + 1); 909 910 /* found a closer pair */ 911 if (error > tmp_error) { 912 error = tmp_error; 913 age_count = tmp_age_count; 914 age_unit = tmp_age_unit; 915 } 916 917 /* found the exact match, so break the loop */ 918 if (!error) 919 break; 920 } 921 } 922 923 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 924 925 return 0; 926 } 927 928 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 929 { 930 struct mt7530_priv *priv = ds->priv; 931 u8 tx_delay = 0; 932 int val; 933 934 mutex_lock(&priv->reg_mutex); 935 936 val = mt7530_read(priv, MT7530_MHWTRAP); 937 938 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 939 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 940 941 switch (priv->p5_intf_sel) { 942 case P5_INTF_SEL_PHY_P0: 943 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 944 val |= MHWTRAP_PHY0_SEL; 945 fallthrough; 946 case P5_INTF_SEL_PHY_P4: 947 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 948 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 949 950 /* Setup the MAC by default for the cpu port */ 951 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 952 break; 953 case P5_INTF_SEL_GMAC5: 954 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 955 val &= ~MHWTRAP_P5_DIS; 956 break; 957 case P5_DISABLED: 958 interface = PHY_INTERFACE_MODE_NA; 959 break; 960 default: 961 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 962 priv->p5_intf_sel); 963 goto unlock_exit; 964 } 965 966 /* Setup RGMII settings */ 967 if (phy_interface_mode_is_rgmii(interface)) { 968 val |= MHWTRAP_P5_RGMII_MODE; 969 970 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 971 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 972 973 /* Don't set delay in DSA mode */ 974 if (!dsa_is_dsa_port(priv->ds, 5) && 975 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 976 interface == PHY_INTERFACE_MODE_RGMII_ID)) 977 tx_delay = 4; /* n * 0.5 ns */ 978 979 /* P5 RGMII TX Clock Control: delay x */ 980 mt7530_write(priv, MT7530_P5RGMIITXCR, 981 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 982 983 /* reduce P5 RGMII Tx driving, 8mA */ 984 mt7530_write(priv, MT7530_IO_DRV_CR, 985 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 986 } 987 988 mt7530_write(priv, MT7530_MHWTRAP, val); 989 990 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 991 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 992 993 priv->p5_interface = interface; 994 995 unlock_exit: 996 mutex_unlock(&priv->reg_mutex); 997 } 998 999 static int 1000 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1001 { 1002 struct mt7530_priv *priv = ds->priv; 1003 int ret; 1004 1005 /* Setup max capability of CPU port at first */ 1006 if (priv->info->cpu_port_config) { 1007 ret = priv->info->cpu_port_config(ds, port); 1008 if (ret) 1009 return ret; 1010 } 1011 1012 /* Enable Mediatek header mode on the cpu port */ 1013 mt7530_write(priv, MT7530_PVC_P(port), 1014 PORT_SPEC_TAG); 1015 1016 /* Disable flooding by default */ 1017 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1018 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1019 1020 /* Set CPU port number */ 1021 if (priv->id == ID_MT7621) 1022 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1023 1024 /* CPU port gets connected to all user ports of 1025 * the switch. 1026 */ 1027 mt7530_write(priv, MT7530_PCR_P(port), 1028 PCR_MATRIX(dsa_user_ports(priv->ds))); 1029 1030 /* Set to fallback mode for independent VLAN learning */ 1031 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1032 MT7530_PORT_FALLBACK_MODE); 1033 1034 return 0; 1035 } 1036 1037 static int 1038 mt7530_port_enable(struct dsa_switch *ds, int port, 1039 struct phy_device *phy) 1040 { 1041 struct mt7530_priv *priv = ds->priv; 1042 1043 mutex_lock(&priv->reg_mutex); 1044 1045 /* Allow the user port gets connected to the cpu port and also 1046 * restore the port matrix if the port is the member of a certain 1047 * bridge. 1048 */ 1049 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1050 priv->ports[port].enable = true; 1051 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1052 priv->ports[port].pm); 1053 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1054 1055 mutex_unlock(&priv->reg_mutex); 1056 1057 return 0; 1058 } 1059 1060 static void 1061 mt7530_port_disable(struct dsa_switch *ds, int port) 1062 { 1063 struct mt7530_priv *priv = ds->priv; 1064 1065 mutex_lock(&priv->reg_mutex); 1066 1067 /* Clear up all port matrix which could be restored in the next 1068 * enablement for the port. 1069 */ 1070 priv->ports[port].enable = false; 1071 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1072 PCR_MATRIX_CLR); 1073 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1074 1075 mutex_unlock(&priv->reg_mutex); 1076 } 1077 1078 static int 1079 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1080 { 1081 struct mt7530_priv *priv = ds->priv; 1082 struct mii_bus *bus = priv->bus; 1083 int length; 1084 u32 val; 1085 1086 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1087 * largest MTU of the slave ports. Because the switch only has a global 1088 * RX length register, only allowing CPU port here is enough. 1089 */ 1090 if (!dsa_is_cpu_port(ds, port)) 1091 return 0; 1092 1093 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1094 1095 val = mt7530_mii_read(priv, MT7530_GMACCR); 1096 val &= ~MAX_RX_PKT_LEN_MASK; 1097 1098 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1099 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1100 if (length <= 1522) { 1101 val |= MAX_RX_PKT_LEN_1522; 1102 } else if (length <= 1536) { 1103 val |= MAX_RX_PKT_LEN_1536; 1104 } else if (length <= 1552) { 1105 val |= MAX_RX_PKT_LEN_1552; 1106 } else { 1107 val &= ~MAX_RX_JUMBO_MASK; 1108 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1109 val |= MAX_RX_PKT_LEN_JUMBO; 1110 } 1111 1112 mt7530_mii_write(priv, MT7530_GMACCR, val); 1113 1114 mutex_unlock(&bus->mdio_lock); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1121 { 1122 return MT7530_MAX_MTU; 1123 } 1124 1125 static void 1126 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1127 { 1128 struct mt7530_priv *priv = ds->priv; 1129 u32 stp_state; 1130 1131 switch (state) { 1132 case BR_STATE_DISABLED: 1133 stp_state = MT7530_STP_DISABLED; 1134 break; 1135 case BR_STATE_BLOCKING: 1136 stp_state = MT7530_STP_BLOCKING; 1137 break; 1138 case BR_STATE_LISTENING: 1139 stp_state = MT7530_STP_LISTENING; 1140 break; 1141 case BR_STATE_LEARNING: 1142 stp_state = MT7530_STP_LEARNING; 1143 break; 1144 case BR_STATE_FORWARDING: 1145 default: 1146 stp_state = MT7530_STP_FORWARDING; 1147 break; 1148 } 1149 1150 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1151 FID_PST(FID_BRIDGED, stp_state)); 1152 } 1153 1154 static int 1155 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1156 struct switchdev_brport_flags flags, 1157 struct netlink_ext_ack *extack) 1158 { 1159 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1160 BR_BCAST_FLOOD)) 1161 return -EINVAL; 1162 1163 return 0; 1164 } 1165 1166 static int 1167 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1168 struct switchdev_brport_flags flags, 1169 struct netlink_ext_ack *extack) 1170 { 1171 struct mt7530_priv *priv = ds->priv; 1172 1173 if (flags.mask & BR_LEARNING) 1174 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1175 flags.val & BR_LEARNING ? 0 : SA_DIS); 1176 1177 if (flags.mask & BR_FLOOD) 1178 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1179 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1180 1181 if (flags.mask & BR_MCAST_FLOOD) 1182 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1183 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1184 1185 if (flags.mask & BR_BCAST_FLOOD) 1186 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1187 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1188 1189 return 0; 1190 } 1191 1192 static int 1193 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1194 struct dsa_bridge bridge, bool *tx_fwd_offload, 1195 struct netlink_ext_ack *extack) 1196 { 1197 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1198 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1199 struct mt7530_priv *priv = ds->priv; 1200 1201 mutex_lock(&priv->reg_mutex); 1202 1203 dsa_switch_for_each_user_port(other_dp, ds) { 1204 int other_port = other_dp->index; 1205 1206 if (dp == other_dp) 1207 continue; 1208 1209 /* Add this port to the port matrix of the other ports in the 1210 * same bridge. If the port is disabled, port matrix is kept 1211 * and not being setup until the port becomes enabled. 1212 */ 1213 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1214 continue; 1215 1216 if (priv->ports[other_port].enable) 1217 mt7530_set(priv, MT7530_PCR_P(other_port), 1218 PCR_MATRIX(BIT(port))); 1219 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1220 1221 port_bitmap |= BIT(other_port); 1222 } 1223 1224 /* Add the all other ports to this port matrix. */ 1225 if (priv->ports[port].enable) 1226 mt7530_rmw(priv, MT7530_PCR_P(port), 1227 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1228 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1229 1230 /* Set to fallback mode for independent VLAN learning */ 1231 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1232 MT7530_PORT_FALLBACK_MODE); 1233 1234 mutex_unlock(&priv->reg_mutex); 1235 1236 return 0; 1237 } 1238 1239 static void 1240 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1241 { 1242 struct mt7530_priv *priv = ds->priv; 1243 bool all_user_ports_removed = true; 1244 int i; 1245 1246 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1247 * bridge. Don't set standalone ports to fallback mode. 1248 */ 1249 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1250 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1251 MT7530_PORT_FALLBACK_MODE); 1252 1253 mt7530_rmw(priv, MT7530_PVC_P(port), 1254 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1255 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1256 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1257 MT7530_VLAN_ACC_ALL); 1258 1259 /* Set PVID to 0 */ 1260 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1261 G0_PORT_VID_DEF); 1262 1263 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1264 if (dsa_is_user_port(ds, i) && 1265 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1266 all_user_ports_removed = false; 1267 break; 1268 } 1269 } 1270 1271 /* CPU port also does the same thing until all user ports belonging to 1272 * the CPU port get out of VLAN filtering mode. 1273 */ 1274 if (all_user_ports_removed) { 1275 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1276 PCR_MATRIX(dsa_user_ports(priv->ds))); 1277 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1278 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1279 } 1280 } 1281 1282 static void 1283 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1284 { 1285 struct mt7530_priv *priv = ds->priv; 1286 1287 /* Trapped into security mode allows packet forwarding through VLAN 1288 * table lookup. 1289 */ 1290 if (dsa_is_user_port(ds, port)) { 1291 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1292 MT7530_PORT_SECURITY_MODE); 1293 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1294 G0_PORT_VID(priv->ports[port].pvid)); 1295 1296 /* Only accept tagged frames if PVID is not set */ 1297 if (!priv->ports[port].pvid) 1298 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1299 MT7530_VLAN_ACC_TAGGED); 1300 } 1301 1302 /* Set the port as a user port which is to be able to recognize VID 1303 * from incoming packets before fetching entry within the VLAN table. 1304 */ 1305 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1306 VLAN_ATTR(MT7530_VLAN_USER) | 1307 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1308 } 1309 1310 static void 1311 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1312 struct dsa_bridge bridge) 1313 { 1314 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1315 struct mt7530_priv *priv = ds->priv; 1316 1317 mutex_lock(&priv->reg_mutex); 1318 1319 dsa_switch_for_each_user_port(other_dp, ds) { 1320 int other_port = other_dp->index; 1321 1322 if (dp == other_dp) 1323 continue; 1324 1325 /* Remove this port from the port matrix of the other ports 1326 * in the same bridge. If the port is disabled, port matrix 1327 * is kept and not being setup until the port becomes enabled. 1328 */ 1329 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1330 continue; 1331 1332 if (priv->ports[other_port].enable) 1333 mt7530_clear(priv, MT7530_PCR_P(other_port), 1334 PCR_MATRIX(BIT(port))); 1335 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1336 } 1337 1338 /* Set the cpu port to be the only one in the port matrix of 1339 * this port. 1340 */ 1341 if (priv->ports[port].enable) 1342 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1343 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1344 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1345 1346 /* When a port is removed from the bridge, the port would be set up 1347 * back to the default as is at initial boot which is a VLAN-unaware 1348 * port. 1349 */ 1350 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1351 MT7530_PORT_MATRIX_MODE); 1352 1353 mutex_unlock(&priv->reg_mutex); 1354 } 1355 1356 static int 1357 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1358 const unsigned char *addr, u16 vid, 1359 struct dsa_db db) 1360 { 1361 struct mt7530_priv *priv = ds->priv; 1362 int ret; 1363 u8 port_mask = BIT(port); 1364 1365 mutex_lock(&priv->reg_mutex); 1366 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1367 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1368 mutex_unlock(&priv->reg_mutex); 1369 1370 return ret; 1371 } 1372 1373 static int 1374 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1375 const unsigned char *addr, u16 vid, 1376 struct dsa_db db) 1377 { 1378 struct mt7530_priv *priv = ds->priv; 1379 int ret; 1380 u8 port_mask = BIT(port); 1381 1382 mutex_lock(&priv->reg_mutex); 1383 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1384 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1385 mutex_unlock(&priv->reg_mutex); 1386 1387 return ret; 1388 } 1389 1390 static int 1391 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1392 dsa_fdb_dump_cb_t *cb, void *data) 1393 { 1394 struct mt7530_priv *priv = ds->priv; 1395 struct mt7530_fdb _fdb = { 0 }; 1396 int cnt = MT7530_NUM_FDB_RECORDS; 1397 int ret = 0; 1398 u32 rsp = 0; 1399 1400 mutex_lock(&priv->reg_mutex); 1401 1402 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1403 if (ret < 0) 1404 goto err; 1405 1406 do { 1407 if (rsp & ATC_SRCH_HIT) { 1408 mt7530_fdb_read(priv, &_fdb); 1409 if (_fdb.port_mask & BIT(port)) { 1410 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1411 data); 1412 if (ret < 0) 1413 break; 1414 } 1415 } 1416 } while (--cnt && 1417 !(rsp & ATC_SRCH_END) && 1418 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1419 err: 1420 mutex_unlock(&priv->reg_mutex); 1421 1422 return 0; 1423 } 1424 1425 static int 1426 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1427 const struct switchdev_obj_port_mdb *mdb, 1428 struct dsa_db db) 1429 { 1430 struct mt7530_priv *priv = ds->priv; 1431 const u8 *addr = mdb->addr; 1432 u16 vid = mdb->vid; 1433 u8 port_mask = 0; 1434 int ret; 1435 1436 mutex_lock(&priv->reg_mutex); 1437 1438 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1439 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1440 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1441 & PORT_MAP_MASK; 1442 1443 port_mask |= BIT(port); 1444 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1445 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1446 1447 mutex_unlock(&priv->reg_mutex); 1448 1449 return ret; 1450 } 1451 1452 static int 1453 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1454 const struct switchdev_obj_port_mdb *mdb, 1455 struct dsa_db db) 1456 { 1457 struct mt7530_priv *priv = ds->priv; 1458 const u8 *addr = mdb->addr; 1459 u16 vid = mdb->vid; 1460 u8 port_mask = 0; 1461 int ret; 1462 1463 mutex_lock(&priv->reg_mutex); 1464 1465 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1466 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1467 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1468 & PORT_MAP_MASK; 1469 1470 port_mask &= ~BIT(port); 1471 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1472 port_mask ? STATIC_ENT : STATIC_EMP); 1473 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1474 1475 mutex_unlock(&priv->reg_mutex); 1476 1477 return ret; 1478 } 1479 1480 static int 1481 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1482 { 1483 struct mt7530_dummy_poll p; 1484 u32 val; 1485 int ret; 1486 1487 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1488 mt7530_write(priv, MT7530_VTCR, val); 1489 1490 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1491 ret = readx_poll_timeout(_mt7530_read, &p, val, 1492 !(val & VTCR_BUSY), 20, 20000); 1493 if (ret < 0) { 1494 dev_err(priv->dev, "poll timeout\n"); 1495 return ret; 1496 } 1497 1498 val = mt7530_read(priv, MT7530_VTCR); 1499 if (val & VTCR_INVALID) { 1500 dev_err(priv->dev, "read VTCR invalid\n"); 1501 return -EINVAL; 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int 1508 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1509 struct netlink_ext_ack *extack) 1510 { 1511 if (vlan_filtering) { 1512 /* The port is being kept as VLAN-unaware port when bridge is 1513 * set up with vlan_filtering not being set, Otherwise, the 1514 * port and the corresponding CPU port is required the setup 1515 * for becoming a VLAN-aware port. 1516 */ 1517 mt7530_port_set_vlan_aware(ds, port); 1518 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1519 } else { 1520 mt7530_port_set_vlan_unaware(ds, port); 1521 } 1522 1523 return 0; 1524 } 1525 1526 static void 1527 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1528 struct mt7530_hw_vlan_entry *entry) 1529 { 1530 u8 new_members; 1531 u32 val; 1532 1533 new_members = entry->old_members | BIT(entry->port) | 1534 BIT(MT7530_CPU_PORT); 1535 1536 /* Validate the entry with independent learning, create egress tag per 1537 * VLAN and joining the port as one of the port members. 1538 */ 1539 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1540 VLAN_VALID; 1541 mt7530_write(priv, MT7530_VAWD1, val); 1542 1543 /* Decide whether adding tag or not for those outgoing packets from the 1544 * port inside the VLAN. 1545 */ 1546 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1547 MT7530_VLAN_EGRESS_TAG; 1548 mt7530_rmw(priv, MT7530_VAWD2, 1549 ETAG_CTRL_P_MASK(entry->port), 1550 ETAG_CTRL_P(entry->port, val)); 1551 1552 /* CPU port is always taken as a tagged port for serving more than one 1553 * VLANs across and also being applied with egress type stack mode for 1554 * that VLAN tags would be appended after hardware special tag used as 1555 * DSA tag. 1556 */ 1557 mt7530_rmw(priv, MT7530_VAWD2, 1558 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1559 ETAG_CTRL_P(MT7530_CPU_PORT, 1560 MT7530_VLAN_EGRESS_STACK)); 1561 } 1562 1563 static void 1564 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1565 struct mt7530_hw_vlan_entry *entry) 1566 { 1567 u8 new_members; 1568 u32 val; 1569 1570 new_members = entry->old_members & ~BIT(entry->port); 1571 1572 val = mt7530_read(priv, MT7530_VAWD1); 1573 if (!(val & VLAN_VALID)) { 1574 dev_err(priv->dev, 1575 "Cannot be deleted due to invalid entry\n"); 1576 return; 1577 } 1578 1579 /* If certain member apart from CPU port is still alive in the VLAN, 1580 * the entry would be kept valid. Otherwise, the entry is got to be 1581 * disabled. 1582 */ 1583 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1584 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1585 VLAN_VALID; 1586 mt7530_write(priv, MT7530_VAWD1, val); 1587 } else { 1588 mt7530_write(priv, MT7530_VAWD1, 0); 1589 mt7530_write(priv, MT7530_VAWD2, 0); 1590 } 1591 } 1592 1593 static void 1594 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1595 struct mt7530_hw_vlan_entry *entry, 1596 mt7530_vlan_op vlan_op) 1597 { 1598 u32 val; 1599 1600 /* Fetch entry */ 1601 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1602 1603 val = mt7530_read(priv, MT7530_VAWD1); 1604 1605 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1606 1607 /* Manipulate entry */ 1608 vlan_op(priv, entry); 1609 1610 /* Flush result to hardware */ 1611 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1612 } 1613 1614 static int 1615 mt7530_setup_vlan0(struct mt7530_priv *priv) 1616 { 1617 u32 val; 1618 1619 /* Validate the entry with independent learning, keep the original 1620 * ingress tag attribute. 1621 */ 1622 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1623 VLAN_VALID; 1624 mt7530_write(priv, MT7530_VAWD1, val); 1625 1626 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1627 } 1628 1629 static int 1630 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1631 const struct switchdev_obj_port_vlan *vlan, 1632 struct netlink_ext_ack *extack) 1633 { 1634 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1635 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1636 struct mt7530_hw_vlan_entry new_entry; 1637 struct mt7530_priv *priv = ds->priv; 1638 1639 mutex_lock(&priv->reg_mutex); 1640 1641 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1642 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1643 1644 if (pvid) { 1645 priv->ports[port].pvid = vlan->vid; 1646 1647 /* Accept all frames if PVID is set */ 1648 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1649 MT7530_VLAN_ACC_ALL); 1650 1651 /* Only configure PVID if VLAN filtering is enabled */ 1652 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1653 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1654 G0_PORT_VID_MASK, 1655 G0_PORT_VID(vlan->vid)); 1656 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1657 /* This VLAN is overwritten without PVID, so unset it */ 1658 priv->ports[port].pvid = G0_PORT_VID_DEF; 1659 1660 /* Only accept tagged frames if the port is VLAN-aware */ 1661 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1662 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1663 MT7530_VLAN_ACC_TAGGED); 1664 1665 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1666 G0_PORT_VID_DEF); 1667 } 1668 1669 mutex_unlock(&priv->reg_mutex); 1670 1671 return 0; 1672 } 1673 1674 static int 1675 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1676 const struct switchdev_obj_port_vlan *vlan) 1677 { 1678 struct mt7530_hw_vlan_entry target_entry; 1679 struct mt7530_priv *priv = ds->priv; 1680 1681 mutex_lock(&priv->reg_mutex); 1682 1683 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1684 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1685 mt7530_hw_vlan_del); 1686 1687 /* PVID is being restored to the default whenever the PVID port 1688 * is being removed from the VLAN. 1689 */ 1690 if (priv->ports[port].pvid == vlan->vid) { 1691 priv->ports[port].pvid = G0_PORT_VID_DEF; 1692 1693 /* Only accept tagged frames if the port is VLAN-aware */ 1694 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1695 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1696 MT7530_VLAN_ACC_TAGGED); 1697 1698 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1699 G0_PORT_VID_DEF); 1700 } 1701 1702 1703 mutex_unlock(&priv->reg_mutex); 1704 1705 return 0; 1706 } 1707 1708 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1709 { 1710 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1711 MIRROR_PORT(val); 1712 } 1713 1714 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1715 { 1716 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1717 MIRROR_PORT(val); 1718 } 1719 1720 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1721 struct dsa_mall_mirror_tc_entry *mirror, 1722 bool ingress, struct netlink_ext_ack *extack) 1723 { 1724 struct mt7530_priv *priv = ds->priv; 1725 int monitor_port; 1726 u32 val; 1727 1728 /* Check for existent entry */ 1729 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1730 return -EEXIST; 1731 1732 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1733 1734 /* MT7530 only supports one monitor port */ 1735 monitor_port = mt753x_mirror_port_get(priv->id, val); 1736 if (val & MT753X_MIRROR_EN(priv->id) && 1737 monitor_port != mirror->to_local_port) 1738 return -EEXIST; 1739 1740 val |= MT753X_MIRROR_EN(priv->id); 1741 val &= ~MT753X_MIRROR_MASK(priv->id); 1742 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1743 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1744 1745 val = mt7530_read(priv, MT7530_PCR_P(port)); 1746 if (ingress) { 1747 val |= PORT_RX_MIR; 1748 priv->mirror_rx |= BIT(port); 1749 } else { 1750 val |= PORT_TX_MIR; 1751 priv->mirror_tx |= BIT(port); 1752 } 1753 mt7530_write(priv, MT7530_PCR_P(port), val); 1754 1755 return 0; 1756 } 1757 1758 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1759 struct dsa_mall_mirror_tc_entry *mirror) 1760 { 1761 struct mt7530_priv *priv = ds->priv; 1762 u32 val; 1763 1764 val = mt7530_read(priv, MT7530_PCR_P(port)); 1765 if (mirror->ingress) { 1766 val &= ~PORT_RX_MIR; 1767 priv->mirror_rx &= ~BIT(port); 1768 } else { 1769 val &= ~PORT_TX_MIR; 1770 priv->mirror_tx &= ~BIT(port); 1771 } 1772 mt7530_write(priv, MT7530_PCR_P(port), val); 1773 1774 if (!priv->mirror_rx && !priv->mirror_tx) { 1775 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1776 val &= ~MT753X_MIRROR_EN(priv->id); 1777 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1778 } 1779 } 1780 1781 static enum dsa_tag_protocol 1782 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1783 enum dsa_tag_protocol mp) 1784 { 1785 return DSA_TAG_PROTO_MTK; 1786 } 1787 1788 #ifdef CONFIG_GPIOLIB 1789 static inline u32 1790 mt7530_gpio_to_bit(unsigned int offset) 1791 { 1792 /* Map GPIO offset to register bit 1793 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1794 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1795 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1796 * [14:12] port 3 LED 0..2 as GPIO 9..11 1797 * [18:16] port 4 LED 0..2 as GPIO 12..14 1798 */ 1799 return BIT(offset + offset / 3); 1800 } 1801 1802 static int 1803 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1804 { 1805 struct mt7530_priv *priv = gpiochip_get_data(gc); 1806 u32 bit = mt7530_gpio_to_bit(offset); 1807 1808 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1809 } 1810 1811 static void 1812 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1813 { 1814 struct mt7530_priv *priv = gpiochip_get_data(gc); 1815 u32 bit = mt7530_gpio_to_bit(offset); 1816 1817 if (value) 1818 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1819 else 1820 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1821 } 1822 1823 static int 1824 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1825 { 1826 struct mt7530_priv *priv = gpiochip_get_data(gc); 1827 u32 bit = mt7530_gpio_to_bit(offset); 1828 1829 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1830 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1831 } 1832 1833 static int 1834 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1835 { 1836 struct mt7530_priv *priv = gpiochip_get_data(gc); 1837 u32 bit = mt7530_gpio_to_bit(offset); 1838 1839 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1840 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1841 1842 return 0; 1843 } 1844 1845 static int 1846 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1847 { 1848 struct mt7530_priv *priv = gpiochip_get_data(gc); 1849 u32 bit = mt7530_gpio_to_bit(offset); 1850 1851 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1852 1853 if (value) 1854 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1855 else 1856 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1857 1858 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1859 1860 return 0; 1861 } 1862 1863 static int 1864 mt7530_setup_gpio(struct mt7530_priv *priv) 1865 { 1866 struct device *dev = priv->dev; 1867 struct gpio_chip *gc; 1868 1869 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1870 if (!gc) 1871 return -ENOMEM; 1872 1873 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1874 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1875 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1876 1877 gc->label = "mt7530"; 1878 gc->parent = dev; 1879 gc->owner = THIS_MODULE; 1880 gc->get_direction = mt7530_gpio_get_direction; 1881 gc->direction_input = mt7530_gpio_direction_input; 1882 gc->direction_output = mt7530_gpio_direction_output; 1883 gc->get = mt7530_gpio_get; 1884 gc->set = mt7530_gpio_set; 1885 gc->base = -1; 1886 gc->ngpio = 15; 1887 gc->can_sleep = true; 1888 1889 return devm_gpiochip_add_data(dev, gc, priv); 1890 } 1891 #endif /* CONFIG_GPIOLIB */ 1892 1893 static irqreturn_t 1894 mt7530_irq_thread_fn(int irq, void *dev_id) 1895 { 1896 struct mt7530_priv *priv = dev_id; 1897 bool handled = false; 1898 u32 val; 1899 int p; 1900 1901 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1902 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1903 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1904 mutex_unlock(&priv->bus->mdio_lock); 1905 1906 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1907 if (BIT(p) & val) { 1908 unsigned int irq; 1909 1910 irq = irq_find_mapping(priv->irq_domain, p); 1911 handle_nested_irq(irq); 1912 handled = true; 1913 } 1914 } 1915 1916 return IRQ_RETVAL(handled); 1917 } 1918 1919 static void 1920 mt7530_irq_mask(struct irq_data *d) 1921 { 1922 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1923 1924 priv->irq_enable &= ~BIT(d->hwirq); 1925 } 1926 1927 static void 1928 mt7530_irq_unmask(struct irq_data *d) 1929 { 1930 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1931 1932 priv->irq_enable |= BIT(d->hwirq); 1933 } 1934 1935 static void 1936 mt7530_irq_bus_lock(struct irq_data *d) 1937 { 1938 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1939 1940 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1941 } 1942 1943 static void 1944 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1945 { 1946 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1947 1948 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1949 mutex_unlock(&priv->bus->mdio_lock); 1950 } 1951 1952 static struct irq_chip mt7530_irq_chip = { 1953 .name = KBUILD_MODNAME, 1954 .irq_mask = mt7530_irq_mask, 1955 .irq_unmask = mt7530_irq_unmask, 1956 .irq_bus_lock = mt7530_irq_bus_lock, 1957 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1958 }; 1959 1960 static int 1961 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1962 irq_hw_number_t hwirq) 1963 { 1964 irq_set_chip_data(irq, domain->host_data); 1965 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1966 irq_set_nested_thread(irq, true); 1967 irq_set_noprobe(irq); 1968 1969 return 0; 1970 } 1971 1972 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1973 .map = mt7530_irq_map, 1974 .xlate = irq_domain_xlate_onecell, 1975 }; 1976 1977 static void 1978 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1979 { 1980 struct dsa_switch *ds = priv->ds; 1981 int p; 1982 1983 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1984 if (BIT(p) & ds->phys_mii_mask) { 1985 unsigned int irq; 1986 1987 irq = irq_create_mapping(priv->irq_domain, p); 1988 ds->slave_mii_bus->irq[p] = irq; 1989 } 1990 } 1991 } 1992 1993 static int 1994 mt7530_setup_irq(struct mt7530_priv *priv) 1995 { 1996 struct device *dev = priv->dev; 1997 struct device_node *np = dev->of_node; 1998 int ret; 1999 2000 if (!of_property_read_bool(np, "interrupt-controller")) { 2001 dev_info(dev, "no interrupt support\n"); 2002 return 0; 2003 } 2004 2005 priv->irq = of_irq_get(np, 0); 2006 if (priv->irq <= 0) { 2007 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2008 return priv->irq ? : -EINVAL; 2009 } 2010 2011 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2012 &mt7530_irq_domain_ops, priv); 2013 if (!priv->irq_domain) { 2014 dev_err(dev, "failed to create IRQ domain\n"); 2015 return -ENOMEM; 2016 } 2017 2018 /* This register must be set for MT7530 to properly fire interrupts */ 2019 if (priv->id != ID_MT7531) 2020 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2021 2022 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2023 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2024 if (ret) { 2025 irq_domain_remove(priv->irq_domain); 2026 dev_err(dev, "failed to request IRQ: %d\n", ret); 2027 return ret; 2028 } 2029 2030 return 0; 2031 } 2032 2033 static void 2034 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2035 { 2036 int p; 2037 2038 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2039 if (BIT(p) & priv->ds->phys_mii_mask) { 2040 unsigned int irq; 2041 2042 irq = irq_find_mapping(priv->irq_domain, p); 2043 irq_dispose_mapping(irq); 2044 } 2045 } 2046 } 2047 2048 static void 2049 mt7530_free_irq_common(struct mt7530_priv *priv) 2050 { 2051 free_irq(priv->irq, priv); 2052 irq_domain_remove(priv->irq_domain); 2053 } 2054 2055 static void 2056 mt7530_free_irq(struct mt7530_priv *priv) 2057 { 2058 mt7530_free_mdio_irq(priv); 2059 mt7530_free_irq_common(priv); 2060 } 2061 2062 static int 2063 mt7530_setup_mdio(struct mt7530_priv *priv) 2064 { 2065 struct dsa_switch *ds = priv->ds; 2066 struct device *dev = priv->dev; 2067 struct mii_bus *bus; 2068 static int idx; 2069 int ret; 2070 2071 bus = devm_mdiobus_alloc(dev); 2072 if (!bus) 2073 return -ENOMEM; 2074 2075 ds->slave_mii_bus = bus; 2076 bus->priv = priv; 2077 bus->name = KBUILD_MODNAME "-mii"; 2078 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2079 bus->read = mt753x_phy_read; 2080 bus->write = mt753x_phy_write; 2081 bus->parent = dev; 2082 bus->phy_mask = ~ds->phys_mii_mask; 2083 2084 if (priv->irq) 2085 mt7530_setup_mdio_irq(priv); 2086 2087 ret = devm_mdiobus_register(dev, bus); 2088 if (ret) { 2089 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2090 if (priv->irq) 2091 mt7530_free_mdio_irq(priv); 2092 } 2093 2094 return ret; 2095 } 2096 2097 static int 2098 mt7530_setup(struct dsa_switch *ds) 2099 { 2100 struct mt7530_priv *priv = ds->priv; 2101 struct device_node *phy_node; 2102 struct device_node *mac_np; 2103 struct mt7530_dummy_poll p; 2104 phy_interface_t interface; 2105 struct device_node *dn; 2106 u32 id, val; 2107 int ret, i; 2108 2109 /* The parent node of master netdev which holds the common system 2110 * controller also is the container for two GMACs nodes representing 2111 * as two netdev instances. 2112 */ 2113 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2114 ds->assisted_learning_on_cpu_port = true; 2115 ds->mtu_enforcement_ingress = true; 2116 2117 if (priv->id == ID_MT7530) { 2118 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2119 ret = regulator_enable(priv->core_pwr); 2120 if (ret < 0) { 2121 dev_err(priv->dev, 2122 "Failed to enable core power: %d\n", ret); 2123 return ret; 2124 } 2125 2126 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2127 ret = regulator_enable(priv->io_pwr); 2128 if (ret < 0) { 2129 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2130 ret); 2131 return ret; 2132 } 2133 } 2134 2135 /* Reset whole chip through gpio pin or memory-mapped registers for 2136 * different type of hardware 2137 */ 2138 if (priv->mcm) { 2139 reset_control_assert(priv->rstc); 2140 usleep_range(1000, 1100); 2141 reset_control_deassert(priv->rstc); 2142 } else { 2143 gpiod_set_value_cansleep(priv->reset, 0); 2144 usleep_range(1000, 1100); 2145 gpiod_set_value_cansleep(priv->reset, 1); 2146 } 2147 2148 /* Waiting for MT7530 got to stable */ 2149 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2150 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2151 20, 1000000); 2152 if (ret < 0) { 2153 dev_err(priv->dev, "reset timeout\n"); 2154 return ret; 2155 } 2156 2157 id = mt7530_read(priv, MT7530_CREV); 2158 id >>= CHIP_NAME_SHIFT; 2159 if (id != MT7530_ID) { 2160 dev_err(priv->dev, "chip %x can't be supported\n", id); 2161 return -ENODEV; 2162 } 2163 2164 /* Reset the switch through internal reset */ 2165 mt7530_write(priv, MT7530_SYS_CTRL, 2166 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2167 SYS_CTRL_REG_RST); 2168 2169 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2170 val = mt7530_read(priv, MT7530_MHWTRAP); 2171 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2172 val |= MHWTRAP_MANUAL; 2173 mt7530_write(priv, MT7530_MHWTRAP, val); 2174 2175 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2176 2177 /* Enable and reset MIB counters */ 2178 mt7530_mib_reset(ds); 2179 2180 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2181 /* Disable forwarding by default on all ports */ 2182 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2183 PCR_MATRIX_CLR); 2184 2185 /* Disable learning by default on all ports */ 2186 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2187 2188 if (dsa_is_cpu_port(ds, i)) { 2189 ret = mt753x_cpu_port_enable(ds, i); 2190 if (ret) 2191 return ret; 2192 } else { 2193 mt7530_port_disable(ds, i); 2194 2195 /* Set default PVID to 0 on all user ports */ 2196 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2197 G0_PORT_VID_DEF); 2198 } 2199 /* Enable consistent egress tag */ 2200 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2201 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2202 } 2203 2204 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2205 ret = mt7530_setup_vlan0(priv); 2206 if (ret) 2207 return ret; 2208 2209 /* Setup port 5 */ 2210 priv->p5_intf_sel = P5_DISABLED; 2211 interface = PHY_INTERFACE_MODE_NA; 2212 2213 if (!dsa_is_unused_port(ds, 5)) { 2214 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2215 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2216 if (ret && ret != -ENODEV) 2217 return ret; 2218 } else { 2219 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2220 for_each_child_of_node(dn, mac_np) { 2221 if (!of_device_is_compatible(mac_np, 2222 "mediatek,eth-mac")) 2223 continue; 2224 2225 ret = of_property_read_u32(mac_np, "reg", &id); 2226 if (ret < 0 || id != 1) 2227 continue; 2228 2229 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2230 if (!phy_node) 2231 continue; 2232 2233 if (phy_node->parent == priv->dev->of_node->parent) { 2234 ret = of_get_phy_mode(mac_np, &interface); 2235 if (ret && ret != -ENODEV) { 2236 of_node_put(mac_np); 2237 of_node_put(phy_node); 2238 return ret; 2239 } 2240 id = of_mdio_parse_addr(ds->dev, phy_node); 2241 if (id == 0) 2242 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2243 if (id == 4) 2244 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2245 } 2246 of_node_put(mac_np); 2247 of_node_put(phy_node); 2248 break; 2249 } 2250 } 2251 2252 #ifdef CONFIG_GPIOLIB 2253 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2254 ret = mt7530_setup_gpio(priv); 2255 if (ret) 2256 return ret; 2257 } 2258 #endif /* CONFIG_GPIOLIB */ 2259 2260 mt7530_setup_port5(ds, interface); 2261 2262 /* Flush the FDB table */ 2263 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2264 if (ret < 0) 2265 return ret; 2266 2267 return 0; 2268 } 2269 2270 static int 2271 mt7531_setup(struct dsa_switch *ds) 2272 { 2273 struct mt7530_priv *priv = ds->priv; 2274 struct mt7530_dummy_poll p; 2275 u32 val, id; 2276 int ret, i; 2277 2278 /* Reset whole chip through gpio pin or memory-mapped registers for 2279 * different type of hardware 2280 */ 2281 if (priv->mcm) { 2282 reset_control_assert(priv->rstc); 2283 usleep_range(1000, 1100); 2284 reset_control_deassert(priv->rstc); 2285 } else { 2286 gpiod_set_value_cansleep(priv->reset, 0); 2287 usleep_range(1000, 1100); 2288 gpiod_set_value_cansleep(priv->reset, 1); 2289 } 2290 2291 /* Waiting for MT7530 got to stable */ 2292 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2293 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2294 20, 1000000); 2295 if (ret < 0) { 2296 dev_err(priv->dev, "reset timeout\n"); 2297 return ret; 2298 } 2299 2300 id = mt7530_read(priv, MT7531_CREV); 2301 id >>= CHIP_NAME_SHIFT; 2302 2303 if (id != MT7531_ID) { 2304 dev_err(priv->dev, "chip %x can't be supported\n", id); 2305 return -ENODEV; 2306 } 2307 2308 /* Reset the switch through internal reset */ 2309 mt7530_write(priv, MT7530_SYS_CTRL, 2310 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2311 SYS_CTRL_REG_RST); 2312 2313 if (mt7531_dual_sgmii_supported(priv)) { 2314 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2315 2316 /* Let ds->slave_mii_bus be able to access external phy. */ 2317 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2318 MT7531_EXT_P_MDC_11); 2319 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2320 MT7531_EXT_P_MDIO_12); 2321 } else { 2322 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2323 } 2324 dev_dbg(ds->dev, "P5 support %s interface\n", 2325 p5_intf_modes(priv->p5_intf_sel)); 2326 2327 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2328 MT7531_GPIO0_INTERRUPT); 2329 2330 /* Let phylink decide the interface later. */ 2331 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2332 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2333 2334 /* Enable PHY core PLL, since phy_device has not yet been created 2335 * provided for phy_[read,write]_mmd_indirect is called, we provide 2336 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2337 * function. 2338 */ 2339 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2340 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2341 val |= MT7531_PHY_PLL_BYPASS_MODE; 2342 val &= ~MT7531_PHY_PLL_OFF; 2343 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2344 CORE_PLL_GROUP4, val); 2345 2346 /* BPDU to CPU port */ 2347 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2348 BIT(MT7530_CPU_PORT)); 2349 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2350 MT753X_BPDU_CPU_ONLY); 2351 2352 /* Enable and reset MIB counters */ 2353 mt7530_mib_reset(ds); 2354 2355 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2356 /* Disable forwarding by default on all ports */ 2357 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2358 PCR_MATRIX_CLR); 2359 2360 /* Disable learning by default on all ports */ 2361 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2362 2363 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2364 2365 if (dsa_is_cpu_port(ds, i)) { 2366 ret = mt753x_cpu_port_enable(ds, i); 2367 if (ret) 2368 return ret; 2369 } else { 2370 mt7530_port_disable(ds, i); 2371 2372 /* Set default PVID to 0 on all user ports */ 2373 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2374 G0_PORT_VID_DEF); 2375 } 2376 2377 /* Enable consistent egress tag */ 2378 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2379 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2380 } 2381 2382 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2383 ret = mt7530_setup_vlan0(priv); 2384 if (ret) 2385 return ret; 2386 2387 ds->assisted_learning_on_cpu_port = true; 2388 ds->mtu_enforcement_ingress = true; 2389 2390 /* Flush the FDB table */ 2391 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2392 if (ret < 0) 2393 return ret; 2394 2395 return 0; 2396 } 2397 2398 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2399 struct phylink_config *config) 2400 { 2401 switch (port) { 2402 case 0 ... 4: /* Internal phy */ 2403 __set_bit(PHY_INTERFACE_MODE_GMII, 2404 config->supported_interfaces); 2405 break; 2406 2407 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2408 phy_interface_set_rgmii(config->supported_interfaces); 2409 __set_bit(PHY_INTERFACE_MODE_MII, 2410 config->supported_interfaces); 2411 __set_bit(PHY_INTERFACE_MODE_GMII, 2412 config->supported_interfaces); 2413 break; 2414 2415 case 6: /* 1st cpu port */ 2416 __set_bit(PHY_INTERFACE_MODE_RGMII, 2417 config->supported_interfaces); 2418 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2419 config->supported_interfaces); 2420 break; 2421 } 2422 } 2423 2424 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2425 { 2426 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2427 } 2428 2429 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2430 struct phylink_config *config) 2431 { 2432 struct mt7530_priv *priv = ds->priv; 2433 2434 switch (port) { 2435 case 0 ... 4: /* Internal phy */ 2436 __set_bit(PHY_INTERFACE_MODE_GMII, 2437 config->supported_interfaces); 2438 break; 2439 2440 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2441 if (mt7531_is_rgmii_port(priv, port)) { 2442 phy_interface_set_rgmii(config->supported_interfaces); 2443 break; 2444 } 2445 fallthrough; 2446 2447 case 6: /* 1st cpu port supports sgmii/8023z only */ 2448 __set_bit(PHY_INTERFACE_MODE_SGMII, 2449 config->supported_interfaces); 2450 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2451 config->supported_interfaces); 2452 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2453 config->supported_interfaces); 2454 2455 config->mac_capabilities |= MAC_2500FD; 2456 break; 2457 } 2458 } 2459 2460 static int 2461 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2462 { 2463 struct mt7530_priv *priv = ds->priv; 2464 2465 return priv->info->pad_setup(ds, state->interface); 2466 } 2467 2468 static int 2469 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2470 phy_interface_t interface) 2471 { 2472 struct mt7530_priv *priv = ds->priv; 2473 2474 /* Only need to setup port5. */ 2475 if (port != 5) 2476 return 0; 2477 2478 mt7530_setup_port5(priv->ds, interface); 2479 2480 return 0; 2481 } 2482 2483 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2484 phy_interface_t interface, 2485 struct phy_device *phydev) 2486 { 2487 u32 val; 2488 2489 if (!mt7531_is_rgmii_port(priv, port)) { 2490 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2491 port); 2492 return -EINVAL; 2493 } 2494 2495 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2496 val |= GP_CLK_EN; 2497 val &= ~GP_MODE_MASK; 2498 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2499 val &= ~CLK_SKEW_IN_MASK; 2500 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2501 val &= ~CLK_SKEW_OUT_MASK; 2502 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2503 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2504 2505 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2506 if (!phydev || phy_driver_is_genphy(phydev)) { 2507 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2508 switch (interface) { 2509 case PHY_INTERFACE_MODE_RGMII: 2510 val |= TXCLK_NO_REVERSE; 2511 val |= RXCLK_NO_DELAY; 2512 break; 2513 case PHY_INTERFACE_MODE_RGMII_RXID: 2514 val |= TXCLK_NO_REVERSE; 2515 break; 2516 case PHY_INTERFACE_MODE_RGMII_TXID: 2517 val |= RXCLK_NO_DELAY; 2518 break; 2519 case PHY_INTERFACE_MODE_RGMII_ID: 2520 break; 2521 default: 2522 return -EINVAL; 2523 } 2524 } 2525 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2526 2527 return 0; 2528 } 2529 2530 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 2531 phy_interface_t interface, int speed, int duplex) 2532 { 2533 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2534 int port = pcs_to_mt753x_pcs(pcs)->port; 2535 unsigned int val; 2536 2537 /* For adjusting speed and duplex of SGMII force mode. */ 2538 if (interface != PHY_INTERFACE_MODE_SGMII || 2539 phylink_autoneg_inband(mode)) 2540 return; 2541 2542 /* SGMII force mode setting */ 2543 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2544 val &= ~MT7531_SGMII_IF_MODE_MASK; 2545 2546 switch (speed) { 2547 case SPEED_10: 2548 val |= MT7531_SGMII_FORCE_SPEED_10; 2549 break; 2550 case SPEED_100: 2551 val |= MT7531_SGMII_FORCE_SPEED_100; 2552 break; 2553 case SPEED_1000: 2554 val |= MT7531_SGMII_FORCE_SPEED_1000; 2555 break; 2556 } 2557 2558 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2559 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2560 * 2561 * The speed check is unnecessary as the MAC capabilities apply 2562 * this restriction. --rmk 2563 */ 2564 if ((speed == SPEED_10 || speed == SPEED_100) && 2565 duplex != DUPLEX_FULL) 2566 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2567 2568 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2569 } 2570 2571 static bool mt753x_is_mac_port(u32 port) 2572 { 2573 return (port == 5 || port == 6); 2574 } 2575 2576 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2577 phy_interface_t interface) 2578 { 2579 u32 val; 2580 2581 if (!mt753x_is_mac_port(port)) 2582 return -EINVAL; 2583 2584 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2585 MT7531_SGMII_PHYA_PWD); 2586 2587 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2588 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2589 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2590 * encoding. 2591 */ 2592 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2593 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2594 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2595 2596 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2597 2598 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2599 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2600 */ 2601 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2602 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2603 MT7531_SGMII_FORCE_SPEED_1000); 2604 2605 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2606 2607 return 0; 2608 } 2609 2610 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2611 phy_interface_t interface) 2612 { 2613 if (!mt753x_is_mac_port(port)) 2614 return -EINVAL; 2615 2616 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2617 MT7531_SGMII_PHYA_PWD); 2618 2619 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2620 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2621 2622 mt7530_set(priv, MT7531_SGMII_MODE(port), 2623 MT7531_SGMII_REMOTE_FAULT_DIS | 2624 MT7531_SGMII_SPEED_DUPLEX_AN); 2625 2626 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2627 MT7531_SGMII_TX_CONFIG_MASK, 1); 2628 2629 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2630 2631 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2632 2633 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2634 2635 return 0; 2636 } 2637 2638 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) 2639 { 2640 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2641 int port = pcs_to_mt753x_pcs(pcs)->port; 2642 u32 val; 2643 2644 /* Only restart AN when AN is enabled */ 2645 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2646 if (val & MT7531_SGMII_AN_ENABLE) { 2647 val |= MT7531_SGMII_AN_RESTART; 2648 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2649 } 2650 } 2651 2652 static int 2653 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2654 phy_interface_t interface) 2655 { 2656 struct mt7530_priv *priv = ds->priv; 2657 struct phy_device *phydev; 2658 struct dsa_port *dp; 2659 2660 if (!mt753x_is_mac_port(port)) { 2661 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2662 return -EINVAL; 2663 } 2664 2665 switch (interface) { 2666 case PHY_INTERFACE_MODE_RGMII: 2667 case PHY_INTERFACE_MODE_RGMII_ID: 2668 case PHY_INTERFACE_MODE_RGMII_RXID: 2669 case PHY_INTERFACE_MODE_RGMII_TXID: 2670 dp = dsa_to_port(ds, port); 2671 phydev = dp->slave->phydev; 2672 return mt7531_rgmii_setup(priv, port, interface, phydev); 2673 case PHY_INTERFACE_MODE_SGMII: 2674 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2675 case PHY_INTERFACE_MODE_NA: 2676 case PHY_INTERFACE_MODE_1000BASEX: 2677 case PHY_INTERFACE_MODE_2500BASEX: 2678 if (phylink_autoneg_inband(mode)) 2679 return -EINVAL; 2680 2681 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2682 default: 2683 return -EINVAL; 2684 } 2685 2686 return -EINVAL; 2687 } 2688 2689 static int 2690 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2691 const struct phylink_link_state *state) 2692 { 2693 struct mt7530_priv *priv = ds->priv; 2694 2695 return priv->info->mac_port_config(ds, port, mode, state->interface); 2696 } 2697 2698 static struct phylink_pcs * 2699 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2700 phy_interface_t interface) 2701 { 2702 struct mt7530_priv *priv = ds->priv; 2703 2704 switch (interface) { 2705 case PHY_INTERFACE_MODE_TRGMII: 2706 case PHY_INTERFACE_MODE_SGMII: 2707 case PHY_INTERFACE_MODE_1000BASEX: 2708 case PHY_INTERFACE_MODE_2500BASEX: 2709 return &priv->pcs[port].pcs; 2710 2711 default: 2712 return NULL; 2713 } 2714 } 2715 2716 static void 2717 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2718 const struct phylink_link_state *state) 2719 { 2720 struct mt7530_priv *priv = ds->priv; 2721 u32 mcr_cur, mcr_new; 2722 2723 switch (port) { 2724 case 0 ... 4: /* Internal phy */ 2725 if (state->interface != PHY_INTERFACE_MODE_GMII) 2726 goto unsupported; 2727 break; 2728 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2729 if (priv->p5_interface == state->interface) 2730 break; 2731 2732 if (mt753x_mac_config(ds, port, mode, state) < 0) 2733 goto unsupported; 2734 2735 if (priv->p5_intf_sel != P5_DISABLED) 2736 priv->p5_interface = state->interface; 2737 break; 2738 case 6: /* 1st cpu port */ 2739 if (priv->p6_interface == state->interface) 2740 break; 2741 2742 mt753x_pad_setup(ds, state); 2743 2744 if (mt753x_mac_config(ds, port, mode, state) < 0) 2745 goto unsupported; 2746 2747 priv->p6_interface = state->interface; 2748 break; 2749 default: 2750 unsupported: 2751 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2752 __func__, phy_modes(state->interface), port); 2753 return; 2754 } 2755 2756 if (phylink_autoneg_inband(mode) && 2757 state->interface != PHY_INTERFACE_MODE_SGMII) { 2758 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2759 __func__); 2760 return; 2761 } 2762 2763 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2764 mcr_new = mcr_cur; 2765 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2766 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2767 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2768 2769 /* Are we connected to external phy */ 2770 if (port == 5 && dsa_is_user_port(ds, 5)) 2771 mcr_new |= PMCR_EXT_PHY; 2772 2773 if (mcr_new != mcr_cur) 2774 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2775 } 2776 2777 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2778 unsigned int mode, 2779 phy_interface_t interface) 2780 { 2781 struct mt7530_priv *priv = ds->priv; 2782 2783 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2784 } 2785 2786 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2787 unsigned int mode, 2788 phy_interface_t interface, 2789 int speed, int duplex) 2790 { 2791 if (pcs->ops->pcs_link_up) 2792 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2793 } 2794 2795 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2796 unsigned int mode, 2797 phy_interface_t interface, 2798 struct phy_device *phydev, 2799 int speed, int duplex, 2800 bool tx_pause, bool rx_pause) 2801 { 2802 struct mt7530_priv *priv = ds->priv; 2803 u32 mcr; 2804 2805 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2806 2807 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2808 * variants. 2809 */ 2810 if (interface == PHY_INTERFACE_MODE_TRGMII || 2811 (phy_interface_mode_is_8023z(interface))) { 2812 speed = SPEED_1000; 2813 duplex = DUPLEX_FULL; 2814 } 2815 2816 switch (speed) { 2817 case SPEED_1000: 2818 mcr |= PMCR_FORCE_SPEED_1000; 2819 break; 2820 case SPEED_100: 2821 mcr |= PMCR_FORCE_SPEED_100; 2822 break; 2823 } 2824 if (duplex == DUPLEX_FULL) { 2825 mcr |= PMCR_FORCE_FDX; 2826 if (tx_pause) 2827 mcr |= PMCR_TX_FC_EN; 2828 if (rx_pause) 2829 mcr |= PMCR_RX_FC_EN; 2830 } 2831 2832 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2833 switch (speed) { 2834 case SPEED_1000: 2835 mcr |= PMCR_FORCE_EEE1G; 2836 break; 2837 case SPEED_100: 2838 mcr |= PMCR_FORCE_EEE100; 2839 break; 2840 } 2841 } 2842 2843 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2844 } 2845 2846 static int 2847 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2848 { 2849 struct mt7530_priv *priv = ds->priv; 2850 phy_interface_t interface; 2851 int speed; 2852 int ret; 2853 2854 switch (port) { 2855 case 5: 2856 if (mt7531_is_rgmii_port(priv, port)) 2857 interface = PHY_INTERFACE_MODE_RGMII; 2858 else 2859 interface = PHY_INTERFACE_MODE_2500BASEX; 2860 2861 priv->p5_interface = interface; 2862 break; 2863 case 6: 2864 interface = PHY_INTERFACE_MODE_2500BASEX; 2865 2866 mt7531_pad_setup(ds, interface); 2867 2868 priv->p6_interface = interface; 2869 break; 2870 default: 2871 return -EINVAL; 2872 } 2873 2874 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2875 speed = SPEED_2500; 2876 else 2877 speed = SPEED_1000; 2878 2879 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2880 if (ret) 2881 return ret; 2882 mt7530_write(priv, MT7530_PMCR_P(port), 2883 PMCR_CPU_PORT_SETTING(priv->id)); 2884 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2885 interface, speed, DUPLEX_FULL); 2886 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2887 speed, DUPLEX_FULL, true, true); 2888 2889 return 0; 2890 } 2891 2892 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2893 struct phylink_config *config) 2894 { 2895 struct mt7530_priv *priv = ds->priv; 2896 2897 /* This switch only supports full-duplex at 1Gbps */ 2898 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2899 MAC_10 | MAC_100 | MAC_1000FD; 2900 2901 /* This driver does not make use of the speed, duplex, pause or the 2902 * advertisement in its mac_config, so it is safe to mark this driver 2903 * as non-legacy. 2904 */ 2905 config->legacy_pre_march2020 = false; 2906 2907 priv->info->mac_port_get_caps(ds, port, config); 2908 } 2909 2910 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2911 unsigned long *supported, 2912 const struct phylink_link_state *state) 2913 { 2914 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2915 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2916 phy_interface_mode_is_8023z(state->interface)) 2917 phylink_clear(supported, Autoneg); 2918 2919 return 0; 2920 } 2921 2922 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2923 struct phylink_link_state *state) 2924 { 2925 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2926 int port = pcs_to_mt753x_pcs(pcs)->port; 2927 u32 pmsr; 2928 2929 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2930 2931 state->link = (pmsr & PMSR_LINK); 2932 state->an_complete = state->link; 2933 state->duplex = !!(pmsr & PMSR_DPX); 2934 2935 switch (pmsr & PMSR_SPEED_MASK) { 2936 case PMSR_SPEED_10: 2937 state->speed = SPEED_10; 2938 break; 2939 case PMSR_SPEED_100: 2940 state->speed = SPEED_100; 2941 break; 2942 case PMSR_SPEED_1000: 2943 state->speed = SPEED_1000; 2944 break; 2945 default: 2946 state->speed = SPEED_UNKNOWN; 2947 break; 2948 } 2949 2950 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2951 if (pmsr & PMSR_RX_FC) 2952 state->pause |= MLO_PAUSE_RX; 2953 if (pmsr & PMSR_TX_FC) 2954 state->pause |= MLO_PAUSE_TX; 2955 } 2956 2957 static int 2958 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2959 struct phylink_link_state *state) 2960 { 2961 u32 status, val; 2962 u16 config_reg; 2963 2964 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2965 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2966 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2967 (status & MT7531_SGMII_AN_ENABLE)) { 2968 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2969 config_reg = val >> 16; 2970 2971 switch (config_reg & LPA_SGMII_SPD_MASK) { 2972 case LPA_SGMII_1000: 2973 state->speed = SPEED_1000; 2974 break; 2975 case LPA_SGMII_100: 2976 state->speed = SPEED_100; 2977 break; 2978 case LPA_SGMII_10: 2979 state->speed = SPEED_10; 2980 break; 2981 default: 2982 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2983 state->link = false; 2984 return -EINVAL; 2985 } 2986 2987 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2988 state->duplex = DUPLEX_FULL; 2989 else 2990 state->duplex = DUPLEX_HALF; 2991 } 2992 2993 return 0; 2994 } 2995 2996 static void mt7531_pcs_get_state(struct phylink_pcs *pcs, 2997 struct phylink_link_state *state) 2998 { 2999 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3000 int port = pcs_to_mt753x_pcs(pcs)->port; 3001 3002 if (state->interface == PHY_INTERFACE_MODE_SGMII) 3003 mt7531_sgmii_pcs_get_state_an(priv, port, state); 3004 else 3005 state->link = false; 3006 } 3007 3008 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3009 phy_interface_t interface, 3010 const unsigned long *advertising, 3011 bool permit_pause_to_mac) 3012 { 3013 return 0; 3014 } 3015 3016 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3017 { 3018 } 3019 3020 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3021 .pcs_validate = mt753x_pcs_validate, 3022 .pcs_get_state = mt7530_pcs_get_state, 3023 .pcs_config = mt753x_pcs_config, 3024 .pcs_an_restart = mt7530_pcs_an_restart, 3025 }; 3026 3027 static const struct phylink_pcs_ops mt7531_pcs_ops = { 3028 .pcs_validate = mt753x_pcs_validate, 3029 .pcs_get_state = mt7531_pcs_get_state, 3030 .pcs_config = mt753x_pcs_config, 3031 .pcs_an_restart = mt7531_pcs_an_restart, 3032 .pcs_link_up = mt7531_pcs_link_up, 3033 }; 3034 3035 static int 3036 mt753x_setup(struct dsa_switch *ds) 3037 { 3038 struct mt7530_priv *priv = ds->priv; 3039 int i, ret; 3040 3041 /* Initialise the PCS devices */ 3042 for (i = 0; i < priv->ds->num_ports; i++) { 3043 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3044 priv->pcs[i].priv = priv; 3045 priv->pcs[i].port = i; 3046 } 3047 3048 ret = priv->info->sw_setup(ds); 3049 if (ret) 3050 return ret; 3051 3052 ret = mt7530_setup_irq(priv); 3053 if (ret) 3054 return ret; 3055 3056 ret = mt7530_setup_mdio(priv); 3057 if (ret && priv->irq) 3058 mt7530_free_irq_common(priv); 3059 3060 return ret; 3061 } 3062 3063 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3064 struct ethtool_eee *e) 3065 { 3066 struct mt7530_priv *priv = ds->priv; 3067 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3068 3069 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3070 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3071 3072 return 0; 3073 } 3074 3075 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3076 struct ethtool_eee *e) 3077 { 3078 struct mt7530_priv *priv = ds->priv; 3079 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3080 3081 if (e->tx_lpi_timer > 0xFFF) 3082 return -EINVAL; 3083 3084 set = SET_LPI_THRESH(e->tx_lpi_timer); 3085 if (!e->tx_lpi_enabled) 3086 /* Force LPI Mode without a delay */ 3087 set |= LPI_MODE_EN; 3088 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3089 3090 return 0; 3091 } 3092 3093 static const struct dsa_switch_ops mt7530_switch_ops = { 3094 .get_tag_protocol = mtk_get_tag_protocol, 3095 .setup = mt753x_setup, 3096 .get_strings = mt7530_get_strings, 3097 .get_ethtool_stats = mt7530_get_ethtool_stats, 3098 .get_sset_count = mt7530_get_sset_count, 3099 .set_ageing_time = mt7530_set_ageing_time, 3100 .port_enable = mt7530_port_enable, 3101 .port_disable = mt7530_port_disable, 3102 .port_change_mtu = mt7530_port_change_mtu, 3103 .port_max_mtu = mt7530_port_max_mtu, 3104 .port_stp_state_set = mt7530_stp_state_set, 3105 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3106 .port_bridge_flags = mt7530_port_bridge_flags, 3107 .port_bridge_join = mt7530_port_bridge_join, 3108 .port_bridge_leave = mt7530_port_bridge_leave, 3109 .port_fdb_add = mt7530_port_fdb_add, 3110 .port_fdb_del = mt7530_port_fdb_del, 3111 .port_fdb_dump = mt7530_port_fdb_dump, 3112 .port_mdb_add = mt7530_port_mdb_add, 3113 .port_mdb_del = mt7530_port_mdb_del, 3114 .port_vlan_filtering = mt7530_port_vlan_filtering, 3115 .port_vlan_add = mt7530_port_vlan_add, 3116 .port_vlan_del = mt7530_port_vlan_del, 3117 .port_mirror_add = mt753x_port_mirror_add, 3118 .port_mirror_del = mt753x_port_mirror_del, 3119 .phylink_get_caps = mt753x_phylink_get_caps, 3120 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3121 .phylink_mac_config = mt753x_phylink_mac_config, 3122 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3123 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3124 .get_mac_eee = mt753x_get_mac_eee, 3125 .set_mac_eee = mt753x_set_mac_eee, 3126 }; 3127 3128 static const struct mt753x_info mt753x_table[] = { 3129 [ID_MT7621] = { 3130 .id = ID_MT7621, 3131 .pcs_ops = &mt7530_pcs_ops, 3132 .sw_setup = mt7530_setup, 3133 .phy_read = mt7530_phy_read, 3134 .phy_write = mt7530_phy_write, 3135 .pad_setup = mt7530_pad_clk_setup, 3136 .mac_port_get_caps = mt7530_mac_port_get_caps, 3137 .mac_port_config = mt7530_mac_config, 3138 }, 3139 [ID_MT7530] = { 3140 .id = ID_MT7530, 3141 .pcs_ops = &mt7530_pcs_ops, 3142 .sw_setup = mt7530_setup, 3143 .phy_read = mt7530_phy_read, 3144 .phy_write = mt7530_phy_write, 3145 .pad_setup = mt7530_pad_clk_setup, 3146 .mac_port_get_caps = mt7530_mac_port_get_caps, 3147 .mac_port_config = mt7530_mac_config, 3148 }, 3149 [ID_MT7531] = { 3150 .id = ID_MT7531, 3151 .pcs_ops = &mt7531_pcs_ops, 3152 .sw_setup = mt7531_setup, 3153 .phy_read = mt7531_ind_phy_read, 3154 .phy_write = mt7531_ind_phy_write, 3155 .pad_setup = mt7531_pad_setup, 3156 .cpu_port_config = mt7531_cpu_port_config, 3157 .mac_port_get_caps = mt7531_mac_port_get_caps, 3158 .mac_port_config = mt7531_mac_config, 3159 }, 3160 }; 3161 3162 static const struct of_device_id mt7530_of_match[] = { 3163 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3164 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3165 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3166 { /* sentinel */ }, 3167 }; 3168 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3169 3170 static int 3171 mt7530_probe(struct mdio_device *mdiodev) 3172 { 3173 struct mt7530_priv *priv; 3174 struct device_node *dn; 3175 3176 dn = mdiodev->dev.of_node; 3177 3178 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3179 if (!priv) 3180 return -ENOMEM; 3181 3182 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3183 if (!priv->ds) 3184 return -ENOMEM; 3185 3186 priv->ds->dev = &mdiodev->dev; 3187 priv->ds->num_ports = MT7530_NUM_PORTS; 3188 3189 /* Use medatek,mcm property to distinguish hardware type that would 3190 * casues a little bit differences on power-on sequence. 3191 */ 3192 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3193 if (priv->mcm) { 3194 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3195 3196 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3197 if (IS_ERR(priv->rstc)) { 3198 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3199 return PTR_ERR(priv->rstc); 3200 } 3201 } 3202 3203 /* Get the hardware identifier from the devicetree node. 3204 * We will need it for some of the clock and regulator setup. 3205 */ 3206 priv->info = of_device_get_match_data(&mdiodev->dev); 3207 if (!priv->info) 3208 return -EINVAL; 3209 3210 /* Sanity check if these required device operations are filled 3211 * properly. 3212 */ 3213 if (!priv->info->sw_setup || !priv->info->pad_setup || 3214 !priv->info->phy_read || !priv->info->phy_write || 3215 !priv->info->mac_port_get_caps || 3216 !priv->info->mac_port_config) 3217 return -EINVAL; 3218 3219 priv->id = priv->info->id; 3220 3221 if (priv->id == ID_MT7530) { 3222 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3223 if (IS_ERR(priv->core_pwr)) 3224 return PTR_ERR(priv->core_pwr); 3225 3226 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3227 if (IS_ERR(priv->io_pwr)) 3228 return PTR_ERR(priv->io_pwr); 3229 } 3230 3231 /* Not MCM that indicates switch works as the remote standalone 3232 * integrated circuit so the GPIO pin would be used to complete 3233 * the reset, otherwise memory-mapped register accessing used 3234 * through syscon provides in the case of MCM. 3235 */ 3236 if (!priv->mcm) { 3237 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3238 GPIOD_OUT_LOW); 3239 if (IS_ERR(priv->reset)) { 3240 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3241 return PTR_ERR(priv->reset); 3242 } 3243 } 3244 3245 priv->bus = mdiodev->bus; 3246 priv->dev = &mdiodev->dev; 3247 priv->ds->priv = priv; 3248 priv->ds->ops = &mt7530_switch_ops; 3249 mutex_init(&priv->reg_mutex); 3250 dev_set_drvdata(&mdiodev->dev, priv); 3251 3252 return dsa_register_switch(priv->ds); 3253 } 3254 3255 static void 3256 mt7530_remove(struct mdio_device *mdiodev) 3257 { 3258 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3259 int ret = 0; 3260 3261 if (!priv) 3262 return; 3263 3264 ret = regulator_disable(priv->core_pwr); 3265 if (ret < 0) 3266 dev_err(priv->dev, 3267 "Failed to disable core power: %d\n", ret); 3268 3269 ret = regulator_disable(priv->io_pwr); 3270 if (ret < 0) 3271 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3272 ret); 3273 3274 if (priv->irq) 3275 mt7530_free_irq(priv); 3276 3277 dsa_unregister_switch(priv->ds); 3278 mutex_destroy(&priv->reg_mutex); 3279 3280 dev_set_drvdata(&mdiodev->dev, NULL); 3281 } 3282 3283 static void mt7530_shutdown(struct mdio_device *mdiodev) 3284 { 3285 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3286 3287 if (!priv) 3288 return; 3289 3290 dsa_switch_shutdown(priv->ds); 3291 3292 dev_set_drvdata(&mdiodev->dev, NULL); 3293 } 3294 3295 static struct mdio_driver mt7530_mdio_driver = { 3296 .probe = mt7530_probe, 3297 .remove = mt7530_remove, 3298 .shutdown = mt7530_shutdown, 3299 .mdiodrv.driver = { 3300 .name = "mt7530", 3301 .of_match_table = mt7530_of_match, 3302 }, 3303 }; 3304 3305 mdio_module_driver(mt7530_mdio_driver); 3306 3307 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3308 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3309 MODULE_LICENSE("GPL"); 3310