1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 #include <net/pkt_cls.h> 25 26 #include "mt7530.h" 27 28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 29 { 30 return container_of(pcs, struct mt753x_pcs, pcs); 31 } 32 33 /* String, offset, and register size in bytes if different from 4 bytes */ 34 static const struct mt7530_mib_desc mt7530_mib[] = { 35 MIB_DESC(1, 0x00, "TxDrop"), 36 MIB_DESC(1, 0x04, "TxCrcErr"), 37 MIB_DESC(1, 0x08, "TxUnicast"), 38 MIB_DESC(1, 0x0c, "TxMulticast"), 39 MIB_DESC(1, 0x10, "TxBroadcast"), 40 MIB_DESC(1, 0x14, "TxCollision"), 41 MIB_DESC(1, 0x18, "TxSingleCollision"), 42 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 43 MIB_DESC(1, 0x20, "TxDeferred"), 44 MIB_DESC(1, 0x24, "TxLateCollision"), 45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 46 MIB_DESC(1, 0x2c, "TxPause"), 47 MIB_DESC(1, 0x30, "TxPktSz64"), 48 MIB_DESC(1, 0x34, "TxPktSz65To127"), 49 MIB_DESC(1, 0x38, "TxPktSz128To255"), 50 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 51 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 52 MIB_DESC(1, 0x44, "Tx1024ToMax"), 53 MIB_DESC(2, 0x48, "TxBytes"), 54 MIB_DESC(1, 0x60, "RxDrop"), 55 MIB_DESC(1, 0x64, "RxFiltering"), 56 MIB_DESC(1, 0x68, "RxUnicast"), 57 MIB_DESC(1, 0x6c, "RxMulticast"), 58 MIB_DESC(1, 0x70, "RxBroadcast"), 59 MIB_DESC(1, 0x74, "RxAlignErr"), 60 MIB_DESC(1, 0x78, "RxCrcErr"), 61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 62 MIB_DESC(1, 0x80, "RxFragErr"), 63 MIB_DESC(1, 0x84, "RxOverSzErr"), 64 MIB_DESC(1, 0x88, "RxJabberErr"), 65 MIB_DESC(1, 0x8c, "RxPause"), 66 MIB_DESC(1, 0x90, "RxPktSz64"), 67 MIB_DESC(1, 0x94, "RxPktSz65To127"), 68 MIB_DESC(1, 0x98, "RxPktSz128To255"), 69 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 72 MIB_DESC(2, 0xa8, "RxBytes"), 73 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 74 MIB_DESC(1, 0xb4, "RxIngressDrop"), 75 MIB_DESC(1, 0xb8, "RxArlDrop"), 76 }; 77 78 static void 79 mt7530_mutex_lock(struct mt7530_priv *priv) 80 { 81 if (priv->bus) 82 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 83 } 84 85 static void 86 mt7530_mutex_unlock(struct mt7530_priv *priv) 87 { 88 if (priv->bus) 89 mutex_unlock(&priv->bus->mdio_lock); 90 } 91 92 static void 93 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 94 { 95 struct mii_bus *bus = priv->bus; 96 int ret; 97 98 mt7530_mutex_lock(priv); 99 100 /* Write the desired MMD Devad */ 101 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 102 MII_MMD_CTRL, MDIO_MMD_VEND2); 103 if (ret < 0) 104 goto err; 105 106 /* Write the desired MMD register address */ 107 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 108 MII_MMD_DATA, reg); 109 if (ret < 0) 110 goto err; 111 112 /* Select the Function : DATA with no post increment */ 113 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 114 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 115 if (ret < 0) 116 goto err; 117 118 /* Write the data into MMD's selected register */ 119 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 120 MII_MMD_DATA, val); 121 err: 122 if (ret < 0) 123 dev_err(&bus->dev, "failed to write mmd register\n"); 124 125 mt7530_mutex_unlock(priv); 126 } 127 128 static void 129 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 130 { 131 struct mii_bus *bus = priv->bus; 132 u32 val; 133 int ret; 134 135 mt7530_mutex_lock(priv); 136 137 /* Write the desired MMD Devad */ 138 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 139 MII_MMD_CTRL, MDIO_MMD_VEND2); 140 if (ret < 0) 141 goto err; 142 143 /* Write the desired MMD register address */ 144 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 145 MII_MMD_DATA, reg); 146 if (ret < 0) 147 goto err; 148 149 /* Select the Function : DATA with no post increment */ 150 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 151 MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR); 152 if (ret < 0) 153 goto err; 154 155 /* Read the content of the MMD's selected register */ 156 val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 157 MII_MMD_DATA); 158 val &= ~mask; 159 val |= set; 160 /* Write the data into MMD's selected register */ 161 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 162 MII_MMD_DATA, val); 163 err: 164 if (ret < 0) 165 dev_err(&bus->dev, "failed to write mmd register\n"); 166 167 mt7530_mutex_unlock(priv); 168 } 169 170 static void 171 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 172 { 173 core_rmw(priv, reg, 0, val); 174 } 175 176 static void 177 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 178 { 179 core_rmw(priv, reg, val, 0); 180 } 181 182 static int 183 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 184 { 185 int ret; 186 187 ret = regmap_write(priv->regmap, reg, val); 188 189 if (ret < 0) 190 dev_err(priv->dev, 191 "failed to write mt7530 register\n"); 192 193 return ret; 194 } 195 196 static u32 197 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 198 { 199 int ret; 200 u32 val; 201 202 ret = regmap_read(priv->regmap, reg, &val); 203 if (ret) { 204 WARN_ON_ONCE(1); 205 dev_err(priv->dev, 206 "failed to read mt7530 register\n"); 207 return 0; 208 } 209 210 return val; 211 } 212 213 static void 214 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 215 { 216 mt7530_mutex_lock(priv); 217 218 mt7530_mii_write(priv, reg, val); 219 220 mt7530_mutex_unlock(priv); 221 } 222 223 static u32 224 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 225 { 226 return mt7530_mii_read(p->priv, p->reg); 227 } 228 229 static u32 230 _mt7530_read(struct mt7530_dummy_poll *p) 231 { 232 u32 val; 233 234 mt7530_mutex_lock(p->priv); 235 236 val = mt7530_mii_read(p->priv, p->reg); 237 238 mt7530_mutex_unlock(p->priv); 239 240 return val; 241 } 242 243 static u32 244 mt7530_read(struct mt7530_priv *priv, u32 reg) 245 { 246 struct mt7530_dummy_poll p; 247 248 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 249 return _mt7530_read(&p); 250 } 251 252 static void 253 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 254 u32 mask, u32 set) 255 { 256 mt7530_mutex_lock(priv); 257 258 regmap_update_bits(priv->regmap, reg, mask, set); 259 260 mt7530_mutex_unlock(priv); 261 } 262 263 static void 264 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 265 { 266 mt7530_rmw(priv, reg, val, val); 267 } 268 269 static void 270 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 271 { 272 mt7530_rmw(priv, reg, val, 0); 273 } 274 275 static int 276 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 277 { 278 u32 val; 279 int ret; 280 struct mt7530_dummy_poll p; 281 282 /* Set the command operating upon the MAC address entries */ 283 val = ATC_BUSY | ATC_MAT(0) | cmd; 284 mt7530_write(priv, MT7530_ATC, val); 285 286 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 287 ret = readx_poll_timeout(_mt7530_read, &p, val, 288 !(val & ATC_BUSY), 20, 20000); 289 if (ret < 0) { 290 dev_err(priv->dev, "reset timeout\n"); 291 return ret; 292 } 293 294 /* Additional sanity for read command if the specified 295 * entry is invalid 296 */ 297 val = mt7530_read(priv, MT7530_ATC); 298 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 299 return -EINVAL; 300 301 if (rsp) 302 *rsp = val; 303 304 return 0; 305 } 306 307 static void 308 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 309 { 310 u32 reg[3]; 311 int i; 312 313 /* Read from ARL table into an array */ 314 for (i = 0; i < 3; i++) { 315 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 316 317 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 318 __func__, __LINE__, i, reg[i]); 319 } 320 321 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 322 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 323 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 324 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 325 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 326 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 327 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 328 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 329 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 330 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 331 } 332 333 static void 334 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 335 u8 port_mask, const u8 *mac, 336 u8 aging, u8 type) 337 { 338 u32 reg[3] = { 0 }; 339 int i; 340 341 reg[1] |= vid & CVID_MASK; 342 reg[1] |= ATA2_IVL; 343 reg[1] |= ATA2_FID(FID_BRIDGED); 344 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 345 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 346 /* STATIC_ENT indicate that entry is static wouldn't 347 * be aged out and STATIC_EMP specified as erasing an 348 * entry 349 */ 350 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 351 reg[1] |= mac[5] << MAC_BYTE_5; 352 reg[1] |= mac[4] << MAC_BYTE_4; 353 reg[0] |= mac[3] << MAC_BYTE_3; 354 reg[0] |= mac[2] << MAC_BYTE_2; 355 reg[0] |= mac[1] << MAC_BYTE_1; 356 reg[0] |= mac[0] << MAC_BYTE_0; 357 358 /* Write array into the ARL table */ 359 for (i = 0; i < 3; i++) 360 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 361 } 362 363 /* Set up switch core clock for MT7530 */ 364 static void mt7530_pll_setup(struct mt7530_priv *priv) 365 { 366 /* Disable core clock */ 367 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 368 369 /* Disable PLL */ 370 core_write(priv, CORE_GSWPLL_GRP1, 0); 371 372 /* Set core clock into 500Mhz */ 373 core_write(priv, CORE_GSWPLL_GRP2, 374 RG_GSWPLL_POSDIV_500M(1) | 375 RG_GSWPLL_FBKDIV_500M(25)); 376 377 /* Enable PLL */ 378 core_write(priv, CORE_GSWPLL_GRP1, 379 RG_GSWPLL_EN_PRE | 380 RG_GSWPLL_POSDIV_200M(2) | 381 RG_GSWPLL_FBKDIV_200M(32)); 382 383 udelay(20); 384 385 /* Enable core clock */ 386 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 387 } 388 389 /* If port 6 is available as a CPU port, always prefer that as the default, 390 * otherwise don't care. 391 */ 392 static struct dsa_port * 393 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 394 { 395 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 396 397 if (dsa_port_is_cpu(cpu_dp)) 398 return cpu_dp; 399 400 return NULL; 401 } 402 403 /* Setup port 6 interface mode and TRGMII TX circuit */ 404 static void 405 mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) 406 { 407 struct mt7530_priv *priv = ds->priv; 408 u32 ncpo1, ssc_delta, xtal; 409 410 /* Disable the MT7530 TRGMII clocks */ 411 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 412 413 if (interface == PHY_INTERFACE_MODE_RGMII) { 414 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 415 P6_INTF_MODE(0)); 416 return; 417 } 418 419 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); 420 421 xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK; 422 423 if (xtal == MT7530_XTAL_25MHZ) 424 ssc_delta = 0x57; 425 else 426 ssc_delta = 0x87; 427 428 if (priv->id == ID_MT7621) { 429 /* PLL frequency: 125MHz: 1.0GBit */ 430 if (xtal == MT7530_XTAL_40MHZ) 431 ncpo1 = 0x0640; 432 if (xtal == MT7530_XTAL_25MHZ) 433 ncpo1 = 0x0a00; 434 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 435 if (xtal == MT7530_XTAL_40MHZ) 436 ncpo1 = 0x0c80; 437 if (xtal == MT7530_XTAL_25MHZ) 438 ncpo1 = 0x1400; 439 } 440 441 /* Setup the MT7530 TRGMII Tx Clock */ 442 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 443 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 444 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 445 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 446 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | 447 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); 448 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | 449 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); 450 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | 451 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 452 453 /* Enable the MT7530 TRGMII clocks */ 454 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 455 } 456 457 static void 458 mt7531_pll_setup(struct mt7530_priv *priv) 459 { 460 enum mt7531_xtal_fsel xtal; 461 u32 top_sig; 462 u32 hwstrap; 463 u32 val; 464 465 val = mt7530_read(priv, MT7531_CREV); 466 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 467 hwstrap = mt7530_read(priv, MT753X_TRAP); 468 if ((val & CHIP_REV_M) > 0) 469 xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ : 470 MT7531_XTAL_FSEL_25MHZ; 471 else 472 xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ : 473 MT7531_XTAL_FSEL_40MHZ; 474 475 /* Step 1 : Disable MT7531 COREPLL */ 476 val = mt7530_read(priv, MT7531_PLLGP_EN); 477 val &= ~EN_COREPLL; 478 mt7530_write(priv, MT7531_PLLGP_EN, val); 479 480 /* Step 2: switch to XTAL output */ 481 val = mt7530_read(priv, MT7531_PLLGP_EN); 482 val |= SW_CLKSW; 483 mt7530_write(priv, MT7531_PLLGP_EN, val); 484 485 val = mt7530_read(priv, MT7531_PLLGP_CR0); 486 val &= ~RG_COREPLL_EN; 487 mt7530_write(priv, MT7531_PLLGP_CR0, val); 488 489 /* Step 3: disable PLLGP and enable program PLLGP */ 490 val = mt7530_read(priv, MT7531_PLLGP_EN); 491 val |= SW_PLLGP; 492 mt7530_write(priv, MT7531_PLLGP_EN, val); 493 494 /* Step 4: program COREPLL output frequency to 500MHz */ 495 val = mt7530_read(priv, MT7531_PLLGP_CR0); 496 val &= ~RG_COREPLL_POSDIV_M; 497 val |= 2 << RG_COREPLL_POSDIV_S; 498 mt7530_write(priv, MT7531_PLLGP_CR0, val); 499 usleep_range(25, 35); 500 501 switch (xtal) { 502 case MT7531_XTAL_FSEL_25MHZ: 503 val = mt7530_read(priv, MT7531_PLLGP_CR0); 504 val &= ~RG_COREPLL_SDM_PCW_M; 505 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 506 mt7530_write(priv, MT7531_PLLGP_CR0, val); 507 break; 508 case MT7531_XTAL_FSEL_40MHZ: 509 val = mt7530_read(priv, MT7531_PLLGP_CR0); 510 val &= ~RG_COREPLL_SDM_PCW_M; 511 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 512 mt7530_write(priv, MT7531_PLLGP_CR0, val); 513 break; 514 } 515 516 /* Set feedback divide ratio update signal to high */ 517 val = mt7530_read(priv, MT7531_PLLGP_CR0); 518 val |= RG_COREPLL_SDM_PCW_CHG; 519 mt7530_write(priv, MT7531_PLLGP_CR0, val); 520 /* Wait for at least 16 XTAL clocks */ 521 usleep_range(10, 20); 522 523 /* Step 5: set feedback divide ratio update signal to low */ 524 val = mt7530_read(priv, MT7531_PLLGP_CR0); 525 val &= ~RG_COREPLL_SDM_PCW_CHG; 526 mt7530_write(priv, MT7531_PLLGP_CR0, val); 527 528 /* Enable 325M clock for SGMII */ 529 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 530 531 /* Enable 250SSC clock for RGMII */ 532 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 533 534 /* Step 6: Enable MT7531 PLL */ 535 val = mt7530_read(priv, MT7531_PLLGP_CR0); 536 val |= RG_COREPLL_EN; 537 mt7530_write(priv, MT7531_PLLGP_CR0, val); 538 539 val = mt7530_read(priv, MT7531_PLLGP_EN); 540 val |= EN_COREPLL; 541 mt7530_write(priv, MT7531_PLLGP_EN, val); 542 usleep_range(25, 35); 543 } 544 545 static void 546 mt7530_mib_reset(struct dsa_switch *ds) 547 { 548 struct mt7530_priv *priv = ds->priv; 549 550 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 551 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 552 } 553 554 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 555 { 556 return mdiobus_read_nested(priv->bus, port, regnum); 557 } 558 559 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 560 u16 val) 561 { 562 return mdiobus_write_nested(priv->bus, port, regnum, val); 563 } 564 565 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 566 int devad, int regnum) 567 { 568 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 569 } 570 571 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 572 int regnum, u16 val) 573 { 574 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 575 } 576 577 static int 578 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 579 int regnum) 580 { 581 struct mt7530_dummy_poll p; 582 u32 reg, val; 583 int ret; 584 585 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 586 587 mt7530_mutex_lock(priv); 588 589 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 590 !(val & MT7531_PHY_ACS_ST), 20, 100000); 591 if (ret < 0) { 592 dev_err(priv->dev, "poll timeout\n"); 593 goto out; 594 } 595 596 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 597 MT7531_MDIO_DEV_ADDR(devad) | regnum; 598 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 599 600 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 601 !(val & MT7531_PHY_ACS_ST), 20, 100000); 602 if (ret < 0) { 603 dev_err(priv->dev, "poll timeout\n"); 604 goto out; 605 } 606 607 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 608 MT7531_MDIO_DEV_ADDR(devad); 609 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 610 611 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 612 !(val & MT7531_PHY_ACS_ST), 20, 100000); 613 if (ret < 0) { 614 dev_err(priv->dev, "poll timeout\n"); 615 goto out; 616 } 617 618 ret = val & MT7531_MDIO_RW_DATA_MASK; 619 out: 620 mt7530_mutex_unlock(priv); 621 622 return ret; 623 } 624 625 static int 626 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 627 int regnum, u16 data) 628 { 629 struct mt7530_dummy_poll p; 630 u32 val, reg; 631 int ret; 632 633 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 634 635 mt7530_mutex_lock(priv); 636 637 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 638 !(val & MT7531_PHY_ACS_ST), 20, 100000); 639 if (ret < 0) { 640 dev_err(priv->dev, "poll timeout\n"); 641 goto out; 642 } 643 644 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 645 MT7531_MDIO_DEV_ADDR(devad) | regnum; 646 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 647 648 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 649 !(val & MT7531_PHY_ACS_ST), 20, 100000); 650 if (ret < 0) { 651 dev_err(priv->dev, "poll timeout\n"); 652 goto out; 653 } 654 655 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 656 MT7531_MDIO_DEV_ADDR(devad) | data; 657 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 658 659 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 660 !(val & MT7531_PHY_ACS_ST), 20, 100000); 661 if (ret < 0) { 662 dev_err(priv->dev, "poll timeout\n"); 663 goto out; 664 } 665 666 out: 667 mt7530_mutex_unlock(priv); 668 669 return ret; 670 } 671 672 static int 673 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 674 { 675 struct mt7530_dummy_poll p; 676 int ret; 677 u32 val; 678 679 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 680 681 mt7530_mutex_lock(priv); 682 683 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 684 !(val & MT7531_PHY_ACS_ST), 20, 100000); 685 if (ret < 0) { 686 dev_err(priv->dev, "poll timeout\n"); 687 goto out; 688 } 689 690 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 691 MT7531_MDIO_REG_ADDR(regnum); 692 693 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 ret = val & MT7531_MDIO_RW_DATA_MASK; 703 out: 704 mt7530_mutex_unlock(priv); 705 706 return ret; 707 } 708 709 static int 710 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 711 u16 data) 712 { 713 struct mt7530_dummy_poll p; 714 int ret; 715 u32 reg; 716 717 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 718 719 mt7530_mutex_lock(priv); 720 721 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 722 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 723 if (ret < 0) { 724 dev_err(priv->dev, "poll timeout\n"); 725 goto out; 726 } 727 728 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 729 MT7531_MDIO_REG_ADDR(regnum) | data; 730 731 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 734 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 out: 741 mt7530_mutex_unlock(priv); 742 743 return ret; 744 } 745 746 static int 747 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 748 { 749 struct mt7530_priv *priv = bus->priv; 750 751 return priv->info->phy_read_c22(priv, port, regnum); 752 } 753 754 static int 755 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 756 { 757 struct mt7530_priv *priv = bus->priv; 758 759 return priv->info->phy_read_c45(priv, port, devad, regnum); 760 } 761 762 static int 763 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 764 { 765 struct mt7530_priv *priv = bus->priv; 766 767 return priv->info->phy_write_c22(priv, port, regnum, val); 768 } 769 770 static int 771 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 772 u16 val) 773 { 774 struct mt7530_priv *priv = bus->priv; 775 776 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 777 } 778 779 static void 780 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 781 uint8_t *data) 782 { 783 int i; 784 785 if (stringset != ETH_SS_STATS) 786 return; 787 788 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 789 ethtool_puts(&data, mt7530_mib[i].name); 790 } 791 792 static void 793 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 794 uint64_t *data) 795 { 796 struct mt7530_priv *priv = ds->priv; 797 const struct mt7530_mib_desc *mib; 798 u32 reg, i; 799 u64 hi; 800 801 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 802 mib = &mt7530_mib[i]; 803 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 804 805 data[i] = mt7530_read(priv, reg); 806 if (mib->size == 2) { 807 hi = mt7530_read(priv, reg + 4); 808 data[i] |= hi << 32; 809 } 810 } 811 } 812 813 static int 814 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 815 { 816 if (sset != ETH_SS_STATS) 817 return 0; 818 819 return ARRAY_SIZE(mt7530_mib); 820 } 821 822 static int 823 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 824 { 825 struct mt7530_priv *priv = ds->priv; 826 unsigned int secs = msecs / 1000; 827 unsigned int tmp_age_count; 828 unsigned int error = -1; 829 unsigned int age_count; 830 unsigned int age_unit; 831 832 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 833 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 834 return -ERANGE; 835 836 /* iterate through all possible age_count to find the closest pair */ 837 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 838 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 839 840 if (tmp_age_unit <= AGE_UNIT_MAX) { 841 unsigned int tmp_error = secs - 842 (tmp_age_count + 1) * (tmp_age_unit + 1); 843 844 /* found a closer pair */ 845 if (error > tmp_error) { 846 error = tmp_error; 847 age_count = tmp_age_count; 848 age_unit = tmp_age_unit; 849 } 850 851 /* found the exact match, so break the loop */ 852 if (!error) 853 break; 854 } 855 } 856 857 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 858 859 return 0; 860 } 861 862 static const char *mt7530_p5_mode_str(unsigned int mode) 863 { 864 switch (mode) { 865 case MUX_PHY_P0: 866 return "MUX PHY P0"; 867 case MUX_PHY_P4: 868 return "MUX PHY P4"; 869 default: 870 return "GMAC5"; 871 } 872 } 873 874 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 875 { 876 struct mt7530_priv *priv = ds->priv; 877 u8 tx_delay = 0; 878 int val; 879 880 mutex_lock(&priv->reg_mutex); 881 882 val = mt7530_read(priv, MT753X_MTRAP); 883 884 val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE; 885 886 switch (priv->p5_mode) { 887 /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ 888 case MUX_PHY_P0: 889 val |= MT7530_P5_PHY0_SEL; 890 fallthrough; 891 892 /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ 893 case MUX_PHY_P4: 894 /* Setup the MAC by default for the cpu port */ 895 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300); 896 break; 897 898 /* GMAC5: P5 -> SoC MAC or external PHY */ 899 default: 900 val |= MT7530_P5_MAC_SEL; 901 break; 902 } 903 904 /* Setup RGMII settings */ 905 if (phy_interface_mode_is_rgmii(interface)) { 906 val |= MT7530_P5_RGMII_MODE; 907 908 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 909 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 910 911 /* Don't set delay in DSA mode */ 912 if (!dsa_is_dsa_port(priv->ds, 5) && 913 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 914 interface == PHY_INTERFACE_MODE_RGMII_ID)) 915 tx_delay = 4; /* n * 0.5 ns */ 916 917 /* P5 RGMII TX Clock Control: delay x */ 918 mt7530_write(priv, MT7530_P5RGMIITXCR, 919 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 920 921 /* reduce P5 RGMII Tx driving, 8mA */ 922 mt7530_write(priv, MT7530_IO_DRV_CR, 923 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 924 } 925 926 mt7530_write(priv, MT753X_MTRAP, val); 927 928 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, 929 mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); 930 931 mutex_unlock(&priv->reg_mutex); 932 } 933 934 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) 935 * of the Open Systems Interconnection basic reference model (OSI/RM) are 936 * described; the medium access control (MAC) and logical link control (LLC) 937 * sublayers. The MAC sublayer is the one facing the physical layer. 938 * 939 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A 940 * Bridge component comprises a MAC Relay Entity for interconnecting the Ports 941 * of the Bridge, at least two Ports, and higher layer entities with at least a 942 * Spanning Tree Protocol Entity included. 943 * 944 * Each Bridge Port also functions as an end station and shall provide the MAC 945 * Service to an LLC Entity. Each instance of the MAC Service is provided to a 946 * distinct LLC Entity that supports protocol identification, multiplexing, and 947 * demultiplexing, for protocol data unit (PDU) transmission and reception by 948 * one or more higher layer entities. 949 * 950 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC 951 * Entity associated with each Bridge Port is modeled as being directly 952 * connected to the attached Local Area Network (LAN). 953 * 954 * On the switch with CPU port architecture, CPU port functions as Management 955 * Port, and the Management Port functionality is provided by software which 956 * functions as an end station. Software is connected to an IEEE 802 LAN that is 957 * wholly contained within the system that incorporates the Bridge. Software 958 * provides access to the LLC Entity associated with each Bridge Port by the 959 * value of the source port field on the special tag on the frame received by 960 * software. 961 * 962 * We call frames that carry control information to determine the active 963 * topology and current extent of each Virtual Local Area Network (VLAN), i.e., 964 * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration 965 * Protocol Data Units (MVRPDUs), and frames from other link constrained 966 * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and 967 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not 968 * forwarded by a Bridge. Permanently configured entries in the filtering 969 * database (FDB) ensure that such frames are discarded by the Forwarding 970 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: 971 * 972 * Each of the reserved MAC addresses specified in Table 8-1 973 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be 974 * permanently configured in the FDB in C-VLAN components and ERs. 975 * 976 * Each of the reserved MAC addresses specified in Table 8-2 977 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently 978 * configured in the FDB in S-VLAN components. 979 * 980 * Each of the reserved MAC addresses specified in Table 8-3 981 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in 982 * TPMR components. 983 * 984 * The FDB entries for reserved MAC addresses shall specify filtering for all 985 * Bridge Ports and all VIDs. Management shall not provide the capability to 986 * modify or remove entries for reserved MAC addresses. 987 * 988 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of 989 * propagation of PDUs within a Bridged Network, as follows: 990 * 991 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no 992 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) 993 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. 994 * PDUs transmitted using this destination address, or any other addresses 995 * that appear in Table 8-1, Table 8-2, and Table 8-3 996 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can 997 * therefore travel no further than those stations that can be reached via a 998 * single individual LAN from the originating station. 999 * 1000 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an 1001 * address that no conformant S-VLAN component, C-VLAN component, or MAC 1002 * Bridge can forward; however, this address is relayed by a TPMR component. 1003 * PDUs using this destination address, or any of the other addresses that 1004 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3 1005 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by 1006 * any TPMRs but will propagate no further than the nearest S-VLAN component, 1007 * C-VLAN component, or MAC Bridge. 1008 * 1009 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address 1010 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is 1011 * relayed by TPMR components and S-VLAN components. PDUs using this 1012 * destination address, or any of the other addresses that appear in Table 8-1 1013 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), 1014 * will be relayed by TPMR components and S-VLAN components but will propagate 1015 * no further than the nearest C-VLAN component or MAC Bridge. 1016 * 1017 * Because the LLC Entity associated with each Bridge Port is provided via CPU 1018 * port, we must not filter these frames but forward them to CPU port. 1019 * 1020 * In a Bridge, the transmission Port is majorly decided by ingress and egress 1021 * rules, FDB, and spanning tree Port State functions of the Forwarding Process. 1022 * For link-local frames, only CPU port should be designated as destination port 1023 * in the FDB, and the other functions of the Forwarding Process must not 1024 * interfere with the decision of the transmission Port. We call this process 1025 * trapping frames to CPU port. 1026 * 1027 * Therefore, on the switch with CPU port architecture, link-local frames must 1028 * be trapped to CPU port, and certain link-local frames received by a Port of a 1029 * Bridge comprising a TPMR component or an S-VLAN component must be excluded 1030 * from it. 1031 * 1032 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port 1033 * MAC Relay (TPMR) component as a TPMR component supports only a subset of the 1034 * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port 1035 * doesn't count) of this architecture will either function as a standard MAC 1036 * Bridge or a standard VLAN Bridge. 1037 * 1038 * Therefore, a Bridge of this architecture can only comprise S-VLAN components, 1039 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component, 1040 * we don't need to relay PDUs using the destination addresses specified on the 1041 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge 1042 * section where they must be relayed by TPMR components. 1043 * 1044 * One option to trap link-local frames to CPU port is to add static FDB entries 1045 * with CPU port designated as destination port. However, because that 1046 * Independent VLAN Learning (IVL) is being used on every VID, each entry only 1047 * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC 1048 * Bridge component or a C-VLAN component, there would have to be 16 times 4096 1049 * entries. This switch intellectual property can only hold a maximum of 2048 1050 * entries. Using this option, there also isn't a mechanism to prevent 1051 * link-local frames from being discarded when the spanning tree Port State of 1052 * the reception Port is discarding. 1053 * 1054 * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 1055 * registers. Whilst this applies to every VID, it doesn't contain all of the 1056 * reserved MAC addresses without affecting the remaining Standard Group MAC 1057 * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the 1058 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination 1059 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF 1060 * destination addresses which may be relayed by MAC Bridges or VLAN Bridges. 1061 * The latter option provides better but not complete conformance. 1062 * 1063 * This switch intellectual property also does not provide a mechanism to trap 1064 * link-local frames with specific destination addresses to CPU port by Bridge, 1065 * to conform to the filtering rules for the distinct Bridge components. 1066 * 1067 * Therefore, regardless of the type of the Bridge component, link-local frames 1068 * with these destination addresses will be trapped to CPU port: 1069 * 1070 * 01-80-C2-00-00-[00,01,02,03,0E] 1071 * 1072 * In a Bridge comprising a MAC Bridge component or a C-VLAN component: 1073 * 1074 * Link-local frames with these destination addresses won't be trapped to CPU 1075 * port which won't conform to IEEE Std 802.1Q-2022: 1076 * 1077 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] 1078 * 1079 * In a Bridge comprising an S-VLAN component: 1080 * 1081 * Link-local frames with these destination addresses will be trapped to CPU 1082 * port which won't conform to IEEE Std 802.1Q-2022: 1083 * 1084 * 01-80-C2-00-00-00 1085 * 1086 * Link-local frames with these destination addresses won't be trapped to CPU 1087 * port which won't conform to IEEE Std 802.1Q-2022: 1088 * 1089 * 01-80-C2-00-00-[04,05,06,07,08,09,0A] 1090 * 1091 * To trap link-local frames to CPU port as conformant as this switch 1092 * intellectual property can allow, link-local frames are made to be regarded as 1093 * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual 1094 * property only lets the frames regarded as BPDUs bypass the spanning tree Port 1095 * State function of the Forwarding Process. 1096 * 1097 * The only remaining interference is the ingress rules. When the reception Port 1098 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in. 1099 * There doesn't seem to be a mechanism on the switch intellectual property to 1100 * have link-local frames bypass this function of the Forwarding Process. 1101 */ 1102 static void 1103 mt753x_trap_frames(struct mt7530_priv *priv) 1104 { 1105 /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them 1106 * VLAN-untagged. 1107 */ 1108 mt7530_rmw(priv, MT753X_BPC, 1109 PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK | 1110 BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK, 1111 PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1112 PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) | 1113 BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1114 TO_CPU_FW_CPU_ONLY); 1115 1116 /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress 1117 * them VLAN-untagged. 1118 */ 1119 mt7530_rmw(priv, MT753X_RGAC1, 1120 R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK | 1121 R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK, 1122 R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1123 R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR | 1124 R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1125 TO_CPU_FW_CPU_ONLY); 1126 1127 /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress 1128 * them VLAN-untagged. 1129 */ 1130 mt7530_rmw(priv, MT753X_RGAC2, 1131 R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK | 1132 R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK, 1133 R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1134 R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR | 1135 R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) | 1136 TO_CPU_FW_CPU_ONLY); 1137 } 1138 1139 static void 1140 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1141 { 1142 struct mt7530_priv *priv = ds->priv; 1143 1144 /* Enable Mediatek header mode on the cpu port */ 1145 mt7530_write(priv, MT7530_PVC_P(port), 1146 PORT_SPEC_TAG); 1147 1148 /* Enable flooding on the CPU port */ 1149 mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1150 UNU_FFP(BIT(port))); 1151 1152 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1153 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1154 * is affine to the inbound user port. 1155 */ 1156 if (priv->id == ID_MT7531 || priv->id == ID_MT7988 || 1157 priv->id == ID_EN7581) 1158 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1159 1160 /* CPU port gets connected to all user ports of 1161 * the switch. 1162 */ 1163 mt7530_write(priv, MT7530_PCR_P(port), 1164 PCR_MATRIX(dsa_user_ports(priv->ds))); 1165 1166 /* Set to fallback mode for independent VLAN learning */ 1167 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1168 MT7530_PORT_FALLBACK_MODE); 1169 } 1170 1171 static int 1172 mt7530_port_enable(struct dsa_switch *ds, int port, 1173 struct phy_device *phy) 1174 { 1175 struct dsa_port *dp = dsa_to_port(ds, port); 1176 struct mt7530_priv *priv = ds->priv; 1177 1178 mutex_lock(&priv->reg_mutex); 1179 1180 /* Allow the user port gets connected to the cpu port and also 1181 * restore the port matrix if the port is the member of a certain 1182 * bridge. 1183 */ 1184 if (dsa_port_is_user(dp)) { 1185 struct dsa_port *cpu_dp = dp->cpu_dp; 1186 1187 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1188 } 1189 priv->ports[port].enable = true; 1190 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1191 priv->ports[port].pm); 1192 1193 mutex_unlock(&priv->reg_mutex); 1194 1195 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1196 return 0; 1197 1198 if (port == 5) 1199 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 1200 else if (port == 6) 1201 mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS); 1202 1203 return 0; 1204 } 1205 1206 static void 1207 mt7530_port_disable(struct dsa_switch *ds, int port) 1208 { 1209 struct mt7530_priv *priv = ds->priv; 1210 1211 mutex_lock(&priv->reg_mutex); 1212 1213 /* Clear up all port matrix which could be restored in the next 1214 * enablement for the port. 1215 */ 1216 priv->ports[port].enable = false; 1217 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1218 PCR_MATRIX_CLR); 1219 1220 mutex_unlock(&priv->reg_mutex); 1221 1222 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 1223 return; 1224 1225 /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */ 1226 if (port == 5 && priv->p5_mode == GMAC5) 1227 mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS); 1228 else if (port == 6) 1229 mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS); 1230 } 1231 1232 static int 1233 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1234 { 1235 struct mt7530_priv *priv = ds->priv; 1236 int length; 1237 u32 val; 1238 1239 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1240 * largest MTU of the user ports. Because the switch only has a global 1241 * RX length register, only allowing CPU port here is enough. 1242 */ 1243 if (!dsa_is_cpu_port(ds, port)) 1244 return 0; 1245 1246 mt7530_mutex_lock(priv); 1247 1248 val = mt7530_mii_read(priv, MT7530_GMACCR); 1249 val &= ~MAX_RX_PKT_LEN_MASK; 1250 1251 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1252 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1253 if (length <= 1522) { 1254 val |= MAX_RX_PKT_LEN_1522; 1255 } else if (length <= 1536) { 1256 val |= MAX_RX_PKT_LEN_1536; 1257 } else if (length <= 1552) { 1258 val |= MAX_RX_PKT_LEN_1552; 1259 } else { 1260 val &= ~MAX_RX_JUMBO_MASK; 1261 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1262 val |= MAX_RX_PKT_LEN_JUMBO; 1263 } 1264 1265 mt7530_mii_write(priv, MT7530_GMACCR, val); 1266 1267 mt7530_mutex_unlock(priv); 1268 1269 return 0; 1270 } 1271 1272 static int 1273 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1274 { 1275 return MT7530_MAX_MTU; 1276 } 1277 1278 static void 1279 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1280 { 1281 struct mt7530_priv *priv = ds->priv; 1282 u32 stp_state; 1283 1284 switch (state) { 1285 case BR_STATE_DISABLED: 1286 stp_state = MT7530_STP_DISABLED; 1287 break; 1288 case BR_STATE_BLOCKING: 1289 stp_state = MT7530_STP_BLOCKING; 1290 break; 1291 case BR_STATE_LISTENING: 1292 stp_state = MT7530_STP_LISTENING; 1293 break; 1294 case BR_STATE_LEARNING: 1295 stp_state = MT7530_STP_LEARNING; 1296 break; 1297 case BR_STATE_FORWARDING: 1298 default: 1299 stp_state = MT7530_STP_FORWARDING; 1300 break; 1301 } 1302 1303 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1304 FID_PST(FID_BRIDGED, stp_state)); 1305 } 1306 1307 static void mt7530_update_port_member(struct mt7530_priv *priv, int port, 1308 const struct net_device *bridge_dev, 1309 bool join) __must_hold(&priv->reg_mutex) 1310 { 1311 struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp; 1312 struct mt7530_port *p = &priv->ports[port], *other_p; 1313 struct dsa_port *cpu_dp = dp->cpu_dp; 1314 u32 port_bitmap = BIT(cpu_dp->index); 1315 int other_port; 1316 bool isolated; 1317 1318 dsa_switch_for_each_user_port(other_dp, priv->ds) { 1319 other_port = other_dp->index; 1320 other_p = &priv->ports[other_port]; 1321 1322 if (dp == other_dp) 1323 continue; 1324 1325 /* Add/remove this port to/from the port matrix of the other 1326 * ports in the same bridge. If the port is disabled, port 1327 * matrix is kept and not being setup until the port becomes 1328 * enabled. 1329 */ 1330 if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev)) 1331 continue; 1332 1333 isolated = p->isolated && other_p->isolated; 1334 1335 if (join && !isolated) { 1336 other_p->pm |= PCR_MATRIX(BIT(port)); 1337 port_bitmap |= BIT(other_port); 1338 } else { 1339 other_p->pm &= ~PCR_MATRIX(BIT(port)); 1340 } 1341 1342 if (other_p->enable) 1343 mt7530_rmw(priv, MT7530_PCR_P(other_port), 1344 PCR_MATRIX_MASK, other_p->pm); 1345 } 1346 1347 /* Add/remove the all other ports to this port matrix. For !join 1348 * (leaving the bridge), only the CPU port will remain in the port matrix 1349 * of this port. 1350 */ 1351 p->pm = PCR_MATRIX(port_bitmap); 1352 if (priv->ports[port].enable) 1353 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, p->pm); 1354 } 1355 1356 static int 1357 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1358 struct switchdev_brport_flags flags, 1359 struct netlink_ext_ack *extack) 1360 { 1361 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1362 BR_BCAST_FLOOD | BR_ISOLATED)) 1363 return -EINVAL; 1364 1365 return 0; 1366 } 1367 1368 static int 1369 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1370 struct switchdev_brport_flags flags, 1371 struct netlink_ext_ack *extack) 1372 { 1373 struct mt7530_priv *priv = ds->priv; 1374 1375 if (flags.mask & BR_LEARNING) 1376 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1377 flags.val & BR_LEARNING ? 0 : SA_DIS); 1378 1379 if (flags.mask & BR_FLOOD) 1380 mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)), 1381 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1382 1383 if (flags.mask & BR_MCAST_FLOOD) 1384 mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)), 1385 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1386 1387 if (flags.mask & BR_BCAST_FLOOD) 1388 mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)), 1389 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1390 1391 if (flags.mask & BR_ISOLATED) { 1392 struct dsa_port *dp = dsa_to_port(ds, port); 1393 struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp); 1394 1395 priv->ports[port].isolated = !!(flags.val & BR_ISOLATED); 1396 1397 mutex_lock(&priv->reg_mutex); 1398 mt7530_update_port_member(priv, port, bridge_dev, true); 1399 mutex_unlock(&priv->reg_mutex); 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int 1406 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1407 struct dsa_bridge bridge, bool *tx_fwd_offload, 1408 struct netlink_ext_ack *extack) 1409 { 1410 struct mt7530_priv *priv = ds->priv; 1411 1412 mutex_lock(&priv->reg_mutex); 1413 1414 mt7530_update_port_member(priv, port, bridge.dev, true); 1415 1416 /* Set to fallback mode for independent VLAN learning */ 1417 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1418 MT7530_PORT_FALLBACK_MODE); 1419 1420 mutex_unlock(&priv->reg_mutex); 1421 1422 return 0; 1423 } 1424 1425 static void 1426 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1427 { 1428 struct mt7530_priv *priv = ds->priv; 1429 bool all_user_ports_removed = true; 1430 int i; 1431 1432 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1433 * bridge. Don't set standalone ports to fallback mode. 1434 */ 1435 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1436 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1437 MT7530_PORT_FALLBACK_MODE); 1438 1439 mt7530_rmw(priv, MT7530_PVC_P(port), 1440 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1441 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1442 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1443 MT7530_VLAN_ACC_ALL); 1444 1445 /* Set PVID to 0 */ 1446 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1447 G0_PORT_VID_DEF); 1448 1449 for (i = 0; i < priv->ds->num_ports; i++) { 1450 if (dsa_is_user_port(ds, i) && 1451 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1452 all_user_ports_removed = false; 1453 break; 1454 } 1455 } 1456 1457 /* CPU port also does the same thing until all user ports belonging to 1458 * the CPU port get out of VLAN filtering mode. 1459 */ 1460 if (all_user_ports_removed) { 1461 struct dsa_port *dp = dsa_to_port(ds, port); 1462 struct dsa_port *cpu_dp = dp->cpu_dp; 1463 1464 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1465 PCR_MATRIX(dsa_user_ports(priv->ds))); 1466 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1467 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1468 } 1469 } 1470 1471 static void 1472 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1473 { 1474 struct mt7530_priv *priv = ds->priv; 1475 1476 /* Trapped into security mode allows packet forwarding through VLAN 1477 * table lookup. 1478 */ 1479 if (dsa_is_user_port(ds, port)) { 1480 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1481 MT7530_PORT_SECURITY_MODE); 1482 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1483 G0_PORT_VID(priv->ports[port].pvid)); 1484 1485 /* Only accept tagged frames if PVID is not set */ 1486 if (!priv->ports[port].pvid) 1487 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1488 MT7530_VLAN_ACC_TAGGED); 1489 1490 /* Set the port as a user port which is to be able to recognize 1491 * VID from incoming packets before fetching entry within the 1492 * VLAN table. 1493 */ 1494 mt7530_rmw(priv, MT7530_PVC_P(port), 1495 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1496 VLAN_ATTR(MT7530_VLAN_USER) | 1497 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1498 } else { 1499 /* Also set CPU ports to the "user" VLAN port attribute, to 1500 * allow VLAN classification, but keep the EG_TAG attribute as 1501 * "consistent" (i.o.w. don't change its value) for packets 1502 * received by the switch from the CPU, so that tagged packets 1503 * are forwarded to user ports as tagged, and untagged as 1504 * untagged. 1505 */ 1506 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1507 VLAN_ATTR(MT7530_VLAN_USER)); 1508 } 1509 } 1510 1511 static void 1512 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1513 struct dsa_bridge bridge) 1514 { 1515 struct mt7530_priv *priv = ds->priv; 1516 1517 mutex_lock(&priv->reg_mutex); 1518 1519 mt7530_update_port_member(priv, port, bridge.dev, false); 1520 1521 /* When a port is removed from the bridge, the port would be set up 1522 * back to the default as is at initial boot which is a VLAN-unaware 1523 * port. 1524 */ 1525 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1526 MT7530_PORT_MATRIX_MODE); 1527 1528 mutex_unlock(&priv->reg_mutex); 1529 } 1530 1531 static int 1532 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1533 const unsigned char *addr, u16 vid, 1534 struct dsa_db db) 1535 { 1536 struct mt7530_priv *priv = ds->priv; 1537 int ret; 1538 u8 port_mask = BIT(port); 1539 1540 mutex_lock(&priv->reg_mutex); 1541 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1542 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1543 mutex_unlock(&priv->reg_mutex); 1544 1545 return ret; 1546 } 1547 1548 static int 1549 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1550 const unsigned char *addr, u16 vid, 1551 struct dsa_db db) 1552 { 1553 struct mt7530_priv *priv = ds->priv; 1554 int ret; 1555 u8 port_mask = BIT(port); 1556 1557 mutex_lock(&priv->reg_mutex); 1558 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1559 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1560 mutex_unlock(&priv->reg_mutex); 1561 1562 return ret; 1563 } 1564 1565 static int 1566 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1567 dsa_fdb_dump_cb_t *cb, void *data) 1568 { 1569 struct mt7530_priv *priv = ds->priv; 1570 struct mt7530_fdb _fdb = { 0 }; 1571 int cnt = MT7530_NUM_FDB_RECORDS; 1572 int ret = 0; 1573 u32 rsp = 0; 1574 1575 mutex_lock(&priv->reg_mutex); 1576 1577 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1578 if (ret < 0) 1579 goto err; 1580 1581 do { 1582 if (rsp & ATC_SRCH_HIT) { 1583 mt7530_fdb_read(priv, &_fdb); 1584 if (_fdb.port_mask & BIT(port)) { 1585 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1586 data); 1587 if (ret < 0) 1588 break; 1589 } 1590 } 1591 } while (--cnt && 1592 !(rsp & ATC_SRCH_END) && 1593 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1594 err: 1595 mutex_unlock(&priv->reg_mutex); 1596 1597 return 0; 1598 } 1599 1600 static int 1601 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1602 const struct switchdev_obj_port_mdb *mdb, 1603 struct dsa_db db) 1604 { 1605 struct mt7530_priv *priv = ds->priv; 1606 const u8 *addr = mdb->addr; 1607 u16 vid = mdb->vid; 1608 u8 port_mask = 0; 1609 int ret; 1610 1611 mutex_lock(&priv->reg_mutex); 1612 1613 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1614 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1615 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1616 & PORT_MAP_MASK; 1617 1618 port_mask |= BIT(port); 1619 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1620 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1621 1622 mutex_unlock(&priv->reg_mutex); 1623 1624 return ret; 1625 } 1626 1627 static int 1628 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1629 const struct switchdev_obj_port_mdb *mdb, 1630 struct dsa_db db) 1631 { 1632 struct mt7530_priv *priv = ds->priv; 1633 const u8 *addr = mdb->addr; 1634 u16 vid = mdb->vid; 1635 u8 port_mask = 0; 1636 int ret; 1637 1638 mutex_lock(&priv->reg_mutex); 1639 1640 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1641 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1642 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1643 & PORT_MAP_MASK; 1644 1645 port_mask &= ~BIT(port); 1646 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1647 port_mask ? STATIC_ENT : STATIC_EMP); 1648 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1649 1650 mutex_unlock(&priv->reg_mutex); 1651 1652 return ret; 1653 } 1654 1655 static int 1656 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1657 { 1658 struct mt7530_dummy_poll p; 1659 u32 val; 1660 int ret; 1661 1662 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1663 mt7530_write(priv, MT7530_VTCR, val); 1664 1665 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1666 ret = readx_poll_timeout(_mt7530_read, &p, val, 1667 !(val & VTCR_BUSY), 20, 20000); 1668 if (ret < 0) { 1669 dev_err(priv->dev, "poll timeout\n"); 1670 return ret; 1671 } 1672 1673 val = mt7530_read(priv, MT7530_VTCR); 1674 if (val & VTCR_INVALID) { 1675 dev_err(priv->dev, "read VTCR invalid\n"); 1676 return -EINVAL; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int 1683 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1684 struct netlink_ext_ack *extack) 1685 { 1686 struct dsa_port *dp = dsa_to_port(ds, port); 1687 struct dsa_port *cpu_dp = dp->cpu_dp; 1688 1689 if (vlan_filtering) { 1690 /* The port is being kept as VLAN-unaware port when bridge is 1691 * set up with vlan_filtering not being set, Otherwise, the 1692 * port and the corresponding CPU port is required the setup 1693 * for becoming a VLAN-aware port. 1694 */ 1695 mt7530_port_set_vlan_aware(ds, port); 1696 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1697 } else { 1698 mt7530_port_set_vlan_unaware(ds, port); 1699 } 1700 1701 return 0; 1702 } 1703 1704 static void 1705 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1706 struct mt7530_hw_vlan_entry *entry) 1707 { 1708 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1709 u8 new_members; 1710 u32 val; 1711 1712 new_members = entry->old_members | BIT(entry->port); 1713 1714 /* Validate the entry with independent learning, create egress tag per 1715 * VLAN and joining the port as one of the port members. 1716 */ 1717 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1718 VLAN_VALID; 1719 mt7530_write(priv, MT7530_VAWD1, val); 1720 1721 /* Decide whether adding tag or not for those outgoing packets from the 1722 * port inside the VLAN. 1723 * CPU port is always taken as a tagged port for serving more than one 1724 * VLANs across and also being applied with egress type stack mode for 1725 * that VLAN tags would be appended after hardware special tag used as 1726 * DSA tag. 1727 */ 1728 if (dsa_port_is_cpu(dp)) 1729 val = MT7530_VLAN_EGRESS_STACK; 1730 else if (entry->untagged) 1731 val = MT7530_VLAN_EGRESS_UNTAG; 1732 else 1733 val = MT7530_VLAN_EGRESS_TAG; 1734 mt7530_rmw(priv, MT7530_VAWD2, 1735 ETAG_CTRL_P_MASK(entry->port), 1736 ETAG_CTRL_P(entry->port, val)); 1737 } 1738 1739 static void 1740 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1741 struct mt7530_hw_vlan_entry *entry) 1742 { 1743 u8 new_members; 1744 u32 val; 1745 1746 new_members = entry->old_members & ~BIT(entry->port); 1747 1748 val = mt7530_read(priv, MT7530_VAWD1); 1749 if (!(val & VLAN_VALID)) { 1750 dev_err(priv->dev, 1751 "Cannot be deleted due to invalid entry\n"); 1752 return; 1753 } 1754 1755 if (new_members) { 1756 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1757 VLAN_VALID; 1758 mt7530_write(priv, MT7530_VAWD1, val); 1759 } else { 1760 mt7530_write(priv, MT7530_VAWD1, 0); 1761 mt7530_write(priv, MT7530_VAWD2, 0); 1762 } 1763 } 1764 1765 static void 1766 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1767 struct mt7530_hw_vlan_entry *entry, 1768 mt7530_vlan_op vlan_op) 1769 { 1770 u32 val; 1771 1772 /* Fetch entry */ 1773 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1774 1775 val = mt7530_read(priv, MT7530_VAWD1); 1776 1777 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1778 1779 /* Manipulate entry */ 1780 vlan_op(priv, entry); 1781 1782 /* Flush result to hardware */ 1783 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1784 } 1785 1786 static int 1787 mt7530_setup_vlan0(struct mt7530_priv *priv) 1788 { 1789 u32 val; 1790 1791 /* Validate the entry with independent learning, keep the original 1792 * ingress tag attribute. 1793 */ 1794 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1795 VLAN_VALID; 1796 mt7530_write(priv, MT7530_VAWD1, val); 1797 1798 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1799 } 1800 1801 static int 1802 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1803 const struct switchdev_obj_port_vlan *vlan, 1804 struct netlink_ext_ack *extack) 1805 { 1806 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1807 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1808 struct mt7530_hw_vlan_entry new_entry; 1809 struct mt7530_priv *priv = ds->priv; 1810 1811 mutex_lock(&priv->reg_mutex); 1812 1813 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1814 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1815 1816 if (pvid) { 1817 priv->ports[port].pvid = vlan->vid; 1818 1819 /* Accept all frames if PVID is set */ 1820 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1821 MT7530_VLAN_ACC_ALL); 1822 1823 /* Only configure PVID if VLAN filtering is enabled */ 1824 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1825 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1826 G0_PORT_VID_MASK, 1827 G0_PORT_VID(vlan->vid)); 1828 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1829 /* This VLAN is overwritten without PVID, so unset it */ 1830 priv->ports[port].pvid = G0_PORT_VID_DEF; 1831 1832 /* Only accept tagged frames if the port is VLAN-aware */ 1833 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1834 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1835 MT7530_VLAN_ACC_TAGGED); 1836 1837 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1838 G0_PORT_VID_DEF); 1839 } 1840 1841 mutex_unlock(&priv->reg_mutex); 1842 1843 return 0; 1844 } 1845 1846 static int 1847 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1848 const struct switchdev_obj_port_vlan *vlan) 1849 { 1850 struct mt7530_hw_vlan_entry target_entry; 1851 struct mt7530_priv *priv = ds->priv; 1852 1853 mutex_lock(&priv->reg_mutex); 1854 1855 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1856 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1857 mt7530_hw_vlan_del); 1858 1859 /* PVID is being restored to the default whenever the PVID port 1860 * is being removed from the VLAN. 1861 */ 1862 if (priv->ports[port].pvid == vlan->vid) { 1863 priv->ports[port].pvid = G0_PORT_VID_DEF; 1864 1865 /* Only accept tagged frames if the port is VLAN-aware */ 1866 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1867 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1868 MT7530_VLAN_ACC_TAGGED); 1869 1870 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1871 G0_PORT_VID_DEF); 1872 } 1873 1874 1875 mutex_unlock(&priv->reg_mutex); 1876 1877 return 0; 1878 } 1879 1880 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1881 struct dsa_mall_mirror_tc_entry *mirror, 1882 bool ingress, struct netlink_ext_ack *extack) 1883 { 1884 struct mt7530_priv *priv = ds->priv; 1885 int monitor_port; 1886 u32 val; 1887 1888 /* Check for existent entry */ 1889 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1890 return -EEXIST; 1891 1892 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1893 1894 /* MT7530 only supports one monitor port */ 1895 monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val); 1896 if (val & MT753X_MIRROR_EN(priv->id) && 1897 monitor_port != mirror->to_local_port) 1898 return -EEXIST; 1899 1900 val |= MT753X_MIRROR_EN(priv->id); 1901 val &= ~MT753X_MIRROR_PORT_MASK(priv->id); 1902 val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port); 1903 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1904 1905 val = mt7530_read(priv, MT7530_PCR_P(port)); 1906 if (ingress) { 1907 val |= PORT_RX_MIR; 1908 priv->mirror_rx |= BIT(port); 1909 } else { 1910 val |= PORT_TX_MIR; 1911 priv->mirror_tx |= BIT(port); 1912 } 1913 mt7530_write(priv, MT7530_PCR_P(port), val); 1914 1915 return 0; 1916 } 1917 1918 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1919 struct dsa_mall_mirror_tc_entry *mirror) 1920 { 1921 struct mt7530_priv *priv = ds->priv; 1922 u32 val; 1923 1924 val = mt7530_read(priv, MT7530_PCR_P(port)); 1925 if (mirror->ingress) { 1926 val &= ~PORT_RX_MIR; 1927 priv->mirror_rx &= ~BIT(port); 1928 } else { 1929 val &= ~PORT_TX_MIR; 1930 priv->mirror_tx &= ~BIT(port); 1931 } 1932 mt7530_write(priv, MT7530_PCR_P(port), val); 1933 1934 if (!priv->mirror_rx && !priv->mirror_tx) { 1935 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1936 val &= ~MT753X_MIRROR_EN(priv->id); 1937 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1938 } 1939 } 1940 1941 static enum dsa_tag_protocol 1942 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1943 enum dsa_tag_protocol mp) 1944 { 1945 return DSA_TAG_PROTO_MTK; 1946 } 1947 1948 #ifdef CONFIG_GPIOLIB 1949 static inline u32 1950 mt7530_gpio_to_bit(unsigned int offset) 1951 { 1952 /* Map GPIO offset to register bit 1953 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1954 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1955 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1956 * [14:12] port 3 LED 0..2 as GPIO 9..11 1957 * [18:16] port 4 LED 0..2 as GPIO 12..14 1958 */ 1959 return BIT(offset + offset / 3); 1960 } 1961 1962 static int 1963 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1964 { 1965 struct mt7530_priv *priv = gpiochip_get_data(gc); 1966 u32 bit = mt7530_gpio_to_bit(offset); 1967 1968 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1969 } 1970 1971 static void 1972 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1973 { 1974 struct mt7530_priv *priv = gpiochip_get_data(gc); 1975 u32 bit = mt7530_gpio_to_bit(offset); 1976 1977 if (value) 1978 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1979 else 1980 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1981 } 1982 1983 static int 1984 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1985 { 1986 struct mt7530_priv *priv = gpiochip_get_data(gc); 1987 u32 bit = mt7530_gpio_to_bit(offset); 1988 1989 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1990 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1991 } 1992 1993 static int 1994 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1995 { 1996 struct mt7530_priv *priv = gpiochip_get_data(gc); 1997 u32 bit = mt7530_gpio_to_bit(offset); 1998 1999 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 2000 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 2001 2002 return 0; 2003 } 2004 2005 static int 2006 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 2007 { 2008 struct mt7530_priv *priv = gpiochip_get_data(gc); 2009 u32 bit = mt7530_gpio_to_bit(offset); 2010 2011 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 2012 2013 if (value) 2014 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 2015 else 2016 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 2017 2018 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 2019 2020 return 0; 2021 } 2022 2023 static int 2024 mt7530_setup_gpio(struct mt7530_priv *priv) 2025 { 2026 struct device *dev = priv->dev; 2027 struct gpio_chip *gc; 2028 2029 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 2030 if (!gc) 2031 return -ENOMEM; 2032 2033 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 2034 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 2035 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 2036 2037 gc->label = "mt7530"; 2038 gc->parent = dev; 2039 gc->owner = THIS_MODULE; 2040 gc->get_direction = mt7530_gpio_get_direction; 2041 gc->direction_input = mt7530_gpio_direction_input; 2042 gc->direction_output = mt7530_gpio_direction_output; 2043 gc->get = mt7530_gpio_get; 2044 gc->set = mt7530_gpio_set; 2045 gc->base = -1; 2046 gc->ngpio = 15; 2047 gc->can_sleep = true; 2048 2049 return devm_gpiochip_add_data(dev, gc, priv); 2050 } 2051 #endif /* CONFIG_GPIOLIB */ 2052 2053 static void 2054 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2055 { 2056 struct dsa_switch *ds = priv->ds; 2057 int p; 2058 2059 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2060 if (BIT(p) & ds->phys_mii_mask) { 2061 unsigned int irq; 2062 2063 irq = irq_create_mapping(priv->irq_domain, p); 2064 ds->user_mii_bus->irq[p] = irq; 2065 } 2066 } 2067 } 2068 2069 static const struct regmap_irq mt7530_irqs[] = { 2070 REGMAP_IRQ_REG_LINE(0, 32), /* PHY0_LC */ 2071 REGMAP_IRQ_REG_LINE(1, 32), /* PHY1_LC */ 2072 REGMAP_IRQ_REG_LINE(2, 32), /* PHY2_LC */ 2073 REGMAP_IRQ_REG_LINE(3, 32), /* PHY3_LC */ 2074 REGMAP_IRQ_REG_LINE(4, 32), /* PHY4_LC */ 2075 REGMAP_IRQ_REG_LINE(5, 32), /* PHY5_LC */ 2076 REGMAP_IRQ_REG_LINE(6, 32), /* PHY6_LC */ 2077 REGMAP_IRQ_REG_LINE(16, 32), /* MAC_PC */ 2078 REGMAP_IRQ_REG_LINE(17, 32), /* BMU */ 2079 REGMAP_IRQ_REG_LINE(18, 32), /* MIB */ 2080 REGMAP_IRQ_REG_LINE(22, 32), /* ARL_COL_FULL_COL */ 2081 REGMAP_IRQ_REG_LINE(23, 32), /* ARL_COL_FULL */ 2082 REGMAP_IRQ_REG_LINE(24, 32), /* ARL_TBL_ERR */ 2083 REGMAP_IRQ_REG_LINE(25, 32), /* ARL_PKT_QERR */ 2084 REGMAP_IRQ_REG_LINE(26, 32), /* ARL_EQ_ERR */ 2085 REGMAP_IRQ_REG_LINE(27, 32), /* ARL_PKT_BC */ 2086 REGMAP_IRQ_REG_LINE(28, 32), /* ARL_SEC_IG1X */ 2087 REGMAP_IRQ_REG_LINE(29, 32), /* ARL_SEC_VLAN */ 2088 REGMAP_IRQ_REG_LINE(30, 32), /* ARL_SEC_TAG */ 2089 REGMAP_IRQ_REG_LINE(31, 32), /* ACL */ 2090 }; 2091 2092 static const struct regmap_irq_chip mt7530_regmap_irq_chip = { 2093 .name = KBUILD_MODNAME, 2094 .status_base = MT7530_SYS_INT_STS, 2095 .unmask_base = MT7530_SYS_INT_EN, 2096 .ack_base = MT7530_SYS_INT_STS, 2097 .init_ack_masked = true, 2098 .irqs = mt7530_irqs, 2099 .num_irqs = ARRAY_SIZE(mt7530_irqs), 2100 .num_regs = 1, 2101 }; 2102 2103 static int 2104 mt7530_setup_irq(struct mt7530_priv *priv) 2105 { 2106 struct regmap_irq_chip_data *irq_data; 2107 struct device *dev = priv->dev; 2108 struct device_node *np = dev->of_node; 2109 int irq, ret; 2110 2111 if (!of_property_read_bool(np, "interrupt-controller")) { 2112 dev_info(dev, "no interrupt support\n"); 2113 return 0; 2114 } 2115 2116 irq = of_irq_get(np, 0); 2117 if (irq <= 0) { 2118 dev_err(dev, "failed to get parent IRQ: %d\n", irq); 2119 return irq ? : -EINVAL; 2120 } 2121 2122 /* This register must be set for MT7530 to properly fire interrupts */ 2123 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 2124 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2125 2126 ret = devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(dev), 2127 priv->regmap, irq, 2128 IRQF_ONESHOT, 2129 0, &mt7530_regmap_irq_chip, 2130 &irq_data); 2131 if (ret) 2132 return ret; 2133 2134 priv->irq_domain = regmap_irq_get_domain(irq_data); 2135 2136 return 0; 2137 } 2138 2139 static void 2140 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2141 { 2142 int p; 2143 2144 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2145 if (BIT(p) & priv->ds->phys_mii_mask) { 2146 unsigned int irq; 2147 2148 irq = irq_find_mapping(priv->irq_domain, p); 2149 irq_dispose_mapping(irq); 2150 } 2151 } 2152 } 2153 2154 static int 2155 mt7530_setup_mdio(struct mt7530_priv *priv) 2156 { 2157 struct device_node *mnp, *np = priv->dev->of_node; 2158 struct dsa_switch *ds = priv->ds; 2159 struct device *dev = priv->dev; 2160 struct mii_bus *bus; 2161 static int idx; 2162 int ret = 0; 2163 2164 mnp = of_get_child_by_name(np, "mdio"); 2165 2166 if (mnp && !of_device_is_available(mnp)) 2167 goto out; 2168 2169 bus = devm_mdiobus_alloc(dev); 2170 if (!bus) { 2171 ret = -ENOMEM; 2172 goto out; 2173 } 2174 2175 if (!mnp) 2176 ds->user_mii_bus = bus; 2177 2178 bus->priv = priv; 2179 bus->name = KBUILD_MODNAME "-mii"; 2180 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2181 bus->read = mt753x_phy_read_c22; 2182 bus->write = mt753x_phy_write_c22; 2183 bus->read_c45 = mt753x_phy_read_c45; 2184 bus->write_c45 = mt753x_phy_write_c45; 2185 bus->parent = dev; 2186 bus->phy_mask = ~ds->phys_mii_mask; 2187 2188 if (priv->irq_domain && !mnp) 2189 mt7530_setup_mdio_irq(priv); 2190 2191 ret = devm_of_mdiobus_register(dev, bus, mnp); 2192 if (ret) { 2193 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2194 if (priv->irq_domain && !mnp) 2195 mt7530_free_mdio_irq(priv); 2196 } 2197 2198 out: 2199 of_node_put(mnp); 2200 return ret; 2201 } 2202 2203 static int 2204 mt7530_setup(struct dsa_switch *ds) 2205 { 2206 struct mt7530_priv *priv = ds->priv; 2207 struct device_node *dn = NULL; 2208 struct device_node *phy_node; 2209 struct device_node *mac_np; 2210 struct mt7530_dummy_poll p; 2211 phy_interface_t interface; 2212 struct dsa_port *cpu_dp; 2213 u32 id, val; 2214 int ret, i; 2215 2216 /* The parent node of conduit netdev which holds the common system 2217 * controller also is the container for two GMACs nodes representing 2218 * as two netdev instances. 2219 */ 2220 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2221 dn = cpu_dp->conduit->dev.of_node->parent; 2222 /* It doesn't matter which CPU port is found first, 2223 * their conduits should share the same parent OF node 2224 */ 2225 break; 2226 } 2227 2228 if (!dn) { 2229 dev_err(ds->dev, "parent OF node of DSA conduit not found"); 2230 return -EINVAL; 2231 } 2232 2233 ds->assisted_learning_on_cpu_port = true; 2234 ds->mtu_enforcement_ingress = true; 2235 2236 if (priv->id == ID_MT7530) { 2237 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2238 ret = regulator_enable(priv->core_pwr); 2239 if (ret < 0) { 2240 dev_err(priv->dev, 2241 "Failed to enable core power: %d\n", ret); 2242 return ret; 2243 } 2244 2245 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2246 ret = regulator_enable(priv->io_pwr); 2247 if (ret < 0) { 2248 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2249 ret); 2250 return ret; 2251 } 2252 } 2253 2254 /* Reset whole chip through gpio pin or memory-mapped registers for 2255 * different type of hardware 2256 */ 2257 if (priv->mcm) { 2258 reset_control_assert(priv->rstc); 2259 usleep_range(5000, 5100); 2260 reset_control_deassert(priv->rstc); 2261 } else { 2262 gpiod_set_value_cansleep(priv->reset, 0); 2263 usleep_range(5000, 5100); 2264 gpiod_set_value_cansleep(priv->reset, 1); 2265 } 2266 2267 /* Waiting for MT7530 got to stable */ 2268 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2269 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2270 20, 1000000); 2271 if (ret < 0) { 2272 dev_err(priv->dev, "reset timeout\n"); 2273 return ret; 2274 } 2275 2276 id = mt7530_read(priv, MT7530_CREV); 2277 id >>= CHIP_NAME_SHIFT; 2278 if (id != MT7530_ID) { 2279 dev_err(priv->dev, "chip %x can't be supported\n", id); 2280 return -ENODEV; 2281 } 2282 2283 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) { 2284 dev_err(priv->dev, 2285 "MT7530 with a 20MHz XTAL is not supported!\n"); 2286 return -EINVAL; 2287 } 2288 2289 /* Reset the switch through internal reset */ 2290 mt7530_write(priv, MT7530_SYS_CTRL, 2291 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2292 SYS_CTRL_REG_RST); 2293 2294 /* Lower Tx driving for TRGMII path */ 2295 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2296 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2297 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2298 2299 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2300 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2301 RD_TAP_MASK, RD_TAP(16)); 2302 2303 /* Allow modifying the trap and directly access PHY registers via the 2304 * MDIO bus the switch is on. 2305 */ 2306 mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP | 2307 MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP); 2308 2309 if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ) 2310 mt7530_pll_setup(priv); 2311 2312 mt753x_trap_frames(priv); 2313 2314 /* Enable and reset MIB counters */ 2315 mt7530_mib_reset(ds); 2316 2317 for (i = 0; i < priv->ds->num_ports; i++) { 2318 /* Clear link settings and enable force mode to force link down 2319 * on all ports until they're enabled later. 2320 */ 2321 mt7530_rmw(priv, MT753X_PMCR_P(i), 2322 PMCR_LINK_SETTINGS_MASK | 2323 MT753X_FORCE_MODE(priv->id), 2324 MT753X_FORCE_MODE(priv->id)); 2325 2326 /* Disable forwarding by default on all ports */ 2327 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2328 PCR_MATRIX_CLR); 2329 2330 /* Disable learning by default on all ports */ 2331 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2332 2333 if (dsa_is_cpu_port(ds, i)) { 2334 mt753x_cpu_port_enable(ds, i); 2335 } else { 2336 mt7530_port_disable(ds, i); 2337 2338 /* Set default PVID to 0 on all user ports */ 2339 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2340 G0_PORT_VID_DEF); 2341 } 2342 /* Enable consistent egress tag */ 2343 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2344 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2345 } 2346 2347 /* Allow mirroring frames received on the local port (monitor port). */ 2348 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2349 2350 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2351 ret = mt7530_setup_vlan0(priv); 2352 if (ret) 2353 return ret; 2354 2355 /* Check for PHY muxing on port 5 */ 2356 if (dsa_is_unused_port(ds, 5)) { 2357 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. 2358 * Set priv->p5_mode to the appropriate value if PHY muxing is 2359 * detected. 2360 */ 2361 for_each_child_of_node(dn, mac_np) { 2362 if (!of_device_is_compatible(mac_np, 2363 "mediatek,eth-mac")) 2364 continue; 2365 2366 ret = of_property_read_u32(mac_np, "reg", &id); 2367 if (ret < 0 || id != 1) 2368 continue; 2369 2370 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2371 if (!phy_node) 2372 continue; 2373 2374 if (phy_node->parent == priv->dev->of_node->parent || 2375 phy_node->parent->parent == priv->dev->of_node) { 2376 ret = of_get_phy_mode(mac_np, &interface); 2377 if (ret && ret != -ENODEV) { 2378 of_node_put(mac_np); 2379 of_node_put(phy_node); 2380 return ret; 2381 } 2382 id = of_mdio_parse_addr(ds->dev, phy_node); 2383 if (id == 0) 2384 priv->p5_mode = MUX_PHY_P0; 2385 if (id == 4) 2386 priv->p5_mode = MUX_PHY_P4; 2387 } 2388 of_node_put(mac_np); 2389 of_node_put(phy_node); 2390 break; 2391 } 2392 2393 if (priv->p5_mode == MUX_PHY_P0 || 2394 priv->p5_mode == MUX_PHY_P4) { 2395 mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS); 2396 mt7530_setup_port5(ds, interface); 2397 } 2398 } 2399 2400 #ifdef CONFIG_GPIOLIB 2401 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2402 ret = mt7530_setup_gpio(priv); 2403 if (ret) 2404 return ret; 2405 } 2406 #endif /* CONFIG_GPIOLIB */ 2407 2408 /* Flush the FDB table */ 2409 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2410 if (ret < 0) 2411 return ret; 2412 2413 return 0; 2414 } 2415 2416 static int 2417 mt7531_setup_common(struct dsa_switch *ds) 2418 { 2419 struct mt7530_priv *priv = ds->priv; 2420 int ret, i; 2421 2422 mt753x_trap_frames(priv); 2423 2424 /* Enable and reset MIB counters */ 2425 mt7530_mib_reset(ds); 2426 2427 /* Disable flooding on all ports */ 2428 mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2429 UNU_FFP_MASK); 2430 2431 for (i = 0; i < priv->ds->num_ports; i++) { 2432 /* Clear link settings and enable force mode to force link down 2433 * on all ports until they're enabled later. 2434 */ 2435 mt7530_rmw(priv, MT753X_PMCR_P(i), 2436 PMCR_LINK_SETTINGS_MASK | 2437 MT753X_FORCE_MODE(priv->id), 2438 MT753X_FORCE_MODE(priv->id)); 2439 2440 /* Disable forwarding by default on all ports */ 2441 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2442 PCR_MATRIX_CLR); 2443 2444 /* Disable learning by default on all ports */ 2445 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2446 2447 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2448 2449 if (dsa_is_cpu_port(ds, i)) { 2450 mt753x_cpu_port_enable(ds, i); 2451 } else { 2452 mt7530_port_disable(ds, i); 2453 2454 /* Set default PVID to 0 on all user ports */ 2455 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2456 G0_PORT_VID_DEF); 2457 } 2458 2459 /* Enable consistent egress tag */ 2460 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2461 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2462 } 2463 2464 /* Allow mirroring frames received on the local port (monitor port). */ 2465 mt7530_set(priv, MT753X_AGC, LOCAL_EN); 2466 2467 /* Enable Special Tag for rx frames */ 2468 if (priv->id == ID_EN7581) 2469 mt7530_write(priv, MT753X_CPORT_SPTAG_CFG, 2470 CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN); 2471 2472 /* Flush the FDB table */ 2473 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2474 if (ret < 0) 2475 return ret; 2476 2477 return 0; 2478 } 2479 2480 static int 2481 mt7531_setup(struct dsa_switch *ds) 2482 { 2483 struct mt7530_priv *priv = ds->priv; 2484 struct mt7530_dummy_poll p; 2485 u32 val, id; 2486 int ret, i; 2487 2488 /* Reset whole chip through gpio pin or memory-mapped registers for 2489 * different type of hardware 2490 */ 2491 if (priv->mcm) { 2492 reset_control_assert(priv->rstc); 2493 usleep_range(5000, 5100); 2494 reset_control_deassert(priv->rstc); 2495 } else { 2496 gpiod_set_value_cansleep(priv->reset, 0); 2497 usleep_range(5000, 5100); 2498 gpiod_set_value_cansleep(priv->reset, 1); 2499 } 2500 2501 /* Waiting for MT7530 got to stable */ 2502 INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP); 2503 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2504 20, 1000000); 2505 if (ret < 0) { 2506 dev_err(priv->dev, "reset timeout\n"); 2507 return ret; 2508 } 2509 2510 id = mt7530_read(priv, MT7531_CREV); 2511 id >>= CHIP_NAME_SHIFT; 2512 2513 if (id != MT7531_ID) { 2514 dev_err(priv->dev, "chip %x can't be supported\n", id); 2515 return -ENODEV; 2516 } 2517 2518 /* MT7531AE has got two SGMII units. One for port 5, one for port 6. 2519 * MT7531BE has got only one SGMII unit which is for port 6. 2520 */ 2521 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 2522 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); 2523 2524 /* Force link down on all ports before internal reset */ 2525 for (i = 0; i < priv->ds->num_ports; i++) 2526 mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK); 2527 2528 /* Reset the switch through internal reset */ 2529 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); 2530 2531 if (!priv->p5_sgmii) { 2532 mt7531_pll_setup(priv); 2533 } else { 2534 /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on 2535 * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO 2536 * to expose the MDIO bus of the switch. 2537 */ 2538 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2539 MT7531_EXT_P_MDC_11); 2540 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2541 MT7531_EXT_P_MDIO_12); 2542 } 2543 2544 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2545 MT7531_GPIO0_INTERRUPT); 2546 2547 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since 2548 * phy_device has not yet been created provided for 2549 * phy_[read,write]_mmd_indirect is called, we provide our own 2550 * mt7531_ind_mmd_phy_[read,write] to complete this function. 2551 */ 2552 val = mt7531_ind_c45_phy_read(priv, 2553 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2554 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2555 val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; 2556 val &= ~MT7531_PHY_PLL_OFF; 2557 mt7531_ind_c45_phy_write(priv, 2558 MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), 2559 MDIO_MMD_VEND2, CORE_PLL_GROUP4, val); 2560 2561 /* Disable EEE advertisement on the switch PHYs. */ 2562 for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr); 2563 i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS; 2564 i++) { 2565 mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 2566 0); 2567 } 2568 2569 ret = mt7531_setup_common(ds); 2570 if (ret) 2571 return ret; 2572 2573 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2574 ret = mt7530_setup_vlan0(priv); 2575 if (ret) 2576 return ret; 2577 2578 ds->assisted_learning_on_cpu_port = true; 2579 ds->mtu_enforcement_ingress = true; 2580 2581 return 0; 2582 } 2583 2584 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2585 struct phylink_config *config) 2586 { 2587 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2588 2589 switch (port) { 2590 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2591 case 0 ... 4: 2592 __set_bit(PHY_INTERFACE_MODE_GMII, 2593 config->supported_interfaces); 2594 break; 2595 2596 /* Port 5 supports rgmii with delays, mii, and gmii. */ 2597 case 5: 2598 phy_interface_set_rgmii(config->supported_interfaces); 2599 __set_bit(PHY_INTERFACE_MODE_MII, 2600 config->supported_interfaces); 2601 __set_bit(PHY_INTERFACE_MODE_GMII, 2602 config->supported_interfaces); 2603 break; 2604 2605 /* Port 6 supports rgmii and trgmii. */ 2606 case 6: 2607 __set_bit(PHY_INTERFACE_MODE_RGMII, 2608 config->supported_interfaces); 2609 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2610 config->supported_interfaces); 2611 break; 2612 } 2613 } 2614 2615 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2616 struct phylink_config *config) 2617 { 2618 struct mt7530_priv *priv = ds->priv; 2619 2620 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2621 2622 switch (port) { 2623 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2624 case 0 ... 4: 2625 __set_bit(PHY_INTERFACE_MODE_GMII, 2626 config->supported_interfaces); 2627 break; 2628 2629 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on 2630 * MT7531AE. 2631 */ 2632 case 5: 2633 if (!priv->p5_sgmii) { 2634 phy_interface_set_rgmii(config->supported_interfaces); 2635 break; 2636 } 2637 fallthrough; 2638 2639 /* Port 6 supports sgmii/802.3z. */ 2640 case 6: 2641 __set_bit(PHY_INTERFACE_MODE_SGMII, 2642 config->supported_interfaces); 2643 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2644 config->supported_interfaces); 2645 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2646 config->supported_interfaces); 2647 2648 config->mac_capabilities |= MAC_2500FD; 2649 break; 2650 } 2651 } 2652 2653 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2654 struct phylink_config *config) 2655 { 2656 switch (port) { 2657 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2658 case 0 ... 3: 2659 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2660 config->supported_interfaces); 2661 2662 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2663 break; 2664 2665 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2666 case 6: 2667 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2668 config->supported_interfaces); 2669 2670 config->mac_capabilities |= MAC_10000FD; 2671 break; 2672 } 2673 } 2674 2675 static void en7581_mac_port_get_caps(struct dsa_switch *ds, int port, 2676 struct phylink_config *config) 2677 { 2678 switch (port) { 2679 /* Ports which are connected to switch PHYs. There is no MII pinout. */ 2680 case 0 ... 4: 2681 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2682 config->supported_interfaces); 2683 2684 config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; 2685 break; 2686 2687 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */ 2688 case 6: 2689 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2690 config->supported_interfaces); 2691 2692 config->mac_capabilities |= MAC_10000FD; 2693 break; 2694 } 2695 } 2696 2697 static void 2698 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2699 phy_interface_t interface) 2700 { 2701 struct mt7530_priv *priv = ds->priv; 2702 2703 if (port == 5) 2704 mt7530_setup_port5(priv->ds, interface); 2705 else if (port == 6) 2706 mt7530_setup_port6(priv->ds, interface); 2707 } 2708 2709 static void mt7531_rgmii_setup(struct mt7530_priv *priv, 2710 phy_interface_t interface, 2711 struct phy_device *phydev) 2712 { 2713 u32 val; 2714 2715 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2716 val |= GP_CLK_EN; 2717 val &= ~GP_MODE_MASK; 2718 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2719 val &= ~CLK_SKEW_IN_MASK; 2720 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2721 val &= ~CLK_SKEW_OUT_MASK; 2722 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2723 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2724 2725 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2726 if (!phydev || phy_driver_is_genphy(phydev)) { 2727 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2728 switch (interface) { 2729 case PHY_INTERFACE_MODE_RGMII: 2730 val |= TXCLK_NO_REVERSE; 2731 val |= RXCLK_NO_DELAY; 2732 break; 2733 case PHY_INTERFACE_MODE_RGMII_RXID: 2734 val |= TXCLK_NO_REVERSE; 2735 break; 2736 case PHY_INTERFACE_MODE_RGMII_TXID: 2737 val |= RXCLK_NO_DELAY; 2738 break; 2739 case PHY_INTERFACE_MODE_RGMII_ID: 2740 break; 2741 default: 2742 break; 2743 } 2744 } 2745 2746 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2747 } 2748 2749 static void 2750 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2751 phy_interface_t interface) 2752 { 2753 struct mt7530_priv *priv = ds->priv; 2754 struct phy_device *phydev; 2755 struct dsa_port *dp; 2756 2757 if (phy_interface_mode_is_rgmii(interface)) { 2758 dp = dsa_to_port(ds, port); 2759 phydev = dp->user->phydev; 2760 mt7531_rgmii_setup(priv, interface, phydev); 2761 } 2762 } 2763 2764 static struct phylink_pcs * 2765 mt753x_phylink_mac_select_pcs(struct phylink_config *config, 2766 phy_interface_t interface) 2767 { 2768 struct dsa_port *dp = dsa_phylink_to_port(config); 2769 struct mt7530_priv *priv = dp->ds->priv; 2770 2771 switch (interface) { 2772 case PHY_INTERFACE_MODE_TRGMII: 2773 return &priv->pcs[dp->index].pcs; 2774 case PHY_INTERFACE_MODE_SGMII: 2775 case PHY_INTERFACE_MODE_1000BASEX: 2776 case PHY_INTERFACE_MODE_2500BASEX: 2777 return priv->ports[dp->index].sgmii_pcs; 2778 default: 2779 return NULL; 2780 } 2781 } 2782 2783 static void 2784 mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2785 const struct phylink_link_state *state) 2786 { 2787 struct dsa_port *dp = dsa_phylink_to_port(config); 2788 struct dsa_switch *ds = dp->ds; 2789 struct mt7530_priv *priv; 2790 int port = dp->index; 2791 2792 priv = ds->priv; 2793 2794 if ((port == 5 || port == 6) && priv->info->mac_port_config) 2795 priv->info->mac_port_config(ds, port, mode, state->interface); 2796 2797 /* Are we connected to external phy */ 2798 if (port == 5 && dsa_is_user_port(ds, 5)) 2799 mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY); 2800 } 2801 2802 static void mt753x_phylink_mac_link_down(struct phylink_config *config, 2803 unsigned int mode, 2804 phy_interface_t interface) 2805 { 2806 struct dsa_port *dp = dsa_phylink_to_port(config); 2807 struct mt7530_priv *priv = dp->ds->priv; 2808 2809 mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK); 2810 } 2811 2812 static void mt753x_phylink_mac_link_up(struct phylink_config *config, 2813 struct phy_device *phydev, 2814 unsigned int mode, 2815 phy_interface_t interface, 2816 int speed, int duplex, 2817 bool tx_pause, bool rx_pause) 2818 { 2819 struct dsa_port *dp = dsa_phylink_to_port(config); 2820 struct mt7530_priv *priv = dp->ds->priv; 2821 u32 mcr; 2822 2823 mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK; 2824 2825 switch (speed) { 2826 case SPEED_1000: 2827 case SPEED_2500: 2828 case SPEED_10000: 2829 mcr |= PMCR_FORCE_SPEED_1000; 2830 break; 2831 case SPEED_100: 2832 mcr |= PMCR_FORCE_SPEED_100; 2833 break; 2834 } 2835 if (duplex == DUPLEX_FULL) { 2836 mcr |= PMCR_FORCE_FDX; 2837 if (tx_pause) 2838 mcr |= PMCR_FORCE_TX_FC_EN; 2839 if (rx_pause) 2840 mcr |= PMCR_FORCE_RX_FC_EN; 2841 } 2842 2843 mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr); 2844 } 2845 2846 static void mt753x_phylink_mac_disable_tx_lpi(struct phylink_config *config) 2847 { 2848 struct dsa_port *dp = dsa_phylink_to_port(config); 2849 struct mt7530_priv *priv = dp->ds->priv; 2850 2851 mt7530_clear(priv, MT753X_PMCR_P(dp->index), 2852 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 2853 } 2854 2855 static int mt753x_phylink_mac_enable_tx_lpi(struct phylink_config *config, 2856 u32 timer, bool tx_clock_stop) 2857 { 2858 struct dsa_port *dp = dsa_phylink_to_port(config); 2859 struct mt7530_priv *priv = dp->ds->priv; 2860 u32 val; 2861 2862 /* If the timer is zero, then set LPI_MODE_EN, which allows the 2863 * system to enter LPI mode immediately rather than waiting for 2864 * the LPI threshold. 2865 */ 2866 if (!timer) 2867 val = LPI_MODE_EN; 2868 else if (FIELD_FIT(LPI_THRESH_MASK, timer)) 2869 val = FIELD_PREP(LPI_THRESH_MASK, timer); 2870 else 2871 val = LPI_THRESH_MASK; 2872 2873 mt7530_rmw(priv, MT753X_PMEEECR_P(dp->index), 2874 LPI_THRESH_MASK | LPI_MODE_EN, val); 2875 2876 mt7530_set(priv, MT753X_PMCR_P(dp->index), 2877 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100); 2878 2879 return 0; 2880 } 2881 2882 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2883 struct phylink_config *config) 2884 { 2885 struct mt7530_priv *priv = ds->priv; 2886 u32 eeecr; 2887 2888 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 2889 2890 config->lpi_capabilities = MAC_100FD | MAC_1000FD | MAC_2500FD; 2891 2892 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port)); 2893 /* tx_lpi_timer should be in microseconds. The time units for 2894 * LPI threshold are unspecified. 2895 */ 2896 config->lpi_timer_default = FIELD_GET(LPI_THRESH_MASK, eeecr); 2897 2898 priv->info->mac_port_get_caps(ds, port, config); 2899 } 2900 2901 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2902 unsigned long *supported, 2903 const struct phylink_link_state *state) 2904 { 2905 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2906 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2907 phy_interface_mode_is_8023z(state->interface)) 2908 phylink_clear(supported, Autoneg); 2909 2910 return 0; 2911 } 2912 2913 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode, 2914 struct phylink_link_state *state) 2915 { 2916 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2917 int port = pcs_to_mt753x_pcs(pcs)->port; 2918 u32 pmsr; 2919 2920 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2921 2922 state->link = (pmsr & PMSR_LINK); 2923 state->an_complete = state->link; 2924 state->duplex = !!(pmsr & PMSR_DPX); 2925 2926 switch (pmsr & PMSR_SPEED_MASK) { 2927 case PMSR_SPEED_10: 2928 state->speed = SPEED_10; 2929 break; 2930 case PMSR_SPEED_100: 2931 state->speed = SPEED_100; 2932 break; 2933 case PMSR_SPEED_1000: 2934 state->speed = SPEED_1000; 2935 break; 2936 default: 2937 state->speed = SPEED_UNKNOWN; 2938 break; 2939 } 2940 2941 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2942 if (pmsr & PMSR_RX_FC) 2943 state->pause |= MLO_PAUSE_RX; 2944 if (pmsr & PMSR_TX_FC) 2945 state->pause |= MLO_PAUSE_TX; 2946 } 2947 2948 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 2949 phy_interface_t interface, 2950 const unsigned long *advertising, 2951 bool permit_pause_to_mac) 2952 { 2953 return 0; 2954 } 2955 2956 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2957 { 2958 } 2959 2960 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2961 .pcs_validate = mt753x_pcs_validate, 2962 .pcs_get_state = mt7530_pcs_get_state, 2963 .pcs_config = mt753x_pcs_config, 2964 .pcs_an_restart = mt7530_pcs_an_restart, 2965 }; 2966 2967 static int 2968 mt753x_setup(struct dsa_switch *ds) 2969 { 2970 struct mt7530_priv *priv = ds->priv; 2971 int ret = priv->info->sw_setup(ds); 2972 int i; 2973 2974 if (ret) 2975 return ret; 2976 2977 ret = mt7530_setup_irq(priv); 2978 if (ret) 2979 return ret; 2980 2981 ret = mt7530_setup_mdio(priv); 2982 if (ret) 2983 return ret; 2984 2985 /* Initialise the PCS devices */ 2986 for (i = 0; i < priv->ds->num_ports; i++) { 2987 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 2988 priv->pcs[i].priv = priv; 2989 priv->pcs[i].port = i; 2990 } 2991 2992 if (priv->create_sgmii) 2993 ret = priv->create_sgmii(priv); 2994 2995 if (ret && priv->irq_domain) 2996 mt7530_free_mdio_irq(priv); 2997 2998 return ret; 2999 } 3000 3001 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3002 struct ethtool_keee *e) 3003 { 3004 if (e->tx_lpi_timer > 0xFFF) 3005 return -EINVAL; 3006 3007 return 0; 3008 } 3009 3010 static void 3011 mt753x_conduit_state_change(struct dsa_switch *ds, 3012 const struct net_device *conduit, 3013 bool operational) 3014 { 3015 struct dsa_port *cpu_dp = conduit->dsa_ptr; 3016 struct mt7530_priv *priv = ds->priv; 3017 int val = 0; 3018 u8 mask; 3019 3020 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be 3021 * forwarded to the numerically smallest CPU port whose conduit 3022 * interface is up. 3023 */ 3024 if (priv->id != ID_MT7530 && priv->id != ID_MT7621) 3025 return; 3026 3027 mask = BIT(cpu_dp->index); 3028 3029 if (operational) 3030 priv->active_cpu_ports |= mask; 3031 else 3032 priv->active_cpu_ports &= ~mask; 3033 3034 if (priv->active_cpu_ports) { 3035 val = MT7530_CPU_EN | 3036 MT7530_CPU_PORT(__ffs(priv->active_cpu_ports)); 3037 } 3038 3039 mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val); 3040 } 3041 3042 static int mt753x_tc_setup_qdisc_tbf(struct dsa_switch *ds, int port, 3043 struct tc_tbf_qopt_offload *qopt) 3044 { 3045 struct tc_tbf_qopt_offload_replace_params *p = &qopt->replace_params; 3046 struct mt7530_priv *priv = ds->priv; 3047 u32 rate = 0; 3048 3049 switch (qopt->command) { 3050 case TC_TBF_REPLACE: 3051 rate = div_u64(p->rate.rate_bytes_ps, 1000) << 3; /* kbps */ 3052 fallthrough; 3053 case TC_TBF_DESTROY: { 3054 u32 val, tick; 3055 3056 mt7530_rmw(priv, MT753X_GERLCR, EGR_BC_MASK, 3057 EGR_BC_CRC_IPG_PREAMBLE); 3058 3059 /* if rate is greater than 10Mbps tick is 1/32 ms, 3060 * 1ms otherwise 3061 */ 3062 tick = rate > 10000 ? 2 : 7; 3063 val = FIELD_PREP(ERLCR_CIR_MASK, (rate >> 5)) | 3064 FIELD_PREP(ERLCR_EN_MASK, !!rate) | 3065 FIELD_PREP(ERLCR_EXP_MASK, tick) | 3066 ERLCR_TBF_MODE_MASK | 3067 FIELD_PREP(ERLCR_MANT_MASK, 0xf); 3068 mt7530_write(priv, MT753X_ERLCR_P(port), val); 3069 break; 3070 } 3071 default: 3072 return -EOPNOTSUPP; 3073 } 3074 3075 return 0; 3076 } 3077 3078 static int mt753x_setup_tc(struct dsa_switch *ds, int port, 3079 enum tc_setup_type type, void *type_data) 3080 { 3081 switch (type) { 3082 case TC_SETUP_QDISC_TBF: 3083 return mt753x_tc_setup_qdisc_tbf(ds, port, type_data); 3084 default: 3085 return -EOPNOTSUPP; 3086 } 3087 } 3088 3089 static int mt7988_setup(struct dsa_switch *ds) 3090 { 3091 struct mt7530_priv *priv = ds->priv; 3092 3093 /* Reset the switch */ 3094 reset_control_assert(priv->rstc); 3095 usleep_range(20, 50); 3096 reset_control_deassert(priv->rstc); 3097 usleep_range(20, 50); 3098 3099 /* Reset the switch PHYs */ 3100 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3101 3102 return mt7531_setup_common(ds); 3103 } 3104 3105 const struct dsa_switch_ops mt7530_switch_ops = { 3106 .get_tag_protocol = mtk_get_tag_protocol, 3107 .setup = mt753x_setup, 3108 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3109 .get_strings = mt7530_get_strings, 3110 .get_ethtool_stats = mt7530_get_ethtool_stats, 3111 .get_sset_count = mt7530_get_sset_count, 3112 .set_ageing_time = mt7530_set_ageing_time, 3113 .port_enable = mt7530_port_enable, 3114 .port_disable = mt7530_port_disable, 3115 .port_change_mtu = mt7530_port_change_mtu, 3116 .port_max_mtu = mt7530_port_max_mtu, 3117 .port_stp_state_set = mt7530_stp_state_set, 3118 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3119 .port_bridge_flags = mt7530_port_bridge_flags, 3120 .port_bridge_join = mt7530_port_bridge_join, 3121 .port_bridge_leave = mt7530_port_bridge_leave, 3122 .port_fdb_add = mt7530_port_fdb_add, 3123 .port_fdb_del = mt7530_port_fdb_del, 3124 .port_fdb_dump = mt7530_port_fdb_dump, 3125 .port_mdb_add = mt7530_port_mdb_add, 3126 .port_mdb_del = mt7530_port_mdb_del, 3127 .port_vlan_filtering = mt7530_port_vlan_filtering, 3128 .port_vlan_add = mt7530_port_vlan_add, 3129 .port_vlan_del = mt7530_port_vlan_del, 3130 .port_mirror_add = mt753x_port_mirror_add, 3131 .port_mirror_del = mt753x_port_mirror_del, 3132 .phylink_get_caps = mt753x_phylink_get_caps, 3133 .support_eee = dsa_supports_eee, 3134 .set_mac_eee = mt753x_set_mac_eee, 3135 .conduit_state_change = mt753x_conduit_state_change, 3136 .port_setup_tc = mt753x_setup_tc, 3137 }; 3138 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3139 3140 static const struct phylink_mac_ops mt753x_phylink_mac_ops = { 3141 .mac_select_pcs = mt753x_phylink_mac_select_pcs, 3142 .mac_config = mt753x_phylink_mac_config, 3143 .mac_link_down = mt753x_phylink_mac_link_down, 3144 .mac_link_up = mt753x_phylink_mac_link_up, 3145 .mac_disable_tx_lpi = mt753x_phylink_mac_disable_tx_lpi, 3146 .mac_enable_tx_lpi = mt753x_phylink_mac_enable_tx_lpi, 3147 }; 3148 3149 const struct mt753x_info mt753x_table[] = { 3150 [ID_MT7621] = { 3151 .id = ID_MT7621, 3152 .pcs_ops = &mt7530_pcs_ops, 3153 .sw_setup = mt7530_setup, 3154 .phy_read_c22 = mt7530_phy_read_c22, 3155 .phy_write_c22 = mt7530_phy_write_c22, 3156 .phy_read_c45 = mt7530_phy_read_c45, 3157 .phy_write_c45 = mt7530_phy_write_c45, 3158 .mac_port_get_caps = mt7530_mac_port_get_caps, 3159 .mac_port_config = mt7530_mac_config, 3160 }, 3161 [ID_MT7530] = { 3162 .id = ID_MT7530, 3163 .pcs_ops = &mt7530_pcs_ops, 3164 .sw_setup = mt7530_setup, 3165 .phy_read_c22 = mt7530_phy_read_c22, 3166 .phy_write_c22 = mt7530_phy_write_c22, 3167 .phy_read_c45 = mt7530_phy_read_c45, 3168 .phy_write_c45 = mt7530_phy_write_c45, 3169 .mac_port_get_caps = mt7530_mac_port_get_caps, 3170 .mac_port_config = mt7530_mac_config, 3171 }, 3172 [ID_MT7531] = { 3173 .id = ID_MT7531, 3174 .pcs_ops = &mt7530_pcs_ops, 3175 .sw_setup = mt7531_setup, 3176 .phy_read_c22 = mt7531_ind_c22_phy_read, 3177 .phy_write_c22 = mt7531_ind_c22_phy_write, 3178 .phy_read_c45 = mt7531_ind_c45_phy_read, 3179 .phy_write_c45 = mt7531_ind_c45_phy_write, 3180 .mac_port_get_caps = mt7531_mac_port_get_caps, 3181 .mac_port_config = mt7531_mac_config, 3182 }, 3183 [ID_MT7988] = { 3184 .id = ID_MT7988, 3185 .pcs_ops = &mt7530_pcs_ops, 3186 .sw_setup = mt7988_setup, 3187 .phy_read_c22 = mt7531_ind_c22_phy_read, 3188 .phy_write_c22 = mt7531_ind_c22_phy_write, 3189 .phy_read_c45 = mt7531_ind_c45_phy_read, 3190 .phy_write_c45 = mt7531_ind_c45_phy_write, 3191 .mac_port_get_caps = mt7988_mac_port_get_caps, 3192 }, 3193 [ID_EN7581] = { 3194 .id = ID_EN7581, 3195 .pcs_ops = &mt7530_pcs_ops, 3196 .sw_setup = mt7988_setup, 3197 .phy_read_c22 = mt7531_ind_c22_phy_read, 3198 .phy_write_c22 = mt7531_ind_c22_phy_write, 3199 .phy_read_c45 = mt7531_ind_c45_phy_read, 3200 .phy_write_c45 = mt7531_ind_c45_phy_write, 3201 .mac_port_get_caps = en7581_mac_port_get_caps, 3202 }, 3203 }; 3204 EXPORT_SYMBOL_GPL(mt753x_table); 3205 3206 int 3207 mt7530_probe_common(struct mt7530_priv *priv) 3208 { 3209 struct device *dev = priv->dev; 3210 3211 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3212 if (!priv->ds) 3213 return -ENOMEM; 3214 3215 priv->ds->dev = dev; 3216 priv->ds->num_ports = MT7530_NUM_PORTS; 3217 3218 /* Get the hardware identifier from the devicetree node. 3219 * We will need it for some of the clock and regulator setup. 3220 */ 3221 priv->info = of_device_get_match_data(dev); 3222 if (!priv->info) 3223 return -EINVAL; 3224 3225 priv->id = priv->info->id; 3226 priv->dev = dev; 3227 priv->ds->priv = priv; 3228 priv->ds->ops = &mt7530_switch_ops; 3229 priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops; 3230 mutex_init(&priv->reg_mutex); 3231 dev_set_drvdata(dev, priv); 3232 3233 return 0; 3234 } 3235 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3236 3237 void 3238 mt7530_remove_common(struct mt7530_priv *priv) 3239 { 3240 if (priv->irq_domain) 3241 mt7530_free_mdio_irq(priv); 3242 3243 dsa_unregister_switch(priv->ds); 3244 3245 mutex_destroy(&priv->reg_mutex); 3246 } 3247 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3248 3249 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3250 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3251 MODULE_LICENSE("GPL"); 3252