1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 148 } 149 150 static void 151 mt7530_mutex_unlock(struct mt7530_priv *priv) 152 { 153 mutex_unlock(&priv->bus->mdio_lock); 154 } 155 156 static void 157 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 158 { 159 mt7530_mutex_lock(priv); 160 161 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 162 163 mt7530_mutex_unlock(priv); 164 } 165 166 static void 167 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 168 { 169 u32 val; 170 171 mt7530_mutex_lock(priv); 172 173 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 174 val &= ~mask; 175 val |= set; 176 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 177 178 mt7530_mutex_unlock(priv); 179 } 180 181 static void 182 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 183 { 184 core_rmw(priv, reg, 0, val); 185 } 186 187 static void 188 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 189 { 190 core_rmw(priv, reg, val, 0); 191 } 192 193 static int 194 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 195 { 196 int ret; 197 198 ret = regmap_write(priv->regmap, reg, val); 199 200 if (ret < 0) 201 dev_err(priv->dev, 202 "failed to write mt7530 register\n"); 203 204 return ret; 205 } 206 207 static u32 208 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 209 { 210 int ret; 211 u32 val; 212 213 ret = regmap_read(priv->regmap, reg, &val); 214 if (ret) { 215 WARN_ON_ONCE(1); 216 dev_err(priv->dev, 217 "failed to read mt7530 register\n"); 218 return 0; 219 } 220 221 return val; 222 } 223 224 static void 225 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 226 { 227 mt7530_mutex_lock(priv); 228 229 mt7530_mii_write(priv, reg, val); 230 231 mt7530_mutex_unlock(priv); 232 } 233 234 static u32 235 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 236 { 237 return mt7530_mii_read(p->priv, p->reg); 238 } 239 240 static u32 241 _mt7530_read(struct mt7530_dummy_poll *p) 242 { 243 u32 val; 244 245 mt7530_mutex_lock(p->priv); 246 247 val = mt7530_mii_read(p->priv, p->reg); 248 249 mt7530_mutex_unlock(p->priv); 250 251 return val; 252 } 253 254 static u32 255 mt7530_read(struct mt7530_priv *priv, u32 reg) 256 { 257 struct mt7530_dummy_poll p; 258 259 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 260 return _mt7530_read(&p); 261 } 262 263 static void 264 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 265 u32 mask, u32 set) 266 { 267 mt7530_mutex_lock(priv); 268 269 regmap_update_bits(priv->regmap, reg, mask, set); 270 271 mt7530_mutex_unlock(priv); 272 } 273 274 static void 275 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 276 { 277 mt7530_rmw(priv, reg, val, val); 278 } 279 280 static void 281 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 282 { 283 mt7530_rmw(priv, reg, val, 0); 284 } 285 286 static int 287 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 288 { 289 u32 val; 290 int ret; 291 struct mt7530_dummy_poll p; 292 293 /* Set the command operating upon the MAC address entries */ 294 val = ATC_BUSY | ATC_MAT(0) | cmd; 295 mt7530_write(priv, MT7530_ATC, val); 296 297 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 298 ret = readx_poll_timeout(_mt7530_read, &p, val, 299 !(val & ATC_BUSY), 20, 20000); 300 if (ret < 0) { 301 dev_err(priv->dev, "reset timeout\n"); 302 return ret; 303 } 304 305 /* Additional sanity for read command if the specified 306 * entry is invalid 307 */ 308 val = mt7530_read(priv, MT7530_ATC); 309 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 310 return -EINVAL; 311 312 if (rsp) 313 *rsp = val; 314 315 return 0; 316 } 317 318 static void 319 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 320 { 321 u32 reg[3]; 322 int i; 323 324 /* Read from ARL table into an array */ 325 for (i = 0; i < 3; i++) { 326 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 327 328 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 329 __func__, __LINE__, i, reg[i]); 330 } 331 332 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 333 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 334 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 335 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 336 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 337 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 338 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 339 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 340 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 341 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 342 } 343 344 static void 345 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 346 u8 port_mask, const u8 *mac, 347 u8 aging, u8 type) 348 { 349 u32 reg[3] = { 0 }; 350 int i; 351 352 reg[1] |= vid & CVID_MASK; 353 reg[1] |= ATA2_IVL; 354 reg[1] |= ATA2_FID(FID_BRIDGED); 355 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 356 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 357 /* STATIC_ENT indicate that entry is static wouldn't 358 * be aged out and STATIC_EMP specified as erasing an 359 * entry 360 */ 361 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 362 reg[1] |= mac[5] << MAC_BYTE_5; 363 reg[1] |= mac[4] << MAC_BYTE_4; 364 reg[0] |= mac[3] << MAC_BYTE_3; 365 reg[0] |= mac[2] << MAC_BYTE_2; 366 reg[0] |= mac[1] << MAC_BYTE_1; 367 reg[0] |= mac[0] << MAC_BYTE_0; 368 369 /* Write array into the ARL table */ 370 for (i = 0; i < 3; i++) 371 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 372 } 373 374 /* Set up switch core clock for MT7530 */ 375 static void mt7530_pll_setup(struct mt7530_priv *priv) 376 { 377 /* Disable core clock */ 378 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 379 380 /* Disable PLL */ 381 core_write(priv, CORE_GSWPLL_GRP1, 0); 382 383 /* Set core clock into 500Mhz */ 384 core_write(priv, CORE_GSWPLL_GRP2, 385 RG_GSWPLL_POSDIV_500M(1) | 386 RG_GSWPLL_FBKDIV_500M(25)); 387 388 /* Enable PLL */ 389 core_write(priv, CORE_GSWPLL_GRP1, 390 RG_GSWPLL_EN_PRE | 391 RG_GSWPLL_POSDIV_200M(2) | 392 RG_GSWPLL_FBKDIV_200M(32)); 393 394 udelay(20); 395 396 /* Enable core clock */ 397 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 398 } 399 400 /* Setup port 6 interface mode and TRGMII TX circuit */ 401 static int 402 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 403 { 404 struct mt7530_priv *priv = ds->priv; 405 u32 ncpo1, ssc_delta, trgint, xtal; 406 407 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 408 409 if (xtal == HWTRAP_XTAL_20MHZ) { 410 dev_err(priv->dev, 411 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 412 __func__); 413 return -EINVAL; 414 } 415 416 switch (interface) { 417 case PHY_INTERFACE_MODE_RGMII: 418 trgint = 0; 419 break; 420 case PHY_INTERFACE_MODE_TRGMII: 421 trgint = 1; 422 if (xtal == HWTRAP_XTAL_25MHZ) 423 ssc_delta = 0x57; 424 else 425 ssc_delta = 0x87; 426 if (priv->id == ID_MT7621) { 427 /* PLL frequency: 150MHz: 1.2GBit */ 428 if (xtal == HWTRAP_XTAL_40MHZ) 429 ncpo1 = 0x0780; 430 if (xtal == HWTRAP_XTAL_25MHZ) 431 ncpo1 = 0x0a00; 432 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 433 if (xtal == HWTRAP_XTAL_40MHZ) 434 ncpo1 = 0x0c80; 435 if (xtal == HWTRAP_XTAL_25MHZ) 436 ncpo1 = 0x1400; 437 } 438 break; 439 default: 440 dev_err(priv->dev, "xMII interface %d not supported\n", 441 interface); 442 return -EINVAL; 443 } 444 445 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 446 P6_INTF_MODE(trgint)); 447 448 if (trgint) { 449 /* Disable the MT7530 TRGMII clocks */ 450 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 451 452 /* Setup the MT7530 TRGMII Tx Clock */ 453 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 454 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 455 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 456 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 457 core_write(priv, CORE_PLL_GROUP4, 458 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 459 RG_SYSPLL_BIAS_LPF_EN); 460 core_write(priv, CORE_PLL_GROUP2, 461 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 462 RG_SYSPLL_POSDIV(1)); 463 core_write(priv, CORE_PLL_GROUP7, 464 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 465 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 466 467 /* Enable the MT7530 TRGMII clocks */ 468 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 469 } 470 471 return 0; 472 } 473 474 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 475 { 476 u32 val; 477 478 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 479 480 return (val & PAD_DUAL_SGMII_EN) != 0; 481 } 482 483 static int 484 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 485 { 486 return 0; 487 } 488 489 static void 490 mt7531_pll_setup(struct mt7530_priv *priv) 491 { 492 u32 top_sig; 493 u32 hwstrap; 494 u32 xtal; 495 u32 val; 496 497 if (mt7531_dual_sgmii_supported(priv)) 498 return; 499 500 val = mt7530_read(priv, MT7531_CREV); 501 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 502 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 503 if ((val & CHIP_REV_M) > 0) 504 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 505 HWTRAP_XTAL_FSEL_25MHZ; 506 else 507 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 508 509 /* Step 1 : Disable MT7531 COREPLL */ 510 val = mt7530_read(priv, MT7531_PLLGP_EN); 511 val &= ~EN_COREPLL; 512 mt7530_write(priv, MT7531_PLLGP_EN, val); 513 514 /* Step 2: switch to XTAL output */ 515 val = mt7530_read(priv, MT7531_PLLGP_EN); 516 val |= SW_CLKSW; 517 mt7530_write(priv, MT7531_PLLGP_EN, val); 518 519 val = mt7530_read(priv, MT7531_PLLGP_CR0); 520 val &= ~RG_COREPLL_EN; 521 mt7530_write(priv, MT7531_PLLGP_CR0, val); 522 523 /* Step 3: disable PLLGP and enable program PLLGP */ 524 val = mt7530_read(priv, MT7531_PLLGP_EN); 525 val |= SW_PLLGP; 526 mt7530_write(priv, MT7531_PLLGP_EN, val); 527 528 /* Step 4: program COREPLL output frequency to 500MHz */ 529 val = mt7530_read(priv, MT7531_PLLGP_CR0); 530 val &= ~RG_COREPLL_POSDIV_M; 531 val |= 2 << RG_COREPLL_POSDIV_S; 532 mt7530_write(priv, MT7531_PLLGP_CR0, val); 533 usleep_range(25, 35); 534 535 switch (xtal) { 536 case HWTRAP_XTAL_FSEL_25MHZ: 537 val = mt7530_read(priv, MT7531_PLLGP_CR0); 538 val &= ~RG_COREPLL_SDM_PCW_M; 539 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 540 mt7530_write(priv, MT7531_PLLGP_CR0, val); 541 break; 542 case HWTRAP_XTAL_FSEL_40MHZ: 543 val = mt7530_read(priv, MT7531_PLLGP_CR0); 544 val &= ~RG_COREPLL_SDM_PCW_M; 545 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 546 mt7530_write(priv, MT7531_PLLGP_CR0, val); 547 break; 548 } 549 550 /* Set feedback divide ratio update signal to high */ 551 val = mt7530_read(priv, MT7531_PLLGP_CR0); 552 val |= RG_COREPLL_SDM_PCW_CHG; 553 mt7530_write(priv, MT7531_PLLGP_CR0, val); 554 /* Wait for at least 16 XTAL clocks */ 555 usleep_range(10, 20); 556 557 /* Step 5: set feedback divide ratio update signal to low */ 558 val = mt7530_read(priv, MT7531_PLLGP_CR0); 559 val &= ~RG_COREPLL_SDM_PCW_CHG; 560 mt7530_write(priv, MT7531_PLLGP_CR0, val); 561 562 /* Enable 325M clock for SGMII */ 563 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 564 565 /* Enable 250SSC clock for RGMII */ 566 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 567 568 /* Step 6: Enable MT7531 PLL */ 569 val = mt7530_read(priv, MT7531_PLLGP_CR0); 570 val |= RG_COREPLL_EN; 571 mt7530_write(priv, MT7531_PLLGP_CR0, val); 572 573 val = mt7530_read(priv, MT7531_PLLGP_EN); 574 val |= EN_COREPLL; 575 mt7530_write(priv, MT7531_PLLGP_EN, val); 576 usleep_range(25, 35); 577 } 578 579 static void 580 mt7530_mib_reset(struct dsa_switch *ds) 581 { 582 struct mt7530_priv *priv = ds->priv; 583 584 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 585 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 586 } 587 588 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 589 { 590 return mdiobus_read_nested(priv->bus, port, regnum); 591 } 592 593 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 594 u16 val) 595 { 596 return mdiobus_write_nested(priv->bus, port, regnum, val); 597 } 598 599 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 600 int devad, int regnum) 601 { 602 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 603 } 604 605 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 606 int regnum, u16 val) 607 { 608 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 609 } 610 611 static int 612 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 613 int regnum) 614 { 615 struct mt7530_dummy_poll p; 616 u32 reg, val; 617 int ret; 618 619 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 620 621 mt7530_mutex_lock(priv); 622 623 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 624 !(val & MT7531_PHY_ACS_ST), 20, 100000); 625 if (ret < 0) { 626 dev_err(priv->dev, "poll timeout\n"); 627 goto out; 628 } 629 630 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 631 MT7531_MDIO_DEV_ADDR(devad) | regnum; 632 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 633 634 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 635 !(val & MT7531_PHY_ACS_ST), 20, 100000); 636 if (ret < 0) { 637 dev_err(priv->dev, "poll timeout\n"); 638 goto out; 639 } 640 641 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 642 MT7531_MDIO_DEV_ADDR(devad); 643 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 644 645 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 646 !(val & MT7531_PHY_ACS_ST), 20, 100000); 647 if (ret < 0) { 648 dev_err(priv->dev, "poll timeout\n"); 649 goto out; 650 } 651 652 ret = val & MT7531_MDIO_RW_DATA_MASK; 653 out: 654 mt7530_mutex_unlock(priv); 655 656 return ret; 657 } 658 659 static int 660 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 661 int regnum, u16 data) 662 { 663 struct mt7530_dummy_poll p; 664 u32 val, reg; 665 int ret; 666 667 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 668 669 mt7530_mutex_lock(priv); 670 671 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 672 !(val & MT7531_PHY_ACS_ST), 20, 100000); 673 if (ret < 0) { 674 dev_err(priv->dev, "poll timeout\n"); 675 goto out; 676 } 677 678 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 679 MT7531_MDIO_DEV_ADDR(devad) | regnum; 680 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 681 682 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 683 !(val & MT7531_PHY_ACS_ST), 20, 100000); 684 if (ret < 0) { 685 dev_err(priv->dev, "poll timeout\n"); 686 goto out; 687 } 688 689 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 690 MT7531_MDIO_DEV_ADDR(devad) | data; 691 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 692 693 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 694 !(val & MT7531_PHY_ACS_ST), 20, 100000); 695 if (ret < 0) { 696 dev_err(priv->dev, "poll timeout\n"); 697 goto out; 698 } 699 700 out: 701 mt7530_mutex_unlock(priv); 702 703 return ret; 704 } 705 706 static int 707 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 708 { 709 struct mt7530_dummy_poll p; 710 int ret; 711 u32 val; 712 713 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 714 715 mt7530_mutex_lock(priv); 716 717 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 718 !(val & MT7531_PHY_ACS_ST), 20, 100000); 719 if (ret < 0) { 720 dev_err(priv->dev, "poll timeout\n"); 721 goto out; 722 } 723 724 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 725 MT7531_MDIO_REG_ADDR(regnum); 726 727 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 728 729 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 730 !(val & MT7531_PHY_ACS_ST), 20, 100000); 731 if (ret < 0) { 732 dev_err(priv->dev, "poll timeout\n"); 733 goto out; 734 } 735 736 ret = val & MT7531_MDIO_RW_DATA_MASK; 737 out: 738 mt7530_mutex_unlock(priv); 739 740 return ret; 741 } 742 743 static int 744 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 745 u16 data) 746 { 747 struct mt7530_dummy_poll p; 748 int ret; 749 u32 reg; 750 751 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 752 753 mt7530_mutex_lock(priv); 754 755 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 756 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 757 if (ret < 0) { 758 dev_err(priv->dev, "poll timeout\n"); 759 goto out; 760 } 761 762 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 763 MT7531_MDIO_REG_ADDR(regnum) | data; 764 765 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 766 767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 768 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 769 if (ret < 0) { 770 dev_err(priv->dev, "poll timeout\n"); 771 goto out; 772 } 773 774 out: 775 mt7530_mutex_unlock(priv); 776 777 return ret; 778 } 779 780 static int 781 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 782 { 783 struct mt7530_priv *priv = bus->priv; 784 785 return priv->info->phy_read_c22(priv, port, regnum); 786 } 787 788 static int 789 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 790 { 791 struct mt7530_priv *priv = bus->priv; 792 793 return priv->info->phy_read_c45(priv, port, devad, regnum); 794 } 795 796 static int 797 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 798 { 799 struct mt7530_priv *priv = bus->priv; 800 801 return priv->info->phy_write_c22(priv, port, regnum, val); 802 } 803 804 static int 805 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 806 u16 val) 807 { 808 struct mt7530_priv *priv = bus->priv; 809 810 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 811 } 812 813 static void 814 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 815 uint8_t *data) 816 { 817 int i; 818 819 if (stringset != ETH_SS_STATS) 820 return; 821 822 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 823 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 824 ETH_GSTRING_LEN); 825 } 826 827 static void 828 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 829 uint64_t *data) 830 { 831 struct mt7530_priv *priv = ds->priv; 832 const struct mt7530_mib_desc *mib; 833 u32 reg, i; 834 u64 hi; 835 836 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 837 mib = &mt7530_mib[i]; 838 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 839 840 data[i] = mt7530_read(priv, reg); 841 if (mib->size == 2) { 842 hi = mt7530_read(priv, reg + 4); 843 data[i] |= hi << 32; 844 } 845 } 846 } 847 848 static int 849 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 850 { 851 if (sset != ETH_SS_STATS) 852 return 0; 853 854 return ARRAY_SIZE(mt7530_mib); 855 } 856 857 static int 858 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 859 { 860 struct mt7530_priv *priv = ds->priv; 861 unsigned int secs = msecs / 1000; 862 unsigned int tmp_age_count; 863 unsigned int error = -1; 864 unsigned int age_count; 865 unsigned int age_unit; 866 867 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 868 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 869 return -ERANGE; 870 871 /* iterate through all possible age_count to find the closest pair */ 872 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 873 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 874 875 if (tmp_age_unit <= AGE_UNIT_MAX) { 876 unsigned int tmp_error = secs - 877 (tmp_age_count + 1) * (tmp_age_unit + 1); 878 879 /* found a closer pair */ 880 if (error > tmp_error) { 881 error = tmp_error; 882 age_count = tmp_age_count; 883 age_unit = tmp_age_unit; 884 } 885 886 /* found the exact match, so break the loop */ 887 if (!error) 888 break; 889 } 890 } 891 892 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 893 894 return 0; 895 } 896 897 static const char *p5_intf_modes(unsigned int p5_interface) 898 { 899 switch (p5_interface) { 900 case P5_DISABLED: 901 return "DISABLED"; 902 case P5_INTF_SEL_PHY_P0: 903 return "PHY P0"; 904 case P5_INTF_SEL_PHY_P4: 905 return "PHY P4"; 906 case P5_INTF_SEL_GMAC5: 907 return "GMAC5"; 908 case P5_INTF_SEL_GMAC5_SGMII: 909 return "GMAC5_SGMII"; 910 default: 911 return "unknown"; 912 } 913 } 914 915 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 916 { 917 struct mt7530_priv *priv = ds->priv; 918 u8 tx_delay = 0; 919 int val; 920 921 mutex_lock(&priv->reg_mutex); 922 923 val = mt7530_read(priv, MT7530_MHWTRAP); 924 925 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 926 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 927 928 switch (priv->p5_intf_sel) { 929 case P5_INTF_SEL_PHY_P0: 930 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 931 val |= MHWTRAP_PHY0_SEL; 932 fallthrough; 933 case P5_INTF_SEL_PHY_P4: 934 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 935 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 936 937 /* Setup the MAC by default for the cpu port */ 938 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 939 break; 940 case P5_INTF_SEL_GMAC5: 941 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 942 val &= ~MHWTRAP_P5_DIS; 943 break; 944 case P5_DISABLED: 945 interface = PHY_INTERFACE_MODE_NA; 946 break; 947 default: 948 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 949 priv->p5_intf_sel); 950 goto unlock_exit; 951 } 952 953 /* Setup RGMII settings */ 954 if (phy_interface_mode_is_rgmii(interface)) { 955 val |= MHWTRAP_P5_RGMII_MODE; 956 957 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 958 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 959 960 /* Don't set delay in DSA mode */ 961 if (!dsa_is_dsa_port(priv->ds, 5) && 962 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 963 interface == PHY_INTERFACE_MODE_RGMII_ID)) 964 tx_delay = 4; /* n * 0.5 ns */ 965 966 /* P5 RGMII TX Clock Control: delay x */ 967 mt7530_write(priv, MT7530_P5RGMIITXCR, 968 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 969 970 /* reduce P5 RGMII Tx driving, 8mA */ 971 mt7530_write(priv, MT7530_IO_DRV_CR, 972 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 973 } 974 975 mt7530_write(priv, MT7530_MHWTRAP, val); 976 977 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 978 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 979 980 priv->p5_interface = interface; 981 982 unlock_exit: 983 mutex_unlock(&priv->reg_mutex); 984 } 985 986 static int 987 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 988 { 989 struct mt7530_priv *priv = ds->priv; 990 int ret; 991 992 /* Setup max capability of CPU port at first */ 993 if (priv->info->cpu_port_config) { 994 ret = priv->info->cpu_port_config(ds, port); 995 if (ret) 996 return ret; 997 } 998 999 /* Enable Mediatek header mode on the cpu port */ 1000 mt7530_write(priv, MT7530_PVC_P(port), 1001 PORT_SPEC_TAG); 1002 1003 /* Disable flooding by default */ 1004 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1005 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1006 1007 /* Set CPU port number */ 1008 if (priv->id == ID_MT7621) 1009 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1010 1011 /* CPU port gets connected to all user ports of 1012 * the switch. 1013 */ 1014 mt7530_write(priv, MT7530_PCR_P(port), 1015 PCR_MATRIX(dsa_user_ports(priv->ds))); 1016 1017 /* Set to fallback mode for independent VLAN learning */ 1018 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1019 MT7530_PORT_FALLBACK_MODE); 1020 1021 return 0; 1022 } 1023 1024 static int 1025 mt7530_port_enable(struct dsa_switch *ds, int port, 1026 struct phy_device *phy) 1027 { 1028 struct dsa_port *dp = dsa_to_port(ds, port); 1029 struct mt7530_priv *priv = ds->priv; 1030 1031 mutex_lock(&priv->reg_mutex); 1032 1033 /* Allow the user port gets connected to the cpu port and also 1034 * restore the port matrix if the port is the member of a certain 1035 * bridge. 1036 */ 1037 if (dsa_port_is_user(dp)) { 1038 struct dsa_port *cpu_dp = dp->cpu_dp; 1039 1040 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1041 } 1042 priv->ports[port].enable = true; 1043 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1044 priv->ports[port].pm); 1045 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1046 1047 mutex_unlock(&priv->reg_mutex); 1048 1049 return 0; 1050 } 1051 1052 static void 1053 mt7530_port_disable(struct dsa_switch *ds, int port) 1054 { 1055 struct mt7530_priv *priv = ds->priv; 1056 1057 mutex_lock(&priv->reg_mutex); 1058 1059 /* Clear up all port matrix which could be restored in the next 1060 * enablement for the port. 1061 */ 1062 priv->ports[port].enable = false; 1063 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1064 PCR_MATRIX_CLR); 1065 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1066 1067 mutex_unlock(&priv->reg_mutex); 1068 } 1069 1070 static int 1071 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1072 { 1073 struct mt7530_priv *priv = ds->priv; 1074 int length; 1075 u32 val; 1076 1077 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1078 * largest MTU of the slave ports. Because the switch only has a global 1079 * RX length register, only allowing CPU port here is enough. 1080 */ 1081 if (!dsa_is_cpu_port(ds, port)) 1082 return 0; 1083 1084 mt7530_mutex_lock(priv); 1085 1086 val = mt7530_mii_read(priv, MT7530_GMACCR); 1087 val &= ~MAX_RX_PKT_LEN_MASK; 1088 1089 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1090 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1091 if (length <= 1522) { 1092 val |= MAX_RX_PKT_LEN_1522; 1093 } else if (length <= 1536) { 1094 val |= MAX_RX_PKT_LEN_1536; 1095 } else if (length <= 1552) { 1096 val |= MAX_RX_PKT_LEN_1552; 1097 } else { 1098 val &= ~MAX_RX_JUMBO_MASK; 1099 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1100 val |= MAX_RX_PKT_LEN_JUMBO; 1101 } 1102 1103 mt7530_mii_write(priv, MT7530_GMACCR, val); 1104 1105 mt7530_mutex_unlock(priv); 1106 1107 return 0; 1108 } 1109 1110 static int 1111 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1112 { 1113 return MT7530_MAX_MTU; 1114 } 1115 1116 static void 1117 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1118 { 1119 struct mt7530_priv *priv = ds->priv; 1120 u32 stp_state; 1121 1122 switch (state) { 1123 case BR_STATE_DISABLED: 1124 stp_state = MT7530_STP_DISABLED; 1125 break; 1126 case BR_STATE_BLOCKING: 1127 stp_state = MT7530_STP_BLOCKING; 1128 break; 1129 case BR_STATE_LISTENING: 1130 stp_state = MT7530_STP_LISTENING; 1131 break; 1132 case BR_STATE_LEARNING: 1133 stp_state = MT7530_STP_LEARNING; 1134 break; 1135 case BR_STATE_FORWARDING: 1136 default: 1137 stp_state = MT7530_STP_FORWARDING; 1138 break; 1139 } 1140 1141 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1142 FID_PST(FID_BRIDGED, stp_state)); 1143 } 1144 1145 static int 1146 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1147 struct switchdev_brport_flags flags, 1148 struct netlink_ext_ack *extack) 1149 { 1150 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1151 BR_BCAST_FLOOD)) 1152 return -EINVAL; 1153 1154 return 0; 1155 } 1156 1157 static int 1158 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1159 struct switchdev_brport_flags flags, 1160 struct netlink_ext_ack *extack) 1161 { 1162 struct mt7530_priv *priv = ds->priv; 1163 1164 if (flags.mask & BR_LEARNING) 1165 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1166 flags.val & BR_LEARNING ? 0 : SA_DIS); 1167 1168 if (flags.mask & BR_FLOOD) 1169 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1170 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1171 1172 if (flags.mask & BR_MCAST_FLOOD) 1173 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1174 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1175 1176 if (flags.mask & BR_BCAST_FLOOD) 1177 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1178 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1179 1180 return 0; 1181 } 1182 1183 static int 1184 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1185 struct dsa_bridge bridge, bool *tx_fwd_offload, 1186 struct netlink_ext_ack *extack) 1187 { 1188 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1189 struct dsa_port *cpu_dp = dp->cpu_dp; 1190 u32 port_bitmap = BIT(cpu_dp->index); 1191 struct mt7530_priv *priv = ds->priv; 1192 1193 mutex_lock(&priv->reg_mutex); 1194 1195 dsa_switch_for_each_user_port(other_dp, ds) { 1196 int other_port = other_dp->index; 1197 1198 if (dp == other_dp) 1199 continue; 1200 1201 /* Add this port to the port matrix of the other ports in the 1202 * same bridge. If the port is disabled, port matrix is kept 1203 * and not being setup until the port becomes enabled. 1204 */ 1205 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1206 continue; 1207 1208 if (priv->ports[other_port].enable) 1209 mt7530_set(priv, MT7530_PCR_P(other_port), 1210 PCR_MATRIX(BIT(port))); 1211 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1212 1213 port_bitmap |= BIT(other_port); 1214 } 1215 1216 /* Add the all other ports to this port matrix. */ 1217 if (priv->ports[port].enable) 1218 mt7530_rmw(priv, MT7530_PCR_P(port), 1219 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1220 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1221 1222 /* Set to fallback mode for independent VLAN learning */ 1223 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1224 MT7530_PORT_FALLBACK_MODE); 1225 1226 mutex_unlock(&priv->reg_mutex); 1227 1228 return 0; 1229 } 1230 1231 static void 1232 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1233 { 1234 struct mt7530_priv *priv = ds->priv; 1235 bool all_user_ports_removed = true; 1236 int i; 1237 1238 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1239 * bridge. Don't set standalone ports to fallback mode. 1240 */ 1241 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1242 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1243 MT7530_PORT_FALLBACK_MODE); 1244 1245 mt7530_rmw(priv, MT7530_PVC_P(port), 1246 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1247 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1248 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1249 MT7530_VLAN_ACC_ALL); 1250 1251 /* Set PVID to 0 */ 1252 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1253 G0_PORT_VID_DEF); 1254 1255 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1256 if (dsa_is_user_port(ds, i) && 1257 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1258 all_user_ports_removed = false; 1259 break; 1260 } 1261 } 1262 1263 /* CPU port also does the same thing until all user ports belonging to 1264 * the CPU port get out of VLAN filtering mode. 1265 */ 1266 if (all_user_ports_removed) { 1267 struct dsa_port *dp = dsa_to_port(ds, port); 1268 struct dsa_port *cpu_dp = dp->cpu_dp; 1269 1270 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1271 PCR_MATRIX(dsa_user_ports(priv->ds))); 1272 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1273 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1274 } 1275 } 1276 1277 static void 1278 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1279 { 1280 struct mt7530_priv *priv = ds->priv; 1281 1282 /* Trapped into security mode allows packet forwarding through VLAN 1283 * table lookup. 1284 */ 1285 if (dsa_is_user_port(ds, port)) { 1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1287 MT7530_PORT_SECURITY_MODE); 1288 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1289 G0_PORT_VID(priv->ports[port].pvid)); 1290 1291 /* Only accept tagged frames if PVID is not set */ 1292 if (!priv->ports[port].pvid) 1293 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1294 MT7530_VLAN_ACC_TAGGED); 1295 1296 /* Set the port as a user port which is to be able to recognize 1297 * VID from incoming packets before fetching entry within the 1298 * VLAN table. 1299 */ 1300 mt7530_rmw(priv, MT7530_PVC_P(port), 1301 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1302 VLAN_ATTR(MT7530_VLAN_USER) | 1303 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1304 } else { 1305 /* Also set CPU ports to the "user" VLAN port attribute, to 1306 * allow VLAN classification, but keep the EG_TAG attribute as 1307 * "consistent" (i.o.w. don't change its value) for packets 1308 * received by the switch from the CPU, so that tagged packets 1309 * are forwarded to user ports as tagged, and untagged as 1310 * untagged. 1311 */ 1312 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1313 VLAN_ATTR(MT7530_VLAN_USER)); 1314 } 1315 } 1316 1317 static void 1318 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1319 struct dsa_bridge bridge) 1320 { 1321 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1322 struct dsa_port *cpu_dp = dp->cpu_dp; 1323 struct mt7530_priv *priv = ds->priv; 1324 1325 mutex_lock(&priv->reg_mutex); 1326 1327 dsa_switch_for_each_user_port(other_dp, ds) { 1328 int other_port = other_dp->index; 1329 1330 if (dp == other_dp) 1331 continue; 1332 1333 /* Remove this port from the port matrix of the other ports 1334 * in the same bridge. If the port is disabled, port matrix 1335 * is kept and not being setup until the port becomes enabled. 1336 */ 1337 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1338 continue; 1339 1340 if (priv->ports[other_port].enable) 1341 mt7530_clear(priv, MT7530_PCR_P(other_port), 1342 PCR_MATRIX(BIT(port))); 1343 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1344 } 1345 1346 /* Set the cpu port to be the only one in the port matrix of 1347 * this port. 1348 */ 1349 if (priv->ports[port].enable) 1350 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1351 PCR_MATRIX(BIT(cpu_dp->index))); 1352 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1353 1354 /* When a port is removed from the bridge, the port would be set up 1355 * back to the default as is at initial boot which is a VLAN-unaware 1356 * port. 1357 */ 1358 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1359 MT7530_PORT_MATRIX_MODE); 1360 1361 mutex_unlock(&priv->reg_mutex); 1362 } 1363 1364 static int 1365 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1366 const unsigned char *addr, u16 vid, 1367 struct dsa_db db) 1368 { 1369 struct mt7530_priv *priv = ds->priv; 1370 int ret; 1371 u8 port_mask = BIT(port); 1372 1373 mutex_lock(&priv->reg_mutex); 1374 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1375 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1376 mutex_unlock(&priv->reg_mutex); 1377 1378 return ret; 1379 } 1380 1381 static int 1382 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1383 const unsigned char *addr, u16 vid, 1384 struct dsa_db db) 1385 { 1386 struct mt7530_priv *priv = ds->priv; 1387 int ret; 1388 u8 port_mask = BIT(port); 1389 1390 mutex_lock(&priv->reg_mutex); 1391 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1392 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1393 mutex_unlock(&priv->reg_mutex); 1394 1395 return ret; 1396 } 1397 1398 static int 1399 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1400 dsa_fdb_dump_cb_t *cb, void *data) 1401 { 1402 struct mt7530_priv *priv = ds->priv; 1403 struct mt7530_fdb _fdb = { 0 }; 1404 int cnt = MT7530_NUM_FDB_RECORDS; 1405 int ret = 0; 1406 u32 rsp = 0; 1407 1408 mutex_lock(&priv->reg_mutex); 1409 1410 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1411 if (ret < 0) 1412 goto err; 1413 1414 do { 1415 if (rsp & ATC_SRCH_HIT) { 1416 mt7530_fdb_read(priv, &_fdb); 1417 if (_fdb.port_mask & BIT(port)) { 1418 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1419 data); 1420 if (ret < 0) 1421 break; 1422 } 1423 } 1424 } while (--cnt && 1425 !(rsp & ATC_SRCH_END) && 1426 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1427 err: 1428 mutex_unlock(&priv->reg_mutex); 1429 1430 return 0; 1431 } 1432 1433 static int 1434 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1435 const struct switchdev_obj_port_mdb *mdb, 1436 struct dsa_db db) 1437 { 1438 struct mt7530_priv *priv = ds->priv; 1439 const u8 *addr = mdb->addr; 1440 u16 vid = mdb->vid; 1441 u8 port_mask = 0; 1442 int ret; 1443 1444 mutex_lock(&priv->reg_mutex); 1445 1446 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1447 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1448 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1449 & PORT_MAP_MASK; 1450 1451 port_mask |= BIT(port); 1452 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1453 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1454 1455 mutex_unlock(&priv->reg_mutex); 1456 1457 return ret; 1458 } 1459 1460 static int 1461 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1462 const struct switchdev_obj_port_mdb *mdb, 1463 struct dsa_db db) 1464 { 1465 struct mt7530_priv *priv = ds->priv; 1466 const u8 *addr = mdb->addr; 1467 u16 vid = mdb->vid; 1468 u8 port_mask = 0; 1469 int ret; 1470 1471 mutex_lock(&priv->reg_mutex); 1472 1473 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1474 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1475 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1476 & PORT_MAP_MASK; 1477 1478 port_mask &= ~BIT(port); 1479 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1480 port_mask ? STATIC_ENT : STATIC_EMP); 1481 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1482 1483 mutex_unlock(&priv->reg_mutex); 1484 1485 return ret; 1486 } 1487 1488 static int 1489 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1490 { 1491 struct mt7530_dummy_poll p; 1492 u32 val; 1493 int ret; 1494 1495 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1496 mt7530_write(priv, MT7530_VTCR, val); 1497 1498 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1499 ret = readx_poll_timeout(_mt7530_read, &p, val, 1500 !(val & VTCR_BUSY), 20, 20000); 1501 if (ret < 0) { 1502 dev_err(priv->dev, "poll timeout\n"); 1503 return ret; 1504 } 1505 1506 val = mt7530_read(priv, MT7530_VTCR); 1507 if (val & VTCR_INVALID) { 1508 dev_err(priv->dev, "read VTCR invalid\n"); 1509 return -EINVAL; 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int 1516 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1517 struct netlink_ext_ack *extack) 1518 { 1519 struct dsa_port *dp = dsa_to_port(ds, port); 1520 struct dsa_port *cpu_dp = dp->cpu_dp; 1521 1522 if (vlan_filtering) { 1523 /* The port is being kept as VLAN-unaware port when bridge is 1524 * set up with vlan_filtering not being set, Otherwise, the 1525 * port and the corresponding CPU port is required the setup 1526 * for becoming a VLAN-aware port. 1527 */ 1528 mt7530_port_set_vlan_aware(ds, port); 1529 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1530 } else { 1531 mt7530_port_set_vlan_unaware(ds, port); 1532 } 1533 1534 return 0; 1535 } 1536 1537 static void 1538 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1539 struct mt7530_hw_vlan_entry *entry) 1540 { 1541 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1542 u8 new_members; 1543 u32 val; 1544 1545 new_members = entry->old_members | BIT(entry->port); 1546 1547 /* Validate the entry with independent learning, create egress tag per 1548 * VLAN and joining the port as one of the port members. 1549 */ 1550 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1551 VLAN_VALID; 1552 mt7530_write(priv, MT7530_VAWD1, val); 1553 1554 /* Decide whether adding tag or not for those outgoing packets from the 1555 * port inside the VLAN. 1556 * CPU port is always taken as a tagged port for serving more than one 1557 * VLANs across and also being applied with egress type stack mode for 1558 * that VLAN tags would be appended after hardware special tag used as 1559 * DSA tag. 1560 */ 1561 if (dsa_port_is_cpu(dp)) 1562 val = MT7530_VLAN_EGRESS_STACK; 1563 else if (entry->untagged) 1564 val = MT7530_VLAN_EGRESS_UNTAG; 1565 else 1566 val = MT7530_VLAN_EGRESS_TAG; 1567 mt7530_rmw(priv, MT7530_VAWD2, 1568 ETAG_CTRL_P_MASK(entry->port), 1569 ETAG_CTRL_P(entry->port, val)); 1570 } 1571 1572 static void 1573 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1574 struct mt7530_hw_vlan_entry *entry) 1575 { 1576 u8 new_members; 1577 u32 val; 1578 1579 new_members = entry->old_members & ~BIT(entry->port); 1580 1581 val = mt7530_read(priv, MT7530_VAWD1); 1582 if (!(val & VLAN_VALID)) { 1583 dev_err(priv->dev, 1584 "Cannot be deleted due to invalid entry\n"); 1585 return; 1586 } 1587 1588 if (new_members) { 1589 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1590 VLAN_VALID; 1591 mt7530_write(priv, MT7530_VAWD1, val); 1592 } else { 1593 mt7530_write(priv, MT7530_VAWD1, 0); 1594 mt7530_write(priv, MT7530_VAWD2, 0); 1595 } 1596 } 1597 1598 static void 1599 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1600 struct mt7530_hw_vlan_entry *entry, 1601 mt7530_vlan_op vlan_op) 1602 { 1603 u32 val; 1604 1605 /* Fetch entry */ 1606 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1607 1608 val = mt7530_read(priv, MT7530_VAWD1); 1609 1610 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1611 1612 /* Manipulate entry */ 1613 vlan_op(priv, entry); 1614 1615 /* Flush result to hardware */ 1616 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1617 } 1618 1619 static int 1620 mt7530_setup_vlan0(struct mt7530_priv *priv) 1621 { 1622 u32 val; 1623 1624 /* Validate the entry with independent learning, keep the original 1625 * ingress tag attribute. 1626 */ 1627 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1628 VLAN_VALID; 1629 mt7530_write(priv, MT7530_VAWD1, val); 1630 1631 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1632 } 1633 1634 static int 1635 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1636 const struct switchdev_obj_port_vlan *vlan, 1637 struct netlink_ext_ack *extack) 1638 { 1639 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1640 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1641 struct mt7530_hw_vlan_entry new_entry; 1642 struct mt7530_priv *priv = ds->priv; 1643 1644 mutex_lock(&priv->reg_mutex); 1645 1646 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1647 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1648 1649 if (pvid) { 1650 priv->ports[port].pvid = vlan->vid; 1651 1652 /* Accept all frames if PVID is set */ 1653 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1654 MT7530_VLAN_ACC_ALL); 1655 1656 /* Only configure PVID if VLAN filtering is enabled */ 1657 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1658 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1659 G0_PORT_VID_MASK, 1660 G0_PORT_VID(vlan->vid)); 1661 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1662 /* This VLAN is overwritten without PVID, so unset it */ 1663 priv->ports[port].pvid = G0_PORT_VID_DEF; 1664 1665 /* Only accept tagged frames if the port is VLAN-aware */ 1666 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1667 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1668 MT7530_VLAN_ACC_TAGGED); 1669 1670 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1671 G0_PORT_VID_DEF); 1672 } 1673 1674 mutex_unlock(&priv->reg_mutex); 1675 1676 return 0; 1677 } 1678 1679 static int 1680 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1681 const struct switchdev_obj_port_vlan *vlan) 1682 { 1683 struct mt7530_hw_vlan_entry target_entry; 1684 struct mt7530_priv *priv = ds->priv; 1685 1686 mutex_lock(&priv->reg_mutex); 1687 1688 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1689 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1690 mt7530_hw_vlan_del); 1691 1692 /* PVID is being restored to the default whenever the PVID port 1693 * is being removed from the VLAN. 1694 */ 1695 if (priv->ports[port].pvid == vlan->vid) { 1696 priv->ports[port].pvid = G0_PORT_VID_DEF; 1697 1698 /* Only accept tagged frames if the port is VLAN-aware */ 1699 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1700 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1701 MT7530_VLAN_ACC_TAGGED); 1702 1703 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1704 G0_PORT_VID_DEF); 1705 } 1706 1707 1708 mutex_unlock(&priv->reg_mutex); 1709 1710 return 0; 1711 } 1712 1713 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1714 { 1715 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1716 MIRROR_PORT(val); 1717 } 1718 1719 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1720 { 1721 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1722 MIRROR_PORT(val); 1723 } 1724 1725 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1726 struct dsa_mall_mirror_tc_entry *mirror, 1727 bool ingress, struct netlink_ext_ack *extack) 1728 { 1729 struct mt7530_priv *priv = ds->priv; 1730 int monitor_port; 1731 u32 val; 1732 1733 /* Check for existent entry */ 1734 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1735 return -EEXIST; 1736 1737 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1738 1739 /* MT7530 only supports one monitor port */ 1740 monitor_port = mt753x_mirror_port_get(priv->id, val); 1741 if (val & MT753X_MIRROR_EN(priv->id) && 1742 monitor_port != mirror->to_local_port) 1743 return -EEXIST; 1744 1745 val |= MT753X_MIRROR_EN(priv->id); 1746 val &= ~MT753X_MIRROR_MASK(priv->id); 1747 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1748 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1749 1750 val = mt7530_read(priv, MT7530_PCR_P(port)); 1751 if (ingress) { 1752 val |= PORT_RX_MIR; 1753 priv->mirror_rx |= BIT(port); 1754 } else { 1755 val |= PORT_TX_MIR; 1756 priv->mirror_tx |= BIT(port); 1757 } 1758 mt7530_write(priv, MT7530_PCR_P(port), val); 1759 1760 return 0; 1761 } 1762 1763 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1764 struct dsa_mall_mirror_tc_entry *mirror) 1765 { 1766 struct mt7530_priv *priv = ds->priv; 1767 u32 val; 1768 1769 val = mt7530_read(priv, MT7530_PCR_P(port)); 1770 if (mirror->ingress) { 1771 val &= ~PORT_RX_MIR; 1772 priv->mirror_rx &= ~BIT(port); 1773 } else { 1774 val &= ~PORT_TX_MIR; 1775 priv->mirror_tx &= ~BIT(port); 1776 } 1777 mt7530_write(priv, MT7530_PCR_P(port), val); 1778 1779 if (!priv->mirror_rx && !priv->mirror_tx) { 1780 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1781 val &= ~MT753X_MIRROR_EN(priv->id); 1782 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1783 } 1784 } 1785 1786 static enum dsa_tag_protocol 1787 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1788 enum dsa_tag_protocol mp) 1789 { 1790 return DSA_TAG_PROTO_MTK; 1791 } 1792 1793 #ifdef CONFIG_GPIOLIB 1794 static inline u32 1795 mt7530_gpio_to_bit(unsigned int offset) 1796 { 1797 /* Map GPIO offset to register bit 1798 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1799 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1800 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1801 * [14:12] port 3 LED 0..2 as GPIO 9..11 1802 * [18:16] port 4 LED 0..2 as GPIO 12..14 1803 */ 1804 return BIT(offset + offset / 3); 1805 } 1806 1807 static int 1808 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1809 { 1810 struct mt7530_priv *priv = gpiochip_get_data(gc); 1811 u32 bit = mt7530_gpio_to_bit(offset); 1812 1813 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1814 } 1815 1816 static void 1817 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1818 { 1819 struct mt7530_priv *priv = gpiochip_get_data(gc); 1820 u32 bit = mt7530_gpio_to_bit(offset); 1821 1822 if (value) 1823 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1824 else 1825 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1826 } 1827 1828 static int 1829 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1830 { 1831 struct mt7530_priv *priv = gpiochip_get_data(gc); 1832 u32 bit = mt7530_gpio_to_bit(offset); 1833 1834 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1835 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1836 } 1837 1838 static int 1839 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1840 { 1841 struct mt7530_priv *priv = gpiochip_get_data(gc); 1842 u32 bit = mt7530_gpio_to_bit(offset); 1843 1844 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1845 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1846 1847 return 0; 1848 } 1849 1850 static int 1851 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1852 { 1853 struct mt7530_priv *priv = gpiochip_get_data(gc); 1854 u32 bit = mt7530_gpio_to_bit(offset); 1855 1856 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1857 1858 if (value) 1859 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1860 else 1861 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1862 1863 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1864 1865 return 0; 1866 } 1867 1868 static int 1869 mt7530_setup_gpio(struct mt7530_priv *priv) 1870 { 1871 struct device *dev = priv->dev; 1872 struct gpio_chip *gc; 1873 1874 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1875 if (!gc) 1876 return -ENOMEM; 1877 1878 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1879 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1880 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1881 1882 gc->label = "mt7530"; 1883 gc->parent = dev; 1884 gc->owner = THIS_MODULE; 1885 gc->get_direction = mt7530_gpio_get_direction; 1886 gc->direction_input = mt7530_gpio_direction_input; 1887 gc->direction_output = mt7530_gpio_direction_output; 1888 gc->get = mt7530_gpio_get; 1889 gc->set = mt7530_gpio_set; 1890 gc->base = -1; 1891 gc->ngpio = 15; 1892 gc->can_sleep = true; 1893 1894 return devm_gpiochip_add_data(dev, gc, priv); 1895 } 1896 #endif /* CONFIG_GPIOLIB */ 1897 1898 static irqreturn_t 1899 mt7530_irq_thread_fn(int irq, void *dev_id) 1900 { 1901 struct mt7530_priv *priv = dev_id; 1902 bool handled = false; 1903 u32 val; 1904 int p; 1905 1906 mt7530_mutex_lock(priv); 1907 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1908 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1909 mt7530_mutex_unlock(priv); 1910 1911 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1912 if (BIT(p) & val) { 1913 unsigned int irq; 1914 1915 irq = irq_find_mapping(priv->irq_domain, p); 1916 handle_nested_irq(irq); 1917 handled = true; 1918 } 1919 } 1920 1921 return IRQ_RETVAL(handled); 1922 } 1923 1924 static void 1925 mt7530_irq_mask(struct irq_data *d) 1926 { 1927 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1928 1929 priv->irq_enable &= ~BIT(d->hwirq); 1930 } 1931 1932 static void 1933 mt7530_irq_unmask(struct irq_data *d) 1934 { 1935 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1936 1937 priv->irq_enable |= BIT(d->hwirq); 1938 } 1939 1940 static void 1941 mt7530_irq_bus_lock(struct irq_data *d) 1942 { 1943 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1944 1945 mt7530_mutex_lock(priv); 1946 } 1947 1948 static void 1949 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1950 { 1951 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1952 1953 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1954 mt7530_mutex_unlock(priv); 1955 } 1956 1957 static struct irq_chip mt7530_irq_chip = { 1958 .name = KBUILD_MODNAME, 1959 .irq_mask = mt7530_irq_mask, 1960 .irq_unmask = mt7530_irq_unmask, 1961 .irq_bus_lock = mt7530_irq_bus_lock, 1962 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1963 }; 1964 1965 static int 1966 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1967 irq_hw_number_t hwirq) 1968 { 1969 irq_set_chip_data(irq, domain->host_data); 1970 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1971 irq_set_nested_thread(irq, true); 1972 irq_set_noprobe(irq); 1973 1974 return 0; 1975 } 1976 1977 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1978 .map = mt7530_irq_map, 1979 .xlate = irq_domain_xlate_onecell, 1980 }; 1981 1982 static void 1983 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1984 { 1985 struct dsa_switch *ds = priv->ds; 1986 int p; 1987 1988 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1989 if (BIT(p) & ds->phys_mii_mask) { 1990 unsigned int irq; 1991 1992 irq = irq_create_mapping(priv->irq_domain, p); 1993 ds->slave_mii_bus->irq[p] = irq; 1994 } 1995 } 1996 } 1997 1998 static int 1999 mt7530_setup_irq(struct mt7530_priv *priv) 2000 { 2001 struct device *dev = priv->dev; 2002 struct device_node *np = dev->of_node; 2003 int ret; 2004 2005 if (!of_property_read_bool(np, "interrupt-controller")) { 2006 dev_info(dev, "no interrupt support\n"); 2007 return 0; 2008 } 2009 2010 priv->irq = of_irq_get(np, 0); 2011 if (priv->irq <= 0) { 2012 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2013 return priv->irq ? : -EINVAL; 2014 } 2015 2016 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2017 &mt7530_irq_domain_ops, priv); 2018 if (!priv->irq_domain) { 2019 dev_err(dev, "failed to create IRQ domain\n"); 2020 return -ENOMEM; 2021 } 2022 2023 /* This register must be set for MT7530 to properly fire interrupts */ 2024 if (priv->id != ID_MT7531) 2025 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2026 2027 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2028 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2029 if (ret) { 2030 irq_domain_remove(priv->irq_domain); 2031 dev_err(dev, "failed to request IRQ: %d\n", ret); 2032 return ret; 2033 } 2034 2035 return 0; 2036 } 2037 2038 static void 2039 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2040 { 2041 int p; 2042 2043 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2044 if (BIT(p) & priv->ds->phys_mii_mask) { 2045 unsigned int irq; 2046 2047 irq = irq_find_mapping(priv->irq_domain, p); 2048 irq_dispose_mapping(irq); 2049 } 2050 } 2051 } 2052 2053 static void 2054 mt7530_free_irq_common(struct mt7530_priv *priv) 2055 { 2056 free_irq(priv->irq, priv); 2057 irq_domain_remove(priv->irq_domain); 2058 } 2059 2060 static void 2061 mt7530_free_irq(struct mt7530_priv *priv) 2062 { 2063 mt7530_free_mdio_irq(priv); 2064 mt7530_free_irq_common(priv); 2065 } 2066 2067 static int 2068 mt7530_setup_mdio(struct mt7530_priv *priv) 2069 { 2070 struct dsa_switch *ds = priv->ds; 2071 struct device *dev = priv->dev; 2072 struct mii_bus *bus; 2073 static int idx; 2074 int ret; 2075 2076 bus = devm_mdiobus_alloc(dev); 2077 if (!bus) 2078 return -ENOMEM; 2079 2080 ds->slave_mii_bus = bus; 2081 bus->priv = priv; 2082 bus->name = KBUILD_MODNAME "-mii"; 2083 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2084 bus->read = mt753x_phy_read_c22; 2085 bus->write = mt753x_phy_write_c22; 2086 bus->read_c45 = mt753x_phy_read_c45; 2087 bus->write_c45 = mt753x_phy_write_c45; 2088 bus->parent = dev; 2089 bus->phy_mask = ~ds->phys_mii_mask; 2090 2091 if (priv->irq) 2092 mt7530_setup_mdio_irq(priv); 2093 2094 ret = devm_mdiobus_register(dev, bus); 2095 if (ret) { 2096 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2097 if (priv->irq) 2098 mt7530_free_mdio_irq(priv); 2099 } 2100 2101 return ret; 2102 } 2103 2104 static int 2105 mt7530_setup(struct dsa_switch *ds) 2106 { 2107 struct mt7530_priv *priv = ds->priv; 2108 struct device_node *dn = NULL; 2109 struct device_node *phy_node; 2110 struct device_node *mac_np; 2111 struct mt7530_dummy_poll p; 2112 phy_interface_t interface; 2113 struct dsa_port *cpu_dp; 2114 u32 id, val; 2115 int ret, i; 2116 2117 /* The parent node of master netdev which holds the common system 2118 * controller also is the container for two GMACs nodes representing 2119 * as two netdev instances. 2120 */ 2121 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2122 dn = cpu_dp->master->dev.of_node->parent; 2123 /* It doesn't matter which CPU port is found first, 2124 * their masters should share the same parent OF node 2125 */ 2126 break; 2127 } 2128 2129 if (!dn) { 2130 dev_err(ds->dev, "parent OF node of DSA master not found"); 2131 return -EINVAL; 2132 } 2133 2134 ds->assisted_learning_on_cpu_port = true; 2135 ds->mtu_enforcement_ingress = true; 2136 2137 if (priv->id == ID_MT7530) { 2138 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2139 ret = regulator_enable(priv->core_pwr); 2140 if (ret < 0) { 2141 dev_err(priv->dev, 2142 "Failed to enable core power: %d\n", ret); 2143 return ret; 2144 } 2145 2146 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2147 ret = regulator_enable(priv->io_pwr); 2148 if (ret < 0) { 2149 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2150 ret); 2151 return ret; 2152 } 2153 } 2154 2155 /* Reset whole chip through gpio pin or memory-mapped registers for 2156 * different type of hardware 2157 */ 2158 if (priv->mcm) { 2159 reset_control_assert(priv->rstc); 2160 usleep_range(1000, 1100); 2161 reset_control_deassert(priv->rstc); 2162 } else { 2163 gpiod_set_value_cansleep(priv->reset, 0); 2164 usleep_range(1000, 1100); 2165 gpiod_set_value_cansleep(priv->reset, 1); 2166 } 2167 2168 /* Waiting for MT7530 got to stable */ 2169 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2170 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2171 20, 1000000); 2172 if (ret < 0) { 2173 dev_err(priv->dev, "reset timeout\n"); 2174 return ret; 2175 } 2176 2177 id = mt7530_read(priv, MT7530_CREV); 2178 id >>= CHIP_NAME_SHIFT; 2179 if (id != MT7530_ID) { 2180 dev_err(priv->dev, "chip %x can't be supported\n", id); 2181 return -ENODEV; 2182 } 2183 2184 /* Reset the switch through internal reset */ 2185 mt7530_write(priv, MT7530_SYS_CTRL, 2186 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2187 SYS_CTRL_REG_RST); 2188 2189 mt7530_pll_setup(priv); 2190 2191 /* Lower Tx driving for TRGMII path */ 2192 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2193 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2194 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2195 2196 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2197 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2198 RD_TAP_MASK, RD_TAP(16)); 2199 2200 /* Enable port 6 */ 2201 val = mt7530_read(priv, MT7530_MHWTRAP); 2202 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2203 val |= MHWTRAP_MANUAL; 2204 mt7530_write(priv, MT7530_MHWTRAP, val); 2205 2206 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2207 2208 /* Enable and reset MIB counters */ 2209 mt7530_mib_reset(ds); 2210 2211 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2212 /* Disable forwarding by default on all ports */ 2213 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2214 PCR_MATRIX_CLR); 2215 2216 /* Disable learning by default on all ports */ 2217 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2218 2219 if (dsa_is_cpu_port(ds, i)) { 2220 ret = mt753x_cpu_port_enable(ds, i); 2221 if (ret) 2222 return ret; 2223 } else { 2224 mt7530_port_disable(ds, i); 2225 2226 /* Set default PVID to 0 on all user ports */ 2227 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2228 G0_PORT_VID_DEF); 2229 } 2230 /* Enable consistent egress tag */ 2231 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2232 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2233 } 2234 2235 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2236 ret = mt7530_setup_vlan0(priv); 2237 if (ret) 2238 return ret; 2239 2240 /* Setup port 5 */ 2241 priv->p5_intf_sel = P5_DISABLED; 2242 interface = PHY_INTERFACE_MODE_NA; 2243 2244 if (!dsa_is_unused_port(ds, 5)) { 2245 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2246 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2247 if (ret && ret != -ENODEV) 2248 return ret; 2249 } else { 2250 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2251 for_each_child_of_node(dn, mac_np) { 2252 if (!of_device_is_compatible(mac_np, 2253 "mediatek,eth-mac")) 2254 continue; 2255 2256 ret = of_property_read_u32(mac_np, "reg", &id); 2257 if (ret < 0 || id != 1) 2258 continue; 2259 2260 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2261 if (!phy_node) 2262 continue; 2263 2264 if (phy_node->parent == priv->dev->of_node->parent) { 2265 ret = of_get_phy_mode(mac_np, &interface); 2266 if (ret && ret != -ENODEV) { 2267 of_node_put(mac_np); 2268 of_node_put(phy_node); 2269 return ret; 2270 } 2271 id = of_mdio_parse_addr(ds->dev, phy_node); 2272 if (id == 0) 2273 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2274 if (id == 4) 2275 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2276 } 2277 of_node_put(mac_np); 2278 of_node_put(phy_node); 2279 break; 2280 } 2281 } 2282 2283 #ifdef CONFIG_GPIOLIB 2284 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2285 ret = mt7530_setup_gpio(priv); 2286 if (ret) 2287 return ret; 2288 } 2289 #endif /* CONFIG_GPIOLIB */ 2290 2291 mt7530_setup_port5(ds, interface); 2292 2293 /* Flush the FDB table */ 2294 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2295 if (ret < 0) 2296 return ret; 2297 2298 return 0; 2299 } 2300 2301 static int 2302 mt7531_setup_common(struct dsa_switch *ds) 2303 { 2304 struct mt7530_priv *priv = ds->priv; 2305 struct dsa_port *cpu_dp; 2306 int ret, i; 2307 2308 /* BPDU to CPU port */ 2309 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2310 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2311 BIT(cpu_dp->index)); 2312 break; 2313 } 2314 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2315 MT753X_BPDU_CPU_ONLY); 2316 2317 /* Enable and reset MIB counters */ 2318 mt7530_mib_reset(ds); 2319 2320 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2321 /* Disable forwarding by default on all ports */ 2322 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2323 PCR_MATRIX_CLR); 2324 2325 /* Disable learning by default on all ports */ 2326 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2327 2328 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2329 2330 if (dsa_is_cpu_port(ds, i)) { 2331 ret = mt753x_cpu_port_enable(ds, i); 2332 if (ret) 2333 return ret; 2334 } else { 2335 mt7530_port_disable(ds, i); 2336 2337 /* Set default PVID to 0 on all user ports */ 2338 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2339 G0_PORT_VID_DEF); 2340 } 2341 2342 /* Enable consistent egress tag */ 2343 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2344 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2345 } 2346 2347 /* Flush the FDB table */ 2348 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2349 if (ret < 0) 2350 return ret; 2351 2352 return 0; 2353 } 2354 2355 static int 2356 mt7531_setup(struct dsa_switch *ds) 2357 { 2358 struct mt7530_priv *priv = ds->priv; 2359 struct mt7530_dummy_poll p; 2360 u32 val, id; 2361 int ret, i; 2362 2363 /* Reset whole chip through gpio pin or memory-mapped registers for 2364 * different type of hardware 2365 */ 2366 if (priv->mcm) { 2367 reset_control_assert(priv->rstc); 2368 usleep_range(1000, 1100); 2369 reset_control_deassert(priv->rstc); 2370 } else { 2371 gpiod_set_value_cansleep(priv->reset, 0); 2372 usleep_range(1000, 1100); 2373 gpiod_set_value_cansleep(priv->reset, 1); 2374 } 2375 2376 /* Waiting for MT7530 got to stable */ 2377 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2378 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2379 20, 1000000); 2380 if (ret < 0) { 2381 dev_err(priv->dev, "reset timeout\n"); 2382 return ret; 2383 } 2384 2385 id = mt7530_read(priv, MT7531_CREV); 2386 id >>= CHIP_NAME_SHIFT; 2387 2388 if (id != MT7531_ID) { 2389 dev_err(priv->dev, "chip %x can't be supported\n", id); 2390 return -ENODEV; 2391 } 2392 2393 /* all MACs must be forced link-down before sw reset */ 2394 for (i = 0; i < MT7530_NUM_PORTS; i++) 2395 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2396 2397 /* Reset the switch through internal reset */ 2398 mt7530_write(priv, MT7530_SYS_CTRL, 2399 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2400 SYS_CTRL_REG_RST); 2401 2402 mt7531_pll_setup(priv); 2403 2404 if (mt7531_dual_sgmii_supported(priv)) { 2405 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2406 2407 /* Let ds->slave_mii_bus be able to access external phy. */ 2408 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2409 MT7531_EXT_P_MDC_11); 2410 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2411 MT7531_EXT_P_MDIO_12); 2412 } else { 2413 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2414 } 2415 dev_dbg(ds->dev, "P5 support %s interface\n", 2416 p5_intf_modes(priv->p5_intf_sel)); 2417 2418 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2419 MT7531_GPIO0_INTERRUPT); 2420 2421 /* Let phylink decide the interface later. */ 2422 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2423 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2424 2425 /* Enable PHY core PLL, since phy_device has not yet been created 2426 * provided for phy_[read,write]_mmd_indirect is called, we provide 2427 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2428 * function. 2429 */ 2430 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2431 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2432 val |= MT7531_PHY_PLL_BYPASS_MODE; 2433 val &= ~MT7531_PHY_PLL_OFF; 2434 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2435 CORE_PLL_GROUP4, val); 2436 2437 mt7531_setup_common(ds); 2438 2439 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2440 ret = mt7530_setup_vlan0(priv); 2441 if (ret) 2442 return ret; 2443 2444 ds->assisted_learning_on_cpu_port = true; 2445 ds->mtu_enforcement_ingress = true; 2446 2447 return 0; 2448 } 2449 2450 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2451 struct phylink_config *config) 2452 { 2453 switch (port) { 2454 case 0 ... 4: /* Internal phy */ 2455 __set_bit(PHY_INTERFACE_MODE_GMII, 2456 config->supported_interfaces); 2457 break; 2458 2459 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2460 phy_interface_set_rgmii(config->supported_interfaces); 2461 __set_bit(PHY_INTERFACE_MODE_MII, 2462 config->supported_interfaces); 2463 __set_bit(PHY_INTERFACE_MODE_GMII, 2464 config->supported_interfaces); 2465 break; 2466 2467 case 6: /* 1st cpu port */ 2468 __set_bit(PHY_INTERFACE_MODE_RGMII, 2469 config->supported_interfaces); 2470 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2471 config->supported_interfaces); 2472 break; 2473 } 2474 } 2475 2476 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2477 { 2478 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2479 } 2480 2481 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2482 struct phylink_config *config) 2483 { 2484 struct mt7530_priv *priv = ds->priv; 2485 2486 switch (port) { 2487 case 0 ... 4: /* Internal phy */ 2488 __set_bit(PHY_INTERFACE_MODE_GMII, 2489 config->supported_interfaces); 2490 break; 2491 2492 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2493 if (mt7531_is_rgmii_port(priv, port)) { 2494 phy_interface_set_rgmii(config->supported_interfaces); 2495 break; 2496 } 2497 fallthrough; 2498 2499 case 6: /* 1st cpu port supports sgmii/8023z only */ 2500 __set_bit(PHY_INTERFACE_MODE_SGMII, 2501 config->supported_interfaces); 2502 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2503 config->supported_interfaces); 2504 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2505 config->supported_interfaces); 2506 2507 config->mac_capabilities |= MAC_2500FD; 2508 break; 2509 } 2510 } 2511 2512 static int 2513 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2514 { 2515 struct mt7530_priv *priv = ds->priv; 2516 2517 return priv->info->pad_setup(ds, state->interface); 2518 } 2519 2520 static int 2521 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2522 phy_interface_t interface) 2523 { 2524 struct mt7530_priv *priv = ds->priv; 2525 2526 /* Only need to setup port5. */ 2527 if (port != 5) 2528 return 0; 2529 2530 mt7530_setup_port5(priv->ds, interface); 2531 2532 return 0; 2533 } 2534 2535 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2536 phy_interface_t interface, 2537 struct phy_device *phydev) 2538 { 2539 u32 val; 2540 2541 if (!mt7531_is_rgmii_port(priv, port)) { 2542 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2543 port); 2544 return -EINVAL; 2545 } 2546 2547 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2548 val |= GP_CLK_EN; 2549 val &= ~GP_MODE_MASK; 2550 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2551 val &= ~CLK_SKEW_IN_MASK; 2552 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2553 val &= ~CLK_SKEW_OUT_MASK; 2554 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2555 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2556 2557 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2558 if (!phydev || phy_driver_is_genphy(phydev)) { 2559 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2560 switch (interface) { 2561 case PHY_INTERFACE_MODE_RGMII: 2562 val |= TXCLK_NO_REVERSE; 2563 val |= RXCLK_NO_DELAY; 2564 break; 2565 case PHY_INTERFACE_MODE_RGMII_RXID: 2566 val |= TXCLK_NO_REVERSE; 2567 break; 2568 case PHY_INTERFACE_MODE_RGMII_TXID: 2569 val |= RXCLK_NO_DELAY; 2570 break; 2571 case PHY_INTERFACE_MODE_RGMII_ID: 2572 break; 2573 default: 2574 return -EINVAL; 2575 } 2576 } 2577 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2578 2579 return 0; 2580 } 2581 2582 static bool mt753x_is_mac_port(u32 port) 2583 { 2584 return (port == 5 || port == 6); 2585 } 2586 2587 static int 2588 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2589 phy_interface_t interface) 2590 { 2591 struct mt7530_priv *priv = ds->priv; 2592 struct phy_device *phydev; 2593 struct dsa_port *dp; 2594 2595 if (!mt753x_is_mac_port(port)) { 2596 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2597 return -EINVAL; 2598 } 2599 2600 switch (interface) { 2601 case PHY_INTERFACE_MODE_RGMII: 2602 case PHY_INTERFACE_MODE_RGMII_ID: 2603 case PHY_INTERFACE_MODE_RGMII_RXID: 2604 case PHY_INTERFACE_MODE_RGMII_TXID: 2605 dp = dsa_to_port(ds, port); 2606 phydev = dp->slave->phydev; 2607 return mt7531_rgmii_setup(priv, port, interface, phydev); 2608 case PHY_INTERFACE_MODE_SGMII: 2609 case PHY_INTERFACE_MODE_NA: 2610 case PHY_INTERFACE_MODE_1000BASEX: 2611 case PHY_INTERFACE_MODE_2500BASEX: 2612 /* handled in SGMII PCS driver */ 2613 return 0; 2614 default: 2615 return -EINVAL; 2616 } 2617 2618 return -EINVAL; 2619 } 2620 2621 static int 2622 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2623 const struct phylink_link_state *state) 2624 { 2625 struct mt7530_priv *priv = ds->priv; 2626 2627 return priv->info->mac_port_config(ds, port, mode, state->interface); 2628 } 2629 2630 static struct phylink_pcs * 2631 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2632 phy_interface_t interface) 2633 { 2634 struct mt7530_priv *priv = ds->priv; 2635 2636 switch (interface) { 2637 case PHY_INTERFACE_MODE_TRGMII: 2638 return &priv->pcs[port].pcs; 2639 case PHY_INTERFACE_MODE_SGMII: 2640 case PHY_INTERFACE_MODE_1000BASEX: 2641 case PHY_INTERFACE_MODE_2500BASEX: 2642 return priv->ports[port].sgmii_pcs; 2643 default: 2644 return NULL; 2645 } 2646 } 2647 2648 static void 2649 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2650 const struct phylink_link_state *state) 2651 { 2652 struct mt7530_priv *priv = ds->priv; 2653 u32 mcr_cur, mcr_new; 2654 2655 switch (port) { 2656 case 0 ... 4: /* Internal phy */ 2657 if (state->interface != PHY_INTERFACE_MODE_GMII) 2658 goto unsupported; 2659 break; 2660 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2661 if (priv->p5_interface == state->interface) 2662 break; 2663 2664 if (mt753x_mac_config(ds, port, mode, state) < 0) 2665 goto unsupported; 2666 2667 if (priv->p5_intf_sel != P5_DISABLED) 2668 priv->p5_interface = state->interface; 2669 break; 2670 case 6: /* 1st cpu port */ 2671 if (priv->p6_interface == state->interface) 2672 break; 2673 2674 mt753x_pad_setup(ds, state); 2675 2676 if (mt753x_mac_config(ds, port, mode, state) < 0) 2677 goto unsupported; 2678 2679 priv->p6_interface = state->interface; 2680 break; 2681 default: 2682 unsupported: 2683 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2684 __func__, phy_modes(state->interface), port); 2685 return; 2686 } 2687 2688 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2689 mcr_new = mcr_cur; 2690 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2691 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2692 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2693 2694 /* Are we connected to external phy */ 2695 if (port == 5 && dsa_is_user_port(ds, 5)) 2696 mcr_new |= PMCR_EXT_PHY; 2697 2698 if (mcr_new != mcr_cur) 2699 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2700 } 2701 2702 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2703 unsigned int mode, 2704 phy_interface_t interface) 2705 { 2706 struct mt7530_priv *priv = ds->priv; 2707 2708 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2709 } 2710 2711 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2712 unsigned int mode, 2713 phy_interface_t interface, 2714 int speed, int duplex) 2715 { 2716 if (pcs->ops->pcs_link_up) 2717 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2718 } 2719 2720 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2721 unsigned int mode, 2722 phy_interface_t interface, 2723 struct phy_device *phydev, 2724 int speed, int duplex, 2725 bool tx_pause, bool rx_pause) 2726 { 2727 struct mt7530_priv *priv = ds->priv; 2728 u32 mcr; 2729 2730 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2731 2732 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2733 * variants. 2734 */ 2735 if (interface == PHY_INTERFACE_MODE_TRGMII || 2736 (phy_interface_mode_is_8023z(interface))) { 2737 speed = SPEED_1000; 2738 duplex = DUPLEX_FULL; 2739 } 2740 2741 switch (speed) { 2742 case SPEED_1000: 2743 mcr |= PMCR_FORCE_SPEED_1000; 2744 break; 2745 case SPEED_100: 2746 mcr |= PMCR_FORCE_SPEED_100; 2747 break; 2748 } 2749 if (duplex == DUPLEX_FULL) { 2750 mcr |= PMCR_FORCE_FDX; 2751 if (tx_pause) 2752 mcr |= PMCR_TX_FC_EN; 2753 if (rx_pause) 2754 mcr |= PMCR_RX_FC_EN; 2755 } 2756 2757 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2758 switch (speed) { 2759 case SPEED_1000: 2760 mcr |= PMCR_FORCE_EEE1G; 2761 break; 2762 case SPEED_100: 2763 mcr |= PMCR_FORCE_EEE100; 2764 break; 2765 } 2766 } 2767 2768 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2769 } 2770 2771 static int 2772 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2773 { 2774 struct mt7530_priv *priv = ds->priv; 2775 phy_interface_t interface; 2776 int speed; 2777 int ret; 2778 2779 switch (port) { 2780 case 5: 2781 if (mt7531_is_rgmii_port(priv, port)) 2782 interface = PHY_INTERFACE_MODE_RGMII; 2783 else 2784 interface = PHY_INTERFACE_MODE_2500BASEX; 2785 2786 priv->p5_interface = interface; 2787 break; 2788 case 6: 2789 interface = PHY_INTERFACE_MODE_2500BASEX; 2790 2791 priv->p6_interface = interface; 2792 break; 2793 default: 2794 return -EINVAL; 2795 } 2796 2797 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2798 speed = SPEED_2500; 2799 else 2800 speed = SPEED_1000; 2801 2802 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2803 if (ret) 2804 return ret; 2805 mt7530_write(priv, MT7530_PMCR_P(port), 2806 PMCR_CPU_PORT_SETTING(priv->id)); 2807 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2808 interface, speed, DUPLEX_FULL); 2809 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2810 speed, DUPLEX_FULL, true, true); 2811 2812 return 0; 2813 } 2814 2815 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2816 struct phylink_config *config) 2817 { 2818 struct mt7530_priv *priv = ds->priv; 2819 2820 /* This switch only supports full-duplex at 1Gbps */ 2821 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2822 MAC_10 | MAC_100 | MAC_1000FD; 2823 2824 /* This driver does not make use of the speed, duplex, pause or the 2825 * advertisement in its mac_config, so it is safe to mark this driver 2826 * as non-legacy. 2827 */ 2828 config->legacy_pre_march2020 = false; 2829 2830 priv->info->mac_port_get_caps(ds, port, config); 2831 } 2832 2833 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2834 unsigned long *supported, 2835 const struct phylink_link_state *state) 2836 { 2837 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2838 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2839 phy_interface_mode_is_8023z(state->interface)) 2840 phylink_clear(supported, Autoneg); 2841 2842 return 0; 2843 } 2844 2845 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2846 struct phylink_link_state *state) 2847 { 2848 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2849 int port = pcs_to_mt753x_pcs(pcs)->port; 2850 u32 pmsr; 2851 2852 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2853 2854 state->link = (pmsr & PMSR_LINK); 2855 state->an_complete = state->link; 2856 state->duplex = !!(pmsr & PMSR_DPX); 2857 2858 switch (pmsr & PMSR_SPEED_MASK) { 2859 case PMSR_SPEED_10: 2860 state->speed = SPEED_10; 2861 break; 2862 case PMSR_SPEED_100: 2863 state->speed = SPEED_100; 2864 break; 2865 case PMSR_SPEED_1000: 2866 state->speed = SPEED_1000; 2867 break; 2868 default: 2869 state->speed = SPEED_UNKNOWN; 2870 break; 2871 } 2872 2873 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2874 if (pmsr & PMSR_RX_FC) 2875 state->pause |= MLO_PAUSE_RX; 2876 if (pmsr & PMSR_TX_FC) 2877 state->pause |= MLO_PAUSE_TX; 2878 } 2879 2880 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 2881 phy_interface_t interface, 2882 const unsigned long *advertising, 2883 bool permit_pause_to_mac) 2884 { 2885 return 0; 2886 } 2887 2888 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2889 { 2890 } 2891 2892 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2893 .pcs_validate = mt753x_pcs_validate, 2894 .pcs_get_state = mt7530_pcs_get_state, 2895 .pcs_config = mt753x_pcs_config, 2896 .pcs_an_restart = mt7530_pcs_an_restart, 2897 }; 2898 2899 static int 2900 mt753x_setup(struct dsa_switch *ds) 2901 { 2902 struct mt7530_priv *priv = ds->priv; 2903 int i, ret; 2904 2905 /* Initialise the PCS devices */ 2906 for (i = 0; i < priv->ds->num_ports; i++) { 2907 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 2908 priv->pcs[i].priv = priv; 2909 priv->pcs[i].port = i; 2910 } 2911 2912 ret = priv->info->sw_setup(ds); 2913 if (ret) 2914 return ret; 2915 2916 ret = mt7530_setup_irq(priv); 2917 if (ret) 2918 return ret; 2919 2920 ret = mt7530_setup_mdio(priv); 2921 if (ret && priv->irq) 2922 mt7530_free_irq_common(priv); 2923 2924 return ret; 2925 } 2926 2927 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 2928 struct ethtool_eee *e) 2929 { 2930 struct mt7530_priv *priv = ds->priv; 2931 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 2932 2933 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 2934 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 2935 2936 return 0; 2937 } 2938 2939 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 2940 struct ethtool_eee *e) 2941 { 2942 struct mt7530_priv *priv = ds->priv; 2943 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 2944 2945 if (e->tx_lpi_timer > 0xFFF) 2946 return -EINVAL; 2947 2948 set = SET_LPI_THRESH(e->tx_lpi_timer); 2949 if (!e->tx_lpi_enabled) 2950 /* Force LPI Mode without a delay */ 2951 set |= LPI_MODE_EN; 2952 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 2953 2954 return 0; 2955 } 2956 2957 const struct dsa_switch_ops mt7530_switch_ops = { 2958 .get_tag_protocol = mtk_get_tag_protocol, 2959 .setup = mt753x_setup, 2960 .get_strings = mt7530_get_strings, 2961 .get_ethtool_stats = mt7530_get_ethtool_stats, 2962 .get_sset_count = mt7530_get_sset_count, 2963 .set_ageing_time = mt7530_set_ageing_time, 2964 .port_enable = mt7530_port_enable, 2965 .port_disable = mt7530_port_disable, 2966 .port_change_mtu = mt7530_port_change_mtu, 2967 .port_max_mtu = mt7530_port_max_mtu, 2968 .port_stp_state_set = mt7530_stp_state_set, 2969 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 2970 .port_bridge_flags = mt7530_port_bridge_flags, 2971 .port_bridge_join = mt7530_port_bridge_join, 2972 .port_bridge_leave = mt7530_port_bridge_leave, 2973 .port_fdb_add = mt7530_port_fdb_add, 2974 .port_fdb_del = mt7530_port_fdb_del, 2975 .port_fdb_dump = mt7530_port_fdb_dump, 2976 .port_mdb_add = mt7530_port_mdb_add, 2977 .port_mdb_del = mt7530_port_mdb_del, 2978 .port_vlan_filtering = mt7530_port_vlan_filtering, 2979 .port_vlan_add = mt7530_port_vlan_add, 2980 .port_vlan_del = mt7530_port_vlan_del, 2981 .port_mirror_add = mt753x_port_mirror_add, 2982 .port_mirror_del = mt753x_port_mirror_del, 2983 .phylink_get_caps = mt753x_phylink_get_caps, 2984 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 2985 .phylink_mac_config = mt753x_phylink_mac_config, 2986 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2987 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2988 .get_mac_eee = mt753x_get_mac_eee, 2989 .set_mac_eee = mt753x_set_mac_eee, 2990 }; 2991 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 2992 2993 const struct mt753x_info mt753x_table[] = { 2994 [ID_MT7621] = { 2995 .id = ID_MT7621, 2996 .pcs_ops = &mt7530_pcs_ops, 2997 .sw_setup = mt7530_setup, 2998 .phy_read_c22 = mt7530_phy_read_c22, 2999 .phy_write_c22 = mt7530_phy_write_c22, 3000 .phy_read_c45 = mt7530_phy_read_c45, 3001 .phy_write_c45 = mt7530_phy_write_c45, 3002 .pad_setup = mt7530_pad_clk_setup, 3003 .mac_port_get_caps = mt7530_mac_port_get_caps, 3004 .mac_port_config = mt7530_mac_config, 3005 }, 3006 [ID_MT7530] = { 3007 .id = ID_MT7530, 3008 .pcs_ops = &mt7530_pcs_ops, 3009 .sw_setup = mt7530_setup, 3010 .phy_read_c22 = mt7530_phy_read_c22, 3011 .phy_write_c22 = mt7530_phy_write_c22, 3012 .phy_read_c45 = mt7530_phy_read_c45, 3013 .phy_write_c45 = mt7530_phy_write_c45, 3014 .pad_setup = mt7530_pad_clk_setup, 3015 .mac_port_get_caps = mt7530_mac_port_get_caps, 3016 .mac_port_config = mt7530_mac_config, 3017 }, 3018 [ID_MT7531] = { 3019 .id = ID_MT7531, 3020 .pcs_ops = &mt7530_pcs_ops, 3021 .sw_setup = mt7531_setup, 3022 .phy_read_c22 = mt7531_ind_c22_phy_read, 3023 .phy_write_c22 = mt7531_ind_c22_phy_write, 3024 .phy_read_c45 = mt7531_ind_c45_phy_read, 3025 .phy_write_c45 = mt7531_ind_c45_phy_write, 3026 .pad_setup = mt7531_pad_setup, 3027 .cpu_port_config = mt7531_cpu_port_config, 3028 .mac_port_get_caps = mt7531_mac_port_get_caps, 3029 .mac_port_config = mt7531_mac_config, 3030 }, 3031 }; 3032 EXPORT_SYMBOL_GPL(mt753x_table); 3033 3034 int 3035 mt7530_probe_common(struct mt7530_priv *priv) 3036 { 3037 struct device *dev = priv->dev; 3038 3039 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3040 if (!priv->ds) 3041 return -ENOMEM; 3042 3043 priv->ds->dev = dev; 3044 priv->ds->num_ports = MT7530_NUM_PORTS; 3045 3046 /* Get the hardware identifier from the devicetree node. 3047 * We will need it for some of the clock and regulator setup. 3048 */ 3049 priv->info = of_device_get_match_data(dev); 3050 if (!priv->info) 3051 return -EINVAL; 3052 3053 /* Sanity check if these required device operations are filled 3054 * properly. 3055 */ 3056 if (!priv->info->sw_setup || !priv->info->pad_setup || 3057 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3058 !priv->info->mac_port_get_caps || 3059 !priv->info->mac_port_config) 3060 return -EINVAL; 3061 3062 priv->id = priv->info->id; 3063 priv->dev = dev; 3064 priv->ds->priv = priv; 3065 priv->ds->ops = &mt7530_switch_ops; 3066 mutex_init(&priv->reg_mutex); 3067 dev_set_drvdata(dev, priv); 3068 3069 return 0; 3070 } 3071 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3072 3073 void 3074 mt7530_remove_common(struct mt7530_priv *priv) 3075 { 3076 if (priv->irq) 3077 mt7530_free_irq(priv); 3078 3079 dsa_unregister_switch(priv->ds); 3080 3081 mutex_destroy(&priv->reg_mutex); 3082 } 3083 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3084 3085 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3086 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3087 MODULE_LICENSE("GPL"); 3088